1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Allwinner H616 SoC pinctrl driver.
4  *
5  * Copyright (C) 2020 Arm Ltd.
6  * based on the H6 pinctrl driver
7  *   Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
8  */
9 
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <linux/of.h>
13 #include <linux/of_device.h>
14 #include <linux/pinctrl/pinctrl.h>
15 
16 #include "pinctrl-sunxi.h"
17 
18 static const struct sunxi_desc_pin h616_pins[] = {
19 	/* Internal connection to the AC200 part */
20 	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
21 		  SUNXI_FUNCTION(0x2, "emac1")),	/* ERXD1 */
22 	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
23 		  SUNXI_FUNCTION(0x2, "emac1")),	/* ERXD0 */
24 	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
25 		  SUNXI_FUNCTION(0x2, "emac1")),	/* ECRS_DV */
26 	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
27 		  SUNXI_FUNCTION(0x2, "emac1")),	/* ERXERR */
28 	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
29 		  SUNXI_FUNCTION(0x2, "emac1")),	/* ETXD1 */
30 	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
31 		  SUNXI_FUNCTION(0x2, "emac1")),	/* ETXD0 */
32 	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
33 		  SUNXI_FUNCTION(0x2, "emac1")),	/* ETXCK */
34 	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
35 		  SUNXI_FUNCTION(0x2, "emac1")),	/* ETXEN */
36 	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
37 		  SUNXI_FUNCTION(0x2, "emac1")),	/* EMDC */
38 	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
39 		  SUNXI_FUNCTION(0x2, "emac1")),	/* EMDIO */
40 	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
41 		  SUNXI_FUNCTION(0x2, "i2c3")),		/* SCK */
42 	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
43 		  SUNXI_FUNCTION(0x2, "i2c3")),		/* SDA */
44 	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
45 		  SUNXI_FUNCTION(0x2, "pwm5")),
46 	/* Hole */
47 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
48 		  SUNXI_FUNCTION(0x0, "gpio_in"),
49 		  SUNXI_FUNCTION(0x1, "gpio_out"),
50 		  SUNXI_FUNCTION(0x2, "nand0"),		/* WE */
51 		  SUNXI_FUNCTION(0x3, "mmc2"),		/* DS */
52 		  SUNXI_FUNCTION(0x4, "spi0"),		/* CLK */
53 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)),	/* PC_EINT0 */
54 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
55 		  SUNXI_FUNCTION(0x0, "gpio_in"),
56 		  SUNXI_FUNCTION(0x1, "gpio_out"),
57 		  SUNXI_FUNCTION(0x2, "nand0"),		/* ALE */
58 		  SUNXI_FUNCTION(0x3, "mmc2"),		/* RST */
59 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)),	/* PC_EINT1 */
60 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
61 		  SUNXI_FUNCTION(0x0, "gpio_in"),
62 		  SUNXI_FUNCTION(0x1, "gpio_out"),
63 		  SUNXI_FUNCTION(0x2, "nand0"),		/* CLE */
64 		  SUNXI_FUNCTION(0x4, "spi0"),		/* MOSI */
65 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)),	/* PC_EINT2 */
66 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
67 		  SUNXI_FUNCTION(0x0, "gpio_in"),
68 		  SUNXI_FUNCTION(0x1, "gpio_out"),
69 		  SUNXI_FUNCTION(0x2, "nand0"),		/* CE1 */
70 		  SUNXI_FUNCTION(0x4, "spi0"),		/* CS0 */
71 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)),	/* PC_EINT3 */
72 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
73 		  SUNXI_FUNCTION(0x0, "gpio_in"),
74 		  SUNXI_FUNCTION(0x1, "gpio_out"),
75 		  SUNXI_FUNCTION(0x2, "nand0"),		/* CE0 */
76 		  SUNXI_FUNCTION(0x4, "spi0"),		/* MISO */
77 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)),	/* PC_EINT4 */
78 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
79 		  SUNXI_FUNCTION(0x0, "gpio_in"),
80 		  SUNXI_FUNCTION(0x1, "gpio_out"),
81 		  SUNXI_FUNCTION(0x2, "nand0"),		/* RE */
82 		  SUNXI_FUNCTION(0x3, "mmc2"),		/* CLK */
83 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)),	/* PC_EINT5 */
84 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
85 		  SUNXI_FUNCTION(0x0, "gpio_in"),
86 		  SUNXI_FUNCTION(0x1, "gpio_out"),
87 		  SUNXI_FUNCTION(0x2, "nand0"),		/* RB0 */
88 		  SUNXI_FUNCTION(0x3, "mmc2"),		/* CMD */
89 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)),	/* PC_EINT6 */
90 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
91 		  SUNXI_FUNCTION(0x0, "gpio_in"),
92 		  SUNXI_FUNCTION(0x1, "gpio_out"),
93 		  SUNXI_FUNCTION(0x2, "nand0"),		/* RB1 */
94 		  SUNXI_FUNCTION(0x4, "spi0"),		/* CS1 */
95 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)),	/* PC_EINT7 */
96 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
97 		  SUNXI_FUNCTION(0x0, "gpio_in"),
98 		  SUNXI_FUNCTION(0x1, "gpio_out"),
99 		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ7 */
100 		  SUNXI_FUNCTION(0x3, "mmc2"),		/* D3 */
101 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)),	/* PC_EINT8 */
102 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
103 		  SUNXI_FUNCTION(0x0, "gpio_in"),
104 		  SUNXI_FUNCTION(0x1, "gpio_out"),
105 		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ6 */
106 		  SUNXI_FUNCTION(0x3, "mmc2"),		/* D4 */
107 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)),	/* PC_EINT9 */
108 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
109 		  SUNXI_FUNCTION(0x0, "gpio_in"),
110 		  SUNXI_FUNCTION(0x1, "gpio_out"),
111 		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ5 */
112 		  SUNXI_FUNCTION(0x3, "mmc2"),		/* D0 */
113 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)),	/* PC_EINT10 */
114 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
115 		  SUNXI_FUNCTION(0x0, "gpio_in"),
116 		  SUNXI_FUNCTION(0x1, "gpio_out"),
117 		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ4 */
118 		  SUNXI_FUNCTION(0x3, "mmc2"),		/* D5 */
119 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)),	/* PC_EINT11 */
120 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
121 		  SUNXI_FUNCTION(0x0, "gpio_in"),
122 		  SUNXI_FUNCTION(0x1, "gpio_out"),
123 		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQS */
124 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)),	/* PC_EINT12 */
125 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
126 		  SUNXI_FUNCTION(0x0, "gpio_in"),
127 		  SUNXI_FUNCTION(0x1, "gpio_out"),
128 		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ3 */
129 		  SUNXI_FUNCTION(0x3, "mmc2"),		/* D1 */
130 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)),	/* PC_EINT13 */
131 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
132 		  SUNXI_FUNCTION(0x0, "gpio_in"),
133 		  SUNXI_FUNCTION(0x1, "gpio_out"),
134 		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ2 */
135 		  SUNXI_FUNCTION(0x3, "mmc2"),		/* D6 */
136 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 14)),	/* PC_EINT14 */
137 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
138 		  SUNXI_FUNCTION(0x0, "gpio_in"),
139 		  SUNXI_FUNCTION(0x1, "gpio_out"),
140 		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ1 */
141 		  SUNXI_FUNCTION(0x3, "mmc2"),		/* D2 */
142 		  SUNXI_FUNCTION(0x4, "spi0"),		/* WP */
143 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 15)),	/* PC_EINT15 */
144 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
145 		  SUNXI_FUNCTION(0x0, "gpio_in"),
146 		  SUNXI_FUNCTION(0x1, "gpio_out"),
147 		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ0 */
148 		  SUNXI_FUNCTION(0x3, "mmc2"),		/* D7 */
149 		  SUNXI_FUNCTION(0x4, "spi0"),		/* HOLD */
150 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 16)),	/* PC_EINT16 */
151 	/* Hole */
152 	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
153 		  SUNXI_FUNCTION(0x0, "gpio_in"),
154 		  SUNXI_FUNCTION(0x1, "gpio_out"),
155 		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D1 */
156 		  SUNXI_FUNCTION(0x3, "jtag"),		/* MS */
157 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 0)),	/* PF_EINT0 */
158 	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
159 		  SUNXI_FUNCTION(0x0, "gpio_in"),
160 		  SUNXI_FUNCTION(0x1, "gpio_out"),
161 		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D0 */
162 		  SUNXI_FUNCTION(0x3, "jtag"),		/* DI */
163 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 1)),	/* PF_EINT1 */
164 	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
165 		  SUNXI_FUNCTION(0x0, "gpio_in"),
166 		  SUNXI_FUNCTION(0x1, "gpio_out"),
167 		  SUNXI_FUNCTION(0x2, "mmc0"),		/* CLK */
168 		  SUNXI_FUNCTION(0x3, "uart0"),		/* TX */
169 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 2)),	/* PF_EINT2 */
170 	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
171 		  SUNXI_FUNCTION(0x0, "gpio_in"),
172 		  SUNXI_FUNCTION(0x1, "gpio_out"),
173 		  SUNXI_FUNCTION(0x2, "mmc0"),		/* CMD */
174 		  SUNXI_FUNCTION(0x3, "jtag"),		/* DO */
175 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 3)),	/* PF_EINT3 */
176 	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
177 		  SUNXI_FUNCTION(0x0, "gpio_in"),
178 		  SUNXI_FUNCTION(0x1, "gpio_out"),
179 		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D3 */
180 		  SUNXI_FUNCTION(0x3, "uart0"),		/* RX */
181 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 4)),	/* PF_EINT4 */
182 	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
183 		  SUNXI_FUNCTION(0x0, "gpio_in"),
184 		  SUNXI_FUNCTION(0x1, "gpio_out"),
185 		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D2 */
186 		  SUNXI_FUNCTION(0x3, "jtag"),		/* CK */
187 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 5)),	/* PF_EINT5 */
188 	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
189 		  SUNXI_FUNCTION(0x0, "gpio_in"),
190 		  SUNXI_FUNCTION(0x1, "gpio_out"),
191 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 6)),	/* PF_EINT6 */
192 	/* Hole */
193 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
194 		  SUNXI_FUNCTION(0x0, "gpio_in"),
195 		  SUNXI_FUNCTION(0x1, "gpio_out"),
196 		  SUNXI_FUNCTION(0x2, "mmc1"),		/* CLK */
197 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 0)),	/* PG_EINT0 */
198 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
199 		  SUNXI_FUNCTION(0x0, "gpio_in"),
200 		  SUNXI_FUNCTION(0x1, "gpio_out"),
201 		  SUNXI_FUNCTION(0x2, "mmc1"),		/* CMD */
202 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 1)),	/* PG_EINT1 */
203 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
204 		  SUNXI_FUNCTION(0x0, "gpio_in"),
205 		  SUNXI_FUNCTION(0x1, "gpio_out"),
206 		  SUNXI_FUNCTION(0x2, "mmc1"),		/* D0 */
207 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 2)),	/* PG_EINT2 */
208 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
209 		  SUNXI_FUNCTION(0x0, "gpio_in"),
210 		  SUNXI_FUNCTION(0x1, "gpio_out"),
211 		  SUNXI_FUNCTION(0x2, "mmc1"),		/* D1 */
212 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 3)),	/* PG_EINT3 */
213 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
214 		  SUNXI_FUNCTION(0x0, "gpio_in"),
215 		  SUNXI_FUNCTION(0x1, "gpio_out"),
216 		  SUNXI_FUNCTION(0x2, "mmc1"),		/* D2 */
217 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 4)),	/* PG_EINT4 */
218 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
219 		  SUNXI_FUNCTION(0x0, "gpio_in"),
220 		  SUNXI_FUNCTION(0x1, "gpio_out"),
221 		  SUNXI_FUNCTION(0x2, "mmc1"),		/* D3 */
222 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 5)),	/* PG_EINT5 */
223 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
224 		  SUNXI_FUNCTION(0x0, "gpio_in"),
225 		  SUNXI_FUNCTION(0x1, "gpio_out"),
226 		  SUNXI_FUNCTION(0x2, "uart1"),		/* TX */
227 		  SUNXI_FUNCTION(0x4, "jtag"),		/* MS */
228 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 6)),	/* PG_EINT6 */
229 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
230 		  SUNXI_FUNCTION(0x0, "gpio_in"),
231 		  SUNXI_FUNCTION(0x1, "gpio_out"),
232 		  SUNXI_FUNCTION(0x2, "uart1"),		/* RX */
233 		  SUNXI_FUNCTION(0x4, "jtag"),		/* CK */
234 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 7)),	/* PG_EINT7 */
235 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
236 		  SUNXI_FUNCTION(0x0, "gpio_in"),
237 		  SUNXI_FUNCTION(0x1, "gpio_out"),
238 		  SUNXI_FUNCTION(0x2, "uart1"),		/* RTS */
239 		  SUNXI_FUNCTION(0x3, "clock"),		/* PLL_LOCK_DEBUG */
240 		  SUNXI_FUNCTION(0x4, "jtag"),		/* DO */
241 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 8)),	/* PG_EINT8 */
242 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
243 		  SUNXI_FUNCTION(0x0, "gpio_in"),
244 		  SUNXI_FUNCTION(0x1, "gpio_out"),
245 		  SUNXI_FUNCTION(0x2, "uart1"),		/* CTS */
246 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 9)),	/* PG_EINT9 */
247 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
248 		  SUNXI_FUNCTION(0x0, "gpio_in"),
249 		  SUNXI_FUNCTION(0x1, "gpio_out"),
250 		  SUNXI_FUNCTION(0x2, "i2s2"),	/* MCLK */
251 		  SUNXI_FUNCTION(0x3, "clock"),		/* X32KFOUT */
252 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 10)),	/* PG_EINT10 */
253 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
254 		  SUNXI_FUNCTION(0x0, "gpio_in"),
255 		  SUNXI_FUNCTION(0x1, "gpio_out"),
256 		  SUNXI_FUNCTION(0x2, "i2s2"),	/* BCLK */
257 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 11)),	/* PG_EINT11 */
258 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
259 		  SUNXI_FUNCTION(0x0, "gpio_in"),
260 		  SUNXI_FUNCTION(0x1, "gpio_out"),
261 		  SUNXI_FUNCTION(0x2, "i2s2"),	/* SYNC */
262 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 12)),	/* PG_EINT12 */
263 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
264 		  SUNXI_FUNCTION(0x0, "gpio_in"),
265 		  SUNXI_FUNCTION(0x1, "gpio_out"),
266 		  SUNXI_FUNCTION(0x2, "i2s2"),	/* DOUT */
267 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 13)),	/* PG_EINT13 */
268 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),
269 		  SUNXI_FUNCTION(0x0, "gpio_in"),
270 		  SUNXI_FUNCTION(0x1, "gpio_out"),
271 		  SUNXI_FUNCTION(0x2, "i2s2"),	/* DIN */
272 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 14)),	/* PG_EINT14 */
273 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15),
274 		  SUNXI_FUNCTION(0x0, "gpio_in"),
275 		  SUNXI_FUNCTION(0x1, "gpio_out"),
276 		  SUNXI_FUNCTION(0x2, "uart2"),		/* TX */
277 		  SUNXI_FUNCTION(0x5, "i2c4"),		/* SCK */
278 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 15)),	/* PG_EINT15 */
279 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 16),
280 		  SUNXI_FUNCTION(0x0, "gpio_in"),
281 		  SUNXI_FUNCTION(0x1, "gpio_out"),
282 		  SUNXI_FUNCTION(0x2, "uart2"),		/* RX */
283 		  SUNXI_FUNCTION(0x5, "i2c4"),		/* SDA */
284 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 16)),	/* PG_EINT16 */
285 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 17),
286 		  SUNXI_FUNCTION(0x0, "gpio_in"),
287 		  SUNXI_FUNCTION(0x1, "gpio_out"),
288 		  SUNXI_FUNCTION(0x2, "uart2"),		/* RTS */
289 		  SUNXI_FUNCTION(0x5, "i2c3"),		/* SCK */
290 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 17)),	/* PG_EINT17 */
291 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 18),
292 		  SUNXI_FUNCTION(0x0, "gpio_in"),
293 		  SUNXI_FUNCTION(0x1, "gpio_out"),
294 		  SUNXI_FUNCTION(0x2, "uart2"),		/* CTS */
295 		  SUNXI_FUNCTION(0x5, "i2c3"),		/* SDA */
296 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 18)),	/* PG_EINT18 */
297 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 19),
298 		  SUNXI_FUNCTION(0x0, "gpio_in"),
299 		  SUNXI_FUNCTION(0x1, "gpio_out"),
300 		  SUNXI_FUNCTION(0x4, "pwm1"),
301 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 19)),	/* PG_EINT19 */
302 	/* Hole */
303 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
304 		  SUNXI_FUNCTION(0x0, "gpio_in"),
305 		  SUNXI_FUNCTION(0x1, "gpio_out"),
306 		  SUNXI_FUNCTION(0x2, "uart0"),		/* TX */
307 		  SUNXI_FUNCTION(0x4, "pwm3"),
308 		  SUNXI_FUNCTION(0x5, "i2c1"),		/* SCK */
309 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 0)),	/* PH_EINT0 */
310 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
311 		  SUNXI_FUNCTION(0x0, "gpio_in"),
312 		  SUNXI_FUNCTION(0x1, "gpio_out"),
313 		  SUNXI_FUNCTION(0x2, "uart0"),		/* RX */
314 		  SUNXI_FUNCTION(0x4, "pwm4"),
315 		  SUNXI_FUNCTION(0x5, "i2c1"),		/* SDA */
316 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 1)),	/* PH_EINT1 */
317 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
318 		  SUNXI_FUNCTION(0x0, "gpio_in"),
319 		  SUNXI_FUNCTION(0x1, "gpio_out"),
320 		  SUNXI_FUNCTION(0x2, "uart5"),		/* TX */
321 		  SUNXI_FUNCTION(0x3, "spdif"),		/* MCLK */
322 		  SUNXI_FUNCTION(0x4, "pwm2"),
323 		  SUNXI_FUNCTION(0x5, "i2c2"),		/* SCK */
324 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 2)),	/* PH_EINT2 */
325 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
326 		  SUNXI_FUNCTION(0x0, "gpio_in"),
327 		  SUNXI_FUNCTION(0x1, "gpio_out"),
328 		  SUNXI_FUNCTION(0x2, "uart5"),		/* RX */
329 		  SUNXI_FUNCTION(0x4, "pwm1"),
330 		  SUNXI_FUNCTION(0x5, "i2c2"),		/* SDA */
331 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 3)),	/* PH_EINT3 */
332 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
333 		  SUNXI_FUNCTION(0x0, "gpio_in"),
334 		  SUNXI_FUNCTION(0x1, "gpio_out"),
335 		  SUNXI_FUNCTION(0x3, "spdif"),		/* OUT */
336 		  SUNXI_FUNCTION(0x5, "i2c3"),		/* SCK */
337 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 4)),	/* PH_EINT4 */
338 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
339 		  SUNXI_FUNCTION(0x0, "gpio_in"),
340 		  SUNXI_FUNCTION(0x1, "gpio_out"),
341 		  SUNXI_FUNCTION(0x2, "uart2"),		/* TX */
342 		  SUNXI_FUNCTION(0x3, "i2s3"),	/* MCLK */
343 		  SUNXI_FUNCTION(0x4, "spi1"),		/* CS0 */
344 		  SUNXI_FUNCTION(0x5, "i2c3"),		/* SDA */
345 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 5)),	/* PH_EINT5 */
346 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
347 		  SUNXI_FUNCTION(0x0, "gpio_in"),
348 		  SUNXI_FUNCTION(0x1, "gpio_out"),
349 		  SUNXI_FUNCTION(0x2, "uart2"),		/* RX */
350 		  SUNXI_FUNCTION(0x3, "i2s3"),	/* BCLK */
351 		  SUNXI_FUNCTION(0x4, "spi1"),		/* CLK */
352 		  SUNXI_FUNCTION(0x5, "i2c4"),		/* SCK */
353 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 6)),	/* PH_EINT6 */
354 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
355 		  SUNXI_FUNCTION(0x0, "gpio_in"),
356 		  SUNXI_FUNCTION(0x1, "gpio_out"),
357 		  SUNXI_FUNCTION(0x2, "uart2"),		/* RTS */
358 		  SUNXI_FUNCTION(0x3, "i2s3"),	/* SYNC */
359 		  SUNXI_FUNCTION(0x4, "spi1"),		/* MOSI */
360 		  SUNXI_FUNCTION(0x5, "i2c4"),		/* SDA */
361 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 7)),	/* PH_EINT7 */
362 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
363 		  SUNXI_FUNCTION(0x0, "gpio_in"),
364 		  SUNXI_FUNCTION(0x1, "gpio_out"),
365 		  SUNXI_FUNCTION(0x2, "uart2"),		/* CTS */
366 		  SUNXI_FUNCTION(0x3, "i2s3_dout0"),	/* DO0 */
367 		  SUNXI_FUNCTION(0x4, "spi1"),		/* MISO */
368 		  SUNXI_FUNCTION(0x5, "i2s3_din1"),	/* DI1 */
369 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 8)),	/* PH_EINT8 */
370 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
371 		  SUNXI_FUNCTION(0x0, "gpio_in"),
372 		  SUNXI_FUNCTION(0x1, "gpio_out"),
373 		  SUNXI_FUNCTION(0x3, "i2s3_din0"),	/* DI0 */
374 		  SUNXI_FUNCTION(0x4, "spi1"),		/* CS1 */
375 		  SUNXI_FUNCTION(0x5, "i2s3_dout1"),	/* DO1 */
376 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 9)),	/* PH_EINT9 */
377 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
378 		  SUNXI_FUNCTION(0x0, "gpio_in"),
379 		  SUNXI_FUNCTION(0x1, "gpio_out"),
380 		  SUNXI_FUNCTION(0x3, "ir_rx"),
381 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 10)),	/* PH_EINT10 */
382 	/* Hole */
383 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 0),
384 		  SUNXI_FUNCTION(0x0, "gpio_in"),
385 		  SUNXI_FUNCTION(0x1, "gpio_out"),
386 		  SUNXI_FUNCTION(0x2, "emac0"),		/* ERXD3 */
387 		  SUNXI_FUNCTION(0x3, "dmic"),		/* CLK */
388 		  SUNXI_FUNCTION(0x4, "i2s0"),	/* MCLK */
389 		  SUNXI_FUNCTION(0x5, "hdmi"),		/* HSCL */
390 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 0)),	/* PI_EINT0 */
391 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 1),
392 		  SUNXI_FUNCTION(0x0, "gpio_in"),
393 		  SUNXI_FUNCTION(0x1, "gpio_out"),
394 		  SUNXI_FUNCTION(0x2, "emac0"),		/* ERXD2 */
395 		  SUNXI_FUNCTION(0x3, "dmic"),		/* DATA0 */
396 		  SUNXI_FUNCTION(0x4, "i2s0"),	/* BCLK */
397 		  SUNXI_FUNCTION(0x5, "hdmi"),		/* HSDA */
398 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 1)),	/* PI_EINT1 */
399 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 2),
400 		  SUNXI_FUNCTION(0x0, "gpio_in"),
401 		  SUNXI_FUNCTION(0x1, "gpio_out"),
402 		  SUNXI_FUNCTION(0x2, "emac0"),		/* ERXD1 */
403 		  SUNXI_FUNCTION(0x3, "dmic"),		/* DATA1 */
404 		  SUNXI_FUNCTION(0x4, "i2s0"),	/* SYNC */
405 		  SUNXI_FUNCTION(0x5, "hdmi"),		/* HCEC */
406 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 2)),	/* PI_EINT2 */
407 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 3),
408 		  SUNXI_FUNCTION(0x0, "gpio_in"),
409 		  SUNXI_FUNCTION(0x1, "gpio_out"),
410 		  SUNXI_FUNCTION(0x2, "emac0"),		/* ERXD0 */
411 		  SUNXI_FUNCTION(0x3, "dmic"),		/* DATA2 */
412 		  SUNXI_FUNCTION(0x4, "i2s0_dout0"),	/* DO0 */
413 		  SUNXI_FUNCTION(0x5, "i2s0_din1"),	/* DI1 */
414 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 3)),	/* PI_EINT3 */
415 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 4),
416 		  SUNXI_FUNCTION(0x0, "gpio_in"),
417 		  SUNXI_FUNCTION(0x1, "gpio_out"),
418 		  SUNXI_FUNCTION(0x2, "emac0"),		/* ERXCK */
419 		  SUNXI_FUNCTION(0x3, "dmic"),		/* DATA3 */
420 		  SUNXI_FUNCTION(0x4, "i2s0_din0"),	/* DI0 */
421 		  SUNXI_FUNCTION(0x5, "i2s0_dout1"),	/* DO1 */
422 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 4)),	/* PI_EINT4 */
423 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 5),
424 		  SUNXI_FUNCTION(0x0, "gpio_in"),
425 		  SUNXI_FUNCTION(0x1, "gpio_out"),
426 		  SUNXI_FUNCTION(0x2, "emac0"),		/* ERXCTL */
427 		  SUNXI_FUNCTION(0x3, "uart2"),		/* TX */
428 		  SUNXI_FUNCTION(0x4, "ts0"),		/* CLK */
429 		  SUNXI_FUNCTION(0x5, "i2c0"),		/* SCK */
430 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 5)),	/* PI_EINT5 */
431 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 6),
432 		  SUNXI_FUNCTION(0x0, "gpio_in"),
433 		  SUNXI_FUNCTION(0x1, "gpio_out"),
434 		  SUNXI_FUNCTION(0x2, "emac0"),		/* ENULL */
435 		  SUNXI_FUNCTION(0x3, "uart2"),		/* RX */
436 		  SUNXI_FUNCTION(0x4, "ts0"),		/* ERR */
437 		  SUNXI_FUNCTION(0x5, "i2c0"),		/* SDA */
438 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 6)),	/* PI_EINT6 */
439 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 7),
440 		  SUNXI_FUNCTION(0x0, "gpio_in"),
441 		  SUNXI_FUNCTION(0x1, "gpio_out"),
442 		  SUNXI_FUNCTION(0x2, "emac0"),		/* ETXD3 */
443 		  SUNXI_FUNCTION(0x3, "uart2"),		/* RTS */
444 		  SUNXI_FUNCTION(0x4, "ts0"),		/* SYNC */
445 		  SUNXI_FUNCTION(0x5, "i2c1"),		/* SCK */
446 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 7)),	/* PI_EINT7 */
447 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 8),
448 		  SUNXI_FUNCTION(0x0, "gpio_in"),
449 		  SUNXI_FUNCTION(0x1, "gpio_out"),
450 		  SUNXI_FUNCTION(0x2, "emac0"),		/* ETXD2 */
451 		  SUNXI_FUNCTION(0x3, "uart2"),		/* CTS */
452 		  SUNXI_FUNCTION(0x4, "ts0"),		/* DVLD */
453 		  SUNXI_FUNCTION(0x5, "i2c1"),		/* SDA */
454 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 8)),	/* PI_EINT8 */
455 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 9),
456 		  SUNXI_FUNCTION(0x0, "gpio_in"),
457 		  SUNXI_FUNCTION(0x1, "gpio_out"),
458 		  SUNXI_FUNCTION(0x2, "emac0"),		/* ETXD1 */
459 		  SUNXI_FUNCTION(0x3, "uart3"),		/* TX */
460 		  SUNXI_FUNCTION(0x4, "ts0"),		/* D0 */
461 		  SUNXI_FUNCTION(0x5, "i2c2"),		/* SCK */
462 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 9)),	/* PI_EINT9 */
463 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 10),
464 		  SUNXI_FUNCTION(0x0, "gpio_in"),
465 		  SUNXI_FUNCTION(0x1, "gpio_out"),
466 		  SUNXI_FUNCTION(0x2, "emac0"),		/* ETXD0 */
467 		  SUNXI_FUNCTION(0x3, "uart3"),		/* RX */
468 		  SUNXI_FUNCTION(0x4, "ts0"),		/* D1 */
469 		  SUNXI_FUNCTION(0x5, "i2c2"),		/* SDA */
470 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 10)),	/* PI_EINT10 */
471 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 11),
472 		  SUNXI_FUNCTION(0x0, "gpio_in"),
473 		  SUNXI_FUNCTION(0x1, "gpio_out"),
474 		  SUNXI_FUNCTION(0x2, "emac0"),		/* ETXCK */
475 		  SUNXI_FUNCTION(0x3, "uart3"),		/* RTS */
476 		  SUNXI_FUNCTION(0x4, "ts0"),		/* D2 */
477 		  SUNXI_FUNCTION(0x5, "pwm1"),
478 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 11)),	/* PI_EINT11 */
479 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 12),
480 		  SUNXI_FUNCTION(0x0, "gpio_in"),
481 		  SUNXI_FUNCTION(0x1, "gpio_out"),
482 		  SUNXI_FUNCTION(0x2, "emac0"),		/* ETXCTL */
483 		  SUNXI_FUNCTION(0x3, "uart3"),		/* CTS */
484 		  SUNXI_FUNCTION(0x4, "ts0"),		/* D3 */
485 		  SUNXI_FUNCTION(0x5, "pwm2"),
486 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 12)),	/* PI_EINT12 */
487 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13),
488 		  SUNXI_FUNCTION(0x0, "gpio_in"),
489 		  SUNXI_FUNCTION(0x1, "gpio_out"),
490 		  SUNXI_FUNCTION(0x2, "emac0"),		/* ECLKIN */
491 		  SUNXI_FUNCTION(0x3, "uart4"),		/* TX */
492 		  SUNXI_FUNCTION(0x4, "ts0"),		/* D4 */
493 		  SUNXI_FUNCTION(0x5, "pwm3"),
494 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 13)),	/* PI_EINT13 */
495 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14),
496 		  SUNXI_FUNCTION(0x0, "gpio_in"),
497 		  SUNXI_FUNCTION(0x1, "gpio_out"),
498 		  SUNXI_FUNCTION(0x2, "emac0"),		/* MDC */
499 		  SUNXI_FUNCTION(0x3, "uart4"),		/* RX */
500 		  SUNXI_FUNCTION(0x4, "ts0"),		/* D5 */
501 		  SUNXI_FUNCTION(0x5, "pwm4"),
502 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 14)),	/* PI_EINT14 */
503 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 15),
504 		  SUNXI_FUNCTION(0x0, "gpio_in"),
505 		  SUNXI_FUNCTION(0x1, "gpio_out"),
506 		  SUNXI_FUNCTION(0x2, "emac0"),		/* MDIO */
507 		  SUNXI_FUNCTION(0x3, "uart4"),		/* RTS */
508 		  SUNXI_FUNCTION(0x4, "ts0"),		/* D6 */
509 		  SUNXI_FUNCTION(0x5, "clock"),		/* CLK_FANOUT0 */
510 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 15)),	/* PI_EINT15 */
511 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 16),
512 		  SUNXI_FUNCTION(0x0, "gpio_in"),
513 		  SUNXI_FUNCTION(0x1, "gpio_out"),
514 		  SUNXI_FUNCTION(0x2, "emac0"),		/* EPHY_CLK */
515 		  SUNXI_FUNCTION(0x3, "uart4"),		/* CTS */
516 		  SUNXI_FUNCTION(0x4, "ts0"),		/* D7 */
517 		  SUNXI_FUNCTION(0x5, "clock"),		/* CLK_FANOUT1 */
518 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 16)),	/* PI_EINT16 */
519 };
520 static const unsigned int h616_irq_bank_map[] = { 0, 2, 3, 4, 5, 6, 7, 8 };
521 
522 static const struct sunxi_pinctrl_desc h616_pinctrl_data = {
523 	.pins = h616_pins,
524 	.npins = ARRAY_SIZE(h616_pins),
525 	.irq_banks = ARRAY_SIZE(h616_irq_bank_map),
526 	.irq_bank_map = h616_irq_bank_map,
527 	.irq_read_needs_mux = true,
528 	.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
529 };
530 
531 static int h616_pinctrl_probe(struct platform_device *pdev)
532 {
533 	return sunxi_pinctrl_init(pdev, &h616_pinctrl_data);
534 }
535 
536 static const struct of_device_id h616_pinctrl_match[] = {
537 	{ .compatible = "allwinner,sun50i-h616-pinctrl", },
538 	{}
539 };
540 
541 static struct platform_driver h616_pinctrl_driver = {
542 	.probe	= h616_pinctrl_probe,
543 	.driver	= {
544 		.name		= "sun50i-h616-pinctrl",
545 		.of_match_table	= h616_pinctrl_match,
546 	},
547 };
548 builtin_platform_driver(h616_pinctrl_driver);
549