1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Allwinner H6 R_PIO pin controller driver 4 * 5 * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> 6 * 7 * Based on pinctrl-sun6i-a31-r.c, which is: 8 * Copyright (C) 2014 Boris Brezillon 9 * Boris Brezillon <boris.brezillon@free-electrons.com> 10 * Copyright (C) 2014 Maxime Ripard 11 * Maxime Ripard <maxime.ripard@free-electrons.com> 12 */ 13 14 #include <linux/init.h> 15 #include <linux/platform_device.h> 16 #include <linux/of.h> 17 #include <linux/of_device.h> 18 #include <linux/pinctrl/pinctrl.h> 19 20 #include "pinctrl-sunxi.h" 21 22 static const struct sunxi_desc_pin sun50i_h6_r_pins[] = { 23 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0), 24 SUNXI_FUNCTION(0x0, "gpio_in"), 25 SUNXI_FUNCTION(0x1, "gpio_out"), 26 SUNXI_FUNCTION(0x2, "s_rsb"), /* SCK */ 27 SUNXI_FUNCTION(0x3, "s_i2c"), /* SCK */ 28 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PL_EINT0 */ 29 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1), 30 SUNXI_FUNCTION(0x0, "gpio_in"), 31 SUNXI_FUNCTION(0x1, "gpio_out"), 32 SUNXI_FUNCTION(0x2, "s_rsb"), /* SDA */ 33 SUNXI_FUNCTION(0x3, "s_i2c"), /* SDA */ 34 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PL_EINT1 */ 35 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2), 36 SUNXI_FUNCTION(0x0, "gpio_in"), 37 SUNXI_FUNCTION(0x1, "gpio_out"), 38 SUNXI_FUNCTION(0x2, "s_uart"), /* TX */ 39 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PL_EINT2 */ 40 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3), 41 SUNXI_FUNCTION(0x0, "gpio_in"), 42 SUNXI_FUNCTION(0x1, "gpio_out"), 43 SUNXI_FUNCTION(0x2, "s_uart"), /* RX */ 44 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PL_EINT3 */ 45 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4), 46 SUNXI_FUNCTION(0x0, "gpio_in"), 47 SUNXI_FUNCTION(0x1, "gpio_out"), 48 SUNXI_FUNCTION(0x2, "s_jtag"), /* MS */ 49 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PL_EINT4 */ 50 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5), 51 SUNXI_FUNCTION(0x0, "gpio_in"), 52 SUNXI_FUNCTION(0x1, "gpio_out"), 53 SUNXI_FUNCTION(0x2, "s_jtag"), /* CK */ 54 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PL_EINT5 */ 55 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6), 56 SUNXI_FUNCTION(0x0, "gpio_in"), 57 SUNXI_FUNCTION(0x1, "gpio_out"), 58 SUNXI_FUNCTION(0x2, "s_jtag"), /* DO */ 59 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PL_EINT6 */ 60 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7), 61 SUNXI_FUNCTION(0x0, "gpio_in"), 62 SUNXI_FUNCTION(0x1, "gpio_out"), 63 SUNXI_FUNCTION(0x2, "s_jtag"), /* DI */ 64 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PL_EINT7 */ 65 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8), 66 SUNXI_FUNCTION(0x0, "gpio_in"), 67 SUNXI_FUNCTION(0x1, "gpio_out"), 68 SUNXI_FUNCTION(0x2, "s_pwm"), 69 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PL_EINT8 */ 70 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9), 71 SUNXI_FUNCTION(0x0, "gpio_in"), 72 SUNXI_FUNCTION(0x1, "gpio_out"), 73 SUNXI_FUNCTION(0x2, "s_cir_rx"), 74 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PL_EINT9 */ 75 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10), 76 SUNXI_FUNCTION(0x0, "gpio_in"), 77 SUNXI_FUNCTION(0x1, "gpio_out"), 78 SUNXI_FUNCTION(0x2, "s_w1"), 79 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PL_EINT10 */ 80 /* Hole */ 81 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 0), 82 SUNXI_FUNCTION(0x0, "gpio_in"), 83 SUNXI_FUNCTION(0x1, "gpio_out"), 84 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PM_EINT0 */ 85 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 1), 86 SUNXI_FUNCTION(0x0, "gpio_in"), 87 SUNXI_FUNCTION(0x1, "gpio_out"), 88 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PM_EINT1 */ 89 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 2), 90 SUNXI_FUNCTION(0x0, "gpio_in"), 91 SUNXI_FUNCTION(0x1, "gpio_out"), 92 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2), /* PM_EINT2 */ 93 SUNXI_FUNCTION(0x3, "1wire")), 94 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 3), 95 SUNXI_FUNCTION(0x0, "gpio_in"), 96 SUNXI_FUNCTION(0x1, "gpio_out"), 97 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PM_EINT3 */ 98 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 4), 99 SUNXI_FUNCTION(0x0, "gpio_in"), 100 SUNXI_FUNCTION(0x1, "gpio_out"), 101 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PM_EINT4 */ 102 }; 103 104 static const struct sunxi_pinctrl_desc sun50i_h6_r_pinctrl_data = { 105 .pins = sun50i_h6_r_pins, 106 .npins = ARRAY_SIZE(sun50i_h6_r_pins), 107 .pin_base = PL_BASE, 108 .irq_banks = 2, 109 .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL, 110 }; 111 112 static int sun50i_h6_r_pinctrl_probe(struct platform_device *pdev) 113 { 114 return sunxi_pinctrl_init(pdev, 115 &sun50i_h6_r_pinctrl_data); 116 } 117 118 static const struct of_device_id sun50i_h6_r_pinctrl_match[] = { 119 { .compatible = "allwinner,sun50i-h6-r-pinctrl", }, 120 {} 121 }; 122 123 static struct platform_driver sun50i_h6_r_pinctrl_driver = { 124 .probe = sun50i_h6_r_pinctrl_probe, 125 .driver = { 126 .name = "sun50i-h6-r-pinctrl", 127 .of_match_table = sun50i_h6_r_pinctrl_match, 128 }, 129 }; 130 builtin_platform_driver(sun50i_h6_r_pinctrl_driver); 131