1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
4  *
5  * Based on:
6  * huangshuosheng <huangshuosheng@allwinnertech.com>
7  */
8 
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/of_device.h>
12 #include <linux/pinctrl/pinctrl.h>
13 #include <linux/platform_device.h>
14 
15 #include "pinctrl-sunxi.h"
16 
17 static const struct sunxi_desc_pin a100_pins[] = {
18 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
19 		  SUNXI_FUNCTION(0x0, "gpio_in"),
20 		  SUNXI_FUNCTION(0x1, "gpio_out"),
21 		  SUNXI_FUNCTION(0x2, "uart2"),		/* TX */
22 		  SUNXI_FUNCTION(0x3, "spi2"),		/* CS */
23 		  SUNXI_FUNCTION(0x4, "jtag"),		/* MS */
24 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),
25 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
26 		  SUNXI_FUNCTION(0x0, "gpio_in"),
27 		  SUNXI_FUNCTION(0x1, "gpio_out"),
28 		  SUNXI_FUNCTION(0x2, "uart2"),		/* RX */
29 		  SUNXI_FUNCTION(0x3, "spi2"),		/* CLK */
30 		  SUNXI_FUNCTION(0x4, "jtag"),		/* CK */
31 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),
32 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
33 		  SUNXI_FUNCTION(0x0, "gpio_in"),
34 		  SUNXI_FUNCTION(0x1, "gpio_out"),
35 		  SUNXI_FUNCTION(0x2, "uart2"),		/* RTS */
36 		  SUNXI_FUNCTION(0x3, "spi2"),		/* MOSI */
37 		  SUNXI_FUNCTION(0x4, "jtag"),		/* DO */
38 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),
39 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
40 		  SUNXI_FUNCTION(0x0, "gpio_in"),
41 		  SUNXI_FUNCTION(0x1, "gpio_out"),
42 		  SUNXI_FUNCTION(0x2, "uart2"),		/* CTS */
43 		  SUNXI_FUNCTION(0x3, "spi2"),		/* MISO */
44 		  SUNXI_FUNCTION(0x4, "jtag"),		/* DI */
45 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),
46 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
47 		  SUNXI_FUNCTION(0x0, "gpio_in"),
48 		  SUNXI_FUNCTION(0x1, "gpio_out"),
49 		  SUNXI_FUNCTION(0x2, "i2c1"),		/* SCK */
50 		  SUNXI_FUNCTION(0x3, "i2s0"),		/* MCLK */
51 		  SUNXI_FUNCTION(0x4, "jtag_gpu"),	/* MS_GPU */
52 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),
53 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
54 		  SUNXI_FUNCTION(0x0, "gpio_in"),
55 		  SUNXI_FUNCTION(0x1, "gpio_out"),
56 		  SUNXI_FUNCTION(0x2, "i2c1"),		/* SDA */
57 		  SUNXI_FUNCTION(0x3, "i2s0"),		/* BCLK */
58 		  SUNXI_FUNCTION(0x4, "jtag_gpu"),	/* CK_GPU */
59 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),
60 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
61 		  SUNXI_FUNCTION(0x0, "gpio_in"),
62 		  SUNXI_FUNCTION(0x1, "gpio_out"),
63 		  SUNXI_FUNCTION(0x3, "i2s0"),		/* LRCK */
64 		  SUNXI_FUNCTION(0x4, "jtag_gpu"),	/* DO_GPU */
65 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),
66 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
67 		  SUNXI_FUNCTION(0x0, "gpio_in"),
68 		  SUNXI_FUNCTION(0x1, "gpio_out"),
69 		  SUNXI_FUNCTION(0x2, "spdif"),		/* DIN */
70 		  SUNXI_FUNCTION(0x3, "i2s0_dout0"),	/* DOUT0 */
71 		  SUNXI_FUNCTION(0x4, "i2s0_din1"),	/* DIN1 */
72 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),
73 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
74 		  SUNXI_FUNCTION(0x0, "gpio_in"),
75 		  SUNXI_FUNCTION(0x1, "gpio_out"),
76 		  SUNXI_FUNCTION(0x2, "spdif"),		/* DOUT */
77 		  SUNXI_FUNCTION(0x3, "i2s0_din0"),	/* DIN0 */
78 		  SUNXI_FUNCTION(0x4, "i2s0_dout1"),	/* DOUT1 */
79 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),
80 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
81 		  SUNXI_FUNCTION(0x0, "gpio_in"),
82 		  SUNXI_FUNCTION(0x1, "gpio_out"),
83 		  SUNXI_FUNCTION(0x2, "uart0"),		/* TX */
84 		  SUNXI_FUNCTION(0x3, "i2c0"),		/* SCK */
85 		  SUNXI_FUNCTION(0x4, "jtag_gpu"),	/* DI_GPU */
86 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),
87 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
88 		  SUNXI_FUNCTION(0x0, "gpio_in"),
89 		  SUNXI_FUNCTION(0x1, "gpio_out"),
90 		  SUNXI_FUNCTION(0x2, "uart0"),		/* RX */
91 		  SUNXI_FUNCTION(0x3, "i2c0"),		/* SDA */
92 		  SUNXI_FUNCTION(0x4, "pwm1"),
93 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)),
94 	/* HOLE */
95 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
96 		  SUNXI_FUNCTION(0x0, "gpio_in"),
97 		  SUNXI_FUNCTION(0x1, "gpio_out"),
98 		  SUNXI_FUNCTION(0x2, "nand0"),		/* WE */
99 		  SUNXI_FUNCTION(0x3, "mmc2"),		/* DS */
100 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)),
101 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
102 		  SUNXI_FUNCTION(0x0, "gpio_in"),
103 		  SUNXI_FUNCTION(0x1, "gpio_out"),
104 		  SUNXI_FUNCTION(0x2, "nand0"),		/* ALE */
105 		  SUNXI_FUNCTION(0x3, "mmc2"),		/* RST */
106 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)),
107 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
108 		  SUNXI_FUNCTION(0x0, "gpio_in"),
109 		  SUNXI_FUNCTION(0x1, "gpio_out"),
110 		  SUNXI_FUNCTION(0x2, "nand0"),		/* CLE */
111 		  SUNXI_FUNCTION(0x4, "spi0"),		/* MOSI */
112 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)),
113 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
114 		  SUNXI_FUNCTION(0x0, "gpio_in"),
115 		  SUNXI_FUNCTION(0x1, "gpio_out"),
116 		  SUNXI_FUNCTION(0x2, "nand0"),		/* CE1 */
117 		  SUNXI_FUNCTION(0x4, "spi0"),		/* CS0 */
118 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)),
119 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
120 		  SUNXI_FUNCTION(0x0, "gpio_in"),
121 		  SUNXI_FUNCTION(0x1, "gpio_out"),
122 		  SUNXI_FUNCTION(0x2, "nand0"),		/* CE0 */
123 		  SUNXI_FUNCTION(0x4, "spi0"),		/* MISO */
124 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)),
125 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
126 		  SUNXI_FUNCTION(0x0, "gpio_in"),
127 		  SUNXI_FUNCTION(0x1, "gpio_out"),
128 		  SUNXI_FUNCTION(0x2, "nand0"),		/* RE */
129 		  SUNXI_FUNCTION(0x3, "mmc2"),		/* CLK */
130 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)),
131 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
132 		  SUNXI_FUNCTION(0x0, "gpio_in"),
133 		  SUNXI_FUNCTION(0x1, "gpio_out"),
134 		  SUNXI_FUNCTION(0x2, "nand0"),		/* RB0 */
135 		  SUNXI_FUNCTION(0x3, "mmc2"),		/* CMD */
136 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)),
137 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
138 		  SUNXI_FUNCTION(0x0, "gpio_in"),
139 		  SUNXI_FUNCTION(0x1, "gpio_out"),
140 		  SUNXI_FUNCTION(0x2, "nand0"),		/* RB1 */
141 		  SUNXI_FUNCTION(0x4, "spi0"),		/* CS1 */
142 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)),
143 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
144 		  SUNXI_FUNCTION(0x0, "gpio_in"),
145 		  SUNXI_FUNCTION(0x1, "gpio_out"),
146 		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ7 */
147 		  SUNXI_FUNCTION(0x3, "mmc2"),		/* D3 */
148 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)),
149 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
150 		  SUNXI_FUNCTION(0x0, "gpio_in"),
151 		  SUNXI_FUNCTION(0x1, "gpio_out"),
152 		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ6 */
153 		  SUNXI_FUNCTION(0x3, "mmc2"),		/* D4 */
154 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)),
155 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
156 		  SUNXI_FUNCTION(0x0, "gpio_in"),
157 		  SUNXI_FUNCTION(0x1, "gpio_out"),
158 		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ5 */
159 		  SUNXI_FUNCTION(0x3, "mmc2"),		/* D0 */
160 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)),
161 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
162 		  SUNXI_FUNCTION(0x0, "gpio_in"),
163 		  SUNXI_FUNCTION(0x1, "gpio_out"),
164 		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ4 */
165 		  SUNXI_FUNCTION(0x3, "mmc2"),		/* D5 */
166 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)),
167 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
168 		  SUNXI_FUNCTION(0x0, "gpio_in"),
169 		  SUNXI_FUNCTION(0x1, "gpio_out"),
170 		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQS */
171 		  SUNXI_FUNCTION(0x4, "spi0"),		/* CLK */
172 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)),
173 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
174 		  SUNXI_FUNCTION(0x0, "gpio_in"),
175 		  SUNXI_FUNCTION(0x1, "gpio_out"),
176 		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ3 */
177 		  SUNXI_FUNCTION(0x3, "mmc2"),		/* D1 */
178 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)),
179 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
180 		  SUNXI_FUNCTION(0x0, "gpio_in"),
181 		  SUNXI_FUNCTION(0x1, "gpio_out"),
182 		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ2 */
183 		  SUNXI_FUNCTION(0x3, "mmc2"),		/* D6 */
184 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 14)),
185 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
186 		  SUNXI_FUNCTION(0x0, "gpio_in"),
187 		  SUNXI_FUNCTION(0x1, "gpio_out"),
188 		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ1 */
189 		  SUNXI_FUNCTION(0x3, "mmc2"),		/* D2 */
190 		  SUNXI_FUNCTION(0x4, "spi0"),		/* WP */
191 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 15)),
192 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
193 		  SUNXI_FUNCTION(0x0, "gpio_in"),
194 		  SUNXI_FUNCTION(0x1, "gpio_out"),
195 		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ0 */
196 		  SUNXI_FUNCTION(0x3, "mmc2"),		/* D7 */
197 		  SUNXI_FUNCTION(0x4, "spi0"),		/* HOLD */
198 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 16)),
199 	/* HOLE */
200 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
201 		  SUNXI_FUNCTION(0x0, "gpio_in"),
202 		  SUNXI_FUNCTION(0x1, "gpio_out"),
203 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D2 */
204 		  SUNXI_FUNCTION(0x3, "lvds0"),		/* D0P */
205 		  SUNXI_FUNCTION(0x4, "dsi0"),		/* DP0 */
206 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)),
207 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
208 		  SUNXI_FUNCTION(0x0, "gpio_in"),
209 		  SUNXI_FUNCTION(0x1, "gpio_out"),
210 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D3 */
211 		  SUNXI_FUNCTION(0x3, "lvds0"),		/* D0N */
212 		  SUNXI_FUNCTION(0x4, "dsi0"),		/* DM0 */
213 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)),
214 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
215 		  SUNXI_FUNCTION(0x0, "gpio_in"),
216 		  SUNXI_FUNCTION(0x1, "gpio_out"),
217 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D4 */
218 		  SUNXI_FUNCTION(0x3, "lvds0"),		/* D1P */
219 		  SUNXI_FUNCTION(0x4, "dsi0"),		/* DP1 */
220 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)),
221 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
222 		  SUNXI_FUNCTION(0x0, "gpio_in"),
223 		  SUNXI_FUNCTION(0x1, "gpio_out"),
224 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D5 */
225 		  SUNXI_FUNCTION(0x3, "lvds0"),		/* D1N */
226 		  SUNXI_FUNCTION(0x4, "dsi0"),		/* DM1 */
227 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)),
228 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
229 		  SUNXI_FUNCTION(0x0, "gpio_in"),
230 		  SUNXI_FUNCTION(0x1, "gpio_out"),
231 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D6 */
232 		  SUNXI_FUNCTION(0x3, "lvds0"),		/* D2P */
233 		  SUNXI_FUNCTION(0x4, "dsi0"),		/* CKP */
234 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)),
235 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
236 		  SUNXI_FUNCTION(0x0, "gpio_in"),
237 		  SUNXI_FUNCTION(0x1, "gpio_out"),
238 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D7 */
239 		  SUNXI_FUNCTION(0x3, "lvds0"),		/* D2N */
240 		  SUNXI_FUNCTION(0x4, "dsi0"),		/* CKM */
241 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)),
242 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
243 		  SUNXI_FUNCTION(0x0, "gpio_in"),
244 		  SUNXI_FUNCTION(0x1, "gpio_out"),
245 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D10 */
246 		  SUNXI_FUNCTION(0x3, "lvds0"),		/* CKP */
247 		  SUNXI_FUNCTION(0x4, "dsi0"),		/* DP2 */
248 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)),
249 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
250 		  SUNXI_FUNCTION(0x0, "gpio_in"),
251 		  SUNXI_FUNCTION(0x1, "gpio_out"),
252 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D11 */
253 		  SUNXI_FUNCTION(0x3, "lvds0"),		/* CKN */
254 		  SUNXI_FUNCTION(0x4, "dsi0"),		/* DM2 */
255 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)),
256 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
257 		  SUNXI_FUNCTION(0x0, "gpio_in"),
258 		  SUNXI_FUNCTION(0x1, "gpio_out"),
259 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D12 */
260 		  SUNXI_FUNCTION(0x4, "dsi0"),		/* DP3 */
261 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)),
262 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
263 		  SUNXI_FUNCTION(0x0, "gpio_in"),
264 		  SUNXI_FUNCTION(0x1, "gpio_out"),
265 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D13 */
266 		  SUNXI_FUNCTION(0x4, "dsi0"),		/* DM3 */
267 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)),
268 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
269 		  SUNXI_FUNCTION(0x0, "gpio_in"),
270 		  SUNXI_FUNCTION(0x1, "gpio_out"),
271 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D14 */
272 		  SUNXI_FUNCTION(0x4, "spi1"),		/* CS */
273 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)),
274 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
275 		  SUNXI_FUNCTION(0x0, "gpio_in"),
276 		  SUNXI_FUNCTION(0x1, "gpio_out"),
277 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D15 */
278 		  SUNXI_FUNCTION(0x4, "spi1"),		/* CLK */
279 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)),
280 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
281 		  SUNXI_FUNCTION(0x0, "gpio_in"),
282 		  SUNXI_FUNCTION(0x1, "gpio_out"),
283 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D18 */
284 		  SUNXI_FUNCTION(0x4, "spi1"),		/* MOSI */
285 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)),
286 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
287 		  SUNXI_FUNCTION(0x0, "gpio_in"),
288 		  SUNXI_FUNCTION(0x1, "gpio_out"),
289 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D19 */
290 		  SUNXI_FUNCTION(0x4, "spi1"),		/* MISO */
291 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)),
292 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
293 		  SUNXI_FUNCTION(0x0, "gpio_in"),
294 		  SUNXI_FUNCTION(0x1, "gpio_out"),
295 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D20 */
296 		  SUNXI_FUNCTION(0x4, "uart3"),		/* TX */
297 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)),
298 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
299 		  SUNXI_FUNCTION(0x0, "gpio_in"),
300 		  SUNXI_FUNCTION(0x1, "gpio_out"),
301 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D21 */
302 		  SUNXI_FUNCTION(0x4, "uart3"),		/* RX */
303 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)),
304 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
305 		  SUNXI_FUNCTION(0x0, "gpio_in"),
306 		  SUNXI_FUNCTION(0x1, "gpio_out"),
307 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D22 */
308 		  SUNXI_FUNCTION(0x4, "uart3"),		/* RTS */
309 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)),
310 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
311 		  SUNXI_FUNCTION(0x0, "gpio_in"),
312 		  SUNXI_FUNCTION(0x1, "gpio_out"),
313 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D23 */
314 		  SUNXI_FUNCTION(0x4, "uart3"),		/* CTS */
315 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 17)),
316 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
317 		  SUNXI_FUNCTION(0x0, "gpio_in"),
318 		  SUNXI_FUNCTION(0x1, "gpio_out"),
319 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* CLK */
320 		  SUNXI_FUNCTION(0x4, "uart4"),		/* TX */
321 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 18)),
322 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
323 		  SUNXI_FUNCTION(0x0, "gpio_in"),
324 		  SUNXI_FUNCTION(0x1, "gpio_out"),
325 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* DE */
326 		  SUNXI_FUNCTION(0x4, "uart4"),		/* RX */
327 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 19)),
328 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
329 		  SUNXI_FUNCTION(0x0, "gpio_in"),
330 		  SUNXI_FUNCTION(0x1, "gpio_out"),
331 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* HSYNC */
332 		  SUNXI_FUNCTION(0x3, "pwm2"),
333 		  SUNXI_FUNCTION(0x4, "uart4"),		/* RTS */
334 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 20)),
335 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
336 		  SUNXI_FUNCTION(0x0, "gpio_in"),
337 		  SUNXI_FUNCTION(0x1, "gpio_out"),
338 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* VSYNC */
339 		  SUNXI_FUNCTION(0x3, "pwm3"),
340 		  SUNXI_FUNCTION(0x4, "uart4"),		/* CTS */
341 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 21)),
342 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
343 		  SUNXI_FUNCTION(0x0, "gpio_in"),
344 		  SUNXI_FUNCTION(0x1, "gpio_out"),
345 		  SUNXI_FUNCTION(0x2, "pwm1"),
346 		  SUNXI_FUNCTION(0x4, "i2c0"),		/* SCK */
347 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 22)),
348 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
349 		  SUNXI_FUNCTION(0x0, "gpio_in"),
350 		  SUNXI_FUNCTION(0x1, "gpio_out"),
351 		  SUNXI_FUNCTION(0x2, "pwm0"),
352 		  SUNXI_FUNCTION(0x4, "i2c0"),		/* SDA */
353 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 23)),
354 	/* HOLE */
355 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
356 		  SUNXI_FUNCTION(0x0, "gpio_in"),
357 		  SUNXI_FUNCTION(0x1, "gpio_out"),
358 		  SUNXI_FUNCTION(0x2, "csi"),		/* MCLK */
359 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)),
360 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
361 		  SUNXI_FUNCTION(0x0, "gpio_in"),
362 		  SUNXI_FUNCTION(0x1, "gpio_out"),
363 		  SUNXI_FUNCTION(0x2, "i2c2"),		/* SCK */
364 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)),
365 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
366 		  SUNXI_FUNCTION(0x0, "gpio_in"),
367 		  SUNXI_FUNCTION(0x1, "gpio_out"),
368 		  SUNXI_FUNCTION(0x2, "i2c2"),		/* SDA */
369 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)),
370 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
371 		  SUNXI_FUNCTION(0x0, "gpio_in"),
372 		  SUNXI_FUNCTION(0x1, "gpio_out"),
373 		  SUNXI_FUNCTION(0x2, "i2c3"),		/* SCK */
374 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)),
375 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
376 		  SUNXI_FUNCTION(0x0, "gpio_in"),
377 		  SUNXI_FUNCTION(0x1, "gpio_out"),
378 		  SUNXI_FUNCTION(0x2, "i2c3"),		/* SDA */
379 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)),
380 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
381 		  SUNXI_FUNCTION(0x0, "gpio_in"),
382 		  SUNXI_FUNCTION(0x1, "gpio_out"),
383 		  SUNXI_FUNCTION(0x2, "csi"),		/* MCLK */
384 		  SUNXI_FUNCTION(0x3, "pll"),		/* LOCK_DBG */
385 		  SUNXI_FUNCTION(0x4, "i2s2"),		/* MCLK */
386 		  SUNXI_FUNCTION(0x5, "ledc"),		/* LEDC */
387 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)),
388 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
389 		  SUNXI_FUNCTION(0x0, "gpio_in"),
390 		  SUNXI_FUNCTION(0x1, "gpio_out"),
391 		  SUNXI_FUNCTION(0x3, "bist0"),		/* RESULT0 */
392 		  SUNXI_FUNCTION(0x4, "i2s2"),		/* BCLK */
393 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)),
394 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
395 		  SUNXI_FUNCTION(0x0, "gpio_in"),
396 		  SUNXI_FUNCTION(0x1, "gpio_out"),
397 		  SUNXI_FUNCTION(0x2, "csi"),		/* SM_VS */
398 		  SUNXI_FUNCTION(0x3, "bist0"),		/* RESULT1 */
399 		  SUNXI_FUNCTION(0x4, "i2s2"),		/* LRCK */
400 		  SUNXI_FUNCTION(0x5, "tcon0"),		/* TRIG */
401 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3,	7)),
402 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
403 		  SUNXI_FUNCTION(0x0, "gpio_in"),
404 		  SUNXI_FUNCTION(0x1, "gpio_out"),
405 		  SUNXI_FUNCTION(0x3, "bist0"),		/* RESULT2 */
406 		  SUNXI_FUNCTION(0x4, "i2s2"),		/* DOUT0 */
407 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)),
408 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
409 		  SUNXI_FUNCTION(0x0, "gpio_in"),
410 		  SUNXI_FUNCTION(0x1, "gpio_out"),
411 		  SUNXI_FUNCTION(0x3, "bist0"),		/* RESULT3 */
412 		  SUNXI_FUNCTION(0x4, "i2s2"),		/* DIN0 */
413 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)),
414 	/* HOLE */
415 	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
416 		  SUNXI_FUNCTION(0x0, "gpio_in"),
417 		  SUNXI_FUNCTION(0x1, "gpio_out"),
418 		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D1 */
419 		  SUNXI_FUNCTION(0x3, "jtag"),		/* MS1 */
420 		  SUNXI_FUNCTION(0x4, "jtag_gpu"),	/* MS_GPU */
421 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 0)),
422 	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
423 		  SUNXI_FUNCTION(0x0, "gpio_in"),
424 		  SUNXI_FUNCTION(0x1, "gpio_out"),
425 		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D0 */
426 		  SUNXI_FUNCTION(0x3, "jtag"),		/* DI1 */
427 		  SUNXI_FUNCTION(0x4, "jtag_gpu"),	/* DI_GPU */
428 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 1)),
429 	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
430 		  SUNXI_FUNCTION(0x0, "gpio_in"),
431 		  SUNXI_FUNCTION(0x1, "gpio_out"),
432 		  SUNXI_FUNCTION(0x2, "mmc0"),		/* CLK */
433 		  SUNXI_FUNCTION(0x3, "uart0"),		/* TX */
434 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 2)),
435 	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
436 		  SUNXI_FUNCTION(0x0, "gpio_in"),
437 		  SUNXI_FUNCTION(0x1, "gpio_out"),
438 		  SUNXI_FUNCTION(0x2, "mmc0"),		/* CMD */
439 		  SUNXI_FUNCTION(0x3, "jtag"),		/* DO */
440 		  SUNXI_FUNCTION(0x4, "jtag_gpu"),	/* DO_GPU */
441 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 3)),
442 	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
443 		  SUNXI_FUNCTION(0x0, "gpio_in"),
444 		  SUNXI_FUNCTION(0x1, "gpio_out"),
445 		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D3 */
446 		  SUNXI_FUNCTION(0x3, "uart0"),		/* RX */
447 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 4)),
448 	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
449 		  SUNXI_FUNCTION(0x0, "gpio_in"),
450 		  SUNXI_FUNCTION(0x1, "gpio_out"),
451 		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D2 */
452 		  SUNXI_FUNCTION(0x3, "jtag"),		/* CK */
453 		  SUNXI_FUNCTION(0x4, "jtag_gpu"),	/* CK_GPU */
454 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 5)),
455 	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
456 		  SUNXI_FUNCTION(0x0, "gpio_in"),
457 		  SUNXI_FUNCTION(0x1, "gpio_out"),
458 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 6)),
459 	/* HOLE */
460 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
461 		  SUNXI_FUNCTION(0x0, "gpio_in"),
462 		  SUNXI_FUNCTION(0x1, "gpio_out"),
463 		  SUNXI_FUNCTION(0x2, "mmc1"),		/* CLK */
464 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 0)),
465 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
466 		  SUNXI_FUNCTION(0x0, "gpio_in"),
467 		  SUNXI_FUNCTION(0x1, "gpio_out"),
468 		  SUNXI_FUNCTION(0x2, "mmc1"),		/* CMD */
469 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 1)),
470 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
471 		  SUNXI_FUNCTION(0x0, "gpio_in"),
472 		  SUNXI_FUNCTION(0x1, "gpio_out"),
473 		  SUNXI_FUNCTION(0x2, "mmc1"),		/* D0 */
474 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 2)),
475 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
476 		  SUNXI_FUNCTION(0x0, "gpio_in"),
477 		  SUNXI_FUNCTION(0x1, "gpio_out"),
478 		  SUNXI_FUNCTION(0x2, "mmc1"),		/* D1 */
479 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 3)),
480 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
481 		  SUNXI_FUNCTION(0x0, "gpio_in"),
482 		  SUNXI_FUNCTION(0x1, "gpio_out"),
483 		  SUNXI_FUNCTION(0x2, "mmc1"),		/* D2 */
484 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 4)),
485 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
486 		  SUNXI_FUNCTION(0x0, "gpio_in"),
487 		  SUNXI_FUNCTION(0x1, "gpio_out"),
488 		  SUNXI_FUNCTION(0x2, "mmc1"),		/* D3 */
489 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 5)),
490 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
491 		  SUNXI_FUNCTION(0x0, "gpio_in"),
492 		  SUNXI_FUNCTION(0x1, "gpio_out"),
493 		  SUNXI_FUNCTION(0x2, "uart1"),		/* TX */
494 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 6)),
495 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
496 		  SUNXI_FUNCTION(0x0, "gpio_in"),
497 		  SUNXI_FUNCTION(0x1, "gpio_out"),
498 		  SUNXI_FUNCTION(0x2, "uart1"),		/* RX */
499 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 7)),
500 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
501 		  SUNXI_FUNCTION(0x0, "gpio_in"),
502 		  SUNXI_FUNCTION(0x1, "gpio_out"),
503 		  SUNXI_FUNCTION(0x2, "uart1"),		/* RTS */
504 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 8)),
505 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
506 		  SUNXI_FUNCTION(0x0, "gpio_in"),
507 		  SUNXI_FUNCTION(0x1, "gpio_out"),
508 		  SUNXI_FUNCTION(0x2, "uart1"),		/* CTS */
509 		  SUNXI_FUNCTION(0x3, "i2s1"),		/* MCLK */
510 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 9)),
511 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
512 		  SUNXI_FUNCTION(0x0, "gpio_in"),
513 		  SUNXI_FUNCTION(0x1, "gpio_out"),
514 		  SUNXI_FUNCTION(0x3, "i2s1"),		/* BCLK */
515 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 10)),
516 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
517 		  SUNXI_FUNCTION(0x0, "gpio_in"),
518 		  SUNXI_FUNCTION(0x1, "gpio_out"),
519 		  SUNXI_FUNCTION(0x3, "i2s1"),		/* LRCK */
520 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 11)),
521 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
522 		  SUNXI_FUNCTION(0x0, "gpio_in"),
523 		  SUNXI_FUNCTION(0x1, "gpio_out"),
524 		  SUNXI_FUNCTION(0x3, "i2s1_dout0"),	/* DOUT0 */
525 		  SUNXI_FUNCTION(0x4, "i2s1_din1"),	/* DIN1 */
526 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 12)),
527 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
528 		  SUNXI_FUNCTION(0x0, "gpio_in"),
529 		  SUNXI_FUNCTION(0x1, "gpio_out"),
530 		  SUNXI_FUNCTION(0x3, "i2s1_din0"),	/* DIN0 */
531 		  SUNXI_FUNCTION(0x4, "i2s1_dout1"),	/* DOUT1 */
532 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 13)),
533 	/* HOLE */
534 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
535 		  SUNXI_FUNCTION(0x0, "gpio_in"),
536 		  SUNXI_FUNCTION(0x1, "gpio_out"),
537 		  SUNXI_FUNCTION(0x2, "i2c0"),		/* SCK */
538 		  SUNXI_FUNCTION(0x5, "emac0"),		/* RXD1 */
539 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 0)),
540 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
541 		  SUNXI_FUNCTION(0x0, "gpio_in"),
542 		  SUNXI_FUNCTION(0x1, "gpio_out"),
543 		  SUNXI_FUNCTION(0x2, "i2c0"),		/* SDA */
544 		  SUNXI_FUNCTION(0x5, "emac0"),		/* RXD0 */
545 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 1)),
546 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
547 		  SUNXI_FUNCTION(0x0, "gpio_in"),
548 		  SUNXI_FUNCTION(0x1, "gpio_out"),
549 		  SUNXI_FUNCTION(0x2, "i2c1"),		/* SCK */
550 		  SUNXI_FUNCTION(0x5, "emac0"),		/* RXCTL */
551 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 2)),
552 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
553 		  SUNXI_FUNCTION(0x0, "gpio_in"),
554 		  SUNXI_FUNCTION(0x1, "gpio_out"),
555 		  SUNXI_FUNCTION(0x2, "i2c1"),		/* SDA */
556 		  SUNXI_FUNCTION(0x3, "cir0"),		/* OUT */
557 		  SUNXI_FUNCTION(0x5, "emac0"),		/* CLKIN */
558 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 3)),
559 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
560 		  SUNXI_FUNCTION(0x0, "gpio_in"),
561 		  SUNXI_FUNCTION(0x1, "gpio_out"),
562 		  SUNXI_FUNCTION(0x2, "uart3"),		/* TX */
563 		  SUNXI_FUNCTION(0x3, "spi1"),		/* CS */
564 		  SUNXI_FUNCTION(0x5, "emac0"),		/* TXD1 */
565 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 4)),
566 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
567 		  SUNXI_FUNCTION(0x0, "gpio_in"),
568 		  SUNXI_FUNCTION(0x1, "gpio_out"),
569 		  SUNXI_FUNCTION(0x2, "uart3"),		/* RX */
570 		  SUNXI_FUNCTION(0x3, "spi1"),		/* CLK */
571 		  SUNXI_FUNCTION(0x4, "ledc"),
572 		  SUNXI_FUNCTION(0x5, "emac0"),		/* TXD0 */
573 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 5)),
574 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
575 		  SUNXI_FUNCTION(0x0, "gpio_in"),
576 		  SUNXI_FUNCTION(0x1, "gpio_out"),
577 		  SUNXI_FUNCTION(0x2, "uart3"),		/* RTS */
578 		  SUNXI_FUNCTION(0x3, "spi1"),		/* MOSI */
579 		  SUNXI_FUNCTION(0x5, "emac0"),		/* TXCK */
580 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 6)),
581 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
582 		  SUNXI_FUNCTION(0x0, "gpio_in"),
583 		  SUNXI_FUNCTION(0x1, "gpio_out"),
584 		  SUNXI_FUNCTION(0x2, "uart3"),		/* CTS */
585 		  SUNXI_FUNCTION(0x3, "spi1"),		/* MISO */
586 		  SUNXI_FUNCTION(0x4, "spdif"),		/* OUT */
587 		  SUNXI_FUNCTION(0x5, "emac0"),		/* TXCTL */
588 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 7)),
589 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
590 		  SUNXI_FUNCTION(0x0, "gpio_in"),
591 		  SUNXI_FUNCTION(0x1, "gpio_out"),
592 		  SUNXI_FUNCTION(0x2, "dmic"),		/* CLK */
593 		  SUNXI_FUNCTION(0x3, "spi2"),		/* CS */
594 		  SUNXI_FUNCTION(0x4, "i2s2"),		/* MCLK */
595 		  SUNXI_FUNCTION(0x5, "i2s2_din2"),	/* DIN2 */
596 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 8)),
597 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
598 		  SUNXI_FUNCTION(0x0, "gpio_in"),
599 		  SUNXI_FUNCTION(0x1, "gpio_out"),
600 		  SUNXI_FUNCTION(0x2, "dmic"),		/* DATA0 */
601 		  SUNXI_FUNCTION(0x3, "spi2"),		/* CLK */
602 		  SUNXI_FUNCTION(0x4, "i2s2"),		/* BCLK */
603 		  SUNXI_FUNCTION(0x5, "emac0"),		/* MDC */
604 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 9)),
605 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
606 		  SUNXI_FUNCTION(0x0, "gpio_in"),
607 		  SUNXI_FUNCTION(0x1, "gpio_out"),
608 		  SUNXI_FUNCTION(0x2, "dmic"),		/* DATA1 */
609 		  SUNXI_FUNCTION(0x3, "spi2"),		/* MOSI */
610 		  SUNXI_FUNCTION(0x4, "i2s2"),		/* LRCK */
611 		  SUNXI_FUNCTION(0x5, "emac0"),		/* MDIO */
612 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 10)),
613 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
614 		  SUNXI_FUNCTION(0x0, "gpio_in"),
615 		  SUNXI_FUNCTION(0x1, "gpio_out"),
616 		  SUNXI_FUNCTION(0x2, "dmic"),		/* DATA2 */
617 		  SUNXI_FUNCTION(0x3, "spi2"),		/* MISO */
618 		  SUNXI_FUNCTION(0x4, "i2s2_dout0"),	/* DOUT0 */
619 		  SUNXI_FUNCTION(0x5, "i2s2_din1"),	/* DIN1 */
620 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 11)),
621 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
622 		  SUNXI_FUNCTION(0x0, "gpio_in"),
623 		  SUNXI_FUNCTION(0x1, "gpio_out"),
624 		  SUNXI_FUNCTION(0x2, "dmic"),		/* DATA3 */
625 		  SUNXI_FUNCTION(0x3, "i2c3"),		/* SCK */
626 		  SUNXI_FUNCTION(0x4, "i2s2_din0"),	/* DIN0 */
627 		  SUNXI_FUNCTION(0x5, "i2s2_dout1"),	/* DOUT1 */
628 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 12)),
629 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13),
630 		  SUNXI_FUNCTION(0x0, "gpio_in"),
631 		  SUNXI_FUNCTION(0x1, "gpio_out"),
632 		  SUNXI_FUNCTION(0x3, "i2c3"),		/* SCK */
633 		  SUNXI_FUNCTION(0x4, "i2s3"),		/* MCLK */
634 		  SUNXI_FUNCTION(0x5, "emac0"),		/* EPHY */
635 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 13)),
636 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
637 		  SUNXI_FUNCTION(0x0, "gpio_in"),
638 		  SUNXI_FUNCTION(0x1, "gpio_out"),
639 		  SUNXI_FUNCTION(0x4, "i2s3"),		/* BCLK */
640 		  SUNXI_FUNCTION(0x5, "emac0"),		/* RXD3 */
641 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 14)),
642 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
643 		  SUNXI_FUNCTION(0x0, "gpio_in"),
644 		  SUNXI_FUNCTION(0x1, "gpio_out"),
645 		  SUNXI_FUNCTION(0x4, "i2s3"),		/* LRCK */
646 		  SUNXI_FUNCTION(0x5, "emac0"),		/* RXD2 */
647 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 15)),
648 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
649 		  SUNXI_FUNCTION(0x0, "gpio_in"),
650 		  SUNXI_FUNCTION(0x1, "gpio_out"),
651 		  SUNXI_FUNCTION(0x3, "i2s3_dout0"),	/* DOUT0 */
652 		  SUNXI_FUNCTION(0x4, "i2s3_din1"),	/* DIN1 */
653 		  SUNXI_FUNCTION(0x5, "emac0"),		/* RXCK */
654 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 16)),
655 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
656 		  SUNXI_FUNCTION(0x0, "gpio_in"),
657 		  SUNXI_FUNCTION(0x1, "gpio_out"),
658 		  SUNXI_FUNCTION(0x3, "i2s3_dout1"),	/* DOUT1 */
659 		  SUNXI_FUNCTION(0x4, "i2s3_din0"),	/* DIN0 */
660 		  SUNXI_FUNCTION(0x5, "emac0"),		/* TXD3 */
661 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 17)),
662 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
663 		  SUNXI_FUNCTION(0x0, "gpio_in"),
664 		  SUNXI_FUNCTION(0x1, "gpio_out"),
665 		  SUNXI_FUNCTION(0x2, "cir0"),		/* OUT */
666 		  SUNXI_FUNCTION(0x3, "i2s3_dout2"),	/* DOUT2 */
667 		  SUNXI_FUNCTION(0x4, "i2s3_din2"),	/* DIN2 */
668 		  SUNXI_FUNCTION(0x5, "emac0"),		/* TXD2 */
669 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 18)),
670 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
671 		  SUNXI_FUNCTION(0x0, "gpio_in"),
672 		  SUNXI_FUNCTION(0x1, "gpio_out"),
673 		  SUNXI_FUNCTION(0x2, "cir0"),		/* IN */
674 		  SUNXI_FUNCTION(0x3, "i2s3_dout3"),	/* DOUT3 */
675 		  SUNXI_FUNCTION(0x4, "i2s3_din3"),	/* DIN3 */
676 		  SUNXI_FUNCTION(0x5, "ledc"),
677 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 19)),
678 };
679 
680 static const unsigned int a100_irq_bank_map[] = { 1, 2, 3, 4, 5, 6, 7};
681 
682 static const struct sunxi_pinctrl_desc a100_pinctrl_data = {
683 	.pins = a100_pins,
684 	.npins = ARRAY_SIZE(a100_pins),
685 	.irq_banks = 7,
686 	.irq_bank_map = a100_irq_bank_map,
687 	.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_CTL,
688 };
689 
690 static int a100_pinctrl_probe(struct platform_device *pdev)
691 {
692 	return sunxi_pinctrl_init(pdev, &a100_pinctrl_data);
693 }
694 
695 static const struct of_device_id a100_pinctrl_match[] = {
696 	{ .compatible = "allwinner,sun50i-a100-pinctrl", },
697 	{}
698 };
699 MODULE_DEVICE_TABLE(of, a100_pinctrl_match);
700 
701 static struct platform_driver a100_pinctrl_driver = {
702 	.probe	= a100_pinctrl_probe,
703 	.driver	= {
704 		.name		= "sun50i-a100-pinctrl",
705 		.of_match_table	= a100_pinctrl_match,
706 	},
707 };
708 module_platform_driver(a100_pinctrl_driver);
709