1*aa74c44bSWells Lu // SPDX-License-Identifier: GPL-2.0 2*aa74c44bSWells Lu /* 3*aa74c44bSWells Lu * SP7021 Pin Controller Driver. 4*aa74c44bSWells Lu * Copyright (C) Sunplus Tech / Tibbo Tech. 5*aa74c44bSWells Lu */ 6*aa74c44bSWells Lu 7*aa74c44bSWells Lu #include <linux/gpio/driver.h> 8*aa74c44bSWells Lu #include <linux/kernel.h> 9*aa74c44bSWells Lu #include <linux/pinctrl/pinctrl.h> 10*aa74c44bSWells Lu 11*aa74c44bSWells Lu #include "sppctl.h" 12*aa74c44bSWells Lu 13*aa74c44bSWells Lu #define D_PIS(x, y) "P" __stringify(x) "_0" __stringify(y) 14*aa74c44bSWells Lu #define D(x, y) ((x) * 8 + (y)) 15*aa74c44bSWells Lu #define P(x, y) PINCTRL_PIN(D(x, y), D_PIS(x, y)) 16*aa74c44bSWells Lu 17*aa74c44bSWells Lu const char * const sppctl_gpio_list_s[] = { 18*aa74c44bSWells Lu D_PIS(0, 0), D_PIS(0, 1), D_PIS(0, 2), D_PIS(0, 3), 19*aa74c44bSWells Lu D_PIS(0, 4), D_PIS(0, 5), D_PIS(0, 6), D_PIS(0, 7), 20*aa74c44bSWells Lu D_PIS(1, 0), D_PIS(1, 1), D_PIS(1, 2), D_PIS(1, 3), 21*aa74c44bSWells Lu D_PIS(1, 4), D_PIS(1, 5), D_PIS(1, 6), D_PIS(1, 7), 22*aa74c44bSWells Lu D_PIS(2, 0), D_PIS(2, 1), D_PIS(2, 2), D_PIS(2, 3), 23*aa74c44bSWells Lu D_PIS(2, 4), D_PIS(2, 5), D_PIS(2, 6), D_PIS(2, 7), 24*aa74c44bSWells Lu D_PIS(3, 0), D_PIS(3, 1), D_PIS(3, 2), D_PIS(3, 3), 25*aa74c44bSWells Lu D_PIS(3, 4), D_PIS(3, 5), D_PIS(3, 6), D_PIS(3, 7), 26*aa74c44bSWells Lu D_PIS(4, 0), D_PIS(4, 1), D_PIS(4, 2), D_PIS(4, 3), 27*aa74c44bSWells Lu D_PIS(4, 4), D_PIS(4, 5), D_PIS(4, 6), D_PIS(4, 7), 28*aa74c44bSWells Lu D_PIS(5, 0), D_PIS(5, 1), D_PIS(5, 2), D_PIS(5, 3), 29*aa74c44bSWells Lu D_PIS(5, 4), D_PIS(5, 5), D_PIS(5, 6), D_PIS(5, 7), 30*aa74c44bSWells Lu D_PIS(6, 0), D_PIS(6, 1), D_PIS(6, 2), D_PIS(6, 3), 31*aa74c44bSWells Lu D_PIS(6, 4), D_PIS(6, 5), D_PIS(6, 6), D_PIS(6, 7), 32*aa74c44bSWells Lu D_PIS(7, 0), D_PIS(7, 1), D_PIS(7, 2), D_PIS(7, 3), 33*aa74c44bSWells Lu D_PIS(7, 4), D_PIS(7, 5), D_PIS(7, 6), D_PIS(7, 7), 34*aa74c44bSWells Lu D_PIS(8, 0), D_PIS(8, 1), D_PIS(8, 2), D_PIS(8, 3), 35*aa74c44bSWells Lu D_PIS(8, 4), D_PIS(8, 5), D_PIS(8, 6), D_PIS(8, 7), 36*aa74c44bSWells Lu D_PIS(9, 0), D_PIS(9, 1), D_PIS(9, 2), D_PIS(9, 3), 37*aa74c44bSWells Lu D_PIS(9, 4), D_PIS(9, 5), D_PIS(9, 6), D_PIS(9, 7), 38*aa74c44bSWells Lu D_PIS(10, 0), D_PIS(10, 1), D_PIS(10, 2), D_PIS(10, 3), 39*aa74c44bSWells Lu D_PIS(10, 4), D_PIS(10, 5), D_PIS(10, 6), D_PIS(10, 7), 40*aa74c44bSWells Lu D_PIS(11, 0), D_PIS(11, 1), D_PIS(11, 2), D_PIS(11, 3), 41*aa74c44bSWells Lu D_PIS(11, 4), D_PIS(11, 5), D_PIS(11, 6), D_PIS(11, 7), 42*aa74c44bSWells Lu D_PIS(12, 0), D_PIS(12, 1), D_PIS(12, 2), 43*aa74c44bSWells Lu }; 44*aa74c44bSWells Lu 45*aa74c44bSWells Lu const size_t sppctl_gpio_list_sz = ARRAY_SIZE(sppctl_gpio_list_s); 46*aa74c44bSWells Lu 47*aa74c44bSWells Lu const unsigned int sppctl_pins_gpio[] = { 48*aa74c44bSWells Lu D(0, 0), D(0, 1), D(0, 2), D(0, 3), D(0, 4), D(0, 5), D(0, 6), D(0, 7), 49*aa74c44bSWells Lu D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), D(1, 6), D(1, 7), 50*aa74c44bSWells Lu D(2, 0), D(2, 1), D(2, 2), D(2, 3), D(2, 4), D(2, 5), D(2, 6), D(2, 7), 51*aa74c44bSWells Lu D(3, 0), D(3, 1), D(3, 2), D(3, 3), D(3, 4), D(3, 5), D(3, 6), D(3, 7), 52*aa74c44bSWells Lu D(4, 0), D(4, 1), D(4, 2), D(4, 3), D(4, 4), D(4, 5), D(4, 6), D(4, 7), 53*aa74c44bSWells Lu D(5, 0), D(5, 1), D(5, 2), D(5, 3), D(5, 4), D(5, 5), D(5, 6), D(5, 7), 54*aa74c44bSWells Lu D(6, 0), D(6, 1), D(6, 2), D(6, 3), D(6, 4), D(6, 5), D(6, 6), D(6, 7), 55*aa74c44bSWells Lu D(7, 0), D(7, 1), D(7, 2), D(7, 3), D(7, 4), D(7, 5), D(7, 6), D(7, 7), 56*aa74c44bSWells Lu D(8, 0), D(8, 1), D(8, 2), D(8, 3), D(8, 4), D(8, 5), D(8, 6), D(8, 7), 57*aa74c44bSWells Lu D(9, 0), D(9, 1), D(9, 2), D(9, 3), D(9, 4), D(9, 5), D(9, 6), D(9, 7), 58*aa74c44bSWells Lu D(10, 0), D(10, 1), D(10, 2), D(10, 3), D(10, 4), D(10, 5), D(10, 6), D(10, 7), 59*aa74c44bSWells Lu D(11, 0), D(11, 1), D(11, 2), D(11, 3), D(11, 4), D(11, 5), D(11, 6), D(11, 7), 60*aa74c44bSWells Lu D(12, 0), D(12, 1), D(12, 2), 61*aa74c44bSWells Lu }; 62*aa74c44bSWells Lu 63*aa74c44bSWells Lu const struct pinctrl_pin_desc sppctl_pins_all[] = { 64*aa74c44bSWells Lu /* gpio and iop only */ 65*aa74c44bSWells Lu P(0, 0), P(0, 1), P(0, 2), P(0, 3), P(0, 4), P(0, 5), P(0, 6), P(0, 7), 66*aa74c44bSWells Lu /* gpio, iop, muxable */ 67*aa74c44bSWells Lu P(1, 0), P(1, 1), P(1, 2), P(1, 3), P(1, 4), P(1, 5), P(1, 6), P(1, 7), 68*aa74c44bSWells Lu P(2, 0), P(2, 1), P(2, 2), P(2, 3), P(2, 4), P(2, 5), P(2, 6), P(2, 7), 69*aa74c44bSWells Lu P(3, 0), P(3, 1), P(3, 2), P(3, 3), P(3, 4), P(3, 5), P(3, 6), P(3, 7), 70*aa74c44bSWells Lu P(4, 0), P(4, 1), P(4, 2), P(4, 3), P(4, 4), P(4, 5), P(4, 6), P(4, 7), 71*aa74c44bSWells Lu P(5, 0), P(5, 1), P(5, 2), P(5, 3), P(5, 4), P(5, 5), P(5, 6), P(5, 7), 72*aa74c44bSWells Lu P(6, 0), P(6, 1), P(6, 2), P(6, 3), P(6, 4), P(6, 5), P(6, 6), P(6, 7), 73*aa74c44bSWells Lu P(7, 0), P(7, 1), P(7, 2), P(7, 3), P(7, 4), P(7, 5), P(7, 6), P(7, 7), 74*aa74c44bSWells Lu P(8, 0), P(8, 1), P(8, 2), P(8, 3), P(8, 4), P(8, 5), P(8, 6), P(8, 7), 75*aa74c44bSWells Lu /* gpio and iop only */ 76*aa74c44bSWells Lu P(9, 0), P(9, 1), P(9, 2), P(9, 3), P(9, 4), P(9, 5), P(9, 6), P(9, 7), 77*aa74c44bSWells Lu P(10, 0), P(10, 1), P(10, 2), P(10, 3), P(10, 4), P(10, 5), P(10, 6), P(10, 7), 78*aa74c44bSWells Lu P(11, 0), P(11, 1), P(11, 2), P(11, 3), P(11, 4), P(11, 5), P(11, 6), P(11, 7), 79*aa74c44bSWells Lu P(12, 0), P(12, 1), P(12, 2), 80*aa74c44bSWells Lu }; 81*aa74c44bSWells Lu 82*aa74c44bSWells Lu const size_t sppctl_pins_all_sz = ARRAY_SIZE(sppctl_pins_all); 83*aa74c44bSWells Lu 84*aa74c44bSWells Lu const char * const sppctl_pmux_list_s[] = { 85*aa74c44bSWells Lu D_PIS(0, 0), 86*aa74c44bSWells Lu D_PIS(1, 0), D_PIS(1, 1), D_PIS(1, 2), D_PIS(1, 3), 87*aa74c44bSWells Lu D_PIS(1, 4), D_PIS(1, 5), D_PIS(1, 6), D_PIS(1, 7), 88*aa74c44bSWells Lu D_PIS(2, 0), D_PIS(2, 1), D_PIS(2, 2), D_PIS(2, 3), 89*aa74c44bSWells Lu D_PIS(2, 4), D_PIS(2, 5), D_PIS(2, 6), D_PIS(2, 7), 90*aa74c44bSWells Lu D_PIS(3, 0), D_PIS(3, 1), D_PIS(3, 2), D_PIS(3, 3), 91*aa74c44bSWells Lu D_PIS(3, 4), D_PIS(3, 5), D_PIS(3, 6), D_PIS(3, 7), 92*aa74c44bSWells Lu D_PIS(4, 0), D_PIS(4, 1), D_PIS(4, 2), D_PIS(4, 3), 93*aa74c44bSWells Lu D_PIS(4, 4), D_PIS(4, 5), D_PIS(4, 6), D_PIS(4, 7), 94*aa74c44bSWells Lu D_PIS(5, 0), D_PIS(5, 1), D_PIS(5, 2), D_PIS(5, 3), 95*aa74c44bSWells Lu D_PIS(5, 4), D_PIS(5, 5), D_PIS(5, 6), D_PIS(5, 7), 96*aa74c44bSWells Lu D_PIS(6, 0), D_PIS(6, 1), D_PIS(6, 2), D_PIS(6, 3), 97*aa74c44bSWells Lu D_PIS(6, 4), D_PIS(6, 5), D_PIS(6, 6), D_PIS(6, 7), 98*aa74c44bSWells Lu D_PIS(7, 0), D_PIS(7, 1), D_PIS(7, 2), D_PIS(7, 3), 99*aa74c44bSWells Lu D_PIS(7, 4), D_PIS(7, 5), D_PIS(7, 6), D_PIS(7, 7), 100*aa74c44bSWells Lu D_PIS(8, 0), D_PIS(8, 1), D_PIS(8, 2), D_PIS(8, 3), 101*aa74c44bSWells Lu D_PIS(8, 4), D_PIS(8, 5), D_PIS(8, 6), D_PIS(8, 7), 102*aa74c44bSWells Lu }; 103*aa74c44bSWells Lu 104*aa74c44bSWells Lu const size_t sppctl_pmux_list_sz = ARRAY_SIZE(sppctl_pmux_list_s); 105*aa74c44bSWells Lu 106*aa74c44bSWells Lu static const unsigned int pins_spif1[] = { 107*aa74c44bSWells Lu D(10, 3), D(10, 4), D(10, 6), D(10, 7), 108*aa74c44bSWells Lu }; 109*aa74c44bSWells Lu 110*aa74c44bSWells Lu static const unsigned int pins_spif2[] = { 111*aa74c44bSWells Lu D(9, 4), D(9, 6), D(9, 7), D(10, 1), 112*aa74c44bSWells Lu }; 113*aa74c44bSWells Lu 114*aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_spif[] = { 115*aa74c44bSWells Lu EGRP("SPI_FLASH1", 1, pins_spif1), 116*aa74c44bSWells Lu EGRP("SPI_FLASH2", 2, pins_spif2), 117*aa74c44bSWells Lu }; 118*aa74c44bSWells Lu 119*aa74c44bSWells Lu static const unsigned int pins_spi41[] = { 120*aa74c44bSWells Lu D(10, 2), D(10, 5), 121*aa74c44bSWells Lu }; 122*aa74c44bSWells Lu 123*aa74c44bSWells Lu static const unsigned int pins_spi42[] = { 124*aa74c44bSWells Lu D(9, 5), D(9, 8), 125*aa74c44bSWells Lu }; 126*aa74c44bSWells Lu 127*aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_spi4[] = { 128*aa74c44bSWells Lu EGRP("SPI_FLASH_4BIT1", 1, pins_spi41), 129*aa74c44bSWells Lu EGRP("SPI_FLASH_4BIT2", 2, pins_spi42), 130*aa74c44bSWells Lu }; 131*aa74c44bSWells Lu 132*aa74c44bSWells Lu static const unsigned int pins_snan[] = { 133*aa74c44bSWells Lu D(9, 4), D(9, 5), D(9, 6), D(9, 7), D(10, 0), D(10, 1), 134*aa74c44bSWells Lu }; 135*aa74c44bSWells Lu 136*aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_snan[] = { 137*aa74c44bSWells Lu EGRP("SPI_NAND", 1, pins_snan), 138*aa74c44bSWells Lu }; 139*aa74c44bSWells Lu 140*aa74c44bSWells Lu static const unsigned int pins_emmc[] = { 141*aa74c44bSWells Lu D(9, 0), D(9, 1), D(9, 2), D(9, 3), D(9, 4), D(9, 5), 142*aa74c44bSWells Lu D(9, 6), D(9, 7), D(10, 0), D(10, 1), 143*aa74c44bSWells Lu }; 144*aa74c44bSWells Lu 145*aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_emmc[] = { 146*aa74c44bSWells Lu EGRP("CARD0_EMMC", 1, pins_emmc), 147*aa74c44bSWells Lu }; 148*aa74c44bSWells Lu 149*aa74c44bSWells Lu static const unsigned int pins_sdsd[] = { 150*aa74c44bSWells Lu D(8, 1), D(8, 2), D(8, 3), D(8, 4), D(8, 5), D(8, 6), 151*aa74c44bSWells Lu }; 152*aa74c44bSWells Lu 153*aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_sdsd[] = { 154*aa74c44bSWells Lu EGRP("SD_CARD", 1, pins_sdsd), 155*aa74c44bSWells Lu }; 156*aa74c44bSWells Lu 157*aa74c44bSWells Lu static const unsigned int pins_uar0[] = { 158*aa74c44bSWells Lu D(11, 0), D(11, 1), 159*aa74c44bSWells Lu }; 160*aa74c44bSWells Lu 161*aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_uar0[] = { 162*aa74c44bSWells Lu EGRP("UA0", 1, pins_uar0), 163*aa74c44bSWells Lu }; 164*aa74c44bSWells Lu 165*aa74c44bSWells Lu static const unsigned int pins_adbg1[] = { 166*aa74c44bSWells Lu D(10, 2), D(10, 3), 167*aa74c44bSWells Lu }; 168*aa74c44bSWells Lu 169*aa74c44bSWells Lu static const unsigned int pins_adbg2[] = { 170*aa74c44bSWells Lu D(7, 1), D(7, 2), 171*aa74c44bSWells Lu }; 172*aa74c44bSWells Lu 173*aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_adbg[] = { 174*aa74c44bSWells Lu EGRP("ACHIP_DEBUG1", 1, pins_adbg1), 175*aa74c44bSWells Lu EGRP("ACHIP_DEBUG2", 2, pins_adbg2), 176*aa74c44bSWells Lu }; 177*aa74c44bSWells Lu 178*aa74c44bSWells Lu static const unsigned int pins_aua2axi1[] = { 179*aa74c44bSWells Lu D(2, 0), D(2, 1), D(2, 2), 180*aa74c44bSWells Lu }; 181*aa74c44bSWells Lu 182*aa74c44bSWells Lu static const unsigned int pins_aua2axi2[] = { 183*aa74c44bSWells Lu D(1, 0), D(1, 1), D(1, 2), 184*aa74c44bSWells Lu }; 185*aa74c44bSWells Lu 186*aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_au2x[] = { 187*aa74c44bSWells Lu EGRP("ACHIP_UA2AXI1", 1, pins_aua2axi1), 188*aa74c44bSWells Lu EGRP("ACHIP_UA2AXI2", 2, pins_aua2axi2), 189*aa74c44bSWells Lu }; 190*aa74c44bSWells Lu 191*aa74c44bSWells Lu static const unsigned int pins_fpga[] = { 192*aa74c44bSWells Lu D(0, 2), D(0, 3), D(0, 4), D(0, 5), D(0, 6), D(0, 7), 193*aa74c44bSWells Lu D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), 194*aa74c44bSWells Lu D(1, 6), D(1, 7), D(2, 0), D(2, 1), D(2, 2), D(2, 3), 195*aa74c44bSWells Lu D(2, 4), D(2, 5), D(2, 6), D(2, 7), D(3, 0), D(3, 1), 196*aa74c44bSWells Lu D(3, 2), D(3, 3), D(3, 4), D(3, 5), D(3, 6), D(3, 7), 197*aa74c44bSWells Lu D(4, 0), D(4, 1), D(4, 2), D(4, 3), D(4, 4), D(4, 5), 198*aa74c44bSWells Lu D(4, 6), D(4, 7), D(5, 0), D(5, 1), D(5, 2), 199*aa74c44bSWells Lu }; 200*aa74c44bSWells Lu 201*aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_fpga[] = { 202*aa74c44bSWells Lu EGRP("FPGA_IFX", 1, pins_fpga), 203*aa74c44bSWells Lu }; 204*aa74c44bSWells Lu 205*aa74c44bSWells Lu static const unsigned int pins_hdmi1[] = { 206*aa74c44bSWells Lu D(10, 6), D(12, 2), D(12, 1), 207*aa74c44bSWells Lu }; 208*aa74c44bSWells Lu 209*aa74c44bSWells Lu static const unsigned int pins_hdmi2[] = { 210*aa74c44bSWells Lu D(8, 3), D(8, 5), D(8, 6), 211*aa74c44bSWells Lu }; 212*aa74c44bSWells Lu 213*aa74c44bSWells Lu static const unsigned int pins_hdmi3[] = { 214*aa74c44bSWells Lu D(7, 4), D(7, 6), D(7, 7), 215*aa74c44bSWells Lu }; 216*aa74c44bSWells Lu 217*aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_hdmi[] = { 218*aa74c44bSWells Lu EGRP("HDMI_TX1", 1, pins_hdmi1), 219*aa74c44bSWells Lu EGRP("HDMI_TX2", 2, pins_hdmi2), 220*aa74c44bSWells Lu EGRP("HDMI_TX3", 3, pins_hdmi3), 221*aa74c44bSWells Lu }; 222*aa74c44bSWells Lu 223*aa74c44bSWells Lu static const unsigned int pins_eadc[] = { 224*aa74c44bSWells Lu D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), D(1, 6), 225*aa74c44bSWells Lu }; 226*aa74c44bSWells Lu 227*aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_eadc[] = { 228*aa74c44bSWells Lu EGRP("AUD_EXT_ADC_IFX0", 1, pins_eadc), 229*aa74c44bSWells Lu }; 230*aa74c44bSWells Lu 231*aa74c44bSWells Lu static const unsigned int pins_edac[] = { 232*aa74c44bSWells Lu D(2, 5), D(2, 6), D(2, 7), D(3, 0), D(3, 1), D(3, 2), D(3, 4), 233*aa74c44bSWells Lu }; 234*aa74c44bSWells Lu 235*aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_edac[] = { 236*aa74c44bSWells Lu EGRP("AUD_EXT_DAC_IFX0", 1, pins_edac), 237*aa74c44bSWells Lu }; 238*aa74c44bSWells Lu 239*aa74c44bSWells Lu static const unsigned int pins_spdi[] = { 240*aa74c44bSWells Lu D(2, 4), 241*aa74c44bSWells Lu }; 242*aa74c44bSWells Lu 243*aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_spdi[] = { 244*aa74c44bSWells Lu EGRP("AUD_IEC_RX0", 1, pins_spdi), 245*aa74c44bSWells Lu }; 246*aa74c44bSWells Lu 247*aa74c44bSWells Lu static const unsigned int pins_spdo[] = { 248*aa74c44bSWells Lu D(3, 6), 249*aa74c44bSWells Lu }; 250*aa74c44bSWells Lu 251*aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_spdo[] = { 252*aa74c44bSWells Lu EGRP("AUD_IEC_TX0", 1, pins_spdo), 253*aa74c44bSWells Lu }; 254*aa74c44bSWells Lu 255*aa74c44bSWells Lu static const unsigned int pins_tdmt[] = { 256*aa74c44bSWells Lu D(2, 5), D(2, 6), D(2, 7), D(3, 0), D(3, 1), D(3, 2), 257*aa74c44bSWells Lu }; 258*aa74c44bSWells Lu 259*aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_tdmt[] = { 260*aa74c44bSWells Lu EGRP("TDMTX_IFX0", 1, pins_tdmt), 261*aa74c44bSWells Lu }; 262*aa74c44bSWells Lu 263*aa74c44bSWells Lu static const unsigned int pins_tdmr[] = { 264*aa74c44bSWells Lu D(1, 7), D(2, 0), D(2, 1), D(2, 2), 265*aa74c44bSWells Lu }; 266*aa74c44bSWells Lu 267*aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_tdmr[] = { 268*aa74c44bSWells Lu EGRP("TDMRX_IFX0", 1, pins_tdmr), 269*aa74c44bSWells Lu }; 270*aa74c44bSWells Lu 271*aa74c44bSWells Lu static const unsigned int pins_pdmr[] = { 272*aa74c44bSWells Lu D(1, 7), D(2, 0), D(2, 1), D(2, 2), D(2, 3), 273*aa74c44bSWells Lu }; 274*aa74c44bSWells Lu 275*aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_pdmr[] = { 276*aa74c44bSWells Lu EGRP("PDMRX_IFX0", 1, pins_pdmr), 277*aa74c44bSWells Lu }; 278*aa74c44bSWells Lu 279*aa74c44bSWells Lu static const unsigned int pins_pcmt[] = { 280*aa74c44bSWells Lu D(3, 7), D(4, 0), D(4, 1), D(4, 2), D(4, 3), D(4, 4), 281*aa74c44bSWells Lu }; 282*aa74c44bSWells Lu 283*aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_pcmt[] = { 284*aa74c44bSWells Lu EGRP("PCM_IEC_TX", 1, pins_pcmt), 285*aa74c44bSWells Lu }; 286*aa74c44bSWells Lu 287*aa74c44bSWells Lu static const unsigned int pins_lcdi[] = { 288*aa74c44bSWells Lu D(1, 4), D(1, 5), D(1, 6), D(1, 7), D(2, 0), D(2, 1), D(2, 2), D(2, 3), 289*aa74c44bSWells Lu D(2, 4), D(2, 5), D(2, 6), D(2, 7), D(3, 0), D(3, 1), D(3, 2), D(3, 3), 290*aa74c44bSWells Lu D(3, 4), D(3, 5), D(3, 6), D(3, 7), D(4, 0), D(4, 1), D(4, 2), D(4, 3), 291*aa74c44bSWells Lu D(4, 4), D(4, 5), D(4, 6), D(4, 7), 292*aa74c44bSWells Lu }; 293*aa74c44bSWells Lu 294*aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_lcdi[] = { 295*aa74c44bSWells Lu EGRP("LCDIF", 1, pins_lcdi), 296*aa74c44bSWells Lu }; 297*aa74c44bSWells Lu 298*aa74c44bSWells Lu static const unsigned int pins_dvdd[] = { 299*aa74c44bSWells Lu D(7, 0), D(7, 1), D(7, 2), D(7, 3), D(7, 4), D(7, 5), D(7, 6), D(7, 7), 300*aa74c44bSWells Lu D(8, 0), D(8, 1), D(8, 2), D(8, 3), D(8, 4), D(8, 5), 301*aa74c44bSWells Lu }; 302*aa74c44bSWells Lu 303*aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_dvdd[] = { 304*aa74c44bSWells Lu EGRP("DVD_DSP_DEBUG", 1, pins_dvdd), 305*aa74c44bSWells Lu }; 306*aa74c44bSWells Lu 307*aa74c44bSWells Lu static const unsigned int pins_i2cd[] = { 308*aa74c44bSWells Lu D(1, 0), D(1, 1), 309*aa74c44bSWells Lu }; 310*aa74c44bSWells Lu 311*aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_i2cd[] = { 312*aa74c44bSWells Lu EGRP("I2C_DEBUG", 1, pins_i2cd), 313*aa74c44bSWells Lu }; 314*aa74c44bSWells Lu 315*aa74c44bSWells Lu static const unsigned int pins_i2cs[] = { 316*aa74c44bSWells Lu D(0, 0), D(0, 1), 317*aa74c44bSWells Lu }; 318*aa74c44bSWells Lu 319*aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_i2cs[] = { 320*aa74c44bSWells Lu EGRP("I2C_SLAVE", 1, pins_i2cs), 321*aa74c44bSWells Lu }; 322*aa74c44bSWells Lu 323*aa74c44bSWells Lu static const unsigned int pins_wakp[] = { 324*aa74c44bSWells Lu D(10, 5), 325*aa74c44bSWells Lu }; 326*aa74c44bSWells Lu 327*aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_wakp[] = { 328*aa74c44bSWells Lu EGRP("WAKEUP", 1, pins_wakp), 329*aa74c44bSWells Lu }; 330*aa74c44bSWells Lu 331*aa74c44bSWells Lu static const unsigned int pins_u2ax[] = { 332*aa74c44bSWells Lu D(2, 0), D(2, 1), D(3, 0), D(3, 1), 333*aa74c44bSWells Lu }; 334*aa74c44bSWells Lu 335*aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_u2ax[] = { 336*aa74c44bSWells Lu EGRP("UART2AXI", 1, pins_u2ax), 337*aa74c44bSWells Lu }; 338*aa74c44bSWells Lu 339*aa74c44bSWells Lu static const unsigned int pins_u0ic[] = { 340*aa74c44bSWells Lu D(0, 0), D(0, 1), D(0, 4), D(0, 5), D(1, 0), D(1, 1), 341*aa74c44bSWells Lu }; 342*aa74c44bSWells Lu 343*aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_u0ic[] = { 344*aa74c44bSWells Lu EGRP("USB0_I2C", 1, pins_u0ic), 345*aa74c44bSWells Lu }; 346*aa74c44bSWells Lu 347*aa74c44bSWells Lu static const unsigned int pins_u1ic[] = { 348*aa74c44bSWells Lu D(0, 2), D(0, 3), D(0, 6), D(0, 7), D(1, 2), D(1, 3), 349*aa74c44bSWells Lu }; 350*aa74c44bSWells Lu 351*aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_u1ic[] = { 352*aa74c44bSWells Lu EGRP("USB1_I2C", 1, pins_u1ic), 353*aa74c44bSWells Lu }; 354*aa74c44bSWells Lu 355*aa74c44bSWells Lu static const unsigned int pins_u0ot[] = { 356*aa74c44bSWells Lu D(11, 2), 357*aa74c44bSWells Lu }; 358*aa74c44bSWells Lu 359*aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_u0ot[] = { 360*aa74c44bSWells Lu EGRP("USB0_OTG", 1, pins_u0ot), 361*aa74c44bSWells Lu }; 362*aa74c44bSWells Lu 363*aa74c44bSWells Lu static const unsigned int pins_u1ot[] = { 364*aa74c44bSWells Lu D(11, 3), 365*aa74c44bSWells Lu }; 366*aa74c44bSWells Lu 367*aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_u1ot[] = { 368*aa74c44bSWells Lu EGRP("USB1_OTG", 1, pins_u1ot), 369*aa74c44bSWells Lu }; 370*aa74c44bSWells Lu 371*aa74c44bSWells Lu static const unsigned int pins_uphd[] = { 372*aa74c44bSWells Lu D(0, 1), D(0, 2), D(0, 3), D(7, 4), D(7, 5), D(7, 6), 373*aa74c44bSWells Lu D(7, 7), D(8, 0), D(8, 1), D(8, 2), D(8, 3), 374*aa74c44bSWells Lu D(9, 7), D(10, 2), D(10, 3), D(10, 4), 375*aa74c44bSWells Lu }; 376*aa74c44bSWells Lu 377*aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_up0d[] = { 378*aa74c44bSWells Lu EGRP("UPHY0_DEBUG", 1, pins_uphd), 379*aa74c44bSWells Lu }; 380*aa74c44bSWells Lu 381*aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_up1d[] = { 382*aa74c44bSWells Lu EGRP("UPHY1_DEBUG", 1, pins_uphd), 383*aa74c44bSWells Lu }; 384*aa74c44bSWells Lu 385*aa74c44bSWells Lu static const unsigned int pins_upex[] = { 386*aa74c44bSWells Lu D(0, 0), D(0, 1), D(0, 2), D(0, 3), D(0, 4), D(0, 5), D(0, 6), D(0, 7), 387*aa74c44bSWells Lu D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), D(1, 6), D(1, 7), 388*aa74c44bSWells Lu D(2, 0), D(2, 1), D(2, 2), D(2, 3), D(2, 4), D(2, 5), D(2, 6), D(2, 7), 389*aa74c44bSWells Lu D(3, 0), D(3, 1), D(3, 2), D(3, 3), D(3, 4), D(3, 5), D(3, 6), D(3, 7), 390*aa74c44bSWells Lu D(4, 0), D(4, 1), D(4, 2), D(4, 3), D(4, 4), D(4, 5), D(4, 6), D(4, 7), 391*aa74c44bSWells Lu D(5, 0), D(5, 1), D(5, 2), D(5, 3), D(5, 4), D(5, 5), D(5, 6), D(5, 7), 392*aa74c44bSWells Lu D(6, 0), D(6, 1), D(6, 2), D(6, 3), D(6, 4), D(6, 5), D(6, 6), D(6, 7), 393*aa74c44bSWells Lu D(7, 0), D(7, 1), D(7, 2), D(7, 3), D(7, 4), D(7, 5), D(7, 6), D(7, 7), 394*aa74c44bSWells Lu D(8, 0), D(8, 1), D(8, 2), D(8, 3), D(8, 4), D(8, 5), D(8, 6), D(8, 7), 395*aa74c44bSWells Lu D(9, 0), D(9, 1), D(9, 2), D(9, 3), D(9, 4), D(9, 5), D(9, 6), D(9, 7), 396*aa74c44bSWells Lu D(10, 0), D(10, 1), D(10, 2), D(10, 3), D(10, 4), D(10, 5), D(10, 6), D(10, 7), 397*aa74c44bSWells Lu }; 398*aa74c44bSWells Lu 399*aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_upex[] = { 400*aa74c44bSWells Lu EGRP("UPHY0_EXT", 1, pins_upex), 401*aa74c44bSWells Lu }; 402*aa74c44bSWells Lu 403*aa74c44bSWells Lu static const unsigned int pins_prp1[] = { 404*aa74c44bSWells Lu D(0, 6), D(0, 7), 405*aa74c44bSWells Lu D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), D(1, 6), D(1, 7), 406*aa74c44bSWells Lu D(2, 1), D(2, 2), D(2, 3), D(2, 4), D(2, 5), D(2, 6), D(2, 7), 407*aa74c44bSWells Lu D(3, 0), D(3, 1), D(3, 2), 408*aa74c44bSWells Lu }; 409*aa74c44bSWells Lu 410*aa74c44bSWells Lu static const unsigned int pins_prp2[] = { 411*aa74c44bSWells Lu D(3, 4), D(3, 6), D(3, 7), 412*aa74c44bSWells Lu D(4, 0), D(4, 1), D(4, 2), D(4, 3), D(4, 4), D(4, 5), D(4, 6), D(4, 7), 413*aa74c44bSWells Lu D(5, 0), D(5, 1), D(5, 2), D(5, 3), D(5, 4), D(5, 5), D(5, 6), D(5, 7), 414*aa74c44bSWells Lu D(6, 4), 415*aa74c44bSWells Lu }; 416*aa74c44bSWells Lu 417*aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_prbp[] = { 418*aa74c44bSWells Lu EGRP("PROBE_PORT1", 1, pins_prp1), 419*aa74c44bSWells Lu EGRP("PROBE_PORT2", 2, pins_prp2), 420*aa74c44bSWells Lu }; 421*aa74c44bSWells Lu 422*aa74c44bSWells Lu const struct sppctl_func sppctl_list_funcs[] = { 423*aa74c44bSWells Lu FNCN("L2SW_CLK_OUT", pinmux_type_fpmx, 0x00, 0, 7), 424*aa74c44bSWells Lu FNCN("L2SW_MAC_SMI_MDC", pinmux_type_fpmx, 0x00, 8, 7), 425*aa74c44bSWells Lu FNCN("L2SW_LED_FLASH0", pinmux_type_fpmx, 0x01, 0, 7), 426*aa74c44bSWells Lu FNCN("L2SW_LED_FLASH1", pinmux_type_fpmx, 0x01, 8, 7), 427*aa74c44bSWells Lu FNCN("L2SW_LED_ON0", pinmux_type_fpmx, 0x02, 0, 7), 428*aa74c44bSWells Lu FNCN("L2SW_LED_ON1", pinmux_type_fpmx, 0x02, 8, 7), 429*aa74c44bSWells Lu FNCN("L2SW_MAC_SMI_MDIO", pinmux_type_fpmx, 0x03, 0, 7), 430*aa74c44bSWells Lu FNCN("L2SW_P0_MAC_RMII_TXEN", pinmux_type_fpmx, 0x03, 8, 7), 431*aa74c44bSWells Lu FNCN("L2SW_P0_MAC_RMII_TXD0", pinmux_type_fpmx, 0x04, 0, 7), 432*aa74c44bSWells Lu FNCN("L2SW_P0_MAC_RMII_TXD1", pinmux_type_fpmx, 0x04, 8, 7), 433*aa74c44bSWells Lu FNCN("L2SW_P0_MAC_RMII_CRSDV", pinmux_type_fpmx, 0x05, 0, 7), 434*aa74c44bSWells Lu FNCN("L2SW_P0_MAC_RMII_RXD0", pinmux_type_fpmx, 0x05, 8, 7), 435*aa74c44bSWells Lu FNCN("L2SW_P0_MAC_RMII_RXD1", pinmux_type_fpmx, 0x06, 0, 7), 436*aa74c44bSWells Lu FNCN("L2SW_P0_MAC_RMII_RXER", pinmux_type_fpmx, 0x06, 8, 7), 437*aa74c44bSWells Lu FNCN("L2SW_P1_MAC_RMII_TXEN", pinmux_type_fpmx, 0x07, 0, 7), 438*aa74c44bSWells Lu FNCN("L2SW_P1_MAC_RMII_TXD0", pinmux_type_fpmx, 0x07, 8, 7), 439*aa74c44bSWells Lu FNCN("L2SW_P1_MAC_RMII_TXD1", pinmux_type_fpmx, 0x08, 0, 7), 440*aa74c44bSWells Lu FNCN("L2SW_P1_MAC_RMII_CRSDV", pinmux_type_fpmx, 0x08, 8, 7), 441*aa74c44bSWells Lu FNCN("L2SW_P1_MAC_RMII_RXD0", pinmux_type_fpmx, 0x09, 0, 7), 442*aa74c44bSWells Lu FNCN("L2SW_P1_MAC_RMII_RXD1", pinmux_type_fpmx, 0x09, 8, 7), 443*aa74c44bSWells Lu FNCN("L2SW_P1_MAC_RMII_RXER", pinmux_type_fpmx, 0x0A, 0, 7), 444*aa74c44bSWells Lu FNCN("DAISY_MODE", pinmux_type_fpmx, 0x0A, 8, 7), 445*aa74c44bSWells Lu FNCN("SDIO_CLK", pinmux_type_fpmx, 0x0B, 0, 7), /* 1x SDIO */ 446*aa74c44bSWells Lu FNCN("SDIO_CMD", pinmux_type_fpmx, 0x0B, 8, 7), 447*aa74c44bSWells Lu FNCN("SDIO_D0", pinmux_type_fpmx, 0x0C, 0, 7), 448*aa74c44bSWells Lu FNCN("SDIO_D1", pinmux_type_fpmx, 0x0C, 8, 7), 449*aa74c44bSWells Lu FNCN("SDIO_D2", pinmux_type_fpmx, 0x0D, 0, 7), 450*aa74c44bSWells Lu FNCN("SDIO_D3", pinmux_type_fpmx, 0x0D, 8, 7), 451*aa74c44bSWells Lu FNCN("PWM0", pinmux_type_fpmx, 0x0E, 0, 7), /* 8x PWM */ 452*aa74c44bSWells Lu FNCN("PWM1", pinmux_type_fpmx, 0x0E, 8, 7), 453*aa74c44bSWells Lu FNCN("PWM2", pinmux_type_fpmx, 0x0F, 0, 7), 454*aa74c44bSWells Lu FNCN("PWM3", pinmux_type_fpmx, 0x0F, 8, 7), 455*aa74c44bSWells Lu 456*aa74c44bSWells Lu FNCN("PWM4", pinmux_type_fpmx, 0x10, 0, 7), 457*aa74c44bSWells Lu FNCN("PWM5", pinmux_type_fpmx, 0x10, 8, 7), 458*aa74c44bSWells Lu FNCN("PWM6", pinmux_type_fpmx, 0x11, 0, 7), 459*aa74c44bSWells Lu FNCN("PWM7", pinmux_type_fpmx, 0x11, 8, 7), 460*aa74c44bSWells Lu FNCN("ICM0_D", pinmux_type_fpmx, 0x12, 0, 7), /* 4x Input captures */ 461*aa74c44bSWells Lu FNCN("ICM1_D", pinmux_type_fpmx, 0x12, 8, 7), 462*aa74c44bSWells Lu FNCN("ICM2_D", pinmux_type_fpmx, 0x13, 0, 7), 463*aa74c44bSWells Lu FNCN("ICM3_D", pinmux_type_fpmx, 0x13, 8, 7), 464*aa74c44bSWells Lu FNCN("ICM0_CLK", pinmux_type_fpmx, 0x14, 0, 7), 465*aa74c44bSWells Lu FNCN("ICM1_CLK", pinmux_type_fpmx, 0x14, 8, 7), 466*aa74c44bSWells Lu FNCN("ICM2_CLK", pinmux_type_fpmx, 0x15, 0, 7), 467*aa74c44bSWells Lu FNCN("ICM3_CLK", pinmux_type_fpmx, 0x15, 8, 7), 468*aa74c44bSWells Lu FNCN("SPIM0_INT", pinmux_type_fpmx, 0x16, 0, 7), /* 4x SPI masters */ 469*aa74c44bSWells Lu FNCN("SPIM0_CLK", pinmux_type_fpmx, 0x16, 8, 7), 470*aa74c44bSWells Lu FNCN("SPIM0_EN", pinmux_type_fpmx, 0x17, 0, 7), 471*aa74c44bSWells Lu FNCN("SPIM0_DO", pinmux_type_fpmx, 0x17, 8, 7), 472*aa74c44bSWells Lu FNCN("SPIM0_DI", pinmux_type_fpmx, 0x18, 0, 7), 473*aa74c44bSWells Lu FNCN("SPIM1_INT", pinmux_type_fpmx, 0x18, 8, 7), 474*aa74c44bSWells Lu FNCN("SPIM1_CLK", pinmux_type_fpmx, 0x19, 0, 7), 475*aa74c44bSWells Lu FNCN("SPIM1_EN", pinmux_type_fpmx, 0x19, 8, 7), 476*aa74c44bSWells Lu FNCN("SPIM1_DO", pinmux_type_fpmx, 0x1A, 0, 7), 477*aa74c44bSWells Lu FNCN("SPIM1_DI", pinmux_type_fpmx, 0x1A, 8, 7), 478*aa74c44bSWells Lu FNCN("SPIM2_INT", pinmux_type_fpmx, 0x1B, 0, 7), 479*aa74c44bSWells Lu FNCN("SPIM2_CLK", pinmux_type_fpmx, 0x1B, 8, 7), 480*aa74c44bSWells Lu FNCN("SPIM2_EN", pinmux_type_fpmx, 0x1C, 0, 7), 481*aa74c44bSWells Lu FNCN("SPIM2_DO", pinmux_type_fpmx, 0x1C, 8, 7), 482*aa74c44bSWells Lu FNCN("SPIM2_DI", pinmux_type_fpmx, 0x1D, 0, 7), 483*aa74c44bSWells Lu FNCN("SPIM3_INT", pinmux_type_fpmx, 0x1D, 8, 7), 484*aa74c44bSWells Lu FNCN("SPIM3_CLK", pinmux_type_fpmx, 0x1E, 0, 7), 485*aa74c44bSWells Lu FNCN("SPIM3_EN", pinmux_type_fpmx, 0x1E, 8, 7), 486*aa74c44bSWells Lu FNCN("SPIM3_DO", pinmux_type_fpmx, 0x1F, 0, 7), 487*aa74c44bSWells Lu FNCN("SPIM3_DI", pinmux_type_fpmx, 0x1F, 8, 7), 488*aa74c44bSWells Lu 489*aa74c44bSWells Lu FNCN("SPI0S_INT", pinmux_type_fpmx, 0x20, 0, 7), /* 4x SPI slaves */ 490*aa74c44bSWells Lu FNCN("SPI0S_CLK", pinmux_type_fpmx, 0x20, 8, 7), 491*aa74c44bSWells Lu FNCN("SPI0S_EN", pinmux_type_fpmx, 0x21, 0, 7), 492*aa74c44bSWells Lu FNCN("SPI0S_DO", pinmux_type_fpmx, 0x21, 8, 7), 493*aa74c44bSWells Lu FNCN("SPI0S_DI", pinmux_type_fpmx, 0x22, 0, 7), 494*aa74c44bSWells Lu FNCN("SPI1S_INT", pinmux_type_fpmx, 0x22, 8, 7), 495*aa74c44bSWells Lu FNCN("SPI1S_CLK", pinmux_type_fpmx, 0x23, 0, 7), 496*aa74c44bSWells Lu FNCN("SPI1S_EN", pinmux_type_fpmx, 0x23, 8, 7), 497*aa74c44bSWells Lu FNCN("SPI1S_DO", pinmux_type_fpmx, 0x24, 0, 7), 498*aa74c44bSWells Lu FNCN("SPI1S_DI", pinmux_type_fpmx, 0x24, 8, 7), 499*aa74c44bSWells Lu FNCN("SPI2S_INT", pinmux_type_fpmx, 0x25, 0, 7), 500*aa74c44bSWells Lu FNCN("SPI2S_CLK", pinmux_type_fpmx, 0x25, 8, 7), 501*aa74c44bSWells Lu FNCN("SPI2S_EN", pinmux_type_fpmx, 0x26, 0, 7), 502*aa74c44bSWells Lu FNCN("SPI2S_DO", pinmux_type_fpmx, 0x26, 8, 7), 503*aa74c44bSWells Lu FNCN("SPI2S_DI", pinmux_type_fpmx, 0x27, 0, 7), 504*aa74c44bSWells Lu FNCN("SPI3S_INT", pinmux_type_fpmx, 0x27, 8, 7), 505*aa74c44bSWells Lu FNCN("SPI3S_CLK", pinmux_type_fpmx, 0x28, 0, 7), 506*aa74c44bSWells Lu FNCN("SPI3S_EN", pinmux_type_fpmx, 0x28, 8, 7), 507*aa74c44bSWells Lu FNCN("SPI3S_DO", pinmux_type_fpmx, 0x29, 0, 7), 508*aa74c44bSWells Lu FNCN("SPI3S_DI", pinmux_type_fpmx, 0x29, 8, 7), 509*aa74c44bSWells Lu FNCN("I2CM0_CLK", pinmux_type_fpmx, 0x2A, 0, 7), /* 4x I2C masters */ 510*aa74c44bSWells Lu FNCN("I2CM0_DAT", pinmux_type_fpmx, 0x2A, 8, 7), 511*aa74c44bSWells Lu FNCN("I2CM1_CLK", pinmux_type_fpmx, 0x2B, 0, 7), 512*aa74c44bSWells Lu FNCN("I2CM1_DAT", pinmux_type_fpmx, 0x2B, 8, 7), 513*aa74c44bSWells Lu FNCN("I2CM2_CLK", pinmux_type_fpmx, 0x2C, 0, 7), 514*aa74c44bSWells Lu FNCN("I2CM2_DAT", pinmux_type_fpmx, 0x2C, 8, 7), 515*aa74c44bSWells Lu FNCN("I2CM3_CLK", pinmux_type_fpmx, 0x2D, 0, 7), 516*aa74c44bSWells Lu FNCN("I2CM3_DAT", pinmux_type_fpmx, 0x2D, 8, 7), 517*aa74c44bSWells Lu FNCN("UA1_TX", pinmux_type_fpmx, 0x2E, 0, 7), /* 4x UARTS */ 518*aa74c44bSWells Lu FNCN("UA1_RX", pinmux_type_fpmx, 0x2E, 8, 7), 519*aa74c44bSWells Lu FNCN("UA1_CTS", pinmux_type_fpmx, 0x2F, 0, 7), 520*aa74c44bSWells Lu FNCN("UA1_RTS", pinmux_type_fpmx, 0x2F, 8, 7), 521*aa74c44bSWells Lu 522*aa74c44bSWells Lu FNCN("UA2_TX", pinmux_type_fpmx, 0x30, 0, 7), 523*aa74c44bSWells Lu FNCN("UA2_RX", pinmux_type_fpmx, 0x30, 8, 7), 524*aa74c44bSWells Lu FNCN("UA2_CTS", pinmux_type_fpmx, 0x31, 0, 7), 525*aa74c44bSWells Lu FNCN("UA2_RTS", pinmux_type_fpmx, 0x31, 8, 7), 526*aa74c44bSWells Lu FNCN("UA3_TX", pinmux_type_fpmx, 0x32, 0, 7), 527*aa74c44bSWells Lu FNCN("UA3_RX", pinmux_type_fpmx, 0x32, 8, 7), 528*aa74c44bSWells Lu FNCN("UA3_CTS", pinmux_type_fpmx, 0x33, 0, 7), 529*aa74c44bSWells Lu FNCN("UA3_RTS", pinmux_type_fpmx, 0x33, 8, 7), 530*aa74c44bSWells Lu FNCN("UA4_TX", pinmux_type_fpmx, 0x34, 0, 7), 531*aa74c44bSWells Lu FNCN("UA4_RX", pinmux_type_fpmx, 0x34, 8, 7), 532*aa74c44bSWells Lu FNCN("UA4_CTS", pinmux_type_fpmx, 0x35, 0, 7), 533*aa74c44bSWells Lu FNCN("UA4_RTS", pinmux_type_fpmx, 0x35, 8, 7), 534*aa74c44bSWells Lu FNCN("TIMER0_INT", pinmux_type_fpmx, 0x36, 0, 7), /* 4x timer int. */ 535*aa74c44bSWells Lu FNCN("TIMER1_INT", pinmux_type_fpmx, 0x36, 8, 7), 536*aa74c44bSWells Lu FNCN("TIMER2_INT", pinmux_type_fpmx, 0x37, 0, 7), 537*aa74c44bSWells Lu FNCN("TIMER3_INT", pinmux_type_fpmx, 0x37, 8, 7), 538*aa74c44bSWells Lu FNCN("GPIO_INT0", pinmux_type_fpmx, 0x38, 0, 7), /* 8x GPIO int. */ 539*aa74c44bSWells Lu FNCN("GPIO_INT1", pinmux_type_fpmx, 0x38, 8, 7), 540*aa74c44bSWells Lu FNCN("GPIO_INT2", pinmux_type_fpmx, 0x39, 0, 7), 541*aa74c44bSWells Lu FNCN("GPIO_INT3", pinmux_type_fpmx, 0x39, 8, 7), 542*aa74c44bSWells Lu FNCN("GPIO_INT4", pinmux_type_fpmx, 0x3A, 0, 7), 543*aa74c44bSWells Lu FNCN("GPIO_INT5", pinmux_type_fpmx, 0x3A, 8, 7), 544*aa74c44bSWells Lu FNCN("GPIO_INT6", pinmux_type_fpmx, 0x3B, 0, 7), 545*aa74c44bSWells Lu FNCN("GPIO_INT7", pinmux_type_fpmx, 0x3B, 8, 7), 546*aa74c44bSWells Lu 547*aa74c44bSWells Lu /* MOON1 register */ 548*aa74c44bSWells Lu FNCE("SPI_FLASH", pinmux_type_grp, 0x01, 0, 2, sp7021grps_spif), 549*aa74c44bSWells Lu FNCE("SPI_FLASH_4BIT", pinmux_type_grp, 0x01, 2, 2, sp7021grps_spi4), 550*aa74c44bSWells Lu FNCE("SPI_NAND", pinmux_type_grp, 0x01, 4, 1, sp7021grps_snan), 551*aa74c44bSWells Lu FNCE("CARD0_EMMC", pinmux_type_grp, 0x01, 5, 1, sp7021grps_emmc), 552*aa74c44bSWells Lu FNCE("SD_CARD", pinmux_type_grp, 0x01, 6, 1, sp7021grps_sdsd), 553*aa74c44bSWells Lu FNCE("UA0", pinmux_type_grp, 0x01, 7, 1, sp7021grps_uar0), 554*aa74c44bSWells Lu FNCE("ACHIP_DEBUG", pinmux_type_grp, 0x01, 8, 2, sp7021grps_adbg), 555*aa74c44bSWells Lu FNCE("ACHIP_UA2AXI", pinmux_type_grp, 0x01, 10, 2, sp7021grps_au2x), 556*aa74c44bSWells Lu FNCE("FPGA_IFX", pinmux_type_grp, 0x01, 12, 1, sp7021grps_fpga), 557*aa74c44bSWells Lu FNCE("HDMI_TX", pinmux_type_grp, 0x01, 13, 2, sp7021grps_hdmi), 558*aa74c44bSWells Lu 559*aa74c44bSWells Lu FNCE("AUD_EXT_ADC_IFX0", pinmux_type_grp, 0x01, 15, 1, sp7021grps_eadc), 560*aa74c44bSWells Lu FNCE("AUD_EXT_DAC_IFX0", pinmux_type_grp, 0x02, 0, 1, sp7021grps_edac), 561*aa74c44bSWells Lu FNCE("SPDIF_RX", pinmux_type_grp, 0x02, 2, 1, sp7021grps_spdi), 562*aa74c44bSWells Lu FNCE("SPDIF_TX", pinmux_type_grp, 0x02, 3, 1, sp7021grps_spdo), 563*aa74c44bSWells Lu FNCE("TDMTX_IFX0", pinmux_type_grp, 0x02, 4, 1, sp7021grps_tdmt), 564*aa74c44bSWells Lu FNCE("TDMRX_IFX0", pinmux_type_grp, 0x02, 5, 1, sp7021grps_tdmr), 565*aa74c44bSWells Lu FNCE("PDMRX_IFX0", pinmux_type_grp, 0x02, 6, 1, sp7021grps_pdmr), 566*aa74c44bSWells Lu FNCE("PCM_IEC_TX", pinmux_type_grp, 0x02, 7, 1, sp7021grps_pcmt), 567*aa74c44bSWells Lu FNCE("LCDIF", pinmux_type_grp, 0x04, 6, 1, sp7021grps_lcdi), 568*aa74c44bSWells Lu FNCE("DVD_DSP_DEBUG", pinmux_type_grp, 0x02, 8, 1, sp7021grps_dvdd), 569*aa74c44bSWells Lu FNCE("I2C_DEBUG", pinmux_type_grp, 0x02, 9, 1, sp7021grps_i2cd), 570*aa74c44bSWells Lu FNCE("I2C_SLAVE", pinmux_type_grp, 0x02, 10, 1, sp7021grps_i2cs), 571*aa74c44bSWells Lu FNCE("WAKEUP", pinmux_type_grp, 0x02, 11, 1, sp7021grps_wakp), 572*aa74c44bSWells Lu FNCE("UART2AXI", pinmux_type_grp, 0x02, 12, 2, sp7021grps_u2ax), 573*aa74c44bSWells Lu FNCE("USB0_I2C", pinmux_type_grp, 0x02, 14, 2, sp7021grps_u0ic), 574*aa74c44bSWells Lu FNCE("USB1_I2C", pinmux_type_grp, 0x03, 0, 2, sp7021grps_u1ic), 575*aa74c44bSWells Lu FNCE("USB0_OTG", pinmux_type_grp, 0x03, 2, 1, sp7021grps_u0ot), 576*aa74c44bSWells Lu FNCE("USB1_OTG", pinmux_type_grp, 0x03, 3, 1, sp7021grps_u1ot), 577*aa74c44bSWells Lu FNCE("UPHY0_DEBUG", pinmux_type_grp, 0x03, 4, 1, sp7021grps_up0d), 578*aa74c44bSWells Lu FNCE("UPHY1_DEBUG", pinmux_type_grp, 0x03, 5, 1, sp7021grps_up1d), 579*aa74c44bSWells Lu FNCE("UPHY0_EXT", pinmux_type_grp, 0x03, 6, 1, sp7021grps_upex), 580*aa74c44bSWells Lu FNCE("PROBE_PORT", pinmux_type_grp, 0x03, 7, 2, sp7021grps_prbp), 581*aa74c44bSWells Lu }; 582*aa74c44bSWells Lu 583*aa74c44bSWells Lu const size_t sppctl_list_funcs_sz = ARRAY_SIZE(sppctl_list_funcs); 584