1aa74c44bSWells Lu // SPDX-License-Identifier: GPL-2.0 2aa74c44bSWells Lu /* 3aa74c44bSWells Lu * SP7021 Pin Controller Driver. 4aa74c44bSWells Lu * Copyright (C) Sunplus Tech / Tibbo Tech. 5aa74c44bSWells Lu */ 6aa74c44bSWells Lu 7aa74c44bSWells Lu #include <linux/gpio/driver.h> 8aa74c44bSWells Lu #include <linux/kernel.h> 9aa74c44bSWells Lu #include <linux/pinctrl/pinctrl.h> 10aa74c44bSWells Lu 11aa74c44bSWells Lu #include "sppctl.h" 12aa74c44bSWells Lu 13aa74c44bSWells Lu #define D_PIS(x, y) "P" __stringify(x) "_0" __stringify(y) 14aa74c44bSWells Lu #define D(x, y) ((x) * 8 + (y)) 15aa74c44bSWells Lu #define P(x, y) PINCTRL_PIN(D(x, y), D_PIS(x, y)) 16aa74c44bSWells Lu 17aa74c44bSWells Lu const char * const sppctl_gpio_list_s[] = { 18aa74c44bSWells Lu D_PIS(0, 0), D_PIS(0, 1), D_PIS(0, 2), D_PIS(0, 3), 19aa74c44bSWells Lu D_PIS(0, 4), D_PIS(0, 5), D_PIS(0, 6), D_PIS(0, 7), 20aa74c44bSWells Lu D_PIS(1, 0), D_PIS(1, 1), D_PIS(1, 2), D_PIS(1, 3), 21aa74c44bSWells Lu D_PIS(1, 4), D_PIS(1, 5), D_PIS(1, 6), D_PIS(1, 7), 22aa74c44bSWells Lu D_PIS(2, 0), D_PIS(2, 1), D_PIS(2, 2), D_PIS(2, 3), 23aa74c44bSWells Lu D_PIS(2, 4), D_PIS(2, 5), D_PIS(2, 6), D_PIS(2, 7), 24aa74c44bSWells Lu D_PIS(3, 0), D_PIS(3, 1), D_PIS(3, 2), D_PIS(3, 3), 25aa74c44bSWells Lu D_PIS(3, 4), D_PIS(3, 5), D_PIS(3, 6), D_PIS(3, 7), 26aa74c44bSWells Lu D_PIS(4, 0), D_PIS(4, 1), D_PIS(4, 2), D_PIS(4, 3), 27aa74c44bSWells Lu D_PIS(4, 4), D_PIS(4, 5), D_PIS(4, 6), D_PIS(4, 7), 28aa74c44bSWells Lu D_PIS(5, 0), D_PIS(5, 1), D_PIS(5, 2), D_PIS(5, 3), 29aa74c44bSWells Lu D_PIS(5, 4), D_PIS(5, 5), D_PIS(5, 6), D_PIS(5, 7), 30aa74c44bSWells Lu D_PIS(6, 0), D_PIS(6, 1), D_PIS(6, 2), D_PIS(6, 3), 31aa74c44bSWells Lu D_PIS(6, 4), D_PIS(6, 5), D_PIS(6, 6), D_PIS(6, 7), 32aa74c44bSWells Lu D_PIS(7, 0), D_PIS(7, 1), D_PIS(7, 2), D_PIS(7, 3), 33aa74c44bSWells Lu D_PIS(7, 4), D_PIS(7, 5), D_PIS(7, 6), D_PIS(7, 7), 34aa74c44bSWells Lu D_PIS(8, 0), D_PIS(8, 1), D_PIS(8, 2), D_PIS(8, 3), 35aa74c44bSWells Lu D_PIS(8, 4), D_PIS(8, 5), D_PIS(8, 6), D_PIS(8, 7), 36aa74c44bSWells Lu D_PIS(9, 0), D_PIS(9, 1), D_PIS(9, 2), D_PIS(9, 3), 37aa74c44bSWells Lu D_PIS(9, 4), D_PIS(9, 5), D_PIS(9, 6), D_PIS(9, 7), 38aa74c44bSWells Lu D_PIS(10, 0), D_PIS(10, 1), D_PIS(10, 2), D_PIS(10, 3), 39aa74c44bSWells Lu D_PIS(10, 4), D_PIS(10, 5), D_PIS(10, 6), D_PIS(10, 7), 40aa74c44bSWells Lu D_PIS(11, 0), D_PIS(11, 1), D_PIS(11, 2), D_PIS(11, 3), 41aa74c44bSWells Lu D_PIS(11, 4), D_PIS(11, 5), D_PIS(11, 6), D_PIS(11, 7), 42aa74c44bSWells Lu D_PIS(12, 0), D_PIS(12, 1), D_PIS(12, 2), 43aa74c44bSWells Lu }; 44aa74c44bSWells Lu 45aa74c44bSWells Lu const size_t sppctl_gpio_list_sz = ARRAY_SIZE(sppctl_gpio_list_s); 46aa74c44bSWells Lu 47aa74c44bSWells Lu const unsigned int sppctl_pins_gpio[] = { 48aa74c44bSWells Lu D(0, 0), D(0, 1), D(0, 2), D(0, 3), D(0, 4), D(0, 5), D(0, 6), D(0, 7), 49aa74c44bSWells Lu D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), D(1, 6), D(1, 7), 50aa74c44bSWells Lu D(2, 0), D(2, 1), D(2, 2), D(2, 3), D(2, 4), D(2, 5), D(2, 6), D(2, 7), 51aa74c44bSWells Lu D(3, 0), D(3, 1), D(3, 2), D(3, 3), D(3, 4), D(3, 5), D(3, 6), D(3, 7), 52aa74c44bSWells Lu D(4, 0), D(4, 1), D(4, 2), D(4, 3), D(4, 4), D(4, 5), D(4, 6), D(4, 7), 53aa74c44bSWells Lu D(5, 0), D(5, 1), D(5, 2), D(5, 3), D(5, 4), D(5, 5), D(5, 6), D(5, 7), 54aa74c44bSWells Lu D(6, 0), D(6, 1), D(6, 2), D(6, 3), D(6, 4), D(6, 5), D(6, 6), D(6, 7), 55aa74c44bSWells Lu D(7, 0), D(7, 1), D(7, 2), D(7, 3), D(7, 4), D(7, 5), D(7, 6), D(7, 7), 56aa74c44bSWells Lu D(8, 0), D(8, 1), D(8, 2), D(8, 3), D(8, 4), D(8, 5), D(8, 6), D(8, 7), 57aa74c44bSWells Lu D(9, 0), D(9, 1), D(9, 2), D(9, 3), D(9, 4), D(9, 5), D(9, 6), D(9, 7), 58aa74c44bSWells Lu D(10, 0), D(10, 1), D(10, 2), D(10, 3), D(10, 4), D(10, 5), D(10, 6), D(10, 7), 59aa74c44bSWells Lu D(11, 0), D(11, 1), D(11, 2), D(11, 3), D(11, 4), D(11, 5), D(11, 6), D(11, 7), 60aa74c44bSWells Lu D(12, 0), D(12, 1), D(12, 2), 61aa74c44bSWells Lu }; 62aa74c44bSWells Lu 63aa74c44bSWells Lu const struct pinctrl_pin_desc sppctl_pins_all[] = { 64aa74c44bSWells Lu /* gpio and iop only */ 65aa74c44bSWells Lu P(0, 0), P(0, 1), P(0, 2), P(0, 3), P(0, 4), P(0, 5), P(0, 6), P(0, 7), 66aa74c44bSWells Lu /* gpio, iop, muxable */ 67aa74c44bSWells Lu P(1, 0), P(1, 1), P(1, 2), P(1, 3), P(1, 4), P(1, 5), P(1, 6), P(1, 7), 68aa74c44bSWells Lu P(2, 0), P(2, 1), P(2, 2), P(2, 3), P(2, 4), P(2, 5), P(2, 6), P(2, 7), 69aa74c44bSWells Lu P(3, 0), P(3, 1), P(3, 2), P(3, 3), P(3, 4), P(3, 5), P(3, 6), P(3, 7), 70aa74c44bSWells Lu P(4, 0), P(4, 1), P(4, 2), P(4, 3), P(4, 4), P(4, 5), P(4, 6), P(4, 7), 71aa74c44bSWells Lu P(5, 0), P(5, 1), P(5, 2), P(5, 3), P(5, 4), P(5, 5), P(5, 6), P(5, 7), 72aa74c44bSWells Lu P(6, 0), P(6, 1), P(6, 2), P(6, 3), P(6, 4), P(6, 5), P(6, 6), P(6, 7), 73aa74c44bSWells Lu P(7, 0), P(7, 1), P(7, 2), P(7, 3), P(7, 4), P(7, 5), P(7, 6), P(7, 7), 74aa74c44bSWells Lu P(8, 0), P(8, 1), P(8, 2), P(8, 3), P(8, 4), P(8, 5), P(8, 6), P(8, 7), 75aa74c44bSWells Lu /* gpio and iop only */ 76aa74c44bSWells Lu P(9, 0), P(9, 1), P(9, 2), P(9, 3), P(9, 4), P(9, 5), P(9, 6), P(9, 7), 77aa74c44bSWells Lu P(10, 0), P(10, 1), P(10, 2), P(10, 3), P(10, 4), P(10, 5), P(10, 6), P(10, 7), 78aa74c44bSWells Lu P(11, 0), P(11, 1), P(11, 2), P(11, 3), P(11, 4), P(11, 5), P(11, 6), P(11, 7), 79aa74c44bSWells Lu P(12, 0), P(12, 1), P(12, 2), 80aa74c44bSWells Lu }; 81aa74c44bSWells Lu 82aa74c44bSWells Lu const size_t sppctl_pins_all_sz = ARRAY_SIZE(sppctl_pins_all); 83aa74c44bSWells Lu 84aa74c44bSWells Lu const char * const sppctl_pmux_list_s[] = { 85aa74c44bSWells Lu D_PIS(0, 0), 86aa74c44bSWells Lu D_PIS(1, 0), D_PIS(1, 1), D_PIS(1, 2), D_PIS(1, 3), 87aa74c44bSWells Lu D_PIS(1, 4), D_PIS(1, 5), D_PIS(1, 6), D_PIS(1, 7), 88aa74c44bSWells Lu D_PIS(2, 0), D_PIS(2, 1), D_PIS(2, 2), D_PIS(2, 3), 89aa74c44bSWells Lu D_PIS(2, 4), D_PIS(2, 5), D_PIS(2, 6), D_PIS(2, 7), 90aa74c44bSWells Lu D_PIS(3, 0), D_PIS(3, 1), D_PIS(3, 2), D_PIS(3, 3), 91aa74c44bSWells Lu D_PIS(3, 4), D_PIS(3, 5), D_PIS(3, 6), D_PIS(3, 7), 92aa74c44bSWells Lu D_PIS(4, 0), D_PIS(4, 1), D_PIS(4, 2), D_PIS(4, 3), 93aa74c44bSWells Lu D_PIS(4, 4), D_PIS(4, 5), D_PIS(4, 6), D_PIS(4, 7), 94aa74c44bSWells Lu D_PIS(5, 0), D_PIS(5, 1), D_PIS(5, 2), D_PIS(5, 3), 95aa74c44bSWells Lu D_PIS(5, 4), D_PIS(5, 5), D_PIS(5, 6), D_PIS(5, 7), 96aa74c44bSWells Lu D_PIS(6, 0), D_PIS(6, 1), D_PIS(6, 2), D_PIS(6, 3), 97aa74c44bSWells Lu D_PIS(6, 4), D_PIS(6, 5), D_PIS(6, 6), D_PIS(6, 7), 98aa74c44bSWells Lu D_PIS(7, 0), D_PIS(7, 1), D_PIS(7, 2), D_PIS(7, 3), 99aa74c44bSWells Lu D_PIS(7, 4), D_PIS(7, 5), D_PIS(7, 6), D_PIS(7, 7), 100aa74c44bSWells Lu D_PIS(8, 0), D_PIS(8, 1), D_PIS(8, 2), D_PIS(8, 3), 101aa74c44bSWells Lu D_PIS(8, 4), D_PIS(8, 5), D_PIS(8, 6), D_PIS(8, 7), 102aa74c44bSWells Lu }; 103aa74c44bSWells Lu 104aa74c44bSWells Lu const size_t sppctl_pmux_list_sz = ARRAY_SIZE(sppctl_pmux_list_s); 105aa74c44bSWells Lu 106aa74c44bSWells Lu static const unsigned int pins_spif1[] = { 107aa74c44bSWells Lu D(10, 3), D(10, 4), D(10, 6), D(10, 7), 108aa74c44bSWells Lu }; 109aa74c44bSWells Lu 110aa74c44bSWells Lu static const unsigned int pins_spif2[] = { 111aa74c44bSWells Lu D(9, 4), D(9, 6), D(9, 7), D(10, 1), 112aa74c44bSWells Lu }; 113aa74c44bSWells Lu 114aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_spif[] = { 115aa74c44bSWells Lu EGRP("SPI_FLASH1", 1, pins_spif1), 116aa74c44bSWells Lu EGRP("SPI_FLASH2", 2, pins_spif2), 117aa74c44bSWells Lu }; 118aa74c44bSWells Lu 119aa74c44bSWells Lu static const unsigned int pins_spi41[] = { 120aa74c44bSWells Lu D(10, 2), D(10, 5), 121aa74c44bSWells Lu }; 122aa74c44bSWells Lu 123aa74c44bSWells Lu static const unsigned int pins_spi42[] = { 124aa74c44bSWells Lu D(9, 5), D(9, 8), 125aa74c44bSWells Lu }; 126aa74c44bSWells Lu 127aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_spi4[] = { 128aa74c44bSWells Lu EGRP("SPI_FLASH_4BIT1", 1, pins_spi41), 129aa74c44bSWells Lu EGRP("SPI_FLASH_4BIT2", 2, pins_spi42), 130aa74c44bSWells Lu }; 131aa74c44bSWells Lu 132aa74c44bSWells Lu static const unsigned int pins_snan[] = { 133aa74c44bSWells Lu D(9, 4), D(9, 5), D(9, 6), D(9, 7), D(10, 0), D(10, 1), 134aa74c44bSWells Lu }; 135aa74c44bSWells Lu 136aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_snan[] = { 137aa74c44bSWells Lu EGRP("SPI_NAND", 1, pins_snan), 138aa74c44bSWells Lu }; 139aa74c44bSWells Lu 140aa74c44bSWells Lu static const unsigned int pins_emmc[] = { 141aa74c44bSWells Lu D(9, 0), D(9, 1), D(9, 2), D(9, 3), D(9, 4), D(9, 5), 142aa74c44bSWells Lu D(9, 6), D(9, 7), D(10, 0), D(10, 1), 143aa74c44bSWells Lu }; 144aa74c44bSWells Lu 145aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_emmc[] = { 146aa74c44bSWells Lu EGRP("CARD0_EMMC", 1, pins_emmc), 147aa74c44bSWells Lu }; 148aa74c44bSWells Lu 149aa74c44bSWells Lu static const unsigned int pins_sdsd[] = { 150aa74c44bSWells Lu D(8, 1), D(8, 2), D(8, 3), D(8, 4), D(8, 5), D(8, 6), 151aa74c44bSWells Lu }; 152aa74c44bSWells Lu 153aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_sdsd[] = { 154aa74c44bSWells Lu EGRP("SD_CARD", 1, pins_sdsd), 155aa74c44bSWells Lu }; 156aa74c44bSWells Lu 157aa74c44bSWells Lu static const unsigned int pins_uar0[] = { 158aa74c44bSWells Lu D(11, 0), D(11, 1), 159aa74c44bSWells Lu }; 160aa74c44bSWells Lu 161aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_uar0[] = { 162aa74c44bSWells Lu EGRP("UA0", 1, pins_uar0), 163aa74c44bSWells Lu }; 164aa74c44bSWells Lu 165aa74c44bSWells Lu static const unsigned int pins_adbg1[] = { 166aa74c44bSWells Lu D(10, 2), D(10, 3), 167aa74c44bSWells Lu }; 168aa74c44bSWells Lu 169aa74c44bSWells Lu static const unsigned int pins_adbg2[] = { 170aa74c44bSWells Lu D(7, 1), D(7, 2), 171aa74c44bSWells Lu }; 172aa74c44bSWells Lu 173aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_adbg[] = { 174aa74c44bSWells Lu EGRP("ACHIP_DEBUG1", 1, pins_adbg1), 175aa74c44bSWells Lu EGRP("ACHIP_DEBUG2", 2, pins_adbg2), 176aa74c44bSWells Lu }; 177aa74c44bSWells Lu 178aa74c44bSWells Lu static const unsigned int pins_aua2axi1[] = { 179aa74c44bSWells Lu D(2, 0), D(2, 1), D(2, 2), 180aa74c44bSWells Lu }; 181aa74c44bSWells Lu 182aa74c44bSWells Lu static const unsigned int pins_aua2axi2[] = { 183aa74c44bSWells Lu D(1, 0), D(1, 1), D(1, 2), 184aa74c44bSWells Lu }; 185aa74c44bSWells Lu 186aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_au2x[] = { 187aa74c44bSWells Lu EGRP("ACHIP_UA2AXI1", 1, pins_aua2axi1), 188aa74c44bSWells Lu EGRP("ACHIP_UA2AXI2", 2, pins_aua2axi2), 189aa74c44bSWells Lu }; 190aa74c44bSWells Lu 191aa74c44bSWells Lu static const unsigned int pins_fpga[] = { 192aa74c44bSWells Lu D(0, 2), D(0, 3), D(0, 4), D(0, 5), D(0, 6), D(0, 7), 193aa74c44bSWells Lu D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), 194aa74c44bSWells Lu D(1, 6), D(1, 7), D(2, 0), D(2, 1), D(2, 2), D(2, 3), 195aa74c44bSWells Lu D(2, 4), D(2, 5), D(2, 6), D(2, 7), D(3, 0), D(3, 1), 196aa74c44bSWells Lu D(3, 2), D(3, 3), D(3, 4), D(3, 5), D(3, 6), D(3, 7), 197aa74c44bSWells Lu D(4, 0), D(4, 1), D(4, 2), D(4, 3), D(4, 4), D(4, 5), 198aa74c44bSWells Lu D(4, 6), D(4, 7), D(5, 0), D(5, 1), D(5, 2), 199aa74c44bSWells Lu }; 200aa74c44bSWells Lu 201aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_fpga[] = { 202aa74c44bSWells Lu EGRP("FPGA_IFX", 1, pins_fpga), 203aa74c44bSWells Lu }; 204aa74c44bSWells Lu 205aa74c44bSWells Lu static const unsigned int pins_hdmi1[] = { 206aa74c44bSWells Lu D(10, 6), D(12, 2), D(12, 1), 207aa74c44bSWells Lu }; 208aa74c44bSWells Lu 209aa74c44bSWells Lu static const unsigned int pins_hdmi2[] = { 210aa74c44bSWells Lu D(8, 3), D(8, 5), D(8, 6), 211aa74c44bSWells Lu }; 212aa74c44bSWells Lu 213aa74c44bSWells Lu static const unsigned int pins_hdmi3[] = { 214aa74c44bSWells Lu D(7, 4), D(7, 6), D(7, 7), 215aa74c44bSWells Lu }; 216aa74c44bSWells Lu 217aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_hdmi[] = { 218aa74c44bSWells Lu EGRP("HDMI_TX1", 1, pins_hdmi1), 219aa74c44bSWells Lu EGRP("HDMI_TX2", 2, pins_hdmi2), 220aa74c44bSWells Lu EGRP("HDMI_TX3", 3, pins_hdmi3), 221aa74c44bSWells Lu }; 222aa74c44bSWells Lu 223aa74c44bSWells Lu static const unsigned int pins_eadc[] = { 224aa74c44bSWells Lu D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), D(1, 6), 225aa74c44bSWells Lu }; 226aa74c44bSWells Lu 227aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_eadc[] = { 228aa74c44bSWells Lu EGRP("AUD_EXT_ADC_IFX0", 1, pins_eadc), 229aa74c44bSWells Lu }; 230aa74c44bSWells Lu 231aa74c44bSWells Lu static const unsigned int pins_edac[] = { 232aa74c44bSWells Lu D(2, 5), D(2, 6), D(2, 7), D(3, 0), D(3, 1), D(3, 2), D(3, 4), 233aa74c44bSWells Lu }; 234aa74c44bSWells Lu 235aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_edac[] = { 236aa74c44bSWells Lu EGRP("AUD_EXT_DAC_IFX0", 1, pins_edac), 237aa74c44bSWells Lu }; 238aa74c44bSWells Lu 239aa74c44bSWells Lu static const unsigned int pins_spdi[] = { 240aa74c44bSWells Lu D(2, 4), 241aa74c44bSWells Lu }; 242aa74c44bSWells Lu 243aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_spdi[] = { 244aa74c44bSWells Lu EGRP("AUD_IEC_RX0", 1, pins_spdi), 245aa74c44bSWells Lu }; 246aa74c44bSWells Lu 247aa74c44bSWells Lu static const unsigned int pins_spdo[] = { 248aa74c44bSWells Lu D(3, 6), 249aa74c44bSWells Lu }; 250aa74c44bSWells Lu 251aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_spdo[] = { 252aa74c44bSWells Lu EGRP("AUD_IEC_TX0", 1, pins_spdo), 253aa74c44bSWells Lu }; 254aa74c44bSWells Lu 255aa74c44bSWells Lu static const unsigned int pins_tdmt[] = { 256aa74c44bSWells Lu D(2, 5), D(2, 6), D(2, 7), D(3, 0), D(3, 1), D(3, 2), 257aa74c44bSWells Lu }; 258aa74c44bSWells Lu 259aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_tdmt[] = { 260aa74c44bSWells Lu EGRP("TDMTX_IFX0", 1, pins_tdmt), 261aa74c44bSWells Lu }; 262aa74c44bSWells Lu 263aa74c44bSWells Lu static const unsigned int pins_tdmr[] = { 264aa74c44bSWells Lu D(1, 7), D(2, 0), D(2, 1), D(2, 2), 265aa74c44bSWells Lu }; 266aa74c44bSWells Lu 267aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_tdmr[] = { 268aa74c44bSWells Lu EGRP("TDMRX_IFX0", 1, pins_tdmr), 269aa74c44bSWells Lu }; 270aa74c44bSWells Lu 271aa74c44bSWells Lu static const unsigned int pins_pdmr[] = { 272aa74c44bSWells Lu D(1, 7), D(2, 0), D(2, 1), D(2, 2), D(2, 3), 273aa74c44bSWells Lu }; 274aa74c44bSWells Lu 275aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_pdmr[] = { 276aa74c44bSWells Lu EGRP("PDMRX_IFX0", 1, pins_pdmr), 277aa74c44bSWells Lu }; 278aa74c44bSWells Lu 279aa74c44bSWells Lu static const unsigned int pins_pcmt[] = { 280aa74c44bSWells Lu D(3, 7), D(4, 0), D(4, 1), D(4, 2), D(4, 3), D(4, 4), 281aa74c44bSWells Lu }; 282aa74c44bSWells Lu 283aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_pcmt[] = { 284aa74c44bSWells Lu EGRP("PCM_IEC_TX", 1, pins_pcmt), 285aa74c44bSWells Lu }; 286aa74c44bSWells Lu 287aa74c44bSWells Lu static const unsigned int pins_lcdi[] = { 288aa74c44bSWells Lu D(1, 4), D(1, 5), D(1, 6), D(1, 7), D(2, 0), D(2, 1), D(2, 2), D(2, 3), 289aa74c44bSWells Lu D(2, 4), D(2, 5), D(2, 6), D(2, 7), D(3, 0), D(3, 1), D(3, 2), D(3, 3), 290aa74c44bSWells Lu D(3, 4), D(3, 5), D(3, 6), D(3, 7), D(4, 0), D(4, 1), D(4, 2), D(4, 3), 291aa74c44bSWells Lu D(4, 4), D(4, 5), D(4, 6), D(4, 7), 292aa74c44bSWells Lu }; 293aa74c44bSWells Lu 294aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_lcdi[] = { 295aa74c44bSWells Lu EGRP("LCDIF", 1, pins_lcdi), 296aa74c44bSWells Lu }; 297aa74c44bSWells Lu 298aa74c44bSWells Lu static const unsigned int pins_dvdd[] = { 299aa74c44bSWells Lu D(7, 0), D(7, 1), D(7, 2), D(7, 3), D(7, 4), D(7, 5), D(7, 6), D(7, 7), 300aa74c44bSWells Lu D(8, 0), D(8, 1), D(8, 2), D(8, 3), D(8, 4), D(8, 5), 301aa74c44bSWells Lu }; 302aa74c44bSWells Lu 303aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_dvdd[] = { 304aa74c44bSWells Lu EGRP("DVD_DSP_DEBUG", 1, pins_dvdd), 305aa74c44bSWells Lu }; 306aa74c44bSWells Lu 307aa74c44bSWells Lu static const unsigned int pins_i2cd[] = { 308aa74c44bSWells Lu D(1, 0), D(1, 1), 309aa74c44bSWells Lu }; 310aa74c44bSWells Lu 311aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_i2cd[] = { 312aa74c44bSWells Lu EGRP("I2C_DEBUG", 1, pins_i2cd), 313aa74c44bSWells Lu }; 314aa74c44bSWells Lu 315aa74c44bSWells Lu static const unsigned int pins_i2cs[] = { 316aa74c44bSWells Lu D(0, 0), D(0, 1), 317aa74c44bSWells Lu }; 318aa74c44bSWells Lu 319aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_i2cs[] = { 320aa74c44bSWells Lu EGRP("I2C_SLAVE", 1, pins_i2cs), 321aa74c44bSWells Lu }; 322aa74c44bSWells Lu 323aa74c44bSWells Lu static const unsigned int pins_wakp[] = { 324aa74c44bSWells Lu D(10, 5), 325aa74c44bSWells Lu }; 326aa74c44bSWells Lu 327aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_wakp[] = { 328aa74c44bSWells Lu EGRP("WAKEUP", 1, pins_wakp), 329aa74c44bSWells Lu }; 330aa74c44bSWells Lu 331aa74c44bSWells Lu static const unsigned int pins_u2ax[] = { 332aa74c44bSWells Lu D(2, 0), D(2, 1), D(3, 0), D(3, 1), 333aa74c44bSWells Lu }; 334aa74c44bSWells Lu 335aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_u2ax[] = { 336aa74c44bSWells Lu EGRP("UART2AXI", 1, pins_u2ax), 337aa74c44bSWells Lu }; 338aa74c44bSWells Lu 339aa74c44bSWells Lu static const unsigned int pins_u0ic[] = { 340aa74c44bSWells Lu D(0, 0), D(0, 1), D(0, 4), D(0, 5), D(1, 0), D(1, 1), 341aa74c44bSWells Lu }; 342aa74c44bSWells Lu 343aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_u0ic[] = { 344aa74c44bSWells Lu EGRP("USB0_I2C", 1, pins_u0ic), 345aa74c44bSWells Lu }; 346aa74c44bSWells Lu 347aa74c44bSWells Lu static const unsigned int pins_u1ic[] = { 348aa74c44bSWells Lu D(0, 2), D(0, 3), D(0, 6), D(0, 7), D(1, 2), D(1, 3), 349aa74c44bSWells Lu }; 350aa74c44bSWells Lu 351aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_u1ic[] = { 352aa74c44bSWells Lu EGRP("USB1_I2C", 1, pins_u1ic), 353aa74c44bSWells Lu }; 354aa74c44bSWells Lu 355aa74c44bSWells Lu static const unsigned int pins_u0ot[] = { 356aa74c44bSWells Lu D(11, 2), 357aa74c44bSWells Lu }; 358aa74c44bSWells Lu 359aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_u0ot[] = { 360aa74c44bSWells Lu EGRP("USB0_OTG", 1, pins_u0ot), 361aa74c44bSWells Lu }; 362aa74c44bSWells Lu 363aa74c44bSWells Lu static const unsigned int pins_u1ot[] = { 364aa74c44bSWells Lu D(11, 3), 365aa74c44bSWells Lu }; 366aa74c44bSWells Lu 367aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_u1ot[] = { 368aa74c44bSWells Lu EGRP("USB1_OTG", 1, pins_u1ot), 369aa74c44bSWells Lu }; 370aa74c44bSWells Lu 371aa74c44bSWells Lu static const unsigned int pins_uphd[] = { 372aa74c44bSWells Lu D(0, 1), D(0, 2), D(0, 3), D(7, 4), D(7, 5), D(7, 6), 373aa74c44bSWells Lu D(7, 7), D(8, 0), D(8, 1), D(8, 2), D(8, 3), 374aa74c44bSWells Lu D(9, 7), D(10, 2), D(10, 3), D(10, 4), 375aa74c44bSWells Lu }; 376aa74c44bSWells Lu 377aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_up0d[] = { 378aa74c44bSWells Lu EGRP("UPHY0_DEBUG", 1, pins_uphd), 379aa74c44bSWells Lu }; 380aa74c44bSWells Lu 381aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_up1d[] = { 382aa74c44bSWells Lu EGRP("UPHY1_DEBUG", 1, pins_uphd), 383aa74c44bSWells Lu }; 384aa74c44bSWells Lu 385aa74c44bSWells Lu static const unsigned int pins_upex[] = { 386aa74c44bSWells Lu D(0, 0), D(0, 1), D(0, 2), D(0, 3), D(0, 4), D(0, 5), D(0, 6), D(0, 7), 387aa74c44bSWells Lu D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), D(1, 6), D(1, 7), 388aa74c44bSWells Lu D(2, 0), D(2, 1), D(2, 2), D(2, 3), D(2, 4), D(2, 5), D(2, 6), D(2, 7), 389aa74c44bSWells Lu D(3, 0), D(3, 1), D(3, 2), D(3, 3), D(3, 4), D(3, 5), D(3, 6), D(3, 7), 390aa74c44bSWells Lu D(4, 0), D(4, 1), D(4, 2), D(4, 3), D(4, 4), D(4, 5), D(4, 6), D(4, 7), 391aa74c44bSWells Lu D(5, 0), D(5, 1), D(5, 2), D(5, 3), D(5, 4), D(5, 5), D(5, 6), D(5, 7), 392aa74c44bSWells Lu D(6, 0), D(6, 1), D(6, 2), D(6, 3), D(6, 4), D(6, 5), D(6, 6), D(6, 7), 393aa74c44bSWells Lu D(7, 0), D(7, 1), D(7, 2), D(7, 3), D(7, 4), D(7, 5), D(7, 6), D(7, 7), 394aa74c44bSWells Lu D(8, 0), D(8, 1), D(8, 2), D(8, 3), D(8, 4), D(8, 5), D(8, 6), D(8, 7), 395aa74c44bSWells Lu D(9, 0), D(9, 1), D(9, 2), D(9, 3), D(9, 4), D(9, 5), D(9, 6), D(9, 7), 396aa74c44bSWells Lu D(10, 0), D(10, 1), D(10, 2), D(10, 3), D(10, 4), D(10, 5), D(10, 6), D(10, 7), 397aa74c44bSWells Lu }; 398aa74c44bSWells Lu 399aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_upex[] = { 400aa74c44bSWells Lu EGRP("UPHY0_EXT", 1, pins_upex), 401aa74c44bSWells Lu }; 402aa74c44bSWells Lu 403aa74c44bSWells Lu static const unsigned int pins_prp1[] = { 404aa74c44bSWells Lu D(0, 6), D(0, 7), 405aa74c44bSWells Lu D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), D(1, 6), D(1, 7), 406aa74c44bSWells Lu D(2, 1), D(2, 2), D(2, 3), D(2, 4), D(2, 5), D(2, 6), D(2, 7), 407aa74c44bSWells Lu D(3, 0), D(3, 1), D(3, 2), 408aa74c44bSWells Lu }; 409aa74c44bSWells Lu 410aa74c44bSWells Lu static const unsigned int pins_prp2[] = { 411aa74c44bSWells Lu D(3, 4), D(3, 6), D(3, 7), 412aa74c44bSWells Lu D(4, 0), D(4, 1), D(4, 2), D(4, 3), D(4, 4), D(4, 5), D(4, 6), D(4, 7), 413aa74c44bSWells Lu D(5, 0), D(5, 1), D(5, 2), D(5, 3), D(5, 4), D(5, 5), D(5, 6), D(5, 7), 414aa74c44bSWells Lu D(6, 4), 415aa74c44bSWells Lu }; 416aa74c44bSWells Lu 417aa74c44bSWells Lu static const struct sppctl_grp sp7021grps_prbp[] = { 418aa74c44bSWells Lu EGRP("PROBE_PORT1", 1, pins_prp1), 419aa74c44bSWells Lu EGRP("PROBE_PORT2", 2, pins_prp2), 420aa74c44bSWells Lu }; 421aa74c44bSWells Lu 422*08b7cf13SWells Lu /* 423*08b7cf13SWells Lu * Due to compatible reason, the first valid item should start at the third 424*08b7cf13SWells Lu * position of the array. Please keep the first two items of the table 425*08b7cf13SWells Lu * no use (dummy). 426*08b7cf13SWells Lu */ 427aa74c44bSWells Lu const struct sppctl_func sppctl_list_funcs[] = { 428*08b7cf13SWells Lu FNCN("", pinmux_type_fpmx, 0x00, 0, 0), 429*08b7cf13SWells Lu FNCN("", pinmux_type_fpmx, 0x00, 0, 0), 430*08b7cf13SWells Lu 431aa74c44bSWells Lu FNCN("L2SW_CLK_OUT", pinmux_type_fpmx, 0x00, 0, 7), 432aa74c44bSWells Lu FNCN("L2SW_MAC_SMI_MDC", pinmux_type_fpmx, 0x00, 8, 7), 433aa74c44bSWells Lu FNCN("L2SW_LED_FLASH0", pinmux_type_fpmx, 0x01, 0, 7), 434aa74c44bSWells Lu FNCN("L2SW_LED_FLASH1", pinmux_type_fpmx, 0x01, 8, 7), 435aa74c44bSWells Lu FNCN("L2SW_LED_ON0", pinmux_type_fpmx, 0x02, 0, 7), 436aa74c44bSWells Lu FNCN("L2SW_LED_ON1", pinmux_type_fpmx, 0x02, 8, 7), 437aa74c44bSWells Lu FNCN("L2SW_MAC_SMI_MDIO", pinmux_type_fpmx, 0x03, 0, 7), 438aa74c44bSWells Lu FNCN("L2SW_P0_MAC_RMII_TXEN", pinmux_type_fpmx, 0x03, 8, 7), 439aa74c44bSWells Lu FNCN("L2SW_P0_MAC_RMII_TXD0", pinmux_type_fpmx, 0x04, 0, 7), 440aa74c44bSWells Lu FNCN("L2SW_P0_MAC_RMII_TXD1", pinmux_type_fpmx, 0x04, 8, 7), 441aa74c44bSWells Lu FNCN("L2SW_P0_MAC_RMII_CRSDV", pinmux_type_fpmx, 0x05, 0, 7), 442aa74c44bSWells Lu FNCN("L2SW_P0_MAC_RMII_RXD0", pinmux_type_fpmx, 0x05, 8, 7), 443aa74c44bSWells Lu FNCN("L2SW_P0_MAC_RMII_RXD1", pinmux_type_fpmx, 0x06, 0, 7), 444aa74c44bSWells Lu FNCN("L2SW_P0_MAC_RMII_RXER", pinmux_type_fpmx, 0x06, 8, 7), 445aa74c44bSWells Lu FNCN("L2SW_P1_MAC_RMII_TXEN", pinmux_type_fpmx, 0x07, 0, 7), 446aa74c44bSWells Lu FNCN("L2SW_P1_MAC_RMII_TXD0", pinmux_type_fpmx, 0x07, 8, 7), 447aa74c44bSWells Lu FNCN("L2SW_P1_MAC_RMII_TXD1", pinmux_type_fpmx, 0x08, 0, 7), 448aa74c44bSWells Lu FNCN("L2SW_P1_MAC_RMII_CRSDV", pinmux_type_fpmx, 0x08, 8, 7), 449aa74c44bSWells Lu FNCN("L2SW_P1_MAC_RMII_RXD0", pinmux_type_fpmx, 0x09, 0, 7), 450aa74c44bSWells Lu FNCN("L2SW_P1_MAC_RMII_RXD1", pinmux_type_fpmx, 0x09, 8, 7), 451aa74c44bSWells Lu FNCN("L2SW_P1_MAC_RMII_RXER", pinmux_type_fpmx, 0x0A, 0, 7), 452aa74c44bSWells Lu FNCN("DAISY_MODE", pinmux_type_fpmx, 0x0A, 8, 7), 453aa74c44bSWells Lu FNCN("SDIO_CLK", pinmux_type_fpmx, 0x0B, 0, 7), /* 1x SDIO */ 454aa74c44bSWells Lu FNCN("SDIO_CMD", pinmux_type_fpmx, 0x0B, 8, 7), 455aa74c44bSWells Lu FNCN("SDIO_D0", pinmux_type_fpmx, 0x0C, 0, 7), 456aa74c44bSWells Lu FNCN("SDIO_D1", pinmux_type_fpmx, 0x0C, 8, 7), 457aa74c44bSWells Lu FNCN("SDIO_D2", pinmux_type_fpmx, 0x0D, 0, 7), 458aa74c44bSWells Lu FNCN("SDIO_D3", pinmux_type_fpmx, 0x0D, 8, 7), 459aa74c44bSWells Lu FNCN("PWM0", pinmux_type_fpmx, 0x0E, 0, 7), /* 8x PWM */ 460aa74c44bSWells Lu FNCN("PWM1", pinmux_type_fpmx, 0x0E, 8, 7), 461aa74c44bSWells Lu FNCN("PWM2", pinmux_type_fpmx, 0x0F, 0, 7), 462aa74c44bSWells Lu FNCN("PWM3", pinmux_type_fpmx, 0x0F, 8, 7), 463aa74c44bSWells Lu 464aa74c44bSWells Lu FNCN("PWM4", pinmux_type_fpmx, 0x10, 0, 7), 465aa74c44bSWells Lu FNCN("PWM5", pinmux_type_fpmx, 0x10, 8, 7), 466aa74c44bSWells Lu FNCN("PWM6", pinmux_type_fpmx, 0x11, 0, 7), 467aa74c44bSWells Lu FNCN("PWM7", pinmux_type_fpmx, 0x11, 8, 7), 468aa74c44bSWells Lu FNCN("ICM0_D", pinmux_type_fpmx, 0x12, 0, 7), /* 4x Input captures */ 469aa74c44bSWells Lu FNCN("ICM1_D", pinmux_type_fpmx, 0x12, 8, 7), 470aa74c44bSWells Lu FNCN("ICM2_D", pinmux_type_fpmx, 0x13, 0, 7), 471aa74c44bSWells Lu FNCN("ICM3_D", pinmux_type_fpmx, 0x13, 8, 7), 472aa74c44bSWells Lu FNCN("ICM0_CLK", pinmux_type_fpmx, 0x14, 0, 7), 473aa74c44bSWells Lu FNCN("ICM1_CLK", pinmux_type_fpmx, 0x14, 8, 7), 474aa74c44bSWells Lu FNCN("ICM2_CLK", pinmux_type_fpmx, 0x15, 0, 7), 475aa74c44bSWells Lu FNCN("ICM3_CLK", pinmux_type_fpmx, 0x15, 8, 7), 476aa74c44bSWells Lu FNCN("SPIM0_INT", pinmux_type_fpmx, 0x16, 0, 7), /* 4x SPI masters */ 477aa74c44bSWells Lu FNCN("SPIM0_CLK", pinmux_type_fpmx, 0x16, 8, 7), 478aa74c44bSWells Lu FNCN("SPIM0_EN", pinmux_type_fpmx, 0x17, 0, 7), 479aa74c44bSWells Lu FNCN("SPIM0_DO", pinmux_type_fpmx, 0x17, 8, 7), 480aa74c44bSWells Lu FNCN("SPIM0_DI", pinmux_type_fpmx, 0x18, 0, 7), 481aa74c44bSWells Lu FNCN("SPIM1_INT", pinmux_type_fpmx, 0x18, 8, 7), 482aa74c44bSWells Lu FNCN("SPIM1_CLK", pinmux_type_fpmx, 0x19, 0, 7), 483aa74c44bSWells Lu FNCN("SPIM1_EN", pinmux_type_fpmx, 0x19, 8, 7), 484aa74c44bSWells Lu FNCN("SPIM1_DO", pinmux_type_fpmx, 0x1A, 0, 7), 485aa74c44bSWells Lu FNCN("SPIM1_DI", pinmux_type_fpmx, 0x1A, 8, 7), 486aa74c44bSWells Lu FNCN("SPIM2_INT", pinmux_type_fpmx, 0x1B, 0, 7), 487aa74c44bSWells Lu FNCN("SPIM2_CLK", pinmux_type_fpmx, 0x1B, 8, 7), 488aa74c44bSWells Lu FNCN("SPIM2_EN", pinmux_type_fpmx, 0x1C, 0, 7), 489aa74c44bSWells Lu FNCN("SPIM2_DO", pinmux_type_fpmx, 0x1C, 8, 7), 490aa74c44bSWells Lu FNCN("SPIM2_DI", pinmux_type_fpmx, 0x1D, 0, 7), 491aa74c44bSWells Lu FNCN("SPIM3_INT", pinmux_type_fpmx, 0x1D, 8, 7), 492aa74c44bSWells Lu FNCN("SPIM3_CLK", pinmux_type_fpmx, 0x1E, 0, 7), 493aa74c44bSWells Lu FNCN("SPIM3_EN", pinmux_type_fpmx, 0x1E, 8, 7), 494aa74c44bSWells Lu FNCN("SPIM3_DO", pinmux_type_fpmx, 0x1F, 0, 7), 495aa74c44bSWells Lu FNCN("SPIM3_DI", pinmux_type_fpmx, 0x1F, 8, 7), 496aa74c44bSWells Lu 497aa74c44bSWells Lu FNCN("SPI0S_INT", pinmux_type_fpmx, 0x20, 0, 7), /* 4x SPI slaves */ 498aa74c44bSWells Lu FNCN("SPI0S_CLK", pinmux_type_fpmx, 0x20, 8, 7), 499aa74c44bSWells Lu FNCN("SPI0S_EN", pinmux_type_fpmx, 0x21, 0, 7), 500aa74c44bSWells Lu FNCN("SPI0S_DO", pinmux_type_fpmx, 0x21, 8, 7), 501aa74c44bSWells Lu FNCN("SPI0S_DI", pinmux_type_fpmx, 0x22, 0, 7), 502aa74c44bSWells Lu FNCN("SPI1S_INT", pinmux_type_fpmx, 0x22, 8, 7), 503aa74c44bSWells Lu FNCN("SPI1S_CLK", pinmux_type_fpmx, 0x23, 0, 7), 504aa74c44bSWells Lu FNCN("SPI1S_EN", pinmux_type_fpmx, 0x23, 8, 7), 505aa74c44bSWells Lu FNCN("SPI1S_DO", pinmux_type_fpmx, 0x24, 0, 7), 506aa74c44bSWells Lu FNCN("SPI1S_DI", pinmux_type_fpmx, 0x24, 8, 7), 507aa74c44bSWells Lu FNCN("SPI2S_INT", pinmux_type_fpmx, 0x25, 0, 7), 508aa74c44bSWells Lu FNCN("SPI2S_CLK", pinmux_type_fpmx, 0x25, 8, 7), 509aa74c44bSWells Lu FNCN("SPI2S_EN", pinmux_type_fpmx, 0x26, 0, 7), 510aa74c44bSWells Lu FNCN("SPI2S_DO", pinmux_type_fpmx, 0x26, 8, 7), 511aa74c44bSWells Lu FNCN("SPI2S_DI", pinmux_type_fpmx, 0x27, 0, 7), 512aa74c44bSWells Lu FNCN("SPI3S_INT", pinmux_type_fpmx, 0x27, 8, 7), 513aa74c44bSWells Lu FNCN("SPI3S_CLK", pinmux_type_fpmx, 0x28, 0, 7), 514aa74c44bSWells Lu FNCN("SPI3S_EN", pinmux_type_fpmx, 0x28, 8, 7), 515aa74c44bSWells Lu FNCN("SPI3S_DO", pinmux_type_fpmx, 0x29, 0, 7), 516aa74c44bSWells Lu FNCN("SPI3S_DI", pinmux_type_fpmx, 0x29, 8, 7), 517aa74c44bSWells Lu FNCN("I2CM0_CLK", pinmux_type_fpmx, 0x2A, 0, 7), /* 4x I2C masters */ 518aa74c44bSWells Lu FNCN("I2CM0_DAT", pinmux_type_fpmx, 0x2A, 8, 7), 519aa74c44bSWells Lu FNCN("I2CM1_CLK", pinmux_type_fpmx, 0x2B, 0, 7), 520aa74c44bSWells Lu FNCN("I2CM1_DAT", pinmux_type_fpmx, 0x2B, 8, 7), 521aa74c44bSWells Lu FNCN("I2CM2_CLK", pinmux_type_fpmx, 0x2C, 0, 7), 522aa74c44bSWells Lu FNCN("I2CM2_DAT", pinmux_type_fpmx, 0x2C, 8, 7), 523aa74c44bSWells Lu FNCN("I2CM3_CLK", pinmux_type_fpmx, 0x2D, 0, 7), 524aa74c44bSWells Lu FNCN("I2CM3_DAT", pinmux_type_fpmx, 0x2D, 8, 7), 525aa74c44bSWells Lu FNCN("UA1_TX", pinmux_type_fpmx, 0x2E, 0, 7), /* 4x UARTS */ 526aa74c44bSWells Lu FNCN("UA1_RX", pinmux_type_fpmx, 0x2E, 8, 7), 527aa74c44bSWells Lu FNCN("UA1_CTS", pinmux_type_fpmx, 0x2F, 0, 7), 528aa74c44bSWells Lu FNCN("UA1_RTS", pinmux_type_fpmx, 0x2F, 8, 7), 529aa74c44bSWells Lu 530aa74c44bSWells Lu FNCN("UA2_TX", pinmux_type_fpmx, 0x30, 0, 7), 531aa74c44bSWells Lu FNCN("UA2_RX", pinmux_type_fpmx, 0x30, 8, 7), 532aa74c44bSWells Lu FNCN("UA2_CTS", pinmux_type_fpmx, 0x31, 0, 7), 533aa74c44bSWells Lu FNCN("UA2_RTS", pinmux_type_fpmx, 0x31, 8, 7), 534aa74c44bSWells Lu FNCN("UA3_TX", pinmux_type_fpmx, 0x32, 0, 7), 535aa74c44bSWells Lu FNCN("UA3_RX", pinmux_type_fpmx, 0x32, 8, 7), 536aa74c44bSWells Lu FNCN("UA3_CTS", pinmux_type_fpmx, 0x33, 0, 7), 537aa74c44bSWells Lu FNCN("UA3_RTS", pinmux_type_fpmx, 0x33, 8, 7), 538aa74c44bSWells Lu FNCN("UA4_TX", pinmux_type_fpmx, 0x34, 0, 7), 539aa74c44bSWells Lu FNCN("UA4_RX", pinmux_type_fpmx, 0x34, 8, 7), 540aa74c44bSWells Lu FNCN("UA4_CTS", pinmux_type_fpmx, 0x35, 0, 7), 541aa74c44bSWells Lu FNCN("UA4_RTS", pinmux_type_fpmx, 0x35, 8, 7), 542aa74c44bSWells Lu FNCN("TIMER0_INT", pinmux_type_fpmx, 0x36, 0, 7), /* 4x timer int. */ 543aa74c44bSWells Lu FNCN("TIMER1_INT", pinmux_type_fpmx, 0x36, 8, 7), 544aa74c44bSWells Lu FNCN("TIMER2_INT", pinmux_type_fpmx, 0x37, 0, 7), 545aa74c44bSWells Lu FNCN("TIMER3_INT", pinmux_type_fpmx, 0x37, 8, 7), 546aa74c44bSWells Lu FNCN("GPIO_INT0", pinmux_type_fpmx, 0x38, 0, 7), /* 8x GPIO int. */ 547aa74c44bSWells Lu FNCN("GPIO_INT1", pinmux_type_fpmx, 0x38, 8, 7), 548aa74c44bSWells Lu FNCN("GPIO_INT2", pinmux_type_fpmx, 0x39, 0, 7), 549aa74c44bSWells Lu FNCN("GPIO_INT3", pinmux_type_fpmx, 0x39, 8, 7), 550aa74c44bSWells Lu FNCN("GPIO_INT4", pinmux_type_fpmx, 0x3A, 0, 7), 551aa74c44bSWells Lu FNCN("GPIO_INT5", pinmux_type_fpmx, 0x3A, 8, 7), 552aa74c44bSWells Lu FNCN("GPIO_INT6", pinmux_type_fpmx, 0x3B, 0, 7), 553aa74c44bSWells Lu FNCN("GPIO_INT7", pinmux_type_fpmx, 0x3B, 8, 7), 554aa74c44bSWells Lu 555aa74c44bSWells Lu /* MOON1 register */ 556aa74c44bSWells Lu FNCE("SPI_FLASH", pinmux_type_grp, 0x01, 0, 2, sp7021grps_spif), 557aa74c44bSWells Lu FNCE("SPI_FLASH_4BIT", pinmux_type_grp, 0x01, 2, 2, sp7021grps_spi4), 558aa74c44bSWells Lu FNCE("SPI_NAND", pinmux_type_grp, 0x01, 4, 1, sp7021grps_snan), 559aa74c44bSWells Lu FNCE("CARD0_EMMC", pinmux_type_grp, 0x01, 5, 1, sp7021grps_emmc), 560aa74c44bSWells Lu FNCE("SD_CARD", pinmux_type_grp, 0x01, 6, 1, sp7021grps_sdsd), 561aa74c44bSWells Lu FNCE("UA0", pinmux_type_grp, 0x01, 7, 1, sp7021grps_uar0), 562aa74c44bSWells Lu FNCE("ACHIP_DEBUG", pinmux_type_grp, 0x01, 8, 2, sp7021grps_adbg), 563aa74c44bSWells Lu FNCE("ACHIP_UA2AXI", pinmux_type_grp, 0x01, 10, 2, sp7021grps_au2x), 564aa74c44bSWells Lu FNCE("FPGA_IFX", pinmux_type_grp, 0x01, 12, 1, sp7021grps_fpga), 565aa74c44bSWells Lu FNCE("HDMI_TX", pinmux_type_grp, 0x01, 13, 2, sp7021grps_hdmi), 566aa74c44bSWells Lu 567aa74c44bSWells Lu FNCE("AUD_EXT_ADC_IFX0", pinmux_type_grp, 0x01, 15, 1, sp7021grps_eadc), 568aa74c44bSWells Lu FNCE("AUD_EXT_DAC_IFX0", pinmux_type_grp, 0x02, 0, 1, sp7021grps_edac), 569aa74c44bSWells Lu FNCE("SPDIF_RX", pinmux_type_grp, 0x02, 2, 1, sp7021grps_spdi), 570aa74c44bSWells Lu FNCE("SPDIF_TX", pinmux_type_grp, 0x02, 3, 1, sp7021grps_spdo), 571aa74c44bSWells Lu FNCE("TDMTX_IFX0", pinmux_type_grp, 0x02, 4, 1, sp7021grps_tdmt), 572aa74c44bSWells Lu FNCE("TDMRX_IFX0", pinmux_type_grp, 0x02, 5, 1, sp7021grps_tdmr), 573aa74c44bSWells Lu FNCE("PDMRX_IFX0", pinmux_type_grp, 0x02, 6, 1, sp7021grps_pdmr), 574aa74c44bSWells Lu FNCE("PCM_IEC_TX", pinmux_type_grp, 0x02, 7, 1, sp7021grps_pcmt), 575aa74c44bSWells Lu FNCE("LCDIF", pinmux_type_grp, 0x04, 6, 1, sp7021grps_lcdi), 576aa74c44bSWells Lu FNCE("DVD_DSP_DEBUG", pinmux_type_grp, 0x02, 8, 1, sp7021grps_dvdd), 577aa74c44bSWells Lu FNCE("I2C_DEBUG", pinmux_type_grp, 0x02, 9, 1, sp7021grps_i2cd), 578aa74c44bSWells Lu FNCE("I2C_SLAVE", pinmux_type_grp, 0x02, 10, 1, sp7021grps_i2cs), 579aa74c44bSWells Lu FNCE("WAKEUP", pinmux_type_grp, 0x02, 11, 1, sp7021grps_wakp), 580aa74c44bSWells Lu FNCE("UART2AXI", pinmux_type_grp, 0x02, 12, 2, sp7021grps_u2ax), 581aa74c44bSWells Lu FNCE("USB0_I2C", pinmux_type_grp, 0x02, 14, 2, sp7021grps_u0ic), 582aa74c44bSWells Lu FNCE("USB1_I2C", pinmux_type_grp, 0x03, 0, 2, sp7021grps_u1ic), 583aa74c44bSWells Lu FNCE("USB0_OTG", pinmux_type_grp, 0x03, 2, 1, sp7021grps_u0ot), 584aa74c44bSWells Lu FNCE("USB1_OTG", pinmux_type_grp, 0x03, 3, 1, sp7021grps_u1ot), 585aa74c44bSWells Lu FNCE("UPHY0_DEBUG", pinmux_type_grp, 0x03, 4, 1, sp7021grps_up0d), 586aa74c44bSWells Lu FNCE("UPHY1_DEBUG", pinmux_type_grp, 0x03, 5, 1, sp7021grps_up1d), 587aa74c44bSWells Lu FNCE("UPHY0_EXT", pinmux_type_grp, 0x03, 6, 1, sp7021grps_upex), 588aa74c44bSWells Lu FNCE("PROBE_PORT", pinmux_type_grp, 0x03, 7, 2, sp7021grps_prbp), 589aa74c44bSWells Lu }; 590aa74c44bSWells Lu 591aa74c44bSWells Lu const size_t sppctl_list_funcs_sz = ARRAY_SIZE(sppctl_list_funcs); 592