1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) Maxime Coquelin 2015
4  * Copyright (C) STMicroelectronics 2017
5  * Author:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
6  *
7  * Heavily based on Mediatek's pinctrl driver
8  */
9 #include <linux/clk.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/hwspinlock.h>
12 #include <linux/io.h>
13 #include <linux/irq.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/of_address.h>
18 #include <linux/of_device.h>
19 #include <linux/of_irq.h>
20 #include <linux/pinctrl/consumer.h>
21 #include <linux/pinctrl/machine.h>
22 #include <linux/pinctrl/pinconf.h>
23 #include <linux/pinctrl/pinconf-generic.h>
24 #include <linux/pinctrl/pinctrl.h>
25 #include <linux/pinctrl/pinmux.h>
26 #include <linux/platform_device.h>
27 #include <linux/regmap.h>
28 #include <linux/reset.h>
29 #include <linux/slab.h>
30 
31 #include "../core.h"
32 #include "../pinconf.h"
33 #include "../pinctrl-utils.h"
34 #include "pinctrl-stm32.h"
35 
36 #define STM32_GPIO_MODER	0x00
37 #define STM32_GPIO_TYPER	0x04
38 #define STM32_GPIO_SPEEDR	0x08
39 #define STM32_GPIO_PUPDR	0x0c
40 #define STM32_GPIO_IDR		0x10
41 #define STM32_GPIO_ODR		0x14
42 #define STM32_GPIO_BSRR		0x18
43 #define STM32_GPIO_LCKR		0x1c
44 #define STM32_GPIO_AFRL		0x20
45 #define STM32_GPIO_AFRH		0x24
46 
47 /* custom bitfield to backup pin status */
48 #define STM32_GPIO_BKP_MODE_SHIFT	0
49 #define STM32_GPIO_BKP_MODE_MASK	GENMASK(1, 0)
50 #define STM32_GPIO_BKP_ALT_SHIFT	2
51 #define STM32_GPIO_BKP_ALT_MASK		GENMASK(5, 2)
52 #define STM32_GPIO_BKP_SPEED_SHIFT	6
53 #define STM32_GPIO_BKP_SPEED_MASK	GENMASK(7, 6)
54 #define STM32_GPIO_BKP_PUPD_SHIFT	8
55 #define STM32_GPIO_BKP_PUPD_MASK	GENMASK(9, 8)
56 #define STM32_GPIO_BKP_TYPE		10
57 #define STM32_GPIO_BKP_VAL		11
58 
59 #define STM32_GPIO_PINS_PER_BANK 16
60 #define STM32_GPIO_IRQ_LINE	 16
61 
62 #define SYSCFG_IRQMUX_MASK GENMASK(3, 0)
63 
64 #define gpio_range_to_bank(chip) \
65 		container_of(chip, struct stm32_gpio_bank, range)
66 
67 #define HWSPINLOCK_TIMEOUT	5 /* msec */
68 
69 static const char * const stm32_gpio_functions[] = {
70 	"gpio", "af0", "af1",
71 	"af2", "af3", "af4",
72 	"af5", "af6", "af7",
73 	"af8", "af9", "af10",
74 	"af11", "af12", "af13",
75 	"af14", "af15", "analog",
76 };
77 
78 struct stm32_pinctrl_group {
79 	const char *name;
80 	unsigned long config;
81 	unsigned pin;
82 };
83 
84 struct stm32_gpio_bank {
85 	void __iomem *base;
86 	struct clk *clk;
87 	spinlock_t lock;
88 	struct gpio_chip gpio_chip;
89 	struct pinctrl_gpio_range range;
90 	struct fwnode_handle *fwnode;
91 	struct irq_domain *domain;
92 	u32 bank_nr;
93 	u32 bank_ioport_nr;
94 	u32 pin_backup[STM32_GPIO_PINS_PER_BANK];
95 };
96 
97 struct stm32_pinctrl {
98 	struct device *dev;
99 	struct pinctrl_dev *pctl_dev;
100 	struct pinctrl_desc pctl_desc;
101 	struct stm32_pinctrl_group *groups;
102 	unsigned ngroups;
103 	const char **grp_names;
104 	struct stm32_gpio_bank *banks;
105 	unsigned nbanks;
106 	const struct stm32_pinctrl_match_data *match_data;
107 	struct irq_domain	*domain;
108 	struct regmap		*regmap;
109 	struct regmap_field	*irqmux[STM32_GPIO_PINS_PER_BANK];
110 	struct hwspinlock *hwlock;
111 	struct stm32_desc_pin *pins;
112 	u32 npins;
113 	u32 pkg;
114 	u16 irqmux_map;
115 	spinlock_t irqmux_lock;
116 };
117 
118 static inline int stm32_gpio_pin(int gpio)
119 {
120 	return gpio % STM32_GPIO_PINS_PER_BANK;
121 }
122 
123 static inline u32 stm32_gpio_get_mode(u32 function)
124 {
125 	switch (function) {
126 	case STM32_PIN_GPIO:
127 		return 0;
128 	case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
129 		return 2;
130 	case STM32_PIN_ANALOG:
131 		return 3;
132 	}
133 
134 	return 0;
135 }
136 
137 static inline u32 stm32_gpio_get_alt(u32 function)
138 {
139 	switch (function) {
140 	case STM32_PIN_GPIO:
141 		return 0;
142 	case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
143 		return function - 1;
144 	case STM32_PIN_ANALOG:
145 		return 0;
146 	}
147 
148 	return 0;
149 }
150 
151 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank,
152 				    u32 offset, u32 value)
153 {
154 	bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL);
155 	bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL;
156 }
157 
158 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset,
159 				   u32 mode, u32 alt)
160 {
161 	bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK |
162 				      STM32_GPIO_BKP_ALT_MASK);
163 	bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT;
164 	bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT;
165 }
166 
167 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset,
168 				      u32 drive)
169 {
170 	bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE);
171 	bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE;
172 }
173 
174 static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset,
175 				    u32 speed)
176 {
177 	bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK;
178 	bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT;
179 }
180 
181 static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset,
182 				   u32 bias)
183 {
184 	bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK;
185 	bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT;
186 }
187 
188 /* GPIO functions */
189 
190 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,
191 	unsigned offset, int value)
192 {
193 	stm32_gpio_backup_value(bank, offset, value);
194 
195 	if (!value)
196 		offset += STM32_GPIO_PINS_PER_BANK;
197 
198 	clk_enable(bank->clk);
199 
200 	writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR);
201 
202 	clk_disable(bank->clk);
203 }
204 
205 static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset)
206 {
207 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
208 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
209 	struct pinctrl_gpio_range *range;
210 	int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK);
211 
212 	range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin);
213 	if (!range) {
214 		dev_err(pctl->dev, "pin %d not in range.\n", pin);
215 		return -EINVAL;
216 	}
217 
218 	return pinctrl_gpio_request(chip->base + offset);
219 }
220 
221 static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset)
222 {
223 	pinctrl_gpio_free(chip->base + offset);
224 }
225 
226 static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset)
227 {
228 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
229 	int ret;
230 
231 	clk_enable(bank->clk);
232 
233 	ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
234 
235 	clk_disable(bank->clk);
236 
237 	return ret;
238 }
239 
240 static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
241 {
242 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
243 
244 	__stm32_gpio_set(bank, offset, value);
245 }
246 
247 static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
248 {
249 	return pinctrl_gpio_direction_input(chip->base + offset);
250 }
251 
252 static int stm32_gpio_direction_output(struct gpio_chip *chip,
253 	unsigned offset, int value)
254 {
255 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
256 
257 	__stm32_gpio_set(bank, offset, value);
258 	pinctrl_gpio_direction_output(chip->base + offset);
259 
260 	return 0;
261 }
262 
263 
264 static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
265 {
266 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
267 	struct irq_fwspec fwspec;
268 
269 	fwspec.fwnode = bank->fwnode;
270 	fwspec.param_count = 2;
271 	fwspec.param[0] = offset;
272 	fwspec.param[1] = IRQ_TYPE_NONE;
273 
274 	return irq_create_fwspec_mapping(&fwspec);
275 }
276 
277 static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
278 {
279 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
280 	int pin = stm32_gpio_pin(offset);
281 	int ret;
282 	u32 mode, alt;
283 
284 	stm32_pmx_get_mode(bank, pin, &mode, &alt);
285 	if ((alt == 0) && (mode == 0))
286 		ret = 1;
287 	else if ((alt == 0) && (mode == 1))
288 		ret = 0;
289 	else
290 		ret = -EINVAL;
291 
292 	return ret;
293 }
294 
295 static const struct gpio_chip stm32_gpio_template = {
296 	.request		= stm32_gpio_request,
297 	.free			= stm32_gpio_free,
298 	.get			= stm32_gpio_get,
299 	.set			= stm32_gpio_set,
300 	.direction_input	= stm32_gpio_direction_input,
301 	.direction_output	= stm32_gpio_direction_output,
302 	.to_irq			= stm32_gpio_to_irq,
303 	.get_direction		= stm32_gpio_get_direction,
304 };
305 
306 static int stm32_gpio_irq_request_resources(struct irq_data *irq_data)
307 {
308 	struct stm32_gpio_bank *bank = irq_data->domain->host_data;
309 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
310 	int ret;
311 
312 	ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);
313 	if (ret)
314 		return ret;
315 
316 	ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq);
317 	if (ret) {
318 		dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
319 			irq_data->hwirq);
320 		return ret;
321 	}
322 
323 	return 0;
324 }
325 
326 static void stm32_gpio_irq_release_resources(struct irq_data *irq_data)
327 {
328 	struct stm32_gpio_bank *bank = irq_data->domain->host_data;
329 
330 	gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq);
331 }
332 
333 static struct irq_chip stm32_gpio_irq_chip = {
334 	.name		= "stm32gpio",
335 	.irq_eoi	= irq_chip_eoi_parent,
336 	.irq_ack	= irq_chip_ack_parent,
337 	.irq_mask	= irq_chip_mask_parent,
338 	.irq_unmask	= irq_chip_unmask_parent,
339 	.irq_set_type	= irq_chip_set_type_parent,
340 	.irq_set_wake	= irq_chip_set_wake_parent,
341 	.irq_request_resources = stm32_gpio_irq_request_resources,
342 	.irq_release_resources = stm32_gpio_irq_release_resources,
343 };
344 
345 static int stm32_gpio_domain_translate(struct irq_domain *d,
346 				       struct irq_fwspec *fwspec,
347 				       unsigned long *hwirq,
348 				       unsigned int *type)
349 {
350 	if ((fwspec->param_count != 2) ||
351 	    (fwspec->param[0] >= STM32_GPIO_IRQ_LINE))
352 		return -EINVAL;
353 
354 	*hwirq = fwspec->param[0];
355 	*type = fwspec->param[1];
356 	return 0;
357 }
358 
359 static int stm32_gpio_domain_activate(struct irq_domain *d,
360 				      struct irq_data *irq_data, bool reserve)
361 {
362 	struct stm32_gpio_bank *bank = d->host_data;
363 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
364 	unsigned long flags;
365 	int ret = 0;
366 
367 	/*
368 	 * gpio irq mux is shared between several banks, a lock has to be done
369 	 * to avoid overriding.
370 	 */
371 	spin_lock_irqsave(&pctl->irqmux_lock, flags);
372 	if (pctl->hwlock)
373 		ret = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);
374 
375 	if (ret) {
376 		dev_err(pctl->dev, "Can't get hwspinlock\n");
377 		goto unlock;
378 	}
379 
380 	if (pctl->irqmux_map & BIT(irq_data->hwirq)) {
381 		dev_err(pctl->dev, "irq line %ld already requested.\n",
382 			irq_data->hwirq);
383 		ret = -EBUSY;
384 		if (pctl->hwlock)
385 			hwspin_unlock(pctl->hwlock);
386 		goto unlock;
387 	} else {
388 		pctl->irqmux_map |= BIT(irq_data->hwirq);
389 	}
390 
391 	regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr);
392 
393 	if (pctl->hwlock)
394 		hwspin_unlock(pctl->hwlock);
395 
396 unlock:
397 	spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
398 	return ret;
399 }
400 
401 static void stm32_gpio_domain_deactivate(struct irq_domain *d,
402 					 struct irq_data *irq_data)
403 {
404 	struct stm32_gpio_bank *bank = d->host_data;
405 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
406 	unsigned long flags;
407 
408 	spin_lock_irqsave(&pctl->irqmux_lock, flags);
409 	pctl->irqmux_map &= ~BIT(irq_data->hwirq);
410 	spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
411 }
412 
413 static int stm32_gpio_domain_alloc(struct irq_domain *d,
414 				   unsigned int virq,
415 				   unsigned int nr_irqs, void *data)
416 {
417 	struct stm32_gpio_bank *bank = d->host_data;
418 	struct irq_fwspec *fwspec = data;
419 	struct irq_fwspec parent_fwspec;
420 	irq_hw_number_t hwirq;
421 
422 	hwirq = fwspec->param[0];
423 	parent_fwspec.fwnode = d->parent->fwnode;
424 	parent_fwspec.param_count = 2;
425 	parent_fwspec.param[0] = fwspec->param[0];
426 	parent_fwspec.param[1] = fwspec->param[1];
427 
428 	irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip,
429 				      bank);
430 
431 	return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec);
432 }
433 
434 static const struct irq_domain_ops stm32_gpio_domain_ops = {
435 	.translate      = stm32_gpio_domain_translate,
436 	.alloc          = stm32_gpio_domain_alloc,
437 	.free           = irq_domain_free_irqs_common,
438 	.activate	= stm32_gpio_domain_activate,
439 	.deactivate	= stm32_gpio_domain_deactivate,
440 };
441 
442 /* Pinctrl functions */
443 static struct stm32_pinctrl_group *
444 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin)
445 {
446 	int i;
447 
448 	for (i = 0; i < pctl->ngroups; i++) {
449 		struct stm32_pinctrl_group *grp = pctl->groups + i;
450 
451 		if (grp->pin == pin)
452 			return grp;
453 	}
454 
455 	return NULL;
456 }
457 
458 static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl,
459 		u32 pin_num, u32 fnum)
460 {
461 	int i;
462 
463 	for (i = 0; i < pctl->npins; i++) {
464 		const struct stm32_desc_pin *pin = pctl->pins + i;
465 		const struct stm32_desc_function *func = pin->functions;
466 
467 		if (pin->pin.number != pin_num)
468 			continue;
469 
470 		while (func && func->name) {
471 			if (func->num == fnum)
472 				return true;
473 			func++;
474 		}
475 
476 		break;
477 	}
478 
479 	return false;
480 }
481 
482 static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl,
483 		u32 pin, u32 fnum, struct stm32_pinctrl_group *grp,
484 		struct pinctrl_map **map, unsigned *reserved_maps,
485 		unsigned *num_maps)
486 {
487 	if (*num_maps == *reserved_maps)
488 		return -ENOSPC;
489 
490 	(*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
491 	(*map)[*num_maps].data.mux.group = grp->name;
492 
493 	if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) {
494 		dev_err(pctl->dev, "invalid function %d on pin %d .\n",
495 				fnum, pin);
496 		return -EINVAL;
497 	}
498 
499 	(*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum];
500 	(*num_maps)++;
501 
502 	return 0;
503 }
504 
505 static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
506 				      struct device_node *node,
507 				      struct pinctrl_map **map,
508 				      unsigned *reserved_maps,
509 				      unsigned *num_maps)
510 {
511 	struct stm32_pinctrl *pctl;
512 	struct stm32_pinctrl_group *grp;
513 	struct property *pins;
514 	u32 pinfunc, pin, func;
515 	unsigned long *configs;
516 	unsigned int num_configs;
517 	bool has_config = 0;
518 	unsigned reserve = 0;
519 	int num_pins, num_funcs, maps_per_pin, i, err = 0;
520 
521 	pctl = pinctrl_dev_get_drvdata(pctldev);
522 
523 	pins = of_find_property(node, "pinmux", NULL);
524 	if (!pins) {
525 		dev_err(pctl->dev, "missing pins property in node %pOFn .\n",
526 				node);
527 		return -EINVAL;
528 	}
529 
530 	err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
531 		&num_configs);
532 	if (err)
533 		return err;
534 
535 	if (num_configs)
536 		has_config = 1;
537 
538 	num_pins = pins->length / sizeof(u32);
539 	num_funcs = num_pins;
540 	maps_per_pin = 0;
541 	if (num_funcs)
542 		maps_per_pin++;
543 	if (has_config && num_pins >= 1)
544 		maps_per_pin++;
545 
546 	if (!num_pins || !maps_per_pin) {
547 		err = -EINVAL;
548 		goto exit;
549 	}
550 
551 	reserve = num_pins * maps_per_pin;
552 
553 	err = pinctrl_utils_reserve_map(pctldev, map,
554 			reserved_maps, num_maps, reserve);
555 	if (err)
556 		goto exit;
557 
558 	for (i = 0; i < num_pins; i++) {
559 		err = of_property_read_u32_index(node, "pinmux",
560 				i, &pinfunc);
561 		if (err)
562 			goto exit;
563 
564 		pin = STM32_GET_PIN_NO(pinfunc);
565 		func = STM32_GET_PIN_FUNC(pinfunc);
566 
567 		if (!stm32_pctrl_is_function_valid(pctl, pin, func)) {
568 			dev_err(pctl->dev, "invalid function.\n");
569 			err = -EINVAL;
570 			goto exit;
571 		}
572 
573 		grp = stm32_pctrl_find_group_by_pin(pctl, pin);
574 		if (!grp) {
575 			dev_err(pctl->dev, "unable to match pin %d to group\n",
576 					pin);
577 			err = -EINVAL;
578 			goto exit;
579 		}
580 
581 		err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
582 				reserved_maps, num_maps);
583 		if (err)
584 			goto exit;
585 
586 		if (has_config) {
587 			err = pinctrl_utils_add_map_configs(pctldev, map,
588 					reserved_maps, num_maps, grp->name,
589 					configs, num_configs,
590 					PIN_MAP_TYPE_CONFIGS_GROUP);
591 			if (err)
592 				goto exit;
593 		}
594 	}
595 
596 exit:
597 	kfree(configs);
598 	return err;
599 }
600 
601 static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
602 				 struct device_node *np_config,
603 				 struct pinctrl_map **map, unsigned *num_maps)
604 {
605 	struct device_node *np;
606 	unsigned reserved_maps;
607 	int ret;
608 
609 	*map = NULL;
610 	*num_maps = 0;
611 	reserved_maps = 0;
612 
613 	for_each_child_of_node(np_config, np) {
614 		ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map,
615 				&reserved_maps, num_maps);
616 		if (ret < 0) {
617 			pinctrl_utils_free_map(pctldev, *map, *num_maps);
618 			of_node_put(np);
619 			return ret;
620 		}
621 	}
622 
623 	return 0;
624 }
625 
626 static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
627 {
628 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
629 
630 	return pctl->ngroups;
631 }
632 
633 static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev,
634 					      unsigned group)
635 {
636 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
637 
638 	return pctl->groups[group].name;
639 }
640 
641 static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
642 				      unsigned group,
643 				      const unsigned **pins,
644 				      unsigned *num_pins)
645 {
646 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
647 
648 	*pins = (unsigned *)&pctl->groups[group].pin;
649 	*num_pins = 1;
650 
651 	return 0;
652 }
653 
654 static const struct pinctrl_ops stm32_pctrl_ops = {
655 	.dt_node_to_map		= stm32_pctrl_dt_node_to_map,
656 	.dt_free_map		= pinctrl_utils_free_map,
657 	.get_groups_count	= stm32_pctrl_get_groups_count,
658 	.get_group_name		= stm32_pctrl_get_group_name,
659 	.get_group_pins		= stm32_pctrl_get_group_pins,
660 };
661 
662 
663 /* Pinmux functions */
664 
665 static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
666 {
667 	return ARRAY_SIZE(stm32_gpio_functions);
668 }
669 
670 static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev,
671 					   unsigned selector)
672 {
673 	return stm32_gpio_functions[selector];
674 }
675 
676 static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev,
677 				     unsigned function,
678 				     const char * const **groups,
679 				     unsigned * const num_groups)
680 {
681 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
682 
683 	*groups = pctl->grp_names;
684 	*num_groups = pctl->ngroups;
685 
686 	return 0;
687 }
688 
689 static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
690 			      int pin, u32 mode, u32 alt)
691 {
692 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
693 	u32 val;
694 	int alt_shift = (pin % 8) * 4;
695 	int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
696 	unsigned long flags;
697 	int err = 0;
698 
699 	clk_enable(bank->clk);
700 	spin_lock_irqsave(&bank->lock, flags);
701 
702 	if (pctl->hwlock)
703 		err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);
704 
705 	if (err) {
706 		dev_err(pctl->dev, "Can't get hwspinlock\n");
707 		goto unlock;
708 	}
709 
710 	val = readl_relaxed(bank->base + alt_offset);
711 	val &= ~GENMASK(alt_shift + 3, alt_shift);
712 	val |= (alt << alt_shift);
713 	writel_relaxed(val, bank->base + alt_offset);
714 
715 	val = readl_relaxed(bank->base + STM32_GPIO_MODER);
716 	val &= ~GENMASK(pin * 2 + 1, pin * 2);
717 	val |= mode << (pin * 2);
718 	writel_relaxed(val, bank->base + STM32_GPIO_MODER);
719 
720 	if (pctl->hwlock)
721 		hwspin_unlock(pctl->hwlock);
722 
723 	stm32_gpio_backup_mode(bank, pin, mode, alt);
724 
725 unlock:
726 	spin_unlock_irqrestore(&bank->lock, flags);
727 	clk_disable(bank->clk);
728 
729 	return err;
730 }
731 
732 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode,
733 			u32 *alt)
734 {
735 	u32 val;
736 	int alt_shift = (pin % 8) * 4;
737 	int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
738 	unsigned long flags;
739 
740 	clk_enable(bank->clk);
741 	spin_lock_irqsave(&bank->lock, flags);
742 
743 	val = readl_relaxed(bank->base + alt_offset);
744 	val &= GENMASK(alt_shift + 3, alt_shift);
745 	*alt = val >> alt_shift;
746 
747 	val = readl_relaxed(bank->base + STM32_GPIO_MODER);
748 	val &= GENMASK(pin * 2 + 1, pin * 2);
749 	*mode = val >> (pin * 2);
750 
751 	spin_unlock_irqrestore(&bank->lock, flags);
752 	clk_disable(bank->clk);
753 }
754 
755 static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev,
756 			    unsigned function,
757 			    unsigned group)
758 {
759 	bool ret;
760 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
761 	struct stm32_pinctrl_group *g = pctl->groups + group;
762 	struct pinctrl_gpio_range *range;
763 	struct stm32_gpio_bank *bank;
764 	u32 mode, alt;
765 	int pin;
766 
767 	ret = stm32_pctrl_is_function_valid(pctl, g->pin, function);
768 	if (!ret) {
769 		dev_err(pctl->dev, "invalid function %d on group %d .\n",
770 				function, group);
771 		return -EINVAL;
772 	}
773 
774 	range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin);
775 	if (!range) {
776 		dev_err(pctl->dev, "No gpio range defined.\n");
777 		return -EINVAL;
778 	}
779 
780 	bank = gpiochip_get_data(range->gc);
781 	pin = stm32_gpio_pin(g->pin);
782 
783 	mode = stm32_gpio_get_mode(function);
784 	alt = stm32_gpio_get_alt(function);
785 
786 	return stm32_pmx_set_mode(bank, pin, mode, alt);
787 }
788 
789 static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
790 			struct pinctrl_gpio_range *range, unsigned gpio,
791 			bool input)
792 {
793 	struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc);
794 	int pin = stm32_gpio_pin(gpio);
795 
796 	return stm32_pmx_set_mode(bank, pin, !input, 0);
797 }
798 
799 static const struct pinmux_ops stm32_pmx_ops = {
800 	.get_functions_count	= stm32_pmx_get_funcs_cnt,
801 	.get_function_name	= stm32_pmx_get_func_name,
802 	.get_function_groups	= stm32_pmx_get_func_groups,
803 	.set_mux		= stm32_pmx_set_mux,
804 	.gpio_set_direction	= stm32_pmx_gpio_set_direction,
805 	.strict			= true,
806 };
807 
808 /* Pinconf functions */
809 
810 static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
811 				   unsigned offset, u32 drive)
812 {
813 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
814 	unsigned long flags;
815 	u32 val;
816 	int err = 0;
817 
818 	clk_enable(bank->clk);
819 	spin_lock_irqsave(&bank->lock, flags);
820 
821 	if (pctl->hwlock)
822 		err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);
823 
824 	if (err) {
825 		dev_err(pctl->dev, "Can't get hwspinlock\n");
826 		goto unlock;
827 	}
828 
829 	val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
830 	val &= ~BIT(offset);
831 	val |= drive << offset;
832 	writel_relaxed(val, bank->base + STM32_GPIO_TYPER);
833 
834 	if (pctl->hwlock)
835 		hwspin_unlock(pctl->hwlock);
836 
837 	stm32_gpio_backup_driving(bank, offset, drive);
838 
839 unlock:
840 	spin_unlock_irqrestore(&bank->lock, flags);
841 	clk_disable(bank->clk);
842 
843 	return err;
844 }
845 
846 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank,
847 	unsigned int offset)
848 {
849 	unsigned long flags;
850 	u32 val;
851 
852 	clk_enable(bank->clk);
853 	spin_lock_irqsave(&bank->lock, flags);
854 
855 	val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
856 	val &= BIT(offset);
857 
858 	spin_unlock_irqrestore(&bank->lock, flags);
859 	clk_disable(bank->clk);
860 
861 	return (val >> offset);
862 }
863 
864 static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
865 				 unsigned offset, u32 speed)
866 {
867 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
868 	unsigned long flags;
869 	u32 val;
870 	int err = 0;
871 
872 	clk_enable(bank->clk);
873 	spin_lock_irqsave(&bank->lock, flags);
874 
875 	if (pctl->hwlock)
876 		err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);
877 
878 	if (err) {
879 		dev_err(pctl->dev, "Can't get hwspinlock\n");
880 		goto unlock;
881 	}
882 
883 	val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
884 	val &= ~GENMASK(offset * 2 + 1, offset * 2);
885 	val |= speed << (offset * 2);
886 	writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);
887 
888 	if (pctl->hwlock)
889 		hwspin_unlock(pctl->hwlock);
890 
891 	stm32_gpio_backup_speed(bank, offset, speed);
892 
893 unlock:
894 	spin_unlock_irqrestore(&bank->lock, flags);
895 	clk_disable(bank->clk);
896 
897 	return err;
898 }
899 
900 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank,
901 	unsigned int offset)
902 {
903 	unsigned long flags;
904 	u32 val;
905 
906 	clk_enable(bank->clk);
907 	spin_lock_irqsave(&bank->lock, flags);
908 
909 	val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
910 	val &= GENMASK(offset * 2 + 1, offset * 2);
911 
912 	spin_unlock_irqrestore(&bank->lock, flags);
913 	clk_disable(bank->clk);
914 
915 	return (val >> (offset * 2));
916 }
917 
918 static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
919 				unsigned offset, u32 bias)
920 {
921 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
922 	unsigned long flags;
923 	u32 val;
924 	int err = 0;
925 
926 	clk_enable(bank->clk);
927 	spin_lock_irqsave(&bank->lock, flags);
928 
929 	if (pctl->hwlock)
930 		err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);
931 
932 	if (err) {
933 		dev_err(pctl->dev, "Can't get hwspinlock\n");
934 		goto unlock;
935 	}
936 
937 	val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
938 	val &= ~GENMASK(offset * 2 + 1, offset * 2);
939 	val |= bias << (offset * 2);
940 	writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);
941 
942 	if (pctl->hwlock)
943 		hwspin_unlock(pctl->hwlock);
944 
945 	stm32_gpio_backup_bias(bank, offset, bias);
946 
947 unlock:
948 	spin_unlock_irqrestore(&bank->lock, flags);
949 	clk_disable(bank->clk);
950 
951 	return err;
952 }
953 
954 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank,
955 	unsigned int offset)
956 {
957 	unsigned long flags;
958 	u32 val;
959 
960 	clk_enable(bank->clk);
961 	spin_lock_irqsave(&bank->lock, flags);
962 
963 	val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
964 	val &= GENMASK(offset * 2 + 1, offset * 2);
965 
966 	spin_unlock_irqrestore(&bank->lock, flags);
967 	clk_disable(bank->clk);
968 
969 	return (val >> (offset * 2));
970 }
971 
972 static bool stm32_pconf_get(struct stm32_gpio_bank *bank,
973 	unsigned int offset, bool dir)
974 {
975 	unsigned long flags;
976 	u32 val;
977 
978 	clk_enable(bank->clk);
979 	spin_lock_irqsave(&bank->lock, flags);
980 
981 	if (dir)
982 		val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) &
983 			 BIT(offset));
984 	else
985 		val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) &
986 			 BIT(offset));
987 
988 	spin_unlock_irqrestore(&bank->lock, flags);
989 	clk_disable(bank->clk);
990 
991 	return val;
992 }
993 
994 static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev,
995 		unsigned int pin, enum pin_config_param param,
996 		enum pin_config_param arg)
997 {
998 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
999 	struct pinctrl_gpio_range *range;
1000 	struct stm32_gpio_bank *bank;
1001 	int offset, ret = 0;
1002 
1003 	range = pinctrl_find_gpio_range_from_pin(pctldev, pin);
1004 	if (!range) {
1005 		dev_err(pctl->dev, "No gpio range defined.\n");
1006 		return -EINVAL;
1007 	}
1008 
1009 	bank = gpiochip_get_data(range->gc);
1010 	offset = stm32_gpio_pin(pin);
1011 
1012 	switch (param) {
1013 	case PIN_CONFIG_DRIVE_PUSH_PULL:
1014 		ret = stm32_pconf_set_driving(bank, offset, 0);
1015 		break;
1016 	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1017 		ret = stm32_pconf_set_driving(bank, offset, 1);
1018 		break;
1019 	case PIN_CONFIG_SLEW_RATE:
1020 		ret = stm32_pconf_set_speed(bank, offset, arg);
1021 		break;
1022 	case PIN_CONFIG_BIAS_DISABLE:
1023 		ret = stm32_pconf_set_bias(bank, offset, 0);
1024 		break;
1025 	case PIN_CONFIG_BIAS_PULL_UP:
1026 		ret = stm32_pconf_set_bias(bank, offset, 1);
1027 		break;
1028 	case PIN_CONFIG_BIAS_PULL_DOWN:
1029 		ret = stm32_pconf_set_bias(bank, offset, 2);
1030 		break;
1031 	case PIN_CONFIG_OUTPUT:
1032 		__stm32_gpio_set(bank, offset, arg);
1033 		ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false);
1034 		break;
1035 	default:
1036 		ret = -EINVAL;
1037 	}
1038 
1039 	return ret;
1040 }
1041 
1042 static int stm32_pconf_group_get(struct pinctrl_dev *pctldev,
1043 				 unsigned group,
1044 				 unsigned long *config)
1045 {
1046 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1047 
1048 	*config = pctl->groups[group].config;
1049 
1050 	return 0;
1051 }
1052 
1053 static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
1054 				 unsigned long *configs, unsigned num_configs)
1055 {
1056 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1057 	struct stm32_pinctrl_group *g = &pctl->groups[group];
1058 	int i, ret;
1059 
1060 	for (i = 0; i < num_configs; i++) {
1061 		ret = stm32_pconf_parse_conf(pctldev, g->pin,
1062 			pinconf_to_config_param(configs[i]),
1063 			pinconf_to_config_argument(configs[i]));
1064 		if (ret < 0)
1065 			return ret;
1066 
1067 		g->config = configs[i];
1068 	}
1069 
1070 	return 0;
1071 }
1072 
1073 static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev,
1074 				 struct seq_file *s,
1075 				 unsigned int pin)
1076 {
1077 	struct pinctrl_gpio_range *range;
1078 	struct stm32_gpio_bank *bank;
1079 	int offset;
1080 	u32 mode, alt, drive, speed, bias;
1081 	static const char * const modes[] = {
1082 			"input", "output", "alternate", "analog" };
1083 	static const char * const speeds[] = {
1084 			"low", "medium", "high", "very high" };
1085 	static const char * const biasing[] = {
1086 			"floating", "pull up", "pull down", "" };
1087 	bool val;
1088 
1089 	range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
1090 	if (!range)
1091 		return;
1092 
1093 	bank = gpiochip_get_data(range->gc);
1094 	offset = stm32_gpio_pin(pin);
1095 
1096 	stm32_pmx_get_mode(bank, offset, &mode, &alt);
1097 	bias = stm32_pconf_get_bias(bank, offset);
1098 
1099 	seq_printf(s, "%s ", modes[mode]);
1100 
1101 	switch (mode) {
1102 	/* input */
1103 	case 0:
1104 		val = stm32_pconf_get(bank, offset, true);
1105 		seq_printf(s, "- %s - %s",
1106 			   val ? "high" : "low",
1107 			   biasing[bias]);
1108 		break;
1109 
1110 	/* output */
1111 	case 1:
1112 		drive = stm32_pconf_get_driving(bank, offset);
1113 		speed = stm32_pconf_get_speed(bank, offset);
1114 		val = stm32_pconf_get(bank, offset, false);
1115 		seq_printf(s, "- %s - %s - %s - %s %s",
1116 			   val ? "high" : "low",
1117 			   drive ? "open drain" : "push pull",
1118 			   biasing[bias],
1119 			   speeds[speed], "speed");
1120 		break;
1121 
1122 	/* alternate */
1123 	case 2:
1124 		drive = stm32_pconf_get_driving(bank, offset);
1125 		speed = stm32_pconf_get_speed(bank, offset);
1126 		seq_printf(s, "%d - %s - %s - %s %s", alt,
1127 			   drive ? "open drain" : "push pull",
1128 			   biasing[bias],
1129 			   speeds[speed], "speed");
1130 		break;
1131 
1132 	/* analog */
1133 	case 3:
1134 		break;
1135 	}
1136 }
1137 
1138 
1139 static const struct pinconf_ops stm32_pconf_ops = {
1140 	.pin_config_group_get	= stm32_pconf_group_get,
1141 	.pin_config_group_set	= stm32_pconf_group_set,
1142 	.pin_config_dbg_show	= stm32_pconf_dbg_show,
1143 };
1144 
1145 static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,
1146 	struct device_node *np)
1147 {
1148 	struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks];
1149 	int bank_ioport_nr;
1150 	struct pinctrl_gpio_range *range = &bank->range;
1151 	struct of_phandle_args args;
1152 	struct device *dev = pctl->dev;
1153 	struct resource res;
1154 	struct reset_control *rstc;
1155 	int npins = STM32_GPIO_PINS_PER_BANK;
1156 	int bank_nr, err;
1157 
1158 	rstc = of_reset_control_get_exclusive(np, NULL);
1159 	if (!IS_ERR(rstc))
1160 		reset_control_deassert(rstc);
1161 
1162 	if (of_address_to_resource(np, 0, &res))
1163 		return -ENODEV;
1164 
1165 	bank->base = devm_ioremap_resource(dev, &res);
1166 	if (IS_ERR(bank->base))
1167 		return PTR_ERR(bank->base);
1168 
1169 	bank->clk = of_clk_get_by_name(np, NULL);
1170 	if (IS_ERR(bank->clk)) {
1171 		dev_err(dev, "failed to get clk (%ld)\n", PTR_ERR(bank->clk));
1172 		return PTR_ERR(bank->clk);
1173 	}
1174 
1175 	err = clk_prepare(bank->clk);
1176 	if (err) {
1177 		dev_err(dev, "failed to prepare clk (%d)\n", err);
1178 		return err;
1179 	}
1180 
1181 	bank->gpio_chip = stm32_gpio_template;
1182 
1183 	of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label);
1184 
1185 	if (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args)) {
1186 		bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK;
1187 		bank->gpio_chip.base = args.args[1];
1188 	} else {
1189 		bank_nr = pctl->nbanks;
1190 		bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
1191 		range->name = bank->gpio_chip.label;
1192 		range->id = bank_nr;
1193 		range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK;
1194 		range->base = range->id * STM32_GPIO_PINS_PER_BANK;
1195 		range->npins = npins;
1196 		range->gc = &bank->gpio_chip;
1197 		pinctrl_add_gpio_range(pctl->pctl_dev,
1198 				       &pctl->banks[bank_nr].range);
1199 	}
1200 
1201 	if (of_property_read_u32(np, "st,bank-ioport", &bank_ioport_nr))
1202 		bank_ioport_nr = bank_nr;
1203 
1204 	bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
1205 
1206 	bank->gpio_chip.ngpio = npins;
1207 	bank->gpio_chip.of_node = np;
1208 	bank->gpio_chip.parent = dev;
1209 	bank->bank_nr = bank_nr;
1210 	bank->bank_ioport_nr = bank_ioport_nr;
1211 	spin_lock_init(&bank->lock);
1212 
1213 	/* create irq hierarchical domain */
1214 	bank->fwnode = of_node_to_fwnode(np);
1215 
1216 	bank->domain = irq_domain_create_hierarchy(pctl->domain, 0,
1217 					STM32_GPIO_IRQ_LINE, bank->fwnode,
1218 					&stm32_gpio_domain_ops, bank);
1219 
1220 	if (!bank->domain)
1221 		return -ENODEV;
1222 
1223 	err = gpiochip_add_data(&bank->gpio_chip, bank);
1224 	if (err) {
1225 		dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr);
1226 		return err;
1227 	}
1228 
1229 	dev_info(dev, "%s bank added\n", bank->gpio_chip.label);
1230 	return 0;
1231 }
1232 
1233 static struct irq_domain *stm32_pctrl_get_irq_domain(struct device_node *np)
1234 {
1235 	struct device_node *parent;
1236 	struct irq_domain *domain;
1237 
1238 	if (!of_find_property(np, "interrupt-parent", NULL))
1239 		return NULL;
1240 
1241 	parent = of_irq_find_parent(np);
1242 	if (!parent)
1243 		return ERR_PTR(-ENXIO);
1244 
1245 	domain = irq_find_host(parent);
1246 	if (!domain)
1247 		/* domain not registered yet */
1248 		return ERR_PTR(-EPROBE_DEFER);
1249 
1250 	return domain;
1251 }
1252 
1253 static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev,
1254 			   struct stm32_pinctrl *pctl)
1255 {
1256 	struct device_node *np = pdev->dev.of_node;
1257 	struct device *dev = &pdev->dev;
1258 	struct regmap *rm;
1259 	int offset, ret, i;
1260 	int mask, mask_width;
1261 
1262 	pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1263 	if (IS_ERR(pctl->regmap))
1264 		return PTR_ERR(pctl->regmap);
1265 
1266 	rm = pctl->regmap;
1267 
1268 	ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset);
1269 	if (ret)
1270 		return ret;
1271 
1272 	ret = of_property_read_u32_index(np, "st,syscfg", 2, &mask);
1273 	if (ret)
1274 		mask = SYSCFG_IRQMUX_MASK;
1275 
1276 	mask_width = fls(mask);
1277 
1278 	for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) {
1279 		struct reg_field mux;
1280 
1281 		mux.reg = offset + (i / 4) * 4;
1282 		mux.lsb = (i % 4) * mask_width;
1283 		mux.msb = mux.lsb + mask_width - 1;
1284 
1285 		dev_dbg(dev, "irqmux%d: reg:%#x, lsb:%d, msb:%d\n",
1286 			i, mux.reg, mux.lsb, mux.msb);
1287 
1288 		pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux);
1289 		if (IS_ERR(pctl->irqmux[i]))
1290 			return PTR_ERR(pctl->irqmux[i]);
1291 	}
1292 
1293 	return 0;
1294 }
1295 
1296 static int stm32_pctrl_build_state(struct platform_device *pdev)
1297 {
1298 	struct stm32_pinctrl *pctl = platform_get_drvdata(pdev);
1299 	int i;
1300 
1301 	pctl->ngroups = pctl->npins;
1302 
1303 	/* Allocate groups */
1304 	pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
1305 				    sizeof(*pctl->groups), GFP_KERNEL);
1306 	if (!pctl->groups)
1307 		return -ENOMEM;
1308 
1309 	/* We assume that one pin is one group, use pin name as group name. */
1310 	pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
1311 				       sizeof(*pctl->grp_names), GFP_KERNEL);
1312 	if (!pctl->grp_names)
1313 		return -ENOMEM;
1314 
1315 	for (i = 0; i < pctl->npins; i++) {
1316 		const struct stm32_desc_pin *pin = pctl->pins + i;
1317 		struct stm32_pinctrl_group *group = pctl->groups + i;
1318 
1319 		group->name = pin->pin.name;
1320 		group->pin = pin->pin.number;
1321 		pctl->grp_names[i] = pin->pin.name;
1322 	}
1323 
1324 	return 0;
1325 }
1326 
1327 static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl,
1328 				       struct stm32_desc_pin *pins)
1329 {
1330 	const struct stm32_desc_pin *p;
1331 	int i, nb_pins_available = 0;
1332 
1333 	for (i = 0; i < pctl->match_data->npins; i++) {
1334 		p = pctl->match_data->pins + i;
1335 		if (pctl->pkg && !(pctl->pkg & p->pkg))
1336 			continue;
1337 		pins->pin = p->pin;
1338 		pins->functions = p->functions;
1339 		pins++;
1340 		nb_pins_available++;
1341 	}
1342 
1343 	pctl->npins = nb_pins_available;
1344 
1345 	return 0;
1346 }
1347 
1348 static void stm32_pctl_get_package(struct device_node *np,
1349 				   struct stm32_pinctrl *pctl)
1350 {
1351 	if (of_property_read_u32(np, "st,package", &pctl->pkg)) {
1352 		pctl->pkg = 0;
1353 		dev_warn(pctl->dev, "No package detected, use default one\n");
1354 	} else {
1355 		dev_dbg(pctl->dev, "package detected: %x\n", pctl->pkg);
1356 	}
1357 }
1358 
1359 int stm32_pctl_probe(struct platform_device *pdev)
1360 {
1361 	struct device_node *np = pdev->dev.of_node;
1362 	struct device_node *child;
1363 	const struct of_device_id *match;
1364 	struct device *dev = &pdev->dev;
1365 	struct stm32_pinctrl *pctl;
1366 	struct pinctrl_pin_desc *pins;
1367 	int i, ret, hwlock_id, banks = 0;
1368 
1369 	if (!np)
1370 		return -EINVAL;
1371 
1372 	match = of_match_device(dev->driver->of_match_table, dev);
1373 	if (!match || !match->data)
1374 		return -EINVAL;
1375 
1376 	if (!of_find_property(np, "pins-are-numbered", NULL)) {
1377 		dev_err(dev, "only support pins-are-numbered format\n");
1378 		return -EINVAL;
1379 	}
1380 
1381 	pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
1382 	if (!pctl)
1383 		return -ENOMEM;
1384 
1385 	platform_set_drvdata(pdev, pctl);
1386 
1387 	/* check for IRQ controller (may require deferred probe) */
1388 	pctl->domain = stm32_pctrl_get_irq_domain(np);
1389 	if (IS_ERR(pctl->domain))
1390 		return PTR_ERR(pctl->domain);
1391 
1392 	/* hwspinlock is optional */
1393 	hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0);
1394 	if (hwlock_id < 0) {
1395 		if (hwlock_id == -EPROBE_DEFER)
1396 			return hwlock_id;
1397 	} else {
1398 		pctl->hwlock = hwspin_lock_request_specific(hwlock_id);
1399 	}
1400 
1401 	spin_lock_init(&pctl->irqmux_lock);
1402 
1403 	pctl->dev = dev;
1404 	pctl->match_data = match->data;
1405 
1406 	/*  get package information */
1407 	stm32_pctl_get_package(np, pctl);
1408 
1409 	pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins,
1410 				  sizeof(*pctl->pins), GFP_KERNEL);
1411 	if (!pctl->pins)
1412 		return -ENOMEM;
1413 
1414 	ret = stm32_pctrl_create_pins_tab(pctl, pctl->pins);
1415 	if (ret)
1416 		return ret;
1417 
1418 	ret = stm32_pctrl_build_state(pdev);
1419 	if (ret) {
1420 		dev_err(dev, "build state failed: %d\n", ret);
1421 		return -EINVAL;
1422 	}
1423 
1424 	if (pctl->domain) {
1425 		ret = stm32_pctrl_dt_setup_irq(pdev, pctl);
1426 		if (ret)
1427 			return ret;
1428 	}
1429 
1430 	pins = devm_kcalloc(&pdev->dev, pctl->npins, sizeof(*pins),
1431 			    GFP_KERNEL);
1432 	if (!pins)
1433 		return -ENOMEM;
1434 
1435 	for (i = 0; i < pctl->npins; i++)
1436 		pins[i] = pctl->pins[i].pin;
1437 
1438 	pctl->pctl_desc.name = dev_name(&pdev->dev);
1439 	pctl->pctl_desc.owner = THIS_MODULE;
1440 	pctl->pctl_desc.pins = pins;
1441 	pctl->pctl_desc.npins = pctl->npins;
1442 	pctl->pctl_desc.link_consumers = true;
1443 	pctl->pctl_desc.confops = &stm32_pconf_ops;
1444 	pctl->pctl_desc.pctlops = &stm32_pctrl_ops;
1445 	pctl->pctl_desc.pmxops = &stm32_pmx_ops;
1446 	pctl->dev = &pdev->dev;
1447 
1448 	pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
1449 					       pctl);
1450 
1451 	if (IS_ERR(pctl->pctl_dev)) {
1452 		dev_err(&pdev->dev, "Failed pinctrl registration\n");
1453 		return PTR_ERR(pctl->pctl_dev);
1454 	}
1455 
1456 	for_each_available_child_of_node(np, child)
1457 		if (of_property_read_bool(child, "gpio-controller"))
1458 			banks++;
1459 
1460 	if (!banks) {
1461 		dev_err(dev, "at least one GPIO bank is required\n");
1462 		return -EINVAL;
1463 	}
1464 	pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks),
1465 			GFP_KERNEL);
1466 	if (!pctl->banks)
1467 		return -ENOMEM;
1468 
1469 	for_each_available_child_of_node(np, child) {
1470 		if (of_property_read_bool(child, "gpio-controller")) {
1471 			ret = stm32_gpiolib_register_bank(pctl, child);
1472 			if (ret) {
1473 				of_node_put(child);
1474 				return ret;
1475 			}
1476 
1477 			pctl->nbanks++;
1478 		}
1479 	}
1480 
1481 	dev_info(dev, "Pinctrl STM32 initialized\n");
1482 
1483 	return 0;
1484 }
1485 
1486 static int __maybe_unused stm32_pinctrl_restore_gpio_regs(
1487 					struct stm32_pinctrl *pctl, u32 pin)
1488 {
1489 	const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin);
1490 	u32 val, alt, mode, offset = stm32_gpio_pin(pin);
1491 	struct pinctrl_gpio_range *range;
1492 	struct stm32_gpio_bank *bank;
1493 	bool pin_is_irq;
1494 	int ret;
1495 
1496 	range = pinctrl_find_gpio_range_from_pin(pctl->pctl_dev, pin);
1497 	if (!range)
1498 		return 0;
1499 
1500 	pin_is_irq = gpiochip_line_is_irq(range->gc, offset);
1501 
1502 	if (!desc || (!pin_is_irq && !desc->gpio_owner))
1503 		return 0;
1504 
1505 	bank = gpiochip_get_data(range->gc);
1506 
1507 	alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK;
1508 	alt >>= STM32_GPIO_BKP_ALT_SHIFT;
1509 	mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK;
1510 	mode >>= STM32_GPIO_BKP_MODE_SHIFT;
1511 
1512 	ret = stm32_pmx_set_mode(bank, offset, mode, alt);
1513 	if (ret)
1514 		return ret;
1515 
1516 	if (mode == 1) {
1517 		val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL);
1518 		val = val >> STM32_GPIO_BKP_VAL;
1519 		__stm32_gpio_set(bank, offset, val);
1520 	}
1521 
1522 	val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE);
1523 	val >>= STM32_GPIO_BKP_TYPE;
1524 	ret = stm32_pconf_set_driving(bank, offset, val);
1525 	if (ret)
1526 		return ret;
1527 
1528 	val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK;
1529 	val >>= STM32_GPIO_BKP_SPEED_SHIFT;
1530 	ret = stm32_pconf_set_speed(bank, offset, val);
1531 	if (ret)
1532 		return ret;
1533 
1534 	val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK;
1535 	val >>= STM32_GPIO_BKP_PUPD_SHIFT;
1536 	ret = stm32_pconf_set_bias(bank, offset, val);
1537 	if (ret)
1538 		return ret;
1539 
1540 	if (pin_is_irq)
1541 		regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr);
1542 
1543 	return 0;
1544 }
1545 
1546 int __maybe_unused stm32_pinctrl_resume(struct device *dev)
1547 {
1548 	struct stm32_pinctrl *pctl = dev_get_drvdata(dev);
1549 	struct stm32_pinctrl_group *g = pctl->groups;
1550 	int i;
1551 
1552 	for (i = g->pin; i < g->pin + pctl->ngroups; i++)
1553 		stm32_pinctrl_restore_gpio_regs(pctl, i);
1554 
1555 	return 0;
1556 }
1557