1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) Maxime Coquelin 2015
4  * Copyright (C) STMicroelectronics 2017
5  * Author:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
6  *
7  * Heavily based on Mediatek's pinctrl driver
8  */
9 #include <linux/clk.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/hwspinlock.h>
12 #include <linux/io.h>
13 #include <linux/irq.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/module.h>
16 #include <linux/of_address.h>
17 #include <linux/of_device.h>
18 #include <linux/of.h>
19 #include <linux/of_irq.h>
20 #include <linux/platform_device.h>
21 #include <linux/property.h>
22 #include <linux/regmap.h>
23 #include <linux/reset.h>
24 #include <linux/seq_file.h>
25 #include <linux/slab.h>
26 
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/pinctrl/machine.h>
29 #include <linux/pinctrl/pinconf-generic.h>
30 #include <linux/pinctrl/pinconf.h>
31 #include <linux/pinctrl/pinctrl.h>
32 #include <linux/pinctrl/pinmux.h>
33 
34 #include "../core.h"
35 #include "../pinconf.h"
36 #include "../pinctrl-utils.h"
37 #include "pinctrl-stm32.h"
38 
39 #define STM32_GPIO_MODER	0x00
40 #define STM32_GPIO_TYPER	0x04
41 #define STM32_GPIO_SPEEDR	0x08
42 #define STM32_GPIO_PUPDR	0x0c
43 #define STM32_GPIO_IDR		0x10
44 #define STM32_GPIO_ODR		0x14
45 #define STM32_GPIO_BSRR		0x18
46 #define STM32_GPIO_LCKR		0x1c
47 #define STM32_GPIO_AFRL		0x20
48 #define STM32_GPIO_AFRH		0x24
49 #define STM32_GPIO_SECCFGR	0x30
50 
51 /* custom bitfield to backup pin status */
52 #define STM32_GPIO_BKP_MODE_SHIFT	0
53 #define STM32_GPIO_BKP_MODE_MASK	GENMASK(1, 0)
54 #define STM32_GPIO_BKP_ALT_SHIFT	2
55 #define STM32_GPIO_BKP_ALT_MASK		GENMASK(5, 2)
56 #define STM32_GPIO_BKP_SPEED_SHIFT	6
57 #define STM32_GPIO_BKP_SPEED_MASK	GENMASK(7, 6)
58 #define STM32_GPIO_BKP_PUPD_SHIFT	8
59 #define STM32_GPIO_BKP_PUPD_MASK	GENMASK(9, 8)
60 #define STM32_GPIO_BKP_TYPE		10
61 #define STM32_GPIO_BKP_VAL		11
62 
63 #define STM32_GPIO_PINS_PER_BANK 16
64 #define STM32_GPIO_IRQ_LINE	 16
65 
66 #define SYSCFG_IRQMUX_MASK GENMASK(3, 0)
67 
68 #define gpio_range_to_bank(chip) \
69 		container_of(chip, struct stm32_gpio_bank, range)
70 
71 #define HWSPNLCK_TIMEOUT	1000 /* usec */
72 
73 static const char * const stm32_gpio_functions[] = {
74 	"gpio", "af0", "af1",
75 	"af2", "af3", "af4",
76 	"af5", "af6", "af7",
77 	"af8", "af9", "af10",
78 	"af11", "af12", "af13",
79 	"af14", "af15", "analog",
80 };
81 
82 struct stm32_pinctrl_group {
83 	const char *name;
84 	unsigned long config;
85 	unsigned pin;
86 };
87 
88 struct stm32_gpio_bank {
89 	void __iomem *base;
90 	struct clk *clk;
91 	struct reset_control *rstc;
92 	spinlock_t lock;
93 	struct gpio_chip gpio_chip;
94 	struct pinctrl_gpio_range range;
95 	struct fwnode_handle *fwnode;
96 	struct irq_domain *domain;
97 	u32 bank_nr;
98 	u32 bank_ioport_nr;
99 	u32 pin_backup[STM32_GPIO_PINS_PER_BANK];
100 	u8 irq_type[STM32_GPIO_PINS_PER_BANK];
101 	bool secure_control;
102 };
103 
104 struct stm32_pinctrl {
105 	struct device *dev;
106 	struct pinctrl_dev *pctl_dev;
107 	struct pinctrl_desc pctl_desc;
108 	struct stm32_pinctrl_group *groups;
109 	unsigned ngroups;
110 	const char **grp_names;
111 	struct stm32_gpio_bank *banks;
112 	unsigned nbanks;
113 	const struct stm32_pinctrl_match_data *match_data;
114 	struct irq_domain	*domain;
115 	struct regmap		*regmap;
116 	struct regmap_field	*irqmux[STM32_GPIO_PINS_PER_BANK];
117 	struct hwspinlock *hwlock;
118 	struct stm32_desc_pin *pins;
119 	u32 npins;
120 	u32 pkg;
121 	u16 irqmux_map;
122 	spinlock_t irqmux_lock;
123 };
124 
125 static inline int stm32_gpio_pin(int gpio)
126 {
127 	return gpio % STM32_GPIO_PINS_PER_BANK;
128 }
129 
130 static inline u32 stm32_gpio_get_mode(u32 function)
131 {
132 	switch (function) {
133 	case STM32_PIN_GPIO:
134 		return 0;
135 	case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
136 		return 2;
137 	case STM32_PIN_ANALOG:
138 		return 3;
139 	}
140 
141 	return 0;
142 }
143 
144 static inline u32 stm32_gpio_get_alt(u32 function)
145 {
146 	switch (function) {
147 	case STM32_PIN_GPIO:
148 		return 0;
149 	case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
150 		return function - 1;
151 	case STM32_PIN_ANALOG:
152 		return 0;
153 	}
154 
155 	return 0;
156 }
157 
158 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank,
159 				    u32 offset, u32 value)
160 {
161 	bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL);
162 	bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL;
163 }
164 
165 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset,
166 				   u32 mode, u32 alt)
167 {
168 	bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK |
169 				      STM32_GPIO_BKP_ALT_MASK);
170 	bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT;
171 	bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT;
172 }
173 
174 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset,
175 				      u32 drive)
176 {
177 	bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE);
178 	bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE;
179 }
180 
181 static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset,
182 				    u32 speed)
183 {
184 	bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK;
185 	bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT;
186 }
187 
188 static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset,
189 				   u32 bias)
190 {
191 	bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK;
192 	bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT;
193 }
194 
195 /* GPIO functions */
196 
197 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,
198 	unsigned offset, int value)
199 {
200 	stm32_gpio_backup_value(bank, offset, value);
201 
202 	if (!value)
203 		offset += STM32_GPIO_PINS_PER_BANK;
204 
205 	writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR);
206 }
207 
208 static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset)
209 {
210 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
211 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
212 	struct pinctrl_gpio_range *range;
213 	int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK);
214 
215 	range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin);
216 	if (!range) {
217 		dev_err(pctl->dev, "pin %d not in range.\n", pin);
218 		return -EINVAL;
219 	}
220 
221 	return pinctrl_gpio_request(chip->base + offset);
222 }
223 
224 static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset)
225 {
226 	pinctrl_gpio_free(chip->base + offset);
227 }
228 
229 static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset)
230 {
231 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
232 
233 	return !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
234 }
235 
236 static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
237 {
238 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
239 
240 	__stm32_gpio_set(bank, offset, value);
241 }
242 
243 static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
244 {
245 	return pinctrl_gpio_direction_input(chip->base + offset);
246 }
247 
248 static int stm32_gpio_direction_output(struct gpio_chip *chip,
249 	unsigned offset, int value)
250 {
251 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
252 
253 	__stm32_gpio_set(bank, offset, value);
254 	pinctrl_gpio_direction_output(chip->base + offset);
255 
256 	return 0;
257 }
258 
259 
260 static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
261 {
262 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
263 	struct irq_fwspec fwspec;
264 
265 	fwspec.fwnode = bank->fwnode;
266 	fwspec.param_count = 2;
267 	fwspec.param[0] = offset;
268 	fwspec.param[1] = IRQ_TYPE_NONE;
269 
270 	return irq_create_fwspec_mapping(&fwspec);
271 }
272 
273 static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
274 {
275 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
276 	int pin = stm32_gpio_pin(offset);
277 	int ret;
278 	u32 mode, alt;
279 
280 	stm32_pmx_get_mode(bank, pin, &mode, &alt);
281 	if ((alt == 0) && (mode == 0))
282 		ret = GPIO_LINE_DIRECTION_IN;
283 	else if ((alt == 0) && (mode == 1))
284 		ret = GPIO_LINE_DIRECTION_OUT;
285 	else
286 		ret = -EINVAL;
287 
288 	return ret;
289 }
290 
291 static int stm32_gpio_init_valid_mask(struct gpio_chip *chip,
292 				      unsigned long *valid_mask,
293 				      unsigned int ngpios)
294 {
295 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
296 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
297 	unsigned int i;
298 	u32 sec;
299 
300 	/* All gpio are valid per default */
301 	bitmap_fill(valid_mask, ngpios);
302 
303 	if (bank->secure_control) {
304 		/* Tag secured pins as invalid */
305 		sec = readl_relaxed(bank->base + STM32_GPIO_SECCFGR);
306 
307 		for (i = 0; i < ngpios; i++) {
308 			if (sec & BIT(i)) {
309 				clear_bit(i, valid_mask);
310 				dev_dbg(pctl->dev, "No access to gpio %d - %d\n", bank->bank_nr, i);
311 			}
312 		}
313 	}
314 
315 	return 0;
316 }
317 
318 static const struct gpio_chip stm32_gpio_template = {
319 	.request		= stm32_gpio_request,
320 	.free			= stm32_gpio_free,
321 	.get			= stm32_gpio_get,
322 	.set			= stm32_gpio_set,
323 	.direction_input	= stm32_gpio_direction_input,
324 	.direction_output	= stm32_gpio_direction_output,
325 	.to_irq			= stm32_gpio_to_irq,
326 	.get_direction		= stm32_gpio_get_direction,
327 	.set_config		= gpiochip_generic_config,
328 	.init_valid_mask	= stm32_gpio_init_valid_mask,
329 };
330 
331 static void stm32_gpio_irq_trigger(struct irq_data *d)
332 {
333 	struct stm32_gpio_bank *bank = d->domain->host_data;
334 	int level;
335 
336 	/* Do not access the GPIO if this is not LEVEL triggered IRQ. */
337 	if (!(bank->irq_type[d->hwirq] & IRQ_TYPE_LEVEL_MASK))
338 		return;
339 
340 	/* If level interrupt type then retrig */
341 	level = stm32_gpio_get(&bank->gpio_chip, d->hwirq);
342 	if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) ||
343 	    (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH))
344 		irq_chip_retrigger_hierarchy(d);
345 }
346 
347 static void stm32_gpio_irq_eoi(struct irq_data *d)
348 {
349 	irq_chip_eoi_parent(d);
350 	stm32_gpio_irq_trigger(d);
351 };
352 
353 static int stm32_gpio_set_type(struct irq_data *d, unsigned int type)
354 {
355 	struct stm32_gpio_bank *bank = d->domain->host_data;
356 	u32 parent_type;
357 
358 	switch (type) {
359 	case IRQ_TYPE_EDGE_RISING:
360 	case IRQ_TYPE_EDGE_FALLING:
361 	case IRQ_TYPE_EDGE_BOTH:
362 		parent_type = type;
363 		break;
364 	case IRQ_TYPE_LEVEL_HIGH:
365 		parent_type = IRQ_TYPE_EDGE_RISING;
366 		break;
367 	case IRQ_TYPE_LEVEL_LOW:
368 		parent_type = IRQ_TYPE_EDGE_FALLING;
369 		break;
370 	default:
371 		return -EINVAL;
372 	}
373 
374 	bank->irq_type[d->hwirq] = type;
375 
376 	return irq_chip_set_type_parent(d, parent_type);
377 };
378 
379 static int stm32_gpio_irq_request_resources(struct irq_data *irq_data)
380 {
381 	struct stm32_gpio_bank *bank = irq_data->domain->host_data;
382 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
383 	int ret;
384 
385 	ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);
386 	if (ret)
387 		return ret;
388 
389 	ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq);
390 	if (ret) {
391 		dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
392 			irq_data->hwirq);
393 		return ret;
394 	}
395 
396 	return 0;
397 }
398 
399 static void stm32_gpio_irq_release_resources(struct irq_data *irq_data)
400 {
401 	struct stm32_gpio_bank *bank = irq_data->domain->host_data;
402 
403 	gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq);
404 }
405 
406 static void stm32_gpio_irq_unmask(struct irq_data *d)
407 {
408 	irq_chip_unmask_parent(d);
409 	stm32_gpio_irq_trigger(d);
410 }
411 
412 static struct irq_chip stm32_gpio_irq_chip = {
413 	.name		= "stm32gpio",
414 	.irq_eoi	= stm32_gpio_irq_eoi,
415 	.irq_ack	= irq_chip_ack_parent,
416 	.irq_mask	= irq_chip_mask_parent,
417 	.irq_unmask	= stm32_gpio_irq_unmask,
418 	.irq_set_type	= stm32_gpio_set_type,
419 	.irq_set_wake	= irq_chip_set_wake_parent,
420 	.irq_request_resources = stm32_gpio_irq_request_resources,
421 	.irq_release_resources = stm32_gpio_irq_release_resources,
422 };
423 
424 static int stm32_gpio_domain_translate(struct irq_domain *d,
425 				       struct irq_fwspec *fwspec,
426 				       unsigned long *hwirq,
427 				       unsigned int *type)
428 {
429 	if ((fwspec->param_count != 2) ||
430 	    (fwspec->param[0] >= STM32_GPIO_IRQ_LINE))
431 		return -EINVAL;
432 
433 	*hwirq = fwspec->param[0];
434 	*type = fwspec->param[1];
435 	return 0;
436 }
437 
438 static int stm32_gpio_domain_activate(struct irq_domain *d,
439 				      struct irq_data *irq_data, bool reserve)
440 {
441 	struct stm32_gpio_bank *bank = d->host_data;
442 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
443 	int ret = 0;
444 
445 	if (pctl->hwlock) {
446 		ret = hwspin_lock_timeout_in_atomic(pctl->hwlock,
447 						    HWSPNLCK_TIMEOUT);
448 		if (ret) {
449 			dev_err(pctl->dev, "Can't get hwspinlock\n");
450 			return ret;
451 		}
452 	}
453 
454 	regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr);
455 
456 	if (pctl->hwlock)
457 		hwspin_unlock_in_atomic(pctl->hwlock);
458 
459 	return ret;
460 }
461 
462 static int stm32_gpio_domain_alloc(struct irq_domain *d,
463 				   unsigned int virq,
464 				   unsigned int nr_irqs, void *data)
465 {
466 	struct stm32_gpio_bank *bank = d->host_data;
467 	struct irq_fwspec *fwspec = data;
468 	struct irq_fwspec parent_fwspec;
469 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
470 	irq_hw_number_t hwirq = fwspec->param[0];
471 	unsigned long flags;
472 	int ret = 0;
473 
474 	/*
475 	 * Check first that the IRQ MUX of that line is free.
476 	 * gpio irq mux is shared between several banks, protect with a lock
477 	 */
478 	spin_lock_irqsave(&pctl->irqmux_lock, flags);
479 
480 	if (pctl->irqmux_map & BIT(hwirq)) {
481 		dev_err(pctl->dev, "irq line %ld already requested.\n", hwirq);
482 		ret = -EBUSY;
483 	} else {
484 		pctl->irqmux_map |= BIT(hwirq);
485 	}
486 
487 	spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
488 	if (ret)
489 		return ret;
490 
491 	parent_fwspec.fwnode = d->parent->fwnode;
492 	parent_fwspec.param_count = 2;
493 	parent_fwspec.param[0] = fwspec->param[0];
494 	parent_fwspec.param[1] = fwspec->param[1];
495 
496 	irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip,
497 				      bank);
498 
499 	return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec);
500 }
501 
502 static void stm32_gpio_domain_free(struct irq_domain *d, unsigned int virq,
503 				   unsigned int nr_irqs)
504 {
505 	struct stm32_gpio_bank *bank = d->host_data;
506 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
507 	struct irq_data *irq_data = irq_domain_get_irq_data(d, virq);
508 	unsigned long flags, hwirq = irq_data->hwirq;
509 
510 	irq_domain_free_irqs_common(d, virq, nr_irqs);
511 
512 	spin_lock_irqsave(&pctl->irqmux_lock, flags);
513 	pctl->irqmux_map &= ~BIT(hwirq);
514 	spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
515 }
516 
517 static const struct irq_domain_ops stm32_gpio_domain_ops = {
518 	.translate	= stm32_gpio_domain_translate,
519 	.alloc		= stm32_gpio_domain_alloc,
520 	.free		= stm32_gpio_domain_free,
521 	.activate	= stm32_gpio_domain_activate,
522 };
523 
524 /* Pinctrl functions */
525 static struct stm32_pinctrl_group *
526 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin)
527 {
528 	int i;
529 
530 	for (i = 0; i < pctl->ngroups; i++) {
531 		struct stm32_pinctrl_group *grp = pctl->groups + i;
532 
533 		if (grp->pin == pin)
534 			return grp;
535 	}
536 
537 	return NULL;
538 }
539 
540 static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl,
541 		u32 pin_num, u32 fnum)
542 {
543 	int i, k;
544 
545 	for (i = 0; i < pctl->npins; i++) {
546 		const struct stm32_desc_pin *pin = pctl->pins + i;
547 		const struct stm32_desc_function *func = pin->functions;
548 
549 		if (pin->pin.number != pin_num)
550 			continue;
551 
552 		for (k = 0; k < STM32_CONFIG_NUM; k++) {
553 			if (func->num == fnum)
554 				return true;
555 			func++;
556 		}
557 
558 		break;
559 	}
560 
561 	dev_err(pctl->dev, "invalid function %d on pin %d .\n", fnum, pin_num);
562 
563 	return false;
564 }
565 
566 static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl,
567 		u32 pin, u32 fnum, struct stm32_pinctrl_group *grp,
568 		struct pinctrl_map **map, unsigned *reserved_maps,
569 		unsigned *num_maps)
570 {
571 	if (*num_maps == *reserved_maps)
572 		return -ENOSPC;
573 
574 	(*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
575 	(*map)[*num_maps].data.mux.group = grp->name;
576 
577 	if (!stm32_pctrl_is_function_valid(pctl, pin, fnum))
578 		return -EINVAL;
579 
580 	(*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum];
581 	(*num_maps)++;
582 
583 	return 0;
584 }
585 
586 static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
587 				      struct device_node *node,
588 				      struct pinctrl_map **map,
589 				      unsigned *reserved_maps,
590 				      unsigned *num_maps)
591 {
592 	struct stm32_pinctrl *pctl;
593 	struct stm32_pinctrl_group *grp;
594 	struct property *pins;
595 	u32 pinfunc, pin, func;
596 	unsigned long *configs;
597 	unsigned int num_configs;
598 	bool has_config = 0;
599 	unsigned reserve = 0;
600 	int num_pins, num_funcs, maps_per_pin, i, err = 0;
601 
602 	pctl = pinctrl_dev_get_drvdata(pctldev);
603 
604 	pins = of_find_property(node, "pinmux", NULL);
605 	if (!pins) {
606 		dev_err(pctl->dev, "missing pins property in node %pOFn .\n",
607 				node);
608 		return -EINVAL;
609 	}
610 
611 	err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
612 		&num_configs);
613 	if (err)
614 		return err;
615 
616 	if (num_configs)
617 		has_config = 1;
618 
619 	num_pins = pins->length / sizeof(u32);
620 	num_funcs = num_pins;
621 	maps_per_pin = 0;
622 	if (num_funcs)
623 		maps_per_pin++;
624 	if (has_config && num_pins >= 1)
625 		maps_per_pin++;
626 
627 	if (!num_pins || !maps_per_pin) {
628 		err = -EINVAL;
629 		goto exit;
630 	}
631 
632 	reserve = num_pins * maps_per_pin;
633 
634 	err = pinctrl_utils_reserve_map(pctldev, map,
635 			reserved_maps, num_maps, reserve);
636 	if (err)
637 		goto exit;
638 
639 	for (i = 0; i < num_pins; i++) {
640 		err = of_property_read_u32_index(node, "pinmux",
641 				i, &pinfunc);
642 		if (err)
643 			goto exit;
644 
645 		pin = STM32_GET_PIN_NO(pinfunc);
646 		func = STM32_GET_PIN_FUNC(pinfunc);
647 
648 		if (!stm32_pctrl_is_function_valid(pctl, pin, func)) {
649 			err = -EINVAL;
650 			goto exit;
651 		}
652 
653 		grp = stm32_pctrl_find_group_by_pin(pctl, pin);
654 		if (!grp) {
655 			dev_err(pctl->dev, "unable to match pin %d to group\n",
656 					pin);
657 			err = -EINVAL;
658 			goto exit;
659 		}
660 
661 		err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
662 				reserved_maps, num_maps);
663 		if (err)
664 			goto exit;
665 
666 		if (has_config) {
667 			err = pinctrl_utils_add_map_configs(pctldev, map,
668 					reserved_maps, num_maps, grp->name,
669 					configs, num_configs,
670 					PIN_MAP_TYPE_CONFIGS_GROUP);
671 			if (err)
672 				goto exit;
673 		}
674 	}
675 
676 exit:
677 	kfree(configs);
678 	return err;
679 }
680 
681 static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
682 				 struct device_node *np_config,
683 				 struct pinctrl_map **map, unsigned *num_maps)
684 {
685 	struct device_node *np;
686 	unsigned reserved_maps;
687 	int ret;
688 
689 	*map = NULL;
690 	*num_maps = 0;
691 	reserved_maps = 0;
692 
693 	for_each_child_of_node(np_config, np) {
694 		ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map,
695 				&reserved_maps, num_maps);
696 		if (ret < 0) {
697 			pinctrl_utils_free_map(pctldev, *map, *num_maps);
698 			of_node_put(np);
699 			return ret;
700 		}
701 	}
702 
703 	return 0;
704 }
705 
706 static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
707 {
708 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
709 
710 	return pctl->ngroups;
711 }
712 
713 static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev,
714 					      unsigned group)
715 {
716 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
717 
718 	return pctl->groups[group].name;
719 }
720 
721 static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
722 				      unsigned group,
723 				      const unsigned **pins,
724 				      unsigned *num_pins)
725 {
726 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
727 
728 	*pins = (unsigned *)&pctl->groups[group].pin;
729 	*num_pins = 1;
730 
731 	return 0;
732 }
733 
734 static const struct pinctrl_ops stm32_pctrl_ops = {
735 	.dt_node_to_map		= stm32_pctrl_dt_node_to_map,
736 	.dt_free_map		= pinctrl_utils_free_map,
737 	.get_groups_count	= stm32_pctrl_get_groups_count,
738 	.get_group_name		= stm32_pctrl_get_group_name,
739 	.get_group_pins		= stm32_pctrl_get_group_pins,
740 };
741 
742 
743 /* Pinmux functions */
744 
745 static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
746 {
747 	return ARRAY_SIZE(stm32_gpio_functions);
748 }
749 
750 static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev,
751 					   unsigned selector)
752 {
753 	return stm32_gpio_functions[selector];
754 }
755 
756 static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev,
757 				     unsigned function,
758 				     const char * const **groups,
759 				     unsigned * const num_groups)
760 {
761 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
762 
763 	*groups = pctl->grp_names;
764 	*num_groups = pctl->ngroups;
765 
766 	return 0;
767 }
768 
769 static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
770 			      int pin, u32 mode, u32 alt)
771 {
772 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
773 	u32 val;
774 	int alt_shift = (pin % 8) * 4;
775 	int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
776 	unsigned long flags;
777 	int err = 0;
778 
779 	spin_lock_irqsave(&bank->lock, flags);
780 
781 	if (pctl->hwlock) {
782 		err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
783 						    HWSPNLCK_TIMEOUT);
784 		if (err) {
785 			dev_err(pctl->dev, "Can't get hwspinlock\n");
786 			goto unlock;
787 		}
788 	}
789 
790 	val = readl_relaxed(bank->base + alt_offset);
791 	val &= ~GENMASK(alt_shift + 3, alt_shift);
792 	val |= (alt << alt_shift);
793 	writel_relaxed(val, bank->base + alt_offset);
794 
795 	val = readl_relaxed(bank->base + STM32_GPIO_MODER);
796 	val &= ~GENMASK(pin * 2 + 1, pin * 2);
797 	val |= mode << (pin * 2);
798 	writel_relaxed(val, bank->base + STM32_GPIO_MODER);
799 
800 	if (pctl->hwlock)
801 		hwspin_unlock_in_atomic(pctl->hwlock);
802 
803 	stm32_gpio_backup_mode(bank, pin, mode, alt);
804 
805 unlock:
806 	spin_unlock_irqrestore(&bank->lock, flags);
807 
808 	return err;
809 }
810 
811 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode,
812 			u32 *alt)
813 {
814 	u32 val;
815 	int alt_shift = (pin % 8) * 4;
816 	int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
817 	unsigned long flags;
818 
819 	spin_lock_irqsave(&bank->lock, flags);
820 
821 	val = readl_relaxed(bank->base + alt_offset);
822 	val &= GENMASK(alt_shift + 3, alt_shift);
823 	*alt = val >> alt_shift;
824 
825 	val = readl_relaxed(bank->base + STM32_GPIO_MODER);
826 	val &= GENMASK(pin * 2 + 1, pin * 2);
827 	*mode = val >> (pin * 2);
828 
829 	spin_unlock_irqrestore(&bank->lock, flags);
830 }
831 
832 static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev,
833 			    unsigned function,
834 			    unsigned group)
835 {
836 	bool ret;
837 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
838 	struct stm32_pinctrl_group *g = pctl->groups + group;
839 	struct pinctrl_gpio_range *range;
840 	struct stm32_gpio_bank *bank;
841 	u32 mode, alt;
842 	int pin;
843 
844 	ret = stm32_pctrl_is_function_valid(pctl, g->pin, function);
845 	if (!ret)
846 		return -EINVAL;
847 
848 	range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin);
849 	if (!range) {
850 		dev_err(pctl->dev, "No gpio range defined.\n");
851 		return -EINVAL;
852 	}
853 
854 	bank = gpiochip_get_data(range->gc);
855 	pin = stm32_gpio_pin(g->pin);
856 
857 	mode = stm32_gpio_get_mode(function);
858 	alt = stm32_gpio_get_alt(function);
859 
860 	return stm32_pmx_set_mode(bank, pin, mode, alt);
861 }
862 
863 static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
864 			struct pinctrl_gpio_range *range, unsigned gpio,
865 			bool input)
866 {
867 	struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc);
868 	int pin = stm32_gpio_pin(gpio);
869 
870 	return stm32_pmx_set_mode(bank, pin, !input, 0);
871 }
872 
873 static int stm32_pmx_request(struct pinctrl_dev *pctldev, unsigned int gpio)
874 {
875 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
876 	struct pinctrl_gpio_range *range;
877 
878 	range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, gpio);
879 	if (!range) {
880 		dev_err(pctl->dev, "No gpio range defined.\n");
881 		return -EINVAL;
882 	}
883 
884 	if (!gpiochip_line_is_valid(range->gc, stm32_gpio_pin(gpio))) {
885 		dev_warn(pctl->dev, "Can't access gpio %d\n", gpio);
886 		return -EACCES;
887 	}
888 
889 	return 0;
890 }
891 
892 static const struct pinmux_ops stm32_pmx_ops = {
893 	.get_functions_count	= stm32_pmx_get_funcs_cnt,
894 	.get_function_name	= stm32_pmx_get_func_name,
895 	.get_function_groups	= stm32_pmx_get_func_groups,
896 	.set_mux		= stm32_pmx_set_mux,
897 	.gpio_set_direction	= stm32_pmx_gpio_set_direction,
898 	.request		= stm32_pmx_request,
899 	.strict			= true,
900 };
901 
902 /* Pinconf functions */
903 
904 static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
905 				   unsigned offset, u32 drive)
906 {
907 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
908 	unsigned long flags;
909 	u32 val;
910 	int err = 0;
911 
912 	spin_lock_irqsave(&bank->lock, flags);
913 
914 	if (pctl->hwlock) {
915 		err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
916 						    HWSPNLCK_TIMEOUT);
917 		if (err) {
918 			dev_err(pctl->dev, "Can't get hwspinlock\n");
919 			goto unlock;
920 		}
921 	}
922 
923 	val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
924 	val &= ~BIT(offset);
925 	val |= drive << offset;
926 	writel_relaxed(val, bank->base + STM32_GPIO_TYPER);
927 
928 	if (pctl->hwlock)
929 		hwspin_unlock_in_atomic(pctl->hwlock);
930 
931 	stm32_gpio_backup_driving(bank, offset, drive);
932 
933 unlock:
934 	spin_unlock_irqrestore(&bank->lock, flags);
935 
936 	return err;
937 }
938 
939 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank,
940 	unsigned int offset)
941 {
942 	unsigned long flags;
943 	u32 val;
944 
945 	spin_lock_irqsave(&bank->lock, flags);
946 
947 	val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
948 	val &= BIT(offset);
949 
950 	spin_unlock_irqrestore(&bank->lock, flags);
951 
952 	return (val >> offset);
953 }
954 
955 static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
956 				 unsigned offset, u32 speed)
957 {
958 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
959 	unsigned long flags;
960 	u32 val;
961 	int err = 0;
962 
963 	spin_lock_irqsave(&bank->lock, flags);
964 
965 	if (pctl->hwlock) {
966 		err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
967 						    HWSPNLCK_TIMEOUT);
968 		if (err) {
969 			dev_err(pctl->dev, "Can't get hwspinlock\n");
970 			goto unlock;
971 		}
972 	}
973 
974 	val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
975 	val &= ~GENMASK(offset * 2 + 1, offset * 2);
976 	val |= speed << (offset * 2);
977 	writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);
978 
979 	if (pctl->hwlock)
980 		hwspin_unlock_in_atomic(pctl->hwlock);
981 
982 	stm32_gpio_backup_speed(bank, offset, speed);
983 
984 unlock:
985 	spin_unlock_irqrestore(&bank->lock, flags);
986 
987 	return err;
988 }
989 
990 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank,
991 	unsigned int offset)
992 {
993 	unsigned long flags;
994 	u32 val;
995 
996 	spin_lock_irqsave(&bank->lock, flags);
997 
998 	val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
999 	val &= GENMASK(offset * 2 + 1, offset * 2);
1000 
1001 	spin_unlock_irqrestore(&bank->lock, flags);
1002 
1003 	return (val >> (offset * 2));
1004 }
1005 
1006 static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
1007 				unsigned offset, u32 bias)
1008 {
1009 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
1010 	unsigned long flags;
1011 	u32 val;
1012 	int err = 0;
1013 
1014 	spin_lock_irqsave(&bank->lock, flags);
1015 
1016 	if (pctl->hwlock) {
1017 		err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
1018 						    HWSPNLCK_TIMEOUT);
1019 		if (err) {
1020 			dev_err(pctl->dev, "Can't get hwspinlock\n");
1021 			goto unlock;
1022 		}
1023 	}
1024 
1025 	val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
1026 	val &= ~GENMASK(offset * 2 + 1, offset * 2);
1027 	val |= bias << (offset * 2);
1028 	writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);
1029 
1030 	if (pctl->hwlock)
1031 		hwspin_unlock_in_atomic(pctl->hwlock);
1032 
1033 	stm32_gpio_backup_bias(bank, offset, bias);
1034 
1035 unlock:
1036 	spin_unlock_irqrestore(&bank->lock, flags);
1037 
1038 	return err;
1039 }
1040 
1041 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank,
1042 	unsigned int offset)
1043 {
1044 	unsigned long flags;
1045 	u32 val;
1046 
1047 	spin_lock_irqsave(&bank->lock, flags);
1048 
1049 	val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
1050 	val &= GENMASK(offset * 2 + 1, offset * 2);
1051 
1052 	spin_unlock_irqrestore(&bank->lock, flags);
1053 
1054 	return (val >> (offset * 2));
1055 }
1056 
1057 static bool stm32_pconf_get(struct stm32_gpio_bank *bank,
1058 	unsigned int offset, bool dir)
1059 {
1060 	unsigned long flags;
1061 	u32 val;
1062 
1063 	spin_lock_irqsave(&bank->lock, flags);
1064 
1065 	if (dir)
1066 		val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) &
1067 			 BIT(offset));
1068 	else
1069 		val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) &
1070 			 BIT(offset));
1071 
1072 	spin_unlock_irqrestore(&bank->lock, flags);
1073 
1074 	return val;
1075 }
1076 
1077 static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev,
1078 		unsigned int pin, enum pin_config_param param,
1079 		enum pin_config_param arg)
1080 {
1081 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1082 	struct pinctrl_gpio_range *range;
1083 	struct stm32_gpio_bank *bank;
1084 	int offset, ret = 0;
1085 
1086 	range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
1087 	if (!range) {
1088 		dev_err(pctl->dev, "No gpio range defined.\n");
1089 		return -EINVAL;
1090 	}
1091 
1092 	bank = gpiochip_get_data(range->gc);
1093 	offset = stm32_gpio_pin(pin);
1094 
1095 	if (!gpiochip_line_is_valid(range->gc, offset)) {
1096 		dev_warn(pctl->dev, "Can't access gpio %d\n", pin);
1097 		return -EACCES;
1098 	}
1099 
1100 	switch (param) {
1101 	case PIN_CONFIG_DRIVE_PUSH_PULL:
1102 		ret = stm32_pconf_set_driving(bank, offset, 0);
1103 		break;
1104 	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1105 		ret = stm32_pconf_set_driving(bank, offset, 1);
1106 		break;
1107 	case PIN_CONFIG_SLEW_RATE:
1108 		ret = stm32_pconf_set_speed(bank, offset, arg);
1109 		break;
1110 	case PIN_CONFIG_BIAS_DISABLE:
1111 		ret = stm32_pconf_set_bias(bank, offset, 0);
1112 		break;
1113 	case PIN_CONFIG_BIAS_PULL_UP:
1114 		ret = stm32_pconf_set_bias(bank, offset, 1);
1115 		break;
1116 	case PIN_CONFIG_BIAS_PULL_DOWN:
1117 		ret = stm32_pconf_set_bias(bank, offset, 2);
1118 		break;
1119 	case PIN_CONFIG_OUTPUT:
1120 		__stm32_gpio_set(bank, offset, arg);
1121 		ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false);
1122 		break;
1123 	default:
1124 		ret = -ENOTSUPP;
1125 	}
1126 
1127 	return ret;
1128 }
1129 
1130 static int stm32_pconf_group_get(struct pinctrl_dev *pctldev,
1131 				 unsigned group,
1132 				 unsigned long *config)
1133 {
1134 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1135 
1136 	*config = pctl->groups[group].config;
1137 
1138 	return 0;
1139 }
1140 
1141 static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
1142 				 unsigned long *configs, unsigned num_configs)
1143 {
1144 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1145 	struct stm32_pinctrl_group *g = &pctl->groups[group];
1146 	int i, ret;
1147 
1148 	for (i = 0; i < num_configs; i++) {
1149 		mutex_lock(&pctldev->mutex);
1150 		ret = stm32_pconf_parse_conf(pctldev, g->pin,
1151 			pinconf_to_config_param(configs[i]),
1152 			pinconf_to_config_argument(configs[i]));
1153 		mutex_unlock(&pctldev->mutex);
1154 		if (ret < 0)
1155 			return ret;
1156 
1157 		g->config = configs[i];
1158 	}
1159 
1160 	return 0;
1161 }
1162 
1163 static int stm32_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1164 			   unsigned long *configs, unsigned int num_configs)
1165 {
1166 	int i, ret;
1167 
1168 	for (i = 0; i < num_configs; i++) {
1169 		ret = stm32_pconf_parse_conf(pctldev, pin,
1170 				pinconf_to_config_param(configs[i]),
1171 				pinconf_to_config_argument(configs[i]));
1172 		if (ret < 0)
1173 			return ret;
1174 	}
1175 
1176 	return 0;
1177 }
1178 
1179 static struct stm32_desc_pin *
1180 stm32_pconf_get_pin_desc_by_pin_number(struct stm32_pinctrl *pctl,
1181 				       unsigned int pin_number)
1182 {
1183 	struct stm32_desc_pin *pins = pctl->pins;
1184 	int i;
1185 
1186 	for (i = 0; i < pctl->npins; i++) {
1187 		if (pins->pin.number == pin_number)
1188 			return pins;
1189 		pins++;
1190 	}
1191 	return NULL;
1192 }
1193 
1194 static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev,
1195 				 struct seq_file *s,
1196 				 unsigned int pin)
1197 {
1198 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1199 	const struct stm32_desc_pin *pin_desc;
1200 	struct pinctrl_gpio_range *range;
1201 	struct stm32_gpio_bank *bank;
1202 	int offset;
1203 	u32 mode, alt, drive, speed, bias;
1204 	static const char * const modes[] = {
1205 			"input", "output", "alternate", "analog" };
1206 	static const char * const speeds[] = {
1207 			"low", "medium", "high", "very high" };
1208 	static const char * const biasing[] = {
1209 			"floating", "pull up", "pull down", "" };
1210 	bool val;
1211 
1212 	range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
1213 	if (!range)
1214 		return;
1215 
1216 	bank = gpiochip_get_data(range->gc);
1217 	offset = stm32_gpio_pin(pin);
1218 
1219 	if (!gpiochip_line_is_valid(range->gc, offset)) {
1220 		seq_puts(s, "NO ACCESS");
1221 		return;
1222 	}
1223 
1224 	stm32_pmx_get_mode(bank, offset, &mode, &alt);
1225 	bias = stm32_pconf_get_bias(bank, offset);
1226 
1227 	seq_printf(s, "%s ", modes[mode]);
1228 
1229 	switch (mode) {
1230 	/* input */
1231 	case 0:
1232 		val = stm32_pconf_get(bank, offset, true);
1233 		seq_printf(s, "- %s - %s",
1234 			   val ? "high" : "low",
1235 			   biasing[bias]);
1236 		break;
1237 
1238 	/* output */
1239 	case 1:
1240 		drive = stm32_pconf_get_driving(bank, offset);
1241 		speed = stm32_pconf_get_speed(bank, offset);
1242 		val = stm32_pconf_get(bank, offset, false);
1243 		seq_printf(s, "- %s - %s - %s - %s %s",
1244 			   val ? "high" : "low",
1245 			   drive ? "open drain" : "push pull",
1246 			   biasing[bias],
1247 			   speeds[speed], "speed");
1248 		break;
1249 
1250 	/* alternate */
1251 	case 2:
1252 		drive = stm32_pconf_get_driving(bank, offset);
1253 		speed = stm32_pconf_get_speed(bank, offset);
1254 		pin_desc = stm32_pconf_get_pin_desc_by_pin_number(pctl, pin);
1255 		if (!pin_desc)
1256 			return;
1257 
1258 		seq_printf(s, "%d (%s) - %s - %s - %s %s", alt,
1259 			   pin_desc->functions[alt + 1].name,
1260 			   drive ? "open drain" : "push pull",
1261 			   biasing[bias],
1262 			   speeds[speed], "speed");
1263 		break;
1264 
1265 	/* analog */
1266 	case 3:
1267 		break;
1268 	}
1269 }
1270 
1271 static const struct pinconf_ops stm32_pconf_ops = {
1272 	.pin_config_group_get	= stm32_pconf_group_get,
1273 	.pin_config_group_set	= stm32_pconf_group_set,
1274 	.pin_config_set		= stm32_pconf_set,
1275 	.pin_config_dbg_show	= stm32_pconf_dbg_show,
1276 };
1277 
1278 static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, struct fwnode_handle *fwnode)
1279 {
1280 	struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks];
1281 	int bank_ioport_nr;
1282 	struct pinctrl_gpio_range *range = &bank->range;
1283 	struct fwnode_reference_args args;
1284 	struct device *dev = pctl->dev;
1285 	struct resource res;
1286 	int npins = STM32_GPIO_PINS_PER_BANK;
1287 	int bank_nr, err, i = 0;
1288 
1289 	if (!IS_ERR(bank->rstc))
1290 		reset_control_deassert(bank->rstc);
1291 
1292 	if (of_address_to_resource(to_of_node(fwnode), 0, &res))
1293 		return -ENODEV;
1294 
1295 	bank->base = devm_ioremap_resource(dev, &res);
1296 	if (IS_ERR(bank->base))
1297 		return PTR_ERR(bank->base);
1298 
1299 	err = clk_prepare_enable(bank->clk);
1300 	if (err) {
1301 		dev_err(dev, "failed to prepare_enable clk (%d)\n", err);
1302 		return err;
1303 	}
1304 
1305 	bank->gpio_chip = stm32_gpio_template;
1306 
1307 	fwnode_property_read_string(fwnode, "st,bank-name", &bank->gpio_chip.label);
1308 
1309 	if (!fwnode_property_get_reference_args(fwnode, "gpio-ranges", NULL, 3, i, &args)) {
1310 		bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK;
1311 		bank->gpio_chip.base = args.args[1];
1312 
1313 		/* get the last defined gpio line (offset + nb of pins) */
1314 		npins = args.args[0] + args.args[2];
1315 		while (!fwnode_property_get_reference_args(fwnode, "gpio-ranges", NULL, 3, ++i, &args))
1316 			npins = max(npins, (int)(args.args[0] + args.args[2]));
1317 	} else {
1318 		bank_nr = pctl->nbanks;
1319 		bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
1320 		range->name = bank->gpio_chip.label;
1321 		range->id = bank_nr;
1322 		range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK;
1323 		range->base = range->id * STM32_GPIO_PINS_PER_BANK;
1324 		range->npins = npins;
1325 		range->gc = &bank->gpio_chip;
1326 		pinctrl_add_gpio_range(pctl->pctl_dev,
1327 				       &pctl->banks[bank_nr].range);
1328 	}
1329 
1330 	if (fwnode_property_read_u32(fwnode, "st,bank-ioport", &bank_ioport_nr))
1331 		bank_ioport_nr = bank_nr;
1332 
1333 	bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
1334 
1335 	bank->gpio_chip.ngpio = npins;
1336 	bank->gpio_chip.fwnode = fwnode;
1337 	bank->gpio_chip.parent = dev;
1338 	bank->bank_nr = bank_nr;
1339 	bank->bank_ioport_nr = bank_ioport_nr;
1340 	bank->secure_control = pctl->match_data->secure_control;
1341 	spin_lock_init(&bank->lock);
1342 
1343 	if (pctl->domain) {
1344 		/* create irq hierarchical domain */
1345 		bank->fwnode = fwnode;
1346 
1347 		bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, STM32_GPIO_IRQ_LINE,
1348 							   bank->fwnode, &stm32_gpio_domain_ops,
1349 							   bank);
1350 
1351 		if (!bank->domain) {
1352 			err = -ENODEV;
1353 			goto err_clk;
1354 		}
1355 	}
1356 
1357 	err = gpiochip_add_data(&bank->gpio_chip, bank);
1358 	if (err) {
1359 		dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr);
1360 		goto err_clk;
1361 	}
1362 
1363 	dev_info(dev, "%s bank added\n", bank->gpio_chip.label);
1364 	return 0;
1365 
1366 err_clk:
1367 	clk_disable_unprepare(bank->clk);
1368 	return err;
1369 }
1370 
1371 static struct irq_domain *stm32_pctrl_get_irq_domain(struct platform_device *pdev)
1372 {
1373 	struct device_node *np = pdev->dev.of_node;
1374 	struct device_node *parent;
1375 	struct irq_domain *domain;
1376 
1377 	if (!of_find_property(np, "interrupt-parent", NULL))
1378 		return NULL;
1379 
1380 	parent = of_irq_find_parent(np);
1381 	if (!parent)
1382 		return ERR_PTR(-ENXIO);
1383 
1384 	domain = irq_find_host(parent);
1385 	if (!domain)
1386 		/* domain not registered yet */
1387 		return ERR_PTR(-EPROBE_DEFER);
1388 
1389 	return domain;
1390 }
1391 
1392 static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev,
1393 			   struct stm32_pinctrl *pctl)
1394 {
1395 	struct device_node *np = pdev->dev.of_node;
1396 	struct device *dev = &pdev->dev;
1397 	struct regmap *rm;
1398 	int offset, ret, i;
1399 	int mask, mask_width;
1400 
1401 	pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1402 	if (IS_ERR(pctl->regmap))
1403 		return PTR_ERR(pctl->regmap);
1404 
1405 	rm = pctl->regmap;
1406 
1407 	ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset);
1408 	if (ret)
1409 		return ret;
1410 
1411 	ret = of_property_read_u32_index(np, "st,syscfg", 2, &mask);
1412 	if (ret)
1413 		mask = SYSCFG_IRQMUX_MASK;
1414 
1415 	mask_width = fls(mask);
1416 
1417 	for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) {
1418 		struct reg_field mux;
1419 
1420 		mux.reg = offset + (i / 4) * 4;
1421 		mux.lsb = (i % 4) * mask_width;
1422 		mux.msb = mux.lsb + mask_width - 1;
1423 
1424 		dev_dbg(dev, "irqmux%d: reg:%#x, lsb:%d, msb:%d\n",
1425 			i, mux.reg, mux.lsb, mux.msb);
1426 
1427 		pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux);
1428 		if (IS_ERR(pctl->irqmux[i]))
1429 			return PTR_ERR(pctl->irqmux[i]);
1430 	}
1431 
1432 	return 0;
1433 }
1434 
1435 static int stm32_pctrl_build_state(struct platform_device *pdev)
1436 {
1437 	struct stm32_pinctrl *pctl = platform_get_drvdata(pdev);
1438 	int i;
1439 
1440 	pctl->ngroups = pctl->npins;
1441 
1442 	/* Allocate groups */
1443 	pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
1444 				    sizeof(*pctl->groups), GFP_KERNEL);
1445 	if (!pctl->groups)
1446 		return -ENOMEM;
1447 
1448 	/* We assume that one pin is one group, use pin name as group name. */
1449 	pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
1450 				       sizeof(*pctl->grp_names), GFP_KERNEL);
1451 	if (!pctl->grp_names)
1452 		return -ENOMEM;
1453 
1454 	for (i = 0; i < pctl->npins; i++) {
1455 		const struct stm32_desc_pin *pin = pctl->pins + i;
1456 		struct stm32_pinctrl_group *group = pctl->groups + i;
1457 
1458 		group->name = pin->pin.name;
1459 		group->pin = pin->pin.number;
1460 		pctl->grp_names[i] = pin->pin.name;
1461 	}
1462 
1463 	return 0;
1464 }
1465 
1466 static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl,
1467 				       struct stm32_desc_pin *pins)
1468 {
1469 	const struct stm32_desc_pin *p;
1470 	int i, nb_pins_available = 0;
1471 
1472 	for (i = 0; i < pctl->match_data->npins; i++) {
1473 		p = pctl->match_data->pins + i;
1474 		if (pctl->pkg && !(pctl->pkg & p->pkg))
1475 			continue;
1476 		pins->pin = p->pin;
1477 		memcpy((struct stm32_desc_pin *)pins->functions, p->functions,
1478 		       STM32_CONFIG_NUM * sizeof(struct stm32_desc_function));
1479 		pins++;
1480 		nb_pins_available++;
1481 	}
1482 
1483 	pctl->npins = nb_pins_available;
1484 
1485 	return 0;
1486 }
1487 
1488 int stm32_pctl_probe(struct platform_device *pdev)
1489 {
1490 	const struct stm32_pinctrl_match_data *match_data;
1491 	struct fwnode_handle *child;
1492 	struct device *dev = &pdev->dev;
1493 	struct stm32_pinctrl *pctl;
1494 	struct pinctrl_pin_desc *pins;
1495 	int i, ret, hwlock_id;
1496 	unsigned int banks;
1497 
1498 	match_data = device_get_match_data(dev);
1499 	if (!match_data)
1500 		return -EINVAL;
1501 
1502 	pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
1503 	if (!pctl)
1504 		return -ENOMEM;
1505 
1506 	platform_set_drvdata(pdev, pctl);
1507 
1508 	/* check for IRQ controller (may require deferred probe) */
1509 	pctl->domain = stm32_pctrl_get_irq_domain(pdev);
1510 	if (IS_ERR(pctl->domain))
1511 		return PTR_ERR(pctl->domain);
1512 	if (!pctl->domain)
1513 		dev_warn(dev, "pinctrl without interrupt support\n");
1514 
1515 	/* hwspinlock is optional */
1516 	hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0);
1517 	if (hwlock_id < 0) {
1518 		if (hwlock_id == -EPROBE_DEFER)
1519 			return hwlock_id;
1520 	} else {
1521 		pctl->hwlock = hwspin_lock_request_specific(hwlock_id);
1522 	}
1523 
1524 	spin_lock_init(&pctl->irqmux_lock);
1525 
1526 	pctl->dev = dev;
1527 	pctl->match_data = match_data;
1528 
1529 	/*  get optional package information */
1530 	if (!device_property_read_u32(dev, "st,package", &pctl->pkg))
1531 		dev_dbg(pctl->dev, "package detected: %x\n", pctl->pkg);
1532 
1533 	pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins,
1534 				  sizeof(*pctl->pins), GFP_KERNEL);
1535 	if (!pctl->pins)
1536 		return -ENOMEM;
1537 
1538 	ret = stm32_pctrl_create_pins_tab(pctl, pctl->pins);
1539 	if (ret)
1540 		return ret;
1541 
1542 	ret = stm32_pctrl_build_state(pdev);
1543 	if (ret) {
1544 		dev_err(dev, "build state failed: %d\n", ret);
1545 		return -EINVAL;
1546 	}
1547 
1548 	if (pctl->domain) {
1549 		ret = stm32_pctrl_dt_setup_irq(pdev, pctl);
1550 		if (ret)
1551 			return ret;
1552 	}
1553 
1554 	pins = devm_kcalloc(&pdev->dev, pctl->npins, sizeof(*pins),
1555 			    GFP_KERNEL);
1556 	if (!pins)
1557 		return -ENOMEM;
1558 
1559 	for (i = 0; i < pctl->npins; i++)
1560 		pins[i] = pctl->pins[i].pin;
1561 
1562 	pctl->pctl_desc.name = dev_name(&pdev->dev);
1563 	pctl->pctl_desc.owner = THIS_MODULE;
1564 	pctl->pctl_desc.pins = pins;
1565 	pctl->pctl_desc.npins = pctl->npins;
1566 	pctl->pctl_desc.link_consumers = true;
1567 	pctl->pctl_desc.confops = &stm32_pconf_ops;
1568 	pctl->pctl_desc.pctlops = &stm32_pctrl_ops;
1569 	pctl->pctl_desc.pmxops = &stm32_pmx_ops;
1570 	pctl->dev = &pdev->dev;
1571 
1572 	pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
1573 					       pctl);
1574 
1575 	if (IS_ERR(pctl->pctl_dev)) {
1576 		dev_err(&pdev->dev, "Failed pinctrl registration\n");
1577 		return PTR_ERR(pctl->pctl_dev);
1578 	}
1579 
1580 	banks = gpiochip_node_count(dev);
1581 	if (!banks) {
1582 		dev_err(dev, "at least one GPIO bank is required\n");
1583 		return -EINVAL;
1584 	}
1585 	pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks),
1586 			GFP_KERNEL);
1587 	if (!pctl->banks)
1588 		return -ENOMEM;
1589 
1590 	i = 0;
1591 	for_each_gpiochip_node(dev, child) {
1592 		struct stm32_gpio_bank *bank = &pctl->banks[i];
1593 		struct device_node *np = to_of_node(child);
1594 
1595 		bank->rstc = of_reset_control_get_exclusive(np, NULL);
1596 		if (PTR_ERR(bank->rstc) == -EPROBE_DEFER) {
1597 			fwnode_handle_put(child);
1598 			return -EPROBE_DEFER;
1599 		}
1600 
1601 		bank->clk = of_clk_get_by_name(np, NULL);
1602 		if (IS_ERR(bank->clk)) {
1603 			fwnode_handle_put(child);
1604 			return dev_err_probe(dev, PTR_ERR(bank->clk),
1605 					     "failed to get clk\n");
1606 		}
1607 		i++;
1608 	}
1609 
1610 	for_each_gpiochip_node(dev, child) {
1611 		ret = stm32_gpiolib_register_bank(pctl, child);
1612 		if (ret) {
1613 			fwnode_handle_put(child);
1614 
1615 			for (i = 0; i < pctl->nbanks; i++)
1616 				clk_disable_unprepare(pctl->banks[i].clk);
1617 
1618 			return ret;
1619 		}
1620 
1621 		pctl->nbanks++;
1622 	}
1623 
1624 	dev_info(dev, "Pinctrl STM32 initialized\n");
1625 
1626 	return 0;
1627 }
1628 
1629 static int __maybe_unused stm32_pinctrl_restore_gpio_regs(
1630 					struct stm32_pinctrl *pctl, u32 pin)
1631 {
1632 	const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin);
1633 	u32 val, alt, mode, offset = stm32_gpio_pin(pin);
1634 	struct pinctrl_gpio_range *range;
1635 	struct stm32_gpio_bank *bank;
1636 	bool pin_is_irq;
1637 	int ret;
1638 
1639 	range = pinctrl_find_gpio_range_from_pin(pctl->pctl_dev, pin);
1640 	if (!range)
1641 		return 0;
1642 
1643 	if (!gpiochip_line_is_valid(range->gc, offset))
1644 		return 0;
1645 
1646 	pin_is_irq = gpiochip_line_is_irq(range->gc, offset);
1647 
1648 	if (!desc || (!pin_is_irq && !desc->gpio_owner))
1649 		return 0;
1650 
1651 	bank = gpiochip_get_data(range->gc);
1652 
1653 	alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK;
1654 	alt >>= STM32_GPIO_BKP_ALT_SHIFT;
1655 	mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK;
1656 	mode >>= STM32_GPIO_BKP_MODE_SHIFT;
1657 
1658 	ret = stm32_pmx_set_mode(bank, offset, mode, alt);
1659 	if (ret)
1660 		return ret;
1661 
1662 	if (mode == 1) {
1663 		val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL);
1664 		val = val >> STM32_GPIO_BKP_VAL;
1665 		__stm32_gpio_set(bank, offset, val);
1666 	}
1667 
1668 	val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE);
1669 	val >>= STM32_GPIO_BKP_TYPE;
1670 	ret = stm32_pconf_set_driving(bank, offset, val);
1671 	if (ret)
1672 		return ret;
1673 
1674 	val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK;
1675 	val >>= STM32_GPIO_BKP_SPEED_SHIFT;
1676 	ret = stm32_pconf_set_speed(bank, offset, val);
1677 	if (ret)
1678 		return ret;
1679 
1680 	val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK;
1681 	val >>= STM32_GPIO_BKP_PUPD_SHIFT;
1682 	ret = stm32_pconf_set_bias(bank, offset, val);
1683 	if (ret)
1684 		return ret;
1685 
1686 	if (pin_is_irq)
1687 		regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr);
1688 
1689 	return 0;
1690 }
1691 
1692 int __maybe_unused stm32_pinctrl_suspend(struct device *dev)
1693 {
1694 	struct stm32_pinctrl *pctl = dev_get_drvdata(dev);
1695 	int i;
1696 
1697 	for (i = 0; i < pctl->nbanks; i++)
1698 		clk_disable(pctl->banks[i].clk);
1699 
1700 	return 0;
1701 }
1702 
1703 int __maybe_unused stm32_pinctrl_resume(struct device *dev)
1704 {
1705 	struct stm32_pinctrl *pctl = dev_get_drvdata(dev);
1706 	struct stm32_pinctrl_group *g = pctl->groups;
1707 	int i;
1708 
1709 	for (i = 0; i < pctl->nbanks; i++)
1710 		clk_enable(pctl->banks[i].clk);
1711 
1712 	for (i = 0; i < pctl->ngroups; i++, g++)
1713 		stm32_pinctrl_restore_gpio_regs(pctl, g->pin);
1714 
1715 	return 0;
1716 }
1717