1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) Maxime Coquelin 2015
4  * Copyright (C) STMicroelectronics 2017
5  * Author:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
6  *
7  * Heavily based on Mediatek's pinctrl driver
8  */
9 #include <linux/clk.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/hwspinlock.h>
12 #include <linux/io.h>
13 #include <linux/irq.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/of_address.h>
18 #include <linux/of_device.h>
19 #include <linux/of_irq.h>
20 #include <linux/pinctrl/consumer.h>
21 #include <linux/pinctrl/machine.h>
22 #include <linux/pinctrl/pinconf.h>
23 #include <linux/pinctrl/pinconf-generic.h>
24 #include <linux/pinctrl/pinctrl.h>
25 #include <linux/pinctrl/pinmux.h>
26 #include <linux/platform_device.h>
27 #include <linux/regmap.h>
28 #include <linux/reset.h>
29 #include <linux/slab.h>
30 
31 #include "../core.h"
32 #include "../pinconf.h"
33 #include "../pinctrl-utils.h"
34 #include "pinctrl-stm32.h"
35 
36 #define STM32_GPIO_MODER	0x00
37 #define STM32_GPIO_TYPER	0x04
38 #define STM32_GPIO_SPEEDR	0x08
39 #define STM32_GPIO_PUPDR	0x0c
40 #define STM32_GPIO_IDR		0x10
41 #define STM32_GPIO_ODR		0x14
42 #define STM32_GPIO_BSRR		0x18
43 #define STM32_GPIO_LCKR		0x1c
44 #define STM32_GPIO_AFRL		0x20
45 #define STM32_GPIO_AFRH		0x24
46 
47 /* custom bitfield to backup pin status */
48 #define STM32_GPIO_BKP_MODE_SHIFT	0
49 #define STM32_GPIO_BKP_MODE_MASK	GENMASK(1, 0)
50 #define STM32_GPIO_BKP_ALT_SHIFT	2
51 #define STM32_GPIO_BKP_ALT_MASK		GENMASK(5, 2)
52 #define STM32_GPIO_BKP_SPEED_SHIFT	6
53 #define STM32_GPIO_BKP_SPEED_MASK	GENMASK(7, 6)
54 #define STM32_GPIO_BKP_PUPD_SHIFT	8
55 #define STM32_GPIO_BKP_PUPD_MASK	GENMASK(9, 8)
56 #define STM32_GPIO_BKP_TYPE		10
57 #define STM32_GPIO_BKP_VAL		11
58 
59 #define STM32_GPIO_PINS_PER_BANK 16
60 #define STM32_GPIO_IRQ_LINE	 16
61 
62 #define SYSCFG_IRQMUX_MASK GENMASK(3, 0)
63 
64 #define gpio_range_to_bank(chip) \
65 		container_of(chip, struct stm32_gpio_bank, range)
66 
67 #define HWSPNLCK_TIMEOUT	1000 /* usec */
68 
69 static const char * const stm32_gpio_functions[] = {
70 	"gpio", "af0", "af1",
71 	"af2", "af3", "af4",
72 	"af5", "af6", "af7",
73 	"af8", "af9", "af10",
74 	"af11", "af12", "af13",
75 	"af14", "af15", "analog",
76 };
77 
78 struct stm32_pinctrl_group {
79 	const char *name;
80 	unsigned long config;
81 	unsigned pin;
82 };
83 
84 struct stm32_gpio_bank {
85 	void __iomem *base;
86 	struct clk *clk;
87 	struct reset_control *rstc;
88 	spinlock_t lock;
89 	struct gpio_chip gpio_chip;
90 	struct pinctrl_gpio_range range;
91 	struct fwnode_handle *fwnode;
92 	struct irq_domain *domain;
93 	u32 bank_nr;
94 	u32 bank_ioport_nr;
95 	u32 pin_backup[STM32_GPIO_PINS_PER_BANK];
96 	u8 irq_type[STM32_GPIO_PINS_PER_BANK];
97 };
98 
99 struct stm32_pinctrl {
100 	struct device *dev;
101 	struct pinctrl_dev *pctl_dev;
102 	struct pinctrl_desc pctl_desc;
103 	struct stm32_pinctrl_group *groups;
104 	unsigned ngroups;
105 	const char **grp_names;
106 	struct stm32_gpio_bank *banks;
107 	unsigned nbanks;
108 	const struct stm32_pinctrl_match_data *match_data;
109 	struct irq_domain	*domain;
110 	struct regmap		*regmap;
111 	struct regmap_field	*irqmux[STM32_GPIO_PINS_PER_BANK];
112 	struct hwspinlock *hwlock;
113 	struct stm32_desc_pin *pins;
114 	u32 npins;
115 	u32 pkg;
116 	u16 irqmux_map;
117 	spinlock_t irqmux_lock;
118 };
119 
120 static inline int stm32_gpio_pin(int gpio)
121 {
122 	return gpio % STM32_GPIO_PINS_PER_BANK;
123 }
124 
125 static inline u32 stm32_gpio_get_mode(u32 function)
126 {
127 	switch (function) {
128 	case STM32_PIN_GPIO:
129 		return 0;
130 	case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
131 		return 2;
132 	case STM32_PIN_ANALOG:
133 		return 3;
134 	}
135 
136 	return 0;
137 }
138 
139 static inline u32 stm32_gpio_get_alt(u32 function)
140 {
141 	switch (function) {
142 	case STM32_PIN_GPIO:
143 		return 0;
144 	case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
145 		return function - 1;
146 	case STM32_PIN_ANALOG:
147 		return 0;
148 	}
149 
150 	return 0;
151 }
152 
153 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank,
154 				    u32 offset, u32 value)
155 {
156 	bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL);
157 	bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL;
158 }
159 
160 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset,
161 				   u32 mode, u32 alt)
162 {
163 	bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK |
164 				      STM32_GPIO_BKP_ALT_MASK);
165 	bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT;
166 	bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT;
167 }
168 
169 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset,
170 				      u32 drive)
171 {
172 	bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE);
173 	bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE;
174 }
175 
176 static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset,
177 				    u32 speed)
178 {
179 	bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK;
180 	bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT;
181 }
182 
183 static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset,
184 				   u32 bias)
185 {
186 	bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK;
187 	bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT;
188 }
189 
190 /* GPIO functions */
191 
192 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,
193 	unsigned offset, int value)
194 {
195 	stm32_gpio_backup_value(bank, offset, value);
196 
197 	if (!value)
198 		offset += STM32_GPIO_PINS_PER_BANK;
199 
200 	clk_enable(bank->clk);
201 
202 	writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR);
203 
204 	clk_disable(bank->clk);
205 }
206 
207 static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset)
208 {
209 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
210 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
211 	struct pinctrl_gpio_range *range;
212 	int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK);
213 
214 	range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin);
215 	if (!range) {
216 		dev_err(pctl->dev, "pin %d not in range.\n", pin);
217 		return -EINVAL;
218 	}
219 
220 	return pinctrl_gpio_request(chip->base + offset);
221 }
222 
223 static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset)
224 {
225 	pinctrl_gpio_free(chip->base + offset);
226 }
227 
228 static int stm32_gpio_get_noclk(struct gpio_chip *chip, unsigned int offset)
229 {
230 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
231 
232 	return !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
233 }
234 
235 static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset)
236 {
237 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
238 	int ret;
239 
240 	clk_enable(bank->clk);
241 
242 	ret = stm32_gpio_get_noclk(chip, offset);
243 
244 	clk_disable(bank->clk);
245 
246 	return ret;
247 }
248 
249 static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
250 {
251 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
252 
253 	__stm32_gpio_set(bank, offset, value);
254 }
255 
256 static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
257 {
258 	return pinctrl_gpio_direction_input(chip->base + offset);
259 }
260 
261 static int stm32_gpio_direction_output(struct gpio_chip *chip,
262 	unsigned offset, int value)
263 {
264 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
265 
266 	__stm32_gpio_set(bank, offset, value);
267 	pinctrl_gpio_direction_output(chip->base + offset);
268 
269 	return 0;
270 }
271 
272 
273 static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
274 {
275 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
276 	struct irq_fwspec fwspec;
277 
278 	fwspec.fwnode = bank->fwnode;
279 	fwspec.param_count = 2;
280 	fwspec.param[0] = offset;
281 	fwspec.param[1] = IRQ_TYPE_NONE;
282 
283 	return irq_create_fwspec_mapping(&fwspec);
284 }
285 
286 static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
287 {
288 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
289 	int pin = stm32_gpio_pin(offset);
290 	int ret;
291 	u32 mode, alt;
292 
293 	stm32_pmx_get_mode(bank, pin, &mode, &alt);
294 	if ((alt == 0) && (mode == 0))
295 		ret = GPIO_LINE_DIRECTION_IN;
296 	else if ((alt == 0) && (mode == 1))
297 		ret = GPIO_LINE_DIRECTION_OUT;
298 	else
299 		ret = -EINVAL;
300 
301 	return ret;
302 }
303 
304 static const struct gpio_chip stm32_gpio_template = {
305 	.request		= stm32_gpio_request,
306 	.free			= stm32_gpio_free,
307 	.get			= stm32_gpio_get,
308 	.set			= stm32_gpio_set,
309 	.direction_input	= stm32_gpio_direction_input,
310 	.direction_output	= stm32_gpio_direction_output,
311 	.to_irq			= stm32_gpio_to_irq,
312 	.get_direction		= stm32_gpio_get_direction,
313 	.set_config		= gpiochip_generic_config,
314 };
315 
316 static void stm32_gpio_irq_trigger(struct irq_data *d)
317 {
318 	struct stm32_gpio_bank *bank = d->domain->host_data;
319 	int level;
320 
321 	/* Do not access the GPIO if this is not LEVEL triggered IRQ. */
322 	if (!(bank->irq_type[d->hwirq] & IRQ_TYPE_LEVEL_MASK))
323 		return;
324 
325 	/* If level interrupt type then retrig */
326 	level = stm32_gpio_get_noclk(&bank->gpio_chip, d->hwirq);
327 	if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) ||
328 	    (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH))
329 		irq_chip_retrigger_hierarchy(d);
330 }
331 
332 static void stm32_gpio_irq_eoi(struct irq_data *d)
333 {
334 	irq_chip_eoi_parent(d);
335 	stm32_gpio_irq_trigger(d);
336 };
337 
338 static int stm32_gpio_set_type(struct irq_data *d, unsigned int type)
339 {
340 	struct stm32_gpio_bank *bank = d->domain->host_data;
341 	u32 parent_type;
342 
343 	switch (type) {
344 	case IRQ_TYPE_EDGE_RISING:
345 	case IRQ_TYPE_EDGE_FALLING:
346 	case IRQ_TYPE_EDGE_BOTH:
347 		parent_type = type;
348 		break;
349 	case IRQ_TYPE_LEVEL_HIGH:
350 		parent_type = IRQ_TYPE_EDGE_RISING;
351 		break;
352 	case IRQ_TYPE_LEVEL_LOW:
353 		parent_type = IRQ_TYPE_EDGE_FALLING;
354 		break;
355 	default:
356 		return -EINVAL;
357 	}
358 
359 	bank->irq_type[d->hwirq] = type;
360 
361 	return irq_chip_set_type_parent(d, parent_type);
362 };
363 
364 static int stm32_gpio_irq_request_resources(struct irq_data *irq_data)
365 {
366 	struct stm32_gpio_bank *bank = irq_data->domain->host_data;
367 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
368 	unsigned long flags;
369 	int ret;
370 
371 	ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);
372 	if (ret)
373 		return ret;
374 
375 	ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq);
376 	if (ret) {
377 		dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
378 			irq_data->hwirq);
379 		return ret;
380 	}
381 
382 	flags = irqd_get_trigger_type(irq_data);
383 	if (flags & IRQ_TYPE_LEVEL_MASK)
384 		clk_enable(bank->clk);
385 
386 	return 0;
387 }
388 
389 static void stm32_gpio_irq_release_resources(struct irq_data *irq_data)
390 {
391 	struct stm32_gpio_bank *bank = irq_data->domain->host_data;
392 
393 	if (bank->irq_type[irq_data->hwirq] & IRQ_TYPE_LEVEL_MASK)
394 		clk_disable(bank->clk);
395 
396 	gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq);
397 }
398 
399 static void stm32_gpio_irq_unmask(struct irq_data *d)
400 {
401 	irq_chip_unmask_parent(d);
402 	stm32_gpio_irq_trigger(d);
403 }
404 
405 static struct irq_chip stm32_gpio_irq_chip = {
406 	.name		= "stm32gpio",
407 	.irq_eoi	= stm32_gpio_irq_eoi,
408 	.irq_ack	= irq_chip_ack_parent,
409 	.irq_mask	= irq_chip_mask_parent,
410 	.irq_unmask	= stm32_gpio_irq_unmask,
411 	.irq_set_type	= stm32_gpio_set_type,
412 	.irq_set_wake	= irq_chip_set_wake_parent,
413 	.irq_request_resources = stm32_gpio_irq_request_resources,
414 	.irq_release_resources = stm32_gpio_irq_release_resources,
415 };
416 
417 static int stm32_gpio_domain_translate(struct irq_domain *d,
418 				       struct irq_fwspec *fwspec,
419 				       unsigned long *hwirq,
420 				       unsigned int *type)
421 {
422 	if ((fwspec->param_count != 2) ||
423 	    (fwspec->param[0] >= STM32_GPIO_IRQ_LINE))
424 		return -EINVAL;
425 
426 	*hwirq = fwspec->param[0];
427 	*type = fwspec->param[1];
428 	return 0;
429 }
430 
431 static int stm32_gpio_domain_activate(struct irq_domain *d,
432 				      struct irq_data *irq_data, bool reserve)
433 {
434 	struct stm32_gpio_bank *bank = d->host_data;
435 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
436 	int ret = 0;
437 
438 	if (pctl->hwlock) {
439 		ret = hwspin_lock_timeout_in_atomic(pctl->hwlock,
440 						    HWSPNLCK_TIMEOUT);
441 		if (ret) {
442 			dev_err(pctl->dev, "Can't get hwspinlock\n");
443 			return ret;
444 		}
445 	}
446 
447 	regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr);
448 
449 	if (pctl->hwlock)
450 		hwspin_unlock_in_atomic(pctl->hwlock);
451 
452 	return ret;
453 }
454 
455 static int stm32_gpio_domain_alloc(struct irq_domain *d,
456 				   unsigned int virq,
457 				   unsigned int nr_irqs, void *data)
458 {
459 	struct stm32_gpio_bank *bank = d->host_data;
460 	struct irq_fwspec *fwspec = data;
461 	struct irq_fwspec parent_fwspec;
462 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
463 	irq_hw_number_t hwirq = fwspec->param[0];
464 	unsigned long flags;
465 	int ret = 0;
466 
467 	/*
468 	 * Check first that the IRQ MUX of that line is free.
469 	 * gpio irq mux is shared between several banks, protect with a lock
470 	 */
471 	spin_lock_irqsave(&pctl->irqmux_lock, flags);
472 
473 	if (pctl->irqmux_map & BIT(hwirq)) {
474 		dev_err(pctl->dev, "irq line %ld already requested.\n", hwirq);
475 		ret = -EBUSY;
476 	} else {
477 		pctl->irqmux_map |= BIT(hwirq);
478 	}
479 
480 	spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
481 	if (ret)
482 		return ret;
483 
484 	parent_fwspec.fwnode = d->parent->fwnode;
485 	parent_fwspec.param_count = 2;
486 	parent_fwspec.param[0] = fwspec->param[0];
487 	parent_fwspec.param[1] = fwspec->param[1];
488 
489 	irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip,
490 				      bank);
491 
492 	return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec);
493 }
494 
495 static void stm32_gpio_domain_free(struct irq_domain *d, unsigned int virq,
496 				   unsigned int nr_irqs)
497 {
498 	struct stm32_gpio_bank *bank = d->host_data;
499 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
500 	struct irq_data *irq_data = irq_domain_get_irq_data(d, virq);
501 	unsigned long flags, hwirq = irq_data->hwirq;
502 
503 	irq_domain_free_irqs_common(d, virq, nr_irqs);
504 
505 	spin_lock_irqsave(&pctl->irqmux_lock, flags);
506 	pctl->irqmux_map &= ~BIT(hwirq);
507 	spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
508 }
509 
510 static const struct irq_domain_ops stm32_gpio_domain_ops = {
511 	.translate	= stm32_gpio_domain_translate,
512 	.alloc		= stm32_gpio_domain_alloc,
513 	.free		= stm32_gpio_domain_free,
514 	.activate	= stm32_gpio_domain_activate,
515 };
516 
517 /* Pinctrl functions */
518 static struct stm32_pinctrl_group *
519 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin)
520 {
521 	int i;
522 
523 	for (i = 0; i < pctl->ngroups; i++) {
524 		struct stm32_pinctrl_group *grp = pctl->groups + i;
525 
526 		if (grp->pin == pin)
527 			return grp;
528 	}
529 
530 	return NULL;
531 }
532 
533 static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl,
534 		u32 pin_num, u32 fnum)
535 {
536 	int i;
537 
538 	for (i = 0; i < pctl->npins; i++) {
539 		const struct stm32_desc_pin *pin = pctl->pins + i;
540 		const struct stm32_desc_function *func = pin->functions;
541 
542 		if (pin->pin.number != pin_num)
543 			continue;
544 
545 		while (func && func->name) {
546 			if (func->num == fnum)
547 				return true;
548 			func++;
549 		}
550 
551 		break;
552 	}
553 
554 	dev_err(pctl->dev, "invalid function %d on pin %d .\n", fnum, pin_num);
555 
556 	return false;
557 }
558 
559 static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl,
560 		u32 pin, u32 fnum, struct stm32_pinctrl_group *grp,
561 		struct pinctrl_map **map, unsigned *reserved_maps,
562 		unsigned *num_maps)
563 {
564 	if (*num_maps == *reserved_maps)
565 		return -ENOSPC;
566 
567 	(*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
568 	(*map)[*num_maps].data.mux.group = grp->name;
569 
570 	if (!stm32_pctrl_is_function_valid(pctl, pin, fnum))
571 		return -EINVAL;
572 
573 	(*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum];
574 	(*num_maps)++;
575 
576 	return 0;
577 }
578 
579 static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
580 				      struct device_node *node,
581 				      struct pinctrl_map **map,
582 				      unsigned *reserved_maps,
583 				      unsigned *num_maps)
584 {
585 	struct stm32_pinctrl *pctl;
586 	struct stm32_pinctrl_group *grp;
587 	struct property *pins;
588 	u32 pinfunc, pin, func;
589 	unsigned long *configs;
590 	unsigned int num_configs;
591 	bool has_config = 0;
592 	unsigned reserve = 0;
593 	int num_pins, num_funcs, maps_per_pin, i, err = 0;
594 
595 	pctl = pinctrl_dev_get_drvdata(pctldev);
596 
597 	pins = of_find_property(node, "pinmux", NULL);
598 	if (!pins) {
599 		dev_err(pctl->dev, "missing pins property in node %pOFn .\n",
600 				node);
601 		return -EINVAL;
602 	}
603 
604 	err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
605 		&num_configs);
606 	if (err)
607 		return err;
608 
609 	if (num_configs)
610 		has_config = 1;
611 
612 	num_pins = pins->length / sizeof(u32);
613 	num_funcs = num_pins;
614 	maps_per_pin = 0;
615 	if (num_funcs)
616 		maps_per_pin++;
617 	if (has_config && num_pins >= 1)
618 		maps_per_pin++;
619 
620 	if (!num_pins || !maps_per_pin) {
621 		err = -EINVAL;
622 		goto exit;
623 	}
624 
625 	reserve = num_pins * maps_per_pin;
626 
627 	err = pinctrl_utils_reserve_map(pctldev, map,
628 			reserved_maps, num_maps, reserve);
629 	if (err)
630 		goto exit;
631 
632 	for (i = 0; i < num_pins; i++) {
633 		err = of_property_read_u32_index(node, "pinmux",
634 				i, &pinfunc);
635 		if (err)
636 			goto exit;
637 
638 		pin = STM32_GET_PIN_NO(pinfunc);
639 		func = STM32_GET_PIN_FUNC(pinfunc);
640 
641 		if (!stm32_pctrl_is_function_valid(pctl, pin, func)) {
642 			err = -EINVAL;
643 			goto exit;
644 		}
645 
646 		grp = stm32_pctrl_find_group_by_pin(pctl, pin);
647 		if (!grp) {
648 			dev_err(pctl->dev, "unable to match pin %d to group\n",
649 					pin);
650 			err = -EINVAL;
651 			goto exit;
652 		}
653 
654 		err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
655 				reserved_maps, num_maps);
656 		if (err)
657 			goto exit;
658 
659 		if (has_config) {
660 			err = pinctrl_utils_add_map_configs(pctldev, map,
661 					reserved_maps, num_maps, grp->name,
662 					configs, num_configs,
663 					PIN_MAP_TYPE_CONFIGS_GROUP);
664 			if (err)
665 				goto exit;
666 		}
667 	}
668 
669 exit:
670 	kfree(configs);
671 	return err;
672 }
673 
674 static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
675 				 struct device_node *np_config,
676 				 struct pinctrl_map **map, unsigned *num_maps)
677 {
678 	struct device_node *np;
679 	unsigned reserved_maps;
680 	int ret;
681 
682 	*map = NULL;
683 	*num_maps = 0;
684 	reserved_maps = 0;
685 
686 	for_each_child_of_node(np_config, np) {
687 		ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map,
688 				&reserved_maps, num_maps);
689 		if (ret < 0) {
690 			pinctrl_utils_free_map(pctldev, *map, *num_maps);
691 			of_node_put(np);
692 			return ret;
693 		}
694 	}
695 
696 	return 0;
697 }
698 
699 static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
700 {
701 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
702 
703 	return pctl->ngroups;
704 }
705 
706 static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev,
707 					      unsigned group)
708 {
709 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
710 
711 	return pctl->groups[group].name;
712 }
713 
714 static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
715 				      unsigned group,
716 				      const unsigned **pins,
717 				      unsigned *num_pins)
718 {
719 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
720 
721 	*pins = (unsigned *)&pctl->groups[group].pin;
722 	*num_pins = 1;
723 
724 	return 0;
725 }
726 
727 static const struct pinctrl_ops stm32_pctrl_ops = {
728 	.dt_node_to_map		= stm32_pctrl_dt_node_to_map,
729 	.dt_free_map		= pinctrl_utils_free_map,
730 	.get_groups_count	= stm32_pctrl_get_groups_count,
731 	.get_group_name		= stm32_pctrl_get_group_name,
732 	.get_group_pins		= stm32_pctrl_get_group_pins,
733 };
734 
735 
736 /* Pinmux functions */
737 
738 static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
739 {
740 	return ARRAY_SIZE(stm32_gpio_functions);
741 }
742 
743 static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev,
744 					   unsigned selector)
745 {
746 	return stm32_gpio_functions[selector];
747 }
748 
749 static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev,
750 				     unsigned function,
751 				     const char * const **groups,
752 				     unsigned * const num_groups)
753 {
754 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
755 
756 	*groups = pctl->grp_names;
757 	*num_groups = pctl->ngroups;
758 
759 	return 0;
760 }
761 
762 static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
763 			      int pin, u32 mode, u32 alt)
764 {
765 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
766 	u32 val;
767 	int alt_shift = (pin % 8) * 4;
768 	int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
769 	unsigned long flags;
770 	int err = 0;
771 
772 	clk_enable(bank->clk);
773 	spin_lock_irqsave(&bank->lock, flags);
774 
775 	if (pctl->hwlock) {
776 		err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
777 						    HWSPNLCK_TIMEOUT);
778 		if (err) {
779 			dev_err(pctl->dev, "Can't get hwspinlock\n");
780 			goto unlock;
781 		}
782 	}
783 
784 	val = readl_relaxed(bank->base + alt_offset);
785 	val &= ~GENMASK(alt_shift + 3, alt_shift);
786 	val |= (alt << alt_shift);
787 	writel_relaxed(val, bank->base + alt_offset);
788 
789 	val = readl_relaxed(bank->base + STM32_GPIO_MODER);
790 	val &= ~GENMASK(pin * 2 + 1, pin * 2);
791 	val |= mode << (pin * 2);
792 	writel_relaxed(val, bank->base + STM32_GPIO_MODER);
793 
794 	if (pctl->hwlock)
795 		hwspin_unlock_in_atomic(pctl->hwlock);
796 
797 	stm32_gpio_backup_mode(bank, pin, mode, alt);
798 
799 unlock:
800 	spin_unlock_irqrestore(&bank->lock, flags);
801 	clk_disable(bank->clk);
802 
803 	return err;
804 }
805 
806 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode,
807 			u32 *alt)
808 {
809 	u32 val;
810 	int alt_shift = (pin % 8) * 4;
811 	int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
812 	unsigned long flags;
813 
814 	clk_enable(bank->clk);
815 	spin_lock_irqsave(&bank->lock, flags);
816 
817 	val = readl_relaxed(bank->base + alt_offset);
818 	val &= GENMASK(alt_shift + 3, alt_shift);
819 	*alt = val >> alt_shift;
820 
821 	val = readl_relaxed(bank->base + STM32_GPIO_MODER);
822 	val &= GENMASK(pin * 2 + 1, pin * 2);
823 	*mode = val >> (pin * 2);
824 
825 	spin_unlock_irqrestore(&bank->lock, flags);
826 	clk_disable(bank->clk);
827 }
828 
829 static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev,
830 			    unsigned function,
831 			    unsigned group)
832 {
833 	bool ret;
834 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
835 	struct stm32_pinctrl_group *g = pctl->groups + group;
836 	struct pinctrl_gpio_range *range;
837 	struct stm32_gpio_bank *bank;
838 	u32 mode, alt;
839 	int pin;
840 
841 	ret = stm32_pctrl_is_function_valid(pctl, g->pin, function);
842 	if (!ret)
843 		return -EINVAL;
844 
845 	range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin);
846 	if (!range) {
847 		dev_err(pctl->dev, "No gpio range defined.\n");
848 		return -EINVAL;
849 	}
850 
851 	bank = gpiochip_get_data(range->gc);
852 	pin = stm32_gpio_pin(g->pin);
853 
854 	mode = stm32_gpio_get_mode(function);
855 	alt = stm32_gpio_get_alt(function);
856 
857 	return stm32_pmx_set_mode(bank, pin, mode, alt);
858 }
859 
860 static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
861 			struct pinctrl_gpio_range *range, unsigned gpio,
862 			bool input)
863 {
864 	struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc);
865 	int pin = stm32_gpio_pin(gpio);
866 
867 	return stm32_pmx_set_mode(bank, pin, !input, 0);
868 }
869 
870 static const struct pinmux_ops stm32_pmx_ops = {
871 	.get_functions_count	= stm32_pmx_get_funcs_cnt,
872 	.get_function_name	= stm32_pmx_get_func_name,
873 	.get_function_groups	= stm32_pmx_get_func_groups,
874 	.set_mux		= stm32_pmx_set_mux,
875 	.gpio_set_direction	= stm32_pmx_gpio_set_direction,
876 	.strict			= true,
877 };
878 
879 /* Pinconf functions */
880 
881 static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
882 				   unsigned offset, u32 drive)
883 {
884 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
885 	unsigned long flags;
886 	u32 val;
887 	int err = 0;
888 
889 	clk_enable(bank->clk);
890 	spin_lock_irqsave(&bank->lock, flags);
891 
892 	if (pctl->hwlock) {
893 		err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
894 						    HWSPNLCK_TIMEOUT);
895 		if (err) {
896 			dev_err(pctl->dev, "Can't get hwspinlock\n");
897 			goto unlock;
898 		}
899 	}
900 
901 	val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
902 	val &= ~BIT(offset);
903 	val |= drive << offset;
904 	writel_relaxed(val, bank->base + STM32_GPIO_TYPER);
905 
906 	if (pctl->hwlock)
907 		hwspin_unlock_in_atomic(pctl->hwlock);
908 
909 	stm32_gpio_backup_driving(bank, offset, drive);
910 
911 unlock:
912 	spin_unlock_irqrestore(&bank->lock, flags);
913 	clk_disable(bank->clk);
914 
915 	return err;
916 }
917 
918 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank,
919 	unsigned int offset)
920 {
921 	unsigned long flags;
922 	u32 val;
923 
924 	clk_enable(bank->clk);
925 	spin_lock_irqsave(&bank->lock, flags);
926 
927 	val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
928 	val &= BIT(offset);
929 
930 	spin_unlock_irqrestore(&bank->lock, flags);
931 	clk_disable(bank->clk);
932 
933 	return (val >> offset);
934 }
935 
936 static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
937 				 unsigned offset, u32 speed)
938 {
939 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
940 	unsigned long flags;
941 	u32 val;
942 	int err = 0;
943 
944 	clk_enable(bank->clk);
945 	spin_lock_irqsave(&bank->lock, flags);
946 
947 	if (pctl->hwlock) {
948 		err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
949 						    HWSPNLCK_TIMEOUT);
950 		if (err) {
951 			dev_err(pctl->dev, "Can't get hwspinlock\n");
952 			goto unlock;
953 		}
954 	}
955 
956 	val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
957 	val &= ~GENMASK(offset * 2 + 1, offset * 2);
958 	val |= speed << (offset * 2);
959 	writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);
960 
961 	if (pctl->hwlock)
962 		hwspin_unlock_in_atomic(pctl->hwlock);
963 
964 	stm32_gpio_backup_speed(bank, offset, speed);
965 
966 unlock:
967 	spin_unlock_irqrestore(&bank->lock, flags);
968 	clk_disable(bank->clk);
969 
970 	return err;
971 }
972 
973 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank,
974 	unsigned int offset)
975 {
976 	unsigned long flags;
977 	u32 val;
978 
979 	clk_enable(bank->clk);
980 	spin_lock_irqsave(&bank->lock, flags);
981 
982 	val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
983 	val &= GENMASK(offset * 2 + 1, offset * 2);
984 
985 	spin_unlock_irqrestore(&bank->lock, flags);
986 	clk_disable(bank->clk);
987 
988 	return (val >> (offset * 2));
989 }
990 
991 static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
992 				unsigned offset, u32 bias)
993 {
994 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
995 	unsigned long flags;
996 	u32 val;
997 	int err = 0;
998 
999 	clk_enable(bank->clk);
1000 	spin_lock_irqsave(&bank->lock, flags);
1001 
1002 	if (pctl->hwlock) {
1003 		err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
1004 						    HWSPNLCK_TIMEOUT);
1005 		if (err) {
1006 			dev_err(pctl->dev, "Can't get hwspinlock\n");
1007 			goto unlock;
1008 		}
1009 	}
1010 
1011 	val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
1012 	val &= ~GENMASK(offset * 2 + 1, offset * 2);
1013 	val |= bias << (offset * 2);
1014 	writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);
1015 
1016 	if (pctl->hwlock)
1017 		hwspin_unlock_in_atomic(pctl->hwlock);
1018 
1019 	stm32_gpio_backup_bias(bank, offset, bias);
1020 
1021 unlock:
1022 	spin_unlock_irqrestore(&bank->lock, flags);
1023 	clk_disable(bank->clk);
1024 
1025 	return err;
1026 }
1027 
1028 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank,
1029 	unsigned int offset)
1030 {
1031 	unsigned long flags;
1032 	u32 val;
1033 
1034 	clk_enable(bank->clk);
1035 	spin_lock_irqsave(&bank->lock, flags);
1036 
1037 	val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
1038 	val &= GENMASK(offset * 2 + 1, offset * 2);
1039 
1040 	spin_unlock_irqrestore(&bank->lock, flags);
1041 	clk_disable(bank->clk);
1042 
1043 	return (val >> (offset * 2));
1044 }
1045 
1046 static bool stm32_pconf_get(struct stm32_gpio_bank *bank,
1047 	unsigned int offset, bool dir)
1048 {
1049 	unsigned long flags;
1050 	u32 val;
1051 
1052 	clk_enable(bank->clk);
1053 	spin_lock_irqsave(&bank->lock, flags);
1054 
1055 	if (dir)
1056 		val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) &
1057 			 BIT(offset));
1058 	else
1059 		val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) &
1060 			 BIT(offset));
1061 
1062 	spin_unlock_irqrestore(&bank->lock, flags);
1063 	clk_disable(bank->clk);
1064 
1065 	return val;
1066 }
1067 
1068 static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev,
1069 		unsigned int pin, enum pin_config_param param,
1070 		enum pin_config_param arg)
1071 {
1072 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1073 	struct pinctrl_gpio_range *range;
1074 	struct stm32_gpio_bank *bank;
1075 	int offset, ret = 0;
1076 
1077 	range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
1078 	if (!range) {
1079 		dev_err(pctl->dev, "No gpio range defined.\n");
1080 		return -EINVAL;
1081 	}
1082 
1083 	bank = gpiochip_get_data(range->gc);
1084 	offset = stm32_gpio_pin(pin);
1085 
1086 	switch (param) {
1087 	case PIN_CONFIG_DRIVE_PUSH_PULL:
1088 		ret = stm32_pconf_set_driving(bank, offset, 0);
1089 		break;
1090 	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1091 		ret = stm32_pconf_set_driving(bank, offset, 1);
1092 		break;
1093 	case PIN_CONFIG_SLEW_RATE:
1094 		ret = stm32_pconf_set_speed(bank, offset, arg);
1095 		break;
1096 	case PIN_CONFIG_BIAS_DISABLE:
1097 		ret = stm32_pconf_set_bias(bank, offset, 0);
1098 		break;
1099 	case PIN_CONFIG_BIAS_PULL_UP:
1100 		ret = stm32_pconf_set_bias(bank, offset, 1);
1101 		break;
1102 	case PIN_CONFIG_BIAS_PULL_DOWN:
1103 		ret = stm32_pconf_set_bias(bank, offset, 2);
1104 		break;
1105 	case PIN_CONFIG_OUTPUT:
1106 		__stm32_gpio_set(bank, offset, arg);
1107 		ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false);
1108 		break;
1109 	default:
1110 		ret = -ENOTSUPP;
1111 	}
1112 
1113 	return ret;
1114 }
1115 
1116 static int stm32_pconf_group_get(struct pinctrl_dev *pctldev,
1117 				 unsigned group,
1118 				 unsigned long *config)
1119 {
1120 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1121 
1122 	*config = pctl->groups[group].config;
1123 
1124 	return 0;
1125 }
1126 
1127 static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
1128 				 unsigned long *configs, unsigned num_configs)
1129 {
1130 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1131 	struct stm32_pinctrl_group *g = &pctl->groups[group];
1132 	int i, ret;
1133 
1134 	for (i = 0; i < num_configs; i++) {
1135 		mutex_lock(&pctldev->mutex);
1136 		ret = stm32_pconf_parse_conf(pctldev, g->pin,
1137 			pinconf_to_config_param(configs[i]),
1138 			pinconf_to_config_argument(configs[i]));
1139 		mutex_unlock(&pctldev->mutex);
1140 		if (ret < 0)
1141 			return ret;
1142 
1143 		g->config = configs[i];
1144 	}
1145 
1146 	return 0;
1147 }
1148 
1149 static int stm32_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1150 			   unsigned long *configs, unsigned int num_configs)
1151 {
1152 	int i, ret;
1153 
1154 	for (i = 0; i < num_configs; i++) {
1155 		ret = stm32_pconf_parse_conf(pctldev, pin,
1156 				pinconf_to_config_param(configs[i]),
1157 				pinconf_to_config_argument(configs[i]));
1158 		if (ret < 0)
1159 			return ret;
1160 	}
1161 
1162 	return 0;
1163 }
1164 
1165 static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev,
1166 				 struct seq_file *s,
1167 				 unsigned int pin)
1168 {
1169 	struct pinctrl_gpio_range *range;
1170 	struct stm32_gpio_bank *bank;
1171 	int offset;
1172 	u32 mode, alt, drive, speed, bias;
1173 	static const char * const modes[] = {
1174 			"input", "output", "alternate", "analog" };
1175 	static const char * const speeds[] = {
1176 			"low", "medium", "high", "very high" };
1177 	static const char * const biasing[] = {
1178 			"floating", "pull up", "pull down", "" };
1179 	bool val;
1180 
1181 	range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
1182 	if (!range)
1183 		return;
1184 
1185 	bank = gpiochip_get_data(range->gc);
1186 	offset = stm32_gpio_pin(pin);
1187 
1188 	stm32_pmx_get_mode(bank, offset, &mode, &alt);
1189 	bias = stm32_pconf_get_bias(bank, offset);
1190 
1191 	seq_printf(s, "%s ", modes[mode]);
1192 
1193 	switch (mode) {
1194 	/* input */
1195 	case 0:
1196 		val = stm32_pconf_get(bank, offset, true);
1197 		seq_printf(s, "- %s - %s",
1198 			   val ? "high" : "low",
1199 			   biasing[bias]);
1200 		break;
1201 
1202 	/* output */
1203 	case 1:
1204 		drive = stm32_pconf_get_driving(bank, offset);
1205 		speed = stm32_pconf_get_speed(bank, offset);
1206 		val = stm32_pconf_get(bank, offset, false);
1207 		seq_printf(s, "- %s - %s - %s - %s %s",
1208 			   val ? "high" : "low",
1209 			   drive ? "open drain" : "push pull",
1210 			   biasing[bias],
1211 			   speeds[speed], "speed");
1212 		break;
1213 
1214 	/* alternate */
1215 	case 2:
1216 		drive = stm32_pconf_get_driving(bank, offset);
1217 		speed = stm32_pconf_get_speed(bank, offset);
1218 		seq_printf(s, "%d - %s - %s - %s %s", alt,
1219 			   drive ? "open drain" : "push pull",
1220 			   biasing[bias],
1221 			   speeds[speed], "speed");
1222 		break;
1223 
1224 	/* analog */
1225 	case 3:
1226 		break;
1227 	}
1228 }
1229 
1230 static const struct pinconf_ops stm32_pconf_ops = {
1231 	.pin_config_group_get	= stm32_pconf_group_get,
1232 	.pin_config_group_set	= stm32_pconf_group_set,
1233 	.pin_config_set		= stm32_pconf_set,
1234 	.pin_config_dbg_show	= stm32_pconf_dbg_show,
1235 };
1236 
1237 static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,
1238 	struct device_node *np)
1239 {
1240 	struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks];
1241 	int bank_ioport_nr;
1242 	struct pinctrl_gpio_range *range = &bank->range;
1243 	struct of_phandle_args args;
1244 	struct device *dev = pctl->dev;
1245 	struct resource res;
1246 	int npins = STM32_GPIO_PINS_PER_BANK;
1247 	int bank_nr, err, i = 0;
1248 
1249 	if (!IS_ERR(bank->rstc))
1250 		reset_control_deassert(bank->rstc);
1251 
1252 	if (of_address_to_resource(np, 0, &res))
1253 		return -ENODEV;
1254 
1255 	bank->base = devm_ioremap_resource(dev, &res);
1256 	if (IS_ERR(bank->base))
1257 		return PTR_ERR(bank->base);
1258 
1259 	err = clk_prepare(bank->clk);
1260 	if (err) {
1261 		dev_err(dev, "failed to prepare clk (%d)\n", err);
1262 		return err;
1263 	}
1264 
1265 	bank->gpio_chip = stm32_gpio_template;
1266 
1267 	of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label);
1268 
1269 	if (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, i, &args)) {
1270 		bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK;
1271 		bank->gpio_chip.base = args.args[1];
1272 
1273 		/* get the last defined gpio line (offset + nb of pins) */
1274 		npins = args.args[0] + args.args[2];
1275 		while (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, ++i, &args))
1276 			npins = max(npins, (int)(args.args[0] + args.args[2]));
1277 	} else {
1278 		bank_nr = pctl->nbanks;
1279 		bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
1280 		range->name = bank->gpio_chip.label;
1281 		range->id = bank_nr;
1282 		range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK;
1283 		range->base = range->id * STM32_GPIO_PINS_PER_BANK;
1284 		range->npins = npins;
1285 		range->gc = &bank->gpio_chip;
1286 		pinctrl_add_gpio_range(pctl->pctl_dev,
1287 				       &pctl->banks[bank_nr].range);
1288 	}
1289 
1290 	if (of_property_read_u32(np, "st,bank-ioport", &bank_ioport_nr))
1291 		bank_ioport_nr = bank_nr;
1292 
1293 	bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
1294 
1295 	bank->gpio_chip.ngpio = npins;
1296 	bank->gpio_chip.of_node = np;
1297 	bank->gpio_chip.parent = dev;
1298 	bank->bank_nr = bank_nr;
1299 	bank->bank_ioport_nr = bank_ioport_nr;
1300 	spin_lock_init(&bank->lock);
1301 
1302 	/* create irq hierarchical domain */
1303 	bank->fwnode = of_node_to_fwnode(np);
1304 
1305 	bank->domain = irq_domain_create_hierarchy(pctl->domain, 0,
1306 					STM32_GPIO_IRQ_LINE, bank->fwnode,
1307 					&stm32_gpio_domain_ops, bank);
1308 
1309 	if (!bank->domain)
1310 		return -ENODEV;
1311 
1312 	err = gpiochip_add_data(&bank->gpio_chip, bank);
1313 	if (err) {
1314 		dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr);
1315 		return err;
1316 	}
1317 
1318 	dev_info(dev, "%s bank added\n", bank->gpio_chip.label);
1319 	return 0;
1320 }
1321 
1322 static struct irq_domain *stm32_pctrl_get_irq_domain(struct device_node *np)
1323 {
1324 	struct device_node *parent;
1325 	struct irq_domain *domain;
1326 
1327 	if (!of_find_property(np, "interrupt-parent", NULL))
1328 		return NULL;
1329 
1330 	parent = of_irq_find_parent(np);
1331 	if (!parent)
1332 		return ERR_PTR(-ENXIO);
1333 
1334 	domain = irq_find_host(parent);
1335 	if (!domain)
1336 		/* domain not registered yet */
1337 		return ERR_PTR(-EPROBE_DEFER);
1338 
1339 	return domain;
1340 }
1341 
1342 static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev,
1343 			   struct stm32_pinctrl *pctl)
1344 {
1345 	struct device_node *np = pdev->dev.of_node;
1346 	struct device *dev = &pdev->dev;
1347 	struct regmap *rm;
1348 	int offset, ret, i;
1349 	int mask, mask_width;
1350 
1351 	pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1352 	if (IS_ERR(pctl->regmap))
1353 		return PTR_ERR(pctl->regmap);
1354 
1355 	rm = pctl->regmap;
1356 
1357 	ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset);
1358 	if (ret)
1359 		return ret;
1360 
1361 	ret = of_property_read_u32_index(np, "st,syscfg", 2, &mask);
1362 	if (ret)
1363 		mask = SYSCFG_IRQMUX_MASK;
1364 
1365 	mask_width = fls(mask);
1366 
1367 	for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) {
1368 		struct reg_field mux;
1369 
1370 		mux.reg = offset + (i / 4) * 4;
1371 		mux.lsb = (i % 4) * mask_width;
1372 		mux.msb = mux.lsb + mask_width - 1;
1373 
1374 		dev_dbg(dev, "irqmux%d: reg:%#x, lsb:%d, msb:%d\n",
1375 			i, mux.reg, mux.lsb, mux.msb);
1376 
1377 		pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux);
1378 		if (IS_ERR(pctl->irqmux[i]))
1379 			return PTR_ERR(pctl->irqmux[i]);
1380 	}
1381 
1382 	return 0;
1383 }
1384 
1385 static int stm32_pctrl_build_state(struct platform_device *pdev)
1386 {
1387 	struct stm32_pinctrl *pctl = platform_get_drvdata(pdev);
1388 	int i;
1389 
1390 	pctl->ngroups = pctl->npins;
1391 
1392 	/* Allocate groups */
1393 	pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
1394 				    sizeof(*pctl->groups), GFP_KERNEL);
1395 	if (!pctl->groups)
1396 		return -ENOMEM;
1397 
1398 	/* We assume that one pin is one group, use pin name as group name. */
1399 	pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
1400 				       sizeof(*pctl->grp_names), GFP_KERNEL);
1401 	if (!pctl->grp_names)
1402 		return -ENOMEM;
1403 
1404 	for (i = 0; i < pctl->npins; i++) {
1405 		const struct stm32_desc_pin *pin = pctl->pins + i;
1406 		struct stm32_pinctrl_group *group = pctl->groups + i;
1407 
1408 		group->name = pin->pin.name;
1409 		group->pin = pin->pin.number;
1410 		pctl->grp_names[i] = pin->pin.name;
1411 	}
1412 
1413 	return 0;
1414 }
1415 
1416 static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl,
1417 				       struct stm32_desc_pin *pins)
1418 {
1419 	const struct stm32_desc_pin *p;
1420 	int i, nb_pins_available = 0;
1421 
1422 	for (i = 0; i < pctl->match_data->npins; i++) {
1423 		p = pctl->match_data->pins + i;
1424 		if (pctl->pkg && !(pctl->pkg & p->pkg))
1425 			continue;
1426 		pins->pin = p->pin;
1427 		pins->functions = p->functions;
1428 		pins++;
1429 		nb_pins_available++;
1430 	}
1431 
1432 	pctl->npins = nb_pins_available;
1433 
1434 	return 0;
1435 }
1436 
1437 int stm32_pctl_probe(struct platform_device *pdev)
1438 {
1439 	struct device_node *np = pdev->dev.of_node;
1440 	struct device_node *child;
1441 	const struct of_device_id *match;
1442 	struct device *dev = &pdev->dev;
1443 	struct stm32_pinctrl *pctl;
1444 	struct pinctrl_pin_desc *pins;
1445 	int i, ret, hwlock_id, banks = 0;
1446 
1447 	if (!np)
1448 		return -EINVAL;
1449 
1450 	match = of_match_device(dev->driver->of_match_table, dev);
1451 	if (!match || !match->data)
1452 		return -EINVAL;
1453 
1454 	if (!of_find_property(np, "pins-are-numbered", NULL)) {
1455 		dev_err(dev, "only support pins-are-numbered format\n");
1456 		return -EINVAL;
1457 	}
1458 
1459 	pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
1460 	if (!pctl)
1461 		return -ENOMEM;
1462 
1463 	platform_set_drvdata(pdev, pctl);
1464 
1465 	/* check for IRQ controller (may require deferred probe) */
1466 	pctl->domain = stm32_pctrl_get_irq_domain(np);
1467 	if (IS_ERR(pctl->domain))
1468 		return PTR_ERR(pctl->domain);
1469 
1470 	/* hwspinlock is optional */
1471 	hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0);
1472 	if (hwlock_id < 0) {
1473 		if (hwlock_id == -EPROBE_DEFER)
1474 			return hwlock_id;
1475 	} else {
1476 		pctl->hwlock = hwspin_lock_request_specific(hwlock_id);
1477 	}
1478 
1479 	spin_lock_init(&pctl->irqmux_lock);
1480 
1481 	pctl->dev = dev;
1482 	pctl->match_data = match->data;
1483 
1484 	/*  get optional package information */
1485 	if (!of_property_read_u32(np, "st,package", &pctl->pkg))
1486 		dev_dbg(pctl->dev, "package detected: %x\n", pctl->pkg);
1487 
1488 	pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins,
1489 				  sizeof(*pctl->pins), GFP_KERNEL);
1490 	if (!pctl->pins)
1491 		return -ENOMEM;
1492 
1493 	ret = stm32_pctrl_create_pins_tab(pctl, pctl->pins);
1494 	if (ret)
1495 		return ret;
1496 
1497 	ret = stm32_pctrl_build_state(pdev);
1498 	if (ret) {
1499 		dev_err(dev, "build state failed: %d\n", ret);
1500 		return -EINVAL;
1501 	}
1502 
1503 	if (pctl->domain) {
1504 		ret = stm32_pctrl_dt_setup_irq(pdev, pctl);
1505 		if (ret)
1506 			return ret;
1507 	}
1508 
1509 	pins = devm_kcalloc(&pdev->dev, pctl->npins, sizeof(*pins),
1510 			    GFP_KERNEL);
1511 	if (!pins)
1512 		return -ENOMEM;
1513 
1514 	for (i = 0; i < pctl->npins; i++)
1515 		pins[i] = pctl->pins[i].pin;
1516 
1517 	pctl->pctl_desc.name = dev_name(&pdev->dev);
1518 	pctl->pctl_desc.owner = THIS_MODULE;
1519 	pctl->pctl_desc.pins = pins;
1520 	pctl->pctl_desc.npins = pctl->npins;
1521 	pctl->pctl_desc.link_consumers = true;
1522 	pctl->pctl_desc.confops = &stm32_pconf_ops;
1523 	pctl->pctl_desc.pctlops = &stm32_pctrl_ops;
1524 	pctl->pctl_desc.pmxops = &stm32_pmx_ops;
1525 	pctl->dev = &pdev->dev;
1526 
1527 	pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
1528 					       pctl);
1529 
1530 	if (IS_ERR(pctl->pctl_dev)) {
1531 		dev_err(&pdev->dev, "Failed pinctrl registration\n");
1532 		return PTR_ERR(pctl->pctl_dev);
1533 	}
1534 
1535 	for_each_available_child_of_node(np, child)
1536 		if (of_property_read_bool(child, "gpio-controller"))
1537 			banks++;
1538 
1539 	if (!banks) {
1540 		dev_err(dev, "at least one GPIO bank is required\n");
1541 		return -EINVAL;
1542 	}
1543 	pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks),
1544 			GFP_KERNEL);
1545 	if (!pctl->banks)
1546 		return -ENOMEM;
1547 
1548 	i = 0;
1549 	for_each_available_child_of_node(np, child) {
1550 		struct stm32_gpio_bank *bank = &pctl->banks[i];
1551 
1552 		if (of_property_read_bool(child, "gpio-controller")) {
1553 			bank->rstc = of_reset_control_get_exclusive(child,
1554 								    NULL);
1555 			if (PTR_ERR(bank->rstc) == -EPROBE_DEFER) {
1556 				of_node_put(child);
1557 				return -EPROBE_DEFER;
1558 			}
1559 
1560 			bank->clk = of_clk_get_by_name(child, NULL);
1561 			if (IS_ERR(bank->clk)) {
1562 				if (PTR_ERR(bank->clk) != -EPROBE_DEFER)
1563 					dev_err(dev,
1564 						"failed to get clk (%ld)\n",
1565 						PTR_ERR(bank->clk));
1566 				of_node_put(child);
1567 				return PTR_ERR(bank->clk);
1568 			}
1569 			i++;
1570 		}
1571 	}
1572 
1573 	for_each_available_child_of_node(np, child) {
1574 		if (of_property_read_bool(child, "gpio-controller")) {
1575 			ret = stm32_gpiolib_register_bank(pctl, child);
1576 			if (ret) {
1577 				of_node_put(child);
1578 				return ret;
1579 			}
1580 
1581 			pctl->nbanks++;
1582 		}
1583 	}
1584 
1585 	dev_info(dev, "Pinctrl STM32 initialized\n");
1586 
1587 	return 0;
1588 }
1589 
1590 static int __maybe_unused stm32_pinctrl_restore_gpio_regs(
1591 					struct stm32_pinctrl *pctl, u32 pin)
1592 {
1593 	const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin);
1594 	u32 val, alt, mode, offset = stm32_gpio_pin(pin);
1595 	struct pinctrl_gpio_range *range;
1596 	struct stm32_gpio_bank *bank;
1597 	bool pin_is_irq;
1598 	int ret;
1599 
1600 	range = pinctrl_find_gpio_range_from_pin(pctl->pctl_dev, pin);
1601 	if (!range)
1602 		return 0;
1603 
1604 	pin_is_irq = gpiochip_line_is_irq(range->gc, offset);
1605 
1606 	if (!desc || (!pin_is_irq && !desc->gpio_owner))
1607 		return 0;
1608 
1609 	bank = gpiochip_get_data(range->gc);
1610 
1611 	alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK;
1612 	alt >>= STM32_GPIO_BKP_ALT_SHIFT;
1613 	mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK;
1614 	mode >>= STM32_GPIO_BKP_MODE_SHIFT;
1615 
1616 	ret = stm32_pmx_set_mode(bank, offset, mode, alt);
1617 	if (ret)
1618 		return ret;
1619 
1620 	if (mode == 1) {
1621 		val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL);
1622 		val = val >> STM32_GPIO_BKP_VAL;
1623 		__stm32_gpio_set(bank, offset, val);
1624 	}
1625 
1626 	val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE);
1627 	val >>= STM32_GPIO_BKP_TYPE;
1628 	ret = stm32_pconf_set_driving(bank, offset, val);
1629 	if (ret)
1630 		return ret;
1631 
1632 	val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK;
1633 	val >>= STM32_GPIO_BKP_SPEED_SHIFT;
1634 	ret = stm32_pconf_set_speed(bank, offset, val);
1635 	if (ret)
1636 		return ret;
1637 
1638 	val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK;
1639 	val >>= STM32_GPIO_BKP_PUPD_SHIFT;
1640 	ret = stm32_pconf_set_bias(bank, offset, val);
1641 	if (ret)
1642 		return ret;
1643 
1644 	if (pin_is_irq)
1645 		regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr);
1646 
1647 	return 0;
1648 }
1649 
1650 int __maybe_unused stm32_pinctrl_resume(struct device *dev)
1651 {
1652 	struct stm32_pinctrl *pctl = dev_get_drvdata(dev);
1653 	struct stm32_pinctrl_group *g = pctl->groups;
1654 	int i;
1655 
1656 	for (i = 0; i < pctl->ngroups; i++, g++)
1657 		stm32_pinctrl_restore_gpio_regs(pctl, g->pin);
1658 
1659 	return 0;
1660 }
1661