1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics 2017 5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 * 7 * Heavily based on Mediatek's pinctrl driver 8 */ 9 #include <linux/clk.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/hwspinlock.h> 12 #include <linux/io.h> 13 #include <linux/irq.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/of_address.h> 18 #include <linux/of_device.h> 19 #include <linux/of_irq.h> 20 #include <linux/pinctrl/consumer.h> 21 #include <linux/pinctrl/machine.h> 22 #include <linux/pinctrl/pinconf.h> 23 #include <linux/pinctrl/pinconf-generic.h> 24 #include <linux/pinctrl/pinctrl.h> 25 #include <linux/pinctrl/pinmux.h> 26 #include <linux/platform_device.h> 27 #include <linux/regmap.h> 28 #include <linux/reset.h> 29 #include <linux/slab.h> 30 31 #include "../core.h" 32 #include "../pinconf.h" 33 #include "../pinctrl-utils.h" 34 #include "pinctrl-stm32.h" 35 36 #define STM32_GPIO_MODER 0x00 37 #define STM32_GPIO_TYPER 0x04 38 #define STM32_GPIO_SPEEDR 0x08 39 #define STM32_GPIO_PUPDR 0x0c 40 #define STM32_GPIO_IDR 0x10 41 #define STM32_GPIO_ODR 0x14 42 #define STM32_GPIO_BSRR 0x18 43 #define STM32_GPIO_LCKR 0x1c 44 #define STM32_GPIO_AFRL 0x20 45 #define STM32_GPIO_AFRH 0x24 46 47 /* custom bitfield to backup pin status */ 48 #define STM32_GPIO_BKP_MODE_SHIFT 0 49 #define STM32_GPIO_BKP_MODE_MASK GENMASK(1, 0) 50 #define STM32_GPIO_BKP_ALT_SHIFT 2 51 #define STM32_GPIO_BKP_ALT_MASK GENMASK(5, 2) 52 #define STM32_GPIO_BKP_SPEED_SHIFT 6 53 #define STM32_GPIO_BKP_SPEED_MASK GENMASK(7, 6) 54 #define STM32_GPIO_BKP_PUPD_SHIFT 8 55 #define STM32_GPIO_BKP_PUPD_MASK GENMASK(9, 8) 56 #define STM32_GPIO_BKP_TYPE 10 57 #define STM32_GPIO_BKP_VAL 11 58 59 #define STM32_GPIO_PINS_PER_BANK 16 60 #define STM32_GPIO_IRQ_LINE 16 61 62 #define SYSCFG_IRQMUX_MASK GENMASK(3, 0) 63 64 #define gpio_range_to_bank(chip) \ 65 container_of(chip, struct stm32_gpio_bank, range) 66 67 #define HWSPINLOCK_TIMEOUT 5 /* msec */ 68 69 static const char * const stm32_gpio_functions[] = { 70 "gpio", "af0", "af1", 71 "af2", "af3", "af4", 72 "af5", "af6", "af7", 73 "af8", "af9", "af10", 74 "af11", "af12", "af13", 75 "af14", "af15", "analog", 76 }; 77 78 struct stm32_pinctrl_group { 79 const char *name; 80 unsigned long config; 81 unsigned pin; 82 }; 83 84 struct stm32_gpio_bank { 85 void __iomem *base; 86 struct clk *clk; 87 spinlock_t lock; 88 struct gpio_chip gpio_chip; 89 struct pinctrl_gpio_range range; 90 struct fwnode_handle *fwnode; 91 struct irq_domain *domain; 92 u32 bank_nr; 93 u32 bank_ioport_nr; 94 u32 pin_backup[STM32_GPIO_PINS_PER_BANK]; 95 }; 96 97 struct stm32_pinctrl { 98 struct device *dev; 99 struct pinctrl_dev *pctl_dev; 100 struct pinctrl_desc pctl_desc; 101 struct stm32_pinctrl_group *groups; 102 unsigned ngroups; 103 const char **grp_names; 104 struct stm32_gpio_bank *banks; 105 unsigned nbanks; 106 const struct stm32_pinctrl_match_data *match_data; 107 struct irq_domain *domain; 108 struct regmap *regmap; 109 struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK]; 110 struct hwspinlock *hwlock; 111 struct stm32_desc_pin *pins; 112 u32 npins; 113 u32 pkg; 114 u16 irqmux_map; 115 spinlock_t irqmux_lock; 116 }; 117 118 static inline int stm32_gpio_pin(int gpio) 119 { 120 return gpio % STM32_GPIO_PINS_PER_BANK; 121 } 122 123 static inline u32 stm32_gpio_get_mode(u32 function) 124 { 125 switch (function) { 126 case STM32_PIN_GPIO: 127 return 0; 128 case STM32_PIN_AF(0) ... STM32_PIN_AF(15): 129 return 2; 130 case STM32_PIN_ANALOG: 131 return 3; 132 } 133 134 return 0; 135 } 136 137 static inline u32 stm32_gpio_get_alt(u32 function) 138 { 139 switch (function) { 140 case STM32_PIN_GPIO: 141 return 0; 142 case STM32_PIN_AF(0) ... STM32_PIN_AF(15): 143 return function - 1; 144 case STM32_PIN_ANALOG: 145 return 0; 146 } 147 148 return 0; 149 } 150 151 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank, 152 u32 offset, u32 value) 153 { 154 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL); 155 bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL; 156 } 157 158 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset, 159 u32 mode, u32 alt) 160 { 161 bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK | 162 STM32_GPIO_BKP_ALT_MASK); 163 bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT; 164 bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT; 165 } 166 167 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset, 168 u32 drive) 169 { 170 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE); 171 bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE; 172 } 173 174 static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset, 175 u32 speed) 176 { 177 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK; 178 bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT; 179 } 180 181 static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset, 182 u32 bias) 183 { 184 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK; 185 bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT; 186 } 187 188 /* GPIO functions */ 189 190 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank, 191 unsigned offset, int value) 192 { 193 stm32_gpio_backup_value(bank, offset, value); 194 195 if (!value) 196 offset += STM32_GPIO_PINS_PER_BANK; 197 198 clk_enable(bank->clk); 199 200 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR); 201 202 clk_disable(bank->clk); 203 } 204 205 static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset) 206 { 207 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 208 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 209 struct pinctrl_gpio_range *range; 210 int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK); 211 212 range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin); 213 if (!range) { 214 dev_err(pctl->dev, "pin %d not in range.\n", pin); 215 return -EINVAL; 216 } 217 218 return pinctrl_gpio_request(chip->base + offset); 219 } 220 221 static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset) 222 { 223 pinctrl_gpio_free(chip->base + offset); 224 } 225 226 static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset) 227 { 228 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 229 int ret; 230 231 clk_enable(bank->clk); 232 233 ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset)); 234 235 clk_disable(bank->clk); 236 237 return ret; 238 } 239 240 static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 241 { 242 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 243 244 __stm32_gpio_set(bank, offset, value); 245 } 246 247 static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 248 { 249 return pinctrl_gpio_direction_input(chip->base + offset); 250 } 251 252 static int stm32_gpio_direction_output(struct gpio_chip *chip, 253 unsigned offset, int value) 254 { 255 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 256 257 __stm32_gpio_set(bank, offset, value); 258 pinctrl_gpio_direction_output(chip->base + offset); 259 260 return 0; 261 } 262 263 264 static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) 265 { 266 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 267 struct irq_fwspec fwspec; 268 269 fwspec.fwnode = bank->fwnode; 270 fwspec.param_count = 2; 271 fwspec.param[0] = offset; 272 fwspec.param[1] = IRQ_TYPE_NONE; 273 274 return irq_create_fwspec_mapping(&fwspec); 275 } 276 277 static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 278 { 279 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 280 int pin = stm32_gpio_pin(offset); 281 int ret; 282 u32 mode, alt; 283 284 stm32_pmx_get_mode(bank, pin, &mode, &alt); 285 if ((alt == 0) && (mode == 0)) 286 ret = 1; 287 else if ((alt == 0) && (mode == 1)) 288 ret = 0; 289 else 290 ret = -EINVAL; 291 292 return ret; 293 } 294 295 static const struct gpio_chip stm32_gpio_template = { 296 .request = stm32_gpio_request, 297 .free = stm32_gpio_free, 298 .get = stm32_gpio_get, 299 .set = stm32_gpio_set, 300 .direction_input = stm32_gpio_direction_input, 301 .direction_output = stm32_gpio_direction_output, 302 .to_irq = stm32_gpio_to_irq, 303 .get_direction = stm32_gpio_get_direction, 304 }; 305 306 static int stm32_gpio_irq_request_resources(struct irq_data *irq_data) 307 { 308 struct stm32_gpio_bank *bank = irq_data->domain->host_data; 309 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 310 int ret; 311 312 ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq); 313 if (ret) 314 return ret; 315 316 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq); 317 if (ret) { 318 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", 319 irq_data->hwirq); 320 return ret; 321 } 322 323 return 0; 324 } 325 326 static void stm32_gpio_irq_release_resources(struct irq_data *irq_data) 327 { 328 struct stm32_gpio_bank *bank = irq_data->domain->host_data; 329 330 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq); 331 } 332 333 static struct irq_chip stm32_gpio_irq_chip = { 334 .name = "stm32gpio", 335 .irq_eoi = irq_chip_eoi_parent, 336 .irq_ack = irq_chip_ack_parent, 337 .irq_mask = irq_chip_mask_parent, 338 .irq_unmask = irq_chip_unmask_parent, 339 .irq_set_type = irq_chip_set_type_parent, 340 .irq_set_wake = irq_chip_set_wake_parent, 341 .irq_request_resources = stm32_gpio_irq_request_resources, 342 .irq_release_resources = stm32_gpio_irq_release_resources, 343 }; 344 345 static int stm32_gpio_domain_translate(struct irq_domain *d, 346 struct irq_fwspec *fwspec, 347 unsigned long *hwirq, 348 unsigned int *type) 349 { 350 if ((fwspec->param_count != 2) || 351 (fwspec->param[0] >= STM32_GPIO_IRQ_LINE)) 352 return -EINVAL; 353 354 *hwirq = fwspec->param[0]; 355 *type = fwspec->param[1]; 356 return 0; 357 } 358 359 static int stm32_gpio_domain_activate(struct irq_domain *d, 360 struct irq_data *irq_data, bool reserve) 361 { 362 struct stm32_gpio_bank *bank = d->host_data; 363 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 364 unsigned long flags; 365 int ret = 0; 366 367 /* 368 * gpio irq mux is shared between several banks, a lock has to be done 369 * to avoid overriding. 370 */ 371 spin_lock_irqsave(&pctl->irqmux_lock, flags); 372 if (pctl->hwlock) 373 ret = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT); 374 375 if (ret) { 376 dev_err(pctl->dev, "Can't get hwspinlock\n"); 377 goto unlock; 378 } 379 380 if (pctl->irqmux_map & BIT(irq_data->hwirq)) { 381 dev_err(pctl->dev, "irq line %ld already requested.\n", 382 irq_data->hwirq); 383 ret = -EBUSY; 384 if (pctl->hwlock) 385 hwspin_unlock(pctl->hwlock); 386 goto unlock; 387 } else { 388 pctl->irqmux_map |= BIT(irq_data->hwirq); 389 } 390 391 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr); 392 393 if (pctl->hwlock) 394 hwspin_unlock(pctl->hwlock); 395 396 unlock: 397 spin_unlock_irqrestore(&pctl->irqmux_lock, flags); 398 return ret; 399 } 400 401 static void stm32_gpio_domain_deactivate(struct irq_domain *d, 402 struct irq_data *irq_data) 403 { 404 struct stm32_gpio_bank *bank = d->host_data; 405 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 406 unsigned long flags; 407 408 spin_lock_irqsave(&pctl->irqmux_lock, flags); 409 pctl->irqmux_map &= ~BIT(irq_data->hwirq); 410 spin_unlock_irqrestore(&pctl->irqmux_lock, flags); 411 } 412 413 static int stm32_gpio_domain_alloc(struct irq_domain *d, 414 unsigned int virq, 415 unsigned int nr_irqs, void *data) 416 { 417 struct stm32_gpio_bank *bank = d->host_data; 418 struct irq_fwspec *fwspec = data; 419 struct irq_fwspec parent_fwspec; 420 irq_hw_number_t hwirq; 421 422 hwirq = fwspec->param[0]; 423 parent_fwspec.fwnode = d->parent->fwnode; 424 parent_fwspec.param_count = 2; 425 parent_fwspec.param[0] = fwspec->param[0]; 426 parent_fwspec.param[1] = fwspec->param[1]; 427 428 irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip, 429 bank); 430 431 return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec); 432 } 433 434 static const struct irq_domain_ops stm32_gpio_domain_ops = { 435 .translate = stm32_gpio_domain_translate, 436 .alloc = stm32_gpio_domain_alloc, 437 .free = irq_domain_free_irqs_common, 438 .activate = stm32_gpio_domain_activate, 439 .deactivate = stm32_gpio_domain_deactivate, 440 }; 441 442 /* Pinctrl functions */ 443 static struct stm32_pinctrl_group * 444 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin) 445 { 446 int i; 447 448 for (i = 0; i < pctl->ngroups; i++) { 449 struct stm32_pinctrl_group *grp = pctl->groups + i; 450 451 if (grp->pin == pin) 452 return grp; 453 } 454 455 return NULL; 456 } 457 458 static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl, 459 u32 pin_num, u32 fnum) 460 { 461 int i; 462 463 for (i = 0; i < pctl->npins; i++) { 464 const struct stm32_desc_pin *pin = pctl->pins + i; 465 const struct stm32_desc_function *func = pin->functions; 466 467 if (pin->pin.number != pin_num) 468 continue; 469 470 while (func && func->name) { 471 if (func->num == fnum) 472 return true; 473 func++; 474 } 475 476 break; 477 } 478 479 return false; 480 } 481 482 static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl, 483 u32 pin, u32 fnum, struct stm32_pinctrl_group *grp, 484 struct pinctrl_map **map, unsigned *reserved_maps, 485 unsigned *num_maps) 486 { 487 if (*num_maps == *reserved_maps) 488 return -ENOSPC; 489 490 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; 491 (*map)[*num_maps].data.mux.group = grp->name; 492 493 if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) { 494 dev_err(pctl->dev, "invalid function %d on pin %d .\n", 495 fnum, pin); 496 return -EINVAL; 497 } 498 499 (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum]; 500 (*num_maps)++; 501 502 return 0; 503 } 504 505 static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, 506 struct device_node *node, 507 struct pinctrl_map **map, 508 unsigned *reserved_maps, 509 unsigned *num_maps) 510 { 511 struct stm32_pinctrl *pctl; 512 struct stm32_pinctrl_group *grp; 513 struct property *pins; 514 u32 pinfunc, pin, func; 515 unsigned long *configs; 516 unsigned int num_configs; 517 bool has_config = 0; 518 unsigned reserve = 0; 519 int num_pins, num_funcs, maps_per_pin, i, err = 0; 520 521 pctl = pinctrl_dev_get_drvdata(pctldev); 522 523 pins = of_find_property(node, "pinmux", NULL); 524 if (!pins) { 525 dev_err(pctl->dev, "missing pins property in node %pOFn .\n", 526 node); 527 return -EINVAL; 528 } 529 530 err = pinconf_generic_parse_dt_config(node, pctldev, &configs, 531 &num_configs); 532 if (err) 533 return err; 534 535 if (num_configs) 536 has_config = 1; 537 538 num_pins = pins->length / sizeof(u32); 539 num_funcs = num_pins; 540 maps_per_pin = 0; 541 if (num_funcs) 542 maps_per_pin++; 543 if (has_config && num_pins >= 1) 544 maps_per_pin++; 545 546 if (!num_pins || !maps_per_pin) { 547 err = -EINVAL; 548 goto exit; 549 } 550 551 reserve = num_pins * maps_per_pin; 552 553 err = pinctrl_utils_reserve_map(pctldev, map, 554 reserved_maps, num_maps, reserve); 555 if (err) 556 goto exit; 557 558 for (i = 0; i < num_pins; i++) { 559 err = of_property_read_u32_index(node, "pinmux", 560 i, &pinfunc); 561 if (err) 562 goto exit; 563 564 pin = STM32_GET_PIN_NO(pinfunc); 565 func = STM32_GET_PIN_FUNC(pinfunc); 566 567 if (!stm32_pctrl_is_function_valid(pctl, pin, func)) { 568 dev_err(pctl->dev, "invalid function.\n"); 569 err = -EINVAL; 570 goto exit; 571 } 572 573 grp = stm32_pctrl_find_group_by_pin(pctl, pin); 574 if (!grp) { 575 dev_err(pctl->dev, "unable to match pin %d to group\n", 576 pin); 577 err = -EINVAL; 578 goto exit; 579 } 580 581 err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map, 582 reserved_maps, num_maps); 583 if (err) 584 goto exit; 585 586 if (has_config) { 587 err = pinctrl_utils_add_map_configs(pctldev, map, 588 reserved_maps, num_maps, grp->name, 589 configs, num_configs, 590 PIN_MAP_TYPE_CONFIGS_GROUP); 591 if (err) 592 goto exit; 593 } 594 } 595 596 exit: 597 kfree(configs); 598 return err; 599 } 600 601 static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 602 struct device_node *np_config, 603 struct pinctrl_map **map, unsigned *num_maps) 604 { 605 struct device_node *np; 606 unsigned reserved_maps; 607 int ret; 608 609 *map = NULL; 610 *num_maps = 0; 611 reserved_maps = 0; 612 613 for_each_child_of_node(np_config, np) { 614 ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map, 615 &reserved_maps, num_maps); 616 if (ret < 0) { 617 pinctrl_utils_free_map(pctldev, *map, *num_maps); 618 return ret; 619 } 620 } 621 622 return 0; 623 } 624 625 static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev) 626 { 627 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 628 629 return pctl->ngroups; 630 } 631 632 static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev, 633 unsigned group) 634 { 635 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 636 637 return pctl->groups[group].name; 638 } 639 640 static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev, 641 unsigned group, 642 const unsigned **pins, 643 unsigned *num_pins) 644 { 645 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 646 647 *pins = (unsigned *)&pctl->groups[group].pin; 648 *num_pins = 1; 649 650 return 0; 651 } 652 653 static const struct pinctrl_ops stm32_pctrl_ops = { 654 .dt_node_to_map = stm32_pctrl_dt_node_to_map, 655 .dt_free_map = pinctrl_utils_free_map, 656 .get_groups_count = stm32_pctrl_get_groups_count, 657 .get_group_name = stm32_pctrl_get_group_name, 658 .get_group_pins = stm32_pctrl_get_group_pins, 659 }; 660 661 662 /* Pinmux functions */ 663 664 static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 665 { 666 return ARRAY_SIZE(stm32_gpio_functions); 667 } 668 669 static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev, 670 unsigned selector) 671 { 672 return stm32_gpio_functions[selector]; 673 } 674 675 static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev, 676 unsigned function, 677 const char * const **groups, 678 unsigned * const num_groups) 679 { 680 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 681 682 *groups = pctl->grp_names; 683 *num_groups = pctl->ngroups; 684 685 return 0; 686 } 687 688 static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank, 689 int pin, u32 mode, u32 alt) 690 { 691 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 692 u32 val; 693 int alt_shift = (pin % 8) * 4; 694 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; 695 unsigned long flags; 696 int err = 0; 697 698 clk_enable(bank->clk); 699 spin_lock_irqsave(&bank->lock, flags); 700 701 if (pctl->hwlock) 702 err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT); 703 704 if (err) { 705 dev_err(pctl->dev, "Can't get hwspinlock\n"); 706 goto unlock; 707 } 708 709 val = readl_relaxed(bank->base + alt_offset); 710 val &= ~GENMASK(alt_shift + 3, alt_shift); 711 val |= (alt << alt_shift); 712 writel_relaxed(val, bank->base + alt_offset); 713 714 val = readl_relaxed(bank->base + STM32_GPIO_MODER); 715 val &= ~GENMASK(pin * 2 + 1, pin * 2); 716 val |= mode << (pin * 2); 717 writel_relaxed(val, bank->base + STM32_GPIO_MODER); 718 719 if (pctl->hwlock) 720 hwspin_unlock(pctl->hwlock); 721 722 stm32_gpio_backup_mode(bank, pin, mode, alt); 723 724 unlock: 725 spin_unlock_irqrestore(&bank->lock, flags); 726 clk_disable(bank->clk); 727 728 return err; 729 } 730 731 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, 732 u32 *alt) 733 { 734 u32 val; 735 int alt_shift = (pin % 8) * 4; 736 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; 737 unsigned long flags; 738 739 clk_enable(bank->clk); 740 spin_lock_irqsave(&bank->lock, flags); 741 742 val = readl_relaxed(bank->base + alt_offset); 743 val &= GENMASK(alt_shift + 3, alt_shift); 744 *alt = val >> alt_shift; 745 746 val = readl_relaxed(bank->base + STM32_GPIO_MODER); 747 val &= GENMASK(pin * 2 + 1, pin * 2); 748 *mode = val >> (pin * 2); 749 750 spin_unlock_irqrestore(&bank->lock, flags); 751 clk_disable(bank->clk); 752 } 753 754 static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev, 755 unsigned function, 756 unsigned group) 757 { 758 bool ret; 759 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 760 struct stm32_pinctrl_group *g = pctl->groups + group; 761 struct pinctrl_gpio_range *range; 762 struct stm32_gpio_bank *bank; 763 u32 mode, alt; 764 int pin; 765 766 ret = stm32_pctrl_is_function_valid(pctl, g->pin, function); 767 if (!ret) { 768 dev_err(pctl->dev, "invalid function %d on group %d .\n", 769 function, group); 770 return -EINVAL; 771 } 772 773 range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin); 774 if (!range) { 775 dev_err(pctl->dev, "No gpio range defined.\n"); 776 return -EINVAL; 777 } 778 779 bank = gpiochip_get_data(range->gc); 780 pin = stm32_gpio_pin(g->pin); 781 782 mode = stm32_gpio_get_mode(function); 783 alt = stm32_gpio_get_alt(function); 784 785 return stm32_pmx_set_mode(bank, pin, mode, alt); 786 } 787 788 static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 789 struct pinctrl_gpio_range *range, unsigned gpio, 790 bool input) 791 { 792 struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc); 793 int pin = stm32_gpio_pin(gpio); 794 795 return stm32_pmx_set_mode(bank, pin, !input, 0); 796 } 797 798 static const struct pinmux_ops stm32_pmx_ops = { 799 .get_functions_count = stm32_pmx_get_funcs_cnt, 800 .get_function_name = stm32_pmx_get_func_name, 801 .get_function_groups = stm32_pmx_get_func_groups, 802 .set_mux = stm32_pmx_set_mux, 803 .gpio_set_direction = stm32_pmx_gpio_set_direction, 804 .strict = true, 805 }; 806 807 /* Pinconf functions */ 808 809 static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank, 810 unsigned offset, u32 drive) 811 { 812 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 813 unsigned long flags; 814 u32 val; 815 int err = 0; 816 817 clk_enable(bank->clk); 818 spin_lock_irqsave(&bank->lock, flags); 819 820 if (pctl->hwlock) 821 err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT); 822 823 if (err) { 824 dev_err(pctl->dev, "Can't get hwspinlock\n"); 825 goto unlock; 826 } 827 828 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); 829 val &= ~BIT(offset); 830 val |= drive << offset; 831 writel_relaxed(val, bank->base + STM32_GPIO_TYPER); 832 833 if (pctl->hwlock) 834 hwspin_unlock(pctl->hwlock); 835 836 stm32_gpio_backup_driving(bank, offset, drive); 837 838 unlock: 839 spin_unlock_irqrestore(&bank->lock, flags); 840 clk_disable(bank->clk); 841 842 return err; 843 } 844 845 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank, 846 unsigned int offset) 847 { 848 unsigned long flags; 849 u32 val; 850 851 clk_enable(bank->clk); 852 spin_lock_irqsave(&bank->lock, flags); 853 854 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); 855 val &= BIT(offset); 856 857 spin_unlock_irqrestore(&bank->lock, flags); 858 clk_disable(bank->clk); 859 860 return (val >> offset); 861 } 862 863 static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank, 864 unsigned offset, u32 speed) 865 { 866 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 867 unsigned long flags; 868 u32 val; 869 int err = 0; 870 871 clk_enable(bank->clk); 872 spin_lock_irqsave(&bank->lock, flags); 873 874 if (pctl->hwlock) 875 err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT); 876 877 if (err) { 878 dev_err(pctl->dev, "Can't get hwspinlock\n"); 879 goto unlock; 880 } 881 882 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); 883 val &= ~GENMASK(offset * 2 + 1, offset * 2); 884 val |= speed << (offset * 2); 885 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR); 886 887 if (pctl->hwlock) 888 hwspin_unlock(pctl->hwlock); 889 890 stm32_gpio_backup_speed(bank, offset, speed); 891 892 unlock: 893 spin_unlock_irqrestore(&bank->lock, flags); 894 clk_disable(bank->clk); 895 896 return err; 897 } 898 899 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank, 900 unsigned int offset) 901 { 902 unsigned long flags; 903 u32 val; 904 905 clk_enable(bank->clk); 906 spin_lock_irqsave(&bank->lock, flags); 907 908 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); 909 val &= GENMASK(offset * 2 + 1, offset * 2); 910 911 spin_unlock_irqrestore(&bank->lock, flags); 912 clk_disable(bank->clk); 913 914 return (val >> (offset * 2)); 915 } 916 917 static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank, 918 unsigned offset, u32 bias) 919 { 920 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 921 unsigned long flags; 922 u32 val; 923 int err = 0; 924 925 clk_enable(bank->clk); 926 spin_lock_irqsave(&bank->lock, flags); 927 928 if (pctl->hwlock) 929 err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT); 930 931 if (err) { 932 dev_err(pctl->dev, "Can't get hwspinlock\n"); 933 goto unlock; 934 } 935 936 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); 937 val &= ~GENMASK(offset * 2 + 1, offset * 2); 938 val |= bias << (offset * 2); 939 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR); 940 941 if (pctl->hwlock) 942 hwspin_unlock(pctl->hwlock); 943 944 stm32_gpio_backup_bias(bank, offset, bias); 945 946 unlock: 947 spin_unlock_irqrestore(&bank->lock, flags); 948 clk_disable(bank->clk); 949 950 return err; 951 } 952 953 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank, 954 unsigned int offset) 955 { 956 unsigned long flags; 957 u32 val; 958 959 clk_enable(bank->clk); 960 spin_lock_irqsave(&bank->lock, flags); 961 962 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); 963 val &= GENMASK(offset * 2 + 1, offset * 2); 964 965 spin_unlock_irqrestore(&bank->lock, flags); 966 clk_disable(bank->clk); 967 968 return (val >> (offset * 2)); 969 } 970 971 static bool stm32_pconf_get(struct stm32_gpio_bank *bank, 972 unsigned int offset, bool dir) 973 { 974 unsigned long flags; 975 u32 val; 976 977 clk_enable(bank->clk); 978 spin_lock_irqsave(&bank->lock, flags); 979 980 if (dir) 981 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & 982 BIT(offset)); 983 else 984 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) & 985 BIT(offset)); 986 987 spin_unlock_irqrestore(&bank->lock, flags); 988 clk_disable(bank->clk); 989 990 return val; 991 } 992 993 static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev, 994 unsigned int pin, enum pin_config_param param, 995 enum pin_config_param arg) 996 { 997 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 998 struct pinctrl_gpio_range *range; 999 struct stm32_gpio_bank *bank; 1000 int offset, ret = 0; 1001 1002 range = pinctrl_find_gpio_range_from_pin(pctldev, pin); 1003 if (!range) { 1004 dev_err(pctl->dev, "No gpio range defined.\n"); 1005 return -EINVAL; 1006 } 1007 1008 bank = gpiochip_get_data(range->gc); 1009 offset = stm32_gpio_pin(pin); 1010 1011 switch (param) { 1012 case PIN_CONFIG_DRIVE_PUSH_PULL: 1013 ret = stm32_pconf_set_driving(bank, offset, 0); 1014 break; 1015 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1016 ret = stm32_pconf_set_driving(bank, offset, 1); 1017 break; 1018 case PIN_CONFIG_SLEW_RATE: 1019 ret = stm32_pconf_set_speed(bank, offset, arg); 1020 break; 1021 case PIN_CONFIG_BIAS_DISABLE: 1022 ret = stm32_pconf_set_bias(bank, offset, 0); 1023 break; 1024 case PIN_CONFIG_BIAS_PULL_UP: 1025 ret = stm32_pconf_set_bias(bank, offset, 1); 1026 break; 1027 case PIN_CONFIG_BIAS_PULL_DOWN: 1028 ret = stm32_pconf_set_bias(bank, offset, 2); 1029 break; 1030 case PIN_CONFIG_OUTPUT: 1031 __stm32_gpio_set(bank, offset, arg); 1032 ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false); 1033 break; 1034 default: 1035 ret = -EINVAL; 1036 } 1037 1038 return ret; 1039 } 1040 1041 static int stm32_pconf_group_get(struct pinctrl_dev *pctldev, 1042 unsigned group, 1043 unsigned long *config) 1044 { 1045 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1046 1047 *config = pctl->groups[group].config; 1048 1049 return 0; 1050 } 1051 1052 static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, 1053 unsigned long *configs, unsigned num_configs) 1054 { 1055 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1056 struct stm32_pinctrl_group *g = &pctl->groups[group]; 1057 int i, ret; 1058 1059 for (i = 0; i < num_configs; i++) { 1060 ret = stm32_pconf_parse_conf(pctldev, g->pin, 1061 pinconf_to_config_param(configs[i]), 1062 pinconf_to_config_argument(configs[i])); 1063 if (ret < 0) 1064 return ret; 1065 1066 g->config = configs[i]; 1067 } 1068 1069 return 0; 1070 } 1071 1072 static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev, 1073 struct seq_file *s, 1074 unsigned int pin) 1075 { 1076 struct pinctrl_gpio_range *range; 1077 struct stm32_gpio_bank *bank; 1078 int offset; 1079 u32 mode, alt, drive, speed, bias; 1080 static const char * const modes[] = { 1081 "input", "output", "alternate", "analog" }; 1082 static const char * const speeds[] = { 1083 "low", "medium", "high", "very high" }; 1084 static const char * const biasing[] = { 1085 "floating", "pull up", "pull down", "" }; 1086 bool val; 1087 1088 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); 1089 if (!range) 1090 return; 1091 1092 bank = gpiochip_get_data(range->gc); 1093 offset = stm32_gpio_pin(pin); 1094 1095 stm32_pmx_get_mode(bank, offset, &mode, &alt); 1096 bias = stm32_pconf_get_bias(bank, offset); 1097 1098 seq_printf(s, "%s ", modes[mode]); 1099 1100 switch (mode) { 1101 /* input */ 1102 case 0: 1103 val = stm32_pconf_get(bank, offset, true); 1104 seq_printf(s, "- %s - %s", 1105 val ? "high" : "low", 1106 biasing[bias]); 1107 break; 1108 1109 /* output */ 1110 case 1: 1111 drive = stm32_pconf_get_driving(bank, offset); 1112 speed = stm32_pconf_get_speed(bank, offset); 1113 val = stm32_pconf_get(bank, offset, false); 1114 seq_printf(s, "- %s - %s - %s - %s %s", 1115 val ? "high" : "low", 1116 drive ? "open drain" : "push pull", 1117 biasing[bias], 1118 speeds[speed], "speed"); 1119 break; 1120 1121 /* alternate */ 1122 case 2: 1123 drive = stm32_pconf_get_driving(bank, offset); 1124 speed = stm32_pconf_get_speed(bank, offset); 1125 seq_printf(s, "%d - %s - %s - %s %s", alt, 1126 drive ? "open drain" : "push pull", 1127 biasing[bias], 1128 speeds[speed], "speed"); 1129 break; 1130 1131 /* analog */ 1132 case 3: 1133 break; 1134 } 1135 } 1136 1137 1138 static const struct pinconf_ops stm32_pconf_ops = { 1139 .pin_config_group_get = stm32_pconf_group_get, 1140 .pin_config_group_set = stm32_pconf_group_set, 1141 .pin_config_dbg_show = stm32_pconf_dbg_show, 1142 }; 1143 1144 static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, 1145 struct device_node *np) 1146 { 1147 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks]; 1148 int bank_ioport_nr; 1149 struct pinctrl_gpio_range *range = &bank->range; 1150 struct of_phandle_args args; 1151 struct device *dev = pctl->dev; 1152 struct resource res; 1153 struct reset_control *rstc; 1154 int npins = STM32_GPIO_PINS_PER_BANK; 1155 int bank_nr, err; 1156 1157 rstc = of_reset_control_get_exclusive(np, NULL); 1158 if (!IS_ERR(rstc)) 1159 reset_control_deassert(rstc); 1160 1161 if (of_address_to_resource(np, 0, &res)) 1162 return -ENODEV; 1163 1164 bank->base = devm_ioremap_resource(dev, &res); 1165 if (IS_ERR(bank->base)) 1166 return PTR_ERR(bank->base); 1167 1168 bank->clk = of_clk_get_by_name(np, NULL); 1169 if (IS_ERR(bank->clk)) { 1170 dev_err(dev, "failed to get clk (%ld)\n", PTR_ERR(bank->clk)); 1171 return PTR_ERR(bank->clk); 1172 } 1173 1174 err = clk_prepare(bank->clk); 1175 if (err) { 1176 dev_err(dev, "failed to prepare clk (%d)\n", err); 1177 return err; 1178 } 1179 1180 bank->gpio_chip = stm32_gpio_template; 1181 1182 of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label); 1183 1184 if (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args)) { 1185 bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK; 1186 bank->gpio_chip.base = args.args[1]; 1187 } else { 1188 bank_nr = pctl->nbanks; 1189 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; 1190 range->name = bank->gpio_chip.label; 1191 range->id = bank_nr; 1192 range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK; 1193 range->base = range->id * STM32_GPIO_PINS_PER_BANK; 1194 range->npins = npins; 1195 range->gc = &bank->gpio_chip; 1196 pinctrl_add_gpio_range(pctl->pctl_dev, 1197 &pctl->banks[bank_nr].range); 1198 } 1199 1200 if (of_property_read_u32(np, "st,bank-ioport", &bank_ioport_nr)) 1201 bank_ioport_nr = bank_nr; 1202 1203 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; 1204 1205 bank->gpio_chip.ngpio = npins; 1206 bank->gpio_chip.of_node = np; 1207 bank->gpio_chip.parent = dev; 1208 bank->bank_nr = bank_nr; 1209 bank->bank_ioport_nr = bank_ioport_nr; 1210 spin_lock_init(&bank->lock); 1211 1212 /* create irq hierarchical domain */ 1213 bank->fwnode = of_node_to_fwnode(np); 1214 1215 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, 1216 STM32_GPIO_IRQ_LINE, bank->fwnode, 1217 &stm32_gpio_domain_ops, bank); 1218 1219 if (!bank->domain) 1220 return -ENODEV; 1221 1222 err = gpiochip_add_data(&bank->gpio_chip, bank); 1223 if (err) { 1224 dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr); 1225 return err; 1226 } 1227 1228 dev_info(dev, "%s bank added\n", bank->gpio_chip.label); 1229 return 0; 1230 } 1231 1232 static struct irq_domain *stm32_pctrl_get_irq_domain(struct device_node *np) 1233 { 1234 struct device_node *parent; 1235 struct irq_domain *domain; 1236 1237 if (!of_find_property(np, "interrupt-parent", NULL)) 1238 return NULL; 1239 1240 parent = of_irq_find_parent(np); 1241 if (!parent) 1242 return ERR_PTR(-ENXIO); 1243 1244 domain = irq_find_host(parent); 1245 if (!domain) 1246 /* domain not registered yet */ 1247 return ERR_PTR(-EPROBE_DEFER); 1248 1249 return domain; 1250 } 1251 1252 static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev, 1253 struct stm32_pinctrl *pctl) 1254 { 1255 struct device_node *np = pdev->dev.of_node; 1256 struct device *dev = &pdev->dev; 1257 struct regmap *rm; 1258 int offset, ret, i; 1259 int mask, mask_width; 1260 1261 pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); 1262 if (IS_ERR(pctl->regmap)) 1263 return PTR_ERR(pctl->regmap); 1264 1265 rm = pctl->regmap; 1266 1267 ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset); 1268 if (ret) 1269 return ret; 1270 1271 ret = of_property_read_u32_index(np, "st,syscfg", 2, &mask); 1272 if (ret) 1273 mask = SYSCFG_IRQMUX_MASK; 1274 1275 mask_width = fls(mask); 1276 1277 for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) { 1278 struct reg_field mux; 1279 1280 mux.reg = offset + (i / 4) * 4; 1281 mux.lsb = (i % 4) * mask_width; 1282 mux.msb = mux.lsb + mask_width - 1; 1283 1284 dev_dbg(dev, "irqmux%d: reg:%#x, lsb:%d, msb:%d\n", 1285 i, mux.reg, mux.lsb, mux.msb); 1286 1287 pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux); 1288 if (IS_ERR(pctl->irqmux[i])) 1289 return PTR_ERR(pctl->irqmux[i]); 1290 } 1291 1292 return 0; 1293 } 1294 1295 static int stm32_pctrl_build_state(struct platform_device *pdev) 1296 { 1297 struct stm32_pinctrl *pctl = platform_get_drvdata(pdev); 1298 int i; 1299 1300 pctl->ngroups = pctl->npins; 1301 1302 /* Allocate groups */ 1303 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups, 1304 sizeof(*pctl->groups), GFP_KERNEL); 1305 if (!pctl->groups) 1306 return -ENOMEM; 1307 1308 /* We assume that one pin is one group, use pin name as group name. */ 1309 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups, 1310 sizeof(*pctl->grp_names), GFP_KERNEL); 1311 if (!pctl->grp_names) 1312 return -ENOMEM; 1313 1314 for (i = 0; i < pctl->npins; i++) { 1315 const struct stm32_desc_pin *pin = pctl->pins + i; 1316 struct stm32_pinctrl_group *group = pctl->groups + i; 1317 1318 group->name = pin->pin.name; 1319 group->pin = pin->pin.number; 1320 pctl->grp_names[i] = pin->pin.name; 1321 } 1322 1323 return 0; 1324 } 1325 1326 static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl, 1327 struct stm32_desc_pin *pins) 1328 { 1329 const struct stm32_desc_pin *p; 1330 int i, nb_pins_available = 0; 1331 1332 for (i = 0; i < pctl->match_data->npins; i++) { 1333 p = pctl->match_data->pins + i; 1334 if (pctl->pkg && !(pctl->pkg & p->pkg)) 1335 continue; 1336 pins->pin = p->pin; 1337 pins->functions = p->functions; 1338 pins++; 1339 nb_pins_available++; 1340 } 1341 1342 pctl->npins = nb_pins_available; 1343 1344 return 0; 1345 } 1346 1347 static void stm32_pctl_get_package(struct device_node *np, 1348 struct stm32_pinctrl *pctl) 1349 { 1350 if (of_property_read_u32(np, "st,package", &pctl->pkg)) { 1351 pctl->pkg = 0; 1352 dev_warn(pctl->dev, "No package detected, use default one\n"); 1353 } else { 1354 dev_dbg(pctl->dev, "package detected: %x\n", pctl->pkg); 1355 } 1356 } 1357 1358 int stm32_pctl_probe(struct platform_device *pdev) 1359 { 1360 struct device_node *np = pdev->dev.of_node; 1361 struct device_node *child; 1362 const struct of_device_id *match; 1363 struct device *dev = &pdev->dev; 1364 struct stm32_pinctrl *pctl; 1365 struct pinctrl_pin_desc *pins; 1366 int i, ret, hwlock_id, banks = 0; 1367 1368 if (!np) 1369 return -EINVAL; 1370 1371 match = of_match_device(dev->driver->of_match_table, dev); 1372 if (!match || !match->data) 1373 return -EINVAL; 1374 1375 if (!of_find_property(np, "pins-are-numbered", NULL)) { 1376 dev_err(dev, "only support pins-are-numbered format\n"); 1377 return -EINVAL; 1378 } 1379 1380 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL); 1381 if (!pctl) 1382 return -ENOMEM; 1383 1384 platform_set_drvdata(pdev, pctl); 1385 1386 /* check for IRQ controller (may require deferred probe) */ 1387 pctl->domain = stm32_pctrl_get_irq_domain(np); 1388 if (IS_ERR(pctl->domain)) 1389 return PTR_ERR(pctl->domain); 1390 1391 /* hwspinlock is optional */ 1392 hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0); 1393 if (hwlock_id < 0) { 1394 if (hwlock_id == -EPROBE_DEFER) 1395 return hwlock_id; 1396 } else { 1397 pctl->hwlock = hwspin_lock_request_specific(hwlock_id); 1398 } 1399 1400 spin_lock_init(&pctl->irqmux_lock); 1401 1402 pctl->dev = dev; 1403 pctl->match_data = match->data; 1404 1405 /* get package information */ 1406 stm32_pctl_get_package(np, pctl); 1407 1408 pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins, 1409 sizeof(*pctl->pins), GFP_KERNEL); 1410 if (!pctl->pins) 1411 return -ENOMEM; 1412 1413 ret = stm32_pctrl_create_pins_tab(pctl, pctl->pins); 1414 if (ret) 1415 return ret; 1416 1417 ret = stm32_pctrl_build_state(pdev); 1418 if (ret) { 1419 dev_err(dev, "build state failed: %d\n", ret); 1420 return -EINVAL; 1421 } 1422 1423 if (pctl->domain) { 1424 ret = stm32_pctrl_dt_setup_irq(pdev, pctl); 1425 if (ret) 1426 return ret; 1427 } 1428 1429 pins = devm_kcalloc(&pdev->dev, pctl->npins, sizeof(*pins), 1430 GFP_KERNEL); 1431 if (!pins) 1432 return -ENOMEM; 1433 1434 for (i = 0; i < pctl->npins; i++) 1435 pins[i] = pctl->pins[i].pin; 1436 1437 pctl->pctl_desc.name = dev_name(&pdev->dev); 1438 pctl->pctl_desc.owner = THIS_MODULE; 1439 pctl->pctl_desc.pins = pins; 1440 pctl->pctl_desc.npins = pctl->npins; 1441 pctl->pctl_desc.link_consumers = true; 1442 pctl->pctl_desc.confops = &stm32_pconf_ops; 1443 pctl->pctl_desc.pctlops = &stm32_pctrl_ops; 1444 pctl->pctl_desc.pmxops = &stm32_pmx_ops; 1445 pctl->dev = &pdev->dev; 1446 1447 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc, 1448 pctl); 1449 1450 if (IS_ERR(pctl->pctl_dev)) { 1451 dev_err(&pdev->dev, "Failed pinctrl registration\n"); 1452 return PTR_ERR(pctl->pctl_dev); 1453 } 1454 1455 for_each_available_child_of_node(np, child) 1456 if (of_property_read_bool(child, "gpio-controller")) 1457 banks++; 1458 1459 if (!banks) { 1460 dev_err(dev, "at least one GPIO bank is required\n"); 1461 return -EINVAL; 1462 } 1463 pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks), 1464 GFP_KERNEL); 1465 if (!pctl->banks) 1466 return -ENOMEM; 1467 1468 for_each_available_child_of_node(np, child) { 1469 if (of_property_read_bool(child, "gpio-controller")) { 1470 ret = stm32_gpiolib_register_bank(pctl, child); 1471 if (ret) 1472 return ret; 1473 1474 pctl->nbanks++; 1475 } 1476 } 1477 1478 dev_info(dev, "Pinctrl STM32 initialized\n"); 1479 1480 return 0; 1481 } 1482 1483 static int __maybe_unused stm32_pinctrl_restore_gpio_regs( 1484 struct stm32_pinctrl *pctl, u32 pin) 1485 { 1486 const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin); 1487 u32 val, alt, mode, offset = stm32_gpio_pin(pin); 1488 struct pinctrl_gpio_range *range; 1489 struct stm32_gpio_bank *bank; 1490 bool pin_is_irq; 1491 int ret; 1492 1493 range = pinctrl_find_gpio_range_from_pin(pctl->pctl_dev, pin); 1494 if (!range) 1495 return 0; 1496 1497 pin_is_irq = gpiochip_line_is_irq(range->gc, offset); 1498 1499 if (!desc || (!pin_is_irq && !desc->gpio_owner)) 1500 return 0; 1501 1502 bank = gpiochip_get_data(range->gc); 1503 1504 alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK; 1505 alt >>= STM32_GPIO_BKP_ALT_SHIFT; 1506 mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK; 1507 mode >>= STM32_GPIO_BKP_MODE_SHIFT; 1508 1509 ret = stm32_pmx_set_mode(bank, offset, mode, alt); 1510 if (ret) 1511 return ret; 1512 1513 if (mode == 1) { 1514 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL); 1515 val = val >> STM32_GPIO_BKP_VAL; 1516 __stm32_gpio_set(bank, offset, val); 1517 } 1518 1519 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE); 1520 val >>= STM32_GPIO_BKP_TYPE; 1521 ret = stm32_pconf_set_driving(bank, offset, val); 1522 if (ret) 1523 return ret; 1524 1525 val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK; 1526 val >>= STM32_GPIO_BKP_SPEED_SHIFT; 1527 ret = stm32_pconf_set_speed(bank, offset, val); 1528 if (ret) 1529 return ret; 1530 1531 val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK; 1532 val >>= STM32_GPIO_BKP_PUPD_SHIFT; 1533 ret = stm32_pconf_set_bias(bank, offset, val); 1534 if (ret) 1535 return ret; 1536 1537 if (pin_is_irq) 1538 regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr); 1539 1540 return 0; 1541 } 1542 1543 int __maybe_unused stm32_pinctrl_resume(struct device *dev) 1544 { 1545 struct stm32_pinctrl *pctl = dev_get_drvdata(dev); 1546 struct stm32_pinctrl_group *g = pctl->groups; 1547 int i; 1548 1549 for (i = g->pin; i < g->pin + pctl->ngroups; i++) 1550 stm32_pinctrl_restore_gpio_regs(pctl, i); 1551 1552 return 0; 1553 } 1554