1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics 2017 5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 * 7 * Heavily based on Mediatek's pinctrl driver 8 */ 9 #include <linux/clk.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/hwspinlock.h> 12 #include <linux/io.h> 13 #include <linux/irq.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/of_address.h> 18 #include <linux/of_device.h> 19 #include <linux/of_irq.h> 20 #include <linux/pinctrl/consumer.h> 21 #include <linux/pinctrl/machine.h> 22 #include <linux/pinctrl/pinconf.h> 23 #include <linux/pinctrl/pinconf-generic.h> 24 #include <linux/pinctrl/pinctrl.h> 25 #include <linux/pinctrl/pinmux.h> 26 #include <linux/platform_device.h> 27 #include <linux/regmap.h> 28 #include <linux/reset.h> 29 #include <linux/slab.h> 30 31 #include "../core.h" 32 #include "../pinconf.h" 33 #include "../pinctrl-utils.h" 34 #include "pinctrl-stm32.h" 35 36 #define STM32_GPIO_MODER 0x00 37 #define STM32_GPIO_TYPER 0x04 38 #define STM32_GPIO_SPEEDR 0x08 39 #define STM32_GPIO_PUPDR 0x0c 40 #define STM32_GPIO_IDR 0x10 41 #define STM32_GPIO_ODR 0x14 42 #define STM32_GPIO_BSRR 0x18 43 #define STM32_GPIO_LCKR 0x1c 44 #define STM32_GPIO_AFRL 0x20 45 #define STM32_GPIO_AFRH 0x24 46 47 #define STM32_GPIO_PINS_PER_BANK 16 48 #define STM32_GPIO_IRQ_LINE 16 49 50 #define SYSCFG_IRQMUX_MASK GENMASK(3, 0) 51 52 #define gpio_range_to_bank(chip) \ 53 container_of(chip, struct stm32_gpio_bank, range) 54 55 #define HWSPINLOCK_TIMEOUT 5 /* msec */ 56 57 static const char * const stm32_gpio_functions[] = { 58 "gpio", "af0", "af1", 59 "af2", "af3", "af4", 60 "af5", "af6", "af7", 61 "af8", "af9", "af10", 62 "af11", "af12", "af13", 63 "af14", "af15", "analog", 64 }; 65 66 struct stm32_pinctrl_group { 67 const char *name; 68 unsigned long config; 69 unsigned pin; 70 }; 71 72 struct stm32_gpio_bank { 73 void __iomem *base; 74 struct clk *clk; 75 spinlock_t lock; 76 struct gpio_chip gpio_chip; 77 struct pinctrl_gpio_range range; 78 struct fwnode_handle *fwnode; 79 struct irq_domain *domain; 80 u32 bank_nr; 81 u32 bank_ioport_nr; 82 }; 83 84 struct stm32_pinctrl { 85 struct device *dev; 86 struct pinctrl_dev *pctl_dev; 87 struct pinctrl_desc pctl_desc; 88 struct stm32_pinctrl_group *groups; 89 unsigned ngroups; 90 const char **grp_names; 91 struct stm32_gpio_bank *banks; 92 unsigned nbanks; 93 const struct stm32_pinctrl_match_data *match_data; 94 struct irq_domain *domain; 95 struct regmap *regmap; 96 struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK]; 97 struct hwspinlock *hwlock; 98 }; 99 100 static inline int stm32_gpio_pin(int gpio) 101 { 102 return gpio % STM32_GPIO_PINS_PER_BANK; 103 } 104 105 static inline u32 stm32_gpio_get_mode(u32 function) 106 { 107 switch (function) { 108 case STM32_PIN_GPIO: 109 return 0; 110 case STM32_PIN_AF(0) ... STM32_PIN_AF(15): 111 return 2; 112 case STM32_PIN_ANALOG: 113 return 3; 114 } 115 116 return 0; 117 } 118 119 static inline u32 stm32_gpio_get_alt(u32 function) 120 { 121 switch (function) { 122 case STM32_PIN_GPIO: 123 return 0; 124 case STM32_PIN_AF(0) ... STM32_PIN_AF(15): 125 return function - 1; 126 case STM32_PIN_ANALOG: 127 return 0; 128 } 129 130 return 0; 131 } 132 133 /* GPIO functions */ 134 135 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank, 136 unsigned offset, int value) 137 { 138 if (!value) 139 offset += STM32_GPIO_PINS_PER_BANK; 140 141 clk_enable(bank->clk); 142 143 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR); 144 145 clk_disable(bank->clk); 146 } 147 148 static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset) 149 { 150 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 151 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 152 struct pinctrl_gpio_range *range; 153 int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK); 154 155 range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin); 156 if (!range) { 157 dev_err(pctl->dev, "pin %d not in range.\n", pin); 158 return -EINVAL; 159 } 160 161 return pinctrl_gpio_request(chip->base + offset); 162 } 163 164 static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset) 165 { 166 pinctrl_gpio_free(chip->base + offset); 167 } 168 169 static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset) 170 { 171 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 172 int ret; 173 174 clk_enable(bank->clk); 175 176 ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset)); 177 178 clk_disable(bank->clk); 179 180 return ret; 181 } 182 183 static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 184 { 185 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 186 187 __stm32_gpio_set(bank, offset, value); 188 } 189 190 static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 191 { 192 return pinctrl_gpio_direction_input(chip->base + offset); 193 } 194 195 static int stm32_gpio_direction_output(struct gpio_chip *chip, 196 unsigned offset, int value) 197 { 198 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 199 200 __stm32_gpio_set(bank, offset, value); 201 pinctrl_gpio_direction_output(chip->base + offset); 202 203 return 0; 204 } 205 206 207 static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) 208 { 209 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 210 struct irq_fwspec fwspec; 211 212 fwspec.fwnode = bank->fwnode; 213 fwspec.param_count = 2; 214 fwspec.param[0] = offset; 215 fwspec.param[1] = IRQ_TYPE_NONE; 216 217 return irq_create_fwspec_mapping(&fwspec); 218 } 219 220 static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 221 { 222 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 223 int pin = stm32_gpio_pin(offset); 224 int ret; 225 u32 mode, alt; 226 227 stm32_pmx_get_mode(bank, pin, &mode, &alt); 228 if ((alt == 0) && (mode == 0)) 229 ret = 1; 230 else if ((alt == 0) && (mode == 1)) 231 ret = 0; 232 else 233 ret = -EINVAL; 234 235 return ret; 236 } 237 238 static const struct gpio_chip stm32_gpio_template = { 239 .request = stm32_gpio_request, 240 .free = stm32_gpio_free, 241 .get = stm32_gpio_get, 242 .set = stm32_gpio_set, 243 .direction_input = stm32_gpio_direction_input, 244 .direction_output = stm32_gpio_direction_output, 245 .to_irq = stm32_gpio_to_irq, 246 .get_direction = stm32_gpio_get_direction, 247 }; 248 249 static int stm32_gpio_irq_request_resources(struct irq_data *irq_data) 250 { 251 struct stm32_gpio_bank *bank = irq_data->domain->host_data; 252 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 253 int ret; 254 255 ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq); 256 if (ret) 257 return ret; 258 259 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq); 260 if (ret) { 261 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", 262 irq_data->hwirq); 263 return ret; 264 } 265 266 return 0; 267 } 268 269 static void stm32_gpio_irq_release_resources(struct irq_data *irq_data) 270 { 271 struct stm32_gpio_bank *bank = irq_data->domain->host_data; 272 273 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq); 274 } 275 276 static struct irq_chip stm32_gpio_irq_chip = { 277 .name = "stm32gpio", 278 .irq_eoi = irq_chip_eoi_parent, 279 .irq_ack = irq_chip_ack_parent, 280 .irq_mask = irq_chip_mask_parent, 281 .irq_unmask = irq_chip_unmask_parent, 282 .irq_set_type = irq_chip_set_type_parent, 283 .irq_set_wake = irq_chip_set_wake_parent, 284 .irq_request_resources = stm32_gpio_irq_request_resources, 285 .irq_release_resources = stm32_gpio_irq_release_resources, 286 }; 287 288 static int stm32_gpio_domain_translate(struct irq_domain *d, 289 struct irq_fwspec *fwspec, 290 unsigned long *hwirq, 291 unsigned int *type) 292 { 293 if ((fwspec->param_count != 2) || 294 (fwspec->param[0] >= STM32_GPIO_IRQ_LINE)) 295 return -EINVAL; 296 297 *hwirq = fwspec->param[0]; 298 *type = fwspec->param[1]; 299 return 0; 300 } 301 302 static int stm32_gpio_domain_activate(struct irq_domain *d, 303 struct irq_data *irq_data, bool reserve) 304 { 305 struct stm32_gpio_bank *bank = d->host_data; 306 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 307 308 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr); 309 return 0; 310 } 311 312 static int stm32_gpio_domain_alloc(struct irq_domain *d, 313 unsigned int virq, 314 unsigned int nr_irqs, void *data) 315 { 316 struct stm32_gpio_bank *bank = d->host_data; 317 struct irq_fwspec *fwspec = data; 318 struct irq_fwspec parent_fwspec; 319 irq_hw_number_t hwirq; 320 321 hwirq = fwspec->param[0]; 322 parent_fwspec.fwnode = d->parent->fwnode; 323 parent_fwspec.param_count = 2; 324 parent_fwspec.param[0] = fwspec->param[0]; 325 parent_fwspec.param[1] = fwspec->param[1]; 326 327 irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip, 328 bank); 329 330 return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec); 331 } 332 333 static const struct irq_domain_ops stm32_gpio_domain_ops = { 334 .translate = stm32_gpio_domain_translate, 335 .alloc = stm32_gpio_domain_alloc, 336 .free = irq_domain_free_irqs_common, 337 .activate = stm32_gpio_domain_activate, 338 }; 339 340 /* Pinctrl functions */ 341 static struct stm32_pinctrl_group * 342 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin) 343 { 344 int i; 345 346 for (i = 0; i < pctl->ngroups; i++) { 347 struct stm32_pinctrl_group *grp = pctl->groups + i; 348 349 if (grp->pin == pin) 350 return grp; 351 } 352 353 return NULL; 354 } 355 356 static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl, 357 u32 pin_num, u32 fnum) 358 { 359 int i; 360 361 for (i = 0; i < pctl->match_data->npins; i++) { 362 const struct stm32_desc_pin *pin = pctl->match_data->pins + i; 363 const struct stm32_desc_function *func = pin->functions; 364 365 if (pin->pin.number != pin_num) 366 continue; 367 368 while (func && func->name) { 369 if (func->num == fnum) 370 return true; 371 func++; 372 } 373 374 break; 375 } 376 377 return false; 378 } 379 380 static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl, 381 u32 pin, u32 fnum, struct stm32_pinctrl_group *grp, 382 struct pinctrl_map **map, unsigned *reserved_maps, 383 unsigned *num_maps) 384 { 385 if (*num_maps == *reserved_maps) 386 return -ENOSPC; 387 388 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; 389 (*map)[*num_maps].data.mux.group = grp->name; 390 391 if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) { 392 dev_err(pctl->dev, "invalid function %d on pin %d .\n", 393 fnum, pin); 394 return -EINVAL; 395 } 396 397 (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum]; 398 (*num_maps)++; 399 400 return 0; 401 } 402 403 static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, 404 struct device_node *node, 405 struct pinctrl_map **map, 406 unsigned *reserved_maps, 407 unsigned *num_maps) 408 { 409 struct stm32_pinctrl *pctl; 410 struct stm32_pinctrl_group *grp; 411 struct property *pins; 412 u32 pinfunc, pin, func; 413 unsigned long *configs; 414 unsigned int num_configs; 415 bool has_config = 0; 416 unsigned reserve = 0; 417 int num_pins, num_funcs, maps_per_pin, i, err; 418 419 pctl = pinctrl_dev_get_drvdata(pctldev); 420 421 pins = of_find_property(node, "pinmux", NULL); 422 if (!pins) { 423 dev_err(pctl->dev, "missing pins property in node %pOFn .\n", 424 node); 425 return -EINVAL; 426 } 427 428 err = pinconf_generic_parse_dt_config(node, pctldev, &configs, 429 &num_configs); 430 if (err) 431 return err; 432 433 if (num_configs) 434 has_config = 1; 435 436 num_pins = pins->length / sizeof(u32); 437 num_funcs = num_pins; 438 maps_per_pin = 0; 439 if (num_funcs) 440 maps_per_pin++; 441 if (has_config && num_pins >= 1) 442 maps_per_pin++; 443 444 if (!num_pins || !maps_per_pin) 445 return -EINVAL; 446 447 reserve = num_pins * maps_per_pin; 448 449 err = pinctrl_utils_reserve_map(pctldev, map, 450 reserved_maps, num_maps, reserve); 451 if (err) 452 return err; 453 454 for (i = 0; i < num_pins; i++) { 455 err = of_property_read_u32_index(node, "pinmux", 456 i, &pinfunc); 457 if (err) 458 return err; 459 460 pin = STM32_GET_PIN_NO(pinfunc); 461 func = STM32_GET_PIN_FUNC(pinfunc); 462 463 if (!stm32_pctrl_is_function_valid(pctl, pin, func)) { 464 dev_err(pctl->dev, "invalid function.\n"); 465 return -EINVAL; 466 } 467 468 grp = stm32_pctrl_find_group_by_pin(pctl, pin); 469 if (!grp) { 470 dev_err(pctl->dev, "unable to match pin %d to group\n", 471 pin); 472 return -EINVAL; 473 } 474 475 err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map, 476 reserved_maps, num_maps); 477 if (err) 478 return err; 479 480 if (has_config) { 481 err = pinctrl_utils_add_map_configs(pctldev, map, 482 reserved_maps, num_maps, grp->name, 483 configs, num_configs, 484 PIN_MAP_TYPE_CONFIGS_GROUP); 485 if (err) 486 return err; 487 } 488 } 489 490 return 0; 491 } 492 493 static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 494 struct device_node *np_config, 495 struct pinctrl_map **map, unsigned *num_maps) 496 { 497 struct device_node *np; 498 unsigned reserved_maps; 499 int ret; 500 501 *map = NULL; 502 *num_maps = 0; 503 reserved_maps = 0; 504 505 for_each_child_of_node(np_config, np) { 506 ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map, 507 &reserved_maps, num_maps); 508 if (ret < 0) { 509 pinctrl_utils_free_map(pctldev, *map, *num_maps); 510 return ret; 511 } 512 } 513 514 return 0; 515 } 516 517 static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev) 518 { 519 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 520 521 return pctl->ngroups; 522 } 523 524 static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev, 525 unsigned group) 526 { 527 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 528 529 return pctl->groups[group].name; 530 } 531 532 static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev, 533 unsigned group, 534 const unsigned **pins, 535 unsigned *num_pins) 536 { 537 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 538 539 *pins = (unsigned *)&pctl->groups[group].pin; 540 *num_pins = 1; 541 542 return 0; 543 } 544 545 static const struct pinctrl_ops stm32_pctrl_ops = { 546 .dt_node_to_map = stm32_pctrl_dt_node_to_map, 547 .dt_free_map = pinctrl_utils_free_map, 548 .get_groups_count = stm32_pctrl_get_groups_count, 549 .get_group_name = stm32_pctrl_get_group_name, 550 .get_group_pins = stm32_pctrl_get_group_pins, 551 }; 552 553 554 /* Pinmux functions */ 555 556 static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 557 { 558 return ARRAY_SIZE(stm32_gpio_functions); 559 } 560 561 static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev, 562 unsigned selector) 563 { 564 return stm32_gpio_functions[selector]; 565 } 566 567 static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev, 568 unsigned function, 569 const char * const **groups, 570 unsigned * const num_groups) 571 { 572 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 573 574 *groups = pctl->grp_names; 575 *num_groups = pctl->ngroups; 576 577 return 0; 578 } 579 580 static void stm32_pmx_set_mode(struct stm32_gpio_bank *bank, 581 int pin, u32 mode, u32 alt) 582 { 583 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 584 u32 val; 585 int alt_shift = (pin % 8) * 4; 586 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; 587 unsigned long flags; 588 int err = 0; 589 590 clk_enable(bank->clk); 591 spin_lock_irqsave(&bank->lock, flags); 592 593 if (pctl->hwlock) 594 err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT); 595 596 if (err) { 597 dev_err(pctl->dev, "Can't get hwspinlock\n"); 598 goto unlock; 599 } 600 601 val = readl_relaxed(bank->base + alt_offset); 602 val &= ~GENMASK(alt_shift + 3, alt_shift); 603 val |= (alt << alt_shift); 604 writel_relaxed(val, bank->base + alt_offset); 605 606 val = readl_relaxed(bank->base + STM32_GPIO_MODER); 607 val &= ~GENMASK(pin * 2 + 1, pin * 2); 608 val |= mode << (pin * 2); 609 writel_relaxed(val, bank->base + STM32_GPIO_MODER); 610 611 if (pctl->hwlock) 612 hwspin_unlock(pctl->hwlock); 613 614 unlock: 615 spin_unlock_irqrestore(&bank->lock, flags); 616 clk_disable(bank->clk); 617 } 618 619 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, 620 u32 *alt) 621 { 622 u32 val; 623 int alt_shift = (pin % 8) * 4; 624 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; 625 unsigned long flags; 626 627 clk_enable(bank->clk); 628 spin_lock_irqsave(&bank->lock, flags); 629 630 val = readl_relaxed(bank->base + alt_offset); 631 val &= GENMASK(alt_shift + 3, alt_shift); 632 *alt = val >> alt_shift; 633 634 val = readl_relaxed(bank->base + STM32_GPIO_MODER); 635 val &= GENMASK(pin * 2 + 1, pin * 2); 636 *mode = val >> (pin * 2); 637 638 spin_unlock_irqrestore(&bank->lock, flags); 639 clk_disable(bank->clk); 640 } 641 642 static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev, 643 unsigned function, 644 unsigned group) 645 { 646 bool ret; 647 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 648 struct stm32_pinctrl_group *g = pctl->groups + group; 649 struct pinctrl_gpio_range *range; 650 struct stm32_gpio_bank *bank; 651 u32 mode, alt; 652 int pin; 653 654 ret = stm32_pctrl_is_function_valid(pctl, g->pin, function); 655 if (!ret) { 656 dev_err(pctl->dev, "invalid function %d on group %d .\n", 657 function, group); 658 return -EINVAL; 659 } 660 661 range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin); 662 if (!range) { 663 dev_err(pctl->dev, "No gpio range defined.\n"); 664 return -EINVAL; 665 } 666 667 bank = gpiochip_get_data(range->gc); 668 pin = stm32_gpio_pin(g->pin); 669 670 mode = stm32_gpio_get_mode(function); 671 alt = stm32_gpio_get_alt(function); 672 673 stm32_pmx_set_mode(bank, pin, mode, alt); 674 675 return 0; 676 } 677 678 static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 679 struct pinctrl_gpio_range *range, unsigned gpio, 680 bool input) 681 { 682 struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc); 683 int pin = stm32_gpio_pin(gpio); 684 685 stm32_pmx_set_mode(bank, pin, !input, 0); 686 687 return 0; 688 } 689 690 static const struct pinmux_ops stm32_pmx_ops = { 691 .get_functions_count = stm32_pmx_get_funcs_cnt, 692 .get_function_name = stm32_pmx_get_func_name, 693 .get_function_groups = stm32_pmx_get_func_groups, 694 .set_mux = stm32_pmx_set_mux, 695 .gpio_set_direction = stm32_pmx_gpio_set_direction, 696 .strict = true, 697 }; 698 699 /* Pinconf functions */ 700 701 static void stm32_pconf_set_driving(struct stm32_gpio_bank *bank, 702 unsigned offset, u32 drive) 703 { 704 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 705 unsigned long flags; 706 u32 val; 707 int err = 0; 708 709 clk_enable(bank->clk); 710 spin_lock_irqsave(&bank->lock, flags); 711 712 if (pctl->hwlock) 713 err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT); 714 715 if (err) { 716 dev_err(pctl->dev, "Can't get hwspinlock\n"); 717 goto unlock; 718 } 719 720 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); 721 val &= ~BIT(offset); 722 val |= drive << offset; 723 writel_relaxed(val, bank->base + STM32_GPIO_TYPER); 724 725 if (pctl->hwlock) 726 hwspin_unlock(pctl->hwlock); 727 728 unlock: 729 spin_unlock_irqrestore(&bank->lock, flags); 730 clk_disable(bank->clk); 731 } 732 733 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank, 734 unsigned int offset) 735 { 736 unsigned long flags; 737 u32 val; 738 739 clk_enable(bank->clk); 740 spin_lock_irqsave(&bank->lock, flags); 741 742 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); 743 val &= BIT(offset); 744 745 spin_unlock_irqrestore(&bank->lock, flags); 746 clk_disable(bank->clk); 747 748 return (val >> offset); 749 } 750 751 static void stm32_pconf_set_speed(struct stm32_gpio_bank *bank, 752 unsigned offset, u32 speed) 753 { 754 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 755 unsigned long flags; 756 u32 val; 757 int err = 0; 758 759 clk_enable(bank->clk); 760 spin_lock_irqsave(&bank->lock, flags); 761 762 if (pctl->hwlock) 763 err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT); 764 765 if (err) { 766 dev_err(pctl->dev, "Can't get hwspinlock\n"); 767 goto unlock; 768 } 769 770 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); 771 val &= ~GENMASK(offset * 2 + 1, offset * 2); 772 val |= speed << (offset * 2); 773 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR); 774 775 if (pctl->hwlock) 776 hwspin_unlock(pctl->hwlock); 777 778 unlock: 779 spin_unlock_irqrestore(&bank->lock, flags); 780 clk_disable(bank->clk); 781 } 782 783 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank, 784 unsigned int offset) 785 { 786 unsigned long flags; 787 u32 val; 788 789 clk_enable(bank->clk); 790 spin_lock_irqsave(&bank->lock, flags); 791 792 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); 793 val &= GENMASK(offset * 2 + 1, offset * 2); 794 795 spin_unlock_irqrestore(&bank->lock, flags); 796 clk_disable(bank->clk); 797 798 return (val >> (offset * 2)); 799 } 800 801 static void stm32_pconf_set_bias(struct stm32_gpio_bank *bank, 802 unsigned offset, u32 bias) 803 { 804 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 805 unsigned long flags; 806 u32 val; 807 int err = 0; 808 809 clk_enable(bank->clk); 810 spin_lock_irqsave(&bank->lock, flags); 811 812 if (pctl->hwlock) 813 err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT); 814 815 if (err) { 816 dev_err(pctl->dev, "Can't get hwspinlock\n"); 817 goto unlock; 818 } 819 820 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); 821 val &= ~GENMASK(offset * 2 + 1, offset * 2); 822 val |= bias << (offset * 2); 823 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR); 824 825 if (pctl->hwlock) 826 hwspin_unlock(pctl->hwlock); 827 828 unlock: 829 spin_unlock_irqrestore(&bank->lock, flags); 830 clk_disable(bank->clk); 831 } 832 833 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank, 834 unsigned int offset) 835 { 836 unsigned long flags; 837 u32 val; 838 839 clk_enable(bank->clk); 840 spin_lock_irqsave(&bank->lock, flags); 841 842 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); 843 val &= GENMASK(offset * 2 + 1, offset * 2); 844 845 spin_unlock_irqrestore(&bank->lock, flags); 846 clk_disable(bank->clk); 847 848 return (val >> (offset * 2)); 849 } 850 851 static bool stm32_pconf_get(struct stm32_gpio_bank *bank, 852 unsigned int offset, bool dir) 853 { 854 unsigned long flags; 855 u32 val; 856 857 clk_enable(bank->clk); 858 spin_lock_irqsave(&bank->lock, flags); 859 860 if (dir) 861 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & 862 BIT(offset)); 863 else 864 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) & 865 BIT(offset)); 866 867 spin_unlock_irqrestore(&bank->lock, flags); 868 clk_disable(bank->clk); 869 870 return val; 871 } 872 873 static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev, 874 unsigned int pin, enum pin_config_param param, 875 enum pin_config_param arg) 876 { 877 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 878 struct pinctrl_gpio_range *range; 879 struct stm32_gpio_bank *bank; 880 int offset, ret = 0; 881 882 range = pinctrl_find_gpio_range_from_pin(pctldev, pin); 883 if (!range) { 884 dev_err(pctl->dev, "No gpio range defined.\n"); 885 return -EINVAL; 886 } 887 888 bank = gpiochip_get_data(range->gc); 889 offset = stm32_gpio_pin(pin); 890 891 switch (param) { 892 case PIN_CONFIG_DRIVE_PUSH_PULL: 893 stm32_pconf_set_driving(bank, offset, 0); 894 break; 895 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 896 stm32_pconf_set_driving(bank, offset, 1); 897 break; 898 case PIN_CONFIG_SLEW_RATE: 899 stm32_pconf_set_speed(bank, offset, arg); 900 break; 901 case PIN_CONFIG_BIAS_DISABLE: 902 stm32_pconf_set_bias(bank, offset, 0); 903 break; 904 case PIN_CONFIG_BIAS_PULL_UP: 905 stm32_pconf_set_bias(bank, offset, 1); 906 break; 907 case PIN_CONFIG_BIAS_PULL_DOWN: 908 stm32_pconf_set_bias(bank, offset, 2); 909 break; 910 case PIN_CONFIG_OUTPUT: 911 __stm32_gpio_set(bank, offset, arg); 912 ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false); 913 break; 914 default: 915 ret = -EINVAL; 916 } 917 918 return ret; 919 } 920 921 static int stm32_pconf_group_get(struct pinctrl_dev *pctldev, 922 unsigned group, 923 unsigned long *config) 924 { 925 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 926 927 *config = pctl->groups[group].config; 928 929 return 0; 930 } 931 932 static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, 933 unsigned long *configs, unsigned num_configs) 934 { 935 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 936 struct stm32_pinctrl_group *g = &pctl->groups[group]; 937 int i, ret; 938 939 for (i = 0; i < num_configs; i++) { 940 ret = stm32_pconf_parse_conf(pctldev, g->pin, 941 pinconf_to_config_param(configs[i]), 942 pinconf_to_config_argument(configs[i])); 943 if (ret < 0) 944 return ret; 945 946 g->config = configs[i]; 947 } 948 949 return 0; 950 } 951 952 static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev, 953 struct seq_file *s, 954 unsigned int pin) 955 { 956 struct pinctrl_gpio_range *range; 957 struct stm32_gpio_bank *bank; 958 int offset; 959 u32 mode, alt, drive, speed, bias; 960 static const char * const modes[] = { 961 "input", "output", "alternate", "analog" }; 962 static const char * const speeds[] = { 963 "low", "medium", "high", "very high" }; 964 static const char * const biasing[] = { 965 "floating", "pull up", "pull down", "" }; 966 bool val; 967 968 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); 969 if (!range) 970 return; 971 972 bank = gpiochip_get_data(range->gc); 973 offset = stm32_gpio_pin(pin); 974 975 stm32_pmx_get_mode(bank, offset, &mode, &alt); 976 bias = stm32_pconf_get_bias(bank, offset); 977 978 seq_printf(s, "%s ", modes[mode]); 979 980 switch (mode) { 981 /* input */ 982 case 0: 983 val = stm32_pconf_get(bank, offset, true); 984 seq_printf(s, "- %s - %s", 985 val ? "high" : "low", 986 biasing[bias]); 987 break; 988 989 /* output */ 990 case 1: 991 drive = stm32_pconf_get_driving(bank, offset); 992 speed = stm32_pconf_get_speed(bank, offset); 993 val = stm32_pconf_get(bank, offset, false); 994 seq_printf(s, "- %s - %s - %s - %s %s", 995 val ? "high" : "low", 996 drive ? "open drain" : "push pull", 997 biasing[bias], 998 speeds[speed], "speed"); 999 break; 1000 1001 /* alternate */ 1002 case 2: 1003 drive = stm32_pconf_get_driving(bank, offset); 1004 speed = stm32_pconf_get_speed(bank, offset); 1005 seq_printf(s, "%d - %s - %s - %s %s", alt, 1006 drive ? "open drain" : "push pull", 1007 biasing[bias], 1008 speeds[speed], "speed"); 1009 break; 1010 1011 /* analog */ 1012 case 3: 1013 break; 1014 } 1015 } 1016 1017 1018 static const struct pinconf_ops stm32_pconf_ops = { 1019 .pin_config_group_get = stm32_pconf_group_get, 1020 .pin_config_group_set = stm32_pconf_group_set, 1021 .pin_config_dbg_show = stm32_pconf_dbg_show, 1022 }; 1023 1024 static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, 1025 struct device_node *np) 1026 { 1027 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks]; 1028 int bank_ioport_nr; 1029 struct pinctrl_gpio_range *range = &bank->range; 1030 struct of_phandle_args args; 1031 struct device *dev = pctl->dev; 1032 struct resource res; 1033 struct reset_control *rstc; 1034 int npins = STM32_GPIO_PINS_PER_BANK; 1035 int bank_nr, err; 1036 1037 rstc = of_reset_control_get_exclusive(np, NULL); 1038 if (!IS_ERR(rstc)) 1039 reset_control_deassert(rstc); 1040 1041 if (of_address_to_resource(np, 0, &res)) 1042 return -ENODEV; 1043 1044 bank->base = devm_ioremap_resource(dev, &res); 1045 if (IS_ERR(bank->base)) 1046 return PTR_ERR(bank->base); 1047 1048 bank->clk = of_clk_get_by_name(np, NULL); 1049 if (IS_ERR(bank->clk)) { 1050 dev_err(dev, "failed to get clk (%ld)\n", PTR_ERR(bank->clk)); 1051 return PTR_ERR(bank->clk); 1052 } 1053 1054 err = clk_prepare(bank->clk); 1055 if (err) { 1056 dev_err(dev, "failed to prepare clk (%d)\n", err); 1057 return err; 1058 } 1059 1060 bank->gpio_chip = stm32_gpio_template; 1061 1062 of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label); 1063 1064 if (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args)) { 1065 bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK; 1066 bank->gpio_chip.base = args.args[1]; 1067 } else { 1068 bank_nr = pctl->nbanks; 1069 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; 1070 range->name = bank->gpio_chip.label; 1071 range->id = bank_nr; 1072 range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK; 1073 range->base = range->id * STM32_GPIO_PINS_PER_BANK; 1074 range->npins = npins; 1075 range->gc = &bank->gpio_chip; 1076 pinctrl_add_gpio_range(pctl->pctl_dev, 1077 &pctl->banks[bank_nr].range); 1078 } 1079 1080 if (of_property_read_u32(np, "st,bank-ioport", &bank_ioport_nr)) 1081 bank_ioport_nr = bank_nr; 1082 1083 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; 1084 1085 bank->gpio_chip.ngpio = npins; 1086 bank->gpio_chip.of_node = np; 1087 bank->gpio_chip.parent = dev; 1088 bank->bank_nr = bank_nr; 1089 bank->bank_ioport_nr = bank_ioport_nr; 1090 spin_lock_init(&bank->lock); 1091 1092 /* create irq hierarchical domain */ 1093 bank->fwnode = of_node_to_fwnode(np); 1094 1095 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, 1096 STM32_GPIO_IRQ_LINE, bank->fwnode, 1097 &stm32_gpio_domain_ops, bank); 1098 1099 if (!bank->domain) 1100 return -ENODEV; 1101 1102 err = gpiochip_add_data(&bank->gpio_chip, bank); 1103 if (err) { 1104 dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr); 1105 return err; 1106 } 1107 1108 dev_info(dev, "%s bank added\n", bank->gpio_chip.label); 1109 return 0; 1110 } 1111 1112 static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev, 1113 struct stm32_pinctrl *pctl) 1114 { 1115 struct device_node *np = pdev->dev.of_node, *parent; 1116 struct device *dev = &pdev->dev; 1117 struct regmap *rm; 1118 int offset, ret, i; 1119 int mask, mask_width; 1120 1121 parent = of_irq_find_parent(np); 1122 if (!parent) 1123 return -ENXIO; 1124 1125 pctl->domain = irq_find_host(parent); 1126 if (!pctl->domain) 1127 return -ENXIO; 1128 1129 pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); 1130 if (IS_ERR(pctl->regmap)) 1131 return PTR_ERR(pctl->regmap); 1132 1133 rm = pctl->regmap; 1134 1135 ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset); 1136 if (ret) 1137 return ret; 1138 1139 ret = of_property_read_u32_index(np, "st,syscfg", 2, &mask); 1140 if (ret) 1141 mask = SYSCFG_IRQMUX_MASK; 1142 1143 mask_width = fls(mask); 1144 1145 for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) { 1146 struct reg_field mux; 1147 1148 mux.reg = offset + (i / 4) * 4; 1149 mux.lsb = (i % 4) * mask_width; 1150 mux.msb = mux.lsb + mask_width - 1; 1151 1152 dev_dbg(dev, "irqmux%d: reg:%#x, lsb:%d, msb:%d\n", 1153 i, mux.reg, mux.lsb, mux.msb); 1154 1155 pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux); 1156 if (IS_ERR(pctl->irqmux[i])) 1157 return PTR_ERR(pctl->irqmux[i]); 1158 } 1159 1160 return 0; 1161 } 1162 1163 static int stm32_pctrl_build_state(struct platform_device *pdev) 1164 { 1165 struct stm32_pinctrl *pctl = platform_get_drvdata(pdev); 1166 int i; 1167 1168 pctl->ngroups = pctl->match_data->npins; 1169 1170 /* Allocate groups */ 1171 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups, 1172 sizeof(*pctl->groups), GFP_KERNEL); 1173 if (!pctl->groups) 1174 return -ENOMEM; 1175 1176 /* We assume that one pin is one group, use pin name as group name. */ 1177 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups, 1178 sizeof(*pctl->grp_names), GFP_KERNEL); 1179 if (!pctl->grp_names) 1180 return -ENOMEM; 1181 1182 for (i = 0; i < pctl->match_data->npins; i++) { 1183 const struct stm32_desc_pin *pin = pctl->match_data->pins + i; 1184 struct stm32_pinctrl_group *group = pctl->groups + i; 1185 1186 group->name = pin->pin.name; 1187 group->pin = pin->pin.number; 1188 1189 pctl->grp_names[i] = pin->pin.name; 1190 } 1191 1192 return 0; 1193 } 1194 1195 int stm32_pctl_probe(struct platform_device *pdev) 1196 { 1197 struct device_node *np = pdev->dev.of_node; 1198 struct device_node *child; 1199 const struct of_device_id *match; 1200 struct device *dev = &pdev->dev; 1201 struct stm32_pinctrl *pctl; 1202 struct pinctrl_pin_desc *pins; 1203 int i, ret, hwlock_id, banks = 0; 1204 1205 if (!np) 1206 return -EINVAL; 1207 1208 match = of_match_device(dev->driver->of_match_table, dev); 1209 if (!match || !match->data) 1210 return -EINVAL; 1211 1212 if (!of_find_property(np, "pins-are-numbered", NULL)) { 1213 dev_err(dev, "only support pins-are-numbered format\n"); 1214 return -EINVAL; 1215 } 1216 1217 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL); 1218 if (!pctl) 1219 return -ENOMEM; 1220 1221 platform_set_drvdata(pdev, pctl); 1222 1223 /* hwspinlock is optional */ 1224 hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0); 1225 if (hwlock_id < 0) { 1226 if (hwlock_id == -EPROBE_DEFER) 1227 return hwlock_id; 1228 } else { 1229 pctl->hwlock = hwspin_lock_request_specific(hwlock_id); 1230 } 1231 1232 pctl->dev = dev; 1233 pctl->match_data = match->data; 1234 ret = stm32_pctrl_build_state(pdev); 1235 if (ret) { 1236 dev_err(dev, "build state failed: %d\n", ret); 1237 return -EINVAL; 1238 } 1239 1240 if (of_find_property(np, "interrupt-parent", NULL)) { 1241 ret = stm32_pctrl_dt_setup_irq(pdev, pctl); 1242 if (ret) 1243 return ret; 1244 } 1245 1246 pins = devm_kcalloc(&pdev->dev, pctl->match_data->npins, sizeof(*pins), 1247 GFP_KERNEL); 1248 if (!pins) 1249 return -ENOMEM; 1250 1251 for (i = 0; i < pctl->match_data->npins; i++) 1252 pins[i] = pctl->match_data->pins[i].pin; 1253 1254 pctl->pctl_desc.name = dev_name(&pdev->dev); 1255 pctl->pctl_desc.owner = THIS_MODULE; 1256 pctl->pctl_desc.pins = pins; 1257 pctl->pctl_desc.npins = pctl->match_data->npins; 1258 pctl->pctl_desc.confops = &stm32_pconf_ops; 1259 pctl->pctl_desc.pctlops = &stm32_pctrl_ops; 1260 pctl->pctl_desc.pmxops = &stm32_pmx_ops; 1261 pctl->dev = &pdev->dev; 1262 1263 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc, 1264 pctl); 1265 1266 if (IS_ERR(pctl->pctl_dev)) { 1267 dev_err(&pdev->dev, "Failed pinctrl registration\n"); 1268 return PTR_ERR(pctl->pctl_dev); 1269 } 1270 1271 for_each_available_child_of_node(np, child) 1272 if (of_property_read_bool(child, "gpio-controller")) 1273 banks++; 1274 1275 if (!banks) { 1276 dev_err(dev, "at least one GPIO bank is required\n"); 1277 return -EINVAL; 1278 } 1279 pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks), 1280 GFP_KERNEL); 1281 if (!pctl->banks) 1282 return -ENOMEM; 1283 1284 for_each_available_child_of_node(np, child) { 1285 if (of_property_read_bool(child, "gpio-controller")) { 1286 ret = stm32_gpiolib_register_bank(pctl, child); 1287 if (ret) 1288 return ret; 1289 1290 pctl->nbanks++; 1291 } 1292 } 1293 1294 dev_info(dev, "Pinctrl STM32 initialized\n"); 1295 1296 return 0; 1297 } 1298 1299