1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics 2017 5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 * 7 * Heavily based on Mediatek's pinctrl driver 8 */ 9 #include <linux/clk.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/io.h> 12 #include <linux/irq.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 #include <linux/of_device.h> 18 #include <linux/of_irq.h> 19 #include <linux/pinctrl/consumer.h> 20 #include <linux/pinctrl/machine.h> 21 #include <linux/pinctrl/pinconf.h> 22 #include <linux/pinctrl/pinconf-generic.h> 23 #include <linux/pinctrl/pinctrl.h> 24 #include <linux/pinctrl/pinmux.h> 25 #include <linux/platform_device.h> 26 #include <linux/regmap.h> 27 #include <linux/reset.h> 28 #include <linux/slab.h> 29 30 #include "../core.h" 31 #include "../pinconf.h" 32 #include "../pinctrl-utils.h" 33 #include "pinctrl-stm32.h" 34 35 #define STM32_GPIO_MODER 0x00 36 #define STM32_GPIO_TYPER 0x04 37 #define STM32_GPIO_SPEEDR 0x08 38 #define STM32_GPIO_PUPDR 0x0c 39 #define STM32_GPIO_IDR 0x10 40 #define STM32_GPIO_ODR 0x14 41 #define STM32_GPIO_BSRR 0x18 42 #define STM32_GPIO_LCKR 0x1c 43 #define STM32_GPIO_AFRL 0x20 44 #define STM32_GPIO_AFRH 0x24 45 46 #define STM32_GPIO_PINS_PER_BANK 16 47 #define STM32_GPIO_IRQ_LINE 16 48 49 #define SYSCFG_IRQMUX_MASK GENMASK(3, 0) 50 51 #define gpio_range_to_bank(chip) \ 52 container_of(chip, struct stm32_gpio_bank, range) 53 54 static const char * const stm32_gpio_functions[] = { 55 "gpio", "af0", "af1", 56 "af2", "af3", "af4", 57 "af5", "af6", "af7", 58 "af8", "af9", "af10", 59 "af11", "af12", "af13", 60 "af14", "af15", "analog", 61 }; 62 63 struct stm32_pinctrl_group { 64 const char *name; 65 unsigned long config; 66 unsigned pin; 67 }; 68 69 struct stm32_gpio_bank { 70 void __iomem *base; 71 struct clk *clk; 72 spinlock_t lock; 73 struct gpio_chip gpio_chip; 74 struct pinctrl_gpio_range range; 75 struct fwnode_handle *fwnode; 76 struct irq_domain *domain; 77 u32 bank_nr; 78 u32 bank_ioport_nr; 79 }; 80 81 struct stm32_pinctrl { 82 struct device *dev; 83 struct pinctrl_dev *pctl_dev; 84 struct pinctrl_desc pctl_desc; 85 struct stm32_pinctrl_group *groups; 86 unsigned ngroups; 87 const char **grp_names; 88 struct stm32_gpio_bank *banks; 89 unsigned nbanks; 90 const struct stm32_pinctrl_match_data *match_data; 91 struct irq_domain *domain; 92 struct regmap *regmap; 93 struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK]; 94 }; 95 96 static inline int stm32_gpio_pin(int gpio) 97 { 98 return gpio % STM32_GPIO_PINS_PER_BANK; 99 } 100 101 static inline u32 stm32_gpio_get_mode(u32 function) 102 { 103 switch (function) { 104 case STM32_PIN_GPIO: 105 return 0; 106 case STM32_PIN_AF(0) ... STM32_PIN_AF(15): 107 return 2; 108 case STM32_PIN_ANALOG: 109 return 3; 110 } 111 112 return 0; 113 } 114 115 static inline u32 stm32_gpio_get_alt(u32 function) 116 { 117 switch (function) { 118 case STM32_PIN_GPIO: 119 return 0; 120 case STM32_PIN_AF(0) ... STM32_PIN_AF(15): 121 return function - 1; 122 case STM32_PIN_ANALOG: 123 return 0; 124 } 125 126 return 0; 127 } 128 129 /* GPIO functions */ 130 131 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank, 132 unsigned offset, int value) 133 { 134 if (!value) 135 offset += STM32_GPIO_PINS_PER_BANK; 136 137 clk_enable(bank->clk); 138 139 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR); 140 141 clk_disable(bank->clk); 142 } 143 144 static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset) 145 { 146 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 147 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 148 struct pinctrl_gpio_range *range; 149 int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK); 150 151 range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin); 152 if (!range) { 153 dev_err(pctl->dev, "pin %d not in range.\n", pin); 154 return -EINVAL; 155 } 156 157 return pinctrl_gpio_request(chip->base + offset); 158 } 159 160 static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset) 161 { 162 pinctrl_gpio_free(chip->base + offset); 163 } 164 165 static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset) 166 { 167 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 168 int ret; 169 170 clk_enable(bank->clk); 171 172 ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset)); 173 174 clk_disable(bank->clk); 175 176 return ret; 177 } 178 179 static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 180 { 181 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 182 183 __stm32_gpio_set(bank, offset, value); 184 } 185 186 static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 187 { 188 return pinctrl_gpio_direction_input(chip->base + offset); 189 } 190 191 static int stm32_gpio_direction_output(struct gpio_chip *chip, 192 unsigned offset, int value) 193 { 194 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 195 196 __stm32_gpio_set(bank, offset, value); 197 pinctrl_gpio_direction_output(chip->base + offset); 198 199 return 0; 200 } 201 202 203 static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) 204 { 205 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 206 struct irq_fwspec fwspec; 207 208 fwspec.fwnode = bank->fwnode; 209 fwspec.param_count = 2; 210 fwspec.param[0] = offset; 211 fwspec.param[1] = IRQ_TYPE_NONE; 212 213 return irq_create_fwspec_mapping(&fwspec); 214 } 215 216 static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 217 { 218 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 219 int pin = stm32_gpio_pin(offset); 220 int ret; 221 u32 mode, alt; 222 223 stm32_pmx_get_mode(bank, pin, &mode, &alt); 224 if ((alt == 0) && (mode == 0)) 225 ret = 1; 226 else if ((alt == 0) && (mode == 1)) 227 ret = 0; 228 else 229 ret = -EINVAL; 230 231 return ret; 232 } 233 234 static const struct gpio_chip stm32_gpio_template = { 235 .request = stm32_gpio_request, 236 .free = stm32_gpio_free, 237 .get = stm32_gpio_get, 238 .set = stm32_gpio_set, 239 .direction_input = stm32_gpio_direction_input, 240 .direction_output = stm32_gpio_direction_output, 241 .to_irq = stm32_gpio_to_irq, 242 .get_direction = stm32_gpio_get_direction, 243 }; 244 245 static int stm32_gpio_irq_request_resources(struct irq_data *irq_data) 246 { 247 struct stm32_gpio_bank *bank = irq_data->domain->host_data; 248 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 249 int ret; 250 251 ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq); 252 if (ret) 253 return ret; 254 255 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq); 256 if (ret) { 257 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", 258 irq_data->hwirq); 259 return ret; 260 } 261 262 return 0; 263 } 264 265 static void stm32_gpio_irq_release_resources(struct irq_data *irq_data) 266 { 267 struct stm32_gpio_bank *bank = irq_data->domain->host_data; 268 269 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq); 270 } 271 272 static struct irq_chip stm32_gpio_irq_chip = { 273 .name = "stm32gpio", 274 .irq_eoi = irq_chip_eoi_parent, 275 .irq_ack = irq_chip_ack_parent, 276 .irq_mask = irq_chip_mask_parent, 277 .irq_unmask = irq_chip_unmask_parent, 278 .irq_set_type = irq_chip_set_type_parent, 279 .irq_set_wake = irq_chip_set_wake_parent, 280 .irq_request_resources = stm32_gpio_irq_request_resources, 281 .irq_release_resources = stm32_gpio_irq_release_resources, 282 }; 283 284 static int stm32_gpio_domain_translate(struct irq_domain *d, 285 struct irq_fwspec *fwspec, 286 unsigned long *hwirq, 287 unsigned int *type) 288 { 289 if ((fwspec->param_count != 2) || 290 (fwspec->param[0] >= STM32_GPIO_IRQ_LINE)) 291 return -EINVAL; 292 293 *hwirq = fwspec->param[0]; 294 *type = fwspec->param[1]; 295 return 0; 296 } 297 298 static int stm32_gpio_domain_activate(struct irq_domain *d, 299 struct irq_data *irq_data, bool reserve) 300 { 301 struct stm32_gpio_bank *bank = d->host_data; 302 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 303 304 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr); 305 return 0; 306 } 307 308 static int stm32_gpio_domain_alloc(struct irq_domain *d, 309 unsigned int virq, 310 unsigned int nr_irqs, void *data) 311 { 312 struct stm32_gpio_bank *bank = d->host_data; 313 struct irq_fwspec *fwspec = data; 314 struct irq_fwspec parent_fwspec; 315 irq_hw_number_t hwirq; 316 317 hwirq = fwspec->param[0]; 318 parent_fwspec.fwnode = d->parent->fwnode; 319 parent_fwspec.param_count = 2; 320 parent_fwspec.param[0] = fwspec->param[0]; 321 parent_fwspec.param[1] = fwspec->param[1]; 322 323 irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip, 324 bank); 325 326 return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec); 327 } 328 329 static const struct irq_domain_ops stm32_gpio_domain_ops = { 330 .translate = stm32_gpio_domain_translate, 331 .alloc = stm32_gpio_domain_alloc, 332 .free = irq_domain_free_irqs_common, 333 .activate = stm32_gpio_domain_activate, 334 }; 335 336 /* Pinctrl functions */ 337 static struct stm32_pinctrl_group * 338 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin) 339 { 340 int i; 341 342 for (i = 0; i < pctl->ngroups; i++) { 343 struct stm32_pinctrl_group *grp = pctl->groups + i; 344 345 if (grp->pin == pin) 346 return grp; 347 } 348 349 return NULL; 350 } 351 352 static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl, 353 u32 pin_num, u32 fnum) 354 { 355 int i; 356 357 for (i = 0; i < pctl->match_data->npins; i++) { 358 const struct stm32_desc_pin *pin = pctl->match_data->pins + i; 359 const struct stm32_desc_function *func = pin->functions; 360 361 if (pin->pin.number != pin_num) 362 continue; 363 364 while (func && func->name) { 365 if (func->num == fnum) 366 return true; 367 func++; 368 } 369 370 break; 371 } 372 373 return false; 374 } 375 376 static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl, 377 u32 pin, u32 fnum, struct stm32_pinctrl_group *grp, 378 struct pinctrl_map **map, unsigned *reserved_maps, 379 unsigned *num_maps) 380 { 381 if (*num_maps == *reserved_maps) 382 return -ENOSPC; 383 384 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; 385 (*map)[*num_maps].data.mux.group = grp->name; 386 387 if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) { 388 dev_err(pctl->dev, "invalid function %d on pin %d .\n", 389 fnum, pin); 390 return -EINVAL; 391 } 392 393 (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum]; 394 (*num_maps)++; 395 396 return 0; 397 } 398 399 static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, 400 struct device_node *node, 401 struct pinctrl_map **map, 402 unsigned *reserved_maps, 403 unsigned *num_maps) 404 { 405 struct stm32_pinctrl *pctl; 406 struct stm32_pinctrl_group *grp; 407 struct property *pins; 408 u32 pinfunc, pin, func; 409 unsigned long *configs; 410 unsigned int num_configs; 411 bool has_config = 0; 412 unsigned reserve = 0; 413 int num_pins, num_funcs, maps_per_pin, i, err; 414 415 pctl = pinctrl_dev_get_drvdata(pctldev); 416 417 pins = of_find_property(node, "pinmux", NULL); 418 if (!pins) { 419 dev_err(pctl->dev, "missing pins property in node %pOFn .\n", 420 node); 421 return -EINVAL; 422 } 423 424 err = pinconf_generic_parse_dt_config(node, pctldev, &configs, 425 &num_configs); 426 if (err) 427 return err; 428 429 if (num_configs) 430 has_config = 1; 431 432 num_pins = pins->length / sizeof(u32); 433 num_funcs = num_pins; 434 maps_per_pin = 0; 435 if (num_funcs) 436 maps_per_pin++; 437 if (has_config && num_pins >= 1) 438 maps_per_pin++; 439 440 if (!num_pins || !maps_per_pin) 441 return -EINVAL; 442 443 reserve = num_pins * maps_per_pin; 444 445 err = pinctrl_utils_reserve_map(pctldev, map, 446 reserved_maps, num_maps, reserve); 447 if (err) 448 return err; 449 450 for (i = 0; i < num_pins; i++) { 451 err = of_property_read_u32_index(node, "pinmux", 452 i, &pinfunc); 453 if (err) 454 return err; 455 456 pin = STM32_GET_PIN_NO(pinfunc); 457 func = STM32_GET_PIN_FUNC(pinfunc); 458 459 if (!stm32_pctrl_is_function_valid(pctl, pin, func)) { 460 dev_err(pctl->dev, "invalid function.\n"); 461 return -EINVAL; 462 } 463 464 grp = stm32_pctrl_find_group_by_pin(pctl, pin); 465 if (!grp) { 466 dev_err(pctl->dev, "unable to match pin %d to group\n", 467 pin); 468 return -EINVAL; 469 } 470 471 err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map, 472 reserved_maps, num_maps); 473 if (err) 474 return err; 475 476 if (has_config) { 477 err = pinctrl_utils_add_map_configs(pctldev, map, 478 reserved_maps, num_maps, grp->name, 479 configs, num_configs, 480 PIN_MAP_TYPE_CONFIGS_GROUP); 481 if (err) 482 return err; 483 } 484 } 485 486 return 0; 487 } 488 489 static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 490 struct device_node *np_config, 491 struct pinctrl_map **map, unsigned *num_maps) 492 { 493 struct device_node *np; 494 unsigned reserved_maps; 495 int ret; 496 497 *map = NULL; 498 *num_maps = 0; 499 reserved_maps = 0; 500 501 for_each_child_of_node(np_config, np) { 502 ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map, 503 &reserved_maps, num_maps); 504 if (ret < 0) { 505 pinctrl_utils_free_map(pctldev, *map, *num_maps); 506 return ret; 507 } 508 } 509 510 return 0; 511 } 512 513 static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev) 514 { 515 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 516 517 return pctl->ngroups; 518 } 519 520 static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev, 521 unsigned group) 522 { 523 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 524 525 return pctl->groups[group].name; 526 } 527 528 static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev, 529 unsigned group, 530 const unsigned **pins, 531 unsigned *num_pins) 532 { 533 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 534 535 *pins = (unsigned *)&pctl->groups[group].pin; 536 *num_pins = 1; 537 538 return 0; 539 } 540 541 static const struct pinctrl_ops stm32_pctrl_ops = { 542 .dt_node_to_map = stm32_pctrl_dt_node_to_map, 543 .dt_free_map = pinctrl_utils_free_map, 544 .get_groups_count = stm32_pctrl_get_groups_count, 545 .get_group_name = stm32_pctrl_get_group_name, 546 .get_group_pins = stm32_pctrl_get_group_pins, 547 }; 548 549 550 /* Pinmux functions */ 551 552 static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 553 { 554 return ARRAY_SIZE(stm32_gpio_functions); 555 } 556 557 static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev, 558 unsigned selector) 559 { 560 return stm32_gpio_functions[selector]; 561 } 562 563 static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev, 564 unsigned function, 565 const char * const **groups, 566 unsigned * const num_groups) 567 { 568 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 569 570 *groups = pctl->grp_names; 571 *num_groups = pctl->ngroups; 572 573 return 0; 574 } 575 576 static void stm32_pmx_set_mode(struct stm32_gpio_bank *bank, 577 int pin, u32 mode, u32 alt) 578 { 579 u32 val; 580 int alt_shift = (pin % 8) * 4; 581 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; 582 unsigned long flags; 583 584 clk_enable(bank->clk); 585 spin_lock_irqsave(&bank->lock, flags); 586 587 val = readl_relaxed(bank->base + alt_offset); 588 val &= ~GENMASK(alt_shift + 3, alt_shift); 589 val |= (alt << alt_shift); 590 writel_relaxed(val, bank->base + alt_offset); 591 592 val = readl_relaxed(bank->base + STM32_GPIO_MODER); 593 val &= ~GENMASK(pin * 2 + 1, pin * 2); 594 val |= mode << (pin * 2); 595 writel_relaxed(val, bank->base + STM32_GPIO_MODER); 596 597 spin_unlock_irqrestore(&bank->lock, flags); 598 clk_disable(bank->clk); 599 } 600 601 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, 602 u32 *alt) 603 { 604 u32 val; 605 int alt_shift = (pin % 8) * 4; 606 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; 607 unsigned long flags; 608 609 clk_enable(bank->clk); 610 spin_lock_irqsave(&bank->lock, flags); 611 612 val = readl_relaxed(bank->base + alt_offset); 613 val &= GENMASK(alt_shift + 3, alt_shift); 614 *alt = val >> alt_shift; 615 616 val = readl_relaxed(bank->base + STM32_GPIO_MODER); 617 val &= GENMASK(pin * 2 + 1, pin * 2); 618 *mode = val >> (pin * 2); 619 620 spin_unlock_irqrestore(&bank->lock, flags); 621 clk_disable(bank->clk); 622 } 623 624 static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev, 625 unsigned function, 626 unsigned group) 627 { 628 bool ret; 629 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 630 struct stm32_pinctrl_group *g = pctl->groups + group; 631 struct pinctrl_gpio_range *range; 632 struct stm32_gpio_bank *bank; 633 u32 mode, alt; 634 int pin; 635 636 ret = stm32_pctrl_is_function_valid(pctl, g->pin, function); 637 if (!ret) { 638 dev_err(pctl->dev, "invalid function %d on group %d .\n", 639 function, group); 640 return -EINVAL; 641 } 642 643 range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin); 644 if (!range) { 645 dev_err(pctl->dev, "No gpio range defined.\n"); 646 return -EINVAL; 647 } 648 649 bank = gpiochip_get_data(range->gc); 650 pin = stm32_gpio_pin(g->pin); 651 652 mode = stm32_gpio_get_mode(function); 653 alt = stm32_gpio_get_alt(function); 654 655 stm32_pmx_set_mode(bank, pin, mode, alt); 656 657 return 0; 658 } 659 660 static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 661 struct pinctrl_gpio_range *range, unsigned gpio, 662 bool input) 663 { 664 struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc); 665 int pin = stm32_gpio_pin(gpio); 666 667 stm32_pmx_set_mode(bank, pin, !input, 0); 668 669 return 0; 670 } 671 672 static const struct pinmux_ops stm32_pmx_ops = { 673 .get_functions_count = stm32_pmx_get_funcs_cnt, 674 .get_function_name = stm32_pmx_get_func_name, 675 .get_function_groups = stm32_pmx_get_func_groups, 676 .set_mux = stm32_pmx_set_mux, 677 .gpio_set_direction = stm32_pmx_gpio_set_direction, 678 .strict = true, 679 }; 680 681 /* Pinconf functions */ 682 683 static void stm32_pconf_set_driving(struct stm32_gpio_bank *bank, 684 unsigned offset, u32 drive) 685 { 686 unsigned long flags; 687 u32 val; 688 689 clk_enable(bank->clk); 690 spin_lock_irqsave(&bank->lock, flags); 691 692 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); 693 val &= ~BIT(offset); 694 val |= drive << offset; 695 writel_relaxed(val, bank->base + STM32_GPIO_TYPER); 696 697 spin_unlock_irqrestore(&bank->lock, flags); 698 clk_disable(bank->clk); 699 } 700 701 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank, 702 unsigned int offset) 703 { 704 unsigned long flags; 705 u32 val; 706 707 clk_enable(bank->clk); 708 spin_lock_irqsave(&bank->lock, flags); 709 710 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); 711 val &= BIT(offset); 712 713 spin_unlock_irqrestore(&bank->lock, flags); 714 clk_disable(bank->clk); 715 716 return (val >> offset); 717 } 718 719 static void stm32_pconf_set_speed(struct stm32_gpio_bank *bank, 720 unsigned offset, u32 speed) 721 { 722 unsigned long flags; 723 u32 val; 724 725 clk_enable(bank->clk); 726 spin_lock_irqsave(&bank->lock, flags); 727 728 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); 729 val &= ~GENMASK(offset * 2 + 1, offset * 2); 730 val |= speed << (offset * 2); 731 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR); 732 733 spin_unlock_irqrestore(&bank->lock, flags); 734 clk_disable(bank->clk); 735 } 736 737 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank, 738 unsigned int offset) 739 { 740 unsigned long flags; 741 u32 val; 742 743 clk_enable(bank->clk); 744 spin_lock_irqsave(&bank->lock, flags); 745 746 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); 747 val &= GENMASK(offset * 2 + 1, offset * 2); 748 749 spin_unlock_irqrestore(&bank->lock, flags); 750 clk_disable(bank->clk); 751 752 return (val >> (offset * 2)); 753 } 754 755 static void stm32_pconf_set_bias(struct stm32_gpio_bank *bank, 756 unsigned offset, u32 bias) 757 { 758 unsigned long flags; 759 u32 val; 760 761 clk_enable(bank->clk); 762 spin_lock_irqsave(&bank->lock, flags); 763 764 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); 765 val &= ~GENMASK(offset * 2 + 1, offset * 2); 766 val |= bias << (offset * 2); 767 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR); 768 769 spin_unlock_irqrestore(&bank->lock, flags); 770 clk_disable(bank->clk); 771 } 772 773 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank, 774 unsigned int offset) 775 { 776 unsigned long flags; 777 u32 val; 778 779 clk_enable(bank->clk); 780 spin_lock_irqsave(&bank->lock, flags); 781 782 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); 783 val &= GENMASK(offset * 2 + 1, offset * 2); 784 785 spin_unlock_irqrestore(&bank->lock, flags); 786 clk_disable(bank->clk); 787 788 return (val >> (offset * 2)); 789 } 790 791 static bool stm32_pconf_get(struct stm32_gpio_bank *bank, 792 unsigned int offset, bool dir) 793 { 794 unsigned long flags; 795 u32 val; 796 797 clk_enable(bank->clk); 798 spin_lock_irqsave(&bank->lock, flags); 799 800 if (dir) 801 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & 802 BIT(offset)); 803 else 804 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) & 805 BIT(offset)); 806 807 spin_unlock_irqrestore(&bank->lock, flags); 808 clk_disable(bank->clk); 809 810 return val; 811 } 812 813 static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev, 814 unsigned int pin, enum pin_config_param param, 815 enum pin_config_param arg) 816 { 817 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 818 struct pinctrl_gpio_range *range; 819 struct stm32_gpio_bank *bank; 820 int offset, ret = 0; 821 822 range = pinctrl_find_gpio_range_from_pin(pctldev, pin); 823 if (!range) { 824 dev_err(pctl->dev, "No gpio range defined.\n"); 825 return -EINVAL; 826 } 827 828 bank = gpiochip_get_data(range->gc); 829 offset = stm32_gpio_pin(pin); 830 831 switch (param) { 832 case PIN_CONFIG_DRIVE_PUSH_PULL: 833 stm32_pconf_set_driving(bank, offset, 0); 834 break; 835 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 836 stm32_pconf_set_driving(bank, offset, 1); 837 break; 838 case PIN_CONFIG_SLEW_RATE: 839 stm32_pconf_set_speed(bank, offset, arg); 840 break; 841 case PIN_CONFIG_BIAS_DISABLE: 842 stm32_pconf_set_bias(bank, offset, 0); 843 break; 844 case PIN_CONFIG_BIAS_PULL_UP: 845 stm32_pconf_set_bias(bank, offset, 1); 846 break; 847 case PIN_CONFIG_BIAS_PULL_DOWN: 848 stm32_pconf_set_bias(bank, offset, 2); 849 break; 850 case PIN_CONFIG_OUTPUT: 851 __stm32_gpio_set(bank, offset, arg); 852 ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false); 853 break; 854 default: 855 ret = -EINVAL; 856 } 857 858 return ret; 859 } 860 861 static int stm32_pconf_group_get(struct pinctrl_dev *pctldev, 862 unsigned group, 863 unsigned long *config) 864 { 865 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 866 867 *config = pctl->groups[group].config; 868 869 return 0; 870 } 871 872 static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, 873 unsigned long *configs, unsigned num_configs) 874 { 875 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 876 struct stm32_pinctrl_group *g = &pctl->groups[group]; 877 int i, ret; 878 879 for (i = 0; i < num_configs; i++) { 880 ret = stm32_pconf_parse_conf(pctldev, g->pin, 881 pinconf_to_config_param(configs[i]), 882 pinconf_to_config_argument(configs[i])); 883 if (ret < 0) 884 return ret; 885 886 g->config = configs[i]; 887 } 888 889 return 0; 890 } 891 892 static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev, 893 struct seq_file *s, 894 unsigned int pin) 895 { 896 struct pinctrl_gpio_range *range; 897 struct stm32_gpio_bank *bank; 898 int offset; 899 u32 mode, alt, drive, speed, bias; 900 static const char * const modes[] = { 901 "input", "output", "alternate", "analog" }; 902 static const char * const speeds[] = { 903 "low", "medium", "high", "very high" }; 904 static const char * const biasing[] = { 905 "floating", "pull up", "pull down", "" }; 906 bool val; 907 908 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); 909 if (!range) 910 return; 911 912 bank = gpiochip_get_data(range->gc); 913 offset = stm32_gpio_pin(pin); 914 915 stm32_pmx_get_mode(bank, offset, &mode, &alt); 916 bias = stm32_pconf_get_bias(bank, offset); 917 918 seq_printf(s, "%s ", modes[mode]); 919 920 switch (mode) { 921 /* input */ 922 case 0: 923 val = stm32_pconf_get(bank, offset, true); 924 seq_printf(s, "- %s - %s", 925 val ? "high" : "low", 926 biasing[bias]); 927 break; 928 929 /* output */ 930 case 1: 931 drive = stm32_pconf_get_driving(bank, offset); 932 speed = stm32_pconf_get_speed(bank, offset); 933 val = stm32_pconf_get(bank, offset, false); 934 seq_printf(s, "- %s - %s - %s - %s %s", 935 val ? "high" : "low", 936 drive ? "open drain" : "push pull", 937 biasing[bias], 938 speeds[speed], "speed"); 939 break; 940 941 /* alternate */ 942 case 2: 943 drive = stm32_pconf_get_driving(bank, offset); 944 speed = stm32_pconf_get_speed(bank, offset); 945 seq_printf(s, "%d - %s - %s - %s %s", alt, 946 drive ? "open drain" : "push pull", 947 biasing[bias], 948 speeds[speed], "speed"); 949 break; 950 951 /* analog */ 952 case 3: 953 break; 954 } 955 } 956 957 958 static const struct pinconf_ops stm32_pconf_ops = { 959 .pin_config_group_get = stm32_pconf_group_get, 960 .pin_config_group_set = stm32_pconf_group_set, 961 .pin_config_dbg_show = stm32_pconf_dbg_show, 962 }; 963 964 static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, 965 struct device_node *np) 966 { 967 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks]; 968 int bank_ioport_nr; 969 struct pinctrl_gpio_range *range = &bank->range; 970 struct of_phandle_args args; 971 struct device *dev = pctl->dev; 972 struct resource res; 973 struct reset_control *rstc; 974 int npins = STM32_GPIO_PINS_PER_BANK; 975 int bank_nr, err; 976 977 rstc = of_reset_control_get_exclusive(np, NULL); 978 if (!IS_ERR(rstc)) 979 reset_control_deassert(rstc); 980 981 if (of_address_to_resource(np, 0, &res)) 982 return -ENODEV; 983 984 bank->base = devm_ioremap_resource(dev, &res); 985 if (IS_ERR(bank->base)) 986 return PTR_ERR(bank->base); 987 988 bank->clk = of_clk_get_by_name(np, NULL); 989 if (IS_ERR(bank->clk)) { 990 dev_err(dev, "failed to get clk (%ld)\n", PTR_ERR(bank->clk)); 991 return PTR_ERR(bank->clk); 992 } 993 994 err = clk_prepare(bank->clk); 995 if (err) { 996 dev_err(dev, "failed to prepare clk (%d)\n", err); 997 return err; 998 } 999 1000 bank->gpio_chip = stm32_gpio_template; 1001 1002 of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label); 1003 1004 if (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args)) { 1005 bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK; 1006 bank->gpio_chip.base = args.args[1]; 1007 } else { 1008 bank_nr = pctl->nbanks; 1009 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; 1010 range->name = bank->gpio_chip.label; 1011 range->id = bank_nr; 1012 range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK; 1013 range->base = range->id * STM32_GPIO_PINS_PER_BANK; 1014 range->npins = npins; 1015 range->gc = &bank->gpio_chip; 1016 pinctrl_add_gpio_range(pctl->pctl_dev, 1017 &pctl->banks[bank_nr].range); 1018 } 1019 1020 if (of_property_read_u32(np, "st,bank-ioport", &bank_ioport_nr)) 1021 bank_ioport_nr = bank_nr; 1022 1023 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; 1024 1025 bank->gpio_chip.ngpio = npins; 1026 bank->gpio_chip.of_node = np; 1027 bank->gpio_chip.parent = dev; 1028 bank->bank_nr = bank_nr; 1029 bank->bank_ioport_nr = bank_ioport_nr; 1030 spin_lock_init(&bank->lock); 1031 1032 /* create irq hierarchical domain */ 1033 bank->fwnode = of_node_to_fwnode(np); 1034 1035 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, 1036 STM32_GPIO_IRQ_LINE, bank->fwnode, 1037 &stm32_gpio_domain_ops, bank); 1038 1039 if (!bank->domain) 1040 return -ENODEV; 1041 1042 err = gpiochip_add_data(&bank->gpio_chip, bank); 1043 if (err) { 1044 dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr); 1045 return err; 1046 } 1047 1048 dev_info(dev, "%s bank added\n", bank->gpio_chip.label); 1049 return 0; 1050 } 1051 1052 static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev, 1053 struct stm32_pinctrl *pctl) 1054 { 1055 struct device_node *np = pdev->dev.of_node, *parent; 1056 struct device *dev = &pdev->dev; 1057 struct regmap *rm; 1058 int offset, ret, i; 1059 int mask, mask_width; 1060 1061 parent = of_irq_find_parent(np); 1062 if (!parent) 1063 return -ENXIO; 1064 1065 pctl->domain = irq_find_host(parent); 1066 if (!pctl->domain) 1067 return -ENXIO; 1068 1069 pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); 1070 if (IS_ERR(pctl->regmap)) 1071 return PTR_ERR(pctl->regmap); 1072 1073 rm = pctl->regmap; 1074 1075 ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset); 1076 if (ret) 1077 return ret; 1078 1079 ret = of_property_read_u32_index(np, "st,syscfg", 2, &mask); 1080 if (ret) 1081 mask = SYSCFG_IRQMUX_MASK; 1082 1083 mask_width = fls(mask); 1084 1085 for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) { 1086 struct reg_field mux; 1087 1088 mux.reg = offset + (i / 4) * 4; 1089 mux.lsb = (i % 4) * mask_width; 1090 mux.msb = mux.lsb + mask_width - 1; 1091 1092 dev_dbg(dev, "irqmux%d: reg:%#x, lsb:%d, msb:%d\n", 1093 i, mux.reg, mux.lsb, mux.msb); 1094 1095 pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux); 1096 if (IS_ERR(pctl->irqmux[i])) 1097 return PTR_ERR(pctl->irqmux[i]); 1098 } 1099 1100 return 0; 1101 } 1102 1103 static int stm32_pctrl_build_state(struct platform_device *pdev) 1104 { 1105 struct stm32_pinctrl *pctl = platform_get_drvdata(pdev); 1106 int i; 1107 1108 pctl->ngroups = pctl->match_data->npins; 1109 1110 /* Allocate groups */ 1111 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups, 1112 sizeof(*pctl->groups), GFP_KERNEL); 1113 if (!pctl->groups) 1114 return -ENOMEM; 1115 1116 /* We assume that one pin is one group, use pin name as group name. */ 1117 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups, 1118 sizeof(*pctl->grp_names), GFP_KERNEL); 1119 if (!pctl->grp_names) 1120 return -ENOMEM; 1121 1122 for (i = 0; i < pctl->match_data->npins; i++) { 1123 const struct stm32_desc_pin *pin = pctl->match_data->pins + i; 1124 struct stm32_pinctrl_group *group = pctl->groups + i; 1125 1126 group->name = pin->pin.name; 1127 group->pin = pin->pin.number; 1128 1129 pctl->grp_names[i] = pin->pin.name; 1130 } 1131 1132 return 0; 1133 } 1134 1135 int stm32_pctl_probe(struct platform_device *pdev) 1136 { 1137 struct device_node *np = pdev->dev.of_node; 1138 struct device_node *child; 1139 const struct of_device_id *match; 1140 struct device *dev = &pdev->dev; 1141 struct stm32_pinctrl *pctl; 1142 struct pinctrl_pin_desc *pins; 1143 int i, ret, banks = 0; 1144 1145 if (!np) 1146 return -EINVAL; 1147 1148 match = of_match_device(dev->driver->of_match_table, dev); 1149 if (!match || !match->data) 1150 return -EINVAL; 1151 1152 if (!of_find_property(np, "pins-are-numbered", NULL)) { 1153 dev_err(dev, "only support pins-are-numbered format\n"); 1154 return -EINVAL; 1155 } 1156 1157 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL); 1158 if (!pctl) 1159 return -ENOMEM; 1160 1161 platform_set_drvdata(pdev, pctl); 1162 1163 pctl->dev = dev; 1164 pctl->match_data = match->data; 1165 ret = stm32_pctrl_build_state(pdev); 1166 if (ret) { 1167 dev_err(dev, "build state failed: %d\n", ret); 1168 return -EINVAL; 1169 } 1170 1171 if (of_find_property(np, "interrupt-parent", NULL)) { 1172 ret = stm32_pctrl_dt_setup_irq(pdev, pctl); 1173 if (ret) 1174 return ret; 1175 } 1176 1177 pins = devm_kcalloc(&pdev->dev, pctl->match_data->npins, sizeof(*pins), 1178 GFP_KERNEL); 1179 if (!pins) 1180 return -ENOMEM; 1181 1182 for (i = 0; i < pctl->match_data->npins; i++) 1183 pins[i] = pctl->match_data->pins[i].pin; 1184 1185 pctl->pctl_desc.name = dev_name(&pdev->dev); 1186 pctl->pctl_desc.owner = THIS_MODULE; 1187 pctl->pctl_desc.pins = pins; 1188 pctl->pctl_desc.npins = pctl->match_data->npins; 1189 pctl->pctl_desc.confops = &stm32_pconf_ops; 1190 pctl->pctl_desc.pctlops = &stm32_pctrl_ops; 1191 pctl->pctl_desc.pmxops = &stm32_pmx_ops; 1192 pctl->dev = &pdev->dev; 1193 1194 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc, 1195 pctl); 1196 1197 if (IS_ERR(pctl->pctl_dev)) { 1198 dev_err(&pdev->dev, "Failed pinctrl registration\n"); 1199 return PTR_ERR(pctl->pctl_dev); 1200 } 1201 1202 for_each_available_child_of_node(np, child) 1203 if (of_property_read_bool(child, "gpio-controller")) 1204 banks++; 1205 1206 if (!banks) { 1207 dev_err(dev, "at least one GPIO bank is required\n"); 1208 return -EINVAL; 1209 } 1210 pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks), 1211 GFP_KERNEL); 1212 if (!pctl->banks) 1213 return -ENOMEM; 1214 1215 for_each_available_child_of_node(np, child) { 1216 if (of_property_read_bool(child, "gpio-controller")) { 1217 ret = stm32_gpiolib_register_bank(pctl, child); 1218 if (ret) 1219 return ret; 1220 1221 pctl->nbanks++; 1222 } 1223 } 1224 1225 dev_info(dev, "Pinctrl STM32 initialized\n"); 1226 1227 return 0; 1228 } 1229 1230