1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics 2017 5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 * 7 * Heavily based on Mediatek's pinctrl driver 8 */ 9 #include <linux/clk.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/hwspinlock.h> 12 #include <linux/io.h> 13 #include <linux/irq.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/of_address.h> 18 #include <linux/of_device.h> 19 #include <linux/of_irq.h> 20 #include <linux/pinctrl/consumer.h> 21 #include <linux/pinctrl/machine.h> 22 #include <linux/pinctrl/pinconf.h> 23 #include <linux/pinctrl/pinconf-generic.h> 24 #include <linux/pinctrl/pinctrl.h> 25 #include <linux/pinctrl/pinmux.h> 26 #include <linux/platform_device.h> 27 #include <linux/regmap.h> 28 #include <linux/reset.h> 29 #include <linux/slab.h> 30 31 #include "../core.h" 32 #include "../pinconf.h" 33 #include "../pinctrl-utils.h" 34 #include "pinctrl-stm32.h" 35 36 #define STM32_GPIO_MODER 0x00 37 #define STM32_GPIO_TYPER 0x04 38 #define STM32_GPIO_SPEEDR 0x08 39 #define STM32_GPIO_PUPDR 0x0c 40 #define STM32_GPIO_IDR 0x10 41 #define STM32_GPIO_ODR 0x14 42 #define STM32_GPIO_BSRR 0x18 43 #define STM32_GPIO_LCKR 0x1c 44 #define STM32_GPIO_AFRL 0x20 45 #define STM32_GPIO_AFRH 0x24 46 47 /* custom bitfield to backup pin status */ 48 #define STM32_GPIO_BKP_MODE_SHIFT 0 49 #define STM32_GPIO_BKP_MODE_MASK GENMASK(1, 0) 50 #define STM32_GPIO_BKP_ALT_SHIFT 2 51 #define STM32_GPIO_BKP_ALT_MASK GENMASK(5, 2) 52 #define STM32_GPIO_BKP_SPEED_SHIFT 6 53 #define STM32_GPIO_BKP_SPEED_MASK GENMASK(7, 6) 54 #define STM32_GPIO_BKP_PUPD_SHIFT 8 55 #define STM32_GPIO_BKP_PUPD_MASK GENMASK(9, 8) 56 #define STM32_GPIO_BKP_TYPE 10 57 #define STM32_GPIO_BKP_VAL 11 58 59 #define STM32_GPIO_PINS_PER_BANK 16 60 #define STM32_GPIO_IRQ_LINE 16 61 62 #define SYSCFG_IRQMUX_MASK GENMASK(3, 0) 63 64 #define gpio_range_to_bank(chip) \ 65 container_of(chip, struct stm32_gpio_bank, range) 66 67 #define HWSPNLCK_TIMEOUT 1000 /* usec */ 68 69 static const char * const stm32_gpio_functions[] = { 70 "gpio", "af0", "af1", 71 "af2", "af3", "af4", 72 "af5", "af6", "af7", 73 "af8", "af9", "af10", 74 "af11", "af12", "af13", 75 "af14", "af15", "analog", 76 }; 77 78 struct stm32_pinctrl_group { 79 const char *name; 80 unsigned long config; 81 unsigned pin; 82 }; 83 84 struct stm32_gpio_bank { 85 void __iomem *base; 86 struct clk *clk; 87 struct reset_control *rstc; 88 spinlock_t lock; 89 struct gpio_chip gpio_chip; 90 struct pinctrl_gpio_range range; 91 struct fwnode_handle *fwnode; 92 struct irq_domain *domain; 93 u32 bank_nr; 94 u32 bank_ioport_nr; 95 u32 pin_backup[STM32_GPIO_PINS_PER_BANK]; 96 u8 irq_type[STM32_GPIO_PINS_PER_BANK]; 97 }; 98 99 struct stm32_pinctrl { 100 struct device *dev; 101 struct pinctrl_dev *pctl_dev; 102 struct pinctrl_desc pctl_desc; 103 struct stm32_pinctrl_group *groups; 104 unsigned ngroups; 105 const char **grp_names; 106 struct stm32_gpio_bank *banks; 107 unsigned nbanks; 108 const struct stm32_pinctrl_match_data *match_data; 109 struct irq_domain *domain; 110 struct regmap *regmap; 111 struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK]; 112 struct hwspinlock *hwlock; 113 struct stm32_desc_pin *pins; 114 u32 npins; 115 u32 pkg; 116 u16 irqmux_map; 117 spinlock_t irqmux_lock; 118 }; 119 120 static inline int stm32_gpio_pin(int gpio) 121 { 122 return gpio % STM32_GPIO_PINS_PER_BANK; 123 } 124 125 static inline u32 stm32_gpio_get_mode(u32 function) 126 { 127 switch (function) { 128 case STM32_PIN_GPIO: 129 return 0; 130 case STM32_PIN_AF(0) ... STM32_PIN_AF(15): 131 return 2; 132 case STM32_PIN_ANALOG: 133 return 3; 134 } 135 136 return 0; 137 } 138 139 static inline u32 stm32_gpio_get_alt(u32 function) 140 { 141 switch (function) { 142 case STM32_PIN_GPIO: 143 return 0; 144 case STM32_PIN_AF(0) ... STM32_PIN_AF(15): 145 return function - 1; 146 case STM32_PIN_ANALOG: 147 return 0; 148 } 149 150 return 0; 151 } 152 153 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank, 154 u32 offset, u32 value) 155 { 156 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL); 157 bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL; 158 } 159 160 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset, 161 u32 mode, u32 alt) 162 { 163 bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK | 164 STM32_GPIO_BKP_ALT_MASK); 165 bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT; 166 bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT; 167 } 168 169 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset, 170 u32 drive) 171 { 172 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE); 173 bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE; 174 } 175 176 static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset, 177 u32 speed) 178 { 179 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK; 180 bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT; 181 } 182 183 static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset, 184 u32 bias) 185 { 186 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK; 187 bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT; 188 } 189 190 /* GPIO functions */ 191 192 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank, 193 unsigned offset, int value) 194 { 195 stm32_gpio_backup_value(bank, offset, value); 196 197 if (!value) 198 offset += STM32_GPIO_PINS_PER_BANK; 199 200 clk_enable(bank->clk); 201 202 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR); 203 204 clk_disable(bank->clk); 205 } 206 207 static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset) 208 { 209 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 210 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 211 struct pinctrl_gpio_range *range; 212 int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK); 213 214 range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin); 215 if (!range) { 216 dev_err(pctl->dev, "pin %d not in range.\n", pin); 217 return -EINVAL; 218 } 219 220 return pinctrl_gpio_request(chip->base + offset); 221 } 222 223 static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset) 224 { 225 pinctrl_gpio_free(chip->base + offset); 226 } 227 228 static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset) 229 { 230 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 231 int ret; 232 233 clk_enable(bank->clk); 234 235 ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset)); 236 237 clk_disable(bank->clk); 238 239 return ret; 240 } 241 242 static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 243 { 244 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 245 246 __stm32_gpio_set(bank, offset, value); 247 } 248 249 static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 250 { 251 return pinctrl_gpio_direction_input(chip->base + offset); 252 } 253 254 static int stm32_gpio_direction_output(struct gpio_chip *chip, 255 unsigned offset, int value) 256 { 257 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 258 259 __stm32_gpio_set(bank, offset, value); 260 pinctrl_gpio_direction_output(chip->base + offset); 261 262 return 0; 263 } 264 265 266 static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) 267 { 268 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 269 struct irq_fwspec fwspec; 270 271 fwspec.fwnode = bank->fwnode; 272 fwspec.param_count = 2; 273 fwspec.param[0] = offset; 274 fwspec.param[1] = IRQ_TYPE_NONE; 275 276 return irq_create_fwspec_mapping(&fwspec); 277 } 278 279 static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 280 { 281 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 282 int pin = stm32_gpio_pin(offset); 283 int ret; 284 u32 mode, alt; 285 286 stm32_pmx_get_mode(bank, pin, &mode, &alt); 287 if ((alt == 0) && (mode == 0)) 288 ret = GPIO_LINE_DIRECTION_IN; 289 else if ((alt == 0) && (mode == 1)) 290 ret = GPIO_LINE_DIRECTION_OUT; 291 else 292 ret = -EINVAL; 293 294 return ret; 295 } 296 297 static const struct gpio_chip stm32_gpio_template = { 298 .request = stm32_gpio_request, 299 .free = stm32_gpio_free, 300 .get = stm32_gpio_get, 301 .set = stm32_gpio_set, 302 .direction_input = stm32_gpio_direction_input, 303 .direction_output = stm32_gpio_direction_output, 304 .to_irq = stm32_gpio_to_irq, 305 .get_direction = stm32_gpio_get_direction, 306 .set_config = gpiochip_generic_config, 307 }; 308 309 static void stm32_gpio_irq_trigger(struct irq_data *d) 310 { 311 struct stm32_gpio_bank *bank = d->domain->host_data; 312 int level; 313 314 /* If level interrupt type then retrig */ 315 level = stm32_gpio_get(&bank->gpio_chip, d->hwirq); 316 if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) || 317 (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH)) 318 irq_chip_retrigger_hierarchy(d); 319 } 320 321 static void stm32_gpio_irq_eoi(struct irq_data *d) 322 { 323 irq_chip_eoi_parent(d); 324 stm32_gpio_irq_trigger(d); 325 }; 326 327 static int stm32_gpio_set_type(struct irq_data *d, unsigned int type) 328 { 329 struct stm32_gpio_bank *bank = d->domain->host_data; 330 u32 parent_type; 331 332 switch (type) { 333 case IRQ_TYPE_EDGE_RISING: 334 case IRQ_TYPE_EDGE_FALLING: 335 case IRQ_TYPE_EDGE_BOTH: 336 parent_type = type; 337 break; 338 case IRQ_TYPE_LEVEL_HIGH: 339 parent_type = IRQ_TYPE_EDGE_RISING; 340 break; 341 case IRQ_TYPE_LEVEL_LOW: 342 parent_type = IRQ_TYPE_EDGE_FALLING; 343 break; 344 default: 345 return -EINVAL; 346 } 347 348 bank->irq_type[d->hwirq] = type; 349 350 return irq_chip_set_type_parent(d, parent_type); 351 }; 352 353 static int stm32_gpio_irq_request_resources(struct irq_data *irq_data) 354 { 355 struct stm32_gpio_bank *bank = irq_data->domain->host_data; 356 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 357 int ret; 358 359 ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq); 360 if (ret) 361 return ret; 362 363 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq); 364 if (ret) { 365 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", 366 irq_data->hwirq); 367 return ret; 368 } 369 370 return 0; 371 } 372 373 static void stm32_gpio_irq_release_resources(struct irq_data *irq_data) 374 { 375 struct stm32_gpio_bank *bank = irq_data->domain->host_data; 376 377 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq); 378 } 379 380 static void stm32_gpio_irq_unmask(struct irq_data *d) 381 { 382 irq_chip_unmask_parent(d); 383 stm32_gpio_irq_trigger(d); 384 } 385 386 static struct irq_chip stm32_gpio_irq_chip = { 387 .name = "stm32gpio", 388 .irq_eoi = stm32_gpio_irq_eoi, 389 .irq_ack = irq_chip_ack_parent, 390 .irq_mask = irq_chip_mask_parent, 391 .irq_unmask = stm32_gpio_irq_unmask, 392 .irq_set_type = stm32_gpio_set_type, 393 .irq_set_wake = irq_chip_set_wake_parent, 394 .irq_request_resources = stm32_gpio_irq_request_resources, 395 .irq_release_resources = stm32_gpio_irq_release_resources, 396 }; 397 398 static int stm32_gpio_domain_translate(struct irq_domain *d, 399 struct irq_fwspec *fwspec, 400 unsigned long *hwirq, 401 unsigned int *type) 402 { 403 if ((fwspec->param_count != 2) || 404 (fwspec->param[0] >= STM32_GPIO_IRQ_LINE)) 405 return -EINVAL; 406 407 *hwirq = fwspec->param[0]; 408 *type = fwspec->param[1]; 409 return 0; 410 } 411 412 static int stm32_gpio_domain_activate(struct irq_domain *d, 413 struct irq_data *irq_data, bool reserve) 414 { 415 struct stm32_gpio_bank *bank = d->host_data; 416 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 417 int ret = 0; 418 419 if (pctl->hwlock) { 420 ret = hwspin_lock_timeout_in_atomic(pctl->hwlock, 421 HWSPNLCK_TIMEOUT); 422 if (ret) { 423 dev_err(pctl->dev, "Can't get hwspinlock\n"); 424 return ret; 425 } 426 } 427 428 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr); 429 430 if (pctl->hwlock) 431 hwspin_unlock_in_atomic(pctl->hwlock); 432 433 return ret; 434 } 435 436 static int stm32_gpio_domain_alloc(struct irq_domain *d, 437 unsigned int virq, 438 unsigned int nr_irqs, void *data) 439 { 440 struct stm32_gpio_bank *bank = d->host_data; 441 struct irq_fwspec *fwspec = data; 442 struct irq_fwspec parent_fwspec; 443 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 444 irq_hw_number_t hwirq = fwspec->param[0]; 445 unsigned long flags; 446 int ret = 0; 447 448 /* 449 * Check first that the IRQ MUX of that line is free. 450 * gpio irq mux is shared between several banks, protect with a lock 451 */ 452 spin_lock_irqsave(&pctl->irqmux_lock, flags); 453 454 if (pctl->irqmux_map & BIT(hwirq)) { 455 dev_err(pctl->dev, "irq line %ld already requested.\n", hwirq); 456 ret = -EBUSY; 457 } else { 458 pctl->irqmux_map |= BIT(hwirq); 459 } 460 461 spin_unlock_irqrestore(&pctl->irqmux_lock, flags); 462 if (ret) 463 return ret; 464 465 parent_fwspec.fwnode = d->parent->fwnode; 466 parent_fwspec.param_count = 2; 467 parent_fwspec.param[0] = fwspec->param[0]; 468 parent_fwspec.param[1] = fwspec->param[1]; 469 470 irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip, 471 bank); 472 473 return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec); 474 } 475 476 static void stm32_gpio_domain_free(struct irq_domain *d, unsigned int virq, 477 unsigned int nr_irqs) 478 { 479 struct stm32_gpio_bank *bank = d->host_data; 480 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 481 struct irq_data *irq_data = irq_domain_get_irq_data(d, virq); 482 unsigned long flags, hwirq = irq_data->hwirq; 483 484 irq_domain_free_irqs_common(d, virq, nr_irqs); 485 486 spin_lock_irqsave(&pctl->irqmux_lock, flags); 487 pctl->irqmux_map &= ~BIT(hwirq); 488 spin_unlock_irqrestore(&pctl->irqmux_lock, flags); 489 } 490 491 static const struct irq_domain_ops stm32_gpio_domain_ops = { 492 .translate = stm32_gpio_domain_translate, 493 .alloc = stm32_gpio_domain_alloc, 494 .free = stm32_gpio_domain_free, 495 .activate = stm32_gpio_domain_activate, 496 }; 497 498 /* Pinctrl functions */ 499 static struct stm32_pinctrl_group * 500 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin) 501 { 502 int i; 503 504 for (i = 0; i < pctl->ngroups; i++) { 505 struct stm32_pinctrl_group *grp = pctl->groups + i; 506 507 if (grp->pin == pin) 508 return grp; 509 } 510 511 return NULL; 512 } 513 514 static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl, 515 u32 pin_num, u32 fnum) 516 { 517 int i; 518 519 for (i = 0; i < pctl->npins; i++) { 520 const struct stm32_desc_pin *pin = pctl->pins + i; 521 const struct stm32_desc_function *func = pin->functions; 522 523 if (pin->pin.number != pin_num) 524 continue; 525 526 while (func && func->name) { 527 if (func->num == fnum) 528 return true; 529 func++; 530 } 531 532 break; 533 } 534 535 dev_err(pctl->dev, "invalid function %d on pin %d .\n", fnum, pin_num); 536 537 return false; 538 } 539 540 static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl, 541 u32 pin, u32 fnum, struct stm32_pinctrl_group *grp, 542 struct pinctrl_map **map, unsigned *reserved_maps, 543 unsigned *num_maps) 544 { 545 if (*num_maps == *reserved_maps) 546 return -ENOSPC; 547 548 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; 549 (*map)[*num_maps].data.mux.group = grp->name; 550 551 if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) 552 return -EINVAL; 553 554 (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum]; 555 (*num_maps)++; 556 557 return 0; 558 } 559 560 static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, 561 struct device_node *node, 562 struct pinctrl_map **map, 563 unsigned *reserved_maps, 564 unsigned *num_maps) 565 { 566 struct stm32_pinctrl *pctl; 567 struct stm32_pinctrl_group *grp; 568 struct property *pins; 569 u32 pinfunc, pin, func; 570 unsigned long *configs; 571 unsigned int num_configs; 572 bool has_config = 0; 573 unsigned reserve = 0; 574 int num_pins, num_funcs, maps_per_pin, i, err = 0; 575 576 pctl = pinctrl_dev_get_drvdata(pctldev); 577 578 pins = of_find_property(node, "pinmux", NULL); 579 if (!pins) { 580 dev_err(pctl->dev, "missing pins property in node %pOFn .\n", 581 node); 582 return -EINVAL; 583 } 584 585 err = pinconf_generic_parse_dt_config(node, pctldev, &configs, 586 &num_configs); 587 if (err) 588 return err; 589 590 if (num_configs) 591 has_config = 1; 592 593 num_pins = pins->length / sizeof(u32); 594 num_funcs = num_pins; 595 maps_per_pin = 0; 596 if (num_funcs) 597 maps_per_pin++; 598 if (has_config && num_pins >= 1) 599 maps_per_pin++; 600 601 if (!num_pins || !maps_per_pin) { 602 err = -EINVAL; 603 goto exit; 604 } 605 606 reserve = num_pins * maps_per_pin; 607 608 err = pinctrl_utils_reserve_map(pctldev, map, 609 reserved_maps, num_maps, reserve); 610 if (err) 611 goto exit; 612 613 for (i = 0; i < num_pins; i++) { 614 err = of_property_read_u32_index(node, "pinmux", 615 i, &pinfunc); 616 if (err) 617 goto exit; 618 619 pin = STM32_GET_PIN_NO(pinfunc); 620 func = STM32_GET_PIN_FUNC(pinfunc); 621 622 if (!stm32_pctrl_is_function_valid(pctl, pin, func)) { 623 err = -EINVAL; 624 goto exit; 625 } 626 627 grp = stm32_pctrl_find_group_by_pin(pctl, pin); 628 if (!grp) { 629 dev_err(pctl->dev, "unable to match pin %d to group\n", 630 pin); 631 err = -EINVAL; 632 goto exit; 633 } 634 635 err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map, 636 reserved_maps, num_maps); 637 if (err) 638 goto exit; 639 640 if (has_config) { 641 err = pinctrl_utils_add_map_configs(pctldev, map, 642 reserved_maps, num_maps, grp->name, 643 configs, num_configs, 644 PIN_MAP_TYPE_CONFIGS_GROUP); 645 if (err) 646 goto exit; 647 } 648 } 649 650 exit: 651 kfree(configs); 652 return err; 653 } 654 655 static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 656 struct device_node *np_config, 657 struct pinctrl_map **map, unsigned *num_maps) 658 { 659 struct device_node *np; 660 unsigned reserved_maps; 661 int ret; 662 663 *map = NULL; 664 *num_maps = 0; 665 reserved_maps = 0; 666 667 for_each_child_of_node(np_config, np) { 668 ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map, 669 &reserved_maps, num_maps); 670 if (ret < 0) { 671 pinctrl_utils_free_map(pctldev, *map, *num_maps); 672 of_node_put(np); 673 return ret; 674 } 675 } 676 677 return 0; 678 } 679 680 static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev) 681 { 682 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 683 684 return pctl->ngroups; 685 } 686 687 static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev, 688 unsigned group) 689 { 690 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 691 692 return pctl->groups[group].name; 693 } 694 695 static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev, 696 unsigned group, 697 const unsigned **pins, 698 unsigned *num_pins) 699 { 700 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 701 702 *pins = (unsigned *)&pctl->groups[group].pin; 703 *num_pins = 1; 704 705 return 0; 706 } 707 708 static const struct pinctrl_ops stm32_pctrl_ops = { 709 .dt_node_to_map = stm32_pctrl_dt_node_to_map, 710 .dt_free_map = pinctrl_utils_free_map, 711 .get_groups_count = stm32_pctrl_get_groups_count, 712 .get_group_name = stm32_pctrl_get_group_name, 713 .get_group_pins = stm32_pctrl_get_group_pins, 714 }; 715 716 717 /* Pinmux functions */ 718 719 static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 720 { 721 return ARRAY_SIZE(stm32_gpio_functions); 722 } 723 724 static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev, 725 unsigned selector) 726 { 727 return stm32_gpio_functions[selector]; 728 } 729 730 static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev, 731 unsigned function, 732 const char * const **groups, 733 unsigned * const num_groups) 734 { 735 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 736 737 *groups = pctl->grp_names; 738 *num_groups = pctl->ngroups; 739 740 return 0; 741 } 742 743 static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank, 744 int pin, u32 mode, u32 alt) 745 { 746 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 747 u32 val; 748 int alt_shift = (pin % 8) * 4; 749 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; 750 unsigned long flags; 751 int err = 0; 752 753 clk_enable(bank->clk); 754 spin_lock_irqsave(&bank->lock, flags); 755 756 if (pctl->hwlock) { 757 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, 758 HWSPNLCK_TIMEOUT); 759 if (err) { 760 dev_err(pctl->dev, "Can't get hwspinlock\n"); 761 goto unlock; 762 } 763 } 764 765 val = readl_relaxed(bank->base + alt_offset); 766 val &= ~GENMASK(alt_shift + 3, alt_shift); 767 val |= (alt << alt_shift); 768 writel_relaxed(val, bank->base + alt_offset); 769 770 val = readl_relaxed(bank->base + STM32_GPIO_MODER); 771 val &= ~GENMASK(pin * 2 + 1, pin * 2); 772 val |= mode << (pin * 2); 773 writel_relaxed(val, bank->base + STM32_GPIO_MODER); 774 775 if (pctl->hwlock) 776 hwspin_unlock_in_atomic(pctl->hwlock); 777 778 stm32_gpio_backup_mode(bank, pin, mode, alt); 779 780 unlock: 781 spin_unlock_irqrestore(&bank->lock, flags); 782 clk_disable(bank->clk); 783 784 return err; 785 } 786 787 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, 788 u32 *alt) 789 { 790 u32 val; 791 int alt_shift = (pin % 8) * 4; 792 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; 793 unsigned long flags; 794 795 clk_enable(bank->clk); 796 spin_lock_irqsave(&bank->lock, flags); 797 798 val = readl_relaxed(bank->base + alt_offset); 799 val &= GENMASK(alt_shift + 3, alt_shift); 800 *alt = val >> alt_shift; 801 802 val = readl_relaxed(bank->base + STM32_GPIO_MODER); 803 val &= GENMASK(pin * 2 + 1, pin * 2); 804 *mode = val >> (pin * 2); 805 806 spin_unlock_irqrestore(&bank->lock, flags); 807 clk_disable(bank->clk); 808 } 809 810 static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev, 811 unsigned function, 812 unsigned group) 813 { 814 bool ret; 815 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 816 struct stm32_pinctrl_group *g = pctl->groups + group; 817 struct pinctrl_gpio_range *range; 818 struct stm32_gpio_bank *bank; 819 u32 mode, alt; 820 int pin; 821 822 ret = stm32_pctrl_is_function_valid(pctl, g->pin, function); 823 if (!ret) 824 return -EINVAL; 825 826 range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin); 827 if (!range) { 828 dev_err(pctl->dev, "No gpio range defined.\n"); 829 return -EINVAL; 830 } 831 832 bank = gpiochip_get_data(range->gc); 833 pin = stm32_gpio_pin(g->pin); 834 835 mode = stm32_gpio_get_mode(function); 836 alt = stm32_gpio_get_alt(function); 837 838 return stm32_pmx_set_mode(bank, pin, mode, alt); 839 } 840 841 static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 842 struct pinctrl_gpio_range *range, unsigned gpio, 843 bool input) 844 { 845 struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc); 846 int pin = stm32_gpio_pin(gpio); 847 848 return stm32_pmx_set_mode(bank, pin, !input, 0); 849 } 850 851 static const struct pinmux_ops stm32_pmx_ops = { 852 .get_functions_count = stm32_pmx_get_funcs_cnt, 853 .get_function_name = stm32_pmx_get_func_name, 854 .get_function_groups = stm32_pmx_get_func_groups, 855 .set_mux = stm32_pmx_set_mux, 856 .gpio_set_direction = stm32_pmx_gpio_set_direction, 857 .strict = true, 858 }; 859 860 /* Pinconf functions */ 861 862 static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank, 863 unsigned offset, u32 drive) 864 { 865 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 866 unsigned long flags; 867 u32 val; 868 int err = 0; 869 870 clk_enable(bank->clk); 871 spin_lock_irqsave(&bank->lock, flags); 872 873 if (pctl->hwlock) { 874 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, 875 HWSPNLCK_TIMEOUT); 876 if (err) { 877 dev_err(pctl->dev, "Can't get hwspinlock\n"); 878 goto unlock; 879 } 880 } 881 882 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); 883 val &= ~BIT(offset); 884 val |= drive << offset; 885 writel_relaxed(val, bank->base + STM32_GPIO_TYPER); 886 887 if (pctl->hwlock) 888 hwspin_unlock_in_atomic(pctl->hwlock); 889 890 stm32_gpio_backup_driving(bank, offset, drive); 891 892 unlock: 893 spin_unlock_irqrestore(&bank->lock, flags); 894 clk_disable(bank->clk); 895 896 return err; 897 } 898 899 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank, 900 unsigned int offset) 901 { 902 unsigned long flags; 903 u32 val; 904 905 clk_enable(bank->clk); 906 spin_lock_irqsave(&bank->lock, flags); 907 908 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); 909 val &= BIT(offset); 910 911 spin_unlock_irqrestore(&bank->lock, flags); 912 clk_disable(bank->clk); 913 914 return (val >> offset); 915 } 916 917 static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank, 918 unsigned offset, u32 speed) 919 { 920 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 921 unsigned long flags; 922 u32 val; 923 int err = 0; 924 925 clk_enable(bank->clk); 926 spin_lock_irqsave(&bank->lock, flags); 927 928 if (pctl->hwlock) { 929 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, 930 HWSPNLCK_TIMEOUT); 931 if (err) { 932 dev_err(pctl->dev, "Can't get hwspinlock\n"); 933 goto unlock; 934 } 935 } 936 937 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); 938 val &= ~GENMASK(offset * 2 + 1, offset * 2); 939 val |= speed << (offset * 2); 940 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR); 941 942 if (pctl->hwlock) 943 hwspin_unlock_in_atomic(pctl->hwlock); 944 945 stm32_gpio_backup_speed(bank, offset, speed); 946 947 unlock: 948 spin_unlock_irqrestore(&bank->lock, flags); 949 clk_disable(bank->clk); 950 951 return err; 952 } 953 954 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank, 955 unsigned int offset) 956 { 957 unsigned long flags; 958 u32 val; 959 960 clk_enable(bank->clk); 961 spin_lock_irqsave(&bank->lock, flags); 962 963 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); 964 val &= GENMASK(offset * 2 + 1, offset * 2); 965 966 spin_unlock_irqrestore(&bank->lock, flags); 967 clk_disable(bank->clk); 968 969 return (val >> (offset * 2)); 970 } 971 972 static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank, 973 unsigned offset, u32 bias) 974 { 975 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 976 unsigned long flags; 977 u32 val; 978 int err = 0; 979 980 clk_enable(bank->clk); 981 spin_lock_irqsave(&bank->lock, flags); 982 983 if (pctl->hwlock) { 984 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, 985 HWSPNLCK_TIMEOUT); 986 if (err) { 987 dev_err(pctl->dev, "Can't get hwspinlock\n"); 988 goto unlock; 989 } 990 } 991 992 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); 993 val &= ~GENMASK(offset * 2 + 1, offset * 2); 994 val |= bias << (offset * 2); 995 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR); 996 997 if (pctl->hwlock) 998 hwspin_unlock_in_atomic(pctl->hwlock); 999 1000 stm32_gpio_backup_bias(bank, offset, bias); 1001 1002 unlock: 1003 spin_unlock_irqrestore(&bank->lock, flags); 1004 clk_disable(bank->clk); 1005 1006 return err; 1007 } 1008 1009 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank, 1010 unsigned int offset) 1011 { 1012 unsigned long flags; 1013 u32 val; 1014 1015 clk_enable(bank->clk); 1016 spin_lock_irqsave(&bank->lock, flags); 1017 1018 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); 1019 val &= GENMASK(offset * 2 + 1, offset * 2); 1020 1021 spin_unlock_irqrestore(&bank->lock, flags); 1022 clk_disable(bank->clk); 1023 1024 return (val >> (offset * 2)); 1025 } 1026 1027 static bool stm32_pconf_get(struct stm32_gpio_bank *bank, 1028 unsigned int offset, bool dir) 1029 { 1030 unsigned long flags; 1031 u32 val; 1032 1033 clk_enable(bank->clk); 1034 spin_lock_irqsave(&bank->lock, flags); 1035 1036 if (dir) 1037 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & 1038 BIT(offset)); 1039 else 1040 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) & 1041 BIT(offset)); 1042 1043 spin_unlock_irqrestore(&bank->lock, flags); 1044 clk_disable(bank->clk); 1045 1046 return val; 1047 } 1048 1049 static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev, 1050 unsigned int pin, enum pin_config_param param, 1051 enum pin_config_param arg) 1052 { 1053 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1054 struct pinctrl_gpio_range *range; 1055 struct stm32_gpio_bank *bank; 1056 int offset, ret = 0; 1057 1058 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); 1059 if (!range) { 1060 dev_err(pctl->dev, "No gpio range defined.\n"); 1061 return -EINVAL; 1062 } 1063 1064 bank = gpiochip_get_data(range->gc); 1065 offset = stm32_gpio_pin(pin); 1066 1067 switch (param) { 1068 case PIN_CONFIG_DRIVE_PUSH_PULL: 1069 ret = stm32_pconf_set_driving(bank, offset, 0); 1070 break; 1071 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1072 ret = stm32_pconf_set_driving(bank, offset, 1); 1073 break; 1074 case PIN_CONFIG_SLEW_RATE: 1075 ret = stm32_pconf_set_speed(bank, offset, arg); 1076 break; 1077 case PIN_CONFIG_BIAS_DISABLE: 1078 ret = stm32_pconf_set_bias(bank, offset, 0); 1079 break; 1080 case PIN_CONFIG_BIAS_PULL_UP: 1081 ret = stm32_pconf_set_bias(bank, offset, 1); 1082 break; 1083 case PIN_CONFIG_BIAS_PULL_DOWN: 1084 ret = stm32_pconf_set_bias(bank, offset, 2); 1085 break; 1086 case PIN_CONFIG_OUTPUT: 1087 __stm32_gpio_set(bank, offset, arg); 1088 ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false); 1089 break; 1090 default: 1091 ret = -ENOTSUPP; 1092 } 1093 1094 return ret; 1095 } 1096 1097 static int stm32_pconf_group_get(struct pinctrl_dev *pctldev, 1098 unsigned group, 1099 unsigned long *config) 1100 { 1101 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1102 1103 *config = pctl->groups[group].config; 1104 1105 return 0; 1106 } 1107 1108 static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, 1109 unsigned long *configs, unsigned num_configs) 1110 { 1111 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1112 struct stm32_pinctrl_group *g = &pctl->groups[group]; 1113 int i, ret; 1114 1115 for (i = 0; i < num_configs; i++) { 1116 mutex_lock(&pctldev->mutex); 1117 ret = stm32_pconf_parse_conf(pctldev, g->pin, 1118 pinconf_to_config_param(configs[i]), 1119 pinconf_to_config_argument(configs[i])); 1120 mutex_unlock(&pctldev->mutex); 1121 if (ret < 0) 1122 return ret; 1123 1124 g->config = configs[i]; 1125 } 1126 1127 return 0; 1128 } 1129 1130 static int stm32_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 1131 unsigned long *configs, unsigned int num_configs) 1132 { 1133 int i, ret; 1134 1135 for (i = 0; i < num_configs; i++) { 1136 ret = stm32_pconf_parse_conf(pctldev, pin, 1137 pinconf_to_config_param(configs[i]), 1138 pinconf_to_config_argument(configs[i])); 1139 if (ret < 0) 1140 return ret; 1141 } 1142 1143 return 0; 1144 } 1145 1146 static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev, 1147 struct seq_file *s, 1148 unsigned int pin) 1149 { 1150 struct pinctrl_gpio_range *range; 1151 struct stm32_gpio_bank *bank; 1152 int offset; 1153 u32 mode, alt, drive, speed, bias; 1154 static const char * const modes[] = { 1155 "input", "output", "alternate", "analog" }; 1156 static const char * const speeds[] = { 1157 "low", "medium", "high", "very high" }; 1158 static const char * const biasing[] = { 1159 "floating", "pull up", "pull down", "" }; 1160 bool val; 1161 1162 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); 1163 if (!range) 1164 return; 1165 1166 bank = gpiochip_get_data(range->gc); 1167 offset = stm32_gpio_pin(pin); 1168 1169 stm32_pmx_get_mode(bank, offset, &mode, &alt); 1170 bias = stm32_pconf_get_bias(bank, offset); 1171 1172 seq_printf(s, "%s ", modes[mode]); 1173 1174 switch (mode) { 1175 /* input */ 1176 case 0: 1177 val = stm32_pconf_get(bank, offset, true); 1178 seq_printf(s, "- %s - %s", 1179 val ? "high" : "low", 1180 biasing[bias]); 1181 break; 1182 1183 /* output */ 1184 case 1: 1185 drive = stm32_pconf_get_driving(bank, offset); 1186 speed = stm32_pconf_get_speed(bank, offset); 1187 val = stm32_pconf_get(bank, offset, false); 1188 seq_printf(s, "- %s - %s - %s - %s %s", 1189 val ? "high" : "low", 1190 drive ? "open drain" : "push pull", 1191 biasing[bias], 1192 speeds[speed], "speed"); 1193 break; 1194 1195 /* alternate */ 1196 case 2: 1197 drive = stm32_pconf_get_driving(bank, offset); 1198 speed = stm32_pconf_get_speed(bank, offset); 1199 seq_printf(s, "%d - %s - %s - %s %s", alt, 1200 drive ? "open drain" : "push pull", 1201 biasing[bias], 1202 speeds[speed], "speed"); 1203 break; 1204 1205 /* analog */ 1206 case 3: 1207 break; 1208 } 1209 } 1210 1211 static const struct pinconf_ops stm32_pconf_ops = { 1212 .pin_config_group_get = stm32_pconf_group_get, 1213 .pin_config_group_set = stm32_pconf_group_set, 1214 .pin_config_set = stm32_pconf_set, 1215 .pin_config_dbg_show = stm32_pconf_dbg_show, 1216 }; 1217 1218 static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, 1219 struct device_node *np) 1220 { 1221 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks]; 1222 int bank_ioport_nr; 1223 struct pinctrl_gpio_range *range = &bank->range; 1224 struct of_phandle_args args; 1225 struct device *dev = pctl->dev; 1226 struct resource res; 1227 int npins = STM32_GPIO_PINS_PER_BANK; 1228 int bank_nr, err, i = 0; 1229 1230 if (!IS_ERR(bank->rstc)) 1231 reset_control_deassert(bank->rstc); 1232 1233 if (of_address_to_resource(np, 0, &res)) 1234 return -ENODEV; 1235 1236 bank->base = devm_ioremap_resource(dev, &res); 1237 if (IS_ERR(bank->base)) 1238 return PTR_ERR(bank->base); 1239 1240 err = clk_prepare(bank->clk); 1241 if (err) { 1242 dev_err(dev, "failed to prepare clk (%d)\n", err); 1243 return err; 1244 } 1245 1246 bank->gpio_chip = stm32_gpio_template; 1247 1248 of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label); 1249 1250 if (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, i, &args)) { 1251 bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK; 1252 bank->gpio_chip.base = args.args[1]; 1253 1254 npins = args.args[2]; 1255 while (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 1256 ++i, &args)) 1257 npins += args.args[2]; 1258 } else { 1259 bank_nr = pctl->nbanks; 1260 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; 1261 range->name = bank->gpio_chip.label; 1262 range->id = bank_nr; 1263 range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK; 1264 range->base = range->id * STM32_GPIO_PINS_PER_BANK; 1265 range->npins = npins; 1266 range->gc = &bank->gpio_chip; 1267 pinctrl_add_gpio_range(pctl->pctl_dev, 1268 &pctl->banks[bank_nr].range); 1269 } 1270 1271 if (of_property_read_u32(np, "st,bank-ioport", &bank_ioport_nr)) 1272 bank_ioport_nr = bank_nr; 1273 1274 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; 1275 1276 bank->gpio_chip.ngpio = npins; 1277 bank->gpio_chip.of_node = np; 1278 bank->gpio_chip.parent = dev; 1279 bank->bank_nr = bank_nr; 1280 bank->bank_ioport_nr = bank_ioport_nr; 1281 spin_lock_init(&bank->lock); 1282 1283 /* create irq hierarchical domain */ 1284 bank->fwnode = of_node_to_fwnode(np); 1285 1286 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, 1287 STM32_GPIO_IRQ_LINE, bank->fwnode, 1288 &stm32_gpio_domain_ops, bank); 1289 1290 if (!bank->domain) 1291 return -ENODEV; 1292 1293 err = gpiochip_add_data(&bank->gpio_chip, bank); 1294 if (err) { 1295 dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr); 1296 return err; 1297 } 1298 1299 dev_info(dev, "%s bank added\n", bank->gpio_chip.label); 1300 return 0; 1301 } 1302 1303 static struct irq_domain *stm32_pctrl_get_irq_domain(struct device_node *np) 1304 { 1305 struct device_node *parent; 1306 struct irq_domain *domain; 1307 1308 if (!of_find_property(np, "interrupt-parent", NULL)) 1309 return NULL; 1310 1311 parent = of_irq_find_parent(np); 1312 if (!parent) 1313 return ERR_PTR(-ENXIO); 1314 1315 domain = irq_find_host(parent); 1316 if (!domain) 1317 /* domain not registered yet */ 1318 return ERR_PTR(-EPROBE_DEFER); 1319 1320 return domain; 1321 } 1322 1323 static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev, 1324 struct stm32_pinctrl *pctl) 1325 { 1326 struct device_node *np = pdev->dev.of_node; 1327 struct device *dev = &pdev->dev; 1328 struct regmap *rm; 1329 int offset, ret, i; 1330 int mask, mask_width; 1331 1332 pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); 1333 if (IS_ERR(pctl->regmap)) 1334 return PTR_ERR(pctl->regmap); 1335 1336 rm = pctl->regmap; 1337 1338 ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset); 1339 if (ret) 1340 return ret; 1341 1342 ret = of_property_read_u32_index(np, "st,syscfg", 2, &mask); 1343 if (ret) 1344 mask = SYSCFG_IRQMUX_MASK; 1345 1346 mask_width = fls(mask); 1347 1348 for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) { 1349 struct reg_field mux; 1350 1351 mux.reg = offset + (i / 4) * 4; 1352 mux.lsb = (i % 4) * mask_width; 1353 mux.msb = mux.lsb + mask_width - 1; 1354 1355 dev_dbg(dev, "irqmux%d: reg:%#x, lsb:%d, msb:%d\n", 1356 i, mux.reg, mux.lsb, mux.msb); 1357 1358 pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux); 1359 if (IS_ERR(pctl->irqmux[i])) 1360 return PTR_ERR(pctl->irqmux[i]); 1361 } 1362 1363 return 0; 1364 } 1365 1366 static int stm32_pctrl_build_state(struct platform_device *pdev) 1367 { 1368 struct stm32_pinctrl *pctl = platform_get_drvdata(pdev); 1369 int i; 1370 1371 pctl->ngroups = pctl->npins; 1372 1373 /* Allocate groups */ 1374 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups, 1375 sizeof(*pctl->groups), GFP_KERNEL); 1376 if (!pctl->groups) 1377 return -ENOMEM; 1378 1379 /* We assume that one pin is one group, use pin name as group name. */ 1380 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups, 1381 sizeof(*pctl->grp_names), GFP_KERNEL); 1382 if (!pctl->grp_names) 1383 return -ENOMEM; 1384 1385 for (i = 0; i < pctl->npins; i++) { 1386 const struct stm32_desc_pin *pin = pctl->pins + i; 1387 struct stm32_pinctrl_group *group = pctl->groups + i; 1388 1389 group->name = pin->pin.name; 1390 group->pin = pin->pin.number; 1391 pctl->grp_names[i] = pin->pin.name; 1392 } 1393 1394 return 0; 1395 } 1396 1397 static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl, 1398 struct stm32_desc_pin *pins) 1399 { 1400 const struct stm32_desc_pin *p; 1401 int i, nb_pins_available = 0; 1402 1403 for (i = 0; i < pctl->match_data->npins; i++) { 1404 p = pctl->match_data->pins + i; 1405 if (pctl->pkg && !(pctl->pkg & p->pkg)) 1406 continue; 1407 pins->pin = p->pin; 1408 pins->functions = p->functions; 1409 pins++; 1410 nb_pins_available++; 1411 } 1412 1413 pctl->npins = nb_pins_available; 1414 1415 return 0; 1416 } 1417 1418 int stm32_pctl_probe(struct platform_device *pdev) 1419 { 1420 struct device_node *np = pdev->dev.of_node; 1421 struct device_node *child; 1422 const struct of_device_id *match; 1423 struct device *dev = &pdev->dev; 1424 struct stm32_pinctrl *pctl; 1425 struct pinctrl_pin_desc *pins; 1426 int i, ret, hwlock_id, banks = 0; 1427 1428 if (!np) 1429 return -EINVAL; 1430 1431 match = of_match_device(dev->driver->of_match_table, dev); 1432 if (!match || !match->data) 1433 return -EINVAL; 1434 1435 if (!of_find_property(np, "pins-are-numbered", NULL)) { 1436 dev_err(dev, "only support pins-are-numbered format\n"); 1437 return -EINVAL; 1438 } 1439 1440 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL); 1441 if (!pctl) 1442 return -ENOMEM; 1443 1444 platform_set_drvdata(pdev, pctl); 1445 1446 /* check for IRQ controller (may require deferred probe) */ 1447 pctl->domain = stm32_pctrl_get_irq_domain(np); 1448 if (IS_ERR(pctl->domain)) 1449 return PTR_ERR(pctl->domain); 1450 1451 /* hwspinlock is optional */ 1452 hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0); 1453 if (hwlock_id < 0) { 1454 if (hwlock_id == -EPROBE_DEFER) 1455 return hwlock_id; 1456 } else { 1457 pctl->hwlock = hwspin_lock_request_specific(hwlock_id); 1458 } 1459 1460 spin_lock_init(&pctl->irqmux_lock); 1461 1462 pctl->dev = dev; 1463 pctl->match_data = match->data; 1464 1465 /* get optional package information */ 1466 if (!of_property_read_u32(np, "st,package", &pctl->pkg)) 1467 dev_dbg(pctl->dev, "package detected: %x\n", pctl->pkg); 1468 1469 pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins, 1470 sizeof(*pctl->pins), GFP_KERNEL); 1471 if (!pctl->pins) 1472 return -ENOMEM; 1473 1474 ret = stm32_pctrl_create_pins_tab(pctl, pctl->pins); 1475 if (ret) 1476 return ret; 1477 1478 ret = stm32_pctrl_build_state(pdev); 1479 if (ret) { 1480 dev_err(dev, "build state failed: %d\n", ret); 1481 return -EINVAL; 1482 } 1483 1484 if (pctl->domain) { 1485 ret = stm32_pctrl_dt_setup_irq(pdev, pctl); 1486 if (ret) 1487 return ret; 1488 } 1489 1490 pins = devm_kcalloc(&pdev->dev, pctl->npins, sizeof(*pins), 1491 GFP_KERNEL); 1492 if (!pins) 1493 return -ENOMEM; 1494 1495 for (i = 0; i < pctl->npins; i++) 1496 pins[i] = pctl->pins[i].pin; 1497 1498 pctl->pctl_desc.name = dev_name(&pdev->dev); 1499 pctl->pctl_desc.owner = THIS_MODULE; 1500 pctl->pctl_desc.pins = pins; 1501 pctl->pctl_desc.npins = pctl->npins; 1502 pctl->pctl_desc.link_consumers = true; 1503 pctl->pctl_desc.confops = &stm32_pconf_ops; 1504 pctl->pctl_desc.pctlops = &stm32_pctrl_ops; 1505 pctl->pctl_desc.pmxops = &stm32_pmx_ops; 1506 pctl->dev = &pdev->dev; 1507 1508 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc, 1509 pctl); 1510 1511 if (IS_ERR(pctl->pctl_dev)) { 1512 dev_err(&pdev->dev, "Failed pinctrl registration\n"); 1513 return PTR_ERR(pctl->pctl_dev); 1514 } 1515 1516 for_each_available_child_of_node(np, child) 1517 if (of_property_read_bool(child, "gpio-controller")) 1518 banks++; 1519 1520 if (!banks) { 1521 dev_err(dev, "at least one GPIO bank is required\n"); 1522 return -EINVAL; 1523 } 1524 pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks), 1525 GFP_KERNEL); 1526 if (!pctl->banks) 1527 return -ENOMEM; 1528 1529 i = 0; 1530 for_each_available_child_of_node(np, child) { 1531 struct stm32_gpio_bank *bank = &pctl->banks[i]; 1532 1533 if (of_property_read_bool(child, "gpio-controller")) { 1534 bank->rstc = of_reset_control_get_exclusive(child, 1535 NULL); 1536 if (PTR_ERR(bank->rstc) == -EPROBE_DEFER) { 1537 of_node_put(child); 1538 return -EPROBE_DEFER; 1539 } 1540 1541 bank->clk = of_clk_get_by_name(child, NULL); 1542 if (IS_ERR(bank->clk)) { 1543 if (PTR_ERR(bank->clk) != -EPROBE_DEFER) 1544 dev_err(dev, 1545 "failed to get clk (%ld)\n", 1546 PTR_ERR(bank->clk)); 1547 of_node_put(child); 1548 return PTR_ERR(bank->clk); 1549 } 1550 i++; 1551 } 1552 } 1553 1554 for_each_available_child_of_node(np, child) { 1555 if (of_property_read_bool(child, "gpio-controller")) { 1556 ret = stm32_gpiolib_register_bank(pctl, child); 1557 if (ret) { 1558 of_node_put(child); 1559 return ret; 1560 } 1561 1562 pctl->nbanks++; 1563 } 1564 } 1565 1566 dev_info(dev, "Pinctrl STM32 initialized\n"); 1567 1568 return 0; 1569 } 1570 1571 static int __maybe_unused stm32_pinctrl_restore_gpio_regs( 1572 struct stm32_pinctrl *pctl, u32 pin) 1573 { 1574 const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin); 1575 u32 val, alt, mode, offset = stm32_gpio_pin(pin); 1576 struct pinctrl_gpio_range *range; 1577 struct stm32_gpio_bank *bank; 1578 bool pin_is_irq; 1579 int ret; 1580 1581 range = pinctrl_find_gpio_range_from_pin(pctl->pctl_dev, pin); 1582 if (!range) 1583 return 0; 1584 1585 pin_is_irq = gpiochip_line_is_irq(range->gc, offset); 1586 1587 if (!desc || (!pin_is_irq && !desc->gpio_owner)) 1588 return 0; 1589 1590 bank = gpiochip_get_data(range->gc); 1591 1592 alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK; 1593 alt >>= STM32_GPIO_BKP_ALT_SHIFT; 1594 mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK; 1595 mode >>= STM32_GPIO_BKP_MODE_SHIFT; 1596 1597 ret = stm32_pmx_set_mode(bank, offset, mode, alt); 1598 if (ret) 1599 return ret; 1600 1601 if (mode == 1) { 1602 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL); 1603 val = val >> STM32_GPIO_BKP_VAL; 1604 __stm32_gpio_set(bank, offset, val); 1605 } 1606 1607 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE); 1608 val >>= STM32_GPIO_BKP_TYPE; 1609 ret = stm32_pconf_set_driving(bank, offset, val); 1610 if (ret) 1611 return ret; 1612 1613 val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK; 1614 val >>= STM32_GPIO_BKP_SPEED_SHIFT; 1615 ret = stm32_pconf_set_speed(bank, offset, val); 1616 if (ret) 1617 return ret; 1618 1619 val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK; 1620 val >>= STM32_GPIO_BKP_PUPD_SHIFT; 1621 ret = stm32_pconf_set_bias(bank, offset, val); 1622 if (ret) 1623 return ret; 1624 1625 if (pin_is_irq) 1626 regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr); 1627 1628 return 0; 1629 } 1630 1631 int __maybe_unused stm32_pinctrl_resume(struct device *dev) 1632 { 1633 struct stm32_pinctrl *pctl = dev_get_drvdata(dev); 1634 struct stm32_pinctrl_group *g = pctl->groups; 1635 int i; 1636 1637 for (i = 0; i < pctl->ngroups; i++, g++) 1638 stm32_pinctrl_restore_gpio_regs(pctl, g->pin); 1639 1640 return 0; 1641 } 1642