1 /* 2 * Copyright (C) Maxime Coquelin 2015 3 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> 4 * License terms: GNU General Public License (GPL), version 2 5 * 6 * Heavily based on Mediatek's pinctrl driver 7 */ 8 #include <linux/clk.h> 9 #include <linux/gpio/driver.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/of_address.h> 14 #include <linux/of_device.h> 15 #include <linux/of_irq.h> 16 #include <linux/pinctrl/consumer.h> 17 #include <linux/pinctrl/machine.h> 18 #include <linux/pinctrl/pinconf.h> 19 #include <linux/pinctrl/pinconf-generic.h> 20 #include <linux/pinctrl/pinctrl.h> 21 #include <linux/pinctrl/pinmux.h> 22 #include <linux/platform_device.h> 23 #include <linux/reset.h> 24 #include <linux/slab.h> 25 26 #include "../core.h" 27 #include "../pinconf.h" 28 #include "../pinctrl-utils.h" 29 #include "pinctrl-stm32.h" 30 31 #define STM32_GPIO_MODER 0x00 32 #define STM32_GPIO_TYPER 0x04 33 #define STM32_GPIO_SPEEDR 0x08 34 #define STM32_GPIO_PUPDR 0x0c 35 #define STM32_GPIO_IDR 0x10 36 #define STM32_GPIO_ODR 0x14 37 #define STM32_GPIO_BSRR 0x18 38 #define STM32_GPIO_LCKR 0x1c 39 #define STM32_GPIO_AFRL 0x20 40 #define STM32_GPIO_AFRH 0x24 41 42 #define STM32_GPIO_PINS_PER_BANK 16 43 44 #define gpio_range_to_bank(chip) \ 45 container_of(chip, struct stm32_gpio_bank, range) 46 47 static const char * const stm32_gpio_functions[] = { 48 "gpio", "af0", "af1", 49 "af2", "af3", "af4", 50 "af5", "af6", "af7", 51 "af8", "af9", "af10", 52 "af11", "af12", "af13", 53 "af14", "af15", "analog", 54 }; 55 56 struct stm32_pinctrl_group { 57 const char *name; 58 unsigned long config; 59 unsigned pin; 60 }; 61 62 struct stm32_gpio_bank { 63 void __iomem *base; 64 struct clk *clk; 65 spinlock_t lock; 66 struct gpio_chip gpio_chip; 67 struct pinctrl_gpio_range range; 68 }; 69 70 struct stm32_pinctrl { 71 struct device *dev; 72 struct pinctrl_dev *pctl_dev; 73 struct pinctrl_desc pctl_desc; 74 struct stm32_pinctrl_group *groups; 75 unsigned ngroups; 76 const char **grp_names; 77 struct stm32_gpio_bank *banks; 78 unsigned nbanks; 79 const struct stm32_pinctrl_match_data *match_data; 80 }; 81 82 static inline int stm32_gpio_pin(int gpio) 83 { 84 return gpio % STM32_GPIO_PINS_PER_BANK; 85 } 86 87 static inline u32 stm32_gpio_get_mode(u32 function) 88 { 89 switch (function) { 90 case STM32_PIN_GPIO: 91 return 0; 92 case STM32_PIN_AF(0) ... STM32_PIN_AF(15): 93 return 2; 94 case STM32_PIN_ANALOG: 95 return 3; 96 } 97 98 return 0; 99 } 100 101 static inline u32 stm32_gpio_get_alt(u32 function) 102 { 103 switch (function) { 104 case STM32_PIN_GPIO: 105 return 0; 106 case STM32_PIN_AF(0) ... STM32_PIN_AF(15): 107 return function - 1; 108 case STM32_PIN_ANALOG: 109 return 0; 110 } 111 112 return 0; 113 } 114 115 /* GPIO functions */ 116 117 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank, 118 unsigned offset, int value) 119 { 120 if (!value) 121 offset += STM32_GPIO_PINS_PER_BANK; 122 123 clk_enable(bank->clk); 124 125 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR); 126 127 clk_disable(bank->clk); 128 } 129 130 static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset) 131 { 132 return pinctrl_request_gpio(chip->base + offset); 133 } 134 135 static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset) 136 { 137 pinctrl_free_gpio(chip->base + offset); 138 } 139 140 static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset) 141 { 142 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 143 int ret; 144 145 clk_enable(bank->clk); 146 147 ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset)); 148 149 clk_disable(bank->clk); 150 151 return ret; 152 } 153 154 static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 155 { 156 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 157 158 __stm32_gpio_set(bank, offset, value); 159 } 160 161 static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 162 { 163 return pinctrl_gpio_direction_input(chip->base + offset); 164 } 165 166 static int stm32_gpio_direction_output(struct gpio_chip *chip, 167 unsigned offset, int value) 168 { 169 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 170 171 __stm32_gpio_set(bank, offset, value); 172 pinctrl_gpio_direction_output(chip->base + offset); 173 174 return 0; 175 } 176 177 static struct gpio_chip stm32_gpio_template = { 178 .request = stm32_gpio_request, 179 .free = stm32_gpio_free, 180 .get = stm32_gpio_get, 181 .set = stm32_gpio_set, 182 .direction_input = stm32_gpio_direction_input, 183 .direction_output = stm32_gpio_direction_output, 184 }; 185 186 /* Pinctrl functions */ 187 188 static struct stm32_pinctrl_group * 189 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin) 190 { 191 int i; 192 193 for (i = 0; i < pctl->ngroups; i++) { 194 struct stm32_pinctrl_group *grp = pctl->groups + i; 195 196 if (grp->pin == pin) 197 return grp; 198 } 199 200 return NULL; 201 } 202 203 static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl, 204 u32 pin_num, u32 fnum) 205 { 206 int i; 207 208 for (i = 0; i < pctl->match_data->npins; i++) { 209 const struct stm32_desc_pin *pin = pctl->match_data->pins + i; 210 const struct stm32_desc_function *func = pin->functions; 211 212 if (pin->pin.number != pin_num) 213 continue; 214 215 while (func && func->name) { 216 if (func->num == fnum) 217 return true; 218 func++; 219 } 220 221 break; 222 } 223 224 return false; 225 } 226 227 static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl, 228 u32 pin, u32 fnum, struct stm32_pinctrl_group *grp, 229 struct pinctrl_map **map, unsigned *reserved_maps, 230 unsigned *num_maps) 231 { 232 if (*num_maps == *reserved_maps) 233 return -ENOSPC; 234 235 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; 236 (*map)[*num_maps].data.mux.group = grp->name; 237 238 if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) { 239 dev_err(pctl->dev, "invalid function %d on pin %d .\n", 240 fnum, pin); 241 return -EINVAL; 242 } 243 244 (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum]; 245 (*num_maps)++; 246 247 return 0; 248 } 249 250 static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, 251 struct device_node *node, 252 struct pinctrl_map **map, 253 unsigned *reserved_maps, 254 unsigned *num_maps) 255 { 256 struct stm32_pinctrl *pctl; 257 struct stm32_pinctrl_group *grp; 258 struct property *pins; 259 u32 pinfunc, pin, func; 260 unsigned long *configs; 261 unsigned int num_configs; 262 bool has_config = 0; 263 unsigned reserve = 0; 264 int num_pins, num_funcs, maps_per_pin, i, err; 265 266 pctl = pinctrl_dev_get_drvdata(pctldev); 267 268 pins = of_find_property(node, "pinmux", NULL); 269 if (!pins) { 270 dev_err(pctl->dev, "missing pins property in node %s .\n", 271 node->name); 272 return -EINVAL; 273 } 274 275 err = pinconf_generic_parse_dt_config(node, pctldev, &configs, 276 &num_configs); 277 if (err) 278 return err; 279 280 if (num_configs) 281 has_config = 1; 282 283 num_pins = pins->length / sizeof(u32); 284 num_funcs = num_pins; 285 maps_per_pin = 0; 286 if (num_funcs) 287 maps_per_pin++; 288 if (has_config && num_pins >= 1) 289 maps_per_pin++; 290 291 if (!num_pins || !maps_per_pin) 292 return -EINVAL; 293 294 reserve = num_pins * maps_per_pin; 295 296 err = pinctrl_utils_reserve_map(pctldev, map, 297 reserved_maps, num_maps, reserve); 298 if (err) 299 return err; 300 301 for (i = 0; i < num_pins; i++) { 302 err = of_property_read_u32_index(node, "pinmux", 303 i, &pinfunc); 304 if (err) 305 return err; 306 307 pin = STM32_GET_PIN_NO(pinfunc); 308 func = STM32_GET_PIN_FUNC(pinfunc); 309 310 if (pin >= pctl->match_data->npins) { 311 dev_err(pctl->dev, "invalid pin number.\n"); 312 return -EINVAL; 313 } 314 315 if (!stm32_pctrl_is_function_valid(pctl, pin, func)) { 316 dev_err(pctl->dev, "invalid function.\n"); 317 return -EINVAL; 318 } 319 320 grp = stm32_pctrl_find_group_by_pin(pctl, pin); 321 if (!grp) { 322 dev_err(pctl->dev, "unable to match pin %d to group\n", 323 pin); 324 return -EINVAL; 325 } 326 327 err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map, 328 reserved_maps, num_maps); 329 if (err) 330 return err; 331 332 if (has_config) { 333 err = pinctrl_utils_add_map_configs(pctldev, map, 334 reserved_maps, num_maps, grp->name, 335 configs, num_configs, 336 PIN_MAP_TYPE_CONFIGS_GROUP); 337 if (err) 338 return err; 339 } 340 } 341 342 return 0; 343 } 344 345 static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 346 struct device_node *np_config, 347 struct pinctrl_map **map, unsigned *num_maps) 348 { 349 struct device_node *np; 350 unsigned reserved_maps; 351 int ret; 352 353 *map = NULL; 354 *num_maps = 0; 355 reserved_maps = 0; 356 357 for_each_child_of_node(np_config, np) { 358 ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map, 359 &reserved_maps, num_maps); 360 if (ret < 0) { 361 pinctrl_utils_free_map(pctldev, *map, *num_maps); 362 return ret; 363 } 364 } 365 366 return 0; 367 } 368 369 static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev) 370 { 371 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 372 373 return pctl->ngroups; 374 } 375 376 static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev, 377 unsigned group) 378 { 379 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 380 381 return pctl->groups[group].name; 382 } 383 384 static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev, 385 unsigned group, 386 const unsigned **pins, 387 unsigned *num_pins) 388 { 389 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 390 391 *pins = (unsigned *)&pctl->groups[group].pin; 392 *num_pins = 1; 393 394 return 0; 395 } 396 397 static const struct pinctrl_ops stm32_pctrl_ops = { 398 .dt_node_to_map = stm32_pctrl_dt_node_to_map, 399 .dt_free_map = pinctrl_utils_free_map, 400 .get_groups_count = stm32_pctrl_get_groups_count, 401 .get_group_name = stm32_pctrl_get_group_name, 402 .get_group_pins = stm32_pctrl_get_group_pins, 403 }; 404 405 406 /* Pinmux functions */ 407 408 static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 409 { 410 return ARRAY_SIZE(stm32_gpio_functions); 411 } 412 413 static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev, 414 unsigned selector) 415 { 416 return stm32_gpio_functions[selector]; 417 } 418 419 static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev, 420 unsigned function, 421 const char * const **groups, 422 unsigned * const num_groups) 423 { 424 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 425 426 *groups = pctl->grp_names; 427 *num_groups = pctl->ngroups; 428 429 return 0; 430 } 431 432 static void stm32_pmx_set_mode(struct stm32_gpio_bank *bank, 433 int pin, u32 mode, u32 alt) 434 { 435 u32 val; 436 int alt_shift = (pin % 8) * 4; 437 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; 438 unsigned long flags; 439 440 clk_enable(bank->clk); 441 spin_lock_irqsave(&bank->lock, flags); 442 443 val = readl_relaxed(bank->base + alt_offset); 444 val &= ~GENMASK(alt_shift + 3, alt_shift); 445 val |= (alt << alt_shift); 446 writel_relaxed(val, bank->base + alt_offset); 447 448 val = readl_relaxed(bank->base + STM32_GPIO_MODER); 449 val &= ~GENMASK(pin * 2 + 1, pin * 2); 450 val |= mode << (pin * 2); 451 writel_relaxed(val, bank->base + STM32_GPIO_MODER); 452 453 spin_unlock_irqrestore(&bank->lock, flags); 454 clk_disable(bank->clk); 455 } 456 457 static void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, 458 int pin, u32 *mode, u32 *alt) 459 { 460 u32 val; 461 int alt_shift = (pin % 8) * 4; 462 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; 463 unsigned long flags; 464 465 clk_enable(bank->clk); 466 spin_lock_irqsave(&bank->lock, flags); 467 468 val = readl_relaxed(bank->base + alt_offset); 469 val &= GENMASK(alt_shift + 3, alt_shift); 470 *alt = val >> alt_shift; 471 472 val = readl_relaxed(bank->base + STM32_GPIO_MODER); 473 val &= GENMASK(pin * 2 + 1, pin * 2); 474 *mode = val >> (pin * 2); 475 476 spin_unlock_irqrestore(&bank->lock, flags); 477 clk_disable(bank->clk); 478 } 479 480 static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev, 481 unsigned function, 482 unsigned group) 483 { 484 bool ret; 485 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 486 struct stm32_pinctrl_group *g = pctl->groups + group; 487 struct pinctrl_gpio_range *range; 488 struct stm32_gpio_bank *bank; 489 u32 mode, alt; 490 int pin; 491 492 ret = stm32_pctrl_is_function_valid(pctl, g->pin, function); 493 if (!ret) { 494 dev_err(pctl->dev, "invalid function %d on group %d .\n", 495 function, group); 496 return -EINVAL; 497 } 498 499 range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin); 500 bank = gpio_range_to_bank(range); 501 pin = stm32_gpio_pin(g->pin); 502 503 mode = stm32_gpio_get_mode(function); 504 alt = stm32_gpio_get_alt(function); 505 506 stm32_pmx_set_mode(bank, pin, mode, alt); 507 508 return 0; 509 } 510 511 static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 512 struct pinctrl_gpio_range *range, unsigned gpio, 513 bool input) 514 { 515 struct stm32_gpio_bank *bank = gpio_range_to_bank(range); 516 int pin = stm32_gpio_pin(gpio); 517 518 stm32_pmx_set_mode(bank, pin, !input, 0); 519 520 return 0; 521 } 522 523 static const struct pinmux_ops stm32_pmx_ops = { 524 .get_functions_count = stm32_pmx_get_funcs_cnt, 525 .get_function_name = stm32_pmx_get_func_name, 526 .get_function_groups = stm32_pmx_get_func_groups, 527 .set_mux = stm32_pmx_set_mux, 528 .gpio_set_direction = stm32_pmx_gpio_set_direction, 529 }; 530 531 /* Pinconf functions */ 532 533 static void stm32_pconf_set_driving(struct stm32_gpio_bank *bank, 534 unsigned offset, u32 drive) 535 { 536 unsigned long flags; 537 u32 val; 538 539 clk_enable(bank->clk); 540 spin_lock_irqsave(&bank->lock, flags); 541 542 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); 543 val &= ~BIT(offset); 544 val |= drive << offset; 545 writel_relaxed(val, bank->base + STM32_GPIO_TYPER); 546 547 spin_unlock_irqrestore(&bank->lock, flags); 548 clk_disable(bank->clk); 549 } 550 551 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank, 552 unsigned int offset) 553 { 554 unsigned long flags; 555 u32 val; 556 557 clk_enable(bank->clk); 558 spin_lock_irqsave(&bank->lock, flags); 559 560 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); 561 val &= BIT(offset); 562 563 spin_unlock_irqrestore(&bank->lock, flags); 564 clk_disable(bank->clk); 565 566 return (val >> offset); 567 } 568 569 static void stm32_pconf_set_speed(struct stm32_gpio_bank *bank, 570 unsigned offset, u32 speed) 571 { 572 unsigned long flags; 573 u32 val; 574 575 clk_enable(bank->clk); 576 spin_lock_irqsave(&bank->lock, flags); 577 578 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); 579 val &= ~GENMASK(offset * 2 + 1, offset * 2); 580 val |= speed << (offset * 2); 581 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR); 582 583 spin_unlock_irqrestore(&bank->lock, flags); 584 clk_disable(bank->clk); 585 } 586 587 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank, 588 unsigned int offset) 589 { 590 unsigned long flags; 591 u32 val; 592 593 clk_enable(bank->clk); 594 spin_lock_irqsave(&bank->lock, flags); 595 596 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); 597 val &= GENMASK(offset * 2 + 1, offset * 2); 598 599 spin_unlock_irqrestore(&bank->lock, flags); 600 clk_disable(bank->clk); 601 602 return (val >> (offset * 2)); 603 } 604 605 static void stm32_pconf_set_bias(struct stm32_gpio_bank *bank, 606 unsigned offset, u32 bias) 607 { 608 unsigned long flags; 609 u32 val; 610 611 clk_enable(bank->clk); 612 spin_lock_irqsave(&bank->lock, flags); 613 614 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); 615 val &= ~GENMASK(offset * 2 + 1, offset * 2); 616 val |= bias << (offset * 2); 617 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR); 618 619 spin_unlock_irqrestore(&bank->lock, flags); 620 clk_disable(bank->clk); 621 } 622 623 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank, 624 unsigned int offset) 625 { 626 unsigned long flags; 627 u32 val; 628 629 clk_enable(bank->clk); 630 spin_lock_irqsave(&bank->lock, flags); 631 632 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); 633 val &= GENMASK(offset * 2 + 1, offset * 2); 634 635 spin_unlock_irqrestore(&bank->lock, flags); 636 clk_disable(bank->clk); 637 638 return (val >> (offset * 2)); 639 } 640 641 static bool stm32_pconf_input_get(struct stm32_gpio_bank *bank, 642 unsigned int offset) 643 { 644 unsigned long flags; 645 u32 val; 646 647 clk_enable(bank->clk); 648 spin_lock_irqsave(&bank->lock, flags); 649 650 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset)); 651 652 spin_unlock_irqrestore(&bank->lock, flags); 653 clk_disable(bank->clk); 654 655 return val; 656 } 657 658 static bool stm32_pconf_output_get(struct stm32_gpio_bank *bank, 659 unsigned int offset) 660 { 661 unsigned long flags; 662 u32 val; 663 664 clk_enable(bank->clk); 665 spin_lock_irqsave(&bank->lock, flags); 666 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) & BIT(offset)); 667 668 spin_unlock_irqrestore(&bank->lock, flags); 669 clk_disable(bank->clk); 670 671 return val; 672 } 673 674 static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev, 675 unsigned int pin, enum pin_config_param param, 676 enum pin_config_param arg) 677 { 678 struct pinctrl_gpio_range *range; 679 struct stm32_gpio_bank *bank; 680 int offset, ret = 0; 681 682 range = pinctrl_find_gpio_range_from_pin(pctldev, pin); 683 bank = gpio_range_to_bank(range); 684 offset = stm32_gpio_pin(pin); 685 686 switch (param) { 687 case PIN_CONFIG_DRIVE_PUSH_PULL: 688 stm32_pconf_set_driving(bank, offset, 0); 689 break; 690 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 691 stm32_pconf_set_driving(bank, offset, 1); 692 break; 693 case PIN_CONFIG_SLEW_RATE: 694 stm32_pconf_set_speed(bank, offset, arg); 695 break; 696 case PIN_CONFIG_BIAS_DISABLE: 697 stm32_pconf_set_bias(bank, offset, 0); 698 break; 699 case PIN_CONFIG_BIAS_PULL_UP: 700 stm32_pconf_set_bias(bank, offset, 1); 701 break; 702 case PIN_CONFIG_BIAS_PULL_DOWN: 703 stm32_pconf_set_bias(bank, offset, 2); 704 break; 705 case PIN_CONFIG_OUTPUT: 706 __stm32_gpio_set(bank, offset, arg); 707 ret = stm32_pmx_gpio_set_direction(pctldev, NULL, pin, false); 708 break; 709 default: 710 ret = -EINVAL; 711 } 712 713 return ret; 714 } 715 716 static int stm32_pconf_group_get(struct pinctrl_dev *pctldev, 717 unsigned group, 718 unsigned long *config) 719 { 720 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 721 722 *config = pctl->groups[group].config; 723 724 return 0; 725 } 726 727 static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, 728 unsigned long *configs, unsigned num_configs) 729 { 730 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 731 struct stm32_pinctrl_group *g = &pctl->groups[group]; 732 int i, ret; 733 734 for (i = 0; i < num_configs; i++) { 735 ret = stm32_pconf_parse_conf(pctldev, g->pin, 736 pinconf_to_config_param(configs[i]), 737 pinconf_to_config_argument(configs[i])); 738 if (ret < 0) 739 return ret; 740 741 g->config = configs[i]; 742 } 743 744 return 0; 745 } 746 747 static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev, 748 struct seq_file *s, 749 unsigned int pin) 750 { 751 struct pinctrl_gpio_range *range; 752 struct stm32_gpio_bank *bank; 753 int offset; 754 u32 mode, alt, drive, speed, bias; 755 static const char * const modes[] = { 756 "input", "output", "alternate", "analog" }; 757 static const char * const speeds[] = { 758 "low", "medium", "high", "very high" }; 759 static const char * const biasing[] = { 760 "floating", "pull up", "pull down", "" }; 761 bool val; 762 763 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); 764 bank = gpio_range_to_bank(range); 765 offset = stm32_gpio_pin(pin); 766 767 stm32_pmx_get_mode(bank, offset, &mode, &alt); 768 bias = stm32_pconf_get_bias(bank, offset); 769 770 seq_printf(s, "%s ", modes[mode]); 771 772 switch (mode) { 773 /* input */ 774 case 0: 775 val = stm32_pconf_input_get(bank, offset); 776 seq_printf(s, "- %s - %s", 777 val ? "high" : "low", 778 biasing[bias]); 779 break; 780 781 /* output */ 782 case 1: 783 drive = stm32_pconf_get_driving(bank, offset); 784 speed = stm32_pconf_get_speed(bank, offset); 785 val = stm32_pconf_output_get(bank, offset); 786 seq_printf(s, "- %s - %s - %s - %s %s", 787 val ? "high" : "low", 788 drive ? "open drain" : "push pull", 789 biasing[bias], 790 speeds[speed], "speed"); 791 break; 792 793 /* alternate */ 794 case 2: 795 drive = stm32_pconf_get_driving(bank, offset); 796 speed = stm32_pconf_get_speed(bank, offset); 797 seq_printf(s, "%d - %s - %s - %s %s", alt, 798 drive ? "open drain" : "push pull", 799 biasing[bias], 800 speeds[speed], "speed"); 801 break; 802 803 /* analog */ 804 case 3: 805 break; 806 } 807 } 808 809 810 static const struct pinconf_ops stm32_pconf_ops = { 811 .pin_config_group_get = stm32_pconf_group_get, 812 .pin_config_group_set = stm32_pconf_group_set, 813 .pin_config_dbg_show = stm32_pconf_dbg_show, 814 }; 815 816 static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, 817 struct device_node *np) 818 { 819 int bank_nr = pctl->nbanks; 820 struct stm32_gpio_bank *bank = &pctl->banks[bank_nr]; 821 struct pinctrl_gpio_range *range = &bank->range; 822 struct device *dev = pctl->dev; 823 struct resource res; 824 struct reset_control *rstc; 825 int err, npins; 826 827 rstc = of_reset_control_get(np, NULL); 828 if (!IS_ERR(rstc)) 829 reset_control_deassert(rstc); 830 831 if (of_address_to_resource(np, 0, &res)) 832 return -ENODEV; 833 834 bank->base = devm_ioremap_resource(dev, &res); 835 if (IS_ERR(bank->base)) 836 return PTR_ERR(bank->base); 837 838 bank->clk = of_clk_get_by_name(np, NULL); 839 if (IS_ERR(bank->clk)) { 840 dev_err(dev, "failed to get clk (%ld)\n", PTR_ERR(bank->clk)); 841 return PTR_ERR(bank->clk); 842 } 843 844 err = clk_prepare(bank->clk); 845 if (err) { 846 dev_err(dev, "failed to prepare clk (%d)\n", err); 847 return err; 848 } 849 850 npins = pctl->match_data->npins; 851 npins -= bank_nr * STM32_GPIO_PINS_PER_BANK; 852 if (npins < 0) 853 return -EINVAL; 854 else if (npins > STM32_GPIO_PINS_PER_BANK) 855 npins = STM32_GPIO_PINS_PER_BANK; 856 857 bank->gpio_chip = stm32_gpio_template; 858 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; 859 bank->gpio_chip.ngpio = npins; 860 bank->gpio_chip.of_node = np; 861 bank->gpio_chip.parent = dev; 862 spin_lock_init(&bank->lock); 863 864 of_property_read_string(np, "st,bank-name", &range->name); 865 bank->gpio_chip.label = range->name; 866 867 range->id = bank_nr; 868 range->pin_base = range->base = range->id * STM32_GPIO_PINS_PER_BANK; 869 range->npins = bank->gpio_chip.ngpio; 870 range->gc = &bank->gpio_chip; 871 err = gpiochip_add_data(&bank->gpio_chip, bank); 872 if (err) { 873 dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr); 874 return err; 875 } 876 877 dev_info(dev, "%s bank added\n", range->name); 878 return 0; 879 } 880 881 static int stm32_pctrl_build_state(struct platform_device *pdev) 882 { 883 struct stm32_pinctrl *pctl = platform_get_drvdata(pdev); 884 int i; 885 886 pctl->ngroups = pctl->match_data->npins; 887 888 /* Allocate groups */ 889 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups, 890 sizeof(*pctl->groups), GFP_KERNEL); 891 if (!pctl->groups) 892 return -ENOMEM; 893 894 /* We assume that one pin is one group, use pin name as group name. */ 895 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups, 896 sizeof(*pctl->grp_names), GFP_KERNEL); 897 if (!pctl->grp_names) 898 return -ENOMEM; 899 900 for (i = 0; i < pctl->match_data->npins; i++) { 901 const struct stm32_desc_pin *pin = pctl->match_data->pins + i; 902 struct stm32_pinctrl_group *group = pctl->groups + i; 903 904 group->name = pin->pin.name; 905 group->pin = pin->pin.number; 906 907 pctl->grp_names[i] = pin->pin.name; 908 } 909 910 return 0; 911 } 912 913 int stm32_pctl_probe(struct platform_device *pdev) 914 { 915 struct device_node *np = pdev->dev.of_node; 916 struct device_node *child; 917 const struct of_device_id *match; 918 struct device *dev = &pdev->dev; 919 struct stm32_pinctrl *pctl; 920 struct pinctrl_pin_desc *pins; 921 int i, ret, banks = 0; 922 923 if (!np) 924 return -EINVAL; 925 926 match = of_match_device(dev->driver->of_match_table, dev); 927 if (!match || !match->data) 928 return -EINVAL; 929 930 if (!of_find_property(np, "pins-are-numbered", NULL)) { 931 dev_err(dev, "only support pins-are-numbered format\n"); 932 return -EINVAL; 933 } 934 935 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL); 936 if (!pctl) 937 return -ENOMEM; 938 939 platform_set_drvdata(pdev, pctl); 940 941 pctl->dev = dev; 942 pctl->match_data = match->data; 943 ret = stm32_pctrl_build_state(pdev); 944 if (ret) { 945 dev_err(dev, "build state failed: %d\n", ret); 946 return -EINVAL; 947 } 948 949 for_each_child_of_node(np, child) 950 if (of_property_read_bool(child, "gpio-controller")) 951 banks++; 952 953 if (!banks) { 954 dev_err(dev, "at least one GPIO bank is required\n"); 955 return -EINVAL; 956 } 957 958 pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks), 959 GFP_KERNEL); 960 if (!pctl->banks) 961 return -ENOMEM; 962 963 for_each_child_of_node(np, child) { 964 if (of_property_read_bool(child, "gpio-controller")) { 965 ret = stm32_gpiolib_register_bank(pctl, child); 966 if (ret) 967 return ret; 968 969 pctl->nbanks++; 970 } 971 } 972 973 pins = devm_kcalloc(&pdev->dev, pctl->match_data->npins, sizeof(*pins), 974 GFP_KERNEL); 975 if (!pins) 976 return -ENOMEM; 977 978 for (i = 0; i < pctl->match_data->npins; i++) 979 pins[i] = pctl->match_data->pins[i].pin; 980 981 pctl->pctl_desc.name = dev_name(&pdev->dev); 982 pctl->pctl_desc.owner = THIS_MODULE; 983 pctl->pctl_desc.pins = pins; 984 pctl->pctl_desc.npins = pctl->match_data->npins; 985 pctl->pctl_desc.confops = &stm32_pconf_ops; 986 pctl->pctl_desc.pctlops = &stm32_pctrl_ops; 987 pctl->pctl_desc.pmxops = &stm32_pmx_ops; 988 pctl->dev = &pdev->dev; 989 990 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc, 991 pctl); 992 if (IS_ERR(pctl->pctl_dev)) { 993 dev_err(&pdev->dev, "Failed pinctrl registration\n"); 994 return PTR_ERR(pctl->pctl_dev); 995 } 996 997 for (i = 0; i < pctl->nbanks; i++) 998 pinctrl_add_gpio_range(pctl->pctl_dev, &pctl->banks[i].range); 999 1000 dev_info(dev, "Pinctrl STM32 initialized\n"); 1001 1002 return 0; 1003 } 1004 1005