1 /* 2 * Copyright (C) Maxime Coquelin 2015 3 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> 4 * License terms: GNU General Public License (GPL), version 2 5 * 6 * Heavily based on Mediatek's pinctrl driver 7 */ 8 #include <linux/clk.h> 9 #include <linux/gpio/driver.h> 10 #include <linux/io.h> 11 #include <linux/irq.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/of_device.h> 17 #include <linux/of_irq.h> 18 #include <linux/pinctrl/consumer.h> 19 #include <linux/pinctrl/machine.h> 20 #include <linux/pinctrl/pinconf.h> 21 #include <linux/pinctrl/pinconf-generic.h> 22 #include <linux/pinctrl/pinctrl.h> 23 #include <linux/pinctrl/pinmux.h> 24 #include <linux/platform_device.h> 25 #include <linux/regmap.h> 26 #include <linux/reset.h> 27 #include <linux/slab.h> 28 29 #include "../core.h" 30 #include "../pinconf.h" 31 #include "../pinctrl-utils.h" 32 #include "pinctrl-stm32.h" 33 34 #define STM32_GPIO_MODER 0x00 35 #define STM32_GPIO_TYPER 0x04 36 #define STM32_GPIO_SPEEDR 0x08 37 #define STM32_GPIO_PUPDR 0x0c 38 #define STM32_GPIO_IDR 0x10 39 #define STM32_GPIO_ODR 0x14 40 #define STM32_GPIO_BSRR 0x18 41 #define STM32_GPIO_LCKR 0x1c 42 #define STM32_GPIO_AFRL 0x20 43 #define STM32_GPIO_AFRH 0x24 44 45 #define STM32_GPIO_PINS_PER_BANK 16 46 #define STM32_GPIO_IRQ_LINE 16 47 48 #define gpio_range_to_bank(chip) \ 49 container_of(chip, struct stm32_gpio_bank, range) 50 51 static const char * const stm32_gpio_functions[] = { 52 "gpio", "af0", "af1", 53 "af2", "af3", "af4", 54 "af5", "af6", "af7", 55 "af8", "af9", "af10", 56 "af11", "af12", "af13", 57 "af14", "af15", "analog", 58 }; 59 60 struct stm32_pinctrl_group { 61 const char *name; 62 unsigned long config; 63 unsigned pin; 64 }; 65 66 struct stm32_gpio_bank { 67 void __iomem *base; 68 struct clk *clk; 69 spinlock_t lock; 70 struct gpio_chip gpio_chip; 71 struct pinctrl_gpio_range range; 72 struct fwnode_handle *fwnode; 73 struct irq_domain *domain; 74 }; 75 76 struct stm32_pinctrl { 77 struct device *dev; 78 struct pinctrl_dev *pctl_dev; 79 struct pinctrl_desc pctl_desc; 80 struct stm32_pinctrl_group *groups; 81 unsigned ngroups; 82 const char **grp_names; 83 struct stm32_gpio_bank *banks; 84 unsigned nbanks; 85 const struct stm32_pinctrl_match_data *match_data; 86 struct irq_domain *domain; 87 struct regmap *regmap; 88 struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK]; 89 }; 90 91 static inline int stm32_gpio_pin(int gpio) 92 { 93 return gpio % STM32_GPIO_PINS_PER_BANK; 94 } 95 96 static inline u32 stm32_gpio_get_mode(u32 function) 97 { 98 switch (function) { 99 case STM32_PIN_GPIO: 100 return 0; 101 case STM32_PIN_AF(0) ... STM32_PIN_AF(15): 102 return 2; 103 case STM32_PIN_ANALOG: 104 return 3; 105 } 106 107 return 0; 108 } 109 110 static inline u32 stm32_gpio_get_alt(u32 function) 111 { 112 switch (function) { 113 case STM32_PIN_GPIO: 114 return 0; 115 case STM32_PIN_AF(0) ... STM32_PIN_AF(15): 116 return function - 1; 117 case STM32_PIN_ANALOG: 118 return 0; 119 } 120 121 return 0; 122 } 123 124 /* GPIO functions */ 125 126 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank, 127 unsigned offset, int value) 128 { 129 if (!value) 130 offset += STM32_GPIO_PINS_PER_BANK; 131 132 clk_enable(bank->clk); 133 134 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR); 135 136 clk_disable(bank->clk); 137 } 138 139 static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset) 140 { 141 return pinctrl_request_gpio(chip->base + offset); 142 } 143 144 static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset) 145 { 146 pinctrl_free_gpio(chip->base + offset); 147 } 148 149 static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset) 150 { 151 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 152 int ret; 153 154 clk_enable(bank->clk); 155 156 ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset)); 157 158 clk_disable(bank->clk); 159 160 return ret; 161 } 162 163 static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 164 { 165 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 166 167 __stm32_gpio_set(bank, offset, value); 168 } 169 170 static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 171 { 172 return pinctrl_gpio_direction_input(chip->base + offset); 173 } 174 175 static int stm32_gpio_direction_output(struct gpio_chip *chip, 176 unsigned offset, int value) 177 { 178 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 179 180 __stm32_gpio_set(bank, offset, value); 181 pinctrl_gpio_direction_output(chip->base + offset); 182 183 return 0; 184 } 185 186 187 static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) 188 { 189 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 190 struct irq_fwspec fwspec; 191 192 fwspec.fwnode = bank->fwnode; 193 fwspec.param_count = 2; 194 fwspec.param[0] = offset; 195 fwspec.param[1] = IRQ_TYPE_NONE; 196 197 return irq_create_fwspec_mapping(&fwspec); 198 } 199 200 static const struct gpio_chip stm32_gpio_template = { 201 .request = stm32_gpio_request, 202 .free = stm32_gpio_free, 203 .get = stm32_gpio_get, 204 .set = stm32_gpio_set, 205 .direction_input = stm32_gpio_direction_input, 206 .direction_output = stm32_gpio_direction_output, 207 .to_irq = stm32_gpio_to_irq, 208 }; 209 210 static struct irq_chip stm32_gpio_irq_chip = { 211 .name = "stm32gpio", 212 .irq_eoi = irq_chip_eoi_parent, 213 .irq_mask = irq_chip_mask_parent, 214 .irq_unmask = irq_chip_unmask_parent, 215 .irq_set_type = irq_chip_set_type_parent, 216 }; 217 218 static int stm32_gpio_domain_translate(struct irq_domain *d, 219 struct irq_fwspec *fwspec, 220 unsigned long *hwirq, 221 unsigned int *type) 222 { 223 if ((fwspec->param_count != 2) || 224 (fwspec->param[0] >= STM32_GPIO_IRQ_LINE)) 225 return -EINVAL; 226 227 *hwirq = fwspec->param[0]; 228 *type = fwspec->param[1]; 229 return 0; 230 } 231 232 static void stm32_gpio_domain_activate(struct irq_domain *d, 233 struct irq_data *irq_data) 234 { 235 struct stm32_gpio_bank *bank = d->host_data; 236 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 237 238 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->range.id); 239 gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq); 240 } 241 242 static void stm32_gpio_domain_deactivate(struct irq_domain *d, 243 struct irq_data *irq_data) 244 { 245 struct stm32_gpio_bank *bank = d->host_data; 246 247 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq); 248 } 249 250 static int stm32_gpio_domain_alloc(struct irq_domain *d, 251 unsigned int virq, 252 unsigned int nr_irqs, void *data) 253 { 254 struct stm32_gpio_bank *bank = d->host_data; 255 struct irq_fwspec *fwspec = data; 256 struct irq_fwspec parent_fwspec; 257 irq_hw_number_t hwirq; 258 259 hwirq = fwspec->param[0]; 260 parent_fwspec.fwnode = d->parent->fwnode; 261 parent_fwspec.param_count = 2; 262 parent_fwspec.param[0] = fwspec->param[0]; 263 parent_fwspec.param[1] = fwspec->param[1]; 264 265 irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip, 266 bank); 267 268 return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec); 269 } 270 271 static const struct irq_domain_ops stm32_gpio_domain_ops = { 272 .translate = stm32_gpio_domain_translate, 273 .alloc = stm32_gpio_domain_alloc, 274 .free = irq_domain_free_irqs_common, 275 .activate = stm32_gpio_domain_activate, 276 .deactivate = stm32_gpio_domain_deactivate, 277 }; 278 279 /* Pinctrl functions */ 280 static struct stm32_pinctrl_group * 281 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin) 282 { 283 int i; 284 285 for (i = 0; i < pctl->ngroups; i++) { 286 struct stm32_pinctrl_group *grp = pctl->groups + i; 287 288 if (grp->pin == pin) 289 return grp; 290 } 291 292 return NULL; 293 } 294 295 static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl, 296 u32 pin_num, u32 fnum) 297 { 298 int i; 299 300 for (i = 0; i < pctl->match_data->npins; i++) { 301 const struct stm32_desc_pin *pin = pctl->match_data->pins + i; 302 const struct stm32_desc_function *func = pin->functions; 303 304 if (pin->pin.number != pin_num) 305 continue; 306 307 while (func && func->name) { 308 if (func->num == fnum) 309 return true; 310 func++; 311 } 312 313 break; 314 } 315 316 return false; 317 } 318 319 static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl, 320 u32 pin, u32 fnum, struct stm32_pinctrl_group *grp, 321 struct pinctrl_map **map, unsigned *reserved_maps, 322 unsigned *num_maps) 323 { 324 if (*num_maps == *reserved_maps) 325 return -ENOSPC; 326 327 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; 328 (*map)[*num_maps].data.mux.group = grp->name; 329 330 if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) { 331 dev_err(pctl->dev, "invalid function %d on pin %d .\n", 332 fnum, pin); 333 return -EINVAL; 334 } 335 336 (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum]; 337 (*num_maps)++; 338 339 return 0; 340 } 341 342 static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, 343 struct device_node *node, 344 struct pinctrl_map **map, 345 unsigned *reserved_maps, 346 unsigned *num_maps) 347 { 348 struct stm32_pinctrl *pctl; 349 struct stm32_pinctrl_group *grp; 350 struct property *pins; 351 u32 pinfunc, pin, func; 352 unsigned long *configs; 353 unsigned int num_configs; 354 bool has_config = 0; 355 unsigned reserve = 0; 356 int num_pins, num_funcs, maps_per_pin, i, err; 357 358 pctl = pinctrl_dev_get_drvdata(pctldev); 359 360 pins = of_find_property(node, "pinmux", NULL); 361 if (!pins) { 362 dev_err(pctl->dev, "missing pins property in node %s .\n", 363 node->name); 364 return -EINVAL; 365 } 366 367 err = pinconf_generic_parse_dt_config(node, pctldev, &configs, 368 &num_configs); 369 if (err) 370 return err; 371 372 if (num_configs) 373 has_config = 1; 374 375 num_pins = pins->length / sizeof(u32); 376 num_funcs = num_pins; 377 maps_per_pin = 0; 378 if (num_funcs) 379 maps_per_pin++; 380 if (has_config && num_pins >= 1) 381 maps_per_pin++; 382 383 if (!num_pins || !maps_per_pin) 384 return -EINVAL; 385 386 reserve = num_pins * maps_per_pin; 387 388 err = pinctrl_utils_reserve_map(pctldev, map, 389 reserved_maps, num_maps, reserve); 390 if (err) 391 return err; 392 393 for (i = 0; i < num_pins; i++) { 394 err = of_property_read_u32_index(node, "pinmux", 395 i, &pinfunc); 396 if (err) 397 return err; 398 399 pin = STM32_GET_PIN_NO(pinfunc); 400 func = STM32_GET_PIN_FUNC(pinfunc); 401 402 if (pin >= pctl->match_data->npins) { 403 dev_err(pctl->dev, "invalid pin number.\n"); 404 return -EINVAL; 405 } 406 407 if (!stm32_pctrl_is_function_valid(pctl, pin, func)) { 408 dev_err(pctl->dev, "invalid function.\n"); 409 return -EINVAL; 410 } 411 412 grp = stm32_pctrl_find_group_by_pin(pctl, pin); 413 if (!grp) { 414 dev_err(pctl->dev, "unable to match pin %d to group\n", 415 pin); 416 return -EINVAL; 417 } 418 419 err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map, 420 reserved_maps, num_maps); 421 if (err) 422 return err; 423 424 if (has_config) { 425 err = pinctrl_utils_add_map_configs(pctldev, map, 426 reserved_maps, num_maps, grp->name, 427 configs, num_configs, 428 PIN_MAP_TYPE_CONFIGS_GROUP); 429 if (err) 430 return err; 431 } 432 } 433 434 return 0; 435 } 436 437 static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 438 struct device_node *np_config, 439 struct pinctrl_map **map, unsigned *num_maps) 440 { 441 struct device_node *np; 442 unsigned reserved_maps; 443 int ret; 444 445 *map = NULL; 446 *num_maps = 0; 447 reserved_maps = 0; 448 449 for_each_child_of_node(np_config, np) { 450 ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map, 451 &reserved_maps, num_maps); 452 if (ret < 0) { 453 pinctrl_utils_free_map(pctldev, *map, *num_maps); 454 return ret; 455 } 456 } 457 458 return 0; 459 } 460 461 static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev) 462 { 463 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 464 465 return pctl->ngroups; 466 } 467 468 static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev, 469 unsigned group) 470 { 471 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 472 473 return pctl->groups[group].name; 474 } 475 476 static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev, 477 unsigned group, 478 const unsigned **pins, 479 unsigned *num_pins) 480 { 481 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 482 483 *pins = (unsigned *)&pctl->groups[group].pin; 484 *num_pins = 1; 485 486 return 0; 487 } 488 489 static const struct pinctrl_ops stm32_pctrl_ops = { 490 .dt_node_to_map = stm32_pctrl_dt_node_to_map, 491 .dt_free_map = pinctrl_utils_free_map, 492 .get_groups_count = stm32_pctrl_get_groups_count, 493 .get_group_name = stm32_pctrl_get_group_name, 494 .get_group_pins = stm32_pctrl_get_group_pins, 495 }; 496 497 498 /* Pinmux functions */ 499 500 static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 501 { 502 return ARRAY_SIZE(stm32_gpio_functions); 503 } 504 505 static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev, 506 unsigned selector) 507 { 508 return stm32_gpio_functions[selector]; 509 } 510 511 static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev, 512 unsigned function, 513 const char * const **groups, 514 unsigned * const num_groups) 515 { 516 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 517 518 *groups = pctl->grp_names; 519 *num_groups = pctl->ngroups; 520 521 return 0; 522 } 523 524 static void stm32_pmx_set_mode(struct stm32_gpio_bank *bank, 525 int pin, u32 mode, u32 alt) 526 { 527 u32 val; 528 int alt_shift = (pin % 8) * 4; 529 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; 530 unsigned long flags; 531 532 clk_enable(bank->clk); 533 spin_lock_irqsave(&bank->lock, flags); 534 535 val = readl_relaxed(bank->base + alt_offset); 536 val &= ~GENMASK(alt_shift + 3, alt_shift); 537 val |= (alt << alt_shift); 538 writel_relaxed(val, bank->base + alt_offset); 539 540 val = readl_relaxed(bank->base + STM32_GPIO_MODER); 541 val &= ~GENMASK(pin * 2 + 1, pin * 2); 542 val |= mode << (pin * 2); 543 writel_relaxed(val, bank->base + STM32_GPIO_MODER); 544 545 spin_unlock_irqrestore(&bank->lock, flags); 546 clk_disable(bank->clk); 547 } 548 549 static void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, 550 int pin, u32 *mode, u32 *alt) 551 { 552 u32 val; 553 int alt_shift = (pin % 8) * 4; 554 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; 555 unsigned long flags; 556 557 clk_enable(bank->clk); 558 spin_lock_irqsave(&bank->lock, flags); 559 560 val = readl_relaxed(bank->base + alt_offset); 561 val &= GENMASK(alt_shift + 3, alt_shift); 562 *alt = val >> alt_shift; 563 564 val = readl_relaxed(bank->base + STM32_GPIO_MODER); 565 val &= GENMASK(pin * 2 + 1, pin * 2); 566 *mode = val >> (pin * 2); 567 568 spin_unlock_irqrestore(&bank->lock, flags); 569 clk_disable(bank->clk); 570 } 571 572 static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev, 573 unsigned function, 574 unsigned group) 575 { 576 bool ret; 577 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 578 struct stm32_pinctrl_group *g = pctl->groups + group; 579 struct pinctrl_gpio_range *range; 580 struct stm32_gpio_bank *bank; 581 u32 mode, alt; 582 int pin; 583 584 ret = stm32_pctrl_is_function_valid(pctl, g->pin, function); 585 if (!ret) { 586 dev_err(pctl->dev, "invalid function %d on group %d .\n", 587 function, group); 588 return -EINVAL; 589 } 590 591 range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin); 592 bank = gpio_range_to_bank(range); 593 pin = stm32_gpio_pin(g->pin); 594 595 mode = stm32_gpio_get_mode(function); 596 alt = stm32_gpio_get_alt(function); 597 598 stm32_pmx_set_mode(bank, pin, mode, alt); 599 600 return 0; 601 } 602 603 static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 604 struct pinctrl_gpio_range *range, unsigned gpio, 605 bool input) 606 { 607 struct stm32_gpio_bank *bank = gpio_range_to_bank(range); 608 int pin = stm32_gpio_pin(gpio); 609 610 stm32_pmx_set_mode(bank, pin, !input, 0); 611 612 return 0; 613 } 614 615 static const struct pinmux_ops stm32_pmx_ops = { 616 .get_functions_count = stm32_pmx_get_funcs_cnt, 617 .get_function_name = stm32_pmx_get_func_name, 618 .get_function_groups = stm32_pmx_get_func_groups, 619 .set_mux = stm32_pmx_set_mux, 620 .gpio_set_direction = stm32_pmx_gpio_set_direction, 621 .strict = true, 622 }; 623 624 /* Pinconf functions */ 625 626 static void stm32_pconf_set_driving(struct stm32_gpio_bank *bank, 627 unsigned offset, u32 drive) 628 { 629 unsigned long flags; 630 u32 val; 631 632 clk_enable(bank->clk); 633 spin_lock_irqsave(&bank->lock, flags); 634 635 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); 636 val &= ~BIT(offset); 637 val |= drive << offset; 638 writel_relaxed(val, bank->base + STM32_GPIO_TYPER); 639 640 spin_unlock_irqrestore(&bank->lock, flags); 641 clk_disable(bank->clk); 642 } 643 644 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank, 645 unsigned int offset) 646 { 647 unsigned long flags; 648 u32 val; 649 650 clk_enable(bank->clk); 651 spin_lock_irqsave(&bank->lock, flags); 652 653 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); 654 val &= BIT(offset); 655 656 spin_unlock_irqrestore(&bank->lock, flags); 657 clk_disable(bank->clk); 658 659 return (val >> offset); 660 } 661 662 static void stm32_pconf_set_speed(struct stm32_gpio_bank *bank, 663 unsigned offset, u32 speed) 664 { 665 unsigned long flags; 666 u32 val; 667 668 clk_enable(bank->clk); 669 spin_lock_irqsave(&bank->lock, flags); 670 671 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); 672 val &= ~GENMASK(offset * 2 + 1, offset * 2); 673 val |= speed << (offset * 2); 674 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR); 675 676 spin_unlock_irqrestore(&bank->lock, flags); 677 clk_disable(bank->clk); 678 } 679 680 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank, 681 unsigned int offset) 682 { 683 unsigned long flags; 684 u32 val; 685 686 clk_enable(bank->clk); 687 spin_lock_irqsave(&bank->lock, flags); 688 689 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); 690 val &= GENMASK(offset * 2 + 1, offset * 2); 691 692 spin_unlock_irqrestore(&bank->lock, flags); 693 clk_disable(bank->clk); 694 695 return (val >> (offset * 2)); 696 } 697 698 static void stm32_pconf_set_bias(struct stm32_gpio_bank *bank, 699 unsigned offset, u32 bias) 700 { 701 unsigned long flags; 702 u32 val; 703 704 clk_enable(bank->clk); 705 spin_lock_irqsave(&bank->lock, flags); 706 707 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); 708 val &= ~GENMASK(offset * 2 + 1, offset * 2); 709 val |= bias << (offset * 2); 710 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR); 711 712 spin_unlock_irqrestore(&bank->lock, flags); 713 clk_disable(bank->clk); 714 } 715 716 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank, 717 unsigned int offset) 718 { 719 unsigned long flags; 720 u32 val; 721 722 clk_enable(bank->clk); 723 spin_lock_irqsave(&bank->lock, flags); 724 725 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); 726 val &= GENMASK(offset * 2 + 1, offset * 2); 727 728 spin_unlock_irqrestore(&bank->lock, flags); 729 clk_disable(bank->clk); 730 731 return (val >> (offset * 2)); 732 } 733 734 static bool stm32_pconf_get(struct stm32_gpio_bank *bank, 735 unsigned int offset, bool dir) 736 { 737 unsigned long flags; 738 u32 val; 739 740 clk_enable(bank->clk); 741 spin_lock_irqsave(&bank->lock, flags); 742 743 if (dir) 744 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & 745 BIT(offset)); 746 else 747 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) & 748 BIT(offset)); 749 750 spin_unlock_irqrestore(&bank->lock, flags); 751 clk_disable(bank->clk); 752 753 return val; 754 } 755 756 static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev, 757 unsigned int pin, enum pin_config_param param, 758 enum pin_config_param arg) 759 { 760 struct pinctrl_gpio_range *range; 761 struct stm32_gpio_bank *bank; 762 int offset, ret = 0; 763 764 range = pinctrl_find_gpio_range_from_pin(pctldev, pin); 765 bank = gpio_range_to_bank(range); 766 offset = stm32_gpio_pin(pin); 767 768 switch (param) { 769 case PIN_CONFIG_DRIVE_PUSH_PULL: 770 stm32_pconf_set_driving(bank, offset, 0); 771 break; 772 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 773 stm32_pconf_set_driving(bank, offset, 1); 774 break; 775 case PIN_CONFIG_SLEW_RATE: 776 stm32_pconf_set_speed(bank, offset, arg); 777 break; 778 case PIN_CONFIG_BIAS_DISABLE: 779 stm32_pconf_set_bias(bank, offset, 0); 780 break; 781 case PIN_CONFIG_BIAS_PULL_UP: 782 stm32_pconf_set_bias(bank, offset, 1); 783 break; 784 case PIN_CONFIG_BIAS_PULL_DOWN: 785 stm32_pconf_set_bias(bank, offset, 2); 786 break; 787 case PIN_CONFIG_OUTPUT: 788 __stm32_gpio_set(bank, offset, arg); 789 ret = stm32_pmx_gpio_set_direction(pctldev, NULL, pin, false); 790 break; 791 default: 792 ret = -EINVAL; 793 } 794 795 return ret; 796 } 797 798 static int stm32_pconf_group_get(struct pinctrl_dev *pctldev, 799 unsigned group, 800 unsigned long *config) 801 { 802 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 803 804 *config = pctl->groups[group].config; 805 806 return 0; 807 } 808 809 static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, 810 unsigned long *configs, unsigned num_configs) 811 { 812 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 813 struct stm32_pinctrl_group *g = &pctl->groups[group]; 814 int i, ret; 815 816 for (i = 0; i < num_configs; i++) { 817 ret = stm32_pconf_parse_conf(pctldev, g->pin, 818 pinconf_to_config_param(configs[i]), 819 pinconf_to_config_argument(configs[i])); 820 if (ret < 0) 821 return ret; 822 823 g->config = configs[i]; 824 } 825 826 return 0; 827 } 828 829 static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev, 830 struct seq_file *s, 831 unsigned int pin) 832 { 833 struct pinctrl_gpio_range *range; 834 struct stm32_gpio_bank *bank; 835 int offset; 836 u32 mode, alt, drive, speed, bias; 837 static const char * const modes[] = { 838 "input", "output", "alternate", "analog" }; 839 static const char * const speeds[] = { 840 "low", "medium", "high", "very high" }; 841 static const char * const biasing[] = { 842 "floating", "pull up", "pull down", "" }; 843 bool val; 844 845 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); 846 bank = gpio_range_to_bank(range); 847 offset = stm32_gpio_pin(pin); 848 849 stm32_pmx_get_mode(bank, offset, &mode, &alt); 850 bias = stm32_pconf_get_bias(bank, offset); 851 852 seq_printf(s, "%s ", modes[mode]); 853 854 switch (mode) { 855 /* input */ 856 case 0: 857 val = stm32_pconf_get(bank, offset, true); 858 seq_printf(s, "- %s - %s", 859 val ? "high" : "low", 860 biasing[bias]); 861 break; 862 863 /* output */ 864 case 1: 865 drive = stm32_pconf_get_driving(bank, offset); 866 speed = stm32_pconf_get_speed(bank, offset); 867 val = stm32_pconf_get(bank, offset, false); 868 seq_printf(s, "- %s - %s - %s - %s %s", 869 val ? "high" : "low", 870 drive ? "open drain" : "push pull", 871 biasing[bias], 872 speeds[speed], "speed"); 873 break; 874 875 /* alternate */ 876 case 2: 877 drive = stm32_pconf_get_driving(bank, offset); 878 speed = stm32_pconf_get_speed(bank, offset); 879 seq_printf(s, "%d - %s - %s - %s %s", alt, 880 drive ? "open drain" : "push pull", 881 biasing[bias], 882 speeds[speed], "speed"); 883 break; 884 885 /* analog */ 886 case 3: 887 break; 888 } 889 } 890 891 892 static const struct pinconf_ops stm32_pconf_ops = { 893 .pin_config_group_get = stm32_pconf_group_get, 894 .pin_config_group_set = stm32_pconf_group_set, 895 .pin_config_dbg_show = stm32_pconf_dbg_show, 896 }; 897 898 static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, 899 struct device_node *np) 900 { 901 int bank_nr = pctl->nbanks; 902 struct stm32_gpio_bank *bank = &pctl->banks[bank_nr]; 903 struct pinctrl_gpio_range *range = &bank->range; 904 struct device *dev = pctl->dev; 905 struct resource res; 906 struct reset_control *rstc; 907 int err, npins; 908 909 rstc = of_reset_control_get(np, NULL); 910 if (!IS_ERR(rstc)) 911 reset_control_deassert(rstc); 912 913 if (of_address_to_resource(np, 0, &res)) 914 return -ENODEV; 915 916 bank->base = devm_ioremap_resource(dev, &res); 917 if (IS_ERR(bank->base)) 918 return PTR_ERR(bank->base); 919 920 bank->clk = of_clk_get_by_name(np, NULL); 921 if (IS_ERR(bank->clk)) { 922 dev_err(dev, "failed to get clk (%ld)\n", PTR_ERR(bank->clk)); 923 return PTR_ERR(bank->clk); 924 } 925 926 err = clk_prepare(bank->clk); 927 if (err) { 928 dev_err(dev, "failed to prepare clk (%d)\n", err); 929 return err; 930 } 931 932 npins = pctl->match_data->npins; 933 npins -= bank_nr * STM32_GPIO_PINS_PER_BANK; 934 if (npins < 0) 935 return -EINVAL; 936 else if (npins > STM32_GPIO_PINS_PER_BANK) 937 npins = STM32_GPIO_PINS_PER_BANK; 938 939 bank->gpio_chip = stm32_gpio_template; 940 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; 941 bank->gpio_chip.ngpio = npins; 942 bank->gpio_chip.of_node = np; 943 bank->gpio_chip.parent = dev; 944 spin_lock_init(&bank->lock); 945 946 of_property_read_string(np, "st,bank-name", &range->name); 947 bank->gpio_chip.label = range->name; 948 949 range->id = bank_nr; 950 range->pin_base = range->base = range->id * STM32_GPIO_PINS_PER_BANK; 951 range->npins = bank->gpio_chip.ngpio; 952 range->gc = &bank->gpio_chip; 953 954 /* create irq hierarchical domain */ 955 bank->fwnode = of_node_to_fwnode(np); 956 957 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, 958 STM32_GPIO_IRQ_LINE, bank->fwnode, 959 &stm32_gpio_domain_ops, bank); 960 961 if (!bank->domain) 962 return -ENODEV; 963 964 err = gpiochip_add_data(&bank->gpio_chip, bank); 965 if (err) { 966 dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr); 967 return err; 968 } 969 970 dev_info(dev, "%s bank added\n", range->name); 971 return 0; 972 } 973 974 static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev, 975 struct stm32_pinctrl *pctl) 976 { 977 struct device_node *np = pdev->dev.of_node, *parent; 978 struct device *dev = &pdev->dev; 979 struct regmap *rm; 980 int offset, ret, i; 981 982 parent = of_irq_find_parent(np); 983 if (!parent) 984 return -ENXIO; 985 986 pctl->domain = irq_find_host(parent); 987 if (!pctl->domain) 988 return -ENXIO; 989 990 pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); 991 if (IS_ERR(pctl->regmap)) 992 return PTR_ERR(pctl->regmap); 993 994 rm = pctl->regmap; 995 996 ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset); 997 if (ret) 998 return ret; 999 1000 for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) { 1001 struct reg_field mux; 1002 1003 mux.reg = offset + (i / 4) * 4; 1004 mux.lsb = (i % 4) * 4; 1005 mux.msb = mux.lsb + 3; 1006 1007 pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux); 1008 if (IS_ERR(pctl->irqmux[i])) 1009 return PTR_ERR(pctl->irqmux[i]); 1010 } 1011 1012 return 0; 1013 } 1014 1015 static int stm32_pctrl_build_state(struct platform_device *pdev) 1016 { 1017 struct stm32_pinctrl *pctl = platform_get_drvdata(pdev); 1018 int i; 1019 1020 pctl->ngroups = pctl->match_data->npins; 1021 1022 /* Allocate groups */ 1023 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups, 1024 sizeof(*pctl->groups), GFP_KERNEL); 1025 if (!pctl->groups) 1026 return -ENOMEM; 1027 1028 /* We assume that one pin is one group, use pin name as group name. */ 1029 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups, 1030 sizeof(*pctl->grp_names), GFP_KERNEL); 1031 if (!pctl->grp_names) 1032 return -ENOMEM; 1033 1034 for (i = 0; i < pctl->match_data->npins; i++) { 1035 const struct stm32_desc_pin *pin = pctl->match_data->pins + i; 1036 struct stm32_pinctrl_group *group = pctl->groups + i; 1037 1038 group->name = pin->pin.name; 1039 group->pin = pin->pin.number; 1040 1041 pctl->grp_names[i] = pin->pin.name; 1042 } 1043 1044 return 0; 1045 } 1046 1047 int stm32_pctl_probe(struct platform_device *pdev) 1048 { 1049 struct device_node *np = pdev->dev.of_node; 1050 struct device_node *child; 1051 const struct of_device_id *match; 1052 struct device *dev = &pdev->dev; 1053 struct stm32_pinctrl *pctl; 1054 struct pinctrl_pin_desc *pins; 1055 int i, ret, banks = 0; 1056 1057 if (!np) 1058 return -EINVAL; 1059 1060 match = of_match_device(dev->driver->of_match_table, dev); 1061 if (!match || !match->data) 1062 return -EINVAL; 1063 1064 if (!of_find_property(np, "pins-are-numbered", NULL)) { 1065 dev_err(dev, "only support pins-are-numbered format\n"); 1066 return -EINVAL; 1067 } 1068 1069 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL); 1070 if (!pctl) 1071 return -ENOMEM; 1072 1073 platform_set_drvdata(pdev, pctl); 1074 1075 pctl->dev = dev; 1076 pctl->match_data = match->data; 1077 ret = stm32_pctrl_build_state(pdev); 1078 if (ret) { 1079 dev_err(dev, "build state failed: %d\n", ret); 1080 return -EINVAL; 1081 } 1082 1083 if (of_find_property(np, "interrupt-parent", NULL)) { 1084 ret = stm32_pctrl_dt_setup_irq(pdev, pctl); 1085 if (ret) 1086 return ret; 1087 } 1088 1089 for_each_child_of_node(np, child) 1090 if (of_property_read_bool(child, "gpio-controller")) 1091 banks++; 1092 1093 if (!banks) { 1094 dev_err(dev, "at least one GPIO bank is required\n"); 1095 return -EINVAL; 1096 } 1097 1098 pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks), 1099 GFP_KERNEL); 1100 if (!pctl->banks) 1101 return -ENOMEM; 1102 1103 for_each_child_of_node(np, child) { 1104 if (of_property_read_bool(child, "gpio-controller")) { 1105 ret = stm32_gpiolib_register_bank(pctl, child); 1106 if (ret) 1107 return ret; 1108 1109 pctl->nbanks++; 1110 } 1111 } 1112 1113 pins = devm_kcalloc(&pdev->dev, pctl->match_data->npins, sizeof(*pins), 1114 GFP_KERNEL); 1115 if (!pins) 1116 return -ENOMEM; 1117 1118 for (i = 0; i < pctl->match_data->npins; i++) 1119 pins[i] = pctl->match_data->pins[i].pin; 1120 1121 pctl->pctl_desc.name = dev_name(&pdev->dev); 1122 pctl->pctl_desc.owner = THIS_MODULE; 1123 pctl->pctl_desc.pins = pins; 1124 pctl->pctl_desc.npins = pctl->match_data->npins; 1125 pctl->pctl_desc.confops = &stm32_pconf_ops; 1126 pctl->pctl_desc.pctlops = &stm32_pctrl_ops; 1127 pctl->pctl_desc.pmxops = &stm32_pmx_ops; 1128 pctl->dev = &pdev->dev; 1129 1130 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc, 1131 pctl); 1132 if (IS_ERR(pctl->pctl_dev)) { 1133 dev_err(&pdev->dev, "Failed pinctrl registration\n"); 1134 return PTR_ERR(pctl->pctl_dev); 1135 } 1136 1137 for (i = 0; i < pctl->nbanks; i++) 1138 pinctrl_add_gpio_range(pctl->pctl_dev, &pctl->banks[i].range); 1139 1140 dev_info(dev, "Pinctrl STM32 initialized\n"); 1141 1142 return 0; 1143 } 1144 1145