1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) Maxime Coquelin 2015
4  * Copyright (C) STMicroelectronics 2017
5  * Author:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
6  *
7  * Heavily based on Mediatek's pinctrl driver
8  */
9 #include <linux/clk.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/hwspinlock.h>
12 #include <linux/io.h>
13 #include <linux/irq.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/of_address.h>
18 #include <linux/of_device.h>
19 #include <linux/of_irq.h>
20 #include <linux/pinctrl/consumer.h>
21 #include <linux/pinctrl/machine.h>
22 #include <linux/pinctrl/pinconf.h>
23 #include <linux/pinctrl/pinconf-generic.h>
24 #include <linux/pinctrl/pinctrl.h>
25 #include <linux/pinctrl/pinmux.h>
26 #include <linux/platform_device.h>
27 #include <linux/regmap.h>
28 #include <linux/reset.h>
29 #include <linux/slab.h>
30 
31 #include "../core.h"
32 #include "../pinconf.h"
33 #include "../pinctrl-utils.h"
34 #include "pinctrl-stm32.h"
35 
36 #define STM32_GPIO_MODER	0x00
37 #define STM32_GPIO_TYPER	0x04
38 #define STM32_GPIO_SPEEDR	0x08
39 #define STM32_GPIO_PUPDR	0x0c
40 #define STM32_GPIO_IDR		0x10
41 #define STM32_GPIO_ODR		0x14
42 #define STM32_GPIO_BSRR		0x18
43 #define STM32_GPIO_LCKR		0x1c
44 #define STM32_GPIO_AFRL		0x20
45 #define STM32_GPIO_AFRH		0x24
46 
47 /* custom bitfield to backup pin status */
48 #define STM32_GPIO_BKP_MODE_SHIFT	0
49 #define STM32_GPIO_BKP_MODE_MASK	GENMASK(1, 0)
50 #define STM32_GPIO_BKP_ALT_SHIFT	2
51 #define STM32_GPIO_BKP_ALT_MASK		GENMASK(5, 2)
52 #define STM32_GPIO_BKP_SPEED_SHIFT	6
53 #define STM32_GPIO_BKP_SPEED_MASK	GENMASK(7, 6)
54 #define STM32_GPIO_BKP_PUPD_SHIFT	8
55 #define STM32_GPIO_BKP_PUPD_MASK	GENMASK(9, 8)
56 #define STM32_GPIO_BKP_TYPE		10
57 #define STM32_GPIO_BKP_VAL		11
58 
59 #define STM32_GPIO_PINS_PER_BANK 16
60 #define STM32_GPIO_IRQ_LINE	 16
61 
62 #define SYSCFG_IRQMUX_MASK GENMASK(3, 0)
63 
64 #define gpio_range_to_bank(chip) \
65 		container_of(chip, struct stm32_gpio_bank, range)
66 
67 #define HWSPNLCK_TIMEOUT	1000 /* usec */
68 
69 static const char * const stm32_gpio_functions[] = {
70 	"gpio", "af0", "af1",
71 	"af2", "af3", "af4",
72 	"af5", "af6", "af7",
73 	"af8", "af9", "af10",
74 	"af11", "af12", "af13",
75 	"af14", "af15", "analog",
76 };
77 
78 struct stm32_pinctrl_group {
79 	const char *name;
80 	unsigned long config;
81 	unsigned pin;
82 };
83 
84 struct stm32_gpio_bank {
85 	void __iomem *base;
86 	struct clk *clk;
87 	struct reset_control *rstc;
88 	spinlock_t lock;
89 	struct gpio_chip gpio_chip;
90 	struct pinctrl_gpio_range range;
91 	struct fwnode_handle *fwnode;
92 	struct irq_domain *domain;
93 	u32 bank_nr;
94 	u32 bank_ioport_nr;
95 	u32 pin_backup[STM32_GPIO_PINS_PER_BANK];
96 	u8 irq_type[STM32_GPIO_PINS_PER_BANK];
97 };
98 
99 struct stm32_pinctrl {
100 	struct device *dev;
101 	struct pinctrl_dev *pctl_dev;
102 	struct pinctrl_desc pctl_desc;
103 	struct stm32_pinctrl_group *groups;
104 	unsigned ngroups;
105 	const char **grp_names;
106 	struct stm32_gpio_bank *banks;
107 	unsigned nbanks;
108 	const struct stm32_pinctrl_match_data *match_data;
109 	struct irq_domain	*domain;
110 	struct regmap		*regmap;
111 	struct regmap_field	*irqmux[STM32_GPIO_PINS_PER_BANK];
112 	struct hwspinlock *hwlock;
113 	struct stm32_desc_pin *pins;
114 	u32 npins;
115 	u32 pkg;
116 	u16 irqmux_map;
117 	spinlock_t irqmux_lock;
118 };
119 
120 static inline int stm32_gpio_pin(int gpio)
121 {
122 	return gpio % STM32_GPIO_PINS_PER_BANK;
123 }
124 
125 static inline u32 stm32_gpio_get_mode(u32 function)
126 {
127 	switch (function) {
128 	case STM32_PIN_GPIO:
129 		return 0;
130 	case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
131 		return 2;
132 	case STM32_PIN_ANALOG:
133 		return 3;
134 	}
135 
136 	return 0;
137 }
138 
139 static inline u32 stm32_gpio_get_alt(u32 function)
140 {
141 	switch (function) {
142 	case STM32_PIN_GPIO:
143 		return 0;
144 	case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
145 		return function - 1;
146 	case STM32_PIN_ANALOG:
147 		return 0;
148 	}
149 
150 	return 0;
151 }
152 
153 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank,
154 				    u32 offset, u32 value)
155 {
156 	bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL);
157 	bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL;
158 }
159 
160 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset,
161 				   u32 mode, u32 alt)
162 {
163 	bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK |
164 				      STM32_GPIO_BKP_ALT_MASK);
165 	bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT;
166 	bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT;
167 }
168 
169 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset,
170 				      u32 drive)
171 {
172 	bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE);
173 	bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE;
174 }
175 
176 static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset,
177 				    u32 speed)
178 {
179 	bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK;
180 	bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT;
181 }
182 
183 static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset,
184 				   u32 bias)
185 {
186 	bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK;
187 	bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT;
188 }
189 
190 /* GPIO functions */
191 
192 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,
193 	unsigned offset, int value)
194 {
195 	stm32_gpio_backup_value(bank, offset, value);
196 
197 	if (!value)
198 		offset += STM32_GPIO_PINS_PER_BANK;
199 
200 	clk_enable(bank->clk);
201 
202 	writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR);
203 
204 	clk_disable(bank->clk);
205 }
206 
207 static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset)
208 {
209 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
210 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
211 	struct pinctrl_gpio_range *range;
212 	int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK);
213 
214 	range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin);
215 	if (!range) {
216 		dev_err(pctl->dev, "pin %d not in range.\n", pin);
217 		return -EINVAL;
218 	}
219 
220 	return pinctrl_gpio_request(chip->base + offset);
221 }
222 
223 static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset)
224 {
225 	pinctrl_gpio_free(chip->base + offset);
226 }
227 
228 static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset)
229 {
230 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
231 	int ret;
232 
233 	clk_enable(bank->clk);
234 
235 	ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
236 
237 	clk_disable(bank->clk);
238 
239 	return ret;
240 }
241 
242 static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
243 {
244 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
245 
246 	__stm32_gpio_set(bank, offset, value);
247 }
248 
249 static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
250 {
251 	return pinctrl_gpio_direction_input(chip->base + offset);
252 }
253 
254 static int stm32_gpio_direction_output(struct gpio_chip *chip,
255 	unsigned offset, int value)
256 {
257 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
258 
259 	__stm32_gpio_set(bank, offset, value);
260 	pinctrl_gpio_direction_output(chip->base + offset);
261 
262 	return 0;
263 }
264 
265 
266 static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
267 {
268 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
269 	struct irq_fwspec fwspec;
270 
271 	fwspec.fwnode = bank->fwnode;
272 	fwspec.param_count = 2;
273 	fwspec.param[0] = offset;
274 	fwspec.param[1] = IRQ_TYPE_NONE;
275 
276 	return irq_create_fwspec_mapping(&fwspec);
277 }
278 
279 static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
280 {
281 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
282 	int pin = stm32_gpio_pin(offset);
283 	int ret;
284 	u32 mode, alt;
285 
286 	stm32_pmx_get_mode(bank, pin, &mode, &alt);
287 	if ((alt == 0) && (mode == 0))
288 		ret = GPIO_LINE_DIRECTION_IN;
289 	else if ((alt == 0) && (mode == 1))
290 		ret = GPIO_LINE_DIRECTION_OUT;
291 	else
292 		ret = -EINVAL;
293 
294 	return ret;
295 }
296 
297 static const struct gpio_chip stm32_gpio_template = {
298 	.request		= stm32_gpio_request,
299 	.free			= stm32_gpio_free,
300 	.get			= stm32_gpio_get,
301 	.set			= stm32_gpio_set,
302 	.direction_input	= stm32_gpio_direction_input,
303 	.direction_output	= stm32_gpio_direction_output,
304 	.to_irq			= stm32_gpio_to_irq,
305 	.get_direction		= stm32_gpio_get_direction,
306 	.set_config		= gpiochip_generic_config,
307 };
308 
309 static void stm32_gpio_irq_trigger(struct irq_data *d)
310 {
311 	struct stm32_gpio_bank *bank = d->domain->host_data;
312 	int level;
313 
314 	/* If level interrupt type then retrig */
315 	level = stm32_gpio_get(&bank->gpio_chip, d->hwirq);
316 	if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) ||
317 	    (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH))
318 		irq_chip_retrigger_hierarchy(d);
319 }
320 
321 static void stm32_gpio_irq_eoi(struct irq_data *d)
322 {
323 	irq_chip_eoi_parent(d);
324 	stm32_gpio_irq_trigger(d);
325 };
326 
327 static int stm32_gpio_set_type(struct irq_data *d, unsigned int type)
328 {
329 	struct stm32_gpio_bank *bank = d->domain->host_data;
330 	u32 parent_type;
331 
332 	switch (type) {
333 	case IRQ_TYPE_EDGE_RISING:
334 	case IRQ_TYPE_EDGE_FALLING:
335 	case IRQ_TYPE_EDGE_BOTH:
336 		parent_type = type;
337 		break;
338 	case IRQ_TYPE_LEVEL_HIGH:
339 		parent_type = IRQ_TYPE_EDGE_RISING;
340 		break;
341 	case IRQ_TYPE_LEVEL_LOW:
342 		parent_type = IRQ_TYPE_EDGE_FALLING;
343 		break;
344 	default:
345 		return -EINVAL;
346 	}
347 
348 	bank->irq_type[d->hwirq] = type;
349 
350 	return irq_chip_set_type_parent(d, parent_type);
351 };
352 
353 static int stm32_gpio_irq_request_resources(struct irq_data *irq_data)
354 {
355 	struct stm32_gpio_bank *bank = irq_data->domain->host_data;
356 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
357 	int ret;
358 
359 	ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);
360 	if (ret)
361 		return ret;
362 
363 	ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq);
364 	if (ret) {
365 		dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
366 			irq_data->hwirq);
367 		return ret;
368 	}
369 
370 	return 0;
371 }
372 
373 static void stm32_gpio_irq_release_resources(struct irq_data *irq_data)
374 {
375 	struct stm32_gpio_bank *bank = irq_data->domain->host_data;
376 
377 	gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq);
378 }
379 
380 static void stm32_gpio_irq_unmask(struct irq_data *d)
381 {
382 	irq_chip_unmask_parent(d);
383 	stm32_gpio_irq_trigger(d);
384 }
385 
386 static struct irq_chip stm32_gpio_irq_chip = {
387 	.name		= "stm32gpio",
388 	.irq_eoi	= stm32_gpio_irq_eoi,
389 	.irq_ack	= irq_chip_ack_parent,
390 	.irq_mask	= irq_chip_mask_parent,
391 	.irq_unmask	= stm32_gpio_irq_unmask,
392 	.irq_set_type	= stm32_gpio_set_type,
393 	.irq_set_wake	= irq_chip_set_wake_parent,
394 	.irq_request_resources = stm32_gpio_irq_request_resources,
395 	.irq_release_resources = stm32_gpio_irq_release_resources,
396 };
397 
398 static int stm32_gpio_domain_translate(struct irq_domain *d,
399 				       struct irq_fwspec *fwspec,
400 				       unsigned long *hwirq,
401 				       unsigned int *type)
402 {
403 	if ((fwspec->param_count != 2) ||
404 	    (fwspec->param[0] >= STM32_GPIO_IRQ_LINE))
405 		return -EINVAL;
406 
407 	*hwirq = fwspec->param[0];
408 	*type = fwspec->param[1];
409 	return 0;
410 }
411 
412 static int stm32_gpio_domain_activate(struct irq_domain *d,
413 				      struct irq_data *irq_data, bool reserve)
414 {
415 	struct stm32_gpio_bank *bank = d->host_data;
416 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
417 	unsigned long flags;
418 	int ret = 0;
419 
420 	/*
421 	 * gpio irq mux is shared between several banks, a lock has to be done
422 	 * to avoid overriding.
423 	 */
424 	spin_lock_irqsave(&pctl->irqmux_lock, flags);
425 
426 	if (pctl->hwlock) {
427 		ret = hwspin_lock_timeout_in_atomic(pctl->hwlock,
428 						    HWSPNLCK_TIMEOUT);
429 		if (ret) {
430 			dev_err(pctl->dev, "Can't get hwspinlock\n");
431 			goto unlock;
432 		}
433 	}
434 
435 	if (pctl->irqmux_map & BIT(irq_data->hwirq)) {
436 		dev_err(pctl->dev, "irq line %ld already requested.\n",
437 			irq_data->hwirq);
438 		ret = -EBUSY;
439 		if (pctl->hwlock)
440 			hwspin_unlock_in_atomic(pctl->hwlock);
441 		goto unlock;
442 	} else {
443 		pctl->irqmux_map |= BIT(irq_data->hwirq);
444 	}
445 
446 	regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr);
447 
448 	if (pctl->hwlock)
449 		hwspin_unlock_in_atomic(pctl->hwlock);
450 
451 unlock:
452 	spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
453 	return ret;
454 }
455 
456 static void stm32_gpio_domain_deactivate(struct irq_domain *d,
457 					 struct irq_data *irq_data)
458 {
459 	struct stm32_gpio_bank *bank = d->host_data;
460 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
461 	unsigned long flags;
462 
463 	spin_lock_irqsave(&pctl->irqmux_lock, flags);
464 	pctl->irqmux_map &= ~BIT(irq_data->hwirq);
465 	spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
466 }
467 
468 static int stm32_gpio_domain_alloc(struct irq_domain *d,
469 				   unsigned int virq,
470 				   unsigned int nr_irqs, void *data)
471 {
472 	struct stm32_gpio_bank *bank = d->host_data;
473 	struct irq_fwspec *fwspec = data;
474 	struct irq_fwspec parent_fwspec;
475 	irq_hw_number_t hwirq;
476 
477 	hwirq = fwspec->param[0];
478 	parent_fwspec.fwnode = d->parent->fwnode;
479 	parent_fwspec.param_count = 2;
480 	parent_fwspec.param[0] = fwspec->param[0];
481 	parent_fwspec.param[1] = fwspec->param[1];
482 
483 	irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip,
484 				      bank);
485 
486 	return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec);
487 }
488 
489 static const struct irq_domain_ops stm32_gpio_domain_ops = {
490 	.translate      = stm32_gpio_domain_translate,
491 	.alloc          = stm32_gpio_domain_alloc,
492 	.free           = irq_domain_free_irqs_common,
493 	.activate	= stm32_gpio_domain_activate,
494 	.deactivate	= stm32_gpio_domain_deactivate,
495 };
496 
497 /* Pinctrl functions */
498 static struct stm32_pinctrl_group *
499 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin)
500 {
501 	int i;
502 
503 	for (i = 0; i < pctl->ngroups; i++) {
504 		struct stm32_pinctrl_group *grp = pctl->groups + i;
505 
506 		if (grp->pin == pin)
507 			return grp;
508 	}
509 
510 	return NULL;
511 }
512 
513 static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl,
514 		u32 pin_num, u32 fnum)
515 {
516 	int i;
517 
518 	for (i = 0; i < pctl->npins; i++) {
519 		const struct stm32_desc_pin *pin = pctl->pins + i;
520 		const struct stm32_desc_function *func = pin->functions;
521 
522 		if (pin->pin.number != pin_num)
523 			continue;
524 
525 		while (func && func->name) {
526 			if (func->num == fnum)
527 				return true;
528 			func++;
529 		}
530 
531 		break;
532 	}
533 
534 	dev_err(pctl->dev, "invalid function %d on pin %d .\n", fnum, pin_num);
535 
536 	return false;
537 }
538 
539 static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl,
540 		u32 pin, u32 fnum, struct stm32_pinctrl_group *grp,
541 		struct pinctrl_map **map, unsigned *reserved_maps,
542 		unsigned *num_maps)
543 {
544 	if (*num_maps == *reserved_maps)
545 		return -ENOSPC;
546 
547 	(*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
548 	(*map)[*num_maps].data.mux.group = grp->name;
549 
550 	if (!stm32_pctrl_is_function_valid(pctl, pin, fnum))
551 		return -EINVAL;
552 
553 	(*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum];
554 	(*num_maps)++;
555 
556 	return 0;
557 }
558 
559 static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
560 				      struct device_node *node,
561 				      struct pinctrl_map **map,
562 				      unsigned *reserved_maps,
563 				      unsigned *num_maps)
564 {
565 	struct stm32_pinctrl *pctl;
566 	struct stm32_pinctrl_group *grp;
567 	struct property *pins;
568 	u32 pinfunc, pin, func;
569 	unsigned long *configs;
570 	unsigned int num_configs;
571 	bool has_config = 0;
572 	unsigned reserve = 0;
573 	int num_pins, num_funcs, maps_per_pin, i, err = 0;
574 
575 	pctl = pinctrl_dev_get_drvdata(pctldev);
576 
577 	pins = of_find_property(node, "pinmux", NULL);
578 	if (!pins) {
579 		dev_err(pctl->dev, "missing pins property in node %pOFn .\n",
580 				node);
581 		return -EINVAL;
582 	}
583 
584 	err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
585 		&num_configs);
586 	if (err)
587 		return err;
588 
589 	if (num_configs)
590 		has_config = 1;
591 
592 	num_pins = pins->length / sizeof(u32);
593 	num_funcs = num_pins;
594 	maps_per_pin = 0;
595 	if (num_funcs)
596 		maps_per_pin++;
597 	if (has_config && num_pins >= 1)
598 		maps_per_pin++;
599 
600 	if (!num_pins || !maps_per_pin) {
601 		err = -EINVAL;
602 		goto exit;
603 	}
604 
605 	reserve = num_pins * maps_per_pin;
606 
607 	err = pinctrl_utils_reserve_map(pctldev, map,
608 			reserved_maps, num_maps, reserve);
609 	if (err)
610 		goto exit;
611 
612 	for (i = 0; i < num_pins; i++) {
613 		err = of_property_read_u32_index(node, "pinmux",
614 				i, &pinfunc);
615 		if (err)
616 			goto exit;
617 
618 		pin = STM32_GET_PIN_NO(pinfunc);
619 		func = STM32_GET_PIN_FUNC(pinfunc);
620 
621 		if (!stm32_pctrl_is_function_valid(pctl, pin, func)) {
622 			err = -EINVAL;
623 			goto exit;
624 		}
625 
626 		grp = stm32_pctrl_find_group_by_pin(pctl, pin);
627 		if (!grp) {
628 			dev_err(pctl->dev, "unable to match pin %d to group\n",
629 					pin);
630 			err = -EINVAL;
631 			goto exit;
632 		}
633 
634 		err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
635 				reserved_maps, num_maps);
636 		if (err)
637 			goto exit;
638 
639 		if (has_config) {
640 			err = pinctrl_utils_add_map_configs(pctldev, map,
641 					reserved_maps, num_maps, grp->name,
642 					configs, num_configs,
643 					PIN_MAP_TYPE_CONFIGS_GROUP);
644 			if (err)
645 				goto exit;
646 		}
647 	}
648 
649 exit:
650 	kfree(configs);
651 	return err;
652 }
653 
654 static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
655 				 struct device_node *np_config,
656 				 struct pinctrl_map **map, unsigned *num_maps)
657 {
658 	struct device_node *np;
659 	unsigned reserved_maps;
660 	int ret;
661 
662 	*map = NULL;
663 	*num_maps = 0;
664 	reserved_maps = 0;
665 
666 	for_each_child_of_node(np_config, np) {
667 		ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map,
668 				&reserved_maps, num_maps);
669 		if (ret < 0) {
670 			pinctrl_utils_free_map(pctldev, *map, *num_maps);
671 			of_node_put(np);
672 			return ret;
673 		}
674 	}
675 
676 	return 0;
677 }
678 
679 static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
680 {
681 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
682 
683 	return pctl->ngroups;
684 }
685 
686 static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev,
687 					      unsigned group)
688 {
689 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
690 
691 	return pctl->groups[group].name;
692 }
693 
694 static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
695 				      unsigned group,
696 				      const unsigned **pins,
697 				      unsigned *num_pins)
698 {
699 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
700 
701 	*pins = (unsigned *)&pctl->groups[group].pin;
702 	*num_pins = 1;
703 
704 	return 0;
705 }
706 
707 static const struct pinctrl_ops stm32_pctrl_ops = {
708 	.dt_node_to_map		= stm32_pctrl_dt_node_to_map,
709 	.dt_free_map		= pinctrl_utils_free_map,
710 	.get_groups_count	= stm32_pctrl_get_groups_count,
711 	.get_group_name		= stm32_pctrl_get_group_name,
712 	.get_group_pins		= stm32_pctrl_get_group_pins,
713 };
714 
715 
716 /* Pinmux functions */
717 
718 static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
719 {
720 	return ARRAY_SIZE(stm32_gpio_functions);
721 }
722 
723 static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev,
724 					   unsigned selector)
725 {
726 	return stm32_gpio_functions[selector];
727 }
728 
729 static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev,
730 				     unsigned function,
731 				     const char * const **groups,
732 				     unsigned * const num_groups)
733 {
734 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
735 
736 	*groups = pctl->grp_names;
737 	*num_groups = pctl->ngroups;
738 
739 	return 0;
740 }
741 
742 static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
743 			      int pin, u32 mode, u32 alt)
744 {
745 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
746 	u32 val;
747 	int alt_shift = (pin % 8) * 4;
748 	int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
749 	unsigned long flags;
750 	int err = 0;
751 
752 	clk_enable(bank->clk);
753 	spin_lock_irqsave(&bank->lock, flags);
754 
755 	if (pctl->hwlock) {
756 		err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
757 						    HWSPNLCK_TIMEOUT);
758 		if (err) {
759 			dev_err(pctl->dev, "Can't get hwspinlock\n");
760 			goto unlock;
761 		}
762 	}
763 
764 	val = readl_relaxed(bank->base + alt_offset);
765 	val &= ~GENMASK(alt_shift + 3, alt_shift);
766 	val |= (alt << alt_shift);
767 	writel_relaxed(val, bank->base + alt_offset);
768 
769 	val = readl_relaxed(bank->base + STM32_GPIO_MODER);
770 	val &= ~GENMASK(pin * 2 + 1, pin * 2);
771 	val |= mode << (pin * 2);
772 	writel_relaxed(val, bank->base + STM32_GPIO_MODER);
773 
774 	if (pctl->hwlock)
775 		hwspin_unlock_in_atomic(pctl->hwlock);
776 
777 	stm32_gpio_backup_mode(bank, pin, mode, alt);
778 
779 unlock:
780 	spin_unlock_irqrestore(&bank->lock, flags);
781 	clk_disable(bank->clk);
782 
783 	return err;
784 }
785 
786 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode,
787 			u32 *alt)
788 {
789 	u32 val;
790 	int alt_shift = (pin % 8) * 4;
791 	int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
792 	unsigned long flags;
793 
794 	clk_enable(bank->clk);
795 	spin_lock_irqsave(&bank->lock, flags);
796 
797 	val = readl_relaxed(bank->base + alt_offset);
798 	val &= GENMASK(alt_shift + 3, alt_shift);
799 	*alt = val >> alt_shift;
800 
801 	val = readl_relaxed(bank->base + STM32_GPIO_MODER);
802 	val &= GENMASK(pin * 2 + 1, pin * 2);
803 	*mode = val >> (pin * 2);
804 
805 	spin_unlock_irqrestore(&bank->lock, flags);
806 	clk_disable(bank->clk);
807 }
808 
809 static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev,
810 			    unsigned function,
811 			    unsigned group)
812 {
813 	bool ret;
814 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
815 	struct stm32_pinctrl_group *g = pctl->groups + group;
816 	struct pinctrl_gpio_range *range;
817 	struct stm32_gpio_bank *bank;
818 	u32 mode, alt;
819 	int pin;
820 
821 	ret = stm32_pctrl_is_function_valid(pctl, g->pin, function);
822 	if (!ret)
823 		return -EINVAL;
824 
825 	range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin);
826 	if (!range) {
827 		dev_err(pctl->dev, "No gpio range defined.\n");
828 		return -EINVAL;
829 	}
830 
831 	bank = gpiochip_get_data(range->gc);
832 	pin = stm32_gpio_pin(g->pin);
833 
834 	mode = stm32_gpio_get_mode(function);
835 	alt = stm32_gpio_get_alt(function);
836 
837 	return stm32_pmx_set_mode(bank, pin, mode, alt);
838 }
839 
840 static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
841 			struct pinctrl_gpio_range *range, unsigned gpio,
842 			bool input)
843 {
844 	struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc);
845 	int pin = stm32_gpio_pin(gpio);
846 
847 	return stm32_pmx_set_mode(bank, pin, !input, 0);
848 }
849 
850 static const struct pinmux_ops stm32_pmx_ops = {
851 	.get_functions_count	= stm32_pmx_get_funcs_cnt,
852 	.get_function_name	= stm32_pmx_get_func_name,
853 	.get_function_groups	= stm32_pmx_get_func_groups,
854 	.set_mux		= stm32_pmx_set_mux,
855 	.gpio_set_direction	= stm32_pmx_gpio_set_direction,
856 	.strict			= true,
857 };
858 
859 /* Pinconf functions */
860 
861 static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
862 				   unsigned offset, u32 drive)
863 {
864 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
865 	unsigned long flags;
866 	u32 val;
867 	int err = 0;
868 
869 	clk_enable(bank->clk);
870 	spin_lock_irqsave(&bank->lock, flags);
871 
872 	if (pctl->hwlock) {
873 		err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
874 						    HWSPNLCK_TIMEOUT);
875 		if (err) {
876 			dev_err(pctl->dev, "Can't get hwspinlock\n");
877 			goto unlock;
878 		}
879 	}
880 
881 	val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
882 	val &= ~BIT(offset);
883 	val |= drive << offset;
884 	writel_relaxed(val, bank->base + STM32_GPIO_TYPER);
885 
886 	if (pctl->hwlock)
887 		hwspin_unlock_in_atomic(pctl->hwlock);
888 
889 	stm32_gpio_backup_driving(bank, offset, drive);
890 
891 unlock:
892 	spin_unlock_irqrestore(&bank->lock, flags);
893 	clk_disable(bank->clk);
894 
895 	return err;
896 }
897 
898 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank,
899 	unsigned int offset)
900 {
901 	unsigned long flags;
902 	u32 val;
903 
904 	clk_enable(bank->clk);
905 	spin_lock_irqsave(&bank->lock, flags);
906 
907 	val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
908 	val &= BIT(offset);
909 
910 	spin_unlock_irqrestore(&bank->lock, flags);
911 	clk_disable(bank->clk);
912 
913 	return (val >> offset);
914 }
915 
916 static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
917 				 unsigned offset, u32 speed)
918 {
919 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
920 	unsigned long flags;
921 	u32 val;
922 	int err = 0;
923 
924 	clk_enable(bank->clk);
925 	spin_lock_irqsave(&bank->lock, flags);
926 
927 	if (pctl->hwlock) {
928 		err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
929 						    HWSPNLCK_TIMEOUT);
930 		if (err) {
931 			dev_err(pctl->dev, "Can't get hwspinlock\n");
932 			goto unlock;
933 		}
934 	}
935 
936 	val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
937 	val &= ~GENMASK(offset * 2 + 1, offset * 2);
938 	val |= speed << (offset * 2);
939 	writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);
940 
941 	if (pctl->hwlock)
942 		hwspin_unlock_in_atomic(pctl->hwlock);
943 
944 	stm32_gpio_backup_speed(bank, offset, speed);
945 
946 unlock:
947 	spin_unlock_irqrestore(&bank->lock, flags);
948 	clk_disable(bank->clk);
949 
950 	return err;
951 }
952 
953 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank,
954 	unsigned int offset)
955 {
956 	unsigned long flags;
957 	u32 val;
958 
959 	clk_enable(bank->clk);
960 	spin_lock_irqsave(&bank->lock, flags);
961 
962 	val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
963 	val &= GENMASK(offset * 2 + 1, offset * 2);
964 
965 	spin_unlock_irqrestore(&bank->lock, flags);
966 	clk_disable(bank->clk);
967 
968 	return (val >> (offset * 2));
969 }
970 
971 static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
972 				unsigned offset, u32 bias)
973 {
974 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
975 	unsigned long flags;
976 	u32 val;
977 	int err = 0;
978 
979 	clk_enable(bank->clk);
980 	spin_lock_irqsave(&bank->lock, flags);
981 
982 	if (pctl->hwlock) {
983 		err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
984 						    HWSPNLCK_TIMEOUT);
985 		if (err) {
986 			dev_err(pctl->dev, "Can't get hwspinlock\n");
987 			goto unlock;
988 		}
989 	}
990 
991 	val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
992 	val &= ~GENMASK(offset * 2 + 1, offset * 2);
993 	val |= bias << (offset * 2);
994 	writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);
995 
996 	if (pctl->hwlock)
997 		hwspin_unlock_in_atomic(pctl->hwlock);
998 
999 	stm32_gpio_backup_bias(bank, offset, bias);
1000 
1001 unlock:
1002 	spin_unlock_irqrestore(&bank->lock, flags);
1003 	clk_disable(bank->clk);
1004 
1005 	return err;
1006 }
1007 
1008 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank,
1009 	unsigned int offset)
1010 {
1011 	unsigned long flags;
1012 	u32 val;
1013 
1014 	clk_enable(bank->clk);
1015 	spin_lock_irqsave(&bank->lock, flags);
1016 
1017 	val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
1018 	val &= GENMASK(offset * 2 + 1, offset * 2);
1019 
1020 	spin_unlock_irqrestore(&bank->lock, flags);
1021 	clk_disable(bank->clk);
1022 
1023 	return (val >> (offset * 2));
1024 }
1025 
1026 static bool stm32_pconf_get(struct stm32_gpio_bank *bank,
1027 	unsigned int offset, bool dir)
1028 {
1029 	unsigned long flags;
1030 	u32 val;
1031 
1032 	clk_enable(bank->clk);
1033 	spin_lock_irqsave(&bank->lock, flags);
1034 
1035 	if (dir)
1036 		val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) &
1037 			 BIT(offset));
1038 	else
1039 		val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) &
1040 			 BIT(offset));
1041 
1042 	spin_unlock_irqrestore(&bank->lock, flags);
1043 	clk_disable(bank->clk);
1044 
1045 	return val;
1046 }
1047 
1048 static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev,
1049 		unsigned int pin, enum pin_config_param param,
1050 		enum pin_config_param arg)
1051 {
1052 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1053 	struct pinctrl_gpio_range *range;
1054 	struct stm32_gpio_bank *bank;
1055 	int offset, ret = 0;
1056 
1057 	range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
1058 	if (!range) {
1059 		dev_err(pctl->dev, "No gpio range defined.\n");
1060 		return -EINVAL;
1061 	}
1062 
1063 	bank = gpiochip_get_data(range->gc);
1064 	offset = stm32_gpio_pin(pin);
1065 
1066 	switch (param) {
1067 	case PIN_CONFIG_DRIVE_PUSH_PULL:
1068 		ret = stm32_pconf_set_driving(bank, offset, 0);
1069 		break;
1070 	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1071 		ret = stm32_pconf_set_driving(bank, offset, 1);
1072 		break;
1073 	case PIN_CONFIG_SLEW_RATE:
1074 		ret = stm32_pconf_set_speed(bank, offset, arg);
1075 		break;
1076 	case PIN_CONFIG_BIAS_DISABLE:
1077 		ret = stm32_pconf_set_bias(bank, offset, 0);
1078 		break;
1079 	case PIN_CONFIG_BIAS_PULL_UP:
1080 		ret = stm32_pconf_set_bias(bank, offset, 1);
1081 		break;
1082 	case PIN_CONFIG_BIAS_PULL_DOWN:
1083 		ret = stm32_pconf_set_bias(bank, offset, 2);
1084 		break;
1085 	case PIN_CONFIG_OUTPUT:
1086 		__stm32_gpio_set(bank, offset, arg);
1087 		ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false);
1088 		break;
1089 	default:
1090 		ret = -ENOTSUPP;
1091 	}
1092 
1093 	return ret;
1094 }
1095 
1096 static int stm32_pconf_group_get(struct pinctrl_dev *pctldev,
1097 				 unsigned group,
1098 				 unsigned long *config)
1099 {
1100 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1101 
1102 	*config = pctl->groups[group].config;
1103 
1104 	return 0;
1105 }
1106 
1107 static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
1108 				 unsigned long *configs, unsigned num_configs)
1109 {
1110 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1111 	struct stm32_pinctrl_group *g = &pctl->groups[group];
1112 	int i, ret;
1113 
1114 	for (i = 0; i < num_configs; i++) {
1115 		mutex_lock(&pctldev->mutex);
1116 		ret = stm32_pconf_parse_conf(pctldev, g->pin,
1117 			pinconf_to_config_param(configs[i]),
1118 			pinconf_to_config_argument(configs[i]));
1119 		mutex_unlock(&pctldev->mutex);
1120 		if (ret < 0)
1121 			return ret;
1122 
1123 		g->config = configs[i];
1124 	}
1125 
1126 	return 0;
1127 }
1128 
1129 static int stm32_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1130 			   unsigned long *configs, unsigned int num_configs)
1131 {
1132 	int i, ret;
1133 
1134 	for (i = 0; i < num_configs; i++) {
1135 		ret = stm32_pconf_parse_conf(pctldev, pin,
1136 				pinconf_to_config_param(configs[i]),
1137 				pinconf_to_config_argument(configs[i]));
1138 		if (ret < 0)
1139 			return ret;
1140 	}
1141 
1142 	return 0;
1143 }
1144 
1145 static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev,
1146 				 struct seq_file *s,
1147 				 unsigned int pin)
1148 {
1149 	struct pinctrl_gpio_range *range;
1150 	struct stm32_gpio_bank *bank;
1151 	int offset;
1152 	u32 mode, alt, drive, speed, bias;
1153 	static const char * const modes[] = {
1154 			"input", "output", "alternate", "analog" };
1155 	static const char * const speeds[] = {
1156 			"low", "medium", "high", "very high" };
1157 	static const char * const biasing[] = {
1158 			"floating", "pull up", "pull down", "" };
1159 	bool val;
1160 
1161 	range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
1162 	if (!range)
1163 		return;
1164 
1165 	bank = gpiochip_get_data(range->gc);
1166 	offset = stm32_gpio_pin(pin);
1167 
1168 	stm32_pmx_get_mode(bank, offset, &mode, &alt);
1169 	bias = stm32_pconf_get_bias(bank, offset);
1170 
1171 	seq_printf(s, "%s ", modes[mode]);
1172 
1173 	switch (mode) {
1174 	/* input */
1175 	case 0:
1176 		val = stm32_pconf_get(bank, offset, true);
1177 		seq_printf(s, "- %s - %s",
1178 			   val ? "high" : "low",
1179 			   biasing[bias]);
1180 		break;
1181 
1182 	/* output */
1183 	case 1:
1184 		drive = stm32_pconf_get_driving(bank, offset);
1185 		speed = stm32_pconf_get_speed(bank, offset);
1186 		val = stm32_pconf_get(bank, offset, false);
1187 		seq_printf(s, "- %s - %s - %s - %s %s",
1188 			   val ? "high" : "low",
1189 			   drive ? "open drain" : "push pull",
1190 			   biasing[bias],
1191 			   speeds[speed], "speed");
1192 		break;
1193 
1194 	/* alternate */
1195 	case 2:
1196 		drive = stm32_pconf_get_driving(bank, offset);
1197 		speed = stm32_pconf_get_speed(bank, offset);
1198 		seq_printf(s, "%d - %s - %s - %s %s", alt,
1199 			   drive ? "open drain" : "push pull",
1200 			   biasing[bias],
1201 			   speeds[speed], "speed");
1202 		break;
1203 
1204 	/* analog */
1205 	case 3:
1206 		break;
1207 	}
1208 }
1209 
1210 static const struct pinconf_ops stm32_pconf_ops = {
1211 	.pin_config_group_get	= stm32_pconf_group_get,
1212 	.pin_config_group_set	= stm32_pconf_group_set,
1213 	.pin_config_set		= stm32_pconf_set,
1214 	.pin_config_dbg_show	= stm32_pconf_dbg_show,
1215 };
1216 
1217 static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,
1218 	struct device_node *np)
1219 {
1220 	struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks];
1221 	int bank_ioport_nr;
1222 	struct pinctrl_gpio_range *range = &bank->range;
1223 	struct of_phandle_args args;
1224 	struct device *dev = pctl->dev;
1225 	struct resource res;
1226 	int npins = STM32_GPIO_PINS_PER_BANK;
1227 	int bank_nr, err;
1228 
1229 	if (!IS_ERR(bank->rstc))
1230 		reset_control_deassert(bank->rstc);
1231 
1232 	if (of_address_to_resource(np, 0, &res))
1233 		return -ENODEV;
1234 
1235 	bank->base = devm_ioremap_resource(dev, &res);
1236 	if (IS_ERR(bank->base))
1237 		return PTR_ERR(bank->base);
1238 
1239 	err = clk_prepare(bank->clk);
1240 	if (err) {
1241 		dev_err(dev, "failed to prepare clk (%d)\n", err);
1242 		return err;
1243 	}
1244 
1245 	bank->gpio_chip = stm32_gpio_template;
1246 
1247 	of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label);
1248 
1249 	if (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args)) {
1250 		bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK;
1251 		bank->gpio_chip.base = args.args[1];
1252 	} else {
1253 		bank_nr = pctl->nbanks;
1254 		bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
1255 		range->name = bank->gpio_chip.label;
1256 		range->id = bank_nr;
1257 		range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK;
1258 		range->base = range->id * STM32_GPIO_PINS_PER_BANK;
1259 		range->npins = npins;
1260 		range->gc = &bank->gpio_chip;
1261 		pinctrl_add_gpio_range(pctl->pctl_dev,
1262 				       &pctl->banks[bank_nr].range);
1263 	}
1264 
1265 	if (of_property_read_u32(np, "st,bank-ioport", &bank_ioport_nr))
1266 		bank_ioport_nr = bank_nr;
1267 
1268 	bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
1269 
1270 	bank->gpio_chip.ngpio = npins;
1271 	bank->gpio_chip.of_node = np;
1272 	bank->gpio_chip.parent = dev;
1273 	bank->bank_nr = bank_nr;
1274 	bank->bank_ioport_nr = bank_ioport_nr;
1275 	spin_lock_init(&bank->lock);
1276 
1277 	/* create irq hierarchical domain */
1278 	bank->fwnode = of_node_to_fwnode(np);
1279 
1280 	bank->domain = irq_domain_create_hierarchy(pctl->domain, 0,
1281 					STM32_GPIO_IRQ_LINE, bank->fwnode,
1282 					&stm32_gpio_domain_ops, bank);
1283 
1284 	if (!bank->domain)
1285 		return -ENODEV;
1286 
1287 	err = gpiochip_add_data(&bank->gpio_chip, bank);
1288 	if (err) {
1289 		dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr);
1290 		return err;
1291 	}
1292 
1293 	dev_info(dev, "%s bank added\n", bank->gpio_chip.label);
1294 	return 0;
1295 }
1296 
1297 static struct irq_domain *stm32_pctrl_get_irq_domain(struct device_node *np)
1298 {
1299 	struct device_node *parent;
1300 	struct irq_domain *domain;
1301 
1302 	if (!of_find_property(np, "interrupt-parent", NULL))
1303 		return NULL;
1304 
1305 	parent = of_irq_find_parent(np);
1306 	if (!parent)
1307 		return ERR_PTR(-ENXIO);
1308 
1309 	domain = irq_find_host(parent);
1310 	if (!domain)
1311 		/* domain not registered yet */
1312 		return ERR_PTR(-EPROBE_DEFER);
1313 
1314 	return domain;
1315 }
1316 
1317 static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev,
1318 			   struct stm32_pinctrl *pctl)
1319 {
1320 	struct device_node *np = pdev->dev.of_node;
1321 	struct device *dev = &pdev->dev;
1322 	struct regmap *rm;
1323 	int offset, ret, i;
1324 	int mask, mask_width;
1325 
1326 	pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1327 	if (IS_ERR(pctl->regmap))
1328 		return PTR_ERR(pctl->regmap);
1329 
1330 	rm = pctl->regmap;
1331 
1332 	ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset);
1333 	if (ret)
1334 		return ret;
1335 
1336 	ret = of_property_read_u32_index(np, "st,syscfg", 2, &mask);
1337 	if (ret)
1338 		mask = SYSCFG_IRQMUX_MASK;
1339 
1340 	mask_width = fls(mask);
1341 
1342 	for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) {
1343 		struct reg_field mux;
1344 
1345 		mux.reg = offset + (i / 4) * 4;
1346 		mux.lsb = (i % 4) * mask_width;
1347 		mux.msb = mux.lsb + mask_width - 1;
1348 
1349 		dev_dbg(dev, "irqmux%d: reg:%#x, lsb:%d, msb:%d\n",
1350 			i, mux.reg, mux.lsb, mux.msb);
1351 
1352 		pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux);
1353 		if (IS_ERR(pctl->irqmux[i]))
1354 			return PTR_ERR(pctl->irqmux[i]);
1355 	}
1356 
1357 	return 0;
1358 }
1359 
1360 static int stm32_pctrl_build_state(struct platform_device *pdev)
1361 {
1362 	struct stm32_pinctrl *pctl = platform_get_drvdata(pdev);
1363 	int i;
1364 
1365 	pctl->ngroups = pctl->npins;
1366 
1367 	/* Allocate groups */
1368 	pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
1369 				    sizeof(*pctl->groups), GFP_KERNEL);
1370 	if (!pctl->groups)
1371 		return -ENOMEM;
1372 
1373 	/* We assume that one pin is one group, use pin name as group name. */
1374 	pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
1375 				       sizeof(*pctl->grp_names), GFP_KERNEL);
1376 	if (!pctl->grp_names)
1377 		return -ENOMEM;
1378 
1379 	for (i = 0; i < pctl->npins; i++) {
1380 		const struct stm32_desc_pin *pin = pctl->pins + i;
1381 		struct stm32_pinctrl_group *group = pctl->groups + i;
1382 
1383 		group->name = pin->pin.name;
1384 		group->pin = pin->pin.number;
1385 		pctl->grp_names[i] = pin->pin.name;
1386 	}
1387 
1388 	return 0;
1389 }
1390 
1391 static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl,
1392 				       struct stm32_desc_pin *pins)
1393 {
1394 	const struct stm32_desc_pin *p;
1395 	int i, nb_pins_available = 0;
1396 
1397 	for (i = 0; i < pctl->match_data->npins; i++) {
1398 		p = pctl->match_data->pins + i;
1399 		if (pctl->pkg && !(pctl->pkg & p->pkg))
1400 			continue;
1401 		pins->pin = p->pin;
1402 		pins->functions = p->functions;
1403 		pins++;
1404 		nb_pins_available++;
1405 	}
1406 
1407 	pctl->npins = nb_pins_available;
1408 
1409 	return 0;
1410 }
1411 
1412 static void stm32_pctl_get_package(struct device_node *np,
1413 				   struct stm32_pinctrl *pctl)
1414 {
1415 	if (of_property_read_u32(np, "st,package", &pctl->pkg)) {
1416 		pctl->pkg = 0;
1417 		dev_warn(pctl->dev, "No package detected, use default one\n");
1418 	} else {
1419 		dev_dbg(pctl->dev, "package detected: %x\n", pctl->pkg);
1420 	}
1421 }
1422 
1423 int stm32_pctl_probe(struct platform_device *pdev)
1424 {
1425 	struct device_node *np = pdev->dev.of_node;
1426 	struct device_node *child;
1427 	const struct of_device_id *match;
1428 	struct device *dev = &pdev->dev;
1429 	struct stm32_pinctrl *pctl;
1430 	struct pinctrl_pin_desc *pins;
1431 	int i, ret, hwlock_id, banks = 0;
1432 
1433 	if (!np)
1434 		return -EINVAL;
1435 
1436 	match = of_match_device(dev->driver->of_match_table, dev);
1437 	if (!match || !match->data)
1438 		return -EINVAL;
1439 
1440 	if (!of_find_property(np, "pins-are-numbered", NULL)) {
1441 		dev_err(dev, "only support pins-are-numbered format\n");
1442 		return -EINVAL;
1443 	}
1444 
1445 	pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
1446 	if (!pctl)
1447 		return -ENOMEM;
1448 
1449 	platform_set_drvdata(pdev, pctl);
1450 
1451 	/* check for IRQ controller (may require deferred probe) */
1452 	pctl->domain = stm32_pctrl_get_irq_domain(np);
1453 	if (IS_ERR(pctl->domain))
1454 		return PTR_ERR(pctl->domain);
1455 
1456 	/* hwspinlock is optional */
1457 	hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0);
1458 	if (hwlock_id < 0) {
1459 		if (hwlock_id == -EPROBE_DEFER)
1460 			return hwlock_id;
1461 	} else {
1462 		pctl->hwlock = hwspin_lock_request_specific(hwlock_id);
1463 	}
1464 
1465 	spin_lock_init(&pctl->irqmux_lock);
1466 
1467 	pctl->dev = dev;
1468 	pctl->match_data = match->data;
1469 
1470 	/*  get package information */
1471 	stm32_pctl_get_package(np, pctl);
1472 
1473 	pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins,
1474 				  sizeof(*pctl->pins), GFP_KERNEL);
1475 	if (!pctl->pins)
1476 		return -ENOMEM;
1477 
1478 	ret = stm32_pctrl_create_pins_tab(pctl, pctl->pins);
1479 	if (ret)
1480 		return ret;
1481 
1482 	ret = stm32_pctrl_build_state(pdev);
1483 	if (ret) {
1484 		dev_err(dev, "build state failed: %d\n", ret);
1485 		return -EINVAL;
1486 	}
1487 
1488 	if (pctl->domain) {
1489 		ret = stm32_pctrl_dt_setup_irq(pdev, pctl);
1490 		if (ret)
1491 			return ret;
1492 	}
1493 
1494 	pins = devm_kcalloc(&pdev->dev, pctl->npins, sizeof(*pins),
1495 			    GFP_KERNEL);
1496 	if (!pins)
1497 		return -ENOMEM;
1498 
1499 	for (i = 0; i < pctl->npins; i++)
1500 		pins[i] = pctl->pins[i].pin;
1501 
1502 	pctl->pctl_desc.name = dev_name(&pdev->dev);
1503 	pctl->pctl_desc.owner = THIS_MODULE;
1504 	pctl->pctl_desc.pins = pins;
1505 	pctl->pctl_desc.npins = pctl->npins;
1506 	pctl->pctl_desc.link_consumers = true;
1507 	pctl->pctl_desc.confops = &stm32_pconf_ops;
1508 	pctl->pctl_desc.pctlops = &stm32_pctrl_ops;
1509 	pctl->pctl_desc.pmxops = &stm32_pmx_ops;
1510 	pctl->dev = &pdev->dev;
1511 
1512 	pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
1513 					       pctl);
1514 
1515 	if (IS_ERR(pctl->pctl_dev)) {
1516 		dev_err(&pdev->dev, "Failed pinctrl registration\n");
1517 		return PTR_ERR(pctl->pctl_dev);
1518 	}
1519 
1520 	for_each_available_child_of_node(np, child)
1521 		if (of_property_read_bool(child, "gpio-controller"))
1522 			banks++;
1523 
1524 	if (!banks) {
1525 		dev_err(dev, "at least one GPIO bank is required\n");
1526 		return -EINVAL;
1527 	}
1528 	pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks),
1529 			GFP_KERNEL);
1530 	if (!pctl->banks)
1531 		return -ENOMEM;
1532 
1533 	i = 0;
1534 	for_each_available_child_of_node(np, child) {
1535 		struct stm32_gpio_bank *bank = &pctl->banks[i];
1536 
1537 		if (of_property_read_bool(child, "gpio-controller")) {
1538 			bank->rstc = of_reset_control_get_exclusive(child,
1539 								    NULL);
1540 			if (PTR_ERR(bank->rstc) == -EPROBE_DEFER) {
1541 				of_node_put(child);
1542 				return -EPROBE_DEFER;
1543 			}
1544 
1545 			bank->clk = of_clk_get_by_name(child, NULL);
1546 			if (IS_ERR(bank->clk)) {
1547 				if (PTR_ERR(bank->clk) != -EPROBE_DEFER)
1548 					dev_err(dev,
1549 						"failed to get clk (%ld)\n",
1550 						PTR_ERR(bank->clk));
1551 				of_node_put(child);
1552 				return PTR_ERR(bank->clk);
1553 			}
1554 			i++;
1555 		}
1556 	}
1557 
1558 	for_each_available_child_of_node(np, child) {
1559 		if (of_property_read_bool(child, "gpio-controller")) {
1560 			ret = stm32_gpiolib_register_bank(pctl, child);
1561 			if (ret) {
1562 				of_node_put(child);
1563 				return ret;
1564 			}
1565 
1566 			pctl->nbanks++;
1567 		}
1568 	}
1569 
1570 	dev_info(dev, "Pinctrl STM32 initialized\n");
1571 
1572 	return 0;
1573 }
1574 
1575 static int __maybe_unused stm32_pinctrl_restore_gpio_regs(
1576 					struct stm32_pinctrl *pctl, u32 pin)
1577 {
1578 	const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin);
1579 	u32 val, alt, mode, offset = stm32_gpio_pin(pin);
1580 	struct pinctrl_gpio_range *range;
1581 	struct stm32_gpio_bank *bank;
1582 	bool pin_is_irq;
1583 	int ret;
1584 
1585 	range = pinctrl_find_gpio_range_from_pin(pctl->pctl_dev, pin);
1586 	if (!range)
1587 		return 0;
1588 
1589 	pin_is_irq = gpiochip_line_is_irq(range->gc, offset);
1590 
1591 	if (!desc || (!pin_is_irq && !desc->gpio_owner))
1592 		return 0;
1593 
1594 	bank = gpiochip_get_data(range->gc);
1595 
1596 	alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK;
1597 	alt >>= STM32_GPIO_BKP_ALT_SHIFT;
1598 	mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK;
1599 	mode >>= STM32_GPIO_BKP_MODE_SHIFT;
1600 
1601 	ret = stm32_pmx_set_mode(bank, offset, mode, alt);
1602 	if (ret)
1603 		return ret;
1604 
1605 	if (mode == 1) {
1606 		val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL);
1607 		val = val >> STM32_GPIO_BKP_VAL;
1608 		__stm32_gpio_set(bank, offset, val);
1609 	}
1610 
1611 	val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE);
1612 	val >>= STM32_GPIO_BKP_TYPE;
1613 	ret = stm32_pconf_set_driving(bank, offset, val);
1614 	if (ret)
1615 		return ret;
1616 
1617 	val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK;
1618 	val >>= STM32_GPIO_BKP_SPEED_SHIFT;
1619 	ret = stm32_pconf_set_speed(bank, offset, val);
1620 	if (ret)
1621 		return ret;
1622 
1623 	val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK;
1624 	val >>= STM32_GPIO_BKP_PUPD_SHIFT;
1625 	ret = stm32_pconf_set_bias(bank, offset, val);
1626 	if (ret)
1627 		return ret;
1628 
1629 	if (pin_is_irq)
1630 		regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr);
1631 
1632 	return 0;
1633 }
1634 
1635 int __maybe_unused stm32_pinctrl_resume(struct device *dev)
1636 {
1637 	struct stm32_pinctrl *pctl = dev_get_drvdata(dev);
1638 	struct stm32_pinctrl_group *g = pctl->groups;
1639 	int i;
1640 
1641 	for (i = g->pin; i < g->pin + pctl->ngroups; i++)
1642 		stm32_pinctrl_restore_gpio_regs(pctl, i);
1643 
1644 	return 0;
1645 }
1646