1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics 2017 5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 * 7 * Heavily based on Mediatek's pinctrl driver 8 */ 9 #include <linux/clk.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/hwspinlock.h> 12 #include <linux/io.h> 13 #include <linux/irq.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/of_address.h> 18 #include <linux/of_device.h> 19 #include <linux/of_irq.h> 20 #include <linux/pinctrl/consumer.h> 21 #include <linux/pinctrl/machine.h> 22 #include <linux/pinctrl/pinconf.h> 23 #include <linux/pinctrl/pinconf-generic.h> 24 #include <linux/pinctrl/pinctrl.h> 25 #include <linux/pinctrl/pinmux.h> 26 #include <linux/platform_device.h> 27 #include <linux/regmap.h> 28 #include <linux/reset.h> 29 #include <linux/slab.h> 30 31 #include "../core.h" 32 #include "../pinconf.h" 33 #include "../pinctrl-utils.h" 34 #include "pinctrl-stm32.h" 35 36 #define STM32_GPIO_MODER 0x00 37 #define STM32_GPIO_TYPER 0x04 38 #define STM32_GPIO_SPEEDR 0x08 39 #define STM32_GPIO_PUPDR 0x0c 40 #define STM32_GPIO_IDR 0x10 41 #define STM32_GPIO_ODR 0x14 42 #define STM32_GPIO_BSRR 0x18 43 #define STM32_GPIO_LCKR 0x1c 44 #define STM32_GPIO_AFRL 0x20 45 #define STM32_GPIO_AFRH 0x24 46 47 #define STM32_GPIO_PINS_PER_BANK 16 48 #define STM32_GPIO_IRQ_LINE 16 49 50 #define SYSCFG_IRQMUX_MASK GENMASK(3, 0) 51 52 #define gpio_range_to_bank(chip) \ 53 container_of(chip, struct stm32_gpio_bank, range) 54 55 #define HWSPINLOCK_TIMEOUT 5 /* msec */ 56 57 static const char * const stm32_gpio_functions[] = { 58 "gpio", "af0", "af1", 59 "af2", "af3", "af4", 60 "af5", "af6", "af7", 61 "af8", "af9", "af10", 62 "af11", "af12", "af13", 63 "af14", "af15", "analog", 64 }; 65 66 struct stm32_pinctrl_group { 67 const char *name; 68 unsigned long config; 69 unsigned pin; 70 }; 71 72 struct stm32_gpio_bank { 73 void __iomem *base; 74 struct clk *clk; 75 spinlock_t lock; 76 struct gpio_chip gpio_chip; 77 struct pinctrl_gpio_range range; 78 struct fwnode_handle *fwnode; 79 struct irq_domain *domain; 80 u32 bank_nr; 81 u32 bank_ioport_nr; 82 }; 83 84 struct stm32_pinctrl { 85 struct device *dev; 86 struct pinctrl_dev *pctl_dev; 87 struct pinctrl_desc pctl_desc; 88 struct stm32_pinctrl_group *groups; 89 unsigned ngroups; 90 const char **grp_names; 91 struct stm32_gpio_bank *banks; 92 unsigned nbanks; 93 const struct stm32_pinctrl_match_data *match_data; 94 struct irq_domain *domain; 95 struct regmap *regmap; 96 struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK]; 97 struct hwspinlock *hwlock; 98 }; 99 100 static inline int stm32_gpio_pin(int gpio) 101 { 102 return gpio % STM32_GPIO_PINS_PER_BANK; 103 } 104 105 static inline u32 stm32_gpio_get_mode(u32 function) 106 { 107 switch (function) { 108 case STM32_PIN_GPIO: 109 return 0; 110 case STM32_PIN_AF(0) ... STM32_PIN_AF(15): 111 return 2; 112 case STM32_PIN_ANALOG: 113 return 3; 114 } 115 116 return 0; 117 } 118 119 static inline u32 stm32_gpio_get_alt(u32 function) 120 { 121 switch (function) { 122 case STM32_PIN_GPIO: 123 return 0; 124 case STM32_PIN_AF(0) ... STM32_PIN_AF(15): 125 return function - 1; 126 case STM32_PIN_ANALOG: 127 return 0; 128 } 129 130 return 0; 131 } 132 133 /* GPIO functions */ 134 135 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank, 136 unsigned offset, int value) 137 { 138 if (!value) 139 offset += STM32_GPIO_PINS_PER_BANK; 140 141 clk_enable(bank->clk); 142 143 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR); 144 145 clk_disable(bank->clk); 146 } 147 148 static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset) 149 { 150 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 151 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 152 struct pinctrl_gpio_range *range; 153 int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK); 154 155 range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin); 156 if (!range) { 157 dev_err(pctl->dev, "pin %d not in range.\n", pin); 158 return -EINVAL; 159 } 160 161 return pinctrl_gpio_request(chip->base + offset); 162 } 163 164 static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset) 165 { 166 pinctrl_gpio_free(chip->base + offset); 167 } 168 169 static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset) 170 { 171 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 172 int ret; 173 174 clk_enable(bank->clk); 175 176 ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset)); 177 178 clk_disable(bank->clk); 179 180 return ret; 181 } 182 183 static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 184 { 185 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 186 187 __stm32_gpio_set(bank, offset, value); 188 } 189 190 static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 191 { 192 return pinctrl_gpio_direction_input(chip->base + offset); 193 } 194 195 static int stm32_gpio_direction_output(struct gpio_chip *chip, 196 unsigned offset, int value) 197 { 198 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 199 200 __stm32_gpio_set(bank, offset, value); 201 pinctrl_gpio_direction_output(chip->base + offset); 202 203 return 0; 204 } 205 206 207 static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) 208 { 209 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 210 struct irq_fwspec fwspec; 211 212 fwspec.fwnode = bank->fwnode; 213 fwspec.param_count = 2; 214 fwspec.param[0] = offset; 215 fwspec.param[1] = IRQ_TYPE_NONE; 216 217 return irq_create_fwspec_mapping(&fwspec); 218 } 219 220 static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 221 { 222 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 223 int pin = stm32_gpio_pin(offset); 224 int ret; 225 u32 mode, alt; 226 227 stm32_pmx_get_mode(bank, pin, &mode, &alt); 228 if ((alt == 0) && (mode == 0)) 229 ret = 1; 230 else if ((alt == 0) && (mode == 1)) 231 ret = 0; 232 else 233 ret = -EINVAL; 234 235 return ret; 236 } 237 238 static const struct gpio_chip stm32_gpio_template = { 239 .request = stm32_gpio_request, 240 .free = stm32_gpio_free, 241 .get = stm32_gpio_get, 242 .set = stm32_gpio_set, 243 .direction_input = stm32_gpio_direction_input, 244 .direction_output = stm32_gpio_direction_output, 245 .to_irq = stm32_gpio_to_irq, 246 .get_direction = stm32_gpio_get_direction, 247 }; 248 249 static int stm32_gpio_irq_request_resources(struct irq_data *irq_data) 250 { 251 struct stm32_gpio_bank *bank = irq_data->domain->host_data; 252 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 253 int ret; 254 255 ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq); 256 if (ret) 257 return ret; 258 259 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq); 260 if (ret) { 261 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", 262 irq_data->hwirq); 263 return ret; 264 } 265 266 return 0; 267 } 268 269 static void stm32_gpio_irq_release_resources(struct irq_data *irq_data) 270 { 271 struct stm32_gpio_bank *bank = irq_data->domain->host_data; 272 273 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq); 274 } 275 276 static struct irq_chip stm32_gpio_irq_chip = { 277 .name = "stm32gpio", 278 .irq_eoi = irq_chip_eoi_parent, 279 .irq_ack = irq_chip_ack_parent, 280 .irq_mask = irq_chip_mask_parent, 281 .irq_unmask = irq_chip_unmask_parent, 282 .irq_set_type = irq_chip_set_type_parent, 283 .irq_set_wake = irq_chip_set_wake_parent, 284 .irq_request_resources = stm32_gpio_irq_request_resources, 285 .irq_release_resources = stm32_gpio_irq_release_resources, 286 }; 287 288 static int stm32_gpio_domain_translate(struct irq_domain *d, 289 struct irq_fwspec *fwspec, 290 unsigned long *hwirq, 291 unsigned int *type) 292 { 293 if ((fwspec->param_count != 2) || 294 (fwspec->param[0] >= STM32_GPIO_IRQ_LINE)) 295 return -EINVAL; 296 297 *hwirq = fwspec->param[0]; 298 *type = fwspec->param[1]; 299 return 0; 300 } 301 302 static int stm32_gpio_domain_activate(struct irq_domain *d, 303 struct irq_data *irq_data, bool reserve) 304 { 305 struct stm32_gpio_bank *bank = d->host_data; 306 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 307 308 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr); 309 return 0; 310 } 311 312 static int stm32_gpio_domain_alloc(struct irq_domain *d, 313 unsigned int virq, 314 unsigned int nr_irqs, void *data) 315 { 316 struct stm32_gpio_bank *bank = d->host_data; 317 struct irq_fwspec *fwspec = data; 318 struct irq_fwspec parent_fwspec; 319 irq_hw_number_t hwirq; 320 321 hwirq = fwspec->param[0]; 322 parent_fwspec.fwnode = d->parent->fwnode; 323 parent_fwspec.param_count = 2; 324 parent_fwspec.param[0] = fwspec->param[0]; 325 parent_fwspec.param[1] = fwspec->param[1]; 326 327 irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip, 328 bank); 329 330 return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec); 331 } 332 333 static const struct irq_domain_ops stm32_gpio_domain_ops = { 334 .translate = stm32_gpio_domain_translate, 335 .alloc = stm32_gpio_domain_alloc, 336 .free = irq_domain_free_irqs_common, 337 .activate = stm32_gpio_domain_activate, 338 }; 339 340 /* Pinctrl functions */ 341 static struct stm32_pinctrl_group * 342 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin) 343 { 344 int i; 345 346 for (i = 0; i < pctl->ngroups; i++) { 347 struct stm32_pinctrl_group *grp = pctl->groups + i; 348 349 if (grp->pin == pin) 350 return grp; 351 } 352 353 return NULL; 354 } 355 356 static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl, 357 u32 pin_num, u32 fnum) 358 { 359 int i; 360 361 for (i = 0; i < pctl->match_data->npins; i++) { 362 const struct stm32_desc_pin *pin = pctl->match_data->pins + i; 363 const struct stm32_desc_function *func = pin->functions; 364 365 if (pin->pin.number != pin_num) 366 continue; 367 368 while (func && func->name) { 369 if (func->num == fnum) 370 return true; 371 func++; 372 } 373 374 break; 375 } 376 377 return false; 378 } 379 380 static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl, 381 u32 pin, u32 fnum, struct stm32_pinctrl_group *grp, 382 struct pinctrl_map **map, unsigned *reserved_maps, 383 unsigned *num_maps) 384 { 385 if (*num_maps == *reserved_maps) 386 return -ENOSPC; 387 388 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; 389 (*map)[*num_maps].data.mux.group = grp->name; 390 391 if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) { 392 dev_err(pctl->dev, "invalid function %d on pin %d .\n", 393 fnum, pin); 394 return -EINVAL; 395 } 396 397 (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum]; 398 (*num_maps)++; 399 400 return 0; 401 } 402 403 static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, 404 struct device_node *node, 405 struct pinctrl_map **map, 406 unsigned *reserved_maps, 407 unsigned *num_maps) 408 { 409 struct stm32_pinctrl *pctl; 410 struct stm32_pinctrl_group *grp; 411 struct property *pins; 412 u32 pinfunc, pin, func; 413 unsigned long *configs; 414 unsigned int num_configs; 415 bool has_config = 0; 416 unsigned reserve = 0; 417 int num_pins, num_funcs, maps_per_pin, i, err = 0; 418 419 pctl = pinctrl_dev_get_drvdata(pctldev); 420 421 pins = of_find_property(node, "pinmux", NULL); 422 if (!pins) { 423 dev_err(pctl->dev, "missing pins property in node %pOFn .\n", 424 node); 425 return -EINVAL; 426 } 427 428 err = pinconf_generic_parse_dt_config(node, pctldev, &configs, 429 &num_configs); 430 if (err) 431 return err; 432 433 if (num_configs) 434 has_config = 1; 435 436 num_pins = pins->length / sizeof(u32); 437 num_funcs = num_pins; 438 maps_per_pin = 0; 439 if (num_funcs) 440 maps_per_pin++; 441 if (has_config && num_pins >= 1) 442 maps_per_pin++; 443 444 if (!num_pins || !maps_per_pin) { 445 err = -EINVAL; 446 goto exit; 447 } 448 449 reserve = num_pins * maps_per_pin; 450 451 err = pinctrl_utils_reserve_map(pctldev, map, 452 reserved_maps, num_maps, reserve); 453 if (err) 454 goto exit; 455 456 for (i = 0; i < num_pins; i++) { 457 err = of_property_read_u32_index(node, "pinmux", 458 i, &pinfunc); 459 if (err) 460 goto exit; 461 462 pin = STM32_GET_PIN_NO(pinfunc); 463 func = STM32_GET_PIN_FUNC(pinfunc); 464 465 if (!stm32_pctrl_is_function_valid(pctl, pin, func)) { 466 dev_err(pctl->dev, "invalid function.\n"); 467 err = -EINVAL; 468 goto exit; 469 } 470 471 grp = stm32_pctrl_find_group_by_pin(pctl, pin); 472 if (!grp) { 473 dev_err(pctl->dev, "unable to match pin %d to group\n", 474 pin); 475 err = -EINVAL; 476 goto exit; 477 } 478 479 err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map, 480 reserved_maps, num_maps); 481 if (err) 482 goto exit; 483 484 if (has_config) { 485 err = pinctrl_utils_add_map_configs(pctldev, map, 486 reserved_maps, num_maps, grp->name, 487 configs, num_configs, 488 PIN_MAP_TYPE_CONFIGS_GROUP); 489 if (err) 490 goto exit; 491 } 492 } 493 494 exit: 495 kfree(configs); 496 return err; 497 } 498 499 static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 500 struct device_node *np_config, 501 struct pinctrl_map **map, unsigned *num_maps) 502 { 503 struct device_node *np; 504 unsigned reserved_maps; 505 int ret; 506 507 *map = NULL; 508 *num_maps = 0; 509 reserved_maps = 0; 510 511 for_each_child_of_node(np_config, np) { 512 ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map, 513 &reserved_maps, num_maps); 514 if (ret < 0) { 515 pinctrl_utils_free_map(pctldev, *map, *num_maps); 516 return ret; 517 } 518 } 519 520 return 0; 521 } 522 523 static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev) 524 { 525 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 526 527 return pctl->ngroups; 528 } 529 530 static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev, 531 unsigned group) 532 { 533 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 534 535 return pctl->groups[group].name; 536 } 537 538 static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev, 539 unsigned group, 540 const unsigned **pins, 541 unsigned *num_pins) 542 { 543 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 544 545 *pins = (unsigned *)&pctl->groups[group].pin; 546 *num_pins = 1; 547 548 return 0; 549 } 550 551 static const struct pinctrl_ops stm32_pctrl_ops = { 552 .dt_node_to_map = stm32_pctrl_dt_node_to_map, 553 .dt_free_map = pinctrl_utils_free_map, 554 .get_groups_count = stm32_pctrl_get_groups_count, 555 .get_group_name = stm32_pctrl_get_group_name, 556 .get_group_pins = stm32_pctrl_get_group_pins, 557 }; 558 559 560 /* Pinmux functions */ 561 562 static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 563 { 564 return ARRAY_SIZE(stm32_gpio_functions); 565 } 566 567 static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev, 568 unsigned selector) 569 { 570 return stm32_gpio_functions[selector]; 571 } 572 573 static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev, 574 unsigned function, 575 const char * const **groups, 576 unsigned * const num_groups) 577 { 578 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 579 580 *groups = pctl->grp_names; 581 *num_groups = pctl->ngroups; 582 583 return 0; 584 } 585 586 static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank, 587 int pin, u32 mode, u32 alt) 588 { 589 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 590 u32 val; 591 int alt_shift = (pin % 8) * 4; 592 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; 593 unsigned long flags; 594 int err = 0; 595 596 clk_enable(bank->clk); 597 spin_lock_irqsave(&bank->lock, flags); 598 599 if (pctl->hwlock) 600 err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT); 601 602 if (err) { 603 dev_err(pctl->dev, "Can't get hwspinlock\n"); 604 goto unlock; 605 } 606 607 val = readl_relaxed(bank->base + alt_offset); 608 val &= ~GENMASK(alt_shift + 3, alt_shift); 609 val |= (alt << alt_shift); 610 writel_relaxed(val, bank->base + alt_offset); 611 612 val = readl_relaxed(bank->base + STM32_GPIO_MODER); 613 val &= ~GENMASK(pin * 2 + 1, pin * 2); 614 val |= mode << (pin * 2); 615 writel_relaxed(val, bank->base + STM32_GPIO_MODER); 616 617 if (pctl->hwlock) 618 hwspin_unlock(pctl->hwlock); 619 620 unlock: 621 spin_unlock_irqrestore(&bank->lock, flags); 622 clk_disable(bank->clk); 623 624 return err; 625 } 626 627 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, 628 u32 *alt) 629 { 630 u32 val; 631 int alt_shift = (pin % 8) * 4; 632 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; 633 unsigned long flags; 634 635 clk_enable(bank->clk); 636 spin_lock_irqsave(&bank->lock, flags); 637 638 val = readl_relaxed(bank->base + alt_offset); 639 val &= GENMASK(alt_shift + 3, alt_shift); 640 *alt = val >> alt_shift; 641 642 val = readl_relaxed(bank->base + STM32_GPIO_MODER); 643 val &= GENMASK(pin * 2 + 1, pin * 2); 644 *mode = val >> (pin * 2); 645 646 spin_unlock_irqrestore(&bank->lock, flags); 647 clk_disable(bank->clk); 648 } 649 650 static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev, 651 unsigned function, 652 unsigned group) 653 { 654 bool ret; 655 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 656 struct stm32_pinctrl_group *g = pctl->groups + group; 657 struct pinctrl_gpio_range *range; 658 struct stm32_gpio_bank *bank; 659 u32 mode, alt; 660 int pin; 661 662 ret = stm32_pctrl_is_function_valid(pctl, g->pin, function); 663 if (!ret) { 664 dev_err(pctl->dev, "invalid function %d on group %d .\n", 665 function, group); 666 return -EINVAL; 667 } 668 669 range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin); 670 if (!range) { 671 dev_err(pctl->dev, "No gpio range defined.\n"); 672 return -EINVAL; 673 } 674 675 bank = gpiochip_get_data(range->gc); 676 pin = stm32_gpio_pin(g->pin); 677 678 mode = stm32_gpio_get_mode(function); 679 alt = stm32_gpio_get_alt(function); 680 681 return stm32_pmx_set_mode(bank, pin, mode, alt); 682 } 683 684 static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 685 struct pinctrl_gpio_range *range, unsigned gpio, 686 bool input) 687 { 688 struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc); 689 int pin = stm32_gpio_pin(gpio); 690 691 return stm32_pmx_set_mode(bank, pin, !input, 0); 692 } 693 694 static const struct pinmux_ops stm32_pmx_ops = { 695 .get_functions_count = stm32_pmx_get_funcs_cnt, 696 .get_function_name = stm32_pmx_get_func_name, 697 .get_function_groups = stm32_pmx_get_func_groups, 698 .set_mux = stm32_pmx_set_mux, 699 .gpio_set_direction = stm32_pmx_gpio_set_direction, 700 .strict = true, 701 }; 702 703 /* Pinconf functions */ 704 705 static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank, 706 unsigned offset, u32 drive) 707 { 708 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 709 unsigned long flags; 710 u32 val; 711 int err = 0; 712 713 clk_enable(bank->clk); 714 spin_lock_irqsave(&bank->lock, flags); 715 716 if (pctl->hwlock) 717 err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT); 718 719 if (err) { 720 dev_err(pctl->dev, "Can't get hwspinlock\n"); 721 goto unlock; 722 } 723 724 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); 725 val &= ~BIT(offset); 726 val |= drive << offset; 727 writel_relaxed(val, bank->base + STM32_GPIO_TYPER); 728 729 if (pctl->hwlock) 730 hwspin_unlock(pctl->hwlock); 731 732 unlock: 733 spin_unlock_irqrestore(&bank->lock, flags); 734 clk_disable(bank->clk); 735 736 return err; 737 } 738 739 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank, 740 unsigned int offset) 741 { 742 unsigned long flags; 743 u32 val; 744 745 clk_enable(bank->clk); 746 spin_lock_irqsave(&bank->lock, flags); 747 748 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); 749 val &= BIT(offset); 750 751 spin_unlock_irqrestore(&bank->lock, flags); 752 clk_disable(bank->clk); 753 754 return (val >> offset); 755 } 756 757 static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank, 758 unsigned offset, u32 speed) 759 { 760 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 761 unsigned long flags; 762 u32 val; 763 int err = 0; 764 765 clk_enable(bank->clk); 766 spin_lock_irqsave(&bank->lock, flags); 767 768 if (pctl->hwlock) 769 err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT); 770 771 if (err) { 772 dev_err(pctl->dev, "Can't get hwspinlock\n"); 773 goto unlock; 774 } 775 776 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); 777 val &= ~GENMASK(offset * 2 + 1, offset * 2); 778 val |= speed << (offset * 2); 779 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR); 780 781 if (pctl->hwlock) 782 hwspin_unlock(pctl->hwlock); 783 784 unlock: 785 spin_unlock_irqrestore(&bank->lock, flags); 786 clk_disable(bank->clk); 787 788 return err; 789 } 790 791 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank, 792 unsigned int offset) 793 { 794 unsigned long flags; 795 u32 val; 796 797 clk_enable(bank->clk); 798 spin_lock_irqsave(&bank->lock, flags); 799 800 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); 801 val &= GENMASK(offset * 2 + 1, offset * 2); 802 803 spin_unlock_irqrestore(&bank->lock, flags); 804 clk_disable(bank->clk); 805 806 return (val >> (offset * 2)); 807 } 808 809 static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank, 810 unsigned offset, u32 bias) 811 { 812 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 813 unsigned long flags; 814 u32 val; 815 int err = 0; 816 817 clk_enable(bank->clk); 818 spin_lock_irqsave(&bank->lock, flags); 819 820 if (pctl->hwlock) 821 err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT); 822 823 if (err) { 824 dev_err(pctl->dev, "Can't get hwspinlock\n"); 825 goto unlock; 826 } 827 828 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); 829 val &= ~GENMASK(offset * 2 + 1, offset * 2); 830 val |= bias << (offset * 2); 831 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR); 832 833 if (pctl->hwlock) 834 hwspin_unlock(pctl->hwlock); 835 836 unlock: 837 spin_unlock_irqrestore(&bank->lock, flags); 838 clk_disable(bank->clk); 839 840 return err; 841 } 842 843 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank, 844 unsigned int offset) 845 { 846 unsigned long flags; 847 u32 val; 848 849 clk_enable(bank->clk); 850 spin_lock_irqsave(&bank->lock, flags); 851 852 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); 853 val &= GENMASK(offset * 2 + 1, offset * 2); 854 855 spin_unlock_irqrestore(&bank->lock, flags); 856 clk_disable(bank->clk); 857 858 return (val >> (offset * 2)); 859 } 860 861 static bool stm32_pconf_get(struct stm32_gpio_bank *bank, 862 unsigned int offset, bool dir) 863 { 864 unsigned long flags; 865 u32 val; 866 867 clk_enable(bank->clk); 868 spin_lock_irqsave(&bank->lock, flags); 869 870 if (dir) 871 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & 872 BIT(offset)); 873 else 874 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) & 875 BIT(offset)); 876 877 spin_unlock_irqrestore(&bank->lock, flags); 878 clk_disable(bank->clk); 879 880 return val; 881 } 882 883 static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev, 884 unsigned int pin, enum pin_config_param param, 885 enum pin_config_param arg) 886 { 887 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 888 struct pinctrl_gpio_range *range; 889 struct stm32_gpio_bank *bank; 890 int offset, ret = 0; 891 892 range = pinctrl_find_gpio_range_from_pin(pctldev, pin); 893 if (!range) { 894 dev_err(pctl->dev, "No gpio range defined.\n"); 895 return -EINVAL; 896 } 897 898 bank = gpiochip_get_data(range->gc); 899 offset = stm32_gpio_pin(pin); 900 901 switch (param) { 902 case PIN_CONFIG_DRIVE_PUSH_PULL: 903 ret = stm32_pconf_set_driving(bank, offset, 0); 904 break; 905 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 906 ret = stm32_pconf_set_driving(bank, offset, 1); 907 break; 908 case PIN_CONFIG_SLEW_RATE: 909 ret = stm32_pconf_set_speed(bank, offset, arg); 910 break; 911 case PIN_CONFIG_BIAS_DISABLE: 912 ret = stm32_pconf_set_bias(bank, offset, 0); 913 break; 914 case PIN_CONFIG_BIAS_PULL_UP: 915 ret = stm32_pconf_set_bias(bank, offset, 1); 916 break; 917 case PIN_CONFIG_BIAS_PULL_DOWN: 918 ret = stm32_pconf_set_bias(bank, offset, 2); 919 break; 920 case PIN_CONFIG_OUTPUT: 921 __stm32_gpio_set(bank, offset, arg); 922 ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false); 923 break; 924 default: 925 ret = -EINVAL; 926 } 927 928 return ret; 929 } 930 931 static int stm32_pconf_group_get(struct pinctrl_dev *pctldev, 932 unsigned group, 933 unsigned long *config) 934 { 935 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 936 937 *config = pctl->groups[group].config; 938 939 return 0; 940 } 941 942 static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, 943 unsigned long *configs, unsigned num_configs) 944 { 945 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 946 struct stm32_pinctrl_group *g = &pctl->groups[group]; 947 int i, ret; 948 949 for (i = 0; i < num_configs; i++) { 950 ret = stm32_pconf_parse_conf(pctldev, g->pin, 951 pinconf_to_config_param(configs[i]), 952 pinconf_to_config_argument(configs[i])); 953 if (ret < 0) 954 return ret; 955 956 g->config = configs[i]; 957 } 958 959 return 0; 960 } 961 962 static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev, 963 struct seq_file *s, 964 unsigned int pin) 965 { 966 struct pinctrl_gpio_range *range; 967 struct stm32_gpio_bank *bank; 968 int offset; 969 u32 mode, alt, drive, speed, bias; 970 static const char * const modes[] = { 971 "input", "output", "alternate", "analog" }; 972 static const char * const speeds[] = { 973 "low", "medium", "high", "very high" }; 974 static const char * const biasing[] = { 975 "floating", "pull up", "pull down", "" }; 976 bool val; 977 978 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); 979 if (!range) 980 return; 981 982 bank = gpiochip_get_data(range->gc); 983 offset = stm32_gpio_pin(pin); 984 985 stm32_pmx_get_mode(bank, offset, &mode, &alt); 986 bias = stm32_pconf_get_bias(bank, offset); 987 988 seq_printf(s, "%s ", modes[mode]); 989 990 switch (mode) { 991 /* input */ 992 case 0: 993 val = stm32_pconf_get(bank, offset, true); 994 seq_printf(s, "- %s - %s", 995 val ? "high" : "low", 996 biasing[bias]); 997 break; 998 999 /* output */ 1000 case 1: 1001 drive = stm32_pconf_get_driving(bank, offset); 1002 speed = stm32_pconf_get_speed(bank, offset); 1003 val = stm32_pconf_get(bank, offset, false); 1004 seq_printf(s, "- %s - %s - %s - %s %s", 1005 val ? "high" : "low", 1006 drive ? "open drain" : "push pull", 1007 biasing[bias], 1008 speeds[speed], "speed"); 1009 break; 1010 1011 /* alternate */ 1012 case 2: 1013 drive = stm32_pconf_get_driving(bank, offset); 1014 speed = stm32_pconf_get_speed(bank, offset); 1015 seq_printf(s, "%d - %s - %s - %s %s", alt, 1016 drive ? "open drain" : "push pull", 1017 biasing[bias], 1018 speeds[speed], "speed"); 1019 break; 1020 1021 /* analog */ 1022 case 3: 1023 break; 1024 } 1025 } 1026 1027 1028 static const struct pinconf_ops stm32_pconf_ops = { 1029 .pin_config_group_get = stm32_pconf_group_get, 1030 .pin_config_group_set = stm32_pconf_group_set, 1031 .pin_config_dbg_show = stm32_pconf_dbg_show, 1032 }; 1033 1034 static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, 1035 struct device_node *np) 1036 { 1037 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks]; 1038 int bank_ioport_nr; 1039 struct pinctrl_gpio_range *range = &bank->range; 1040 struct of_phandle_args args; 1041 struct device *dev = pctl->dev; 1042 struct resource res; 1043 struct reset_control *rstc; 1044 int npins = STM32_GPIO_PINS_PER_BANK; 1045 int bank_nr, err; 1046 1047 rstc = of_reset_control_get_exclusive(np, NULL); 1048 if (!IS_ERR(rstc)) 1049 reset_control_deassert(rstc); 1050 1051 if (of_address_to_resource(np, 0, &res)) 1052 return -ENODEV; 1053 1054 bank->base = devm_ioremap_resource(dev, &res); 1055 if (IS_ERR(bank->base)) 1056 return PTR_ERR(bank->base); 1057 1058 bank->clk = of_clk_get_by_name(np, NULL); 1059 if (IS_ERR(bank->clk)) { 1060 dev_err(dev, "failed to get clk (%ld)\n", PTR_ERR(bank->clk)); 1061 return PTR_ERR(bank->clk); 1062 } 1063 1064 err = clk_prepare(bank->clk); 1065 if (err) { 1066 dev_err(dev, "failed to prepare clk (%d)\n", err); 1067 return err; 1068 } 1069 1070 bank->gpio_chip = stm32_gpio_template; 1071 1072 of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label); 1073 1074 if (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args)) { 1075 bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK; 1076 bank->gpio_chip.base = args.args[1]; 1077 } else { 1078 bank_nr = pctl->nbanks; 1079 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; 1080 range->name = bank->gpio_chip.label; 1081 range->id = bank_nr; 1082 range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK; 1083 range->base = range->id * STM32_GPIO_PINS_PER_BANK; 1084 range->npins = npins; 1085 range->gc = &bank->gpio_chip; 1086 pinctrl_add_gpio_range(pctl->pctl_dev, 1087 &pctl->banks[bank_nr].range); 1088 } 1089 1090 if (of_property_read_u32(np, "st,bank-ioport", &bank_ioport_nr)) 1091 bank_ioport_nr = bank_nr; 1092 1093 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; 1094 1095 bank->gpio_chip.ngpio = npins; 1096 bank->gpio_chip.of_node = np; 1097 bank->gpio_chip.parent = dev; 1098 bank->bank_nr = bank_nr; 1099 bank->bank_ioport_nr = bank_ioport_nr; 1100 spin_lock_init(&bank->lock); 1101 1102 /* create irq hierarchical domain */ 1103 bank->fwnode = of_node_to_fwnode(np); 1104 1105 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, 1106 STM32_GPIO_IRQ_LINE, bank->fwnode, 1107 &stm32_gpio_domain_ops, bank); 1108 1109 if (!bank->domain) 1110 return -ENODEV; 1111 1112 err = gpiochip_add_data(&bank->gpio_chip, bank); 1113 if (err) { 1114 dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr); 1115 return err; 1116 } 1117 1118 dev_info(dev, "%s bank added\n", bank->gpio_chip.label); 1119 return 0; 1120 } 1121 1122 static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev, 1123 struct stm32_pinctrl *pctl) 1124 { 1125 struct device_node *np = pdev->dev.of_node, *parent; 1126 struct device *dev = &pdev->dev; 1127 struct regmap *rm; 1128 int offset, ret, i; 1129 int mask, mask_width; 1130 1131 parent = of_irq_find_parent(np); 1132 if (!parent) 1133 return -ENXIO; 1134 1135 pctl->domain = irq_find_host(parent); 1136 if (!pctl->domain) 1137 return -ENXIO; 1138 1139 pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); 1140 if (IS_ERR(pctl->regmap)) 1141 return PTR_ERR(pctl->regmap); 1142 1143 rm = pctl->regmap; 1144 1145 ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset); 1146 if (ret) 1147 return ret; 1148 1149 ret = of_property_read_u32_index(np, "st,syscfg", 2, &mask); 1150 if (ret) 1151 mask = SYSCFG_IRQMUX_MASK; 1152 1153 mask_width = fls(mask); 1154 1155 for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) { 1156 struct reg_field mux; 1157 1158 mux.reg = offset + (i / 4) * 4; 1159 mux.lsb = (i % 4) * mask_width; 1160 mux.msb = mux.lsb + mask_width - 1; 1161 1162 dev_dbg(dev, "irqmux%d: reg:%#x, lsb:%d, msb:%d\n", 1163 i, mux.reg, mux.lsb, mux.msb); 1164 1165 pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux); 1166 if (IS_ERR(pctl->irqmux[i])) 1167 return PTR_ERR(pctl->irqmux[i]); 1168 } 1169 1170 return 0; 1171 } 1172 1173 static int stm32_pctrl_build_state(struct platform_device *pdev) 1174 { 1175 struct stm32_pinctrl *pctl = platform_get_drvdata(pdev); 1176 int i; 1177 1178 pctl->ngroups = pctl->match_data->npins; 1179 1180 /* Allocate groups */ 1181 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups, 1182 sizeof(*pctl->groups), GFP_KERNEL); 1183 if (!pctl->groups) 1184 return -ENOMEM; 1185 1186 /* We assume that one pin is one group, use pin name as group name. */ 1187 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups, 1188 sizeof(*pctl->grp_names), GFP_KERNEL); 1189 if (!pctl->grp_names) 1190 return -ENOMEM; 1191 1192 for (i = 0; i < pctl->match_data->npins; i++) { 1193 const struct stm32_desc_pin *pin = pctl->match_data->pins + i; 1194 struct stm32_pinctrl_group *group = pctl->groups + i; 1195 1196 group->name = pin->pin.name; 1197 group->pin = pin->pin.number; 1198 1199 pctl->grp_names[i] = pin->pin.name; 1200 } 1201 1202 return 0; 1203 } 1204 1205 int stm32_pctl_probe(struct platform_device *pdev) 1206 { 1207 struct device_node *np = pdev->dev.of_node; 1208 struct device_node *child; 1209 const struct of_device_id *match; 1210 struct device *dev = &pdev->dev; 1211 struct stm32_pinctrl *pctl; 1212 struct pinctrl_pin_desc *pins; 1213 int i, ret, hwlock_id, banks = 0; 1214 1215 if (!np) 1216 return -EINVAL; 1217 1218 match = of_match_device(dev->driver->of_match_table, dev); 1219 if (!match || !match->data) 1220 return -EINVAL; 1221 1222 if (!of_find_property(np, "pins-are-numbered", NULL)) { 1223 dev_err(dev, "only support pins-are-numbered format\n"); 1224 return -EINVAL; 1225 } 1226 1227 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL); 1228 if (!pctl) 1229 return -ENOMEM; 1230 1231 platform_set_drvdata(pdev, pctl); 1232 1233 /* hwspinlock is optional */ 1234 hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0); 1235 if (hwlock_id < 0) { 1236 if (hwlock_id == -EPROBE_DEFER) 1237 return hwlock_id; 1238 } else { 1239 pctl->hwlock = hwspin_lock_request_specific(hwlock_id); 1240 } 1241 1242 pctl->dev = dev; 1243 pctl->match_data = match->data; 1244 ret = stm32_pctrl_build_state(pdev); 1245 if (ret) { 1246 dev_err(dev, "build state failed: %d\n", ret); 1247 return -EINVAL; 1248 } 1249 1250 if (of_find_property(np, "interrupt-parent", NULL)) { 1251 ret = stm32_pctrl_dt_setup_irq(pdev, pctl); 1252 if (ret) 1253 return ret; 1254 } 1255 1256 pins = devm_kcalloc(&pdev->dev, pctl->match_data->npins, sizeof(*pins), 1257 GFP_KERNEL); 1258 if (!pins) 1259 return -ENOMEM; 1260 1261 for (i = 0; i < pctl->match_data->npins; i++) 1262 pins[i] = pctl->match_data->pins[i].pin; 1263 1264 pctl->pctl_desc.name = dev_name(&pdev->dev); 1265 pctl->pctl_desc.owner = THIS_MODULE; 1266 pctl->pctl_desc.pins = pins; 1267 pctl->pctl_desc.npins = pctl->match_data->npins; 1268 pctl->pctl_desc.confops = &stm32_pconf_ops; 1269 pctl->pctl_desc.pctlops = &stm32_pctrl_ops; 1270 pctl->pctl_desc.pmxops = &stm32_pmx_ops; 1271 pctl->dev = &pdev->dev; 1272 1273 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc, 1274 pctl); 1275 1276 if (IS_ERR(pctl->pctl_dev)) { 1277 dev_err(&pdev->dev, "Failed pinctrl registration\n"); 1278 return PTR_ERR(pctl->pctl_dev); 1279 } 1280 1281 for_each_available_child_of_node(np, child) 1282 if (of_property_read_bool(child, "gpio-controller")) 1283 banks++; 1284 1285 if (!banks) { 1286 dev_err(dev, "at least one GPIO bank is required\n"); 1287 return -EINVAL; 1288 } 1289 pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks), 1290 GFP_KERNEL); 1291 if (!pctl->banks) 1292 return -ENOMEM; 1293 1294 for_each_available_child_of_node(np, child) { 1295 if (of_property_read_bool(child, "gpio-controller")) { 1296 ret = stm32_gpiolib_register_bank(pctl, child); 1297 if (ret) 1298 return ret; 1299 1300 pctl->nbanks++; 1301 } 1302 } 1303 1304 dev_info(dev, "Pinctrl STM32 initialized\n"); 1305 1306 return 0; 1307 } 1308 1309