1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics 2017 5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 * 7 * Heavily based on Mediatek's pinctrl driver 8 */ 9 #include <linux/clk.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/hwspinlock.h> 12 #include <linux/io.h> 13 #include <linux/irq.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/of_address.h> 18 #include <linux/of_device.h> 19 #include <linux/of_irq.h> 20 #include <linux/pinctrl/consumer.h> 21 #include <linux/pinctrl/machine.h> 22 #include <linux/pinctrl/pinconf.h> 23 #include <linux/pinctrl/pinconf-generic.h> 24 #include <linux/pinctrl/pinctrl.h> 25 #include <linux/pinctrl/pinmux.h> 26 #include <linux/platform_device.h> 27 #include <linux/property.h> 28 #include <linux/regmap.h> 29 #include <linux/reset.h> 30 #include <linux/slab.h> 31 32 #include "../core.h" 33 #include "../pinconf.h" 34 #include "../pinctrl-utils.h" 35 #include "pinctrl-stm32.h" 36 37 #define STM32_GPIO_MODER 0x00 38 #define STM32_GPIO_TYPER 0x04 39 #define STM32_GPIO_SPEEDR 0x08 40 #define STM32_GPIO_PUPDR 0x0c 41 #define STM32_GPIO_IDR 0x10 42 #define STM32_GPIO_ODR 0x14 43 #define STM32_GPIO_BSRR 0x18 44 #define STM32_GPIO_LCKR 0x1c 45 #define STM32_GPIO_AFRL 0x20 46 #define STM32_GPIO_AFRH 0x24 47 #define STM32_GPIO_SECCFGR 0x30 48 49 /* custom bitfield to backup pin status */ 50 #define STM32_GPIO_BKP_MODE_SHIFT 0 51 #define STM32_GPIO_BKP_MODE_MASK GENMASK(1, 0) 52 #define STM32_GPIO_BKP_ALT_SHIFT 2 53 #define STM32_GPIO_BKP_ALT_MASK GENMASK(5, 2) 54 #define STM32_GPIO_BKP_SPEED_SHIFT 6 55 #define STM32_GPIO_BKP_SPEED_MASK GENMASK(7, 6) 56 #define STM32_GPIO_BKP_PUPD_SHIFT 8 57 #define STM32_GPIO_BKP_PUPD_MASK GENMASK(9, 8) 58 #define STM32_GPIO_BKP_TYPE 10 59 #define STM32_GPIO_BKP_VAL 11 60 61 #define STM32_GPIO_PINS_PER_BANK 16 62 #define STM32_GPIO_IRQ_LINE 16 63 64 #define SYSCFG_IRQMUX_MASK GENMASK(3, 0) 65 66 #define gpio_range_to_bank(chip) \ 67 container_of(chip, struct stm32_gpio_bank, range) 68 69 #define HWSPNLCK_TIMEOUT 1000 /* usec */ 70 71 static const char * const stm32_gpio_functions[] = { 72 "gpio", "af0", "af1", 73 "af2", "af3", "af4", 74 "af5", "af6", "af7", 75 "af8", "af9", "af10", 76 "af11", "af12", "af13", 77 "af14", "af15", "analog", 78 }; 79 80 struct stm32_pinctrl_group { 81 const char *name; 82 unsigned long config; 83 unsigned pin; 84 }; 85 86 struct stm32_gpio_bank { 87 void __iomem *base; 88 struct clk *clk; 89 struct reset_control *rstc; 90 spinlock_t lock; 91 struct gpio_chip gpio_chip; 92 struct pinctrl_gpio_range range; 93 struct fwnode_handle *fwnode; 94 struct irq_domain *domain; 95 u32 bank_nr; 96 u32 bank_ioport_nr; 97 u32 pin_backup[STM32_GPIO_PINS_PER_BANK]; 98 u8 irq_type[STM32_GPIO_PINS_PER_BANK]; 99 bool secure_control; 100 }; 101 102 struct stm32_pinctrl { 103 struct device *dev; 104 struct pinctrl_dev *pctl_dev; 105 struct pinctrl_desc pctl_desc; 106 struct stm32_pinctrl_group *groups; 107 unsigned ngroups; 108 const char **grp_names; 109 struct stm32_gpio_bank *banks; 110 unsigned nbanks; 111 const struct stm32_pinctrl_match_data *match_data; 112 struct irq_domain *domain; 113 struct regmap *regmap; 114 struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK]; 115 struct hwspinlock *hwlock; 116 struct stm32_desc_pin *pins; 117 u32 npins; 118 u32 pkg; 119 u16 irqmux_map; 120 spinlock_t irqmux_lock; 121 }; 122 123 static inline int stm32_gpio_pin(int gpio) 124 { 125 return gpio % STM32_GPIO_PINS_PER_BANK; 126 } 127 128 static inline u32 stm32_gpio_get_mode(u32 function) 129 { 130 switch (function) { 131 case STM32_PIN_GPIO: 132 return 0; 133 case STM32_PIN_AF(0) ... STM32_PIN_AF(15): 134 return 2; 135 case STM32_PIN_ANALOG: 136 return 3; 137 } 138 139 return 0; 140 } 141 142 static inline u32 stm32_gpio_get_alt(u32 function) 143 { 144 switch (function) { 145 case STM32_PIN_GPIO: 146 return 0; 147 case STM32_PIN_AF(0) ... STM32_PIN_AF(15): 148 return function - 1; 149 case STM32_PIN_ANALOG: 150 return 0; 151 } 152 153 return 0; 154 } 155 156 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank, 157 u32 offset, u32 value) 158 { 159 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL); 160 bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL; 161 } 162 163 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset, 164 u32 mode, u32 alt) 165 { 166 bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK | 167 STM32_GPIO_BKP_ALT_MASK); 168 bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT; 169 bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT; 170 } 171 172 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset, 173 u32 drive) 174 { 175 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE); 176 bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE; 177 } 178 179 static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset, 180 u32 speed) 181 { 182 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK; 183 bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT; 184 } 185 186 static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset, 187 u32 bias) 188 { 189 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK; 190 bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT; 191 } 192 193 /* GPIO functions */ 194 195 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank, 196 unsigned offset, int value) 197 { 198 stm32_gpio_backup_value(bank, offset, value); 199 200 if (!value) 201 offset += STM32_GPIO_PINS_PER_BANK; 202 203 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR); 204 } 205 206 static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset) 207 { 208 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 209 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 210 struct pinctrl_gpio_range *range; 211 int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK); 212 213 range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin); 214 if (!range) { 215 dev_err(pctl->dev, "pin %d not in range.\n", pin); 216 return -EINVAL; 217 } 218 219 return pinctrl_gpio_request(chip->base + offset); 220 } 221 222 static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset) 223 { 224 pinctrl_gpio_free(chip->base + offset); 225 } 226 227 static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset) 228 { 229 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 230 231 return !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset)); 232 } 233 234 static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 235 { 236 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 237 238 __stm32_gpio_set(bank, offset, value); 239 } 240 241 static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 242 { 243 return pinctrl_gpio_direction_input(chip->base + offset); 244 } 245 246 static int stm32_gpio_direction_output(struct gpio_chip *chip, 247 unsigned offset, int value) 248 { 249 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 250 251 __stm32_gpio_set(bank, offset, value); 252 pinctrl_gpio_direction_output(chip->base + offset); 253 254 return 0; 255 } 256 257 258 static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) 259 { 260 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 261 struct irq_fwspec fwspec; 262 263 fwspec.fwnode = bank->fwnode; 264 fwspec.param_count = 2; 265 fwspec.param[0] = offset; 266 fwspec.param[1] = IRQ_TYPE_NONE; 267 268 return irq_create_fwspec_mapping(&fwspec); 269 } 270 271 static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 272 { 273 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 274 int pin = stm32_gpio_pin(offset); 275 int ret; 276 u32 mode, alt; 277 278 stm32_pmx_get_mode(bank, pin, &mode, &alt); 279 if ((alt == 0) && (mode == 0)) 280 ret = GPIO_LINE_DIRECTION_IN; 281 else if ((alt == 0) && (mode == 1)) 282 ret = GPIO_LINE_DIRECTION_OUT; 283 else 284 ret = -EINVAL; 285 286 return ret; 287 } 288 289 static int stm32_gpio_init_valid_mask(struct gpio_chip *chip, 290 unsigned long *valid_mask, 291 unsigned int ngpios) 292 { 293 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 294 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 295 unsigned int i; 296 u32 sec; 297 298 /* All gpio are valid per default */ 299 bitmap_fill(valid_mask, ngpios); 300 301 if (bank->secure_control) { 302 /* Tag secured pins as invalid */ 303 sec = readl_relaxed(bank->base + STM32_GPIO_SECCFGR); 304 305 for (i = 0; i < ngpios; i++) { 306 if (sec & BIT(i)) { 307 clear_bit(i, valid_mask); 308 dev_dbg(pctl->dev, "No access to gpio %d - %d\n", bank->bank_nr, i); 309 } 310 } 311 } 312 313 return 0; 314 } 315 316 static const struct gpio_chip stm32_gpio_template = { 317 .request = stm32_gpio_request, 318 .free = stm32_gpio_free, 319 .get = stm32_gpio_get, 320 .set = stm32_gpio_set, 321 .direction_input = stm32_gpio_direction_input, 322 .direction_output = stm32_gpio_direction_output, 323 .to_irq = stm32_gpio_to_irq, 324 .get_direction = stm32_gpio_get_direction, 325 .set_config = gpiochip_generic_config, 326 .init_valid_mask = stm32_gpio_init_valid_mask, 327 }; 328 329 static void stm32_gpio_irq_trigger(struct irq_data *d) 330 { 331 struct stm32_gpio_bank *bank = d->domain->host_data; 332 int level; 333 334 /* Do not access the GPIO if this is not LEVEL triggered IRQ. */ 335 if (!(bank->irq_type[d->hwirq] & IRQ_TYPE_LEVEL_MASK)) 336 return; 337 338 /* If level interrupt type then retrig */ 339 level = stm32_gpio_get(&bank->gpio_chip, d->hwirq); 340 if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) || 341 (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH)) 342 irq_chip_retrigger_hierarchy(d); 343 } 344 345 static void stm32_gpio_irq_eoi(struct irq_data *d) 346 { 347 irq_chip_eoi_parent(d); 348 stm32_gpio_irq_trigger(d); 349 }; 350 351 static int stm32_gpio_set_type(struct irq_data *d, unsigned int type) 352 { 353 struct stm32_gpio_bank *bank = d->domain->host_data; 354 u32 parent_type; 355 356 switch (type) { 357 case IRQ_TYPE_EDGE_RISING: 358 case IRQ_TYPE_EDGE_FALLING: 359 case IRQ_TYPE_EDGE_BOTH: 360 parent_type = type; 361 break; 362 case IRQ_TYPE_LEVEL_HIGH: 363 parent_type = IRQ_TYPE_EDGE_RISING; 364 break; 365 case IRQ_TYPE_LEVEL_LOW: 366 parent_type = IRQ_TYPE_EDGE_FALLING; 367 break; 368 default: 369 return -EINVAL; 370 } 371 372 bank->irq_type[d->hwirq] = type; 373 374 return irq_chip_set_type_parent(d, parent_type); 375 }; 376 377 static int stm32_gpio_irq_request_resources(struct irq_data *irq_data) 378 { 379 struct stm32_gpio_bank *bank = irq_data->domain->host_data; 380 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 381 int ret; 382 383 ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq); 384 if (ret) 385 return ret; 386 387 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq); 388 if (ret) { 389 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", 390 irq_data->hwirq); 391 return ret; 392 } 393 394 return 0; 395 } 396 397 static void stm32_gpio_irq_release_resources(struct irq_data *irq_data) 398 { 399 struct stm32_gpio_bank *bank = irq_data->domain->host_data; 400 401 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq); 402 } 403 404 static void stm32_gpio_irq_unmask(struct irq_data *d) 405 { 406 irq_chip_unmask_parent(d); 407 stm32_gpio_irq_trigger(d); 408 } 409 410 static struct irq_chip stm32_gpio_irq_chip = { 411 .name = "stm32gpio", 412 .irq_eoi = stm32_gpio_irq_eoi, 413 .irq_ack = irq_chip_ack_parent, 414 .irq_mask = irq_chip_mask_parent, 415 .irq_unmask = stm32_gpio_irq_unmask, 416 .irq_set_type = stm32_gpio_set_type, 417 .irq_set_wake = irq_chip_set_wake_parent, 418 .irq_request_resources = stm32_gpio_irq_request_resources, 419 .irq_release_resources = stm32_gpio_irq_release_resources, 420 }; 421 422 static int stm32_gpio_domain_translate(struct irq_domain *d, 423 struct irq_fwspec *fwspec, 424 unsigned long *hwirq, 425 unsigned int *type) 426 { 427 if ((fwspec->param_count != 2) || 428 (fwspec->param[0] >= STM32_GPIO_IRQ_LINE)) 429 return -EINVAL; 430 431 *hwirq = fwspec->param[0]; 432 *type = fwspec->param[1]; 433 return 0; 434 } 435 436 static int stm32_gpio_domain_activate(struct irq_domain *d, 437 struct irq_data *irq_data, bool reserve) 438 { 439 struct stm32_gpio_bank *bank = d->host_data; 440 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 441 int ret = 0; 442 443 if (pctl->hwlock) { 444 ret = hwspin_lock_timeout_in_atomic(pctl->hwlock, 445 HWSPNLCK_TIMEOUT); 446 if (ret) { 447 dev_err(pctl->dev, "Can't get hwspinlock\n"); 448 return ret; 449 } 450 } 451 452 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr); 453 454 if (pctl->hwlock) 455 hwspin_unlock_in_atomic(pctl->hwlock); 456 457 return ret; 458 } 459 460 static int stm32_gpio_domain_alloc(struct irq_domain *d, 461 unsigned int virq, 462 unsigned int nr_irqs, void *data) 463 { 464 struct stm32_gpio_bank *bank = d->host_data; 465 struct irq_fwspec *fwspec = data; 466 struct irq_fwspec parent_fwspec; 467 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 468 irq_hw_number_t hwirq = fwspec->param[0]; 469 unsigned long flags; 470 int ret = 0; 471 472 /* 473 * Check first that the IRQ MUX of that line is free. 474 * gpio irq mux is shared between several banks, protect with a lock 475 */ 476 spin_lock_irqsave(&pctl->irqmux_lock, flags); 477 478 if (pctl->irqmux_map & BIT(hwirq)) { 479 dev_err(pctl->dev, "irq line %ld already requested.\n", hwirq); 480 ret = -EBUSY; 481 } else { 482 pctl->irqmux_map |= BIT(hwirq); 483 } 484 485 spin_unlock_irqrestore(&pctl->irqmux_lock, flags); 486 if (ret) 487 return ret; 488 489 parent_fwspec.fwnode = d->parent->fwnode; 490 parent_fwspec.param_count = 2; 491 parent_fwspec.param[0] = fwspec->param[0]; 492 parent_fwspec.param[1] = fwspec->param[1]; 493 494 irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip, 495 bank); 496 497 return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec); 498 } 499 500 static void stm32_gpio_domain_free(struct irq_domain *d, unsigned int virq, 501 unsigned int nr_irqs) 502 { 503 struct stm32_gpio_bank *bank = d->host_data; 504 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 505 struct irq_data *irq_data = irq_domain_get_irq_data(d, virq); 506 unsigned long flags, hwirq = irq_data->hwirq; 507 508 irq_domain_free_irqs_common(d, virq, nr_irqs); 509 510 spin_lock_irqsave(&pctl->irqmux_lock, flags); 511 pctl->irqmux_map &= ~BIT(hwirq); 512 spin_unlock_irqrestore(&pctl->irqmux_lock, flags); 513 } 514 515 static const struct irq_domain_ops stm32_gpio_domain_ops = { 516 .translate = stm32_gpio_domain_translate, 517 .alloc = stm32_gpio_domain_alloc, 518 .free = stm32_gpio_domain_free, 519 .activate = stm32_gpio_domain_activate, 520 }; 521 522 /* Pinctrl functions */ 523 static struct stm32_pinctrl_group * 524 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin) 525 { 526 int i; 527 528 for (i = 0; i < pctl->ngroups; i++) { 529 struct stm32_pinctrl_group *grp = pctl->groups + i; 530 531 if (grp->pin == pin) 532 return grp; 533 } 534 535 return NULL; 536 } 537 538 static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl, 539 u32 pin_num, u32 fnum) 540 { 541 int i, k; 542 543 for (i = 0; i < pctl->npins; i++) { 544 const struct stm32_desc_pin *pin = pctl->pins + i; 545 const struct stm32_desc_function *func = pin->functions; 546 547 if (pin->pin.number != pin_num) 548 continue; 549 550 for (k = 0; k < STM32_CONFIG_NUM; k++) { 551 if (func->num == fnum) 552 return true; 553 func++; 554 } 555 556 break; 557 } 558 559 dev_err(pctl->dev, "invalid function %d on pin %d .\n", fnum, pin_num); 560 561 return false; 562 } 563 564 static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl, 565 u32 pin, u32 fnum, struct stm32_pinctrl_group *grp, 566 struct pinctrl_map **map, unsigned *reserved_maps, 567 unsigned *num_maps) 568 { 569 if (*num_maps == *reserved_maps) 570 return -ENOSPC; 571 572 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; 573 (*map)[*num_maps].data.mux.group = grp->name; 574 575 if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) 576 return -EINVAL; 577 578 (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum]; 579 (*num_maps)++; 580 581 return 0; 582 } 583 584 static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, 585 struct device_node *node, 586 struct pinctrl_map **map, 587 unsigned *reserved_maps, 588 unsigned *num_maps) 589 { 590 struct stm32_pinctrl *pctl; 591 struct stm32_pinctrl_group *grp; 592 struct property *pins; 593 u32 pinfunc, pin, func; 594 unsigned long *configs; 595 unsigned int num_configs; 596 bool has_config = 0; 597 unsigned reserve = 0; 598 int num_pins, num_funcs, maps_per_pin, i, err = 0; 599 600 pctl = pinctrl_dev_get_drvdata(pctldev); 601 602 pins = of_find_property(node, "pinmux", NULL); 603 if (!pins) { 604 dev_err(pctl->dev, "missing pins property in node %pOFn .\n", 605 node); 606 return -EINVAL; 607 } 608 609 err = pinconf_generic_parse_dt_config(node, pctldev, &configs, 610 &num_configs); 611 if (err) 612 return err; 613 614 if (num_configs) 615 has_config = 1; 616 617 num_pins = pins->length / sizeof(u32); 618 num_funcs = num_pins; 619 maps_per_pin = 0; 620 if (num_funcs) 621 maps_per_pin++; 622 if (has_config && num_pins >= 1) 623 maps_per_pin++; 624 625 if (!num_pins || !maps_per_pin) { 626 err = -EINVAL; 627 goto exit; 628 } 629 630 reserve = num_pins * maps_per_pin; 631 632 err = pinctrl_utils_reserve_map(pctldev, map, 633 reserved_maps, num_maps, reserve); 634 if (err) 635 goto exit; 636 637 for (i = 0; i < num_pins; i++) { 638 err = of_property_read_u32_index(node, "pinmux", 639 i, &pinfunc); 640 if (err) 641 goto exit; 642 643 pin = STM32_GET_PIN_NO(pinfunc); 644 func = STM32_GET_PIN_FUNC(pinfunc); 645 646 if (!stm32_pctrl_is_function_valid(pctl, pin, func)) { 647 err = -EINVAL; 648 goto exit; 649 } 650 651 grp = stm32_pctrl_find_group_by_pin(pctl, pin); 652 if (!grp) { 653 dev_err(pctl->dev, "unable to match pin %d to group\n", 654 pin); 655 err = -EINVAL; 656 goto exit; 657 } 658 659 err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map, 660 reserved_maps, num_maps); 661 if (err) 662 goto exit; 663 664 if (has_config) { 665 err = pinctrl_utils_add_map_configs(pctldev, map, 666 reserved_maps, num_maps, grp->name, 667 configs, num_configs, 668 PIN_MAP_TYPE_CONFIGS_GROUP); 669 if (err) 670 goto exit; 671 } 672 } 673 674 exit: 675 kfree(configs); 676 return err; 677 } 678 679 static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 680 struct device_node *np_config, 681 struct pinctrl_map **map, unsigned *num_maps) 682 { 683 struct device_node *np; 684 unsigned reserved_maps; 685 int ret; 686 687 *map = NULL; 688 *num_maps = 0; 689 reserved_maps = 0; 690 691 for_each_child_of_node(np_config, np) { 692 ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map, 693 &reserved_maps, num_maps); 694 if (ret < 0) { 695 pinctrl_utils_free_map(pctldev, *map, *num_maps); 696 of_node_put(np); 697 return ret; 698 } 699 } 700 701 return 0; 702 } 703 704 static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev) 705 { 706 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 707 708 return pctl->ngroups; 709 } 710 711 static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev, 712 unsigned group) 713 { 714 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 715 716 return pctl->groups[group].name; 717 } 718 719 static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev, 720 unsigned group, 721 const unsigned **pins, 722 unsigned *num_pins) 723 { 724 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 725 726 *pins = (unsigned *)&pctl->groups[group].pin; 727 *num_pins = 1; 728 729 return 0; 730 } 731 732 static const struct pinctrl_ops stm32_pctrl_ops = { 733 .dt_node_to_map = stm32_pctrl_dt_node_to_map, 734 .dt_free_map = pinctrl_utils_free_map, 735 .get_groups_count = stm32_pctrl_get_groups_count, 736 .get_group_name = stm32_pctrl_get_group_name, 737 .get_group_pins = stm32_pctrl_get_group_pins, 738 }; 739 740 741 /* Pinmux functions */ 742 743 static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 744 { 745 return ARRAY_SIZE(stm32_gpio_functions); 746 } 747 748 static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev, 749 unsigned selector) 750 { 751 return stm32_gpio_functions[selector]; 752 } 753 754 static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev, 755 unsigned function, 756 const char * const **groups, 757 unsigned * const num_groups) 758 { 759 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 760 761 *groups = pctl->grp_names; 762 *num_groups = pctl->ngroups; 763 764 return 0; 765 } 766 767 static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank, 768 int pin, u32 mode, u32 alt) 769 { 770 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 771 u32 val; 772 int alt_shift = (pin % 8) * 4; 773 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; 774 unsigned long flags; 775 int err = 0; 776 777 spin_lock_irqsave(&bank->lock, flags); 778 779 if (pctl->hwlock) { 780 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, 781 HWSPNLCK_TIMEOUT); 782 if (err) { 783 dev_err(pctl->dev, "Can't get hwspinlock\n"); 784 goto unlock; 785 } 786 } 787 788 val = readl_relaxed(bank->base + alt_offset); 789 val &= ~GENMASK(alt_shift + 3, alt_shift); 790 val |= (alt << alt_shift); 791 writel_relaxed(val, bank->base + alt_offset); 792 793 val = readl_relaxed(bank->base + STM32_GPIO_MODER); 794 val &= ~GENMASK(pin * 2 + 1, pin * 2); 795 val |= mode << (pin * 2); 796 writel_relaxed(val, bank->base + STM32_GPIO_MODER); 797 798 if (pctl->hwlock) 799 hwspin_unlock_in_atomic(pctl->hwlock); 800 801 stm32_gpio_backup_mode(bank, pin, mode, alt); 802 803 unlock: 804 spin_unlock_irqrestore(&bank->lock, flags); 805 806 return err; 807 } 808 809 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, 810 u32 *alt) 811 { 812 u32 val; 813 int alt_shift = (pin % 8) * 4; 814 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; 815 unsigned long flags; 816 817 spin_lock_irqsave(&bank->lock, flags); 818 819 val = readl_relaxed(bank->base + alt_offset); 820 val &= GENMASK(alt_shift + 3, alt_shift); 821 *alt = val >> alt_shift; 822 823 val = readl_relaxed(bank->base + STM32_GPIO_MODER); 824 val &= GENMASK(pin * 2 + 1, pin * 2); 825 *mode = val >> (pin * 2); 826 827 spin_unlock_irqrestore(&bank->lock, flags); 828 } 829 830 static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev, 831 unsigned function, 832 unsigned group) 833 { 834 bool ret; 835 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 836 struct stm32_pinctrl_group *g = pctl->groups + group; 837 struct pinctrl_gpio_range *range; 838 struct stm32_gpio_bank *bank; 839 u32 mode, alt; 840 int pin; 841 842 ret = stm32_pctrl_is_function_valid(pctl, g->pin, function); 843 if (!ret) 844 return -EINVAL; 845 846 range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin); 847 if (!range) { 848 dev_err(pctl->dev, "No gpio range defined.\n"); 849 return -EINVAL; 850 } 851 852 bank = gpiochip_get_data(range->gc); 853 pin = stm32_gpio_pin(g->pin); 854 855 mode = stm32_gpio_get_mode(function); 856 alt = stm32_gpio_get_alt(function); 857 858 return stm32_pmx_set_mode(bank, pin, mode, alt); 859 } 860 861 static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 862 struct pinctrl_gpio_range *range, unsigned gpio, 863 bool input) 864 { 865 struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc); 866 int pin = stm32_gpio_pin(gpio); 867 868 return stm32_pmx_set_mode(bank, pin, !input, 0); 869 } 870 871 static int stm32_pmx_request(struct pinctrl_dev *pctldev, unsigned int gpio) 872 { 873 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 874 struct pinctrl_gpio_range *range; 875 876 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, gpio); 877 if (!range) { 878 dev_err(pctl->dev, "No gpio range defined.\n"); 879 return -EINVAL; 880 } 881 882 if (!gpiochip_line_is_valid(range->gc, stm32_gpio_pin(gpio))) { 883 dev_warn(pctl->dev, "Can't access gpio %d\n", gpio); 884 return -EACCES; 885 } 886 887 return 0; 888 } 889 890 static const struct pinmux_ops stm32_pmx_ops = { 891 .get_functions_count = stm32_pmx_get_funcs_cnt, 892 .get_function_name = stm32_pmx_get_func_name, 893 .get_function_groups = stm32_pmx_get_func_groups, 894 .set_mux = stm32_pmx_set_mux, 895 .gpio_set_direction = stm32_pmx_gpio_set_direction, 896 .request = stm32_pmx_request, 897 .strict = true, 898 }; 899 900 /* Pinconf functions */ 901 902 static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank, 903 unsigned offset, u32 drive) 904 { 905 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 906 unsigned long flags; 907 u32 val; 908 int err = 0; 909 910 spin_lock_irqsave(&bank->lock, flags); 911 912 if (pctl->hwlock) { 913 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, 914 HWSPNLCK_TIMEOUT); 915 if (err) { 916 dev_err(pctl->dev, "Can't get hwspinlock\n"); 917 goto unlock; 918 } 919 } 920 921 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); 922 val &= ~BIT(offset); 923 val |= drive << offset; 924 writel_relaxed(val, bank->base + STM32_GPIO_TYPER); 925 926 if (pctl->hwlock) 927 hwspin_unlock_in_atomic(pctl->hwlock); 928 929 stm32_gpio_backup_driving(bank, offset, drive); 930 931 unlock: 932 spin_unlock_irqrestore(&bank->lock, flags); 933 934 return err; 935 } 936 937 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank, 938 unsigned int offset) 939 { 940 unsigned long flags; 941 u32 val; 942 943 spin_lock_irqsave(&bank->lock, flags); 944 945 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); 946 val &= BIT(offset); 947 948 spin_unlock_irqrestore(&bank->lock, flags); 949 950 return (val >> offset); 951 } 952 953 static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank, 954 unsigned offset, u32 speed) 955 { 956 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 957 unsigned long flags; 958 u32 val; 959 int err = 0; 960 961 spin_lock_irqsave(&bank->lock, flags); 962 963 if (pctl->hwlock) { 964 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, 965 HWSPNLCK_TIMEOUT); 966 if (err) { 967 dev_err(pctl->dev, "Can't get hwspinlock\n"); 968 goto unlock; 969 } 970 } 971 972 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); 973 val &= ~GENMASK(offset * 2 + 1, offset * 2); 974 val |= speed << (offset * 2); 975 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR); 976 977 if (pctl->hwlock) 978 hwspin_unlock_in_atomic(pctl->hwlock); 979 980 stm32_gpio_backup_speed(bank, offset, speed); 981 982 unlock: 983 spin_unlock_irqrestore(&bank->lock, flags); 984 985 return err; 986 } 987 988 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank, 989 unsigned int offset) 990 { 991 unsigned long flags; 992 u32 val; 993 994 spin_lock_irqsave(&bank->lock, flags); 995 996 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); 997 val &= GENMASK(offset * 2 + 1, offset * 2); 998 999 spin_unlock_irqrestore(&bank->lock, flags); 1000 1001 return (val >> (offset * 2)); 1002 } 1003 1004 static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank, 1005 unsigned offset, u32 bias) 1006 { 1007 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 1008 unsigned long flags; 1009 u32 val; 1010 int err = 0; 1011 1012 spin_lock_irqsave(&bank->lock, flags); 1013 1014 if (pctl->hwlock) { 1015 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, 1016 HWSPNLCK_TIMEOUT); 1017 if (err) { 1018 dev_err(pctl->dev, "Can't get hwspinlock\n"); 1019 goto unlock; 1020 } 1021 } 1022 1023 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); 1024 val &= ~GENMASK(offset * 2 + 1, offset * 2); 1025 val |= bias << (offset * 2); 1026 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR); 1027 1028 if (pctl->hwlock) 1029 hwspin_unlock_in_atomic(pctl->hwlock); 1030 1031 stm32_gpio_backup_bias(bank, offset, bias); 1032 1033 unlock: 1034 spin_unlock_irqrestore(&bank->lock, flags); 1035 1036 return err; 1037 } 1038 1039 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank, 1040 unsigned int offset) 1041 { 1042 unsigned long flags; 1043 u32 val; 1044 1045 spin_lock_irqsave(&bank->lock, flags); 1046 1047 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); 1048 val &= GENMASK(offset * 2 + 1, offset * 2); 1049 1050 spin_unlock_irqrestore(&bank->lock, flags); 1051 1052 return (val >> (offset * 2)); 1053 } 1054 1055 static bool stm32_pconf_get(struct stm32_gpio_bank *bank, 1056 unsigned int offset, bool dir) 1057 { 1058 unsigned long flags; 1059 u32 val; 1060 1061 spin_lock_irqsave(&bank->lock, flags); 1062 1063 if (dir) 1064 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & 1065 BIT(offset)); 1066 else 1067 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) & 1068 BIT(offset)); 1069 1070 spin_unlock_irqrestore(&bank->lock, flags); 1071 1072 return val; 1073 } 1074 1075 static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev, 1076 unsigned int pin, enum pin_config_param param, 1077 enum pin_config_param arg) 1078 { 1079 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1080 struct pinctrl_gpio_range *range; 1081 struct stm32_gpio_bank *bank; 1082 int offset, ret = 0; 1083 1084 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); 1085 if (!range) { 1086 dev_err(pctl->dev, "No gpio range defined.\n"); 1087 return -EINVAL; 1088 } 1089 1090 bank = gpiochip_get_data(range->gc); 1091 offset = stm32_gpio_pin(pin); 1092 1093 if (!gpiochip_line_is_valid(range->gc, offset)) { 1094 dev_warn(pctl->dev, "Can't access gpio %d\n", pin); 1095 return -EACCES; 1096 } 1097 1098 switch (param) { 1099 case PIN_CONFIG_DRIVE_PUSH_PULL: 1100 ret = stm32_pconf_set_driving(bank, offset, 0); 1101 break; 1102 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1103 ret = stm32_pconf_set_driving(bank, offset, 1); 1104 break; 1105 case PIN_CONFIG_SLEW_RATE: 1106 ret = stm32_pconf_set_speed(bank, offset, arg); 1107 break; 1108 case PIN_CONFIG_BIAS_DISABLE: 1109 ret = stm32_pconf_set_bias(bank, offset, 0); 1110 break; 1111 case PIN_CONFIG_BIAS_PULL_UP: 1112 ret = stm32_pconf_set_bias(bank, offset, 1); 1113 break; 1114 case PIN_CONFIG_BIAS_PULL_DOWN: 1115 ret = stm32_pconf_set_bias(bank, offset, 2); 1116 break; 1117 case PIN_CONFIG_OUTPUT: 1118 __stm32_gpio_set(bank, offset, arg); 1119 ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false); 1120 break; 1121 default: 1122 ret = -ENOTSUPP; 1123 } 1124 1125 return ret; 1126 } 1127 1128 static int stm32_pconf_group_get(struct pinctrl_dev *pctldev, 1129 unsigned group, 1130 unsigned long *config) 1131 { 1132 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1133 1134 *config = pctl->groups[group].config; 1135 1136 return 0; 1137 } 1138 1139 static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, 1140 unsigned long *configs, unsigned num_configs) 1141 { 1142 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1143 struct stm32_pinctrl_group *g = &pctl->groups[group]; 1144 int i, ret; 1145 1146 for (i = 0; i < num_configs; i++) { 1147 mutex_lock(&pctldev->mutex); 1148 ret = stm32_pconf_parse_conf(pctldev, g->pin, 1149 pinconf_to_config_param(configs[i]), 1150 pinconf_to_config_argument(configs[i])); 1151 mutex_unlock(&pctldev->mutex); 1152 if (ret < 0) 1153 return ret; 1154 1155 g->config = configs[i]; 1156 } 1157 1158 return 0; 1159 } 1160 1161 static int stm32_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 1162 unsigned long *configs, unsigned int num_configs) 1163 { 1164 int i, ret; 1165 1166 for (i = 0; i < num_configs; i++) { 1167 ret = stm32_pconf_parse_conf(pctldev, pin, 1168 pinconf_to_config_param(configs[i]), 1169 pinconf_to_config_argument(configs[i])); 1170 if (ret < 0) 1171 return ret; 1172 } 1173 1174 return 0; 1175 } 1176 1177 static struct stm32_desc_pin * 1178 stm32_pconf_get_pin_desc_by_pin_number(struct stm32_pinctrl *pctl, 1179 unsigned int pin_number) 1180 { 1181 struct stm32_desc_pin *pins = pctl->pins; 1182 int i; 1183 1184 for (i = 0; i < pctl->npins; i++) { 1185 if (pins->pin.number == pin_number) 1186 return pins; 1187 pins++; 1188 } 1189 return NULL; 1190 } 1191 1192 static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev, 1193 struct seq_file *s, 1194 unsigned int pin) 1195 { 1196 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1197 const struct stm32_desc_pin *pin_desc; 1198 struct pinctrl_gpio_range *range; 1199 struct stm32_gpio_bank *bank; 1200 int offset; 1201 u32 mode, alt, drive, speed, bias; 1202 static const char * const modes[] = { 1203 "input", "output", "alternate", "analog" }; 1204 static const char * const speeds[] = { 1205 "low", "medium", "high", "very high" }; 1206 static const char * const biasing[] = { 1207 "floating", "pull up", "pull down", "" }; 1208 bool val; 1209 1210 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); 1211 if (!range) 1212 return; 1213 1214 bank = gpiochip_get_data(range->gc); 1215 offset = stm32_gpio_pin(pin); 1216 1217 if (!gpiochip_line_is_valid(range->gc, offset)) { 1218 seq_puts(s, "NO ACCESS"); 1219 return; 1220 } 1221 1222 stm32_pmx_get_mode(bank, offset, &mode, &alt); 1223 bias = stm32_pconf_get_bias(bank, offset); 1224 1225 seq_printf(s, "%s ", modes[mode]); 1226 1227 switch (mode) { 1228 /* input */ 1229 case 0: 1230 val = stm32_pconf_get(bank, offset, true); 1231 seq_printf(s, "- %s - %s", 1232 val ? "high" : "low", 1233 biasing[bias]); 1234 break; 1235 1236 /* output */ 1237 case 1: 1238 drive = stm32_pconf_get_driving(bank, offset); 1239 speed = stm32_pconf_get_speed(bank, offset); 1240 val = stm32_pconf_get(bank, offset, false); 1241 seq_printf(s, "- %s - %s - %s - %s %s", 1242 val ? "high" : "low", 1243 drive ? "open drain" : "push pull", 1244 biasing[bias], 1245 speeds[speed], "speed"); 1246 break; 1247 1248 /* alternate */ 1249 case 2: 1250 drive = stm32_pconf_get_driving(bank, offset); 1251 speed = stm32_pconf_get_speed(bank, offset); 1252 pin_desc = stm32_pconf_get_pin_desc_by_pin_number(pctl, pin); 1253 if (!pin_desc) 1254 return; 1255 1256 seq_printf(s, "%d (%s) - %s - %s - %s %s", alt, 1257 pin_desc->functions[alt + 1].name, 1258 drive ? "open drain" : "push pull", 1259 biasing[bias], 1260 speeds[speed], "speed"); 1261 break; 1262 1263 /* analog */ 1264 case 3: 1265 break; 1266 } 1267 } 1268 1269 static const struct pinconf_ops stm32_pconf_ops = { 1270 .pin_config_group_get = stm32_pconf_group_get, 1271 .pin_config_group_set = stm32_pconf_group_set, 1272 .pin_config_set = stm32_pconf_set, 1273 .pin_config_dbg_show = stm32_pconf_dbg_show, 1274 }; 1275 1276 static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, struct fwnode_handle *fwnode) 1277 { 1278 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks]; 1279 int bank_ioport_nr; 1280 struct pinctrl_gpio_range *range = &bank->range; 1281 struct fwnode_reference_args args; 1282 struct device *dev = pctl->dev; 1283 struct resource res; 1284 int npins = STM32_GPIO_PINS_PER_BANK; 1285 int bank_nr, err, i = 0; 1286 1287 if (!IS_ERR(bank->rstc)) 1288 reset_control_deassert(bank->rstc); 1289 1290 if (of_address_to_resource(to_of_node(fwnode), 0, &res)) 1291 return -ENODEV; 1292 1293 bank->base = devm_ioremap_resource(dev, &res); 1294 if (IS_ERR(bank->base)) 1295 return PTR_ERR(bank->base); 1296 1297 err = clk_prepare_enable(bank->clk); 1298 if (err) { 1299 dev_err(dev, "failed to prepare_enable clk (%d)\n", err); 1300 return err; 1301 } 1302 1303 bank->gpio_chip = stm32_gpio_template; 1304 1305 fwnode_property_read_string(fwnode, "st,bank-name", &bank->gpio_chip.label); 1306 1307 if (!fwnode_property_get_reference_args(fwnode, "gpio-ranges", NULL, 3, i, &args)) { 1308 bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK; 1309 bank->gpio_chip.base = args.args[1]; 1310 1311 /* get the last defined gpio line (offset + nb of pins) */ 1312 npins = args.args[0] + args.args[2]; 1313 while (!fwnode_property_get_reference_args(fwnode, "gpio-ranges", NULL, 3, ++i, &args)) 1314 npins = max(npins, (int)(args.args[0] + args.args[2])); 1315 } else { 1316 bank_nr = pctl->nbanks; 1317 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; 1318 range->name = bank->gpio_chip.label; 1319 range->id = bank_nr; 1320 range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK; 1321 range->base = range->id * STM32_GPIO_PINS_PER_BANK; 1322 range->npins = npins; 1323 range->gc = &bank->gpio_chip; 1324 pinctrl_add_gpio_range(pctl->pctl_dev, 1325 &pctl->banks[bank_nr].range); 1326 } 1327 1328 if (fwnode_property_read_u32(fwnode, "st,bank-ioport", &bank_ioport_nr)) 1329 bank_ioport_nr = bank_nr; 1330 1331 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; 1332 1333 bank->gpio_chip.ngpio = npins; 1334 bank->gpio_chip.fwnode = fwnode; 1335 bank->gpio_chip.parent = dev; 1336 bank->bank_nr = bank_nr; 1337 bank->bank_ioport_nr = bank_ioport_nr; 1338 bank->secure_control = pctl->match_data->secure_control; 1339 spin_lock_init(&bank->lock); 1340 1341 /* create irq hierarchical domain */ 1342 bank->fwnode = fwnode; 1343 1344 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, 1345 STM32_GPIO_IRQ_LINE, bank->fwnode, 1346 &stm32_gpio_domain_ops, bank); 1347 1348 if (!bank->domain) { 1349 err = -ENODEV; 1350 goto err_clk; 1351 } 1352 1353 err = gpiochip_add_data(&bank->gpio_chip, bank); 1354 if (err) { 1355 dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr); 1356 goto err_clk; 1357 } 1358 1359 dev_info(dev, "%s bank added\n", bank->gpio_chip.label); 1360 return 0; 1361 1362 err_clk: 1363 clk_disable_unprepare(bank->clk); 1364 return err; 1365 } 1366 1367 static struct irq_domain *stm32_pctrl_get_irq_domain(struct platform_device *pdev) 1368 { 1369 struct device_node *np = pdev->dev.of_node; 1370 struct device_node *parent; 1371 struct irq_domain *domain; 1372 1373 if (!of_find_property(np, "interrupt-parent", NULL)) 1374 return NULL; 1375 1376 parent = of_irq_find_parent(np); 1377 if (!parent) 1378 return ERR_PTR(-ENXIO); 1379 1380 domain = irq_find_host(parent); 1381 if (!domain) 1382 /* domain not registered yet */ 1383 return ERR_PTR(-EPROBE_DEFER); 1384 1385 return domain; 1386 } 1387 1388 static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev, 1389 struct stm32_pinctrl *pctl) 1390 { 1391 struct device_node *np = pdev->dev.of_node; 1392 struct device *dev = &pdev->dev; 1393 struct regmap *rm; 1394 int offset, ret, i; 1395 int mask, mask_width; 1396 1397 pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); 1398 if (IS_ERR(pctl->regmap)) 1399 return PTR_ERR(pctl->regmap); 1400 1401 rm = pctl->regmap; 1402 1403 ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset); 1404 if (ret) 1405 return ret; 1406 1407 ret = of_property_read_u32_index(np, "st,syscfg", 2, &mask); 1408 if (ret) 1409 mask = SYSCFG_IRQMUX_MASK; 1410 1411 mask_width = fls(mask); 1412 1413 for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) { 1414 struct reg_field mux; 1415 1416 mux.reg = offset + (i / 4) * 4; 1417 mux.lsb = (i % 4) * mask_width; 1418 mux.msb = mux.lsb + mask_width - 1; 1419 1420 dev_dbg(dev, "irqmux%d: reg:%#x, lsb:%d, msb:%d\n", 1421 i, mux.reg, mux.lsb, mux.msb); 1422 1423 pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux); 1424 if (IS_ERR(pctl->irqmux[i])) 1425 return PTR_ERR(pctl->irqmux[i]); 1426 } 1427 1428 return 0; 1429 } 1430 1431 static int stm32_pctrl_build_state(struct platform_device *pdev) 1432 { 1433 struct stm32_pinctrl *pctl = platform_get_drvdata(pdev); 1434 int i; 1435 1436 pctl->ngroups = pctl->npins; 1437 1438 /* Allocate groups */ 1439 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups, 1440 sizeof(*pctl->groups), GFP_KERNEL); 1441 if (!pctl->groups) 1442 return -ENOMEM; 1443 1444 /* We assume that one pin is one group, use pin name as group name. */ 1445 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups, 1446 sizeof(*pctl->grp_names), GFP_KERNEL); 1447 if (!pctl->grp_names) 1448 return -ENOMEM; 1449 1450 for (i = 0; i < pctl->npins; i++) { 1451 const struct stm32_desc_pin *pin = pctl->pins + i; 1452 struct stm32_pinctrl_group *group = pctl->groups + i; 1453 1454 group->name = pin->pin.name; 1455 group->pin = pin->pin.number; 1456 pctl->grp_names[i] = pin->pin.name; 1457 } 1458 1459 return 0; 1460 } 1461 1462 static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl, 1463 struct stm32_desc_pin *pins) 1464 { 1465 const struct stm32_desc_pin *p; 1466 int i, nb_pins_available = 0; 1467 1468 for (i = 0; i < pctl->match_data->npins; i++) { 1469 p = pctl->match_data->pins + i; 1470 if (pctl->pkg && !(pctl->pkg & p->pkg)) 1471 continue; 1472 pins->pin = p->pin; 1473 memcpy((struct stm32_desc_pin *)pins->functions, p->functions, 1474 STM32_CONFIG_NUM * sizeof(struct stm32_desc_function)); 1475 pins++; 1476 nb_pins_available++; 1477 } 1478 1479 pctl->npins = nb_pins_available; 1480 1481 return 0; 1482 } 1483 1484 int stm32_pctl_probe(struct platform_device *pdev) 1485 { 1486 const struct stm32_pinctrl_match_data *match_data; 1487 struct fwnode_handle *child; 1488 struct device *dev = &pdev->dev; 1489 struct stm32_pinctrl *pctl; 1490 struct pinctrl_pin_desc *pins; 1491 int i, ret, hwlock_id; 1492 unsigned int banks; 1493 1494 match_data = device_get_match_data(dev); 1495 if (!match_data) 1496 return -EINVAL; 1497 1498 if (!device_property_present(dev, "pins-are-numbered")) { 1499 dev_err(dev, "only support pins-are-numbered format\n"); 1500 return -EINVAL; 1501 } 1502 1503 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL); 1504 if (!pctl) 1505 return -ENOMEM; 1506 1507 platform_set_drvdata(pdev, pctl); 1508 1509 /* check for IRQ controller (may require deferred probe) */ 1510 pctl->domain = stm32_pctrl_get_irq_domain(pdev); 1511 if (IS_ERR(pctl->domain)) 1512 return PTR_ERR(pctl->domain); 1513 1514 /* hwspinlock is optional */ 1515 hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0); 1516 if (hwlock_id < 0) { 1517 if (hwlock_id == -EPROBE_DEFER) 1518 return hwlock_id; 1519 } else { 1520 pctl->hwlock = hwspin_lock_request_specific(hwlock_id); 1521 } 1522 1523 spin_lock_init(&pctl->irqmux_lock); 1524 1525 pctl->dev = dev; 1526 pctl->match_data = match_data; 1527 1528 /* get optional package information */ 1529 if (!device_property_read_u32(dev, "st,package", &pctl->pkg)) 1530 dev_dbg(pctl->dev, "package detected: %x\n", pctl->pkg); 1531 1532 pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins, 1533 sizeof(*pctl->pins), GFP_KERNEL); 1534 if (!pctl->pins) 1535 return -ENOMEM; 1536 1537 ret = stm32_pctrl_create_pins_tab(pctl, pctl->pins); 1538 if (ret) 1539 return ret; 1540 1541 ret = stm32_pctrl_build_state(pdev); 1542 if (ret) { 1543 dev_err(dev, "build state failed: %d\n", ret); 1544 return -EINVAL; 1545 } 1546 1547 if (pctl->domain) { 1548 ret = stm32_pctrl_dt_setup_irq(pdev, pctl); 1549 if (ret) 1550 return ret; 1551 } 1552 1553 pins = devm_kcalloc(&pdev->dev, pctl->npins, sizeof(*pins), 1554 GFP_KERNEL); 1555 if (!pins) 1556 return -ENOMEM; 1557 1558 for (i = 0; i < pctl->npins; i++) 1559 pins[i] = pctl->pins[i].pin; 1560 1561 pctl->pctl_desc.name = dev_name(&pdev->dev); 1562 pctl->pctl_desc.owner = THIS_MODULE; 1563 pctl->pctl_desc.pins = pins; 1564 pctl->pctl_desc.npins = pctl->npins; 1565 pctl->pctl_desc.link_consumers = true; 1566 pctl->pctl_desc.confops = &stm32_pconf_ops; 1567 pctl->pctl_desc.pctlops = &stm32_pctrl_ops; 1568 pctl->pctl_desc.pmxops = &stm32_pmx_ops; 1569 pctl->dev = &pdev->dev; 1570 1571 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc, 1572 pctl); 1573 1574 if (IS_ERR(pctl->pctl_dev)) { 1575 dev_err(&pdev->dev, "Failed pinctrl registration\n"); 1576 return PTR_ERR(pctl->pctl_dev); 1577 } 1578 1579 banks = gpiochip_node_count(dev); 1580 if (!banks) { 1581 dev_err(dev, "at least one GPIO bank is required\n"); 1582 return -EINVAL; 1583 } 1584 pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks), 1585 GFP_KERNEL); 1586 if (!pctl->banks) 1587 return -ENOMEM; 1588 1589 i = 0; 1590 for_each_gpiochip_node(dev, child) { 1591 struct stm32_gpio_bank *bank = &pctl->banks[i]; 1592 struct device_node *np = to_of_node(child); 1593 1594 bank->rstc = of_reset_control_get_exclusive(np, NULL); 1595 if (PTR_ERR(bank->rstc) == -EPROBE_DEFER) { 1596 fwnode_handle_put(child); 1597 return -EPROBE_DEFER; 1598 } 1599 1600 bank->clk = of_clk_get_by_name(np, NULL); 1601 if (IS_ERR(bank->clk)) { 1602 if (PTR_ERR(bank->clk) != -EPROBE_DEFER) 1603 dev_err(dev, "failed to get clk (%ld)\n", PTR_ERR(bank->clk)); 1604 fwnode_handle_put(child); 1605 return PTR_ERR(bank->clk); 1606 } 1607 i++; 1608 } 1609 1610 for_each_gpiochip_node(dev, child) { 1611 ret = stm32_gpiolib_register_bank(pctl, child); 1612 if (ret) { 1613 fwnode_handle_put(child); 1614 1615 for (i = 0; i < pctl->nbanks; i++) 1616 clk_disable_unprepare(pctl->banks[i].clk); 1617 1618 return ret; 1619 } 1620 1621 pctl->nbanks++; 1622 } 1623 1624 dev_info(dev, "Pinctrl STM32 initialized\n"); 1625 1626 return 0; 1627 } 1628 1629 static int __maybe_unused stm32_pinctrl_restore_gpio_regs( 1630 struct stm32_pinctrl *pctl, u32 pin) 1631 { 1632 const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin); 1633 u32 val, alt, mode, offset = stm32_gpio_pin(pin); 1634 struct pinctrl_gpio_range *range; 1635 struct stm32_gpio_bank *bank; 1636 bool pin_is_irq; 1637 int ret; 1638 1639 range = pinctrl_find_gpio_range_from_pin(pctl->pctl_dev, pin); 1640 if (!range) 1641 return 0; 1642 1643 if (!gpiochip_line_is_valid(range->gc, offset)) 1644 return 0; 1645 1646 pin_is_irq = gpiochip_line_is_irq(range->gc, offset); 1647 1648 if (!desc || (!pin_is_irq && !desc->gpio_owner)) 1649 return 0; 1650 1651 bank = gpiochip_get_data(range->gc); 1652 1653 alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK; 1654 alt >>= STM32_GPIO_BKP_ALT_SHIFT; 1655 mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK; 1656 mode >>= STM32_GPIO_BKP_MODE_SHIFT; 1657 1658 ret = stm32_pmx_set_mode(bank, offset, mode, alt); 1659 if (ret) 1660 return ret; 1661 1662 if (mode == 1) { 1663 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL); 1664 val = val >> STM32_GPIO_BKP_VAL; 1665 __stm32_gpio_set(bank, offset, val); 1666 } 1667 1668 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE); 1669 val >>= STM32_GPIO_BKP_TYPE; 1670 ret = stm32_pconf_set_driving(bank, offset, val); 1671 if (ret) 1672 return ret; 1673 1674 val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK; 1675 val >>= STM32_GPIO_BKP_SPEED_SHIFT; 1676 ret = stm32_pconf_set_speed(bank, offset, val); 1677 if (ret) 1678 return ret; 1679 1680 val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK; 1681 val >>= STM32_GPIO_BKP_PUPD_SHIFT; 1682 ret = stm32_pconf_set_bias(bank, offset, val); 1683 if (ret) 1684 return ret; 1685 1686 if (pin_is_irq) 1687 regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr); 1688 1689 return 0; 1690 } 1691 1692 int __maybe_unused stm32_pinctrl_suspend(struct device *dev) 1693 { 1694 struct stm32_pinctrl *pctl = dev_get_drvdata(dev); 1695 int i; 1696 1697 for (i = 0; i < pctl->nbanks; i++) 1698 clk_disable(pctl->banks[i].clk); 1699 1700 return 0; 1701 } 1702 1703 int __maybe_unused stm32_pinctrl_resume(struct device *dev) 1704 { 1705 struct stm32_pinctrl *pctl = dev_get_drvdata(dev); 1706 struct stm32_pinctrl_group *g = pctl->groups; 1707 int i; 1708 1709 for (i = 0; i < pctl->nbanks; i++) 1710 clk_enable(pctl->banks[i].clk); 1711 1712 for (i = 0; i < pctl->ngroups; i++, g++) 1713 stm32_pinctrl_restore_gpio_regs(pctl, g->pin); 1714 1715 return 0; 1716 } 1717