1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics 2017 5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 * 7 * Heavily based on Mediatek's pinctrl driver 8 */ 9 #include <linux/clk.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/io.h> 12 #include <linux/irq.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 #include <linux/of_device.h> 18 #include <linux/of_irq.h> 19 #include <linux/pinctrl/consumer.h> 20 #include <linux/pinctrl/machine.h> 21 #include <linux/pinctrl/pinconf.h> 22 #include <linux/pinctrl/pinconf-generic.h> 23 #include <linux/pinctrl/pinctrl.h> 24 #include <linux/pinctrl/pinmux.h> 25 #include <linux/platform_device.h> 26 #include <linux/regmap.h> 27 #include <linux/reset.h> 28 #include <linux/slab.h> 29 30 #include "../core.h" 31 #include "../pinconf.h" 32 #include "../pinctrl-utils.h" 33 #include "pinctrl-stm32.h" 34 35 #define STM32_GPIO_MODER 0x00 36 #define STM32_GPIO_TYPER 0x04 37 #define STM32_GPIO_SPEEDR 0x08 38 #define STM32_GPIO_PUPDR 0x0c 39 #define STM32_GPIO_IDR 0x10 40 #define STM32_GPIO_ODR 0x14 41 #define STM32_GPIO_BSRR 0x18 42 #define STM32_GPIO_LCKR 0x1c 43 #define STM32_GPIO_AFRL 0x20 44 #define STM32_GPIO_AFRH 0x24 45 46 #define STM32_GPIO_PINS_PER_BANK 16 47 #define STM32_GPIO_IRQ_LINE 16 48 49 #define gpio_range_to_bank(chip) \ 50 container_of(chip, struct stm32_gpio_bank, range) 51 52 static const char * const stm32_gpio_functions[] = { 53 "gpio", "af0", "af1", 54 "af2", "af3", "af4", 55 "af5", "af6", "af7", 56 "af8", "af9", "af10", 57 "af11", "af12", "af13", 58 "af14", "af15", "analog", 59 }; 60 61 struct stm32_pinctrl_group { 62 const char *name; 63 unsigned long config; 64 unsigned pin; 65 }; 66 67 struct stm32_gpio_bank { 68 void __iomem *base; 69 struct clk *clk; 70 spinlock_t lock; 71 struct gpio_chip gpio_chip; 72 struct pinctrl_gpio_range range; 73 struct fwnode_handle *fwnode; 74 struct irq_domain *domain; 75 u32 bank_nr; 76 }; 77 78 struct stm32_pinctrl { 79 struct device *dev; 80 struct pinctrl_dev *pctl_dev; 81 struct pinctrl_desc pctl_desc; 82 struct stm32_pinctrl_group *groups; 83 unsigned ngroups; 84 const char **grp_names; 85 struct stm32_gpio_bank *banks; 86 unsigned nbanks; 87 const struct stm32_pinctrl_match_data *match_data; 88 struct irq_domain *domain; 89 struct regmap *regmap; 90 struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK]; 91 }; 92 93 static inline int stm32_gpio_pin(int gpio) 94 { 95 return gpio % STM32_GPIO_PINS_PER_BANK; 96 } 97 98 static inline u32 stm32_gpio_get_mode(u32 function) 99 { 100 switch (function) { 101 case STM32_PIN_GPIO: 102 return 0; 103 case STM32_PIN_AF(0) ... STM32_PIN_AF(15): 104 return 2; 105 case STM32_PIN_ANALOG: 106 return 3; 107 } 108 109 return 0; 110 } 111 112 static inline u32 stm32_gpio_get_alt(u32 function) 113 { 114 switch (function) { 115 case STM32_PIN_GPIO: 116 return 0; 117 case STM32_PIN_AF(0) ... STM32_PIN_AF(15): 118 return function - 1; 119 case STM32_PIN_ANALOG: 120 return 0; 121 } 122 123 return 0; 124 } 125 126 /* GPIO functions */ 127 128 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank, 129 unsigned offset, int value) 130 { 131 if (!value) 132 offset += STM32_GPIO_PINS_PER_BANK; 133 134 clk_enable(bank->clk); 135 136 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR); 137 138 clk_disable(bank->clk); 139 } 140 141 static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset) 142 { 143 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 144 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 145 struct pinctrl_gpio_range *range; 146 int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK); 147 148 range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin); 149 if (!range) { 150 dev_err(pctl->dev, "pin %d not in range.\n", pin); 151 return -EINVAL; 152 } 153 154 return pinctrl_gpio_request(chip->base + offset); 155 } 156 157 static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset) 158 { 159 pinctrl_gpio_free(chip->base + offset); 160 } 161 162 static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset) 163 { 164 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 165 int ret; 166 167 clk_enable(bank->clk); 168 169 ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset)); 170 171 clk_disable(bank->clk); 172 173 return ret; 174 } 175 176 static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 177 { 178 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 179 180 __stm32_gpio_set(bank, offset, value); 181 } 182 183 static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 184 { 185 return pinctrl_gpio_direction_input(chip->base + offset); 186 } 187 188 static int stm32_gpio_direction_output(struct gpio_chip *chip, 189 unsigned offset, int value) 190 { 191 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 192 193 __stm32_gpio_set(bank, offset, value); 194 pinctrl_gpio_direction_output(chip->base + offset); 195 196 return 0; 197 } 198 199 200 static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) 201 { 202 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 203 struct irq_fwspec fwspec; 204 205 fwspec.fwnode = bank->fwnode; 206 fwspec.param_count = 2; 207 fwspec.param[0] = offset; 208 fwspec.param[1] = IRQ_TYPE_NONE; 209 210 return irq_create_fwspec_mapping(&fwspec); 211 } 212 213 static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 214 { 215 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 216 int pin = stm32_gpio_pin(offset); 217 int ret; 218 u32 mode, alt; 219 220 stm32_pmx_get_mode(bank, pin, &mode, &alt); 221 if ((alt == 0) && (mode == 0)) 222 ret = 1; 223 else if ((alt == 0) && (mode == 1)) 224 ret = 0; 225 else 226 ret = -EINVAL; 227 228 return ret; 229 } 230 231 static const struct gpio_chip stm32_gpio_template = { 232 .request = stm32_gpio_request, 233 .free = stm32_gpio_free, 234 .get = stm32_gpio_get, 235 .set = stm32_gpio_set, 236 .direction_input = stm32_gpio_direction_input, 237 .direction_output = stm32_gpio_direction_output, 238 .to_irq = stm32_gpio_to_irq, 239 .get_direction = stm32_gpio_get_direction, 240 }; 241 242 static int stm32_gpio_irq_request_resources(struct irq_data *irq_data) 243 { 244 struct stm32_gpio_bank *bank = irq_data->domain->host_data; 245 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 246 int ret; 247 248 ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq); 249 if (ret) 250 return ret; 251 252 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq); 253 if (ret) { 254 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", 255 irq_data->hwirq); 256 return ret; 257 } 258 259 return 0; 260 } 261 262 static void stm32_gpio_irq_release_resources(struct irq_data *irq_data) 263 { 264 struct stm32_gpio_bank *bank = irq_data->domain->host_data; 265 266 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq); 267 } 268 269 static struct irq_chip stm32_gpio_irq_chip = { 270 .name = "stm32gpio", 271 .irq_ack = irq_chip_ack_parent, 272 .irq_mask = irq_chip_mask_parent, 273 .irq_unmask = irq_chip_unmask_parent, 274 .irq_set_type = irq_chip_set_type_parent, 275 .irq_set_wake = irq_chip_set_wake_parent, 276 .irq_request_resources = stm32_gpio_irq_request_resources, 277 .irq_release_resources = stm32_gpio_irq_release_resources, 278 }; 279 280 static int stm32_gpio_domain_translate(struct irq_domain *d, 281 struct irq_fwspec *fwspec, 282 unsigned long *hwirq, 283 unsigned int *type) 284 { 285 if ((fwspec->param_count != 2) || 286 (fwspec->param[0] >= STM32_GPIO_IRQ_LINE)) 287 return -EINVAL; 288 289 *hwirq = fwspec->param[0]; 290 *type = fwspec->param[1]; 291 return 0; 292 } 293 294 static int stm32_gpio_domain_activate(struct irq_domain *d, 295 struct irq_data *irq_data, bool reserve) 296 { 297 struct stm32_gpio_bank *bank = d->host_data; 298 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 299 300 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_nr); 301 return 0; 302 } 303 304 static int stm32_gpio_domain_alloc(struct irq_domain *d, 305 unsigned int virq, 306 unsigned int nr_irqs, void *data) 307 { 308 struct stm32_gpio_bank *bank = d->host_data; 309 struct irq_fwspec *fwspec = data; 310 struct irq_fwspec parent_fwspec; 311 irq_hw_number_t hwirq; 312 313 hwirq = fwspec->param[0]; 314 parent_fwspec.fwnode = d->parent->fwnode; 315 parent_fwspec.param_count = 2; 316 parent_fwspec.param[0] = fwspec->param[0]; 317 parent_fwspec.param[1] = fwspec->param[1]; 318 319 irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip, 320 bank); 321 322 return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec); 323 } 324 325 static const struct irq_domain_ops stm32_gpio_domain_ops = { 326 .translate = stm32_gpio_domain_translate, 327 .alloc = stm32_gpio_domain_alloc, 328 .free = irq_domain_free_irqs_common, 329 .activate = stm32_gpio_domain_activate, 330 }; 331 332 /* Pinctrl functions */ 333 static struct stm32_pinctrl_group * 334 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin) 335 { 336 int i; 337 338 for (i = 0; i < pctl->ngroups; i++) { 339 struct stm32_pinctrl_group *grp = pctl->groups + i; 340 341 if (grp->pin == pin) 342 return grp; 343 } 344 345 return NULL; 346 } 347 348 static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl, 349 u32 pin_num, u32 fnum) 350 { 351 int i; 352 353 for (i = 0; i < pctl->match_data->npins; i++) { 354 const struct stm32_desc_pin *pin = pctl->match_data->pins + i; 355 const struct stm32_desc_function *func = pin->functions; 356 357 if (pin->pin.number != pin_num) 358 continue; 359 360 while (func && func->name) { 361 if (func->num == fnum) 362 return true; 363 func++; 364 } 365 366 break; 367 } 368 369 return false; 370 } 371 372 static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl, 373 u32 pin, u32 fnum, struct stm32_pinctrl_group *grp, 374 struct pinctrl_map **map, unsigned *reserved_maps, 375 unsigned *num_maps) 376 { 377 if (*num_maps == *reserved_maps) 378 return -ENOSPC; 379 380 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; 381 (*map)[*num_maps].data.mux.group = grp->name; 382 383 if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) { 384 dev_err(pctl->dev, "invalid function %d on pin %d .\n", 385 fnum, pin); 386 return -EINVAL; 387 } 388 389 (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum]; 390 (*num_maps)++; 391 392 return 0; 393 } 394 395 static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, 396 struct device_node *node, 397 struct pinctrl_map **map, 398 unsigned *reserved_maps, 399 unsigned *num_maps) 400 { 401 struct stm32_pinctrl *pctl; 402 struct stm32_pinctrl_group *grp; 403 struct property *pins; 404 u32 pinfunc, pin, func; 405 unsigned long *configs; 406 unsigned int num_configs; 407 bool has_config = 0; 408 unsigned reserve = 0; 409 int num_pins, num_funcs, maps_per_pin, i, err; 410 411 pctl = pinctrl_dev_get_drvdata(pctldev); 412 413 pins = of_find_property(node, "pinmux", NULL); 414 if (!pins) { 415 dev_err(pctl->dev, "missing pins property in node %s .\n", 416 node->name); 417 return -EINVAL; 418 } 419 420 err = pinconf_generic_parse_dt_config(node, pctldev, &configs, 421 &num_configs); 422 if (err) 423 return err; 424 425 if (num_configs) 426 has_config = 1; 427 428 num_pins = pins->length / sizeof(u32); 429 num_funcs = num_pins; 430 maps_per_pin = 0; 431 if (num_funcs) 432 maps_per_pin++; 433 if (has_config && num_pins >= 1) 434 maps_per_pin++; 435 436 if (!num_pins || !maps_per_pin) 437 return -EINVAL; 438 439 reserve = num_pins * maps_per_pin; 440 441 err = pinctrl_utils_reserve_map(pctldev, map, 442 reserved_maps, num_maps, reserve); 443 if (err) 444 return err; 445 446 for (i = 0; i < num_pins; i++) { 447 err = of_property_read_u32_index(node, "pinmux", 448 i, &pinfunc); 449 if (err) 450 return err; 451 452 pin = STM32_GET_PIN_NO(pinfunc); 453 func = STM32_GET_PIN_FUNC(pinfunc); 454 455 if (!stm32_pctrl_is_function_valid(pctl, pin, func)) { 456 dev_err(pctl->dev, "invalid function.\n"); 457 return -EINVAL; 458 } 459 460 grp = stm32_pctrl_find_group_by_pin(pctl, pin); 461 if (!grp) { 462 dev_err(pctl->dev, "unable to match pin %d to group\n", 463 pin); 464 return -EINVAL; 465 } 466 467 err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map, 468 reserved_maps, num_maps); 469 if (err) 470 return err; 471 472 if (has_config) { 473 err = pinctrl_utils_add_map_configs(pctldev, map, 474 reserved_maps, num_maps, grp->name, 475 configs, num_configs, 476 PIN_MAP_TYPE_CONFIGS_GROUP); 477 if (err) 478 return err; 479 } 480 } 481 482 return 0; 483 } 484 485 static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 486 struct device_node *np_config, 487 struct pinctrl_map **map, unsigned *num_maps) 488 { 489 struct device_node *np; 490 unsigned reserved_maps; 491 int ret; 492 493 *map = NULL; 494 *num_maps = 0; 495 reserved_maps = 0; 496 497 for_each_child_of_node(np_config, np) { 498 ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map, 499 &reserved_maps, num_maps); 500 if (ret < 0) { 501 pinctrl_utils_free_map(pctldev, *map, *num_maps); 502 return ret; 503 } 504 } 505 506 return 0; 507 } 508 509 static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev) 510 { 511 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 512 513 return pctl->ngroups; 514 } 515 516 static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev, 517 unsigned group) 518 { 519 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 520 521 return pctl->groups[group].name; 522 } 523 524 static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev, 525 unsigned group, 526 const unsigned **pins, 527 unsigned *num_pins) 528 { 529 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 530 531 *pins = (unsigned *)&pctl->groups[group].pin; 532 *num_pins = 1; 533 534 return 0; 535 } 536 537 static const struct pinctrl_ops stm32_pctrl_ops = { 538 .dt_node_to_map = stm32_pctrl_dt_node_to_map, 539 .dt_free_map = pinctrl_utils_free_map, 540 .get_groups_count = stm32_pctrl_get_groups_count, 541 .get_group_name = stm32_pctrl_get_group_name, 542 .get_group_pins = stm32_pctrl_get_group_pins, 543 }; 544 545 546 /* Pinmux functions */ 547 548 static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 549 { 550 return ARRAY_SIZE(stm32_gpio_functions); 551 } 552 553 static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev, 554 unsigned selector) 555 { 556 return stm32_gpio_functions[selector]; 557 } 558 559 static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev, 560 unsigned function, 561 const char * const **groups, 562 unsigned * const num_groups) 563 { 564 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 565 566 *groups = pctl->grp_names; 567 *num_groups = pctl->ngroups; 568 569 return 0; 570 } 571 572 static void stm32_pmx_set_mode(struct stm32_gpio_bank *bank, 573 int pin, u32 mode, u32 alt) 574 { 575 u32 val; 576 int alt_shift = (pin % 8) * 4; 577 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; 578 unsigned long flags; 579 580 clk_enable(bank->clk); 581 spin_lock_irqsave(&bank->lock, flags); 582 583 val = readl_relaxed(bank->base + alt_offset); 584 val &= ~GENMASK(alt_shift + 3, alt_shift); 585 val |= (alt << alt_shift); 586 writel_relaxed(val, bank->base + alt_offset); 587 588 val = readl_relaxed(bank->base + STM32_GPIO_MODER); 589 val &= ~GENMASK(pin * 2 + 1, pin * 2); 590 val |= mode << (pin * 2); 591 writel_relaxed(val, bank->base + STM32_GPIO_MODER); 592 593 spin_unlock_irqrestore(&bank->lock, flags); 594 clk_disable(bank->clk); 595 } 596 597 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, 598 u32 *alt) 599 { 600 u32 val; 601 int alt_shift = (pin % 8) * 4; 602 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; 603 unsigned long flags; 604 605 clk_enable(bank->clk); 606 spin_lock_irqsave(&bank->lock, flags); 607 608 val = readl_relaxed(bank->base + alt_offset); 609 val &= GENMASK(alt_shift + 3, alt_shift); 610 *alt = val >> alt_shift; 611 612 val = readl_relaxed(bank->base + STM32_GPIO_MODER); 613 val &= GENMASK(pin * 2 + 1, pin * 2); 614 *mode = val >> (pin * 2); 615 616 spin_unlock_irqrestore(&bank->lock, flags); 617 clk_disable(bank->clk); 618 } 619 620 static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev, 621 unsigned function, 622 unsigned group) 623 { 624 bool ret; 625 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 626 struct stm32_pinctrl_group *g = pctl->groups + group; 627 struct pinctrl_gpio_range *range; 628 struct stm32_gpio_bank *bank; 629 u32 mode, alt; 630 int pin; 631 632 ret = stm32_pctrl_is_function_valid(pctl, g->pin, function); 633 if (!ret) { 634 dev_err(pctl->dev, "invalid function %d on group %d .\n", 635 function, group); 636 return -EINVAL; 637 } 638 639 range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin); 640 bank = gpiochip_get_data(range->gc); 641 pin = stm32_gpio_pin(g->pin); 642 643 mode = stm32_gpio_get_mode(function); 644 alt = stm32_gpio_get_alt(function); 645 646 stm32_pmx_set_mode(bank, pin, mode, alt); 647 648 return 0; 649 } 650 651 static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 652 struct pinctrl_gpio_range *range, unsigned gpio, 653 bool input) 654 { 655 struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc); 656 int pin = stm32_gpio_pin(gpio); 657 658 stm32_pmx_set_mode(bank, pin, !input, 0); 659 660 return 0; 661 } 662 663 static const struct pinmux_ops stm32_pmx_ops = { 664 .get_functions_count = stm32_pmx_get_funcs_cnt, 665 .get_function_name = stm32_pmx_get_func_name, 666 .get_function_groups = stm32_pmx_get_func_groups, 667 .set_mux = stm32_pmx_set_mux, 668 .gpio_set_direction = stm32_pmx_gpio_set_direction, 669 .strict = true, 670 }; 671 672 /* Pinconf functions */ 673 674 static void stm32_pconf_set_driving(struct stm32_gpio_bank *bank, 675 unsigned offset, u32 drive) 676 { 677 unsigned long flags; 678 u32 val; 679 680 clk_enable(bank->clk); 681 spin_lock_irqsave(&bank->lock, flags); 682 683 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); 684 val &= ~BIT(offset); 685 val |= drive << offset; 686 writel_relaxed(val, bank->base + STM32_GPIO_TYPER); 687 688 spin_unlock_irqrestore(&bank->lock, flags); 689 clk_disable(bank->clk); 690 } 691 692 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank, 693 unsigned int offset) 694 { 695 unsigned long flags; 696 u32 val; 697 698 clk_enable(bank->clk); 699 spin_lock_irqsave(&bank->lock, flags); 700 701 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); 702 val &= BIT(offset); 703 704 spin_unlock_irqrestore(&bank->lock, flags); 705 clk_disable(bank->clk); 706 707 return (val >> offset); 708 } 709 710 static void stm32_pconf_set_speed(struct stm32_gpio_bank *bank, 711 unsigned offset, u32 speed) 712 { 713 unsigned long flags; 714 u32 val; 715 716 clk_enable(bank->clk); 717 spin_lock_irqsave(&bank->lock, flags); 718 719 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); 720 val &= ~GENMASK(offset * 2 + 1, offset * 2); 721 val |= speed << (offset * 2); 722 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR); 723 724 spin_unlock_irqrestore(&bank->lock, flags); 725 clk_disable(bank->clk); 726 } 727 728 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank, 729 unsigned int offset) 730 { 731 unsigned long flags; 732 u32 val; 733 734 clk_enable(bank->clk); 735 spin_lock_irqsave(&bank->lock, flags); 736 737 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); 738 val &= GENMASK(offset * 2 + 1, offset * 2); 739 740 spin_unlock_irqrestore(&bank->lock, flags); 741 clk_disable(bank->clk); 742 743 return (val >> (offset * 2)); 744 } 745 746 static void stm32_pconf_set_bias(struct stm32_gpio_bank *bank, 747 unsigned offset, u32 bias) 748 { 749 unsigned long flags; 750 u32 val; 751 752 clk_enable(bank->clk); 753 spin_lock_irqsave(&bank->lock, flags); 754 755 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); 756 val &= ~GENMASK(offset * 2 + 1, offset * 2); 757 val |= bias << (offset * 2); 758 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR); 759 760 spin_unlock_irqrestore(&bank->lock, flags); 761 clk_disable(bank->clk); 762 } 763 764 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank, 765 unsigned int offset) 766 { 767 unsigned long flags; 768 u32 val; 769 770 clk_enable(bank->clk); 771 spin_lock_irqsave(&bank->lock, flags); 772 773 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); 774 val &= GENMASK(offset * 2 + 1, offset * 2); 775 776 spin_unlock_irqrestore(&bank->lock, flags); 777 clk_disable(bank->clk); 778 779 return (val >> (offset * 2)); 780 } 781 782 static bool stm32_pconf_get(struct stm32_gpio_bank *bank, 783 unsigned int offset, bool dir) 784 { 785 unsigned long flags; 786 u32 val; 787 788 clk_enable(bank->clk); 789 spin_lock_irqsave(&bank->lock, flags); 790 791 if (dir) 792 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & 793 BIT(offset)); 794 else 795 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) & 796 BIT(offset)); 797 798 spin_unlock_irqrestore(&bank->lock, flags); 799 clk_disable(bank->clk); 800 801 return val; 802 } 803 804 static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev, 805 unsigned int pin, enum pin_config_param param, 806 enum pin_config_param arg) 807 { 808 struct pinctrl_gpio_range *range; 809 struct stm32_gpio_bank *bank; 810 int offset, ret = 0; 811 812 range = pinctrl_find_gpio_range_from_pin(pctldev, pin); 813 bank = gpiochip_get_data(range->gc); 814 offset = stm32_gpio_pin(pin); 815 816 switch (param) { 817 case PIN_CONFIG_DRIVE_PUSH_PULL: 818 stm32_pconf_set_driving(bank, offset, 0); 819 break; 820 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 821 stm32_pconf_set_driving(bank, offset, 1); 822 break; 823 case PIN_CONFIG_SLEW_RATE: 824 stm32_pconf_set_speed(bank, offset, arg); 825 break; 826 case PIN_CONFIG_BIAS_DISABLE: 827 stm32_pconf_set_bias(bank, offset, 0); 828 break; 829 case PIN_CONFIG_BIAS_PULL_UP: 830 stm32_pconf_set_bias(bank, offset, 1); 831 break; 832 case PIN_CONFIG_BIAS_PULL_DOWN: 833 stm32_pconf_set_bias(bank, offset, 2); 834 break; 835 case PIN_CONFIG_OUTPUT: 836 __stm32_gpio_set(bank, offset, arg); 837 ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false); 838 break; 839 default: 840 ret = -EINVAL; 841 } 842 843 return ret; 844 } 845 846 static int stm32_pconf_group_get(struct pinctrl_dev *pctldev, 847 unsigned group, 848 unsigned long *config) 849 { 850 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 851 852 *config = pctl->groups[group].config; 853 854 return 0; 855 } 856 857 static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, 858 unsigned long *configs, unsigned num_configs) 859 { 860 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 861 struct stm32_pinctrl_group *g = &pctl->groups[group]; 862 int i, ret; 863 864 for (i = 0; i < num_configs; i++) { 865 ret = stm32_pconf_parse_conf(pctldev, g->pin, 866 pinconf_to_config_param(configs[i]), 867 pinconf_to_config_argument(configs[i])); 868 if (ret < 0) 869 return ret; 870 871 g->config = configs[i]; 872 } 873 874 return 0; 875 } 876 877 static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev, 878 struct seq_file *s, 879 unsigned int pin) 880 { 881 struct pinctrl_gpio_range *range; 882 struct stm32_gpio_bank *bank; 883 int offset; 884 u32 mode, alt, drive, speed, bias; 885 static const char * const modes[] = { 886 "input", "output", "alternate", "analog" }; 887 static const char * const speeds[] = { 888 "low", "medium", "high", "very high" }; 889 static const char * const biasing[] = { 890 "floating", "pull up", "pull down", "" }; 891 bool val; 892 893 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); 894 bank = gpiochip_get_data(range->gc); 895 offset = stm32_gpio_pin(pin); 896 897 stm32_pmx_get_mode(bank, offset, &mode, &alt); 898 bias = stm32_pconf_get_bias(bank, offset); 899 900 seq_printf(s, "%s ", modes[mode]); 901 902 switch (mode) { 903 /* input */ 904 case 0: 905 val = stm32_pconf_get(bank, offset, true); 906 seq_printf(s, "- %s - %s", 907 val ? "high" : "low", 908 biasing[bias]); 909 break; 910 911 /* output */ 912 case 1: 913 drive = stm32_pconf_get_driving(bank, offset); 914 speed = stm32_pconf_get_speed(bank, offset); 915 val = stm32_pconf_get(bank, offset, false); 916 seq_printf(s, "- %s - %s - %s - %s %s", 917 val ? "high" : "low", 918 drive ? "open drain" : "push pull", 919 biasing[bias], 920 speeds[speed], "speed"); 921 break; 922 923 /* alternate */ 924 case 2: 925 drive = stm32_pconf_get_driving(bank, offset); 926 speed = stm32_pconf_get_speed(bank, offset); 927 seq_printf(s, "%d - %s - %s - %s %s", alt, 928 drive ? "open drain" : "push pull", 929 biasing[bias], 930 speeds[speed], "speed"); 931 break; 932 933 /* analog */ 934 case 3: 935 break; 936 } 937 } 938 939 940 static const struct pinconf_ops stm32_pconf_ops = { 941 .pin_config_group_get = stm32_pconf_group_get, 942 .pin_config_group_set = stm32_pconf_group_set, 943 .pin_config_dbg_show = stm32_pconf_dbg_show, 944 }; 945 946 static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, 947 struct device_node *np) 948 { 949 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks]; 950 struct pinctrl_gpio_range *range = &bank->range; 951 struct of_phandle_args args; 952 struct device *dev = pctl->dev; 953 struct resource res; 954 struct reset_control *rstc; 955 int npins = STM32_GPIO_PINS_PER_BANK; 956 int bank_nr, err; 957 958 rstc = of_reset_control_get_exclusive(np, NULL); 959 if (!IS_ERR(rstc)) 960 reset_control_deassert(rstc); 961 962 if (of_address_to_resource(np, 0, &res)) 963 return -ENODEV; 964 965 bank->base = devm_ioremap_resource(dev, &res); 966 if (IS_ERR(bank->base)) 967 return PTR_ERR(bank->base); 968 969 bank->clk = of_clk_get_by_name(np, NULL); 970 if (IS_ERR(bank->clk)) { 971 dev_err(dev, "failed to get clk (%ld)\n", PTR_ERR(bank->clk)); 972 return PTR_ERR(bank->clk); 973 } 974 975 err = clk_prepare(bank->clk); 976 if (err) { 977 dev_err(dev, "failed to prepare clk (%d)\n", err); 978 return err; 979 } 980 981 bank->gpio_chip = stm32_gpio_template; 982 983 of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label); 984 985 if (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args)) { 986 bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK; 987 bank->gpio_chip.base = args.args[1]; 988 } else { 989 bank_nr = pctl->nbanks; 990 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; 991 range->name = bank->gpio_chip.label; 992 range->id = bank_nr; 993 range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK; 994 range->base = range->id * STM32_GPIO_PINS_PER_BANK; 995 range->npins = npins; 996 range->gc = &bank->gpio_chip; 997 pinctrl_add_gpio_range(pctl->pctl_dev, 998 &pctl->banks[bank_nr].range); 999 } 1000 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; 1001 1002 bank->gpio_chip.ngpio = npins; 1003 bank->gpio_chip.of_node = np; 1004 bank->gpio_chip.parent = dev; 1005 bank->bank_nr = bank_nr; 1006 spin_lock_init(&bank->lock); 1007 1008 /* create irq hierarchical domain */ 1009 bank->fwnode = of_node_to_fwnode(np); 1010 1011 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, 1012 STM32_GPIO_IRQ_LINE, bank->fwnode, 1013 &stm32_gpio_domain_ops, bank); 1014 1015 if (!bank->domain) 1016 return -ENODEV; 1017 1018 err = gpiochip_add_data(&bank->gpio_chip, bank); 1019 if (err) { 1020 dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr); 1021 return err; 1022 } 1023 1024 dev_info(dev, "%s bank added\n", bank->gpio_chip.label); 1025 return 0; 1026 } 1027 1028 static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev, 1029 struct stm32_pinctrl *pctl) 1030 { 1031 struct device_node *np = pdev->dev.of_node, *parent; 1032 struct device *dev = &pdev->dev; 1033 struct regmap *rm; 1034 int offset, ret, i; 1035 1036 parent = of_irq_find_parent(np); 1037 if (!parent) 1038 return -ENXIO; 1039 1040 pctl->domain = irq_find_host(parent); 1041 if (!pctl->domain) 1042 return -ENXIO; 1043 1044 pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); 1045 if (IS_ERR(pctl->regmap)) 1046 return PTR_ERR(pctl->regmap); 1047 1048 rm = pctl->regmap; 1049 1050 ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset); 1051 if (ret) 1052 return ret; 1053 1054 for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) { 1055 struct reg_field mux; 1056 1057 mux.reg = offset + (i / 4) * 4; 1058 mux.lsb = (i % 4) * 4; 1059 mux.msb = mux.lsb + 3; 1060 1061 pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux); 1062 if (IS_ERR(pctl->irqmux[i])) 1063 return PTR_ERR(pctl->irqmux[i]); 1064 } 1065 1066 return 0; 1067 } 1068 1069 static int stm32_pctrl_build_state(struct platform_device *pdev) 1070 { 1071 struct stm32_pinctrl *pctl = platform_get_drvdata(pdev); 1072 int i; 1073 1074 pctl->ngroups = pctl->match_data->npins; 1075 1076 /* Allocate groups */ 1077 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups, 1078 sizeof(*pctl->groups), GFP_KERNEL); 1079 if (!pctl->groups) 1080 return -ENOMEM; 1081 1082 /* We assume that one pin is one group, use pin name as group name. */ 1083 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups, 1084 sizeof(*pctl->grp_names), GFP_KERNEL); 1085 if (!pctl->grp_names) 1086 return -ENOMEM; 1087 1088 for (i = 0; i < pctl->match_data->npins; i++) { 1089 const struct stm32_desc_pin *pin = pctl->match_data->pins + i; 1090 struct stm32_pinctrl_group *group = pctl->groups + i; 1091 1092 group->name = pin->pin.name; 1093 group->pin = pin->pin.number; 1094 1095 pctl->grp_names[i] = pin->pin.name; 1096 } 1097 1098 return 0; 1099 } 1100 1101 int stm32_pctl_probe(struct platform_device *pdev) 1102 { 1103 struct device_node *np = pdev->dev.of_node; 1104 struct device_node *child; 1105 const struct of_device_id *match; 1106 struct device *dev = &pdev->dev; 1107 struct stm32_pinctrl *pctl; 1108 struct pinctrl_pin_desc *pins; 1109 int i, ret, banks = 0; 1110 1111 if (!np) 1112 return -EINVAL; 1113 1114 match = of_match_device(dev->driver->of_match_table, dev); 1115 if (!match || !match->data) 1116 return -EINVAL; 1117 1118 if (!of_find_property(np, "pins-are-numbered", NULL)) { 1119 dev_err(dev, "only support pins-are-numbered format\n"); 1120 return -EINVAL; 1121 } 1122 1123 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL); 1124 if (!pctl) 1125 return -ENOMEM; 1126 1127 platform_set_drvdata(pdev, pctl); 1128 1129 pctl->dev = dev; 1130 pctl->match_data = match->data; 1131 ret = stm32_pctrl_build_state(pdev); 1132 if (ret) { 1133 dev_err(dev, "build state failed: %d\n", ret); 1134 return -EINVAL; 1135 } 1136 1137 if (of_find_property(np, "interrupt-parent", NULL)) { 1138 ret = stm32_pctrl_dt_setup_irq(pdev, pctl); 1139 if (ret) 1140 return ret; 1141 } 1142 1143 pins = devm_kcalloc(&pdev->dev, pctl->match_data->npins, sizeof(*pins), 1144 GFP_KERNEL); 1145 if (!pins) 1146 return -ENOMEM; 1147 1148 for (i = 0; i < pctl->match_data->npins; i++) 1149 pins[i] = pctl->match_data->pins[i].pin; 1150 1151 pctl->pctl_desc.name = dev_name(&pdev->dev); 1152 pctl->pctl_desc.owner = THIS_MODULE; 1153 pctl->pctl_desc.pins = pins; 1154 pctl->pctl_desc.npins = pctl->match_data->npins; 1155 pctl->pctl_desc.confops = &stm32_pconf_ops; 1156 pctl->pctl_desc.pctlops = &stm32_pctrl_ops; 1157 pctl->pctl_desc.pmxops = &stm32_pmx_ops; 1158 pctl->dev = &pdev->dev; 1159 1160 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc, 1161 pctl); 1162 1163 if (IS_ERR(pctl->pctl_dev)) { 1164 dev_err(&pdev->dev, "Failed pinctrl registration\n"); 1165 return PTR_ERR(pctl->pctl_dev); 1166 } 1167 1168 for_each_child_of_node(np, child) 1169 if (of_property_read_bool(child, "gpio-controller")) 1170 banks++; 1171 1172 if (!banks) { 1173 dev_err(dev, "at least one GPIO bank is required\n"); 1174 return -EINVAL; 1175 } 1176 pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks), 1177 GFP_KERNEL); 1178 if (!pctl->banks) 1179 return -ENOMEM; 1180 1181 for_each_child_of_node(np, child) { 1182 if (of_property_read_bool(child, "gpio-controller")) { 1183 ret = stm32_gpiolib_register_bank(pctl, child); 1184 if (ret) 1185 return ret; 1186 1187 pctl->nbanks++; 1188 } 1189 } 1190 1191 dev_info(dev, "Pinctrl STM32 initialized\n"); 1192 1193 return 0; 1194 } 1195 1196