1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Pinctrl / GPIO driver for StarFive JH7110 SoC 4 * 5 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk> 6 * Copyright (C) 2022 StarFive Technology Co., Ltd. 7 */ 8 9 #include <linux/bits.h> 10 #include <linux/clk.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/io.h> 13 #include <linux/mod_devicetable.h> 14 #include <linux/module.h> 15 #include <linux/mutex.h> 16 #include <linux/of.h> 17 #include <linux/of_device.h> 18 #include <linux/platform_device.h> 19 #include <linux/reset.h> 20 #include <linux/seq_file.h> 21 #include <linux/spinlock.h> 22 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/pinctrl/pinconf.h> 25 #include <linux/pinctrl/pinctrl.h> 26 #include <linux/pinctrl/pinmux.h> 27 28 #include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h> 29 30 #include "../core.h" 31 #include "../pinctrl-utils.h" 32 #include "../pinmux.h" 33 #include "../pinconf.h" 34 #include "pinctrl-starfive-jh7110.h" 35 36 /* pad control bits */ 37 #define JH7110_PADCFG_POS BIT(7) 38 #define JH7110_PADCFG_SMT BIT(6) 39 #define JH7110_PADCFG_SLEW BIT(5) 40 #define JH7110_PADCFG_PD BIT(4) 41 #define JH7110_PADCFG_PU BIT(3) 42 #define JH7110_PADCFG_BIAS (JH7110_PADCFG_PD | JH7110_PADCFG_PU) 43 #define JH7110_PADCFG_DS_MASK GENMASK(2, 1) 44 #define JH7110_PADCFG_DS_2MA (0U << 1) 45 #define JH7110_PADCFG_DS_4MA BIT(1) 46 #define JH7110_PADCFG_DS_8MA (2U << 1) 47 #define JH7110_PADCFG_DS_12MA (3U << 1) 48 #define JH7110_PADCFG_IE BIT(0) 49 50 /* 51 * The packed pinmux values from the device tree look like this: 52 * 53 * | 31 - 24 | 23 - 16 | 15 - 10 | 9 - 8 | 7 - 0 | 54 * | din | dout | doen | function | pin | 55 */ 56 static unsigned int jh7110_pinmux_din(u32 v) 57 { 58 return (v & GENMASK(31, 24)) >> 24; 59 } 60 61 static u32 jh7110_pinmux_dout(u32 v) 62 { 63 return (v & GENMASK(23, 16)) >> 16; 64 } 65 66 static u32 jh7110_pinmux_doen(u32 v) 67 { 68 return (v & GENMASK(15, 10)) >> 10; 69 } 70 71 static u32 jh7110_pinmux_function(u32 v) 72 { 73 return (v & GENMASK(9, 8)) >> 8; 74 } 75 76 static unsigned int jh7110_pinmux_pin(u32 v) 77 { 78 return v & GENMASK(7, 0); 79 } 80 81 static struct jh7110_pinctrl *jh7110_from_irq_data(struct irq_data *d) 82 { 83 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 84 85 return container_of(gc, struct jh7110_pinctrl, gc); 86 } 87 88 struct jh7110_pinctrl *jh7110_from_irq_desc(struct irq_desc *desc) 89 { 90 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 91 92 return container_of(gc, struct jh7110_pinctrl, gc); 93 } 94 EXPORT_SYMBOL_GPL(jh7110_from_irq_desc); 95 96 #ifdef CONFIG_DEBUG_FS 97 static void jh7110_pin_dbg_show(struct pinctrl_dev *pctldev, 98 struct seq_file *s, unsigned int pin) 99 { 100 struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); 101 const struct jh7110_pinctrl_soc_info *info = sfp->info; 102 103 seq_printf(s, "%s", dev_name(pctldev->dev)); 104 105 if (pin < sfp->gc.ngpio) { 106 unsigned int offset = 4 * (pin / 4); 107 unsigned int shift = 8 * (pin % 4); 108 u32 dout = readl_relaxed(sfp->base + info->dout_reg_base + offset); 109 u32 doen = readl_relaxed(sfp->base + info->doen_reg_base + offset); 110 u32 gpi = readl_relaxed(sfp->base + info->gpi_reg_base + offset); 111 112 dout = (dout >> shift) & info->dout_mask; 113 doen = (doen >> shift) & info->doen_mask; 114 gpi = ((gpi >> shift) - 2) & info->gpi_mask; 115 116 seq_printf(s, " dout=%u doen=%u din=%u", dout, doen, gpi); 117 } 118 } 119 #else 120 #define jh7110_pin_dbg_show NULL 121 #endif 122 123 static int jh7110_dt_node_to_map(struct pinctrl_dev *pctldev, 124 struct device_node *np, 125 struct pinctrl_map **maps, 126 unsigned int *num_maps) 127 { 128 struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); 129 struct device *dev = sfp->gc.parent; 130 struct device_node *child; 131 struct pinctrl_map *map; 132 const char **pgnames; 133 const char *grpname; 134 int ngroups; 135 int nmaps; 136 int ret; 137 138 ngroups = 0; 139 for_each_child_of_node(np, child) 140 ngroups += 1; 141 nmaps = 2 * ngroups; 142 143 pgnames = devm_kcalloc(dev, ngroups, sizeof(*pgnames), GFP_KERNEL); 144 if (!pgnames) 145 return -ENOMEM; 146 147 map = kcalloc(nmaps, sizeof(*map), GFP_KERNEL); 148 if (!map) 149 return -ENOMEM; 150 151 nmaps = 0; 152 ngroups = 0; 153 mutex_lock(&sfp->mutex); 154 for_each_child_of_node(np, child) { 155 int npins = of_property_count_u32_elems(child, "pinmux"); 156 int *pins; 157 u32 *pinmux; 158 int i; 159 160 if (npins < 1) { 161 dev_err(dev, 162 "invalid pinctrl group %pOFn.%pOFn: pinmux not set\n", 163 np, child); 164 ret = -EINVAL; 165 goto put_child; 166 } 167 168 grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", np, child); 169 if (!grpname) { 170 ret = -ENOMEM; 171 goto put_child; 172 } 173 174 pgnames[ngroups++] = grpname; 175 176 pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL); 177 if (!pins) { 178 ret = -ENOMEM; 179 goto put_child; 180 } 181 182 pinmux = devm_kcalloc(dev, npins, sizeof(*pinmux), GFP_KERNEL); 183 if (!pinmux) { 184 ret = -ENOMEM; 185 goto put_child; 186 } 187 188 ret = of_property_read_u32_array(child, "pinmux", pinmux, npins); 189 if (ret) 190 goto put_child; 191 192 for (i = 0; i < npins; i++) 193 pins[i] = jh7110_pinmux_pin(pinmux[i]); 194 195 map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP; 196 map[nmaps].data.mux.function = np->name; 197 map[nmaps].data.mux.group = grpname; 198 nmaps += 1; 199 200 ret = pinctrl_generic_add_group(pctldev, grpname, 201 pins, npins, pinmux); 202 if (ret < 0) { 203 dev_err(dev, "error adding group %s: %d\n", grpname, ret); 204 goto put_child; 205 } 206 207 ret = pinconf_generic_parse_dt_config(child, pctldev, 208 &map[nmaps].data.configs.configs, 209 &map[nmaps].data.configs.num_configs); 210 if (ret) { 211 dev_err(dev, "error parsing pin config of group %s: %d\n", 212 grpname, ret); 213 goto put_child; 214 } 215 216 /* don't create a map if there are no pinconf settings */ 217 if (map[nmaps].data.configs.num_configs == 0) 218 continue; 219 220 map[nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP; 221 map[nmaps].data.configs.group_or_pin = grpname; 222 nmaps += 1; 223 } 224 225 ret = pinmux_generic_add_function(pctldev, np->name, 226 pgnames, ngroups, NULL); 227 if (ret < 0) { 228 dev_err(dev, "error adding function %s: %d\n", np->name, ret); 229 goto free_map; 230 } 231 mutex_unlock(&sfp->mutex); 232 233 *maps = map; 234 *num_maps = nmaps; 235 return 0; 236 237 put_child: 238 of_node_put(child); 239 free_map: 240 pinctrl_utils_free_map(pctldev, map, nmaps); 241 mutex_unlock(&sfp->mutex); 242 return ret; 243 } 244 245 static const struct pinctrl_ops jh7110_pinctrl_ops = { 246 .get_groups_count = pinctrl_generic_get_group_count, 247 .get_group_name = pinctrl_generic_get_group_name, 248 .get_group_pins = pinctrl_generic_get_group_pins, 249 .pin_dbg_show = jh7110_pin_dbg_show, 250 .dt_node_to_map = jh7110_dt_node_to_map, 251 .dt_free_map = pinctrl_utils_free_map, 252 }; 253 254 void jh7110_set_gpiomux(struct jh7110_pinctrl *sfp, unsigned int pin, 255 unsigned int din, u32 dout, u32 doen) 256 { 257 const struct jh7110_pinctrl_soc_info *info = sfp->info; 258 259 unsigned int offset = 4 * (pin / 4); 260 unsigned int shift = 8 * (pin % 4); 261 u32 dout_mask = info->dout_mask << shift; 262 u32 done_mask = info->doen_mask << shift; 263 u32 ival, imask; 264 void __iomem *reg_dout; 265 void __iomem *reg_doen; 266 void __iomem *reg_din; 267 unsigned long flags; 268 269 reg_dout = sfp->base + info->dout_reg_base + offset; 270 reg_doen = sfp->base + info->doen_reg_base + offset; 271 dout <<= shift; 272 doen <<= shift; 273 if (din != GPI_NONE) { 274 unsigned int ioffset = 4 * (din / 4); 275 unsigned int ishift = 8 * (din % 4); 276 277 reg_din = sfp->base + info->gpi_reg_base + ioffset; 278 ival = (pin + 2) << ishift; 279 imask = info->gpi_mask << ishift; 280 } else { 281 reg_din = NULL; 282 } 283 284 raw_spin_lock_irqsave(&sfp->lock, flags); 285 dout |= readl_relaxed(reg_dout) & ~dout_mask; 286 writel_relaxed(dout, reg_dout); 287 doen |= readl_relaxed(reg_doen) & ~done_mask; 288 writel_relaxed(doen, reg_doen); 289 if (reg_din) { 290 ival |= readl_relaxed(reg_din) & ~imask; 291 writel_relaxed(ival, reg_din); 292 } 293 raw_spin_unlock_irqrestore(&sfp->lock, flags); 294 } 295 EXPORT_SYMBOL_GPL(jh7110_set_gpiomux); 296 297 static int jh7110_set_mux(struct pinctrl_dev *pctldev, 298 unsigned int fsel, unsigned int gsel) 299 { 300 struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); 301 const struct jh7110_pinctrl_soc_info *info = sfp->info; 302 const struct group_desc *group; 303 const u32 *pinmux; 304 unsigned int i; 305 306 group = pinctrl_generic_get_group(pctldev, gsel); 307 if (!group) 308 return -EINVAL; 309 310 pinmux = group->data; 311 for (i = 0; i < group->num_pins; i++) { 312 u32 v = pinmux[i]; 313 314 if (info->jh7110_set_one_pin_mux) 315 info->jh7110_set_one_pin_mux(sfp, 316 jh7110_pinmux_pin(v), 317 jh7110_pinmux_din(v), 318 jh7110_pinmux_dout(v), 319 jh7110_pinmux_doen(v), 320 jh7110_pinmux_function(v)); 321 } 322 323 return 0; 324 } 325 326 static const struct pinmux_ops jh7110_pinmux_ops = { 327 .get_functions_count = pinmux_generic_get_function_count, 328 .get_function_name = pinmux_generic_get_function_name, 329 .get_function_groups = pinmux_generic_get_function_groups, 330 .set_mux = jh7110_set_mux, 331 .strict = true, 332 }; 333 334 static const u8 jh7110_drive_strength_mA[4] = { 2, 4, 8, 12 }; 335 336 static u32 jh7110_padcfg_ds_to_mA(u32 padcfg) 337 { 338 return jh7110_drive_strength_mA[(padcfg >> 1) & 3U]; 339 } 340 341 static u32 jh7110_padcfg_ds_from_mA(u32 v) 342 { 343 int i; 344 345 for (i = 0; i < 3; i++) { 346 if (v <= jh7110_drive_strength_mA[i]) 347 break; 348 } 349 return i << 1; 350 } 351 352 static void jh7110_padcfg_rmw(struct jh7110_pinctrl *sfp, 353 unsigned int pin, u32 mask, u32 value) 354 { 355 const struct jh7110_pinctrl_soc_info *info = sfp->info; 356 void __iomem *reg; 357 unsigned long flags; 358 int padcfg_base; 359 360 if (!info->jh7110_get_padcfg_base) 361 return; 362 363 padcfg_base = info->jh7110_get_padcfg_base(sfp, pin); 364 if (padcfg_base < 0) 365 return; 366 367 reg = sfp->base + padcfg_base + 4 * pin; 368 value &= mask; 369 370 raw_spin_lock_irqsave(&sfp->lock, flags); 371 value |= readl_relaxed(reg) & ~mask; 372 writel_relaxed(value, reg); 373 raw_spin_unlock_irqrestore(&sfp->lock, flags); 374 } 375 376 static int jh7110_pinconf_get(struct pinctrl_dev *pctldev, 377 unsigned int pin, unsigned long *config) 378 { 379 struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); 380 const struct jh7110_pinctrl_soc_info *info = sfp->info; 381 int param = pinconf_to_config_param(*config); 382 u32 padcfg, arg; 383 bool enabled; 384 int padcfg_base; 385 386 if (!info->jh7110_get_padcfg_base) 387 return 0; 388 389 padcfg_base = info->jh7110_get_padcfg_base(sfp, pin); 390 if (padcfg_base < 0) 391 return 0; 392 393 padcfg = readl_relaxed(sfp->base + padcfg_base + 4 * pin); 394 switch (param) { 395 case PIN_CONFIG_BIAS_DISABLE: 396 enabled = !(padcfg & JH7110_PADCFG_BIAS); 397 arg = 0; 398 break; 399 case PIN_CONFIG_BIAS_PULL_DOWN: 400 enabled = padcfg & JH7110_PADCFG_PD; 401 arg = 1; 402 break; 403 case PIN_CONFIG_BIAS_PULL_UP: 404 enabled = padcfg & JH7110_PADCFG_PU; 405 arg = 1; 406 break; 407 case PIN_CONFIG_DRIVE_STRENGTH: 408 enabled = true; 409 arg = jh7110_padcfg_ds_to_mA(padcfg); 410 break; 411 case PIN_CONFIG_INPUT_ENABLE: 412 enabled = padcfg & JH7110_PADCFG_IE; 413 arg = enabled; 414 break; 415 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 416 enabled = padcfg & JH7110_PADCFG_SMT; 417 arg = enabled; 418 break; 419 case PIN_CONFIG_SLEW_RATE: 420 enabled = true; 421 arg = !!(padcfg & JH7110_PADCFG_SLEW); 422 break; 423 default: 424 return -ENOTSUPP; 425 } 426 427 *config = pinconf_to_config_packed(param, arg); 428 return enabled ? 0 : -EINVAL; 429 } 430 431 static int jh7110_pinconf_group_get(struct pinctrl_dev *pctldev, 432 unsigned int gsel, 433 unsigned long *config) 434 { 435 const struct group_desc *group; 436 437 group = pinctrl_generic_get_group(pctldev, gsel); 438 if (!group) 439 return -EINVAL; 440 441 return jh7110_pinconf_get(pctldev, group->pins[0], config); 442 } 443 444 static int jh7110_pinconf_group_set(struct pinctrl_dev *pctldev, 445 unsigned int gsel, 446 unsigned long *configs, 447 unsigned int num_configs) 448 { 449 struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); 450 const struct group_desc *group; 451 u16 mask, value; 452 int i; 453 454 group = pinctrl_generic_get_group(pctldev, gsel); 455 if (!group) 456 return -EINVAL; 457 458 mask = 0; 459 value = 0; 460 for (i = 0; i < num_configs; i++) { 461 int param = pinconf_to_config_param(configs[i]); 462 u32 arg = pinconf_to_config_argument(configs[i]); 463 464 switch (param) { 465 case PIN_CONFIG_BIAS_DISABLE: 466 mask |= JH7110_PADCFG_BIAS; 467 value &= ~JH7110_PADCFG_BIAS; 468 break; 469 case PIN_CONFIG_BIAS_PULL_DOWN: 470 if (arg == 0) 471 return -ENOTSUPP; 472 mask |= JH7110_PADCFG_BIAS; 473 value = (value & ~JH7110_PADCFG_BIAS) | JH7110_PADCFG_PD; 474 break; 475 case PIN_CONFIG_BIAS_PULL_UP: 476 if (arg == 0) 477 return -ENOTSUPP; 478 mask |= JH7110_PADCFG_BIAS; 479 value = (value & ~JH7110_PADCFG_BIAS) | JH7110_PADCFG_PU; 480 break; 481 case PIN_CONFIG_DRIVE_STRENGTH: 482 mask |= JH7110_PADCFG_DS_MASK; 483 value = (value & ~JH7110_PADCFG_DS_MASK) | 484 jh7110_padcfg_ds_from_mA(arg); 485 break; 486 case PIN_CONFIG_INPUT_ENABLE: 487 mask |= JH7110_PADCFG_IE; 488 if (arg) 489 value |= JH7110_PADCFG_IE; 490 else 491 value &= ~JH7110_PADCFG_IE; 492 break; 493 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 494 mask |= JH7110_PADCFG_SMT; 495 if (arg) 496 value |= JH7110_PADCFG_SMT; 497 else 498 value &= ~JH7110_PADCFG_SMT; 499 break; 500 case PIN_CONFIG_SLEW_RATE: 501 mask |= JH7110_PADCFG_SLEW; 502 if (arg) 503 value |= JH7110_PADCFG_SLEW; 504 else 505 value &= ~JH7110_PADCFG_SLEW; 506 break; 507 default: 508 return -ENOTSUPP; 509 } 510 } 511 512 for (i = 0; i < group->num_pins; i++) 513 jh7110_padcfg_rmw(sfp, group->pins[i], mask, value); 514 515 return 0; 516 } 517 518 #ifdef CONFIG_DEBUG_FS 519 static void jh7110_pinconf_dbg_show(struct pinctrl_dev *pctldev, 520 struct seq_file *s, unsigned int pin) 521 { 522 struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); 523 const struct jh7110_pinctrl_soc_info *info = sfp->info; 524 u32 value; 525 int padcfg_base; 526 527 if (!info->jh7110_get_padcfg_base) 528 return; 529 530 padcfg_base = info->jh7110_get_padcfg_base(sfp, pin); 531 if (padcfg_base < 0) 532 return; 533 534 value = readl_relaxed(sfp->base + padcfg_base + 4 * pin); 535 seq_printf(s, " (0x%02x)", value); 536 } 537 #else 538 #define jh7110_pinconf_dbg_show NULL 539 #endif 540 541 static const struct pinconf_ops jh7110_pinconf_ops = { 542 .pin_config_get = jh7110_pinconf_get, 543 .pin_config_group_get = jh7110_pinconf_group_get, 544 .pin_config_group_set = jh7110_pinconf_group_set, 545 .pin_config_dbg_show = jh7110_pinconf_dbg_show, 546 .is_generic = true, 547 }; 548 549 static int jh7110_gpio_request(struct gpio_chip *gc, unsigned int gpio) 550 { 551 return pinctrl_gpio_request(gc->base + gpio); 552 } 553 554 static void jh7110_gpio_free(struct gpio_chip *gc, unsigned int gpio) 555 { 556 pinctrl_gpio_free(gc->base + gpio); 557 } 558 559 static int jh7110_gpio_get_direction(struct gpio_chip *gc, 560 unsigned int gpio) 561 { 562 struct jh7110_pinctrl *sfp = container_of(gc, 563 struct jh7110_pinctrl, gc); 564 const struct jh7110_pinctrl_soc_info *info = sfp->info; 565 unsigned int offset = 4 * (gpio / 4); 566 unsigned int shift = 8 * (gpio % 4); 567 u32 doen = readl_relaxed(sfp->base + info->doen_reg_base + offset); 568 569 doen = (doen >> shift) & info->doen_mask; 570 571 return doen == GPOEN_ENABLE ? 572 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 573 } 574 575 static int jh7110_gpio_direction_input(struct gpio_chip *gc, 576 unsigned int gpio) 577 { 578 struct jh7110_pinctrl *sfp = container_of(gc, 579 struct jh7110_pinctrl, gc); 580 const struct jh7110_pinctrl_soc_info *info = sfp->info; 581 582 /* enable input and schmitt trigger */ 583 jh7110_padcfg_rmw(sfp, gpio, 584 JH7110_PADCFG_IE | JH7110_PADCFG_SMT, 585 JH7110_PADCFG_IE | JH7110_PADCFG_SMT); 586 587 if (info->jh7110_set_one_pin_mux) 588 info->jh7110_set_one_pin_mux(sfp, gpio, 589 GPI_NONE, GPOUT_LOW, GPOEN_DISABLE, 0); 590 591 return 0; 592 } 593 594 static int jh7110_gpio_direction_output(struct gpio_chip *gc, 595 unsigned int gpio, int value) 596 { 597 struct jh7110_pinctrl *sfp = container_of(gc, 598 struct jh7110_pinctrl, gc); 599 const struct jh7110_pinctrl_soc_info *info = sfp->info; 600 601 if (info->jh7110_set_one_pin_mux) 602 info->jh7110_set_one_pin_mux(sfp, gpio, 603 GPI_NONE, value ? GPOUT_HIGH : GPOUT_LOW, 604 GPOEN_ENABLE, 0); 605 606 /* disable input, schmitt trigger and bias */ 607 jh7110_padcfg_rmw(sfp, gpio, 608 JH7110_PADCFG_IE | JH7110_PADCFG_SMT | 609 JH7110_PADCFG_BIAS, 0); 610 return 0; 611 } 612 613 static int jh7110_gpio_get(struct gpio_chip *gc, unsigned int gpio) 614 { 615 struct jh7110_pinctrl *sfp = container_of(gc, 616 struct jh7110_pinctrl, gc); 617 const struct jh7110_pinctrl_soc_info *info = sfp->info; 618 void __iomem *reg = sfp->base + info->gpioin_reg_base 619 + 4 * (gpio / 32); 620 621 return !!(readl_relaxed(reg) & BIT(gpio % 32)); 622 } 623 624 static void jh7110_gpio_set(struct gpio_chip *gc, 625 unsigned int gpio, int value) 626 { 627 struct jh7110_pinctrl *sfp = container_of(gc, 628 struct jh7110_pinctrl, gc); 629 const struct jh7110_pinctrl_soc_info *info = sfp->info; 630 unsigned int offset = 4 * (gpio / 4); 631 unsigned int shift = 8 * (gpio % 4); 632 void __iomem *reg_dout = sfp->base + info->dout_reg_base + offset; 633 u32 dout = (value ? GPOUT_HIGH : GPOUT_LOW) << shift; 634 u32 mask = info->dout_mask << shift; 635 unsigned long flags; 636 637 raw_spin_lock_irqsave(&sfp->lock, flags); 638 dout |= readl_relaxed(reg_dout) & ~mask; 639 writel_relaxed(dout, reg_dout); 640 raw_spin_unlock_irqrestore(&sfp->lock, flags); 641 } 642 643 static int jh7110_gpio_set_config(struct gpio_chip *gc, 644 unsigned int gpio, unsigned long config) 645 { 646 struct jh7110_pinctrl *sfp = container_of(gc, 647 struct jh7110_pinctrl, gc); 648 u32 arg = pinconf_to_config_argument(config); 649 u32 value; 650 u32 mask; 651 652 switch (pinconf_to_config_param(config)) { 653 case PIN_CONFIG_BIAS_DISABLE: 654 mask = JH7110_PADCFG_BIAS; 655 value = 0; 656 break; 657 case PIN_CONFIG_BIAS_PULL_DOWN: 658 if (arg == 0) 659 return -ENOTSUPP; 660 mask = JH7110_PADCFG_BIAS; 661 value = JH7110_PADCFG_PD; 662 break; 663 case PIN_CONFIG_BIAS_PULL_UP: 664 if (arg == 0) 665 return -ENOTSUPP; 666 mask = JH7110_PADCFG_BIAS; 667 value = JH7110_PADCFG_PU; 668 break; 669 case PIN_CONFIG_DRIVE_PUSH_PULL: 670 return 0; 671 case PIN_CONFIG_INPUT_ENABLE: 672 mask = JH7110_PADCFG_IE; 673 value = arg ? JH7110_PADCFG_IE : 0; 674 break; 675 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 676 mask = JH7110_PADCFG_SMT; 677 value = arg ? JH7110_PADCFG_SMT : 0; 678 break; 679 default: 680 return -ENOTSUPP; 681 } 682 683 jh7110_padcfg_rmw(sfp, gpio, mask, value); 684 return 0; 685 } 686 687 static int jh7110_gpio_add_pin_ranges(struct gpio_chip *gc) 688 { 689 struct jh7110_pinctrl *sfp = container_of(gc, 690 struct jh7110_pinctrl, gc); 691 692 sfp->gpios.name = sfp->gc.label; 693 sfp->gpios.base = sfp->gc.base; 694 sfp->gpios.pin_base = 0; 695 sfp->gpios.npins = sfp->gc.ngpio; 696 sfp->gpios.gc = &sfp->gc; 697 pinctrl_add_gpio_range(sfp->pctl, &sfp->gpios); 698 return 0; 699 } 700 701 static void jh7110_irq_ack(struct irq_data *d) 702 { 703 struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d); 704 const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg; 705 irq_hw_number_t gpio = irqd_to_hwirq(d); 706 void __iomem *ic = sfp->base + irq_reg->ic_reg_base 707 + 4 * (gpio / 32); 708 u32 mask = BIT(gpio % 32); 709 unsigned long flags; 710 u32 value; 711 712 raw_spin_lock_irqsave(&sfp->lock, flags); 713 value = readl_relaxed(ic) & ~mask; 714 writel_relaxed(value, ic); 715 writel_relaxed(value | mask, ic); 716 raw_spin_unlock_irqrestore(&sfp->lock, flags); 717 } 718 719 static void jh7110_irq_mask(struct irq_data *d) 720 { 721 struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d); 722 const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg; 723 irq_hw_number_t gpio = irqd_to_hwirq(d); 724 void __iomem *ie = sfp->base + irq_reg->ie_reg_base 725 + 4 * (gpio / 32); 726 u32 mask = BIT(gpio % 32); 727 unsigned long flags; 728 u32 value; 729 730 raw_spin_lock_irqsave(&sfp->lock, flags); 731 value = readl_relaxed(ie) & ~mask; 732 writel_relaxed(value, ie); 733 raw_spin_unlock_irqrestore(&sfp->lock, flags); 734 735 gpiochip_disable_irq(&sfp->gc, d->hwirq); 736 } 737 738 static void jh7110_irq_mask_ack(struct irq_data *d) 739 { 740 struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d); 741 const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg; 742 irq_hw_number_t gpio = irqd_to_hwirq(d); 743 void __iomem *ie = sfp->base + irq_reg->ie_reg_base 744 + 4 * (gpio / 32); 745 void __iomem *ic = sfp->base + irq_reg->ic_reg_base 746 + 4 * (gpio / 32); 747 u32 mask = BIT(gpio % 32); 748 unsigned long flags; 749 u32 value; 750 751 raw_spin_lock_irqsave(&sfp->lock, flags); 752 value = readl_relaxed(ie) & ~mask; 753 writel_relaxed(value, ie); 754 755 value = readl_relaxed(ic) & ~mask; 756 writel_relaxed(value, ic); 757 writel_relaxed(value | mask, ic); 758 raw_spin_unlock_irqrestore(&sfp->lock, flags); 759 } 760 761 static void jh7110_irq_unmask(struct irq_data *d) 762 { 763 struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d); 764 const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg; 765 irq_hw_number_t gpio = irqd_to_hwirq(d); 766 void __iomem *ie = sfp->base + irq_reg->ie_reg_base 767 + 4 * (gpio / 32); 768 u32 mask = BIT(gpio % 32); 769 unsigned long flags; 770 u32 value; 771 772 gpiochip_enable_irq(&sfp->gc, d->hwirq); 773 774 raw_spin_lock_irqsave(&sfp->lock, flags); 775 value = readl_relaxed(ie) | mask; 776 writel_relaxed(value, ie); 777 raw_spin_unlock_irqrestore(&sfp->lock, flags); 778 } 779 780 static int jh7110_irq_set_type(struct irq_data *d, unsigned int trigger) 781 { 782 struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d); 783 const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg; 784 irq_hw_number_t gpio = irqd_to_hwirq(d); 785 void __iomem *base = sfp->base + 4 * (gpio / 32); 786 u32 mask = BIT(gpio % 32); 787 u32 irq_type, edge_both, polarity; 788 unsigned long flags; 789 790 switch (trigger) { 791 case IRQ_TYPE_EDGE_RISING: 792 irq_type = mask; /* 1: edge triggered */ 793 edge_both = 0; /* 0: single edge */ 794 polarity = mask; /* 1: rising edge */ 795 break; 796 case IRQ_TYPE_EDGE_FALLING: 797 irq_type = mask; /* 1: edge triggered */ 798 edge_both = 0; /* 0: single edge */ 799 polarity = 0; /* 0: falling edge */ 800 break; 801 case IRQ_TYPE_EDGE_BOTH: 802 irq_type = mask; /* 1: edge triggered */ 803 edge_both = mask; /* 1: both edges */ 804 polarity = 0; /* 0: ignored */ 805 break; 806 case IRQ_TYPE_LEVEL_HIGH: 807 irq_type = 0; /* 0: level triggered */ 808 edge_both = 0; /* 0: ignored */ 809 polarity = mask; /* 1: high level */ 810 break; 811 case IRQ_TYPE_LEVEL_LOW: 812 irq_type = 0; /* 0: level triggered */ 813 edge_both = 0; /* 0: ignored */ 814 polarity = 0; /* 0: low level */ 815 break; 816 default: 817 return -EINVAL; 818 } 819 820 if (trigger & IRQ_TYPE_EDGE_BOTH) 821 irq_set_handler_locked(d, handle_edge_irq); 822 else 823 irq_set_handler_locked(d, handle_level_irq); 824 825 raw_spin_lock_irqsave(&sfp->lock, flags); 826 irq_type |= readl_relaxed(base + irq_reg->is_reg_base) & ~mask; 827 writel_relaxed(irq_type, base + irq_reg->is_reg_base); 828 829 edge_both |= readl_relaxed(base + irq_reg->ibe_reg_base) & ~mask; 830 writel_relaxed(edge_both, base + irq_reg->ibe_reg_base); 831 832 polarity |= readl_relaxed(base + irq_reg->iev_reg_base) & ~mask; 833 writel_relaxed(polarity, base + irq_reg->iev_reg_base); 834 raw_spin_unlock_irqrestore(&sfp->lock, flags); 835 return 0; 836 } 837 838 static struct irq_chip jh7110_irq_chip = { 839 .irq_ack = jh7110_irq_ack, 840 .irq_mask = jh7110_irq_mask, 841 .irq_mask_ack = jh7110_irq_mask_ack, 842 .irq_unmask = jh7110_irq_unmask, 843 .irq_set_type = jh7110_irq_set_type, 844 .flags = IRQCHIP_IMMUTABLE | IRQCHIP_SET_TYPE_MASKED, 845 GPIOCHIP_IRQ_RESOURCE_HELPERS, 846 }; 847 848 static void jh7110_disable_clock(void *data) 849 { 850 clk_disable_unprepare(data); 851 } 852 853 int jh7110_pinctrl_probe(struct platform_device *pdev) 854 { 855 struct device *dev = &pdev->dev; 856 const struct jh7110_pinctrl_soc_info *info; 857 struct jh7110_pinctrl *sfp; 858 struct pinctrl_desc *jh7110_pinctrl_desc; 859 struct reset_control *rst; 860 struct clk *clk; 861 int ret; 862 863 info = of_device_get_match_data(&pdev->dev); 864 if (!info) 865 return -ENODEV; 866 867 if (!info->pins || !info->npins) { 868 dev_err(dev, "wrong pinctrl info\n"); 869 return -EINVAL; 870 } 871 872 sfp = devm_kzalloc(dev, sizeof(*sfp), GFP_KERNEL); 873 if (!sfp) 874 return -ENOMEM; 875 876 sfp->base = devm_platform_ioremap_resource(pdev, 0); 877 if (IS_ERR(sfp->base)) 878 return PTR_ERR(sfp->base); 879 880 clk = devm_clk_get_optional(dev, NULL); 881 if (IS_ERR(clk)) 882 return dev_err_probe(dev, PTR_ERR(clk), "could not get clock\n"); 883 884 rst = devm_reset_control_get_exclusive(dev, NULL); 885 if (IS_ERR(rst)) 886 return dev_err_probe(dev, PTR_ERR(rst), "could not get reset\n"); 887 888 /* 889 * we don't want to assert reset and risk undoing pin muxing for the 890 * early boot serial console, but let's make sure the reset line is 891 * deasserted in case someone runs a really minimal bootloader. 892 */ 893 ret = reset_control_deassert(rst); 894 if (ret) 895 return dev_err_probe(dev, ret, "could not deassert reset\n"); 896 897 if (clk) { 898 ret = clk_prepare_enable(clk); 899 if (ret) 900 return dev_err_probe(dev, ret, "could not enable clock\n"); 901 902 ret = devm_add_action_or_reset(dev, jh7110_disable_clock, clk); 903 if (ret) 904 return ret; 905 } 906 907 jh7110_pinctrl_desc = devm_kzalloc(&pdev->dev, 908 sizeof(*jh7110_pinctrl_desc), 909 GFP_KERNEL); 910 if (!jh7110_pinctrl_desc) 911 return -ENOMEM; 912 913 jh7110_pinctrl_desc->name = dev_name(dev); 914 jh7110_pinctrl_desc->pins = info->pins; 915 jh7110_pinctrl_desc->npins = info->npins; 916 jh7110_pinctrl_desc->pctlops = &jh7110_pinctrl_ops; 917 jh7110_pinctrl_desc->pmxops = &jh7110_pinmux_ops; 918 jh7110_pinctrl_desc->confops = &jh7110_pinconf_ops; 919 jh7110_pinctrl_desc->owner = THIS_MODULE; 920 921 sfp->info = info; 922 sfp->dev = dev; 923 platform_set_drvdata(pdev, sfp); 924 sfp->gc.parent = dev; 925 raw_spin_lock_init(&sfp->lock); 926 mutex_init(&sfp->mutex); 927 928 ret = devm_pinctrl_register_and_init(dev, 929 jh7110_pinctrl_desc, 930 sfp, &sfp->pctl); 931 if (ret) 932 return dev_err_probe(dev, ret, 933 "could not register pinctrl driver\n"); 934 935 sfp->gc.label = dev_name(dev); 936 sfp->gc.owner = THIS_MODULE; 937 sfp->gc.request = jh7110_gpio_request; 938 sfp->gc.free = jh7110_gpio_free; 939 sfp->gc.get_direction = jh7110_gpio_get_direction; 940 sfp->gc.direction_input = jh7110_gpio_direction_input; 941 sfp->gc.direction_output = jh7110_gpio_direction_output; 942 sfp->gc.get = jh7110_gpio_get; 943 sfp->gc.set = jh7110_gpio_set; 944 sfp->gc.set_config = jh7110_gpio_set_config; 945 sfp->gc.add_pin_ranges = jh7110_gpio_add_pin_ranges; 946 sfp->gc.base = info->gc_base; 947 sfp->gc.ngpio = info->ngpios; 948 949 jh7110_irq_chip.name = sfp->gc.label; 950 gpio_irq_chip_set_chip(&sfp->gc.irq, &jh7110_irq_chip); 951 sfp->gc.irq.parent_handler = info->jh7110_gpio_irq_handler; 952 sfp->gc.irq.num_parents = 1; 953 sfp->gc.irq.parents = devm_kcalloc(dev, sfp->gc.irq.num_parents, 954 sizeof(*sfp->gc.irq.parents), 955 GFP_KERNEL); 956 if (!sfp->gc.irq.parents) 957 return -ENOMEM; 958 sfp->gc.irq.default_type = IRQ_TYPE_NONE; 959 sfp->gc.irq.handler = handle_bad_irq; 960 sfp->gc.irq.init_hw = info->jh7110_gpio_init_hw; 961 962 ret = platform_get_irq(pdev, 0); 963 if (ret < 0) 964 return ret; 965 sfp->gc.irq.parents[0] = ret; 966 967 ret = devm_gpiochip_add_data(dev, &sfp->gc, sfp); 968 if (ret) 969 return dev_err_probe(dev, ret, "could not register gpiochip\n"); 970 971 irq_domain_set_pm_device(sfp->gc.irq.domain, dev); 972 973 dev_info(dev, "StarFive GPIO chip registered %d GPIOs\n", sfp->gc.ngpio); 974 975 return pinctrl_enable(sfp->pctl); 976 } 977 EXPORT_SYMBOL_GPL(jh7110_pinctrl_probe); 978 979 MODULE_DESCRIPTION("Pinctrl driver for the StarFive JH7110 SoC"); 980 MODULE_AUTHOR("Emil Renner Berthing <kernel@esmil.dk>"); 981 MODULE_AUTHOR("Jianlong Huang <jianlong.huang@starfivetech.com>"); 982 MODULE_LICENSE("GPL"); 983