1 /*
2  * Driver for the ST Microelectronics SPEAr3xx pinmux
3  *
4  * Copyright (C) 2012 ST Microelectronics
5  * Viresh Kumar <viresh.linux@gmail.com>
6  *
7  * This file is licensed under the terms of the GNU General Public
8  * License version 2. This program is licensed "as is" without any
9  * warranty of any kind, whether express or implied.
10  */
11 
12 #include <linux/pinctrl/pinctrl.h>
13 
14 #include "pinctrl-spear3xx.h"
15 
16 /* pins */
17 static const struct pinctrl_pin_desc spear3xx_pins[] = {
18 	SPEAR_PIN_0_TO_101,
19 };
20 
21 /* firda_pins */
22 static const unsigned firda_pins[] = { 0, 1 };
23 static struct spear_muxreg firda_muxreg[] = {
24 	{
25 		.reg = -1,
26 		.mask = PMX_FIRDA_MASK,
27 		.val = PMX_FIRDA_MASK,
28 	},
29 };
30 
31 static struct spear_modemux firda_modemux[] = {
32 	{
33 		.modes = ~0,
34 		.muxregs = firda_muxreg,
35 		.nmuxregs = ARRAY_SIZE(firda_muxreg),
36 	},
37 };
38 
39 struct spear_pingroup spear3xx_firda_pingroup = {
40 	.name = "firda_grp",
41 	.pins = firda_pins,
42 	.npins = ARRAY_SIZE(firda_pins),
43 	.modemuxs = firda_modemux,
44 	.nmodemuxs = ARRAY_SIZE(firda_modemux),
45 };
46 
47 static const char *const firda_grps[] = { "firda_grp" };
48 struct spear_function spear3xx_firda_function = {
49 	.name = "firda",
50 	.groups = firda_grps,
51 	.ngroups = ARRAY_SIZE(firda_grps),
52 };
53 
54 /* i2c_pins */
55 static const unsigned i2c_pins[] = { 4, 5 };
56 static struct spear_muxreg i2c_muxreg[] = {
57 	{
58 		.reg = -1,
59 		.mask = PMX_I2C_MASK,
60 		.val = PMX_I2C_MASK,
61 	},
62 };
63 
64 static struct spear_modemux i2c_modemux[] = {
65 	{
66 		.modes = ~0,
67 		.muxregs = i2c_muxreg,
68 		.nmuxregs = ARRAY_SIZE(i2c_muxreg),
69 	},
70 };
71 
72 struct spear_pingroup spear3xx_i2c_pingroup = {
73 	.name = "i2c0_grp",
74 	.pins = i2c_pins,
75 	.npins = ARRAY_SIZE(i2c_pins),
76 	.modemuxs = i2c_modemux,
77 	.nmodemuxs = ARRAY_SIZE(i2c_modemux),
78 };
79 
80 static const char *const i2c_grps[] = { "i2c0_grp" };
81 struct spear_function spear3xx_i2c_function = {
82 	.name = "i2c0",
83 	.groups = i2c_grps,
84 	.ngroups = ARRAY_SIZE(i2c_grps),
85 };
86 
87 /* ssp_cs_pins */
88 static const unsigned ssp_cs_pins[] = { 34, 35, 36 };
89 static struct spear_muxreg ssp_cs_muxreg[] = {
90 	{
91 		.reg = -1,
92 		.mask = PMX_SSP_CS_MASK,
93 		.val = PMX_SSP_CS_MASK,
94 	},
95 };
96 
97 static struct spear_modemux ssp_cs_modemux[] = {
98 	{
99 		.modes = ~0,
100 		.muxregs = ssp_cs_muxreg,
101 		.nmuxregs = ARRAY_SIZE(ssp_cs_muxreg),
102 	},
103 };
104 
105 struct spear_pingroup spear3xx_ssp_cs_pingroup = {
106 	.name = "ssp_cs_grp",
107 	.pins = ssp_cs_pins,
108 	.npins = ARRAY_SIZE(ssp_cs_pins),
109 	.modemuxs = ssp_cs_modemux,
110 	.nmodemuxs = ARRAY_SIZE(ssp_cs_modemux),
111 };
112 
113 static const char *const ssp_cs_grps[] = { "ssp_cs_grp" };
114 struct spear_function spear3xx_ssp_cs_function = {
115 	.name = "ssp_cs",
116 	.groups = ssp_cs_grps,
117 	.ngroups = ARRAY_SIZE(ssp_cs_grps),
118 };
119 
120 /* ssp_pins */
121 static const unsigned ssp_pins[] = { 6, 7, 8, 9 };
122 static struct spear_muxreg ssp_muxreg[] = {
123 	{
124 		.reg = -1,
125 		.mask = PMX_SSP_MASK,
126 		.val = PMX_SSP_MASK,
127 	},
128 };
129 
130 static struct spear_modemux ssp_modemux[] = {
131 	{
132 		.modes = ~0,
133 		.muxregs = ssp_muxreg,
134 		.nmuxregs = ARRAY_SIZE(ssp_muxreg),
135 	},
136 };
137 
138 struct spear_pingroup spear3xx_ssp_pingroup = {
139 	.name = "ssp0_grp",
140 	.pins = ssp_pins,
141 	.npins = ARRAY_SIZE(ssp_pins),
142 	.modemuxs = ssp_modemux,
143 	.nmodemuxs = ARRAY_SIZE(ssp_modemux),
144 };
145 
146 static const char *const ssp_grps[] = { "ssp0_grp" };
147 struct spear_function spear3xx_ssp_function = {
148 	.name = "ssp0",
149 	.groups = ssp_grps,
150 	.ngroups = ARRAY_SIZE(ssp_grps),
151 };
152 
153 /* mii_pins */
154 static const unsigned mii_pins[] = { 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
155 	21, 22, 23, 24, 25, 26, 27 };
156 static struct spear_muxreg mii_muxreg[] = {
157 	{
158 		.reg = -1,
159 		.mask = PMX_MII_MASK,
160 		.val = PMX_MII_MASK,
161 	},
162 };
163 
164 static struct spear_modemux mii_modemux[] = {
165 	{
166 		.modes = ~0,
167 		.muxregs = mii_muxreg,
168 		.nmuxregs = ARRAY_SIZE(mii_muxreg),
169 	},
170 };
171 
172 struct spear_pingroup spear3xx_mii_pingroup = {
173 	.name = "mii0_grp",
174 	.pins = mii_pins,
175 	.npins = ARRAY_SIZE(mii_pins),
176 	.modemuxs = mii_modemux,
177 	.nmodemuxs = ARRAY_SIZE(mii_modemux),
178 };
179 
180 static const char *const mii_grps[] = { "mii0_grp" };
181 struct spear_function spear3xx_mii_function = {
182 	.name = "mii0",
183 	.groups = mii_grps,
184 	.ngroups = ARRAY_SIZE(mii_grps),
185 };
186 
187 /* gpio0_pin0_pins */
188 static const unsigned gpio0_pin0_pins[] = { 28 };
189 static struct spear_muxreg gpio0_pin0_muxreg[] = {
190 	{
191 		.reg = -1,
192 		.mask = PMX_GPIO_PIN0_MASK,
193 		.val = PMX_GPIO_PIN0_MASK,
194 	},
195 };
196 
197 static struct spear_modemux gpio0_pin0_modemux[] = {
198 	{
199 		.modes = ~0,
200 		.muxregs = gpio0_pin0_muxreg,
201 		.nmuxregs = ARRAY_SIZE(gpio0_pin0_muxreg),
202 	},
203 };
204 
205 struct spear_pingroup spear3xx_gpio0_pin0_pingroup = {
206 	.name = "gpio0_pin0_grp",
207 	.pins = gpio0_pin0_pins,
208 	.npins = ARRAY_SIZE(gpio0_pin0_pins),
209 	.modemuxs = gpio0_pin0_modemux,
210 	.nmodemuxs = ARRAY_SIZE(gpio0_pin0_modemux),
211 };
212 
213 /* gpio0_pin1_pins */
214 static const unsigned gpio0_pin1_pins[] = { 29 };
215 static struct spear_muxreg gpio0_pin1_muxreg[] = {
216 	{
217 		.reg = -1,
218 		.mask = PMX_GPIO_PIN1_MASK,
219 		.val = PMX_GPIO_PIN1_MASK,
220 	},
221 };
222 
223 static struct spear_modemux gpio0_pin1_modemux[] = {
224 	{
225 		.modes = ~0,
226 		.muxregs = gpio0_pin1_muxreg,
227 		.nmuxregs = ARRAY_SIZE(gpio0_pin1_muxreg),
228 	},
229 };
230 
231 struct spear_pingroup spear3xx_gpio0_pin1_pingroup = {
232 	.name = "gpio0_pin1_grp",
233 	.pins = gpio0_pin1_pins,
234 	.npins = ARRAY_SIZE(gpio0_pin1_pins),
235 	.modemuxs = gpio0_pin1_modemux,
236 	.nmodemuxs = ARRAY_SIZE(gpio0_pin1_modemux),
237 };
238 
239 /* gpio0_pin2_pins */
240 static const unsigned gpio0_pin2_pins[] = { 30 };
241 static struct spear_muxreg gpio0_pin2_muxreg[] = {
242 	{
243 		.reg = -1,
244 		.mask = PMX_GPIO_PIN2_MASK,
245 		.val = PMX_GPIO_PIN2_MASK,
246 	},
247 };
248 
249 static struct spear_modemux gpio0_pin2_modemux[] = {
250 	{
251 		.modes = ~0,
252 		.muxregs = gpio0_pin2_muxreg,
253 		.nmuxregs = ARRAY_SIZE(gpio0_pin2_muxreg),
254 	},
255 };
256 
257 struct spear_pingroup spear3xx_gpio0_pin2_pingroup = {
258 	.name = "gpio0_pin2_grp",
259 	.pins = gpio0_pin2_pins,
260 	.npins = ARRAY_SIZE(gpio0_pin2_pins),
261 	.modemuxs = gpio0_pin2_modemux,
262 	.nmodemuxs = ARRAY_SIZE(gpio0_pin2_modemux),
263 };
264 
265 /* gpio0_pin3_pins */
266 static const unsigned gpio0_pin3_pins[] = { 31 };
267 static struct spear_muxreg gpio0_pin3_muxreg[] = {
268 	{
269 		.reg = -1,
270 		.mask = PMX_GPIO_PIN3_MASK,
271 		.val = PMX_GPIO_PIN3_MASK,
272 	},
273 };
274 
275 static struct spear_modemux gpio0_pin3_modemux[] = {
276 	{
277 		.modes = ~0,
278 		.muxregs = gpio0_pin3_muxreg,
279 		.nmuxregs = ARRAY_SIZE(gpio0_pin3_muxreg),
280 	},
281 };
282 
283 struct spear_pingroup spear3xx_gpio0_pin3_pingroup = {
284 	.name = "gpio0_pin3_grp",
285 	.pins = gpio0_pin3_pins,
286 	.npins = ARRAY_SIZE(gpio0_pin3_pins),
287 	.modemuxs = gpio0_pin3_modemux,
288 	.nmodemuxs = ARRAY_SIZE(gpio0_pin3_modemux),
289 };
290 
291 /* gpio0_pin4_pins */
292 static const unsigned gpio0_pin4_pins[] = { 32 };
293 static struct spear_muxreg gpio0_pin4_muxreg[] = {
294 	{
295 		.reg = -1,
296 		.mask = PMX_GPIO_PIN4_MASK,
297 		.val = PMX_GPIO_PIN4_MASK,
298 	},
299 };
300 
301 static struct spear_modemux gpio0_pin4_modemux[] = {
302 	{
303 		.modes = ~0,
304 		.muxregs = gpio0_pin4_muxreg,
305 		.nmuxregs = ARRAY_SIZE(gpio0_pin4_muxreg),
306 	},
307 };
308 
309 struct spear_pingroup spear3xx_gpio0_pin4_pingroup = {
310 	.name = "gpio0_pin4_grp",
311 	.pins = gpio0_pin4_pins,
312 	.npins = ARRAY_SIZE(gpio0_pin4_pins),
313 	.modemuxs = gpio0_pin4_modemux,
314 	.nmodemuxs = ARRAY_SIZE(gpio0_pin4_modemux),
315 };
316 
317 /* gpio0_pin5_pins */
318 static const unsigned gpio0_pin5_pins[] = { 33 };
319 static struct spear_muxreg gpio0_pin5_muxreg[] = {
320 	{
321 		.reg = -1,
322 		.mask = PMX_GPIO_PIN5_MASK,
323 		.val = PMX_GPIO_PIN5_MASK,
324 	},
325 };
326 
327 static struct spear_modemux gpio0_pin5_modemux[] = {
328 	{
329 		.modes = ~0,
330 		.muxregs = gpio0_pin5_muxreg,
331 		.nmuxregs = ARRAY_SIZE(gpio0_pin5_muxreg),
332 	},
333 };
334 
335 struct spear_pingroup spear3xx_gpio0_pin5_pingroup = {
336 	.name = "gpio0_pin5_grp",
337 	.pins = gpio0_pin5_pins,
338 	.npins = ARRAY_SIZE(gpio0_pin5_pins),
339 	.modemuxs = gpio0_pin5_modemux,
340 	.nmodemuxs = ARRAY_SIZE(gpio0_pin5_modemux),
341 };
342 
343 static const char *const gpio0_grps[] = { "gpio0_pin0_grp", "gpio0_pin1_grp",
344 	"gpio0_pin2_grp", "gpio0_pin3_grp", "gpio0_pin4_grp", "gpio0_pin5_grp",
345 };
346 struct spear_function spear3xx_gpio0_function = {
347 	.name = "gpio0",
348 	.groups = gpio0_grps,
349 	.ngroups = ARRAY_SIZE(gpio0_grps),
350 };
351 
352 /* uart0_ext_pins */
353 static const unsigned uart0_ext_pins[] = { 37, 38, 39, 40, 41, 42 };
354 static struct spear_muxreg uart0_ext_muxreg[] = {
355 	{
356 		.reg = -1,
357 		.mask = PMX_UART0_MODEM_MASK,
358 		.val = PMX_UART0_MODEM_MASK,
359 	},
360 };
361 
362 static struct spear_modemux uart0_ext_modemux[] = {
363 	{
364 		.modes = ~0,
365 		.muxregs = uart0_ext_muxreg,
366 		.nmuxregs = ARRAY_SIZE(uart0_ext_muxreg),
367 	},
368 };
369 
370 struct spear_pingroup spear3xx_uart0_ext_pingroup = {
371 	.name = "uart0_ext_grp",
372 	.pins = uart0_ext_pins,
373 	.npins = ARRAY_SIZE(uart0_ext_pins),
374 	.modemuxs = uart0_ext_modemux,
375 	.nmodemuxs = ARRAY_SIZE(uart0_ext_modemux),
376 };
377 
378 static const char *const uart0_ext_grps[] = { "uart0_ext_grp" };
379 struct spear_function spear3xx_uart0_ext_function = {
380 	.name = "uart0_ext",
381 	.groups = uart0_ext_grps,
382 	.ngroups = ARRAY_SIZE(uart0_ext_grps),
383 };
384 
385 /* uart0_pins */
386 static const unsigned uart0_pins[] = { 2, 3 };
387 static struct spear_muxreg uart0_muxreg[] = {
388 	{
389 		.reg = -1,
390 		.mask = PMX_UART0_MASK,
391 		.val = PMX_UART0_MASK,
392 	},
393 };
394 
395 static struct spear_modemux uart0_modemux[] = {
396 	{
397 		.modes = ~0,
398 		.muxregs = uart0_muxreg,
399 		.nmuxregs = ARRAY_SIZE(uart0_muxreg),
400 	},
401 };
402 
403 struct spear_pingroup spear3xx_uart0_pingroup = {
404 	.name = "uart0_grp",
405 	.pins = uart0_pins,
406 	.npins = ARRAY_SIZE(uart0_pins),
407 	.modemuxs = uart0_modemux,
408 	.nmodemuxs = ARRAY_SIZE(uart0_modemux),
409 };
410 
411 static const char *const uart0_grps[] = { "uart0_grp" };
412 struct spear_function spear3xx_uart0_function = {
413 	.name = "uart0",
414 	.groups = uart0_grps,
415 	.ngroups = ARRAY_SIZE(uart0_grps),
416 };
417 
418 /* timer_0_1_pins */
419 static const unsigned timer_0_1_pins[] = { 43, 44, 47, 48 };
420 static struct spear_muxreg timer_0_1_muxreg[] = {
421 	{
422 		.reg = -1,
423 		.mask = PMX_TIMER_0_1_MASK,
424 		.val = PMX_TIMER_0_1_MASK,
425 	},
426 };
427 
428 static struct spear_modemux timer_0_1_modemux[] = {
429 	{
430 		.modes = ~0,
431 		.muxregs = timer_0_1_muxreg,
432 		.nmuxregs = ARRAY_SIZE(timer_0_1_muxreg),
433 	},
434 };
435 
436 struct spear_pingroup spear3xx_timer_0_1_pingroup = {
437 	.name = "timer_0_1_grp",
438 	.pins = timer_0_1_pins,
439 	.npins = ARRAY_SIZE(timer_0_1_pins),
440 	.modemuxs = timer_0_1_modemux,
441 	.nmodemuxs = ARRAY_SIZE(timer_0_1_modemux),
442 };
443 
444 static const char *const timer_0_1_grps[] = { "timer_0_1_grp" };
445 struct spear_function spear3xx_timer_0_1_function = {
446 	.name = "timer_0_1",
447 	.groups = timer_0_1_grps,
448 	.ngroups = ARRAY_SIZE(timer_0_1_grps),
449 };
450 
451 /* timer_2_3_pins */
452 static const unsigned timer_2_3_pins[] = { 45, 46, 49, 50 };
453 static struct spear_muxreg timer_2_3_muxreg[] = {
454 	{
455 		.reg = -1,
456 		.mask = PMX_TIMER_2_3_MASK,
457 		.val = PMX_TIMER_2_3_MASK,
458 	},
459 };
460 
461 static struct spear_modemux timer_2_3_modemux[] = {
462 	{
463 		.modes = ~0,
464 		.muxregs = timer_2_3_muxreg,
465 		.nmuxregs = ARRAY_SIZE(timer_2_3_muxreg),
466 	},
467 };
468 
469 struct spear_pingroup spear3xx_timer_2_3_pingroup = {
470 	.name = "timer_2_3_grp",
471 	.pins = timer_2_3_pins,
472 	.npins = ARRAY_SIZE(timer_2_3_pins),
473 	.modemuxs = timer_2_3_modemux,
474 	.nmodemuxs = ARRAY_SIZE(timer_2_3_modemux),
475 };
476 
477 static const char *const timer_2_3_grps[] = { "timer_2_3_grp" };
478 struct spear_function spear3xx_timer_2_3_function = {
479 	.name = "timer_2_3",
480 	.groups = timer_2_3_grps,
481 	.ngroups = ARRAY_SIZE(timer_2_3_grps),
482 };
483 
484 /* Define muxreg arrays */
485 DEFINE_MUXREG(firda_pins, 0, PMX_FIRDA_MASK, 0);
486 DEFINE_MUXREG(i2c_pins, 0, PMX_I2C_MASK, 0);
487 DEFINE_MUXREG(ssp_cs_pins, 0, PMX_SSP_CS_MASK, 0);
488 DEFINE_MUXREG(ssp_pins, 0, PMX_SSP_MASK, 0);
489 DEFINE_MUXREG(mii_pins, 0, PMX_MII_MASK, 0);
490 DEFINE_MUXREG(gpio0_pin0_pins, 0, PMX_GPIO_PIN0_MASK, 0);
491 DEFINE_MUXREG(gpio0_pin1_pins, 0, PMX_GPIO_PIN1_MASK, 0);
492 DEFINE_MUXREG(gpio0_pin2_pins, 0, PMX_GPIO_PIN2_MASK, 0);
493 DEFINE_MUXREG(gpio0_pin3_pins, 0, PMX_GPIO_PIN3_MASK, 0);
494 DEFINE_MUXREG(gpio0_pin4_pins, 0, PMX_GPIO_PIN4_MASK, 0);
495 DEFINE_MUXREG(gpio0_pin5_pins, 0, PMX_GPIO_PIN5_MASK, 0);
496 DEFINE_MUXREG(uart0_ext_pins, 0, PMX_UART0_MODEM_MASK, 0);
497 DEFINE_MUXREG(uart0_pins, 0, PMX_UART0_MASK, 0);
498 DEFINE_MUXREG(timer_0_1_pins, 0, PMX_TIMER_0_1_MASK, 0);
499 DEFINE_MUXREG(timer_2_3_pins, 0, PMX_TIMER_2_3_MASK, 0);
500 
501 static struct spear_gpio_pingroup spear3xx_gpio_pingroup[] = {
502 	GPIO_PINGROUP(firda_pins),
503 	GPIO_PINGROUP(i2c_pins),
504 	GPIO_PINGROUP(ssp_cs_pins),
505 	GPIO_PINGROUP(ssp_pins),
506 	GPIO_PINGROUP(mii_pins),
507 	GPIO_PINGROUP(gpio0_pin0_pins),
508 	GPIO_PINGROUP(gpio0_pin1_pins),
509 	GPIO_PINGROUP(gpio0_pin2_pins),
510 	GPIO_PINGROUP(gpio0_pin3_pins),
511 	GPIO_PINGROUP(gpio0_pin4_pins),
512 	GPIO_PINGROUP(gpio0_pin5_pins),
513 	GPIO_PINGROUP(uart0_ext_pins),
514 	GPIO_PINGROUP(uart0_pins),
515 	GPIO_PINGROUP(timer_0_1_pins),
516 	GPIO_PINGROUP(timer_2_3_pins),
517 };
518 
519 struct spear_pinctrl_machdata spear3xx_machdata = {
520 	.pins = spear3xx_pins,
521 	.npins = ARRAY_SIZE(spear3xx_pins),
522 	.gpio_pingroups = spear3xx_gpio_pingroup,
523 	.ngpio_pingroups = ARRAY_SIZE(spear3xx_gpio_pingroup),
524 };
525