1 /*
2  * Driver for the ST Microelectronics SPEAr1310 pinmux
3  *
4  * Copyright (C) 2012 ST Microelectronics
5  * Viresh Kumar <vireshk@kernel.org>
6  *
7  * This file is licensed under the terms of the GNU General Public
8  * License version 2. This program is licensed "as is" without any
9  * warranty of any kind, whether express or implied.
10  */
11 
12 #include <linux/err.h>
13 #include <linux/init.h>
14 #include <linux/mod_devicetable.h>
15 #include <linux/platform_device.h>
16 #include "pinctrl-spear.h"
17 
18 #define DRIVER_NAME "spear1310-pinmux"
19 
20 /* pins */
21 static const struct pinctrl_pin_desc spear1310_pins[] = {
22 	SPEAR_PIN_0_TO_101,
23 	SPEAR_PIN_102_TO_245,
24 };
25 
26 /* registers */
27 #define PERIP_CFG					0x3B0
28 	#define MCIF_SEL_SHIFT				5
29 	#define MCIF_SEL_SD				(0x1 << MCIF_SEL_SHIFT)
30 	#define MCIF_SEL_CF				(0x2 << MCIF_SEL_SHIFT)
31 	#define MCIF_SEL_XD				(0x3 << MCIF_SEL_SHIFT)
32 	#define MCIF_SEL_MASK				(0x3 << MCIF_SEL_SHIFT)
33 
34 #define PCIE_SATA_CFG					0x3A4
35 	#define PCIE_SATA2_SEL_PCIE			(0 << 31)
36 	#define PCIE_SATA1_SEL_PCIE			(0 << 30)
37 	#define PCIE_SATA0_SEL_PCIE			(0 << 29)
38 	#define PCIE_SATA2_SEL_SATA			(1 << 31)
39 	#define PCIE_SATA1_SEL_SATA			(1 << 30)
40 	#define PCIE_SATA0_SEL_SATA			(1 << 29)
41 	#define SATA2_CFG_TX_CLK_EN			(1 << 27)
42 	#define SATA2_CFG_RX_CLK_EN			(1 << 26)
43 	#define SATA2_CFG_POWERUP_RESET			(1 << 25)
44 	#define SATA2_CFG_PM_CLK_EN			(1 << 24)
45 	#define SATA1_CFG_TX_CLK_EN			(1 << 23)
46 	#define SATA1_CFG_RX_CLK_EN			(1 << 22)
47 	#define SATA1_CFG_POWERUP_RESET			(1 << 21)
48 	#define SATA1_CFG_PM_CLK_EN			(1 << 20)
49 	#define SATA0_CFG_TX_CLK_EN			(1 << 19)
50 	#define SATA0_CFG_RX_CLK_EN			(1 << 18)
51 	#define SATA0_CFG_POWERUP_RESET			(1 << 17)
52 	#define SATA0_CFG_PM_CLK_EN			(1 << 16)
53 	#define PCIE2_CFG_DEVICE_PRESENT		(1 << 11)
54 	#define PCIE2_CFG_POWERUP_RESET			(1 << 10)
55 	#define PCIE2_CFG_CORE_CLK_EN			(1 << 9)
56 	#define PCIE2_CFG_AUX_CLK_EN			(1 << 8)
57 	#define PCIE1_CFG_DEVICE_PRESENT		(1 << 7)
58 	#define PCIE1_CFG_POWERUP_RESET			(1 << 6)
59 	#define PCIE1_CFG_CORE_CLK_EN			(1 << 5)
60 	#define PCIE1_CFG_AUX_CLK_EN			(1 << 4)
61 	#define PCIE0_CFG_DEVICE_PRESENT		(1 << 3)
62 	#define PCIE0_CFG_POWERUP_RESET			(1 << 2)
63 	#define PCIE0_CFG_CORE_CLK_EN			(1 << 1)
64 	#define PCIE0_CFG_AUX_CLK_EN			(1 << 0)
65 
66 #define PAD_FUNCTION_EN_0				0x650
67 	#define PMX_UART0_MASK				(1 << 1)
68 	#define PMX_I2C0_MASK				(1 << 2)
69 	#define PMX_I2S0_MASK				(1 << 3)
70 	#define PMX_SSP0_MASK				(1 << 4)
71 	#define PMX_CLCD1_MASK				(1 << 5)
72 	#define PMX_EGPIO00_MASK			(1 << 6)
73 	#define PMX_EGPIO01_MASK			(1 << 7)
74 	#define PMX_EGPIO02_MASK			(1 << 8)
75 	#define PMX_EGPIO03_MASK			(1 << 9)
76 	#define PMX_EGPIO04_MASK			(1 << 10)
77 	#define PMX_EGPIO05_MASK			(1 << 11)
78 	#define PMX_EGPIO06_MASK			(1 << 12)
79 	#define PMX_EGPIO07_MASK			(1 << 13)
80 	#define PMX_EGPIO08_MASK			(1 << 14)
81 	#define PMX_EGPIO09_MASK			(1 << 15)
82 	#define PMX_SMI_MASK				(1 << 16)
83 	#define PMX_NAND8_MASK				(1 << 17)
84 	#define PMX_GMIICLK_MASK			(1 << 18)
85 	#define PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK	(1 << 19)
86 	#define PMX_RXCLK_RDV_TXEN_D03_MASK		(1 << 20)
87 	#define PMX_GMIID47_MASK			(1 << 21)
88 	#define PMX_MDC_MDIO_MASK			(1 << 22)
89 	#define PMX_MCI_DATA8_15_MASK			(1 << 23)
90 	#define PMX_NFAD23_MASK				(1 << 24)
91 	#define PMX_NFAD24_MASK				(1 << 25)
92 	#define PMX_NFAD25_MASK				(1 << 26)
93 	#define PMX_NFCE3_MASK				(1 << 27)
94 	#define PMX_NFWPRT3_MASK			(1 << 28)
95 	#define PMX_NFRSTPWDWN0_MASK			(1 << 29)
96 	#define PMX_NFRSTPWDWN1_MASK			(1 << 30)
97 	#define PMX_NFRSTPWDWN2_MASK			(1 << 31)
98 
99 #define PAD_FUNCTION_EN_1				0x654
100 	#define PMX_NFRSTPWDWN3_MASK			(1 << 0)
101 	#define PMX_SMINCS2_MASK			(1 << 1)
102 	#define PMX_SMINCS3_MASK			(1 << 2)
103 	#define PMX_CLCD2_MASK				(1 << 3)
104 	#define PMX_KBD_ROWCOL68_MASK			(1 << 4)
105 	#define PMX_EGPIO10_MASK			(1 << 5)
106 	#define PMX_EGPIO11_MASK			(1 << 6)
107 	#define PMX_EGPIO12_MASK			(1 << 7)
108 	#define PMX_EGPIO13_MASK			(1 << 8)
109 	#define PMX_EGPIO14_MASK			(1 << 9)
110 	#define PMX_EGPIO15_MASK			(1 << 10)
111 	#define PMX_UART0_MODEM_MASK			(1 << 11)
112 	#define PMX_GPT0_TMR0_MASK			(1 << 12)
113 	#define PMX_GPT0_TMR1_MASK			(1 << 13)
114 	#define PMX_GPT1_TMR0_MASK			(1 << 14)
115 	#define PMX_GPT1_TMR1_MASK			(1 << 15)
116 	#define PMX_I2S1_MASK				(1 << 16)
117 	#define PMX_KBD_ROWCOL25_MASK			(1 << 17)
118 	#define PMX_NFIO8_15_MASK			(1 << 18)
119 	#define PMX_KBD_COL1_MASK			(1 << 19)
120 	#define PMX_NFCE1_MASK				(1 << 20)
121 	#define PMX_KBD_COL0_MASK			(1 << 21)
122 	#define PMX_NFCE2_MASK				(1 << 22)
123 	#define PMX_KBD_ROW1_MASK			(1 << 23)
124 	#define PMX_NFWPRT1_MASK			(1 << 24)
125 	#define PMX_KBD_ROW0_MASK			(1 << 25)
126 	#define PMX_NFWPRT2_MASK			(1 << 26)
127 	#define PMX_MCIDATA0_MASK			(1 << 27)
128 	#define PMX_MCIDATA1_MASK			(1 << 28)
129 	#define PMX_MCIDATA2_MASK			(1 << 29)
130 	#define PMX_MCIDATA3_MASK			(1 << 30)
131 	#define PMX_MCIDATA4_MASK			(1 << 31)
132 
133 #define PAD_FUNCTION_EN_2				0x658
134 	#define PMX_MCIDATA5_MASK			(1 << 0)
135 	#define PMX_MCIDATA6_MASK			(1 << 1)
136 	#define PMX_MCIDATA7_MASK			(1 << 2)
137 	#define PMX_MCIDATA1SD_MASK			(1 << 3)
138 	#define PMX_MCIDATA2SD_MASK			(1 << 4)
139 	#define PMX_MCIDATA3SD_MASK			(1 << 5)
140 	#define PMX_MCIADDR0ALE_MASK			(1 << 6)
141 	#define PMX_MCIADDR1CLECLK_MASK			(1 << 7)
142 	#define PMX_MCIADDR2_MASK			(1 << 8)
143 	#define PMX_MCICECF_MASK			(1 << 9)
144 	#define PMX_MCICEXD_MASK			(1 << 10)
145 	#define PMX_MCICESDMMC_MASK			(1 << 11)
146 	#define PMX_MCICDCF1_MASK			(1 << 12)
147 	#define PMX_MCICDCF2_MASK			(1 << 13)
148 	#define PMX_MCICDXD_MASK			(1 << 14)
149 	#define PMX_MCICDSDMMC_MASK			(1 << 15)
150 	#define PMX_MCIDATADIR_MASK			(1 << 16)
151 	#define PMX_MCIDMARQWP_MASK			(1 << 17)
152 	#define PMX_MCIIORDRE_MASK			(1 << 18)
153 	#define PMX_MCIIOWRWE_MASK			(1 << 19)
154 	#define PMX_MCIRESETCF_MASK			(1 << 20)
155 	#define PMX_MCICS0CE_MASK			(1 << 21)
156 	#define PMX_MCICFINTR_MASK			(1 << 22)
157 	#define PMX_MCIIORDY_MASK			(1 << 23)
158 	#define PMX_MCICS1_MASK				(1 << 24)
159 	#define PMX_MCIDMAACK_MASK			(1 << 25)
160 	#define PMX_MCISDCMD_MASK			(1 << 26)
161 	#define PMX_MCILEDS_MASK			(1 << 27)
162 	#define PMX_TOUCH_XY_MASK			(1 << 28)
163 	#define PMX_SSP0_CS0_MASK			(1 << 29)
164 	#define PMX_SSP0_CS1_2_MASK			(1 << 30)
165 
166 #define PAD_DIRECTION_SEL_0				0x65C
167 #define PAD_DIRECTION_SEL_1				0x660
168 #define PAD_DIRECTION_SEL_2				0x664
169 
170 /* combined macros */
171 #define PMX_GMII_MASK		(PMX_GMIICLK_MASK |			\
172 				PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK |	\
173 				PMX_RXCLK_RDV_TXEN_D03_MASK |		\
174 				PMX_GMIID47_MASK | PMX_MDC_MDIO_MASK)
175 
176 #define PMX_EGPIO_0_GRP_MASK	(PMX_EGPIO00_MASK | PMX_EGPIO01_MASK |	\
177 				PMX_EGPIO02_MASK |			\
178 				PMX_EGPIO03_MASK | PMX_EGPIO04_MASK |	\
179 				PMX_EGPIO05_MASK | PMX_EGPIO06_MASK |	\
180 				PMX_EGPIO07_MASK | PMX_EGPIO08_MASK |	\
181 				PMX_EGPIO09_MASK)
182 #define PMX_EGPIO_1_GRP_MASK	(PMX_EGPIO10_MASK | PMX_EGPIO11_MASK |	\
183 				PMX_EGPIO12_MASK | PMX_EGPIO13_MASK |	\
184 				PMX_EGPIO14_MASK | PMX_EGPIO15_MASK)
185 
186 #define PMX_KEYBOARD_6X6_MASK	(PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \
187 				PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL0_MASK | \
188 				PMX_KBD_COL1_MASK)
189 
190 #define PMX_NAND8BIT_0_MASK	(PMX_NAND8_MASK | PMX_NFAD23_MASK |	\
191 				PMX_NFAD24_MASK | PMX_NFAD25_MASK |	\
192 				PMX_NFWPRT3_MASK | PMX_NFRSTPWDWN0_MASK | \
193 				PMX_NFRSTPWDWN1_MASK | PMX_NFRSTPWDWN2_MASK | \
194 				PMX_NFCE3_MASK)
195 #define PMX_NAND8BIT_1_MASK	PMX_NFRSTPWDWN3_MASK
196 
197 #define PMX_NAND16BIT_1_MASK	(PMX_KBD_ROWCOL25_MASK | PMX_NFIO8_15_MASK)
198 #define PMX_NAND_4CHIPS_MASK	(PMX_NFCE1_MASK | PMX_NFCE2_MASK |	\
199 				PMX_NFWPRT1_MASK | PMX_NFWPRT2_MASK |	\
200 				PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK |	\
201 				PMX_KBD_COL0_MASK | PMX_KBD_COL1_MASK)
202 
203 #define PMX_MCIFALL_1_MASK	0xF8000000
204 #define PMX_MCIFALL_2_MASK	0x0FFFFFFF
205 
206 #define PMX_PCI_REG1_MASK	(PMX_SMINCS2_MASK | PMX_SMINCS3_MASK |	\
207 				PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK | \
208 				PMX_EGPIO_1_GRP_MASK | PMX_GPT0_TMR0_MASK | \
209 				PMX_GPT0_TMR1_MASK | PMX_GPT1_TMR0_MASK | \
210 				PMX_GPT1_TMR1_MASK | PMX_I2S1_MASK |	\
211 				PMX_NFCE2_MASK)
212 #define PMX_PCI_REG2_MASK	(PMX_TOUCH_XY_MASK | PMX_SSP0_CS0_MASK | \
213 				PMX_SSP0_CS1_2_MASK)
214 
215 #define PMX_SMII_0_1_2_MASK	(PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK)
216 #define PMX_RGMII_REG0_MASK	(PMX_MCI_DATA8_15_MASK |		\
217 				PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK |	\
218 				PMX_GMIID47_MASK)
219 #define PMX_RGMII_REG1_MASK	(PMX_KBD_ROWCOL68_MASK | PMX_EGPIO_1_GRP_MASK |\
220 				PMX_KBD_ROW1_MASK | PMX_NFWPRT1_MASK |	\
221 				PMX_KBD_ROW0_MASK | PMX_NFWPRT2_MASK)
222 #define PMX_RGMII_REG2_MASK	(PMX_TOUCH_XY_MASK | PMX_SSP0_CS0_MASK | \
223 				PMX_SSP0_CS1_2_MASK)
224 
225 #define PCIE_CFG_VAL(x)		(PCIE_SATA##x##_SEL_PCIE |	\
226 				PCIE##x##_CFG_AUX_CLK_EN |	\
227 				PCIE##x##_CFG_CORE_CLK_EN |	\
228 				PCIE##x##_CFG_POWERUP_RESET |	\
229 				PCIE##x##_CFG_DEVICE_PRESENT)
230 #define SATA_CFG_VAL(x)		(PCIE_SATA##x##_SEL_SATA |	\
231 				SATA##x##_CFG_PM_CLK_EN |	\
232 				SATA##x##_CFG_POWERUP_RESET |	\
233 				SATA##x##_CFG_RX_CLK_EN |	\
234 				SATA##x##_CFG_TX_CLK_EN)
235 
236 /* Pad multiplexing for i2c0 device */
237 static const unsigned i2c0_pins[] = { 102, 103 };
238 static struct spear_muxreg i2c0_muxreg[] = {
239 	{
240 		.reg = PAD_FUNCTION_EN_0,
241 		.mask = PMX_I2C0_MASK,
242 		.val = PMX_I2C0_MASK,
243 	}, {
244 		.reg = PAD_DIRECTION_SEL_0,
245 		.mask = PMX_I2C0_MASK,
246 		.val = PMX_I2C0_MASK,
247 	},
248 };
249 
250 static struct spear_modemux i2c0_modemux[] = {
251 	{
252 		.muxregs = i2c0_muxreg,
253 		.nmuxregs = ARRAY_SIZE(i2c0_muxreg),
254 	},
255 };
256 
257 static struct spear_pingroup i2c0_pingroup = {
258 	.name = "i2c0_grp",
259 	.pins = i2c0_pins,
260 	.npins = ARRAY_SIZE(i2c0_pins),
261 	.modemuxs = i2c0_modemux,
262 	.nmodemuxs = ARRAY_SIZE(i2c0_modemux),
263 };
264 
265 static const char *const i2c0_grps[] = { "i2c0_grp" };
266 static struct spear_function i2c0_function = {
267 	.name = "i2c0",
268 	.groups = i2c0_grps,
269 	.ngroups = ARRAY_SIZE(i2c0_grps),
270 };
271 
272 /* Pad multiplexing for ssp0 device */
273 static const unsigned ssp0_pins[] = { 109, 110, 111, 112 };
274 static struct spear_muxreg ssp0_muxreg[] = {
275 	{
276 		.reg = PAD_FUNCTION_EN_0,
277 		.mask = PMX_SSP0_MASK,
278 		.val = PMX_SSP0_MASK,
279 	}, {
280 		.reg = PAD_DIRECTION_SEL_0,
281 		.mask = PMX_SSP0_MASK,
282 		.val = PMX_SSP0_MASK,
283 	},
284 };
285 
286 static struct spear_modemux ssp0_modemux[] = {
287 	{
288 		.muxregs = ssp0_muxreg,
289 		.nmuxregs = ARRAY_SIZE(ssp0_muxreg),
290 	},
291 };
292 
293 static struct spear_pingroup ssp0_pingroup = {
294 	.name = "ssp0_grp",
295 	.pins = ssp0_pins,
296 	.npins = ARRAY_SIZE(ssp0_pins),
297 	.modemuxs = ssp0_modemux,
298 	.nmodemuxs = ARRAY_SIZE(ssp0_modemux),
299 };
300 
301 /* Pad multiplexing for ssp0_cs0 device */
302 static const unsigned ssp0_cs0_pins[] = { 96 };
303 static struct spear_muxreg ssp0_cs0_muxreg[] = {
304 	{
305 		.reg = PAD_FUNCTION_EN_2,
306 		.mask = PMX_SSP0_CS0_MASK,
307 		.val = PMX_SSP0_CS0_MASK,
308 	}, {
309 		.reg = PAD_DIRECTION_SEL_2,
310 		.mask = PMX_SSP0_CS0_MASK,
311 		.val = PMX_SSP0_CS0_MASK,
312 	},
313 };
314 
315 static struct spear_modemux ssp0_cs0_modemux[] = {
316 	{
317 		.muxregs = ssp0_cs0_muxreg,
318 		.nmuxregs = ARRAY_SIZE(ssp0_cs0_muxreg),
319 	},
320 };
321 
322 static struct spear_pingroup ssp0_cs0_pingroup = {
323 	.name = "ssp0_cs0_grp",
324 	.pins = ssp0_cs0_pins,
325 	.npins = ARRAY_SIZE(ssp0_cs0_pins),
326 	.modemuxs = ssp0_cs0_modemux,
327 	.nmodemuxs = ARRAY_SIZE(ssp0_cs0_modemux),
328 };
329 
330 /* ssp0_cs1_2 device */
331 static const unsigned ssp0_cs1_2_pins[] = { 94, 95 };
332 static struct spear_muxreg ssp0_cs1_2_muxreg[] = {
333 	{
334 		.reg = PAD_FUNCTION_EN_2,
335 		.mask = PMX_SSP0_CS1_2_MASK,
336 		.val = PMX_SSP0_CS1_2_MASK,
337 	}, {
338 		.reg = PAD_DIRECTION_SEL_2,
339 		.mask = PMX_SSP0_CS1_2_MASK,
340 		.val = PMX_SSP0_CS1_2_MASK,
341 	},
342 };
343 
344 static struct spear_modemux ssp0_cs1_2_modemux[] = {
345 	{
346 		.muxregs = ssp0_cs1_2_muxreg,
347 		.nmuxregs = ARRAY_SIZE(ssp0_cs1_2_muxreg),
348 	},
349 };
350 
351 static struct spear_pingroup ssp0_cs1_2_pingroup = {
352 	.name = "ssp0_cs1_2_grp",
353 	.pins = ssp0_cs1_2_pins,
354 	.npins = ARRAY_SIZE(ssp0_cs1_2_pins),
355 	.modemuxs = ssp0_cs1_2_modemux,
356 	.nmodemuxs = ARRAY_SIZE(ssp0_cs1_2_modemux),
357 };
358 
359 static const char *const ssp0_grps[] = { "ssp0_grp", "ssp0_cs0_grp",
360 	"ssp0_cs1_2_grp" };
361 static struct spear_function ssp0_function = {
362 	.name = "ssp0",
363 	.groups = ssp0_grps,
364 	.ngroups = ARRAY_SIZE(ssp0_grps),
365 };
366 
367 /* Pad multiplexing for i2s0 device */
368 static const unsigned i2s0_pins[] = { 104, 105, 106, 107, 108 };
369 static struct spear_muxreg i2s0_muxreg[] = {
370 	{
371 		.reg = PAD_FUNCTION_EN_0,
372 		.mask = PMX_I2S0_MASK,
373 		.val = PMX_I2S0_MASK,
374 	}, {
375 		.reg = PAD_DIRECTION_SEL_0,
376 		.mask = PMX_I2S0_MASK,
377 		.val = PMX_I2S0_MASK,
378 	},
379 };
380 
381 static struct spear_modemux i2s0_modemux[] = {
382 	{
383 		.muxregs = i2s0_muxreg,
384 		.nmuxregs = ARRAY_SIZE(i2s0_muxreg),
385 	},
386 };
387 
388 static struct spear_pingroup i2s0_pingroup = {
389 	.name = "i2s0_grp",
390 	.pins = i2s0_pins,
391 	.npins = ARRAY_SIZE(i2s0_pins),
392 	.modemuxs = i2s0_modemux,
393 	.nmodemuxs = ARRAY_SIZE(i2s0_modemux),
394 };
395 
396 static const char *const i2s0_grps[] = { "i2s0_grp" };
397 static struct spear_function i2s0_function = {
398 	.name = "i2s0",
399 	.groups = i2s0_grps,
400 	.ngroups = ARRAY_SIZE(i2s0_grps),
401 };
402 
403 /* Pad multiplexing for i2s1 device */
404 static const unsigned i2s1_pins[] = { 0, 1, 2, 3 };
405 static struct spear_muxreg i2s1_muxreg[] = {
406 	{
407 		.reg = PAD_FUNCTION_EN_1,
408 		.mask = PMX_I2S1_MASK,
409 		.val = PMX_I2S1_MASK,
410 	}, {
411 		.reg = PAD_DIRECTION_SEL_1,
412 		.mask = PMX_I2S1_MASK,
413 		.val = PMX_I2S1_MASK,
414 	},
415 };
416 
417 static struct spear_modemux i2s1_modemux[] = {
418 	{
419 		.muxregs = i2s1_muxreg,
420 		.nmuxregs = ARRAY_SIZE(i2s1_muxreg),
421 	},
422 };
423 
424 static struct spear_pingroup i2s1_pingroup = {
425 	.name = "i2s1_grp",
426 	.pins = i2s1_pins,
427 	.npins = ARRAY_SIZE(i2s1_pins),
428 	.modemuxs = i2s1_modemux,
429 	.nmodemuxs = ARRAY_SIZE(i2s1_modemux),
430 };
431 
432 static const char *const i2s1_grps[] = { "i2s1_grp" };
433 static struct spear_function i2s1_function = {
434 	.name = "i2s1",
435 	.groups = i2s1_grps,
436 	.ngroups = ARRAY_SIZE(i2s1_grps),
437 };
438 
439 /* Pad multiplexing for clcd device */
440 static const unsigned clcd_pins[] = { 113, 114, 115, 116, 117, 118, 119, 120,
441 	121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134,
442 	135, 136, 137, 138, 139, 140, 141, 142 };
443 static struct spear_muxreg clcd_muxreg[] = {
444 	{
445 		.reg = PAD_FUNCTION_EN_0,
446 		.mask = PMX_CLCD1_MASK,
447 		.val = PMX_CLCD1_MASK,
448 	}, {
449 		.reg = PAD_DIRECTION_SEL_0,
450 		.mask = PMX_CLCD1_MASK,
451 		.val = PMX_CLCD1_MASK,
452 	},
453 };
454 
455 static struct spear_modemux clcd_modemux[] = {
456 	{
457 		.muxregs = clcd_muxreg,
458 		.nmuxregs = ARRAY_SIZE(clcd_muxreg),
459 	},
460 };
461 
462 static struct spear_pingroup clcd_pingroup = {
463 	.name = "clcd_grp",
464 	.pins = clcd_pins,
465 	.npins = ARRAY_SIZE(clcd_pins),
466 	.modemuxs = clcd_modemux,
467 	.nmodemuxs = ARRAY_SIZE(clcd_modemux),
468 };
469 
470 static const unsigned clcd_high_res_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37,
471 	38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53 };
472 static struct spear_muxreg clcd_high_res_muxreg[] = {
473 	{
474 		.reg = PAD_FUNCTION_EN_1,
475 		.mask = PMX_CLCD2_MASK,
476 		.val = PMX_CLCD2_MASK,
477 	}, {
478 		.reg = PAD_DIRECTION_SEL_1,
479 		.mask = PMX_CLCD2_MASK,
480 		.val = PMX_CLCD2_MASK,
481 	},
482 };
483 
484 static struct spear_modemux clcd_high_res_modemux[] = {
485 	{
486 		.muxregs = clcd_high_res_muxreg,
487 		.nmuxregs = ARRAY_SIZE(clcd_high_res_muxreg),
488 	},
489 };
490 
491 static struct spear_pingroup clcd_high_res_pingroup = {
492 	.name = "clcd_high_res_grp",
493 	.pins = clcd_high_res_pins,
494 	.npins = ARRAY_SIZE(clcd_high_res_pins),
495 	.modemuxs = clcd_high_res_modemux,
496 	.nmodemuxs = ARRAY_SIZE(clcd_high_res_modemux),
497 };
498 
499 static const char *const clcd_grps[] = { "clcd_grp", "clcd_high_res_grp" };
500 static struct spear_function clcd_function = {
501 	.name = "clcd",
502 	.groups = clcd_grps,
503 	.ngroups = ARRAY_SIZE(clcd_grps),
504 };
505 
506 static const unsigned arm_gpio_pins[] = { 18, 19, 20, 21, 22, 23, 143, 144, 145,
507 	146, 147, 148, 149, 150, 151, 152 };
508 static struct spear_muxreg arm_gpio_muxreg[] = {
509 	{
510 		.reg = PAD_FUNCTION_EN_0,
511 		.mask = PMX_EGPIO_0_GRP_MASK,
512 		.val = PMX_EGPIO_0_GRP_MASK,
513 	}, {
514 		.reg = PAD_FUNCTION_EN_1,
515 		.mask = PMX_EGPIO_1_GRP_MASK,
516 		.val = PMX_EGPIO_1_GRP_MASK,
517 	}, {
518 		.reg = PAD_DIRECTION_SEL_0,
519 		.mask = PMX_EGPIO_0_GRP_MASK,
520 		.val = PMX_EGPIO_0_GRP_MASK,
521 	}, {
522 		.reg = PAD_DIRECTION_SEL_1,
523 		.mask = PMX_EGPIO_1_GRP_MASK,
524 		.val = PMX_EGPIO_1_GRP_MASK,
525 	},
526 };
527 
528 static struct spear_modemux arm_gpio_modemux[] = {
529 	{
530 		.muxregs = arm_gpio_muxreg,
531 		.nmuxregs = ARRAY_SIZE(arm_gpio_muxreg),
532 	},
533 };
534 
535 static struct spear_pingroup arm_gpio_pingroup = {
536 	.name = "arm_gpio_grp",
537 	.pins = arm_gpio_pins,
538 	.npins = ARRAY_SIZE(arm_gpio_pins),
539 	.modemuxs = arm_gpio_modemux,
540 	.nmodemuxs = ARRAY_SIZE(arm_gpio_modemux),
541 };
542 
543 static const char *const arm_gpio_grps[] = { "arm_gpio_grp" };
544 static struct spear_function arm_gpio_function = {
545 	.name = "arm_gpio",
546 	.groups = arm_gpio_grps,
547 	.ngroups = ARRAY_SIZE(arm_gpio_grps),
548 };
549 
550 /* Pad multiplexing for smi 2 chips device */
551 static const unsigned smi_2_chips_pins[] = { 153, 154, 155, 156, 157 };
552 static struct spear_muxreg smi_2_chips_muxreg[] = {
553 	{
554 		.reg = PAD_FUNCTION_EN_0,
555 		.mask = PMX_SMI_MASK,
556 		.val = PMX_SMI_MASK,
557 	}, {
558 		.reg = PAD_DIRECTION_SEL_0,
559 		.mask = PMX_SMI_MASK,
560 		.val = PMX_SMI_MASK,
561 	},
562 };
563 
564 static struct spear_modemux smi_2_chips_modemux[] = {
565 	{
566 		.muxregs = smi_2_chips_muxreg,
567 		.nmuxregs = ARRAY_SIZE(smi_2_chips_muxreg),
568 	},
569 };
570 
571 static struct spear_pingroup smi_2_chips_pingroup = {
572 	.name = "smi_2_chips_grp",
573 	.pins = smi_2_chips_pins,
574 	.npins = ARRAY_SIZE(smi_2_chips_pins),
575 	.modemuxs = smi_2_chips_modemux,
576 	.nmodemuxs = ARRAY_SIZE(smi_2_chips_modemux),
577 };
578 
579 static const unsigned smi_4_chips_pins[] = { 54, 55 };
580 static struct spear_muxreg smi_4_chips_muxreg[] = {
581 	{
582 		.reg = PAD_FUNCTION_EN_0,
583 		.mask = PMX_SMI_MASK,
584 		.val = PMX_SMI_MASK,
585 	}, {
586 		.reg = PAD_FUNCTION_EN_1,
587 		.mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
588 		.val = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
589 	}, {
590 		.reg = PAD_DIRECTION_SEL_0,
591 		.mask = PMX_SMI_MASK,
592 		.val = PMX_SMI_MASK,
593 	}, {
594 		.reg = PAD_DIRECTION_SEL_1,
595 		.mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
596 		.val = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
597 	},
598 };
599 
600 static struct spear_modemux smi_4_chips_modemux[] = {
601 	{
602 		.muxregs = smi_4_chips_muxreg,
603 		.nmuxregs = ARRAY_SIZE(smi_4_chips_muxreg),
604 	},
605 };
606 
607 static struct spear_pingroup smi_4_chips_pingroup = {
608 	.name = "smi_4_chips_grp",
609 	.pins = smi_4_chips_pins,
610 	.npins = ARRAY_SIZE(smi_4_chips_pins),
611 	.modemuxs = smi_4_chips_modemux,
612 	.nmodemuxs = ARRAY_SIZE(smi_4_chips_modemux),
613 };
614 
615 static const char *const smi_grps[] = { "smi_2_chips_grp", "smi_4_chips_grp" };
616 static struct spear_function smi_function = {
617 	.name = "smi",
618 	.groups = smi_grps,
619 	.ngroups = ARRAY_SIZE(smi_grps),
620 };
621 
622 /* Pad multiplexing for gmii device */
623 static const unsigned gmii_pins[] = { 173, 174, 175, 176, 177, 178, 179, 180,
624 	181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194,
625 	195, 196, 197, 198, 199, 200 };
626 static struct spear_muxreg gmii_muxreg[] = {
627 	{
628 		.reg = PAD_FUNCTION_EN_0,
629 		.mask = PMX_GMII_MASK,
630 		.val = PMX_GMII_MASK,
631 	}, {
632 		.reg = PAD_DIRECTION_SEL_0,
633 		.mask = PMX_GMII_MASK,
634 		.val = PMX_GMII_MASK,
635 	},
636 };
637 
638 static struct spear_modemux gmii_modemux[] = {
639 	{
640 		.muxregs = gmii_muxreg,
641 		.nmuxregs = ARRAY_SIZE(gmii_muxreg),
642 	},
643 };
644 
645 static struct spear_pingroup gmii_pingroup = {
646 	.name = "gmii_grp",
647 	.pins = gmii_pins,
648 	.npins = ARRAY_SIZE(gmii_pins),
649 	.modemuxs = gmii_modemux,
650 	.nmodemuxs = ARRAY_SIZE(gmii_modemux),
651 };
652 
653 static const char *const gmii_grps[] = { "gmii_grp" };
654 static struct spear_function gmii_function = {
655 	.name = "gmii",
656 	.groups = gmii_grps,
657 	.ngroups = ARRAY_SIZE(gmii_grps),
658 };
659 
660 /* Pad multiplexing for rgmii device */
661 static const unsigned rgmii_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,
662 	28, 29, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 175,
663 	180, 181, 182, 183, 185, 188, 193, 194, 195, 196, 197, 198, 211, 212 };
664 static struct spear_muxreg rgmii_muxreg[] = {
665 	{
666 		.reg = PAD_FUNCTION_EN_0,
667 		.mask = PMX_RGMII_REG0_MASK,
668 		.val = 0,
669 	}, {
670 		.reg = PAD_FUNCTION_EN_1,
671 		.mask = PMX_RGMII_REG1_MASK,
672 		.val = 0,
673 	}, {
674 		.reg = PAD_FUNCTION_EN_2,
675 		.mask = PMX_RGMII_REG2_MASK,
676 		.val = 0,
677 	}, {
678 		.reg = PAD_DIRECTION_SEL_0,
679 		.mask = PMX_RGMII_REG0_MASK,
680 		.val = PMX_RGMII_REG0_MASK,
681 	}, {
682 		.reg = PAD_DIRECTION_SEL_1,
683 		.mask = PMX_RGMII_REG1_MASK,
684 		.val = PMX_RGMII_REG1_MASK,
685 	}, {
686 		.reg = PAD_DIRECTION_SEL_2,
687 		.mask = PMX_RGMII_REG2_MASK,
688 		.val = PMX_RGMII_REG2_MASK,
689 	},
690 };
691 
692 static struct spear_modemux rgmii_modemux[] = {
693 	{
694 		.muxregs = rgmii_muxreg,
695 		.nmuxregs = ARRAY_SIZE(rgmii_muxreg),
696 	},
697 };
698 
699 static struct spear_pingroup rgmii_pingroup = {
700 	.name = "rgmii_grp",
701 	.pins = rgmii_pins,
702 	.npins = ARRAY_SIZE(rgmii_pins),
703 	.modemuxs = rgmii_modemux,
704 	.nmodemuxs = ARRAY_SIZE(rgmii_modemux),
705 };
706 
707 static const char *const rgmii_grps[] = { "rgmii_grp" };
708 static struct spear_function rgmii_function = {
709 	.name = "rgmii",
710 	.groups = rgmii_grps,
711 	.ngroups = ARRAY_SIZE(rgmii_grps),
712 };
713 
714 /* Pad multiplexing for smii_0_1_2 device */
715 static const unsigned smii_0_1_2_pins[] = { 24, 25, 26, 27, 28, 29, 30, 31, 32,
716 	33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50,
717 	51, 52, 53, 54, 55 };
718 static struct spear_muxreg smii_0_1_2_muxreg[] = {
719 	{
720 		.reg = PAD_FUNCTION_EN_1,
721 		.mask = PMX_SMII_0_1_2_MASK,
722 		.val = 0,
723 	}, {
724 		.reg = PAD_DIRECTION_SEL_1,
725 		.mask = PMX_SMII_0_1_2_MASK,
726 		.val = PMX_SMII_0_1_2_MASK,
727 	},
728 };
729 
730 static struct spear_modemux smii_0_1_2_modemux[] = {
731 	{
732 		.muxregs = smii_0_1_2_muxreg,
733 		.nmuxregs = ARRAY_SIZE(smii_0_1_2_muxreg),
734 	},
735 };
736 
737 static struct spear_pingroup smii_0_1_2_pingroup = {
738 	.name = "smii_0_1_2_grp",
739 	.pins = smii_0_1_2_pins,
740 	.npins = ARRAY_SIZE(smii_0_1_2_pins),
741 	.modemuxs = smii_0_1_2_modemux,
742 	.nmodemuxs = ARRAY_SIZE(smii_0_1_2_modemux),
743 };
744 
745 static const char *const smii_0_1_2_grps[] = { "smii_0_1_2_grp" };
746 static struct spear_function smii_0_1_2_function = {
747 	.name = "smii_0_1_2",
748 	.groups = smii_0_1_2_grps,
749 	.ngroups = ARRAY_SIZE(smii_0_1_2_grps),
750 };
751 
752 /* Pad multiplexing for ras_mii_txclk device */
753 static const unsigned ras_mii_txclk_pins[] = { 98, 99 };
754 static struct spear_muxreg ras_mii_txclk_muxreg[] = {
755 	{
756 		.reg = PAD_FUNCTION_EN_1,
757 		.mask = PMX_NFCE2_MASK,
758 		.val = 0,
759 	}, {
760 		.reg = PAD_DIRECTION_SEL_1,
761 		.mask = PMX_NFCE2_MASK,
762 		.val = PMX_NFCE2_MASK,
763 	},
764 };
765 
766 static struct spear_modemux ras_mii_txclk_modemux[] = {
767 	{
768 		.muxregs = ras_mii_txclk_muxreg,
769 		.nmuxregs = ARRAY_SIZE(ras_mii_txclk_muxreg),
770 	},
771 };
772 
773 static struct spear_pingroup ras_mii_txclk_pingroup = {
774 	.name = "ras_mii_txclk_grp",
775 	.pins = ras_mii_txclk_pins,
776 	.npins = ARRAY_SIZE(ras_mii_txclk_pins),
777 	.modemuxs = ras_mii_txclk_modemux,
778 	.nmodemuxs = ARRAY_SIZE(ras_mii_txclk_modemux),
779 };
780 
781 static const char *const ras_mii_txclk_grps[] = { "ras_mii_txclk_grp" };
782 static struct spear_function ras_mii_txclk_function = {
783 	.name = "ras_mii_txclk",
784 	.groups = ras_mii_txclk_grps,
785 	.ngroups = ARRAY_SIZE(ras_mii_txclk_grps),
786 };
787 
788 /* Pad multiplexing for nand 8bit device (cs0 only) */
789 static const unsigned nand_8bit_pins[] = { 56, 57, 58, 59, 60, 61, 62, 63, 64,
790 	65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82,
791 	83, 84, 85, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169,
792 	170, 171, 172, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211,
793 	212 };
794 static struct spear_muxreg nand_8bit_muxreg[] = {
795 	{
796 		.reg = PAD_FUNCTION_EN_0,
797 		.mask = PMX_NAND8BIT_0_MASK,
798 		.val = PMX_NAND8BIT_0_MASK,
799 	}, {
800 		.reg = PAD_FUNCTION_EN_1,
801 		.mask = PMX_NAND8BIT_1_MASK,
802 		.val = PMX_NAND8BIT_1_MASK,
803 	}, {
804 		.reg = PAD_DIRECTION_SEL_0,
805 		.mask = PMX_NAND8BIT_0_MASK,
806 		.val = PMX_NAND8BIT_0_MASK,
807 	}, {
808 		.reg = PAD_DIRECTION_SEL_1,
809 		.mask = PMX_NAND8BIT_1_MASK,
810 		.val = PMX_NAND8BIT_1_MASK,
811 	},
812 };
813 
814 static struct spear_modemux nand_8bit_modemux[] = {
815 	{
816 		.muxregs = nand_8bit_muxreg,
817 		.nmuxregs = ARRAY_SIZE(nand_8bit_muxreg),
818 	},
819 };
820 
821 static struct spear_pingroup nand_8bit_pingroup = {
822 	.name = "nand_8bit_grp",
823 	.pins = nand_8bit_pins,
824 	.npins = ARRAY_SIZE(nand_8bit_pins),
825 	.modemuxs = nand_8bit_modemux,
826 	.nmodemuxs = ARRAY_SIZE(nand_8bit_modemux),
827 };
828 
829 /* Pad multiplexing for nand 16bit device */
830 static const unsigned nand_16bit_pins[] = { 201, 202, 203, 204, 207, 208, 209,
831 	210 };
832 static struct spear_muxreg nand_16bit_muxreg[] = {
833 	{
834 		.reg = PAD_FUNCTION_EN_1,
835 		.mask = PMX_NAND16BIT_1_MASK,
836 		.val = PMX_NAND16BIT_1_MASK,
837 	}, {
838 		.reg = PAD_DIRECTION_SEL_1,
839 		.mask = PMX_NAND16BIT_1_MASK,
840 		.val = PMX_NAND16BIT_1_MASK,
841 	},
842 };
843 
844 static struct spear_modemux nand_16bit_modemux[] = {
845 	{
846 		.muxregs = nand_16bit_muxreg,
847 		.nmuxregs = ARRAY_SIZE(nand_16bit_muxreg),
848 	},
849 };
850 
851 static struct spear_pingroup nand_16bit_pingroup = {
852 	.name = "nand_16bit_grp",
853 	.pins = nand_16bit_pins,
854 	.npins = ARRAY_SIZE(nand_16bit_pins),
855 	.modemuxs = nand_16bit_modemux,
856 	.nmodemuxs = ARRAY_SIZE(nand_16bit_modemux),
857 };
858 
859 /* Pad multiplexing for nand 4 chips */
860 static const unsigned nand_4_chips_pins[] = { 205, 206, 211, 212 };
861 static struct spear_muxreg nand_4_chips_muxreg[] = {
862 	{
863 		.reg = PAD_FUNCTION_EN_1,
864 		.mask = PMX_NAND_4CHIPS_MASK,
865 		.val = PMX_NAND_4CHIPS_MASK,
866 	}, {
867 		.reg = PAD_DIRECTION_SEL_1,
868 		.mask = PMX_NAND_4CHIPS_MASK,
869 		.val = PMX_NAND_4CHIPS_MASK,
870 	},
871 };
872 
873 static struct spear_modemux nand_4_chips_modemux[] = {
874 	{
875 		.muxregs = nand_4_chips_muxreg,
876 		.nmuxregs = ARRAY_SIZE(nand_4_chips_muxreg),
877 	},
878 };
879 
880 static struct spear_pingroup nand_4_chips_pingroup = {
881 	.name = "nand_4_chips_grp",
882 	.pins = nand_4_chips_pins,
883 	.npins = ARRAY_SIZE(nand_4_chips_pins),
884 	.modemuxs = nand_4_chips_modemux,
885 	.nmodemuxs = ARRAY_SIZE(nand_4_chips_modemux),
886 };
887 
888 static const char *const nand_grps[] = { "nand_8bit_grp", "nand_16bit_grp",
889 	"nand_4_chips_grp" };
890 static struct spear_function nand_function = {
891 	.name = "nand",
892 	.groups = nand_grps,
893 	.ngroups = ARRAY_SIZE(nand_grps),
894 };
895 
896 /* Pad multiplexing for keyboard_6x6 device */
897 static const unsigned keyboard_6x6_pins[] = { 201, 202, 203, 204, 205, 206, 207,
898 	208, 209, 210, 211, 212 };
899 static struct spear_muxreg keyboard_6x6_muxreg[] = {
900 	{
901 		.reg = PAD_FUNCTION_EN_1,
902 		.mask = PMX_KEYBOARD_6X6_MASK | PMX_NFIO8_15_MASK |
903 			PMX_NFCE1_MASK | PMX_NFCE2_MASK | PMX_NFWPRT1_MASK |
904 			PMX_NFWPRT2_MASK,
905 		.val = PMX_KEYBOARD_6X6_MASK,
906 	},
907 };
908 
909 static struct spear_modemux keyboard_6x6_modemux[] = {
910 	{
911 		.muxregs = keyboard_6x6_muxreg,
912 		.nmuxregs = ARRAY_SIZE(keyboard_6x6_muxreg),
913 	},
914 };
915 
916 static struct spear_pingroup keyboard_6x6_pingroup = {
917 	.name = "keyboard_6x6_grp",
918 	.pins = keyboard_6x6_pins,
919 	.npins = ARRAY_SIZE(keyboard_6x6_pins),
920 	.modemuxs = keyboard_6x6_modemux,
921 	.nmodemuxs = ARRAY_SIZE(keyboard_6x6_modemux),
922 };
923 
924 /* Pad multiplexing for keyboard_rowcol6_8 device */
925 static const unsigned keyboard_rowcol6_8_pins[] = { 24, 25, 26, 27, 28, 29 };
926 static struct spear_muxreg keyboard_rowcol6_8_muxreg[] = {
927 	{
928 		.reg = PAD_FUNCTION_EN_1,
929 		.mask = PMX_KBD_ROWCOL68_MASK,
930 		.val = PMX_KBD_ROWCOL68_MASK,
931 	}, {
932 		.reg = PAD_DIRECTION_SEL_1,
933 		.mask = PMX_KBD_ROWCOL68_MASK,
934 		.val = PMX_KBD_ROWCOL68_MASK,
935 	},
936 };
937 
938 static struct spear_modemux keyboard_rowcol6_8_modemux[] = {
939 	{
940 		.muxregs = keyboard_rowcol6_8_muxreg,
941 		.nmuxregs = ARRAY_SIZE(keyboard_rowcol6_8_muxreg),
942 	},
943 };
944 
945 static struct spear_pingroup keyboard_rowcol6_8_pingroup = {
946 	.name = "keyboard_rowcol6_8_grp",
947 	.pins = keyboard_rowcol6_8_pins,
948 	.npins = ARRAY_SIZE(keyboard_rowcol6_8_pins),
949 	.modemuxs = keyboard_rowcol6_8_modemux,
950 	.nmodemuxs = ARRAY_SIZE(keyboard_rowcol6_8_modemux),
951 };
952 
953 static const char *const keyboard_grps[] = { "keyboard_6x6_grp",
954 	"keyboard_rowcol6_8_grp" };
955 static struct spear_function keyboard_function = {
956 	.name = "keyboard",
957 	.groups = keyboard_grps,
958 	.ngroups = ARRAY_SIZE(keyboard_grps),
959 };
960 
961 /* Pad multiplexing for uart0 device */
962 static const unsigned uart0_pins[] = { 100, 101 };
963 static struct spear_muxreg uart0_muxreg[] = {
964 	{
965 		.reg = PAD_FUNCTION_EN_0,
966 		.mask = PMX_UART0_MASK,
967 		.val = PMX_UART0_MASK,
968 	}, {
969 		.reg = PAD_DIRECTION_SEL_0,
970 		.mask = PMX_UART0_MASK,
971 		.val = PMX_UART0_MASK,
972 	},
973 };
974 
975 static struct spear_modemux uart0_modemux[] = {
976 	{
977 		.muxregs = uart0_muxreg,
978 		.nmuxregs = ARRAY_SIZE(uart0_muxreg),
979 	},
980 };
981 
982 static struct spear_pingroup uart0_pingroup = {
983 	.name = "uart0_grp",
984 	.pins = uart0_pins,
985 	.npins = ARRAY_SIZE(uart0_pins),
986 	.modemuxs = uart0_modemux,
987 	.nmodemuxs = ARRAY_SIZE(uart0_modemux),
988 };
989 
990 /* Pad multiplexing for uart0_modem device */
991 static const unsigned uart0_modem_pins[] = { 12, 13, 14, 15, 16, 17 };
992 static struct spear_muxreg uart0_modem_muxreg[] = {
993 	{
994 		.reg = PAD_FUNCTION_EN_1,
995 		.mask = PMX_UART0_MODEM_MASK,
996 		.val = PMX_UART0_MODEM_MASK,
997 	}, {
998 		.reg = PAD_DIRECTION_SEL_1,
999 		.mask = PMX_UART0_MODEM_MASK,
1000 		.val = PMX_UART0_MODEM_MASK,
1001 	},
1002 };
1003 
1004 static struct spear_modemux uart0_modem_modemux[] = {
1005 	{
1006 		.muxregs = uart0_modem_muxreg,
1007 		.nmuxregs = ARRAY_SIZE(uart0_modem_muxreg),
1008 	},
1009 };
1010 
1011 static struct spear_pingroup uart0_modem_pingroup = {
1012 	.name = "uart0_modem_grp",
1013 	.pins = uart0_modem_pins,
1014 	.npins = ARRAY_SIZE(uart0_modem_pins),
1015 	.modemuxs = uart0_modem_modemux,
1016 	.nmodemuxs = ARRAY_SIZE(uart0_modem_modemux),
1017 };
1018 
1019 static const char *const uart0_grps[] = { "uart0_grp", "uart0_modem_grp" };
1020 static struct spear_function uart0_function = {
1021 	.name = "uart0",
1022 	.groups = uart0_grps,
1023 	.ngroups = ARRAY_SIZE(uart0_grps),
1024 };
1025 
1026 /* Pad multiplexing for gpt0_tmr0 device */
1027 static const unsigned gpt0_tmr0_pins[] = { 10, 11 };
1028 static struct spear_muxreg gpt0_tmr0_muxreg[] = {
1029 	{
1030 		.reg = PAD_FUNCTION_EN_1,
1031 		.mask = PMX_GPT0_TMR0_MASK,
1032 		.val = PMX_GPT0_TMR0_MASK,
1033 	}, {
1034 		.reg = PAD_DIRECTION_SEL_1,
1035 		.mask = PMX_GPT0_TMR0_MASK,
1036 		.val = PMX_GPT0_TMR0_MASK,
1037 	},
1038 };
1039 
1040 static struct spear_modemux gpt0_tmr0_modemux[] = {
1041 	{
1042 		.muxregs = gpt0_tmr0_muxreg,
1043 		.nmuxregs = ARRAY_SIZE(gpt0_tmr0_muxreg),
1044 	},
1045 };
1046 
1047 static struct spear_pingroup gpt0_tmr0_pingroup = {
1048 	.name = "gpt0_tmr0_grp",
1049 	.pins = gpt0_tmr0_pins,
1050 	.npins = ARRAY_SIZE(gpt0_tmr0_pins),
1051 	.modemuxs = gpt0_tmr0_modemux,
1052 	.nmodemuxs = ARRAY_SIZE(gpt0_tmr0_modemux),
1053 };
1054 
1055 /* Pad multiplexing for gpt0_tmr1 device */
1056 static const unsigned gpt0_tmr1_pins[] = { 8, 9 };
1057 static struct spear_muxreg gpt0_tmr1_muxreg[] = {
1058 	{
1059 		.reg = PAD_FUNCTION_EN_1,
1060 		.mask = PMX_GPT0_TMR1_MASK,
1061 		.val = PMX_GPT0_TMR1_MASK,
1062 	}, {
1063 		.reg = PAD_DIRECTION_SEL_1,
1064 		.mask = PMX_GPT0_TMR1_MASK,
1065 		.val = PMX_GPT0_TMR1_MASK,
1066 	},
1067 };
1068 
1069 static struct spear_modemux gpt0_tmr1_modemux[] = {
1070 	{
1071 		.muxregs = gpt0_tmr1_muxreg,
1072 		.nmuxregs = ARRAY_SIZE(gpt0_tmr1_muxreg),
1073 	},
1074 };
1075 
1076 static struct spear_pingroup gpt0_tmr1_pingroup = {
1077 	.name = "gpt0_tmr1_grp",
1078 	.pins = gpt0_tmr1_pins,
1079 	.npins = ARRAY_SIZE(gpt0_tmr1_pins),
1080 	.modemuxs = gpt0_tmr1_modemux,
1081 	.nmodemuxs = ARRAY_SIZE(gpt0_tmr1_modemux),
1082 };
1083 
1084 static const char *const gpt0_grps[] = { "gpt0_tmr0_grp", "gpt0_tmr1_grp" };
1085 static struct spear_function gpt0_function = {
1086 	.name = "gpt0",
1087 	.groups = gpt0_grps,
1088 	.ngroups = ARRAY_SIZE(gpt0_grps),
1089 };
1090 
1091 /* Pad multiplexing for gpt1_tmr0 device */
1092 static const unsigned gpt1_tmr0_pins[] = { 6, 7 };
1093 static struct spear_muxreg gpt1_tmr0_muxreg[] = {
1094 	{
1095 		.reg = PAD_FUNCTION_EN_1,
1096 		.mask = PMX_GPT1_TMR0_MASK,
1097 		.val = PMX_GPT1_TMR0_MASK,
1098 	}, {
1099 		.reg = PAD_DIRECTION_SEL_1,
1100 		.mask = PMX_GPT1_TMR0_MASK,
1101 		.val = PMX_GPT1_TMR0_MASK,
1102 	},
1103 };
1104 
1105 static struct spear_modemux gpt1_tmr0_modemux[] = {
1106 	{
1107 		.muxregs = gpt1_tmr0_muxreg,
1108 		.nmuxregs = ARRAY_SIZE(gpt1_tmr0_muxreg),
1109 	},
1110 };
1111 
1112 static struct spear_pingroup gpt1_tmr0_pingroup = {
1113 	.name = "gpt1_tmr0_grp",
1114 	.pins = gpt1_tmr0_pins,
1115 	.npins = ARRAY_SIZE(gpt1_tmr0_pins),
1116 	.modemuxs = gpt1_tmr0_modemux,
1117 	.nmodemuxs = ARRAY_SIZE(gpt1_tmr0_modemux),
1118 };
1119 
1120 /* Pad multiplexing for gpt1_tmr1 device */
1121 static const unsigned gpt1_tmr1_pins[] = { 4, 5 };
1122 static struct spear_muxreg gpt1_tmr1_muxreg[] = {
1123 	{
1124 		.reg = PAD_FUNCTION_EN_1,
1125 		.mask = PMX_GPT1_TMR1_MASK,
1126 		.val = PMX_GPT1_TMR1_MASK,
1127 	}, {
1128 		.reg = PAD_DIRECTION_SEL_1,
1129 		.mask = PMX_GPT1_TMR1_MASK,
1130 		.val = PMX_GPT1_TMR1_MASK,
1131 	},
1132 };
1133 
1134 static struct spear_modemux gpt1_tmr1_modemux[] = {
1135 	{
1136 		.muxregs = gpt1_tmr1_muxreg,
1137 		.nmuxregs = ARRAY_SIZE(gpt1_tmr1_muxreg),
1138 	},
1139 };
1140 
1141 static struct spear_pingroup gpt1_tmr1_pingroup = {
1142 	.name = "gpt1_tmr1_grp",
1143 	.pins = gpt1_tmr1_pins,
1144 	.npins = ARRAY_SIZE(gpt1_tmr1_pins),
1145 	.modemuxs = gpt1_tmr1_modemux,
1146 	.nmodemuxs = ARRAY_SIZE(gpt1_tmr1_modemux),
1147 };
1148 
1149 static const char *const gpt1_grps[] = { "gpt1_tmr1_grp", "gpt1_tmr0_grp" };
1150 static struct spear_function gpt1_function = {
1151 	.name = "gpt1",
1152 	.groups = gpt1_grps,
1153 	.ngroups = ARRAY_SIZE(gpt1_grps),
1154 };
1155 
1156 /* Pad multiplexing for mcif device */
1157 static const unsigned mcif_pins[] = { 86, 87, 88, 89, 90, 91, 92, 93, 213, 214,
1158 	215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228,
1159 	229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242,
1160 	243, 244, 245 };
1161 #define MCIF_MUXREG						\
1162 	{							\
1163 		.reg = PAD_FUNCTION_EN_0,			\
1164 		.mask = PMX_MCI_DATA8_15_MASK,			\
1165 		.val = PMX_MCI_DATA8_15_MASK,			\
1166 	}, {							\
1167 		.reg = PAD_FUNCTION_EN_1,			\
1168 		.mask = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK |	\
1169 			PMX_NFWPRT2_MASK,			\
1170 		.val = PMX_MCIFALL_1_MASK,			\
1171 	}, {							\
1172 		.reg = PAD_FUNCTION_EN_2,			\
1173 		.mask = PMX_MCIFALL_2_MASK,			\
1174 		.val = PMX_MCIFALL_2_MASK,			\
1175 	}, {							\
1176 		.reg = PAD_DIRECTION_SEL_0,			\
1177 		.mask = PMX_MCI_DATA8_15_MASK,			\
1178 		.val = PMX_MCI_DATA8_15_MASK,			\
1179 	}, {							\
1180 		.reg = PAD_DIRECTION_SEL_1,			\
1181 		.mask = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK |	\
1182 			PMX_NFWPRT2_MASK,			\
1183 		.val = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK |  \
1184 			PMX_NFWPRT2_MASK,			\
1185 	}, {							\
1186 		.reg = PAD_DIRECTION_SEL_2,			\
1187 		.mask = PMX_MCIFALL_2_MASK,			\
1188 		.val = PMX_MCIFALL_2_MASK,			\
1189 	}
1190 
1191 /* sdhci device */
1192 static struct spear_muxreg sdhci_muxreg[] = {
1193 	MCIF_MUXREG,
1194 	{
1195 		.reg = PERIP_CFG,
1196 		.mask = MCIF_SEL_MASK,
1197 		.val = MCIF_SEL_SD,
1198 	},
1199 };
1200 
1201 static struct spear_modemux sdhci_modemux[] = {
1202 	{
1203 		.muxregs = sdhci_muxreg,
1204 		.nmuxregs = ARRAY_SIZE(sdhci_muxreg),
1205 	},
1206 };
1207 
1208 static struct spear_pingroup sdhci_pingroup = {
1209 	.name = "sdhci_grp",
1210 	.pins = mcif_pins,
1211 	.npins = ARRAY_SIZE(mcif_pins),
1212 	.modemuxs = sdhci_modemux,
1213 	.nmodemuxs = ARRAY_SIZE(sdhci_modemux),
1214 };
1215 
1216 static const char *const sdhci_grps[] = { "sdhci_grp" };
1217 static struct spear_function sdhci_function = {
1218 	.name = "sdhci",
1219 	.groups = sdhci_grps,
1220 	.ngroups = ARRAY_SIZE(sdhci_grps),
1221 };
1222 
1223 /* cf device */
1224 static struct spear_muxreg cf_muxreg[] = {
1225 	MCIF_MUXREG,
1226 	{
1227 		.reg = PERIP_CFG,
1228 		.mask = MCIF_SEL_MASK,
1229 		.val = MCIF_SEL_CF,
1230 	},
1231 };
1232 
1233 static struct spear_modemux cf_modemux[] = {
1234 	{
1235 		.muxregs = cf_muxreg,
1236 		.nmuxregs = ARRAY_SIZE(cf_muxreg),
1237 	},
1238 };
1239 
1240 static struct spear_pingroup cf_pingroup = {
1241 	.name = "cf_grp",
1242 	.pins = mcif_pins,
1243 	.npins = ARRAY_SIZE(mcif_pins),
1244 	.modemuxs = cf_modemux,
1245 	.nmodemuxs = ARRAY_SIZE(cf_modemux),
1246 };
1247 
1248 static const char *const cf_grps[] = { "cf_grp" };
1249 static struct spear_function cf_function = {
1250 	.name = "cf",
1251 	.groups = cf_grps,
1252 	.ngroups = ARRAY_SIZE(cf_grps),
1253 };
1254 
1255 /* xd device */
1256 static struct spear_muxreg xd_muxreg[] = {
1257 	MCIF_MUXREG,
1258 	{
1259 		.reg = PERIP_CFG,
1260 		.mask = MCIF_SEL_MASK,
1261 		.val = MCIF_SEL_XD,
1262 	},
1263 };
1264 
1265 static struct spear_modemux xd_modemux[] = {
1266 	{
1267 		.muxregs = xd_muxreg,
1268 		.nmuxregs = ARRAY_SIZE(xd_muxreg),
1269 	},
1270 };
1271 
1272 static struct spear_pingroup xd_pingroup = {
1273 	.name = "xd_grp",
1274 	.pins = mcif_pins,
1275 	.npins = ARRAY_SIZE(mcif_pins),
1276 	.modemuxs = xd_modemux,
1277 	.nmodemuxs = ARRAY_SIZE(xd_modemux),
1278 };
1279 
1280 static const char *const xd_grps[] = { "xd_grp" };
1281 static struct spear_function xd_function = {
1282 	.name = "xd",
1283 	.groups = xd_grps,
1284 	.ngroups = ARRAY_SIZE(xd_grps),
1285 };
1286 
1287 /* Pad multiplexing for touch_xy device */
1288 static const unsigned touch_xy_pins[] = { 97 };
1289 static struct spear_muxreg touch_xy_muxreg[] = {
1290 	{
1291 		.reg = PAD_FUNCTION_EN_2,
1292 		.mask = PMX_TOUCH_XY_MASK,
1293 		.val = PMX_TOUCH_XY_MASK,
1294 	}, {
1295 		.reg = PAD_DIRECTION_SEL_2,
1296 		.mask = PMX_TOUCH_XY_MASK,
1297 		.val = PMX_TOUCH_XY_MASK,
1298 	},
1299 };
1300 
1301 static struct spear_modemux touch_xy_modemux[] = {
1302 	{
1303 		.muxregs = touch_xy_muxreg,
1304 		.nmuxregs = ARRAY_SIZE(touch_xy_muxreg),
1305 	},
1306 };
1307 
1308 static struct spear_pingroup touch_xy_pingroup = {
1309 	.name = "touch_xy_grp",
1310 	.pins = touch_xy_pins,
1311 	.npins = ARRAY_SIZE(touch_xy_pins),
1312 	.modemuxs = touch_xy_modemux,
1313 	.nmodemuxs = ARRAY_SIZE(touch_xy_modemux),
1314 };
1315 
1316 static const char *const touch_xy_grps[] = { "touch_xy_grp" };
1317 static struct spear_function touch_xy_function = {
1318 	.name = "touchscreen",
1319 	.groups = touch_xy_grps,
1320 	.ngroups = ARRAY_SIZE(touch_xy_grps),
1321 };
1322 
1323 /* Pad multiplexing for uart1 device */
1324 /* Muxed with I2C */
1325 static const unsigned uart1_dis_i2c_pins[] = { 102, 103 };
1326 static struct spear_muxreg uart1_dis_i2c_muxreg[] = {
1327 	{
1328 		.reg = PAD_FUNCTION_EN_0,
1329 		.mask = PMX_I2C0_MASK,
1330 		.val = 0,
1331 	}, {
1332 		.reg = PAD_DIRECTION_SEL_0,
1333 		.mask = PMX_I2C0_MASK,
1334 		.val = PMX_I2C0_MASK,
1335 	},
1336 };
1337 
1338 static struct spear_modemux uart1_dis_i2c_modemux[] = {
1339 	{
1340 		.muxregs = uart1_dis_i2c_muxreg,
1341 		.nmuxregs = ARRAY_SIZE(uart1_dis_i2c_muxreg),
1342 	},
1343 };
1344 
1345 static struct spear_pingroup uart_1_dis_i2c_pingroup = {
1346 	.name = "uart1_disable_i2c_grp",
1347 	.pins = uart1_dis_i2c_pins,
1348 	.npins = ARRAY_SIZE(uart1_dis_i2c_pins),
1349 	.modemuxs = uart1_dis_i2c_modemux,
1350 	.nmodemuxs = ARRAY_SIZE(uart1_dis_i2c_modemux),
1351 };
1352 
1353 /* Muxed with SD/MMC */
1354 static const unsigned uart1_dis_sd_pins[] = { 214, 215 };
1355 static struct spear_muxreg uart1_dis_sd_muxreg[] = {
1356 	{
1357 		.reg = PAD_FUNCTION_EN_1,
1358 		.mask = PMX_MCIDATA1_MASK |
1359 			PMX_MCIDATA2_MASK,
1360 		.val = 0,
1361 	}, {
1362 		.reg = PAD_DIRECTION_SEL_1,
1363 		.mask = PMX_MCIDATA1_MASK |
1364 			PMX_MCIDATA2_MASK,
1365 		.val = PMX_MCIDATA1_MASK |
1366 			PMX_MCIDATA2_MASK,
1367 	},
1368 };
1369 
1370 static struct spear_modemux uart1_dis_sd_modemux[] = {
1371 	{
1372 		.muxregs = uart1_dis_sd_muxreg,
1373 		.nmuxregs = ARRAY_SIZE(uart1_dis_sd_muxreg),
1374 	},
1375 };
1376 
1377 static struct spear_pingroup uart_1_dis_sd_pingroup = {
1378 	.name = "uart1_disable_sd_grp",
1379 	.pins = uart1_dis_sd_pins,
1380 	.npins = ARRAY_SIZE(uart1_dis_sd_pins),
1381 	.modemuxs = uart1_dis_sd_modemux,
1382 	.nmodemuxs = ARRAY_SIZE(uart1_dis_sd_modemux),
1383 };
1384 
1385 static const char *const uart1_grps[] = { "uart1_disable_i2c_grp",
1386 	"uart1_disable_sd_grp" };
1387 static struct spear_function uart1_function = {
1388 	.name = "uart1",
1389 	.groups = uart1_grps,
1390 	.ngroups = ARRAY_SIZE(uart1_grps),
1391 };
1392 
1393 /* Pad multiplexing for uart2_3 device */
1394 static const unsigned uart2_3_pins[] = { 104, 105, 106, 107 };
1395 static struct spear_muxreg uart2_3_muxreg[] = {
1396 	{
1397 		.reg = PAD_FUNCTION_EN_0,
1398 		.mask = PMX_I2S0_MASK,
1399 		.val = 0,
1400 	}, {
1401 		.reg = PAD_DIRECTION_SEL_0,
1402 		.mask = PMX_I2S0_MASK,
1403 		.val = PMX_I2S0_MASK,
1404 	},
1405 };
1406 
1407 static struct spear_modemux uart2_3_modemux[] = {
1408 	{
1409 		.muxregs = uart2_3_muxreg,
1410 		.nmuxregs = ARRAY_SIZE(uart2_3_muxreg),
1411 	},
1412 };
1413 
1414 static struct spear_pingroup uart_2_3_pingroup = {
1415 	.name = "uart2_3_grp",
1416 	.pins = uart2_3_pins,
1417 	.npins = ARRAY_SIZE(uart2_3_pins),
1418 	.modemuxs = uart2_3_modemux,
1419 	.nmodemuxs = ARRAY_SIZE(uart2_3_modemux),
1420 };
1421 
1422 static const char *const uart2_3_grps[] = { "uart2_3_grp" };
1423 static struct spear_function uart2_3_function = {
1424 	.name = "uart2_3",
1425 	.groups = uart2_3_grps,
1426 	.ngroups = ARRAY_SIZE(uart2_3_grps),
1427 };
1428 
1429 /* Pad multiplexing for uart4 device */
1430 static const unsigned uart4_pins[] = { 108, 113 };
1431 static struct spear_muxreg uart4_muxreg[] = {
1432 	{
1433 		.reg = PAD_FUNCTION_EN_0,
1434 		.mask = PMX_I2S0_MASK | PMX_CLCD1_MASK,
1435 		.val = 0,
1436 	}, {
1437 		.reg = PAD_DIRECTION_SEL_0,
1438 		.mask = PMX_I2S0_MASK | PMX_CLCD1_MASK,
1439 		.val = PMX_I2S0_MASK | PMX_CLCD1_MASK,
1440 	},
1441 };
1442 
1443 static struct spear_modemux uart4_modemux[] = {
1444 	{
1445 		.muxregs = uart4_muxreg,
1446 		.nmuxregs = ARRAY_SIZE(uart4_muxreg),
1447 	},
1448 };
1449 
1450 static struct spear_pingroup uart_4_pingroup = {
1451 	.name = "uart4_grp",
1452 	.pins = uart4_pins,
1453 	.npins = ARRAY_SIZE(uart4_pins),
1454 	.modemuxs = uart4_modemux,
1455 	.nmodemuxs = ARRAY_SIZE(uart4_modemux),
1456 };
1457 
1458 static const char *const uart4_grps[] = { "uart4_grp" };
1459 static struct spear_function uart4_function = {
1460 	.name = "uart4",
1461 	.groups = uart4_grps,
1462 	.ngroups = ARRAY_SIZE(uart4_grps),
1463 };
1464 
1465 /* Pad multiplexing for uart5 device */
1466 static const unsigned uart5_pins[] = { 114, 115 };
1467 static struct spear_muxreg uart5_muxreg[] = {
1468 	{
1469 		.reg = PAD_FUNCTION_EN_0,
1470 		.mask = PMX_CLCD1_MASK,
1471 		.val = 0,
1472 	}, {
1473 		.reg = PAD_DIRECTION_SEL_0,
1474 		.mask = PMX_CLCD1_MASK,
1475 		.val = PMX_CLCD1_MASK,
1476 	},
1477 };
1478 
1479 static struct spear_modemux uart5_modemux[] = {
1480 	{
1481 		.muxregs = uart5_muxreg,
1482 		.nmuxregs = ARRAY_SIZE(uart5_muxreg),
1483 	},
1484 };
1485 
1486 static struct spear_pingroup uart_5_pingroup = {
1487 	.name = "uart5_grp",
1488 	.pins = uart5_pins,
1489 	.npins = ARRAY_SIZE(uart5_pins),
1490 	.modemuxs = uart5_modemux,
1491 	.nmodemuxs = ARRAY_SIZE(uart5_modemux),
1492 };
1493 
1494 static const char *const uart5_grps[] = { "uart5_grp" };
1495 static struct spear_function uart5_function = {
1496 	.name = "uart5",
1497 	.groups = uart5_grps,
1498 	.ngroups = ARRAY_SIZE(uart5_grps),
1499 };
1500 
1501 /* Pad multiplexing for rs485_0_1_tdm_0_1 device */
1502 static const unsigned rs485_0_1_tdm_0_1_pins[] = { 116, 117, 118, 119, 120, 121,
1503 	122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135,
1504 	136, 137 };
1505 static struct spear_muxreg rs485_0_1_tdm_0_1_muxreg[] = {
1506 	{
1507 		.reg = PAD_FUNCTION_EN_0,
1508 		.mask = PMX_CLCD1_MASK,
1509 		.val = 0,
1510 	}, {
1511 		.reg = PAD_DIRECTION_SEL_0,
1512 		.mask = PMX_CLCD1_MASK,
1513 		.val = PMX_CLCD1_MASK,
1514 	},
1515 };
1516 
1517 static struct spear_modemux rs485_0_1_tdm_0_1_modemux[] = {
1518 	{
1519 		.muxregs = rs485_0_1_tdm_0_1_muxreg,
1520 		.nmuxregs = ARRAY_SIZE(rs485_0_1_tdm_0_1_muxreg),
1521 	},
1522 };
1523 
1524 static struct spear_pingroup rs485_0_1_tdm_0_1_pingroup = {
1525 	.name = "rs485_0_1_tdm_0_1_grp",
1526 	.pins = rs485_0_1_tdm_0_1_pins,
1527 	.npins = ARRAY_SIZE(rs485_0_1_tdm_0_1_pins),
1528 	.modemuxs = rs485_0_1_tdm_0_1_modemux,
1529 	.nmodemuxs = ARRAY_SIZE(rs485_0_1_tdm_0_1_modemux),
1530 };
1531 
1532 static const char *const rs485_0_1_tdm_0_1_grps[] = { "rs485_0_1_tdm_0_1_grp" };
1533 static struct spear_function rs485_0_1_tdm_0_1_function = {
1534 	.name = "rs485_0_1_tdm_0_1",
1535 	.groups = rs485_0_1_tdm_0_1_grps,
1536 	.ngroups = ARRAY_SIZE(rs485_0_1_tdm_0_1_grps),
1537 };
1538 
1539 /* Pad multiplexing for i2c_1_2 device */
1540 static const unsigned i2c_1_2_pins[] = { 138, 139, 140, 141 };
1541 static struct spear_muxreg i2c_1_2_muxreg[] = {
1542 	{
1543 		.reg = PAD_FUNCTION_EN_0,
1544 		.mask = PMX_CLCD1_MASK,
1545 		.val = 0,
1546 	}, {
1547 		.reg = PAD_DIRECTION_SEL_0,
1548 		.mask = PMX_CLCD1_MASK,
1549 		.val = PMX_CLCD1_MASK,
1550 	},
1551 };
1552 
1553 static struct spear_modemux i2c_1_2_modemux[] = {
1554 	{
1555 		.muxregs = i2c_1_2_muxreg,
1556 		.nmuxregs = ARRAY_SIZE(i2c_1_2_muxreg),
1557 	},
1558 };
1559 
1560 static struct spear_pingroup i2c_1_2_pingroup = {
1561 	.name = "i2c_1_2_grp",
1562 	.pins = i2c_1_2_pins,
1563 	.npins = ARRAY_SIZE(i2c_1_2_pins),
1564 	.modemuxs = i2c_1_2_modemux,
1565 	.nmodemuxs = ARRAY_SIZE(i2c_1_2_modemux),
1566 };
1567 
1568 static const char *const i2c_1_2_grps[] = { "i2c_1_2_grp" };
1569 static struct spear_function i2c_1_2_function = {
1570 	.name = "i2c_1_2",
1571 	.groups = i2c_1_2_grps,
1572 	.ngroups = ARRAY_SIZE(i2c_1_2_grps),
1573 };
1574 
1575 /* Pad multiplexing for i2c3_dis_smi_clcd device */
1576 /* Muxed with SMI & CLCD */
1577 static const unsigned i2c3_dis_smi_clcd_pins[] = { 142, 153 };
1578 static struct spear_muxreg i2c3_dis_smi_clcd_muxreg[] = {
1579 	{
1580 		.reg = PAD_FUNCTION_EN_0,
1581 		.mask = PMX_CLCD1_MASK | PMX_SMI_MASK,
1582 		.val = 0,
1583 	}, {
1584 		.reg = PAD_DIRECTION_SEL_0,
1585 		.mask = PMX_CLCD1_MASK | PMX_SMI_MASK,
1586 		.val = PMX_CLCD1_MASK | PMX_SMI_MASK,
1587 	},
1588 };
1589 
1590 static struct spear_modemux i2c3_dis_smi_clcd_modemux[] = {
1591 	{
1592 		.muxregs = i2c3_dis_smi_clcd_muxreg,
1593 		.nmuxregs = ARRAY_SIZE(i2c3_dis_smi_clcd_muxreg),
1594 	},
1595 };
1596 
1597 static struct spear_pingroup i2c3_dis_smi_clcd_pingroup = {
1598 	.name = "i2c3_dis_smi_clcd_grp",
1599 	.pins = i2c3_dis_smi_clcd_pins,
1600 	.npins = ARRAY_SIZE(i2c3_dis_smi_clcd_pins),
1601 	.modemuxs = i2c3_dis_smi_clcd_modemux,
1602 	.nmodemuxs = ARRAY_SIZE(i2c3_dis_smi_clcd_modemux),
1603 };
1604 
1605 /* Pad multiplexing for i2c3_dis_sd_i2s0 device */
1606 /* Muxed with SD/MMC & I2S1 */
1607 static const unsigned i2c3_dis_sd_i2s0_pins[] = { 0, 216 };
1608 static struct spear_muxreg i2c3_dis_sd_i2s0_muxreg[] = {
1609 	{
1610 		.reg = PAD_FUNCTION_EN_1,
1611 		.mask = PMX_I2S1_MASK | PMX_MCIDATA3_MASK,
1612 		.val = 0,
1613 	}, {
1614 		.reg = PAD_DIRECTION_SEL_1,
1615 		.mask = PMX_I2S1_MASK | PMX_MCIDATA3_MASK,
1616 		.val = PMX_I2S1_MASK | PMX_MCIDATA3_MASK,
1617 	},
1618 };
1619 
1620 static struct spear_modemux i2c3_dis_sd_i2s0_modemux[] = {
1621 	{
1622 		.muxregs = i2c3_dis_sd_i2s0_muxreg,
1623 		.nmuxregs = ARRAY_SIZE(i2c3_dis_sd_i2s0_muxreg),
1624 	},
1625 };
1626 
1627 static struct spear_pingroup i2c3_dis_sd_i2s0_pingroup = {
1628 	.name = "i2c3_dis_sd_i2s0_grp",
1629 	.pins = i2c3_dis_sd_i2s0_pins,
1630 	.npins = ARRAY_SIZE(i2c3_dis_sd_i2s0_pins),
1631 	.modemuxs = i2c3_dis_sd_i2s0_modemux,
1632 	.nmodemuxs = ARRAY_SIZE(i2c3_dis_sd_i2s0_modemux),
1633 };
1634 
1635 static const char *const i2c3_grps[] = { "i2c3_dis_smi_clcd_grp",
1636 	"i2c3_dis_sd_i2s0_grp" };
1637 static struct spear_function i2c3_unction = {
1638 	.name = "i2c3_i2s1",
1639 	.groups = i2c3_grps,
1640 	.ngroups = ARRAY_SIZE(i2c3_grps),
1641 };
1642 
1643 /* Pad multiplexing for i2c_4_5_dis_smi device */
1644 /* Muxed with SMI */
1645 static const unsigned i2c_4_5_dis_smi_pins[] = { 154, 155, 156, 157 };
1646 static struct spear_muxreg i2c_4_5_dis_smi_muxreg[] = {
1647 	{
1648 		.reg = PAD_FUNCTION_EN_0,
1649 		.mask = PMX_SMI_MASK,
1650 		.val = 0,
1651 	}, {
1652 		.reg = PAD_DIRECTION_SEL_0,
1653 		.mask = PMX_SMI_MASK,
1654 		.val = PMX_SMI_MASK,
1655 	},
1656 };
1657 
1658 static struct spear_modemux i2c_4_5_dis_smi_modemux[] = {
1659 	{
1660 		.muxregs = i2c_4_5_dis_smi_muxreg,
1661 		.nmuxregs = ARRAY_SIZE(i2c_4_5_dis_smi_muxreg),
1662 	},
1663 };
1664 
1665 static struct spear_pingroup i2c_4_5_dis_smi_pingroup = {
1666 	.name = "i2c_4_5_dis_smi_grp",
1667 	.pins = i2c_4_5_dis_smi_pins,
1668 	.npins = ARRAY_SIZE(i2c_4_5_dis_smi_pins),
1669 	.modemuxs = i2c_4_5_dis_smi_modemux,
1670 	.nmodemuxs = ARRAY_SIZE(i2c_4_5_dis_smi_modemux),
1671 };
1672 
1673 /* Pad multiplexing for i2c4_dis_sd device */
1674 /* Muxed with SD/MMC */
1675 static const unsigned i2c4_dis_sd_pins[] = { 217, 218 };
1676 static struct spear_muxreg i2c4_dis_sd_muxreg[] = {
1677 	{
1678 		.reg = PAD_FUNCTION_EN_1,
1679 		.mask = PMX_MCIDATA4_MASK,
1680 		.val = 0,
1681 	}, {
1682 		.reg = PAD_FUNCTION_EN_2,
1683 		.mask = PMX_MCIDATA5_MASK,
1684 		.val = 0,
1685 	}, {
1686 		.reg = PAD_DIRECTION_SEL_1,
1687 		.mask = PMX_MCIDATA4_MASK,
1688 		.val = PMX_MCIDATA4_MASK,
1689 	}, {
1690 		.reg = PAD_DIRECTION_SEL_2,
1691 		.mask = PMX_MCIDATA5_MASK,
1692 		.val = PMX_MCIDATA5_MASK,
1693 	},
1694 };
1695 
1696 static struct spear_modemux i2c4_dis_sd_modemux[] = {
1697 	{
1698 		.muxregs = i2c4_dis_sd_muxreg,
1699 		.nmuxregs = ARRAY_SIZE(i2c4_dis_sd_muxreg),
1700 	},
1701 };
1702 
1703 static struct spear_pingroup i2c4_dis_sd_pingroup = {
1704 	.name = "i2c4_dis_sd_grp",
1705 	.pins = i2c4_dis_sd_pins,
1706 	.npins = ARRAY_SIZE(i2c4_dis_sd_pins),
1707 	.modemuxs = i2c4_dis_sd_modemux,
1708 	.nmodemuxs = ARRAY_SIZE(i2c4_dis_sd_modemux),
1709 };
1710 
1711 /* Pad multiplexing for i2c5_dis_sd device */
1712 /* Muxed with SD/MMC */
1713 static const unsigned i2c5_dis_sd_pins[] = { 219, 220 };
1714 static struct spear_muxreg i2c5_dis_sd_muxreg[] = {
1715 	{
1716 		.reg = PAD_FUNCTION_EN_2,
1717 		.mask = PMX_MCIDATA6_MASK |
1718 			PMX_MCIDATA7_MASK,
1719 		.val = 0,
1720 	}, {
1721 		.reg = PAD_DIRECTION_SEL_2,
1722 		.mask = PMX_MCIDATA6_MASK |
1723 			PMX_MCIDATA7_MASK,
1724 		.val = PMX_MCIDATA6_MASK |
1725 			PMX_MCIDATA7_MASK,
1726 	},
1727 };
1728 
1729 static struct spear_modemux i2c5_dis_sd_modemux[] = {
1730 	{
1731 		.muxregs = i2c5_dis_sd_muxreg,
1732 		.nmuxregs = ARRAY_SIZE(i2c5_dis_sd_muxreg),
1733 	},
1734 };
1735 
1736 static struct spear_pingroup i2c5_dis_sd_pingroup = {
1737 	.name = "i2c5_dis_sd_grp",
1738 	.pins = i2c5_dis_sd_pins,
1739 	.npins = ARRAY_SIZE(i2c5_dis_sd_pins),
1740 	.modemuxs = i2c5_dis_sd_modemux,
1741 	.nmodemuxs = ARRAY_SIZE(i2c5_dis_sd_modemux),
1742 };
1743 
1744 static const char *const i2c_4_5_grps[] = { "i2c5_dis_sd_grp",
1745 	"i2c4_dis_sd_grp", "i2c_4_5_dis_smi_grp" };
1746 static struct spear_function i2c_4_5_function = {
1747 	.name = "i2c_4_5",
1748 	.groups = i2c_4_5_grps,
1749 	.ngroups = ARRAY_SIZE(i2c_4_5_grps),
1750 };
1751 
1752 /* Pad multiplexing for i2c_6_7_dis_kbd device */
1753 /* Muxed with KBD */
1754 static const unsigned i2c_6_7_dis_kbd_pins[] = { 207, 208, 209, 210 };
1755 static struct spear_muxreg i2c_6_7_dis_kbd_muxreg[] = {
1756 	{
1757 		.reg = PAD_FUNCTION_EN_1,
1758 		.mask = PMX_KBD_ROWCOL25_MASK,
1759 		.val = 0,
1760 	}, {
1761 		.reg = PAD_DIRECTION_SEL_1,
1762 		.mask = PMX_KBD_ROWCOL25_MASK,
1763 		.val = PMX_KBD_ROWCOL25_MASK,
1764 	},
1765 };
1766 
1767 static struct spear_modemux i2c_6_7_dis_kbd_modemux[] = {
1768 	{
1769 		.muxregs = i2c_6_7_dis_kbd_muxreg,
1770 		.nmuxregs = ARRAY_SIZE(i2c_6_7_dis_kbd_muxreg),
1771 	},
1772 };
1773 
1774 static struct spear_pingroup i2c_6_7_dis_kbd_pingroup = {
1775 	.name = "i2c_6_7_dis_kbd_grp",
1776 	.pins = i2c_6_7_dis_kbd_pins,
1777 	.npins = ARRAY_SIZE(i2c_6_7_dis_kbd_pins),
1778 	.modemuxs = i2c_6_7_dis_kbd_modemux,
1779 	.nmodemuxs = ARRAY_SIZE(i2c_6_7_dis_kbd_modemux),
1780 };
1781 
1782 /* Pad multiplexing for i2c6_dis_sd device */
1783 /* Muxed with SD/MMC */
1784 static const unsigned i2c6_dis_sd_pins[] = { 236, 237 };
1785 static struct spear_muxreg i2c6_dis_sd_muxreg[] = {
1786 	{
1787 		.reg = PAD_FUNCTION_EN_2,
1788 		.mask = PMX_MCIIORDRE_MASK |
1789 			PMX_MCIIOWRWE_MASK,
1790 		.val = 0,
1791 	}, {
1792 		.reg = PAD_DIRECTION_SEL_2,
1793 		.mask = PMX_MCIIORDRE_MASK |
1794 			PMX_MCIIOWRWE_MASK,
1795 		.val = PMX_MCIIORDRE_MASK |
1796 			PMX_MCIIOWRWE_MASK,
1797 	},
1798 };
1799 
1800 static struct spear_modemux i2c6_dis_sd_modemux[] = {
1801 	{
1802 		.muxregs = i2c6_dis_sd_muxreg,
1803 		.nmuxregs = ARRAY_SIZE(i2c6_dis_sd_muxreg),
1804 	},
1805 };
1806 
1807 static struct spear_pingroup i2c6_dis_sd_pingroup = {
1808 	.name = "i2c6_dis_sd_grp",
1809 	.pins = i2c6_dis_sd_pins,
1810 	.npins = ARRAY_SIZE(i2c6_dis_sd_pins),
1811 	.modemuxs = i2c6_dis_sd_modemux,
1812 	.nmodemuxs = ARRAY_SIZE(i2c6_dis_sd_modemux),
1813 };
1814 
1815 /* Pad multiplexing for i2c7_dis_sd device */
1816 static const unsigned i2c7_dis_sd_pins[] = { 238, 239 };
1817 static struct spear_muxreg i2c7_dis_sd_muxreg[] = {
1818 	{
1819 		.reg = PAD_FUNCTION_EN_2,
1820 		.mask = PMX_MCIRESETCF_MASK |
1821 			PMX_MCICS0CE_MASK,
1822 		.val = 0,
1823 	}, {
1824 		.reg = PAD_DIRECTION_SEL_2,
1825 		.mask = PMX_MCIRESETCF_MASK |
1826 			PMX_MCICS0CE_MASK,
1827 		.val = PMX_MCIRESETCF_MASK |
1828 			PMX_MCICS0CE_MASK,
1829 	},
1830 };
1831 
1832 static struct spear_modemux i2c7_dis_sd_modemux[] = {
1833 	{
1834 		.muxregs = i2c7_dis_sd_muxreg,
1835 		.nmuxregs = ARRAY_SIZE(i2c7_dis_sd_muxreg),
1836 	},
1837 };
1838 
1839 static struct spear_pingroup i2c7_dis_sd_pingroup = {
1840 	.name = "i2c7_dis_sd_grp",
1841 	.pins = i2c7_dis_sd_pins,
1842 	.npins = ARRAY_SIZE(i2c7_dis_sd_pins),
1843 	.modemuxs = i2c7_dis_sd_modemux,
1844 	.nmodemuxs = ARRAY_SIZE(i2c7_dis_sd_modemux),
1845 };
1846 
1847 static const char *const i2c_6_7_grps[] = { "i2c6_dis_sd_grp",
1848 	"i2c7_dis_sd_grp", "i2c_6_7_dis_kbd_grp" };
1849 static struct spear_function i2c_6_7_function = {
1850 	.name = "i2c_6_7",
1851 	.groups = i2c_6_7_grps,
1852 	.ngroups = ARRAY_SIZE(i2c_6_7_grps),
1853 };
1854 
1855 /* Pad multiplexing for can0_dis_nor device */
1856 /* Muxed with NOR */
1857 static const unsigned can0_dis_nor_pins[] = { 56, 57 };
1858 static struct spear_muxreg can0_dis_nor_muxreg[] = {
1859 	{
1860 		.reg = PAD_FUNCTION_EN_0,
1861 		.mask = PMX_NFRSTPWDWN2_MASK,
1862 		.val = 0,
1863 	}, {
1864 		.reg = PAD_FUNCTION_EN_1,
1865 		.mask = PMX_NFRSTPWDWN3_MASK,
1866 		.val = 0,
1867 	}, {
1868 		.reg = PAD_DIRECTION_SEL_0,
1869 		.mask = PMX_NFRSTPWDWN2_MASK,
1870 		.val = PMX_NFRSTPWDWN2_MASK,
1871 	}, {
1872 		.reg = PAD_DIRECTION_SEL_1,
1873 		.mask = PMX_NFRSTPWDWN3_MASK,
1874 		.val = PMX_NFRSTPWDWN3_MASK,
1875 	},
1876 };
1877 
1878 static struct spear_modemux can0_dis_nor_modemux[] = {
1879 	{
1880 		.muxregs = can0_dis_nor_muxreg,
1881 		.nmuxregs = ARRAY_SIZE(can0_dis_nor_muxreg),
1882 	},
1883 };
1884 
1885 static struct spear_pingroup can0_dis_nor_pingroup = {
1886 	.name = "can0_dis_nor_grp",
1887 	.pins = can0_dis_nor_pins,
1888 	.npins = ARRAY_SIZE(can0_dis_nor_pins),
1889 	.modemuxs = can0_dis_nor_modemux,
1890 	.nmodemuxs = ARRAY_SIZE(can0_dis_nor_modemux),
1891 };
1892 
1893 /* Pad multiplexing for can0_dis_sd device */
1894 /* Muxed with SD/MMC */
1895 static const unsigned can0_dis_sd_pins[] = { 240, 241 };
1896 static struct spear_muxreg can0_dis_sd_muxreg[] = {
1897 	{
1898 		.reg = PAD_FUNCTION_EN_2,
1899 		.mask = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK,
1900 		.val = 0,
1901 	}, {
1902 		.reg = PAD_DIRECTION_SEL_2,
1903 		.mask = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK,
1904 		.val = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK,
1905 	},
1906 };
1907 
1908 static struct spear_modemux can0_dis_sd_modemux[] = {
1909 	{
1910 		.muxregs = can0_dis_sd_muxreg,
1911 		.nmuxregs = ARRAY_SIZE(can0_dis_sd_muxreg),
1912 	},
1913 };
1914 
1915 static struct spear_pingroup can0_dis_sd_pingroup = {
1916 	.name = "can0_dis_sd_grp",
1917 	.pins = can0_dis_sd_pins,
1918 	.npins = ARRAY_SIZE(can0_dis_sd_pins),
1919 	.modemuxs = can0_dis_sd_modemux,
1920 	.nmodemuxs = ARRAY_SIZE(can0_dis_sd_modemux),
1921 };
1922 
1923 static const char *const can0_grps[] = { "can0_dis_nor_grp", "can0_dis_sd_grp"
1924 };
1925 static struct spear_function can0_function = {
1926 	.name = "can0",
1927 	.groups = can0_grps,
1928 	.ngroups = ARRAY_SIZE(can0_grps),
1929 };
1930 
1931 /* Pad multiplexing for can1_dis_sd device */
1932 /* Muxed with SD/MMC */
1933 static const unsigned can1_dis_sd_pins[] = { 242, 243 };
1934 static struct spear_muxreg can1_dis_sd_muxreg[] = {
1935 	{
1936 		.reg = PAD_FUNCTION_EN_2,
1937 		.mask = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK,
1938 		.val = 0,
1939 	}, {
1940 		.reg = PAD_DIRECTION_SEL_2,
1941 		.mask = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK,
1942 		.val = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK,
1943 	},
1944 };
1945 
1946 static struct spear_modemux can1_dis_sd_modemux[] = {
1947 	{
1948 		.muxregs = can1_dis_sd_muxreg,
1949 		.nmuxregs = ARRAY_SIZE(can1_dis_sd_muxreg),
1950 	},
1951 };
1952 
1953 static struct spear_pingroup can1_dis_sd_pingroup = {
1954 	.name = "can1_dis_sd_grp",
1955 	.pins = can1_dis_sd_pins,
1956 	.npins = ARRAY_SIZE(can1_dis_sd_pins),
1957 	.modemuxs = can1_dis_sd_modemux,
1958 	.nmodemuxs = ARRAY_SIZE(can1_dis_sd_modemux),
1959 };
1960 
1961 /* Pad multiplexing for can1_dis_kbd device */
1962 /* Muxed with KBD */
1963 static const unsigned can1_dis_kbd_pins[] = { 201, 202 };
1964 static struct spear_muxreg can1_dis_kbd_muxreg[] = {
1965 	{
1966 		.reg = PAD_FUNCTION_EN_1,
1967 		.mask = PMX_KBD_ROWCOL25_MASK,
1968 		.val = 0,
1969 	}, {
1970 		.reg = PAD_DIRECTION_SEL_1,
1971 		.mask = PMX_KBD_ROWCOL25_MASK,
1972 		.val = PMX_KBD_ROWCOL25_MASK,
1973 	},
1974 };
1975 
1976 static struct spear_modemux can1_dis_kbd_modemux[] = {
1977 	{
1978 		.muxregs = can1_dis_kbd_muxreg,
1979 		.nmuxregs = ARRAY_SIZE(can1_dis_kbd_muxreg),
1980 	},
1981 };
1982 
1983 static struct spear_pingroup can1_dis_kbd_pingroup = {
1984 	.name = "can1_dis_kbd_grp",
1985 	.pins = can1_dis_kbd_pins,
1986 	.npins = ARRAY_SIZE(can1_dis_kbd_pins),
1987 	.modemuxs = can1_dis_kbd_modemux,
1988 	.nmodemuxs = ARRAY_SIZE(can1_dis_kbd_modemux),
1989 };
1990 
1991 static const char *const can1_grps[] = { "can1_dis_sd_grp", "can1_dis_kbd_grp"
1992 };
1993 static struct spear_function can1_function = {
1994 	.name = "can1",
1995 	.groups = can1_grps,
1996 	.ngroups = ARRAY_SIZE(can1_grps),
1997 };
1998 
1999 /* Pad multiplexing for (ras-ip) pci device */
2000 static const unsigned pci_pins[] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 18,
2001 	19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,
2002 	37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54,
2003 	55, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99 };
2004 
2005 static struct spear_muxreg pci_muxreg[] = {
2006 	{
2007 		.reg = PAD_FUNCTION_EN_0,
2008 		.mask = PMX_MCI_DATA8_15_MASK,
2009 		.val = 0,
2010 	}, {
2011 		.reg = PAD_FUNCTION_EN_1,
2012 		.mask = PMX_PCI_REG1_MASK,
2013 		.val = 0,
2014 	}, {
2015 		.reg = PAD_FUNCTION_EN_2,
2016 		.mask = PMX_PCI_REG2_MASK,
2017 		.val = 0,
2018 	}, {
2019 		.reg = PAD_DIRECTION_SEL_0,
2020 		.mask = PMX_MCI_DATA8_15_MASK,
2021 		.val = PMX_MCI_DATA8_15_MASK,
2022 	}, {
2023 		.reg = PAD_DIRECTION_SEL_1,
2024 		.mask = PMX_PCI_REG1_MASK,
2025 		.val = PMX_PCI_REG1_MASK,
2026 	}, {
2027 		.reg = PAD_DIRECTION_SEL_2,
2028 		.mask = PMX_PCI_REG2_MASK,
2029 		.val = PMX_PCI_REG2_MASK,
2030 	},
2031 };
2032 
2033 static struct spear_modemux pci_modemux[] = {
2034 	{
2035 		.muxregs = pci_muxreg,
2036 		.nmuxregs = ARRAY_SIZE(pci_muxreg),
2037 	},
2038 };
2039 
2040 static struct spear_pingroup pci_pingroup = {
2041 	.name = "pci_grp",
2042 	.pins = pci_pins,
2043 	.npins = ARRAY_SIZE(pci_pins),
2044 	.modemuxs = pci_modemux,
2045 	.nmodemuxs = ARRAY_SIZE(pci_modemux),
2046 };
2047 
2048 static const char *const pci_grps[] = { "pci_grp" };
2049 static struct spear_function pci_function = {
2050 	.name = "pci",
2051 	.groups = pci_grps,
2052 	.ngroups = ARRAY_SIZE(pci_grps),
2053 };
2054 
2055 /* pad multiplexing for (fix-part) pcie0 device */
2056 static struct spear_muxreg pcie0_muxreg[] = {
2057 	{
2058 		.reg = PCIE_SATA_CFG,
2059 		.mask = PCIE_CFG_VAL(0),
2060 		.val = PCIE_CFG_VAL(0),
2061 	},
2062 };
2063 
2064 static struct spear_modemux pcie0_modemux[] = {
2065 	{
2066 		.muxregs = pcie0_muxreg,
2067 		.nmuxregs = ARRAY_SIZE(pcie0_muxreg),
2068 	},
2069 };
2070 
2071 static struct spear_pingroup pcie0_pingroup = {
2072 	.name = "pcie0_grp",
2073 	.modemuxs = pcie0_modemux,
2074 	.nmodemuxs = ARRAY_SIZE(pcie0_modemux),
2075 };
2076 
2077 /* pad multiplexing for (fix-part) pcie1 device */
2078 static struct spear_muxreg pcie1_muxreg[] = {
2079 	{
2080 		.reg = PCIE_SATA_CFG,
2081 		.mask = PCIE_CFG_VAL(1),
2082 		.val = PCIE_CFG_VAL(1),
2083 	},
2084 };
2085 
2086 static struct spear_modemux pcie1_modemux[] = {
2087 	{
2088 		.muxregs = pcie1_muxreg,
2089 		.nmuxregs = ARRAY_SIZE(pcie1_muxreg),
2090 	},
2091 };
2092 
2093 static struct spear_pingroup pcie1_pingroup = {
2094 	.name = "pcie1_grp",
2095 	.modemuxs = pcie1_modemux,
2096 	.nmodemuxs = ARRAY_SIZE(pcie1_modemux),
2097 };
2098 
2099 /* pad multiplexing for (fix-part) pcie2 device */
2100 static struct spear_muxreg pcie2_muxreg[] = {
2101 	{
2102 		.reg = PCIE_SATA_CFG,
2103 		.mask = PCIE_CFG_VAL(2),
2104 		.val = PCIE_CFG_VAL(2),
2105 	},
2106 };
2107 
2108 static struct spear_modemux pcie2_modemux[] = {
2109 	{
2110 		.muxregs = pcie2_muxreg,
2111 		.nmuxregs = ARRAY_SIZE(pcie2_muxreg),
2112 	},
2113 };
2114 
2115 static struct spear_pingroup pcie2_pingroup = {
2116 	.name = "pcie2_grp",
2117 	.modemuxs = pcie2_modemux,
2118 	.nmodemuxs = ARRAY_SIZE(pcie2_modemux),
2119 };
2120 
2121 static const char *const pcie_grps[] = { "pcie0_grp", "pcie1_grp", "pcie2_grp"
2122 };
2123 static struct spear_function pcie_function = {
2124 	.name = "pci_express",
2125 	.groups = pcie_grps,
2126 	.ngroups = ARRAY_SIZE(pcie_grps),
2127 };
2128 
2129 /* pad multiplexing for sata0 device */
2130 static struct spear_muxreg sata0_muxreg[] = {
2131 	{
2132 		.reg = PCIE_SATA_CFG,
2133 		.mask = SATA_CFG_VAL(0),
2134 		.val = SATA_CFG_VAL(0),
2135 	},
2136 };
2137 
2138 static struct spear_modemux sata0_modemux[] = {
2139 	{
2140 		.muxregs = sata0_muxreg,
2141 		.nmuxregs = ARRAY_SIZE(sata0_muxreg),
2142 	},
2143 };
2144 
2145 static struct spear_pingroup sata0_pingroup = {
2146 	.name = "sata0_grp",
2147 	.modemuxs = sata0_modemux,
2148 	.nmodemuxs = ARRAY_SIZE(sata0_modemux),
2149 };
2150 
2151 /* pad multiplexing for sata1 device */
2152 static struct spear_muxreg sata1_muxreg[] = {
2153 	{
2154 		.reg = PCIE_SATA_CFG,
2155 		.mask = SATA_CFG_VAL(1),
2156 		.val = SATA_CFG_VAL(1),
2157 	},
2158 };
2159 
2160 static struct spear_modemux sata1_modemux[] = {
2161 	{
2162 		.muxregs = sata1_muxreg,
2163 		.nmuxregs = ARRAY_SIZE(sata1_muxreg),
2164 	},
2165 };
2166 
2167 static struct spear_pingroup sata1_pingroup = {
2168 	.name = "sata1_grp",
2169 	.modemuxs = sata1_modemux,
2170 	.nmodemuxs = ARRAY_SIZE(sata1_modemux),
2171 };
2172 
2173 /* pad multiplexing for sata2 device */
2174 static struct spear_muxreg sata2_muxreg[] = {
2175 	{
2176 		.reg = PCIE_SATA_CFG,
2177 		.mask = SATA_CFG_VAL(2),
2178 		.val = SATA_CFG_VAL(2),
2179 	},
2180 };
2181 
2182 static struct spear_modemux sata2_modemux[] = {
2183 	{
2184 		.muxregs = sata2_muxreg,
2185 		.nmuxregs = ARRAY_SIZE(sata2_muxreg),
2186 	},
2187 };
2188 
2189 static struct spear_pingroup sata2_pingroup = {
2190 	.name = "sata2_grp",
2191 	.modemuxs = sata2_modemux,
2192 	.nmodemuxs = ARRAY_SIZE(sata2_modemux),
2193 };
2194 
2195 static const char *const sata_grps[] = { "sata0_grp", "sata1_grp", "sata2_grp"
2196 };
2197 static struct spear_function sata_function = {
2198 	.name = "sata",
2199 	.groups = sata_grps,
2200 	.ngroups = ARRAY_SIZE(sata_grps),
2201 };
2202 
2203 /* Pad multiplexing for ssp1_dis_kbd device */
2204 static const unsigned ssp1_dis_kbd_pins[] = { 203, 204, 205, 206 };
2205 static struct spear_muxreg ssp1_dis_kbd_muxreg[] = {
2206 	{
2207 		.reg = PAD_FUNCTION_EN_1,
2208 		.mask = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK |
2209 			PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK |
2210 			PMX_NFCE2_MASK,
2211 		.val = 0,
2212 	}, {
2213 		.reg = PAD_DIRECTION_SEL_1,
2214 		.mask = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK |
2215 			PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK |
2216 			PMX_NFCE2_MASK,
2217 		.val = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK |
2218 			PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK |
2219 			PMX_NFCE2_MASK,
2220 	},
2221 };
2222 
2223 static struct spear_modemux ssp1_dis_kbd_modemux[] = {
2224 	{
2225 		.muxregs = ssp1_dis_kbd_muxreg,
2226 		.nmuxregs = ARRAY_SIZE(ssp1_dis_kbd_muxreg),
2227 	},
2228 };
2229 
2230 static struct spear_pingroup ssp1_dis_kbd_pingroup = {
2231 	.name = "ssp1_dis_kbd_grp",
2232 	.pins = ssp1_dis_kbd_pins,
2233 	.npins = ARRAY_SIZE(ssp1_dis_kbd_pins),
2234 	.modemuxs = ssp1_dis_kbd_modemux,
2235 	.nmodemuxs = ARRAY_SIZE(ssp1_dis_kbd_modemux),
2236 };
2237 
2238 /* Pad multiplexing for ssp1_dis_sd device */
2239 static const unsigned ssp1_dis_sd_pins[] = { 224, 226, 227, 228 };
2240 static struct spear_muxreg ssp1_dis_sd_muxreg[] = {
2241 	{
2242 		.reg = PAD_FUNCTION_EN_2,
2243 		.mask = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK |
2244 			PMX_MCICECF_MASK | PMX_MCICEXD_MASK,
2245 		.val = 0,
2246 	}, {
2247 		.reg = PAD_DIRECTION_SEL_2,
2248 		.mask = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK |
2249 			PMX_MCICECF_MASK | PMX_MCICEXD_MASK,
2250 		.val = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK |
2251 			PMX_MCICECF_MASK | PMX_MCICEXD_MASK,
2252 	},
2253 };
2254 
2255 static struct spear_modemux ssp1_dis_sd_modemux[] = {
2256 	{
2257 		.muxregs = ssp1_dis_sd_muxreg,
2258 		.nmuxregs = ARRAY_SIZE(ssp1_dis_sd_muxreg),
2259 	},
2260 };
2261 
2262 static struct spear_pingroup ssp1_dis_sd_pingroup = {
2263 	.name = "ssp1_dis_sd_grp",
2264 	.pins = ssp1_dis_sd_pins,
2265 	.npins = ARRAY_SIZE(ssp1_dis_sd_pins),
2266 	.modemuxs = ssp1_dis_sd_modemux,
2267 	.nmodemuxs = ARRAY_SIZE(ssp1_dis_sd_modemux),
2268 };
2269 
2270 static const char *const ssp1_grps[] = { "ssp1_dis_kbd_grp",
2271 	"ssp1_dis_sd_grp" };
2272 static struct spear_function ssp1_function = {
2273 	.name = "ssp1",
2274 	.groups = ssp1_grps,
2275 	.ngroups = ARRAY_SIZE(ssp1_grps),
2276 };
2277 
2278 /* Pad multiplexing for gpt64 device */
2279 static const unsigned gpt64_pins[] = { 230, 231, 232, 245 };
2280 static struct spear_muxreg gpt64_muxreg[] = {
2281 	{
2282 		.reg = PAD_FUNCTION_EN_2,
2283 		.mask = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK
2284 			| PMX_MCILEDS_MASK,
2285 		.val = 0,
2286 	}, {
2287 		.reg = PAD_DIRECTION_SEL_2,
2288 		.mask = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK
2289 			| PMX_MCILEDS_MASK,
2290 		.val = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK
2291 			| PMX_MCILEDS_MASK,
2292 	},
2293 };
2294 
2295 static struct spear_modemux gpt64_modemux[] = {
2296 	{
2297 		.muxregs = gpt64_muxreg,
2298 		.nmuxregs = ARRAY_SIZE(gpt64_muxreg),
2299 	},
2300 };
2301 
2302 static struct spear_pingroup gpt64_pingroup = {
2303 	.name = "gpt64_grp",
2304 	.pins = gpt64_pins,
2305 	.npins = ARRAY_SIZE(gpt64_pins),
2306 	.modemuxs = gpt64_modemux,
2307 	.nmodemuxs = ARRAY_SIZE(gpt64_modemux),
2308 };
2309 
2310 static const char *const gpt64_grps[] = { "gpt64_grp" };
2311 static struct spear_function gpt64_function = {
2312 	.name = "gpt64",
2313 	.groups = gpt64_grps,
2314 	.ngroups = ARRAY_SIZE(gpt64_grps),
2315 };
2316 
2317 /* pingroups */
2318 static struct spear_pingroup *spear1310_pingroups[] = {
2319 	&i2c0_pingroup,
2320 	&ssp0_pingroup,
2321 	&i2s0_pingroup,
2322 	&i2s1_pingroup,
2323 	&clcd_pingroup,
2324 	&clcd_high_res_pingroup,
2325 	&arm_gpio_pingroup,
2326 	&smi_2_chips_pingroup,
2327 	&smi_4_chips_pingroup,
2328 	&gmii_pingroup,
2329 	&rgmii_pingroup,
2330 	&smii_0_1_2_pingroup,
2331 	&ras_mii_txclk_pingroup,
2332 	&nand_8bit_pingroup,
2333 	&nand_16bit_pingroup,
2334 	&nand_4_chips_pingroup,
2335 	&keyboard_6x6_pingroup,
2336 	&keyboard_rowcol6_8_pingroup,
2337 	&uart0_pingroup,
2338 	&uart0_modem_pingroup,
2339 	&gpt0_tmr0_pingroup,
2340 	&gpt0_tmr1_pingroup,
2341 	&gpt1_tmr0_pingroup,
2342 	&gpt1_tmr1_pingroup,
2343 	&sdhci_pingroup,
2344 	&cf_pingroup,
2345 	&xd_pingroup,
2346 	&touch_xy_pingroup,
2347 	&ssp0_cs0_pingroup,
2348 	&ssp0_cs1_2_pingroup,
2349 	&uart_1_dis_i2c_pingroup,
2350 	&uart_1_dis_sd_pingroup,
2351 	&uart_2_3_pingroup,
2352 	&uart_4_pingroup,
2353 	&uart_5_pingroup,
2354 	&rs485_0_1_tdm_0_1_pingroup,
2355 	&i2c_1_2_pingroup,
2356 	&i2c3_dis_smi_clcd_pingroup,
2357 	&i2c3_dis_sd_i2s0_pingroup,
2358 	&i2c_4_5_dis_smi_pingroup,
2359 	&i2c4_dis_sd_pingroup,
2360 	&i2c5_dis_sd_pingroup,
2361 	&i2c_6_7_dis_kbd_pingroup,
2362 	&i2c6_dis_sd_pingroup,
2363 	&i2c7_dis_sd_pingroup,
2364 	&can0_dis_nor_pingroup,
2365 	&can0_dis_sd_pingroup,
2366 	&can1_dis_sd_pingroup,
2367 	&can1_dis_kbd_pingroup,
2368 	&pci_pingroup,
2369 	&pcie0_pingroup,
2370 	&pcie1_pingroup,
2371 	&pcie2_pingroup,
2372 	&sata0_pingroup,
2373 	&sata1_pingroup,
2374 	&sata2_pingroup,
2375 	&ssp1_dis_kbd_pingroup,
2376 	&ssp1_dis_sd_pingroup,
2377 	&gpt64_pingroup,
2378 };
2379 
2380 /* functions */
2381 static struct spear_function *spear1310_functions[] = {
2382 	&i2c0_function,
2383 	&ssp0_function,
2384 	&i2s0_function,
2385 	&i2s1_function,
2386 	&clcd_function,
2387 	&arm_gpio_function,
2388 	&smi_function,
2389 	&gmii_function,
2390 	&rgmii_function,
2391 	&smii_0_1_2_function,
2392 	&ras_mii_txclk_function,
2393 	&nand_function,
2394 	&keyboard_function,
2395 	&uart0_function,
2396 	&gpt0_function,
2397 	&gpt1_function,
2398 	&sdhci_function,
2399 	&cf_function,
2400 	&xd_function,
2401 	&touch_xy_function,
2402 	&uart1_function,
2403 	&uart2_3_function,
2404 	&uart4_function,
2405 	&uart5_function,
2406 	&rs485_0_1_tdm_0_1_function,
2407 	&i2c_1_2_function,
2408 	&i2c3_unction,
2409 	&i2c_4_5_function,
2410 	&i2c_6_7_function,
2411 	&can0_function,
2412 	&can1_function,
2413 	&pci_function,
2414 	&pcie_function,
2415 	&sata_function,
2416 	&ssp1_function,
2417 	&gpt64_function,
2418 };
2419 
2420 static const unsigned pin18[] = { 18, };
2421 static const unsigned pin19[] = { 19, };
2422 static const unsigned pin20[] = { 20, };
2423 static const unsigned pin21[] = { 21, };
2424 static const unsigned pin22[] = { 22, };
2425 static const unsigned pin23[] = { 23, };
2426 static const unsigned pin54[] = { 54, };
2427 static const unsigned pin55[] = { 55, };
2428 static const unsigned pin56[] = { 56, };
2429 static const unsigned pin57[] = { 57, };
2430 static const unsigned pin58[] = { 58, };
2431 static const unsigned pin59[] = { 59, };
2432 static const unsigned pin60[] = { 60, };
2433 static const unsigned pin61[] = { 61, };
2434 static const unsigned pin62[] = { 62, };
2435 static const unsigned pin63[] = { 63, };
2436 static const unsigned pin143[] = { 143, };
2437 static const unsigned pin144[] = { 144, };
2438 static const unsigned pin145[] = { 145, };
2439 static const unsigned pin146[] = { 146, };
2440 static const unsigned pin147[] = { 147, };
2441 static const unsigned pin148[] = { 148, };
2442 static const unsigned pin149[] = { 149, };
2443 static const unsigned pin150[] = { 150, };
2444 static const unsigned pin151[] = { 151, };
2445 static const unsigned pin152[] = { 152, };
2446 static const unsigned pin205[] = { 205, };
2447 static const unsigned pin206[] = { 206, };
2448 static const unsigned pin211[] = { 211, };
2449 static const unsigned pin212[] = { 212, };
2450 static const unsigned pin213[] = { 213, };
2451 static const unsigned pin214[] = { 214, };
2452 static const unsigned pin215[] = { 215, };
2453 static const unsigned pin216[] = { 216, };
2454 static const unsigned pin217[] = { 217, };
2455 static const unsigned pin218[] = { 218, };
2456 static const unsigned pin219[] = { 219, };
2457 static const unsigned pin220[] = { 220, };
2458 static const unsigned pin221[] = { 221, };
2459 static const unsigned pin222[] = { 222, };
2460 static const unsigned pin223[] = { 223, };
2461 static const unsigned pin224[] = { 224, };
2462 static const unsigned pin225[] = { 225, };
2463 static const unsigned pin226[] = { 226, };
2464 static const unsigned pin227[] = { 227, };
2465 static const unsigned pin228[] = { 228, };
2466 static const unsigned pin229[] = { 229, };
2467 static const unsigned pin230[] = { 230, };
2468 static const unsigned pin231[] = { 231, };
2469 static const unsigned pin232[] = { 232, };
2470 static const unsigned pin233[] = { 233, };
2471 static const unsigned pin234[] = { 234, };
2472 static const unsigned pin235[] = { 235, };
2473 static const unsigned pin236[] = { 236, };
2474 static const unsigned pin237[] = { 237, };
2475 static const unsigned pin238[] = { 238, };
2476 static const unsigned pin239[] = { 239, };
2477 static const unsigned pin240[] = { 240, };
2478 static const unsigned pin241[] = { 241, };
2479 static const unsigned pin242[] = { 242, };
2480 static const unsigned pin243[] = { 243, };
2481 static const unsigned pin244[] = { 244, };
2482 static const unsigned pin245[] = { 245, };
2483 
2484 static const unsigned pin_grp0[] = { 173, 174, };
2485 static const unsigned pin_grp1[] = { 175, 185, 188, 197, 198, };
2486 static const unsigned pin_grp2[] = { 176, 177, 178, 179, 184, 186, 187, 189,
2487 	190, 191, 192, };
2488 static const unsigned pin_grp3[] = { 180, 181, 182, 183, 193, 194, 195, 196, };
2489 static const unsigned pin_grp4[] = { 199, 200, };
2490 static const unsigned pin_grp5[] = { 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74,
2491 	75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, };
2492 static const unsigned pin_grp6[] = { 86, 87, 88, 89, 90, 91, 92, 93, };
2493 static const unsigned pin_grp7[] = { 98, 99, };
2494 static const unsigned pin_grp8[] = { 158, 159, 160, 161, 162, 163, 164, 165,
2495 	166, 167, 168, 169, 170, 171, 172, };
2496 
2497 /* Define muxreg arrays */
2498 DEFINE_2_MUXREG(i2c0_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_I2C0_MASK, 0, 1);
2499 DEFINE_2_MUXREG(ssp0_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_SSP0_MASK, 0, 1);
2500 DEFINE_2_MUXREG(ssp0_cs0_pins, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_SSP0_CS0_MASK, 0, 1);
2501 DEFINE_2_MUXREG(ssp0_cs1_2_pins, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_SSP0_CS1_2_MASK, 0, 1);
2502 DEFINE_2_MUXREG(i2s0_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_I2S0_MASK, 0, 1);
2503 DEFINE_2_MUXREG(i2s1_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_I2S1_MASK, 0, 1);
2504 DEFINE_2_MUXREG(clcd_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_CLCD1_MASK, 0, 1);
2505 DEFINE_2_MUXREG(clcd_high_res_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_CLCD2_MASK, 0, 1);
2506 DEFINE_2_MUXREG(pin18, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO15_MASK, 0, 1);
2507 DEFINE_2_MUXREG(pin19, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO14_MASK, 0, 1);
2508 DEFINE_2_MUXREG(pin20, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO13_MASK, 0, 1);
2509 DEFINE_2_MUXREG(pin21, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO12_MASK, 0, 1);
2510 DEFINE_2_MUXREG(pin22, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO11_MASK, 0, 1);
2511 DEFINE_2_MUXREG(pin23, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO10_MASK, 0, 1);
2512 DEFINE_2_MUXREG(pin143, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO00_MASK, 0, 1);
2513 DEFINE_2_MUXREG(pin144, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO01_MASK, 0, 1);
2514 DEFINE_2_MUXREG(pin145, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO02_MASK, 0, 1);
2515 DEFINE_2_MUXREG(pin146, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO03_MASK, 0, 1);
2516 DEFINE_2_MUXREG(pin147, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO04_MASK, 0, 1);
2517 DEFINE_2_MUXREG(pin148, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO05_MASK, 0, 1);
2518 DEFINE_2_MUXREG(pin149, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO06_MASK, 0, 1);
2519 DEFINE_2_MUXREG(pin150, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO07_MASK, 0, 1);
2520 DEFINE_2_MUXREG(pin151, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO08_MASK, 0, 1);
2521 DEFINE_2_MUXREG(pin152, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO09_MASK, 0, 1);
2522 DEFINE_2_MUXREG(smi_2_chips_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_SMI_MASK, 0, 1);
2523 DEFINE_2_MUXREG(pin54, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_SMINCS3_MASK, 0, 1);
2524 DEFINE_2_MUXREG(pin55, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_SMINCS2_MASK, 0, 1);
2525 DEFINE_2_MUXREG(pin56, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_NFRSTPWDWN3_MASK, 0, 1);
2526 DEFINE_2_MUXREG(pin57, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFRSTPWDWN2_MASK, 0, 1);
2527 DEFINE_2_MUXREG(pin58, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFRSTPWDWN1_MASK, 0, 1);
2528 DEFINE_2_MUXREG(pin59, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFRSTPWDWN0_MASK, 0, 1);
2529 DEFINE_2_MUXREG(pin60, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFWPRT3_MASK, 0, 1);
2530 DEFINE_2_MUXREG(pin61, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFCE3_MASK, 0, 1);
2531 DEFINE_2_MUXREG(pin62, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFAD25_MASK, 0, 1);
2532 DEFINE_2_MUXREG(pin63, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFAD24_MASK, 0, 1);
2533 DEFINE_2_MUXREG(pin_grp0, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_GMIICLK_MASK, 0, 1);
2534 DEFINE_2_MUXREG(pin_grp1, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK, 0, 1);
2535 DEFINE_2_MUXREG(pin_grp2, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_RXCLK_RDV_TXEN_D03_MASK, 0, 1);
2536 DEFINE_2_MUXREG(pin_grp3, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_GMIID47_MASK, 0, 1);
2537 DEFINE_2_MUXREG(pin_grp4, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_MDC_MDIO_MASK, 0, 1);
2538 DEFINE_2_MUXREG(pin_grp5, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFAD23_MASK, 0, 1);
2539 DEFINE_2_MUXREG(pin_grp6, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_MCI_DATA8_15_MASK, 0, 1);
2540 DEFINE_2_MUXREG(pin_grp7, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_NFCE2_MASK, 0, 1);
2541 DEFINE_2_MUXREG(pin_grp8, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_NAND8_MASK, 0, 1);
2542 DEFINE_2_MUXREG(nand_16bit_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_NAND16BIT_1_MASK, 0, 1);
2543 DEFINE_2_MUXREG(pin205, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_COL1_MASK | PMX_NFCE1_MASK, 0, 1);
2544 DEFINE_2_MUXREG(pin206, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_COL0_MASK | PMX_NFCE2_MASK, 0, 1);
2545 DEFINE_2_MUXREG(pin211, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_ROW1_MASK | PMX_NFWPRT1_MASK, 0, 1);
2546 DEFINE_2_MUXREG(pin212, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_ROW0_MASK | PMX_NFWPRT2_MASK, 0, 1);
2547 DEFINE_2_MUXREG(pin213, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA0_MASK, 0, 1);
2548 DEFINE_2_MUXREG(pin214, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA1_MASK, 0, 1);
2549 DEFINE_2_MUXREG(pin215, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA2_MASK, 0, 1);
2550 DEFINE_2_MUXREG(pin216, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA3_MASK, 0, 1);
2551 DEFINE_2_MUXREG(pin217, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA4_MASK, 0, 1);
2552 DEFINE_2_MUXREG(pin218, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA5_MASK, 0, 1);
2553 DEFINE_2_MUXREG(pin219, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA6_MASK, 0, 1);
2554 DEFINE_2_MUXREG(pin220, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA7_MASK, 0, 1);
2555 DEFINE_2_MUXREG(pin221, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA1SD_MASK, 0, 1);
2556 DEFINE_2_MUXREG(pin222, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA2SD_MASK, 0, 1);
2557 DEFINE_2_MUXREG(pin223, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA3SD_MASK, 0, 1);
2558 DEFINE_2_MUXREG(pin224, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIADDR0ALE_MASK, 0, 1);
2559 DEFINE_2_MUXREG(pin225, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIADDR1CLECLK_MASK, 0, 1);
2560 DEFINE_2_MUXREG(pin226, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIADDR2_MASK, 0, 1);
2561 DEFINE_2_MUXREG(pin227, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICECF_MASK, 0, 1);
2562 DEFINE_2_MUXREG(pin228, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICEXD_MASK, 0, 1);
2563 DEFINE_2_MUXREG(pin229, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICESDMMC_MASK, 0, 1);
2564 DEFINE_2_MUXREG(pin230, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICDCF1_MASK, 0, 1);
2565 DEFINE_2_MUXREG(pin231, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICDCF2_MASK, 0, 1);
2566 DEFINE_2_MUXREG(pin232, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICDXD_MASK, 0, 1);
2567 DEFINE_2_MUXREG(pin233, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICDSDMMC_MASK, 0, 1);
2568 DEFINE_2_MUXREG(pin234, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATADIR_MASK, 0, 1);
2569 DEFINE_2_MUXREG(pin235, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDMARQWP_MASK, 0, 1);
2570 DEFINE_2_MUXREG(pin236, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIIORDRE_MASK, 0, 1);
2571 DEFINE_2_MUXREG(pin237, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIIOWRWE_MASK, 0, 1);
2572 DEFINE_2_MUXREG(pin238, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIRESETCF_MASK, 0, 1);
2573 DEFINE_2_MUXREG(pin239, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICS0CE_MASK, 0, 1);
2574 DEFINE_2_MUXREG(pin240, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICFINTR_MASK, 0, 1);
2575 DEFINE_2_MUXREG(pin241, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIIORDY_MASK, 0, 1);
2576 DEFINE_2_MUXREG(pin242, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICS1_MASK, 0, 1);
2577 DEFINE_2_MUXREG(pin243, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDMAACK_MASK, 0, 1);
2578 DEFINE_2_MUXREG(pin244, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCISDCMD_MASK, 0, 1);
2579 DEFINE_2_MUXREG(pin245, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCILEDS_MASK, 0, 1);
2580 DEFINE_2_MUXREG(keyboard_rowcol6_8_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_ROWCOL68_MASK, 0, 1);
2581 DEFINE_2_MUXREG(uart0_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_UART0_MASK, 0, 1);
2582 DEFINE_2_MUXREG(uart0_modem_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_UART0_MODEM_MASK, 0, 1);
2583 DEFINE_2_MUXREG(gpt0_tmr0_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_GPT0_TMR0_MASK, 0, 1);
2584 DEFINE_2_MUXREG(gpt0_tmr1_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_GPT0_TMR1_MASK, 0, 1);
2585 DEFINE_2_MUXREG(gpt1_tmr0_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_GPT1_TMR0_MASK, 0, 1);
2586 DEFINE_2_MUXREG(gpt1_tmr1_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_GPT1_TMR1_MASK, 0, 1);
2587 DEFINE_2_MUXREG(touch_xy_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_TOUCH_XY_MASK, 0, 1);
2588 
2589 static struct spear_gpio_pingroup spear1310_gpio_pingroup[] = {
2590 	GPIO_PINGROUP(i2c0_pins),
2591 	GPIO_PINGROUP(ssp0_pins),
2592 	GPIO_PINGROUP(ssp0_cs0_pins),
2593 	GPIO_PINGROUP(ssp0_cs1_2_pins),
2594 	GPIO_PINGROUP(i2s0_pins),
2595 	GPIO_PINGROUP(i2s1_pins),
2596 	GPIO_PINGROUP(clcd_pins),
2597 	GPIO_PINGROUP(clcd_high_res_pins),
2598 	GPIO_PINGROUP(pin18),
2599 	GPIO_PINGROUP(pin19),
2600 	GPIO_PINGROUP(pin20),
2601 	GPIO_PINGROUP(pin21),
2602 	GPIO_PINGROUP(pin22),
2603 	GPIO_PINGROUP(pin23),
2604 	GPIO_PINGROUP(pin143),
2605 	GPIO_PINGROUP(pin144),
2606 	GPIO_PINGROUP(pin145),
2607 	GPIO_PINGROUP(pin146),
2608 	GPIO_PINGROUP(pin147),
2609 	GPIO_PINGROUP(pin148),
2610 	GPIO_PINGROUP(pin149),
2611 	GPIO_PINGROUP(pin150),
2612 	GPIO_PINGROUP(pin151),
2613 	GPIO_PINGROUP(pin152),
2614 	GPIO_PINGROUP(smi_2_chips_pins),
2615 	GPIO_PINGROUP(pin54),
2616 	GPIO_PINGROUP(pin55),
2617 	GPIO_PINGROUP(pin56),
2618 	GPIO_PINGROUP(pin57),
2619 	GPIO_PINGROUP(pin58),
2620 	GPIO_PINGROUP(pin59),
2621 	GPIO_PINGROUP(pin60),
2622 	GPIO_PINGROUP(pin61),
2623 	GPIO_PINGROUP(pin62),
2624 	GPIO_PINGROUP(pin63),
2625 	GPIO_PINGROUP(pin_grp0),
2626 	GPIO_PINGROUP(pin_grp1),
2627 	GPIO_PINGROUP(pin_grp2),
2628 	GPIO_PINGROUP(pin_grp3),
2629 	GPIO_PINGROUP(pin_grp4),
2630 	GPIO_PINGROUP(pin_grp5),
2631 	GPIO_PINGROUP(pin_grp6),
2632 	GPIO_PINGROUP(pin_grp7),
2633 	GPIO_PINGROUP(pin_grp8),
2634 	GPIO_PINGROUP(nand_16bit_pins),
2635 	GPIO_PINGROUP(pin205),
2636 	GPIO_PINGROUP(pin206),
2637 	GPIO_PINGROUP(pin211),
2638 	GPIO_PINGROUP(pin212),
2639 	GPIO_PINGROUP(pin213),
2640 	GPIO_PINGROUP(pin214),
2641 	GPIO_PINGROUP(pin215),
2642 	GPIO_PINGROUP(pin216),
2643 	GPIO_PINGROUP(pin217),
2644 	GPIO_PINGROUP(pin218),
2645 	GPIO_PINGROUP(pin219),
2646 	GPIO_PINGROUP(pin220),
2647 	GPIO_PINGROUP(pin221),
2648 	GPIO_PINGROUP(pin222),
2649 	GPIO_PINGROUP(pin223),
2650 	GPIO_PINGROUP(pin224),
2651 	GPIO_PINGROUP(pin225),
2652 	GPIO_PINGROUP(pin226),
2653 	GPIO_PINGROUP(pin227),
2654 	GPIO_PINGROUP(pin228),
2655 	GPIO_PINGROUP(pin229),
2656 	GPIO_PINGROUP(pin230),
2657 	GPIO_PINGROUP(pin231),
2658 	GPIO_PINGROUP(pin232),
2659 	GPIO_PINGROUP(pin233),
2660 	GPIO_PINGROUP(pin234),
2661 	GPIO_PINGROUP(pin235),
2662 	GPIO_PINGROUP(pin236),
2663 	GPIO_PINGROUP(pin237),
2664 	GPIO_PINGROUP(pin238),
2665 	GPIO_PINGROUP(pin239),
2666 	GPIO_PINGROUP(pin240),
2667 	GPIO_PINGROUP(pin241),
2668 	GPIO_PINGROUP(pin242),
2669 	GPIO_PINGROUP(pin243),
2670 	GPIO_PINGROUP(pin244),
2671 	GPIO_PINGROUP(pin245),
2672 	GPIO_PINGROUP(keyboard_rowcol6_8_pins),
2673 	GPIO_PINGROUP(uart0_pins),
2674 	GPIO_PINGROUP(uart0_modem_pins),
2675 	GPIO_PINGROUP(gpt0_tmr0_pins),
2676 	GPIO_PINGROUP(gpt0_tmr1_pins),
2677 	GPIO_PINGROUP(gpt1_tmr0_pins),
2678 	GPIO_PINGROUP(gpt1_tmr1_pins),
2679 	GPIO_PINGROUP(touch_xy_pins),
2680 };
2681 
2682 static struct spear_pinctrl_machdata spear1310_machdata = {
2683 	.pins = spear1310_pins,
2684 	.npins = ARRAY_SIZE(spear1310_pins),
2685 	.groups = spear1310_pingroups,
2686 	.ngroups = ARRAY_SIZE(spear1310_pingroups),
2687 	.functions = spear1310_functions,
2688 	.nfunctions = ARRAY_SIZE(spear1310_functions),
2689 	.gpio_pingroups = spear1310_gpio_pingroup,
2690 	.ngpio_pingroups = ARRAY_SIZE(spear1310_gpio_pingroup),
2691 	.modes_supported = false,
2692 };
2693 
2694 static const struct of_device_id spear1310_pinctrl_of_match[] = {
2695 	{
2696 		.compatible = "st,spear1310-pinmux",
2697 	},
2698 	{},
2699 };
2700 
2701 static int spear1310_pinctrl_probe(struct platform_device *pdev)
2702 {
2703 	return spear_pinctrl_probe(pdev, &spear1310_machdata);
2704 }
2705 
2706 static struct platform_driver spear1310_pinctrl_driver = {
2707 	.driver = {
2708 		.name = DRIVER_NAME,
2709 		.of_match_table = spear1310_pinctrl_of_match,
2710 	},
2711 	.probe = spear1310_pinctrl_probe,
2712 };
2713 
2714 static int __init spear1310_pinctrl_init(void)
2715 {
2716 	return platform_driver_register(&spear1310_pinctrl_driver);
2717 }
2718 arch_initcall(spear1310_pinctrl_init);
2719