1deda8287SViresh Kumar /* 2deda8287SViresh Kumar * Driver header file for the ST Microelectronics SPEAr pinmux 3deda8287SViresh Kumar * 4deda8287SViresh Kumar * Copyright (C) 2012 ST Microelectronics 510d8935fSViresh Kumar * Viresh Kumar <viresh.linux@gmail.com> 6deda8287SViresh Kumar * 7deda8287SViresh Kumar * This file is licensed under the terms of the GNU General Public 8deda8287SViresh Kumar * License version 2. This program is licensed "as is" without any 9deda8287SViresh Kumar * warranty of any kind, whether express or implied. 10deda8287SViresh Kumar */ 11deda8287SViresh Kumar 12deda8287SViresh Kumar #ifndef __PINMUX_SPEAR_H__ 13deda8287SViresh Kumar #define __PINMUX_SPEAR_H__ 14deda8287SViresh Kumar 15f4f8e563SViresh Kumar #include <linux/gpio.h> 16deda8287SViresh Kumar #include <linux/pinctrl/pinctrl.h> 17deda8287SViresh Kumar #include <linux/types.h> 18deda8287SViresh Kumar 19deda8287SViresh Kumar struct platform_device; 20deda8287SViresh Kumar struct device; 21deda8287SViresh Kumar 22deda8287SViresh Kumar /** 23deda8287SViresh Kumar * struct spear_pmx_mode - SPEAr pmx mode 24deda8287SViresh Kumar * @name: name of pmx mode 25deda8287SViresh Kumar * @mode: mode id 26deda8287SViresh Kumar * @reg: register for configuring this mode 27deda8287SViresh Kumar * @mask: mask of this mode in reg 28deda8287SViresh Kumar * @val: val to be configured at reg after doing (val & mask) 29deda8287SViresh Kumar */ 30deda8287SViresh Kumar struct spear_pmx_mode { 31deda8287SViresh Kumar const char *const name; 32deda8287SViresh Kumar u16 mode; 33deda8287SViresh Kumar u16 reg; 34deda8287SViresh Kumar u16 mask; 35deda8287SViresh Kumar u32 val; 36deda8287SViresh Kumar }; 37deda8287SViresh Kumar 38deda8287SViresh Kumar /** 39deda8287SViresh Kumar * struct spear_muxreg - SPEAr mux reg configuration 40deda8287SViresh Kumar * @reg: register offset 41deda8287SViresh Kumar * @mask: mask bits 42deda8287SViresh Kumar * @val: val to be written on mask bits 43deda8287SViresh Kumar */ 44deda8287SViresh Kumar struct spear_muxreg { 45deda8287SViresh Kumar u16 reg; 46deda8287SViresh Kumar u32 mask; 47deda8287SViresh Kumar u32 val; 48deda8287SViresh Kumar }; 49deda8287SViresh Kumar 50f4f8e563SViresh Kumar struct spear_gpio_pingroup { 51f4f8e563SViresh Kumar const unsigned *pins; 52f4f8e563SViresh Kumar unsigned npins; 53f4f8e563SViresh Kumar struct spear_muxreg *muxregs; 54f4f8e563SViresh Kumar u8 nmuxregs; 55f4f8e563SViresh Kumar }; 56f4f8e563SViresh Kumar 57f4f8e563SViresh Kumar /* ste: set to enable */ 58f4f8e563SViresh Kumar #define DEFINE_MUXREG(__pins, __muxreg, __mask, __ste) \ 59f4f8e563SViresh Kumar static struct spear_muxreg __pins##_muxregs[] = { \ 60f4f8e563SViresh Kumar { \ 61f4f8e563SViresh Kumar .reg = __muxreg, \ 62f4f8e563SViresh Kumar .mask = __mask, \ 63f4f8e563SViresh Kumar .val = __ste ? __mask : 0, \ 64f4f8e563SViresh Kumar }, \ 65f4f8e563SViresh Kumar } 66f4f8e563SViresh Kumar 67f4f8e563SViresh Kumar #define DEFINE_2_MUXREG(__pins, __muxreg1, __muxreg2, __mask, __ste1, __ste2) \ 68f4f8e563SViresh Kumar static struct spear_muxreg __pins##_muxregs[] = { \ 69f4f8e563SViresh Kumar { \ 70f4f8e563SViresh Kumar .reg = __muxreg1, \ 71f4f8e563SViresh Kumar .mask = __mask, \ 72f4f8e563SViresh Kumar .val = __ste1 ? __mask : 0, \ 73f4f8e563SViresh Kumar }, { \ 74f4f8e563SViresh Kumar .reg = __muxreg2, \ 75f4f8e563SViresh Kumar .mask = __mask, \ 76f4f8e563SViresh Kumar .val = __ste2 ? __mask : 0, \ 77f4f8e563SViresh Kumar }, \ 78f4f8e563SViresh Kumar } 79f4f8e563SViresh Kumar 80f4f8e563SViresh Kumar #define GPIO_PINGROUP(__pins) \ 81f4f8e563SViresh Kumar { \ 82f4f8e563SViresh Kumar .pins = __pins, \ 83f4f8e563SViresh Kumar .npins = ARRAY_SIZE(__pins), \ 84f4f8e563SViresh Kumar .muxregs = __pins##_muxregs, \ 85f4f8e563SViresh Kumar .nmuxregs = ARRAY_SIZE(__pins##_muxregs), \ 86f4f8e563SViresh Kumar } 87f4f8e563SViresh Kumar 88deda8287SViresh Kumar /** 89deda8287SViresh Kumar * struct spear_modemux - SPEAr mode mux configuration 90deda8287SViresh Kumar * @modes: mode ids supported by this group of muxregs 91deda8287SViresh Kumar * @nmuxregs: number of muxreg configurations to be done for modes 92deda8287SViresh Kumar * @muxregs: array of muxreg configurations to be done for modes 93deda8287SViresh Kumar */ 94deda8287SViresh Kumar struct spear_modemux { 95deda8287SViresh Kumar u16 modes; 96deda8287SViresh Kumar u8 nmuxregs; 97deda8287SViresh Kumar struct spear_muxreg *muxregs; 98deda8287SViresh Kumar }; 99deda8287SViresh Kumar 100deda8287SViresh Kumar /** 101deda8287SViresh Kumar * struct spear_pingroup - SPEAr pin group configurations 102deda8287SViresh Kumar * @name: name of pin group 103deda8287SViresh Kumar * @pins: array containing pin numbers 104deda8287SViresh Kumar * @npins: size of pins array 105deda8287SViresh Kumar * @modemuxs: array of modemux configurations for this pin group 106deda8287SViresh Kumar * @nmodemuxs: size of array modemuxs 107deda8287SViresh Kumar * 108deda8287SViresh Kumar * A representation of a group of pins in the SPEAr pin controller. Each group 109deda8287SViresh Kumar * allows some parameter or parameters to be configured. 110deda8287SViresh Kumar */ 111deda8287SViresh Kumar struct spear_pingroup { 112deda8287SViresh Kumar const char *name; 113deda8287SViresh Kumar const unsigned *pins; 114deda8287SViresh Kumar unsigned npins; 115deda8287SViresh Kumar struct spear_modemux *modemuxs; 116deda8287SViresh Kumar unsigned nmodemuxs; 117deda8287SViresh Kumar }; 118deda8287SViresh Kumar 119deda8287SViresh Kumar /** 120deda8287SViresh Kumar * struct spear_function - SPEAr pinctrl mux function 121deda8287SViresh Kumar * @name: The name of the function, exported to pinctrl core. 122deda8287SViresh Kumar * @groups: An array of pin groups that may select this function. 123deda8287SViresh Kumar * @ngroups: The number of entries in @groups. 124deda8287SViresh Kumar */ 125deda8287SViresh Kumar struct spear_function { 126deda8287SViresh Kumar const char *name; 127deda8287SViresh Kumar const char *const *groups; 128deda8287SViresh Kumar unsigned ngroups; 129deda8287SViresh Kumar }; 130deda8287SViresh Kumar 131deda8287SViresh Kumar /** 132deda8287SViresh Kumar * struct spear_pinctrl_machdata - SPEAr pin controller machine driver 133deda8287SViresh Kumar * configuration 134deda8287SViresh Kumar * @pins: An array describing all pins the pin controller affects. 135deda8287SViresh Kumar * All pins which are also GPIOs must be listed first within the *array, 136deda8287SViresh Kumar * and be numbered identically to the GPIO controller's *numbering. 137deda8287SViresh Kumar * @npins: The numbmer of entries in @pins. 138deda8287SViresh Kumar * @functions: An array describing all mux functions the SoC supports. 139deda8287SViresh Kumar * @nfunctions: The numbmer of entries in @functions. 140deda8287SViresh Kumar * @groups: An array describing all pin groups the pin SoC supports. 141deda8287SViresh Kumar * @ngroups: The numbmer of entries in @groups. 142f4f8e563SViresh Kumar * @gpio_pingroups: gpio pingroups 143f4f8e563SViresh Kumar * @ngpio_pingroups: gpio pingroups count 144deda8287SViresh Kumar * 145deda8287SViresh Kumar * @modes_supported: Does SoC support modes 146deda8287SViresh Kumar * @mode: mode configured from probe 147deda8287SViresh Kumar * @pmx_modes: array of modes supported by SoC 148deda8287SViresh Kumar * @npmx_modes: number of entries in pmx_modes. 149deda8287SViresh Kumar */ 150deda8287SViresh Kumar struct spear_pinctrl_machdata { 151deda8287SViresh Kumar const struct pinctrl_pin_desc *pins; 152deda8287SViresh Kumar unsigned npins; 153deda8287SViresh Kumar struct spear_function **functions; 154deda8287SViresh Kumar unsigned nfunctions; 155deda8287SViresh Kumar struct spear_pingroup **groups; 156deda8287SViresh Kumar unsigned ngroups; 157f4f8e563SViresh Kumar struct spear_gpio_pingroup *gpio_pingroups; 158f4f8e563SViresh Kumar unsigned ngpio_pingroups; 159deda8287SViresh Kumar 160deda8287SViresh Kumar bool modes_supported; 161deda8287SViresh Kumar u16 mode; 162deda8287SViresh Kumar struct spear_pmx_mode **pmx_modes; 163deda8287SViresh Kumar unsigned npmx_modes; 164deda8287SViresh Kumar }; 165deda8287SViresh Kumar 166deda8287SViresh Kumar /** 167deda8287SViresh Kumar * struct spear_pmx - SPEAr pinctrl mux 168deda8287SViresh Kumar * @dev: pointer to struct dev of platform_device registered 169deda8287SViresh Kumar * @pctl: pointer to struct pinctrl_dev 170deda8287SViresh Kumar * @machdata: pointer to SoC or machine specific structure 171deda8287SViresh Kumar * @vbase: virtual base address of pinmux controller 172deda8287SViresh Kumar */ 173deda8287SViresh Kumar struct spear_pmx { 174deda8287SViresh Kumar struct device *dev; 175deda8287SViresh Kumar struct pinctrl_dev *pctl; 176deda8287SViresh Kumar struct spear_pinctrl_machdata *machdata; 177deda8287SViresh Kumar void __iomem *vbase; 178deda8287SViresh Kumar }; 179deda8287SViresh Kumar 180deda8287SViresh Kumar /* exported routines */ 181deda8287SViresh Kumar void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg); 182f4f8e563SViresh Kumar void __devinit 183f4f8e563SViresh Kumar pmx_init_gpio_pingroup_addr(struct spear_gpio_pingroup *gpio_pingroup, 184f4f8e563SViresh Kumar unsigned count, u16 reg); 185deda8287SViresh Kumar int __devinit spear_pinctrl_probe(struct platform_device *pdev, 186deda8287SViresh Kumar struct spear_pinctrl_machdata *machdata); 187deda8287SViresh Kumar int __devexit spear_pinctrl_remove(struct platform_device *pdev); 188d1e77afeSViresh Kumar 189d1e77afeSViresh Kumar #define SPEAR_PIN_0_TO_101 \ 190d1e77afeSViresh Kumar PINCTRL_PIN(0, "PLGPIO0"), \ 191d1e77afeSViresh Kumar PINCTRL_PIN(1, "PLGPIO1"), \ 192d1e77afeSViresh Kumar PINCTRL_PIN(2, "PLGPIO2"), \ 193d1e77afeSViresh Kumar PINCTRL_PIN(3, "PLGPIO3"), \ 194d1e77afeSViresh Kumar PINCTRL_PIN(4, "PLGPIO4"), \ 195d1e77afeSViresh Kumar PINCTRL_PIN(5, "PLGPIO5"), \ 196d1e77afeSViresh Kumar PINCTRL_PIN(6, "PLGPIO6"), \ 197d1e77afeSViresh Kumar PINCTRL_PIN(7, "PLGPIO7"), \ 198d1e77afeSViresh Kumar PINCTRL_PIN(8, "PLGPIO8"), \ 199d1e77afeSViresh Kumar PINCTRL_PIN(9, "PLGPIO9"), \ 200d1e77afeSViresh Kumar PINCTRL_PIN(10, "PLGPIO10"), \ 201d1e77afeSViresh Kumar PINCTRL_PIN(11, "PLGPIO11"), \ 202d1e77afeSViresh Kumar PINCTRL_PIN(12, "PLGPIO12"), \ 203d1e77afeSViresh Kumar PINCTRL_PIN(13, "PLGPIO13"), \ 204d1e77afeSViresh Kumar PINCTRL_PIN(14, "PLGPIO14"), \ 205d1e77afeSViresh Kumar PINCTRL_PIN(15, "PLGPIO15"), \ 206d1e77afeSViresh Kumar PINCTRL_PIN(16, "PLGPIO16"), \ 207d1e77afeSViresh Kumar PINCTRL_PIN(17, "PLGPIO17"), \ 208d1e77afeSViresh Kumar PINCTRL_PIN(18, "PLGPIO18"), \ 209d1e77afeSViresh Kumar PINCTRL_PIN(19, "PLGPIO19"), \ 210d1e77afeSViresh Kumar PINCTRL_PIN(20, "PLGPIO20"), \ 211d1e77afeSViresh Kumar PINCTRL_PIN(21, "PLGPIO21"), \ 212d1e77afeSViresh Kumar PINCTRL_PIN(22, "PLGPIO22"), \ 213d1e77afeSViresh Kumar PINCTRL_PIN(23, "PLGPIO23"), \ 214d1e77afeSViresh Kumar PINCTRL_PIN(24, "PLGPIO24"), \ 215d1e77afeSViresh Kumar PINCTRL_PIN(25, "PLGPIO25"), \ 216d1e77afeSViresh Kumar PINCTRL_PIN(26, "PLGPIO26"), \ 217d1e77afeSViresh Kumar PINCTRL_PIN(27, "PLGPIO27"), \ 218d1e77afeSViresh Kumar PINCTRL_PIN(28, "PLGPIO28"), \ 219d1e77afeSViresh Kumar PINCTRL_PIN(29, "PLGPIO29"), \ 220d1e77afeSViresh Kumar PINCTRL_PIN(30, "PLGPIO30"), \ 221d1e77afeSViresh Kumar PINCTRL_PIN(31, "PLGPIO31"), \ 222d1e77afeSViresh Kumar PINCTRL_PIN(32, "PLGPIO32"), \ 223d1e77afeSViresh Kumar PINCTRL_PIN(33, "PLGPIO33"), \ 224d1e77afeSViresh Kumar PINCTRL_PIN(34, "PLGPIO34"), \ 225d1e77afeSViresh Kumar PINCTRL_PIN(35, "PLGPIO35"), \ 226d1e77afeSViresh Kumar PINCTRL_PIN(36, "PLGPIO36"), \ 227d1e77afeSViresh Kumar PINCTRL_PIN(37, "PLGPIO37"), \ 228d1e77afeSViresh Kumar PINCTRL_PIN(38, "PLGPIO38"), \ 229d1e77afeSViresh Kumar PINCTRL_PIN(39, "PLGPIO39"), \ 230d1e77afeSViresh Kumar PINCTRL_PIN(40, "PLGPIO40"), \ 231d1e77afeSViresh Kumar PINCTRL_PIN(41, "PLGPIO41"), \ 232d1e77afeSViresh Kumar PINCTRL_PIN(42, "PLGPIO42"), \ 233d1e77afeSViresh Kumar PINCTRL_PIN(43, "PLGPIO43"), \ 234d1e77afeSViresh Kumar PINCTRL_PIN(44, "PLGPIO44"), \ 235d1e77afeSViresh Kumar PINCTRL_PIN(45, "PLGPIO45"), \ 236d1e77afeSViresh Kumar PINCTRL_PIN(46, "PLGPIO46"), \ 237d1e77afeSViresh Kumar PINCTRL_PIN(47, "PLGPIO47"), \ 238d1e77afeSViresh Kumar PINCTRL_PIN(48, "PLGPIO48"), \ 239d1e77afeSViresh Kumar PINCTRL_PIN(49, "PLGPIO49"), \ 240d1e77afeSViresh Kumar PINCTRL_PIN(50, "PLGPIO50"), \ 241d1e77afeSViresh Kumar PINCTRL_PIN(51, "PLGPIO51"), \ 242d1e77afeSViresh Kumar PINCTRL_PIN(52, "PLGPIO52"), \ 243d1e77afeSViresh Kumar PINCTRL_PIN(53, "PLGPIO53"), \ 244d1e77afeSViresh Kumar PINCTRL_PIN(54, "PLGPIO54"), \ 245d1e77afeSViresh Kumar PINCTRL_PIN(55, "PLGPIO55"), \ 246d1e77afeSViresh Kumar PINCTRL_PIN(56, "PLGPIO56"), \ 247d1e77afeSViresh Kumar PINCTRL_PIN(57, "PLGPIO57"), \ 248d1e77afeSViresh Kumar PINCTRL_PIN(58, "PLGPIO58"), \ 249d1e77afeSViresh Kumar PINCTRL_PIN(59, "PLGPIO59"), \ 250d1e77afeSViresh Kumar PINCTRL_PIN(60, "PLGPIO60"), \ 251d1e77afeSViresh Kumar PINCTRL_PIN(61, "PLGPIO61"), \ 252d1e77afeSViresh Kumar PINCTRL_PIN(62, "PLGPIO62"), \ 253d1e77afeSViresh Kumar PINCTRL_PIN(63, "PLGPIO63"), \ 254d1e77afeSViresh Kumar PINCTRL_PIN(64, "PLGPIO64"), \ 255d1e77afeSViresh Kumar PINCTRL_PIN(65, "PLGPIO65"), \ 256d1e77afeSViresh Kumar PINCTRL_PIN(66, "PLGPIO66"), \ 257d1e77afeSViresh Kumar PINCTRL_PIN(67, "PLGPIO67"), \ 258d1e77afeSViresh Kumar PINCTRL_PIN(68, "PLGPIO68"), \ 259d1e77afeSViresh Kumar PINCTRL_PIN(69, "PLGPIO69"), \ 260d1e77afeSViresh Kumar PINCTRL_PIN(70, "PLGPIO70"), \ 261d1e77afeSViresh Kumar PINCTRL_PIN(71, "PLGPIO71"), \ 262d1e77afeSViresh Kumar PINCTRL_PIN(72, "PLGPIO72"), \ 263d1e77afeSViresh Kumar PINCTRL_PIN(73, "PLGPIO73"), \ 264d1e77afeSViresh Kumar PINCTRL_PIN(74, "PLGPIO74"), \ 265d1e77afeSViresh Kumar PINCTRL_PIN(75, "PLGPIO75"), \ 266d1e77afeSViresh Kumar PINCTRL_PIN(76, "PLGPIO76"), \ 267d1e77afeSViresh Kumar PINCTRL_PIN(77, "PLGPIO77"), \ 268d1e77afeSViresh Kumar PINCTRL_PIN(78, "PLGPIO78"), \ 269d1e77afeSViresh Kumar PINCTRL_PIN(79, "PLGPIO79"), \ 270d1e77afeSViresh Kumar PINCTRL_PIN(80, "PLGPIO80"), \ 271d1e77afeSViresh Kumar PINCTRL_PIN(81, "PLGPIO81"), \ 272d1e77afeSViresh Kumar PINCTRL_PIN(82, "PLGPIO82"), \ 273d1e77afeSViresh Kumar PINCTRL_PIN(83, "PLGPIO83"), \ 274d1e77afeSViresh Kumar PINCTRL_PIN(84, "PLGPIO84"), \ 275d1e77afeSViresh Kumar PINCTRL_PIN(85, "PLGPIO85"), \ 276d1e77afeSViresh Kumar PINCTRL_PIN(86, "PLGPIO86"), \ 277d1e77afeSViresh Kumar PINCTRL_PIN(87, "PLGPIO87"), \ 278d1e77afeSViresh Kumar PINCTRL_PIN(88, "PLGPIO88"), \ 279d1e77afeSViresh Kumar PINCTRL_PIN(89, "PLGPIO89"), \ 280d1e77afeSViresh Kumar PINCTRL_PIN(90, "PLGPIO90"), \ 281d1e77afeSViresh Kumar PINCTRL_PIN(91, "PLGPIO91"), \ 282d1e77afeSViresh Kumar PINCTRL_PIN(92, "PLGPIO92"), \ 283d1e77afeSViresh Kumar PINCTRL_PIN(93, "PLGPIO93"), \ 284d1e77afeSViresh Kumar PINCTRL_PIN(94, "PLGPIO94"), \ 285d1e77afeSViresh Kumar PINCTRL_PIN(95, "PLGPIO95"), \ 286d1e77afeSViresh Kumar PINCTRL_PIN(96, "PLGPIO96"), \ 287d1e77afeSViresh Kumar PINCTRL_PIN(97, "PLGPIO97"), \ 288d1e77afeSViresh Kumar PINCTRL_PIN(98, "PLGPIO98"), \ 289d1e77afeSViresh Kumar PINCTRL_PIN(99, "PLGPIO99"), \ 290d1e77afeSViresh Kumar PINCTRL_PIN(100, "PLGPIO100"), \ 291d1e77afeSViresh Kumar PINCTRL_PIN(101, "PLGPIO101") 292d1e77afeSViresh Kumar 29385ed41a7SViresh Kumar #define SPEAR_PIN_102_TO_245 \ 29485ed41a7SViresh Kumar PINCTRL_PIN(102, "PLGPIO102"), \ 29585ed41a7SViresh Kumar PINCTRL_PIN(103, "PLGPIO103"), \ 29685ed41a7SViresh Kumar PINCTRL_PIN(104, "PLGPIO104"), \ 29785ed41a7SViresh Kumar PINCTRL_PIN(105, "PLGPIO105"), \ 29885ed41a7SViresh Kumar PINCTRL_PIN(106, "PLGPIO106"), \ 29985ed41a7SViresh Kumar PINCTRL_PIN(107, "PLGPIO107"), \ 30085ed41a7SViresh Kumar PINCTRL_PIN(108, "PLGPIO108"), \ 30185ed41a7SViresh Kumar PINCTRL_PIN(109, "PLGPIO109"), \ 30285ed41a7SViresh Kumar PINCTRL_PIN(110, "PLGPIO110"), \ 30385ed41a7SViresh Kumar PINCTRL_PIN(111, "PLGPIO111"), \ 30485ed41a7SViresh Kumar PINCTRL_PIN(112, "PLGPIO112"), \ 30585ed41a7SViresh Kumar PINCTRL_PIN(113, "PLGPIO113"), \ 30685ed41a7SViresh Kumar PINCTRL_PIN(114, "PLGPIO114"), \ 30785ed41a7SViresh Kumar PINCTRL_PIN(115, "PLGPIO115"), \ 30885ed41a7SViresh Kumar PINCTRL_PIN(116, "PLGPIO116"), \ 30985ed41a7SViresh Kumar PINCTRL_PIN(117, "PLGPIO117"), \ 31085ed41a7SViresh Kumar PINCTRL_PIN(118, "PLGPIO118"), \ 31185ed41a7SViresh Kumar PINCTRL_PIN(119, "PLGPIO119"), \ 31285ed41a7SViresh Kumar PINCTRL_PIN(120, "PLGPIO120"), \ 31385ed41a7SViresh Kumar PINCTRL_PIN(121, "PLGPIO121"), \ 31485ed41a7SViresh Kumar PINCTRL_PIN(122, "PLGPIO122"), \ 31585ed41a7SViresh Kumar PINCTRL_PIN(123, "PLGPIO123"), \ 31685ed41a7SViresh Kumar PINCTRL_PIN(124, "PLGPIO124"), \ 31785ed41a7SViresh Kumar PINCTRL_PIN(125, "PLGPIO125"), \ 31885ed41a7SViresh Kumar PINCTRL_PIN(126, "PLGPIO126"), \ 31985ed41a7SViresh Kumar PINCTRL_PIN(127, "PLGPIO127"), \ 32085ed41a7SViresh Kumar PINCTRL_PIN(128, "PLGPIO128"), \ 32185ed41a7SViresh Kumar PINCTRL_PIN(129, "PLGPIO129"), \ 32285ed41a7SViresh Kumar PINCTRL_PIN(130, "PLGPIO130"), \ 32385ed41a7SViresh Kumar PINCTRL_PIN(131, "PLGPIO131"), \ 32485ed41a7SViresh Kumar PINCTRL_PIN(132, "PLGPIO132"), \ 32585ed41a7SViresh Kumar PINCTRL_PIN(133, "PLGPIO133"), \ 32685ed41a7SViresh Kumar PINCTRL_PIN(134, "PLGPIO134"), \ 32785ed41a7SViresh Kumar PINCTRL_PIN(135, "PLGPIO135"), \ 32885ed41a7SViresh Kumar PINCTRL_PIN(136, "PLGPIO136"), \ 32985ed41a7SViresh Kumar PINCTRL_PIN(137, "PLGPIO137"), \ 33085ed41a7SViresh Kumar PINCTRL_PIN(138, "PLGPIO138"), \ 33185ed41a7SViresh Kumar PINCTRL_PIN(139, "PLGPIO139"), \ 33285ed41a7SViresh Kumar PINCTRL_PIN(140, "PLGPIO140"), \ 33385ed41a7SViresh Kumar PINCTRL_PIN(141, "PLGPIO141"), \ 33485ed41a7SViresh Kumar PINCTRL_PIN(142, "PLGPIO142"), \ 33585ed41a7SViresh Kumar PINCTRL_PIN(143, "PLGPIO143"), \ 33685ed41a7SViresh Kumar PINCTRL_PIN(144, "PLGPIO144"), \ 33785ed41a7SViresh Kumar PINCTRL_PIN(145, "PLGPIO145"), \ 33885ed41a7SViresh Kumar PINCTRL_PIN(146, "PLGPIO146"), \ 33985ed41a7SViresh Kumar PINCTRL_PIN(147, "PLGPIO147"), \ 34085ed41a7SViresh Kumar PINCTRL_PIN(148, "PLGPIO148"), \ 34185ed41a7SViresh Kumar PINCTRL_PIN(149, "PLGPIO149"), \ 34285ed41a7SViresh Kumar PINCTRL_PIN(150, "PLGPIO150"), \ 34385ed41a7SViresh Kumar PINCTRL_PIN(151, "PLGPIO151"), \ 34485ed41a7SViresh Kumar PINCTRL_PIN(152, "PLGPIO152"), \ 34585ed41a7SViresh Kumar PINCTRL_PIN(153, "PLGPIO153"), \ 34685ed41a7SViresh Kumar PINCTRL_PIN(154, "PLGPIO154"), \ 34785ed41a7SViresh Kumar PINCTRL_PIN(155, "PLGPIO155"), \ 34885ed41a7SViresh Kumar PINCTRL_PIN(156, "PLGPIO156"), \ 34985ed41a7SViresh Kumar PINCTRL_PIN(157, "PLGPIO157"), \ 35085ed41a7SViresh Kumar PINCTRL_PIN(158, "PLGPIO158"), \ 35185ed41a7SViresh Kumar PINCTRL_PIN(159, "PLGPIO159"), \ 35285ed41a7SViresh Kumar PINCTRL_PIN(160, "PLGPIO160"), \ 35385ed41a7SViresh Kumar PINCTRL_PIN(161, "PLGPIO161"), \ 35485ed41a7SViresh Kumar PINCTRL_PIN(162, "PLGPIO162"), \ 35585ed41a7SViresh Kumar PINCTRL_PIN(163, "PLGPIO163"), \ 35685ed41a7SViresh Kumar PINCTRL_PIN(164, "PLGPIO164"), \ 35785ed41a7SViresh Kumar PINCTRL_PIN(165, "PLGPIO165"), \ 35885ed41a7SViresh Kumar PINCTRL_PIN(166, "PLGPIO166"), \ 35985ed41a7SViresh Kumar PINCTRL_PIN(167, "PLGPIO167"), \ 36085ed41a7SViresh Kumar PINCTRL_PIN(168, "PLGPIO168"), \ 36185ed41a7SViresh Kumar PINCTRL_PIN(169, "PLGPIO169"), \ 36285ed41a7SViresh Kumar PINCTRL_PIN(170, "PLGPIO170"), \ 36385ed41a7SViresh Kumar PINCTRL_PIN(171, "PLGPIO171"), \ 36485ed41a7SViresh Kumar PINCTRL_PIN(172, "PLGPIO172"), \ 36585ed41a7SViresh Kumar PINCTRL_PIN(173, "PLGPIO173"), \ 36685ed41a7SViresh Kumar PINCTRL_PIN(174, "PLGPIO174"), \ 36785ed41a7SViresh Kumar PINCTRL_PIN(175, "PLGPIO175"), \ 36885ed41a7SViresh Kumar PINCTRL_PIN(176, "PLGPIO176"), \ 36985ed41a7SViresh Kumar PINCTRL_PIN(177, "PLGPIO177"), \ 37085ed41a7SViresh Kumar PINCTRL_PIN(178, "PLGPIO178"), \ 37185ed41a7SViresh Kumar PINCTRL_PIN(179, "PLGPIO179"), \ 37285ed41a7SViresh Kumar PINCTRL_PIN(180, "PLGPIO180"), \ 37385ed41a7SViresh Kumar PINCTRL_PIN(181, "PLGPIO181"), \ 37485ed41a7SViresh Kumar PINCTRL_PIN(182, "PLGPIO182"), \ 37585ed41a7SViresh Kumar PINCTRL_PIN(183, "PLGPIO183"), \ 37685ed41a7SViresh Kumar PINCTRL_PIN(184, "PLGPIO184"), \ 37785ed41a7SViresh Kumar PINCTRL_PIN(185, "PLGPIO185"), \ 37885ed41a7SViresh Kumar PINCTRL_PIN(186, "PLGPIO186"), \ 37985ed41a7SViresh Kumar PINCTRL_PIN(187, "PLGPIO187"), \ 38085ed41a7SViresh Kumar PINCTRL_PIN(188, "PLGPIO188"), \ 38185ed41a7SViresh Kumar PINCTRL_PIN(189, "PLGPIO189"), \ 38285ed41a7SViresh Kumar PINCTRL_PIN(190, "PLGPIO190"), \ 38385ed41a7SViresh Kumar PINCTRL_PIN(191, "PLGPIO191"), \ 38485ed41a7SViresh Kumar PINCTRL_PIN(192, "PLGPIO192"), \ 38585ed41a7SViresh Kumar PINCTRL_PIN(193, "PLGPIO193"), \ 38685ed41a7SViresh Kumar PINCTRL_PIN(194, "PLGPIO194"), \ 38785ed41a7SViresh Kumar PINCTRL_PIN(195, "PLGPIO195"), \ 38885ed41a7SViresh Kumar PINCTRL_PIN(196, "PLGPIO196"), \ 38985ed41a7SViresh Kumar PINCTRL_PIN(197, "PLGPIO197"), \ 39085ed41a7SViresh Kumar PINCTRL_PIN(198, "PLGPIO198"), \ 39185ed41a7SViresh Kumar PINCTRL_PIN(199, "PLGPIO199"), \ 39285ed41a7SViresh Kumar PINCTRL_PIN(200, "PLGPIO200"), \ 39385ed41a7SViresh Kumar PINCTRL_PIN(201, "PLGPIO201"), \ 39485ed41a7SViresh Kumar PINCTRL_PIN(202, "PLGPIO202"), \ 39585ed41a7SViresh Kumar PINCTRL_PIN(203, "PLGPIO203"), \ 39685ed41a7SViresh Kumar PINCTRL_PIN(204, "PLGPIO204"), \ 39785ed41a7SViresh Kumar PINCTRL_PIN(205, "PLGPIO205"), \ 39885ed41a7SViresh Kumar PINCTRL_PIN(206, "PLGPIO206"), \ 39985ed41a7SViresh Kumar PINCTRL_PIN(207, "PLGPIO207"), \ 40085ed41a7SViresh Kumar PINCTRL_PIN(208, "PLGPIO208"), \ 40185ed41a7SViresh Kumar PINCTRL_PIN(209, "PLGPIO209"), \ 40285ed41a7SViresh Kumar PINCTRL_PIN(210, "PLGPIO210"), \ 40385ed41a7SViresh Kumar PINCTRL_PIN(211, "PLGPIO211"), \ 40485ed41a7SViresh Kumar PINCTRL_PIN(212, "PLGPIO212"), \ 40585ed41a7SViresh Kumar PINCTRL_PIN(213, "PLGPIO213"), \ 40685ed41a7SViresh Kumar PINCTRL_PIN(214, "PLGPIO214"), \ 40785ed41a7SViresh Kumar PINCTRL_PIN(215, "PLGPIO215"), \ 40885ed41a7SViresh Kumar PINCTRL_PIN(216, "PLGPIO216"), \ 40985ed41a7SViresh Kumar PINCTRL_PIN(217, "PLGPIO217"), \ 41085ed41a7SViresh Kumar PINCTRL_PIN(218, "PLGPIO218"), \ 41185ed41a7SViresh Kumar PINCTRL_PIN(219, "PLGPIO219"), \ 41285ed41a7SViresh Kumar PINCTRL_PIN(220, "PLGPIO220"), \ 41385ed41a7SViresh Kumar PINCTRL_PIN(221, "PLGPIO221"), \ 41485ed41a7SViresh Kumar PINCTRL_PIN(222, "PLGPIO222"), \ 41585ed41a7SViresh Kumar PINCTRL_PIN(223, "PLGPIO223"), \ 41685ed41a7SViresh Kumar PINCTRL_PIN(224, "PLGPIO224"), \ 41785ed41a7SViresh Kumar PINCTRL_PIN(225, "PLGPIO225"), \ 41885ed41a7SViresh Kumar PINCTRL_PIN(226, "PLGPIO226"), \ 41985ed41a7SViresh Kumar PINCTRL_PIN(227, "PLGPIO227"), \ 42085ed41a7SViresh Kumar PINCTRL_PIN(228, "PLGPIO228"), \ 42185ed41a7SViresh Kumar PINCTRL_PIN(229, "PLGPIO229"), \ 42285ed41a7SViresh Kumar PINCTRL_PIN(230, "PLGPIO230"), \ 42385ed41a7SViresh Kumar PINCTRL_PIN(231, "PLGPIO231"), \ 42485ed41a7SViresh Kumar PINCTRL_PIN(232, "PLGPIO232"), \ 42585ed41a7SViresh Kumar PINCTRL_PIN(233, "PLGPIO233"), \ 42685ed41a7SViresh Kumar PINCTRL_PIN(234, "PLGPIO234"), \ 42785ed41a7SViresh Kumar PINCTRL_PIN(235, "PLGPIO235"), \ 42885ed41a7SViresh Kumar PINCTRL_PIN(236, "PLGPIO236"), \ 42985ed41a7SViresh Kumar PINCTRL_PIN(237, "PLGPIO237"), \ 43085ed41a7SViresh Kumar PINCTRL_PIN(238, "PLGPIO238"), \ 43185ed41a7SViresh Kumar PINCTRL_PIN(239, "PLGPIO239"), \ 43285ed41a7SViresh Kumar PINCTRL_PIN(240, "PLGPIO240"), \ 43385ed41a7SViresh Kumar PINCTRL_PIN(241, "PLGPIO241"), \ 43485ed41a7SViresh Kumar PINCTRL_PIN(242, "PLGPIO242"), \ 43585ed41a7SViresh Kumar PINCTRL_PIN(243, "PLGPIO243"), \ 43685ed41a7SViresh Kumar PINCTRL_PIN(244, "PLGPIO244"), \ 43785ed41a7SViresh Kumar PINCTRL_PIN(245, "PLGPIO245") 43885ed41a7SViresh Kumar 439deda8287SViresh Kumar #endif /* __PINMUX_SPEAR_H__ */ 440