1deda8287SViresh Kumar /*
2deda8287SViresh Kumar  * Driver header file for the ST Microelectronics SPEAr pinmux
3deda8287SViresh Kumar  *
4deda8287SViresh Kumar  * Copyright (C) 2012 ST Microelectronics
5deda8287SViresh Kumar  * Viresh Kumar <viresh.kumar@st.com>
6deda8287SViresh Kumar  *
7deda8287SViresh Kumar  * This file is licensed under the terms of the GNU General Public
8deda8287SViresh Kumar  * License version 2. This program is licensed "as is" without any
9deda8287SViresh Kumar  * warranty of any kind, whether express or implied.
10deda8287SViresh Kumar  */
11deda8287SViresh Kumar 
12deda8287SViresh Kumar #ifndef __PINMUX_SPEAR_H__
13deda8287SViresh Kumar #define __PINMUX_SPEAR_H__
14deda8287SViresh Kumar 
15deda8287SViresh Kumar #include <linux/pinctrl/pinctrl.h>
16deda8287SViresh Kumar #include <linux/types.h>
17deda8287SViresh Kumar 
18deda8287SViresh Kumar struct platform_device;
19deda8287SViresh Kumar struct device;
20deda8287SViresh Kumar 
21deda8287SViresh Kumar /**
22deda8287SViresh Kumar  * struct spear_pmx_mode - SPEAr pmx mode
23deda8287SViresh Kumar  * @name: name of pmx mode
24deda8287SViresh Kumar  * @mode: mode id
25deda8287SViresh Kumar  * @reg: register for configuring this mode
26deda8287SViresh Kumar  * @mask: mask of this mode in reg
27deda8287SViresh Kumar  * @val: val to be configured at reg after doing (val & mask)
28deda8287SViresh Kumar  */
29deda8287SViresh Kumar struct spear_pmx_mode {
30deda8287SViresh Kumar 	const char *const name;
31deda8287SViresh Kumar 	u16 mode;
32deda8287SViresh Kumar 	u16 reg;
33deda8287SViresh Kumar 	u16 mask;
34deda8287SViresh Kumar 	u32 val;
35deda8287SViresh Kumar };
36deda8287SViresh Kumar 
37deda8287SViresh Kumar /**
38deda8287SViresh Kumar  * struct spear_muxreg - SPEAr mux reg configuration
39deda8287SViresh Kumar  * @reg: register offset
40deda8287SViresh Kumar  * @mask: mask bits
41deda8287SViresh Kumar  * @val: val to be written on mask bits
42deda8287SViresh Kumar  */
43deda8287SViresh Kumar struct spear_muxreg {
44deda8287SViresh Kumar 	u16 reg;
45deda8287SViresh Kumar 	u32 mask;
46deda8287SViresh Kumar 	u32 val;
47deda8287SViresh Kumar };
48deda8287SViresh Kumar 
49deda8287SViresh Kumar /**
50deda8287SViresh Kumar  * struct spear_modemux - SPEAr mode mux configuration
51deda8287SViresh Kumar  * @modes: mode ids supported by this group of muxregs
52deda8287SViresh Kumar  * @nmuxregs: number of muxreg configurations to be done for modes
53deda8287SViresh Kumar  * @muxregs: array of muxreg configurations to be done for modes
54deda8287SViresh Kumar  */
55deda8287SViresh Kumar struct spear_modemux {
56deda8287SViresh Kumar 	u16 modes;
57deda8287SViresh Kumar 	u8 nmuxregs;
58deda8287SViresh Kumar 	struct spear_muxreg *muxregs;
59deda8287SViresh Kumar };
60deda8287SViresh Kumar 
61deda8287SViresh Kumar /**
62deda8287SViresh Kumar  * struct spear_pingroup - SPEAr pin group configurations
63deda8287SViresh Kumar  * @name: name of pin group
64deda8287SViresh Kumar  * @pins: array containing pin numbers
65deda8287SViresh Kumar  * @npins: size of pins array
66deda8287SViresh Kumar  * @modemuxs: array of modemux configurations for this pin group
67deda8287SViresh Kumar  * @nmodemuxs: size of array modemuxs
68deda8287SViresh Kumar  *
69deda8287SViresh Kumar  * A representation of a group of pins in the SPEAr pin controller. Each group
70deda8287SViresh Kumar  * allows some parameter or parameters to be configured.
71deda8287SViresh Kumar  */
72deda8287SViresh Kumar struct spear_pingroup {
73deda8287SViresh Kumar 	const char *name;
74deda8287SViresh Kumar 	const unsigned *pins;
75deda8287SViresh Kumar 	unsigned npins;
76deda8287SViresh Kumar 	struct spear_modemux *modemuxs;
77deda8287SViresh Kumar 	unsigned nmodemuxs;
78deda8287SViresh Kumar };
79deda8287SViresh Kumar 
80deda8287SViresh Kumar /**
81deda8287SViresh Kumar  * struct spear_function - SPEAr pinctrl mux function
82deda8287SViresh Kumar  * @name: The name of the function, exported to pinctrl core.
83deda8287SViresh Kumar  * @groups: An array of pin groups that may select this function.
84deda8287SViresh Kumar  * @ngroups: The number of entries in @groups.
85deda8287SViresh Kumar  */
86deda8287SViresh Kumar struct spear_function {
87deda8287SViresh Kumar 	const char *name;
88deda8287SViresh Kumar 	const char *const *groups;
89deda8287SViresh Kumar 	unsigned ngroups;
90deda8287SViresh Kumar };
91deda8287SViresh Kumar 
92deda8287SViresh Kumar /**
93deda8287SViresh Kumar  * struct spear_pinctrl_machdata - SPEAr pin controller machine driver
94deda8287SViresh Kumar  *	configuration
95deda8287SViresh Kumar  * @pins: An array describing all pins the pin controller affects.
96deda8287SViresh Kumar  *	All pins which are also GPIOs must be listed first within the *array,
97deda8287SViresh Kumar  *	and be numbered identically to the GPIO controller's *numbering.
98deda8287SViresh Kumar  * @npins: The numbmer of entries in @pins.
99deda8287SViresh Kumar  * @functions: An array describing all mux functions the SoC supports.
100deda8287SViresh Kumar  * @nfunctions: The numbmer of entries in @functions.
101deda8287SViresh Kumar  * @groups: An array describing all pin groups the pin SoC supports.
102deda8287SViresh Kumar  * @ngroups: The numbmer of entries in @groups.
103deda8287SViresh Kumar  *
104deda8287SViresh Kumar  * @modes_supported: Does SoC support modes
105deda8287SViresh Kumar  * @mode: mode configured from probe
106deda8287SViresh Kumar  * @pmx_modes: array of modes supported by SoC
107deda8287SViresh Kumar  * @npmx_modes: number of entries in pmx_modes.
108deda8287SViresh Kumar  */
109deda8287SViresh Kumar struct spear_pinctrl_machdata {
110deda8287SViresh Kumar 	const struct pinctrl_pin_desc *pins;
111deda8287SViresh Kumar 	unsigned npins;
112deda8287SViresh Kumar 	struct spear_function **functions;
113deda8287SViresh Kumar 	unsigned nfunctions;
114deda8287SViresh Kumar 	struct spear_pingroup **groups;
115deda8287SViresh Kumar 	unsigned ngroups;
116deda8287SViresh Kumar 
117deda8287SViresh Kumar 	bool modes_supported;
118deda8287SViresh Kumar 	u16 mode;
119deda8287SViresh Kumar 	struct spear_pmx_mode **pmx_modes;
120deda8287SViresh Kumar 	unsigned npmx_modes;
121deda8287SViresh Kumar };
122deda8287SViresh Kumar 
123deda8287SViresh Kumar /**
124deda8287SViresh Kumar  * struct spear_pmx - SPEAr pinctrl mux
125deda8287SViresh Kumar  * @dev: pointer to struct dev of platform_device registered
126deda8287SViresh Kumar  * @pctl: pointer to struct pinctrl_dev
127deda8287SViresh Kumar  * @machdata: pointer to SoC or machine specific structure
128deda8287SViresh Kumar  * @vbase: virtual base address of pinmux controller
129deda8287SViresh Kumar  */
130deda8287SViresh Kumar struct spear_pmx {
131deda8287SViresh Kumar 	struct device *dev;
132deda8287SViresh Kumar 	struct pinctrl_dev *pctl;
133deda8287SViresh Kumar 	struct spear_pinctrl_machdata *machdata;
134deda8287SViresh Kumar 	void __iomem *vbase;
135deda8287SViresh Kumar };
136deda8287SViresh Kumar 
137deda8287SViresh Kumar /* exported routines */
138deda8287SViresh Kumar void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg);
139deda8287SViresh Kumar int __devinit spear_pinctrl_probe(struct platform_device *pdev,
140deda8287SViresh Kumar 		struct spear_pinctrl_machdata *machdata);
141deda8287SViresh Kumar int __devexit spear_pinctrl_remove(struct platform_device *pdev);
142d1e77afeSViresh Kumar 
143d1e77afeSViresh Kumar #define SPEAR_PIN_0_TO_101		\
144d1e77afeSViresh Kumar 	PINCTRL_PIN(0, "PLGPIO0"),	\
145d1e77afeSViresh Kumar 	PINCTRL_PIN(1, "PLGPIO1"),	\
146d1e77afeSViresh Kumar 	PINCTRL_PIN(2, "PLGPIO2"),	\
147d1e77afeSViresh Kumar 	PINCTRL_PIN(3, "PLGPIO3"),	\
148d1e77afeSViresh Kumar 	PINCTRL_PIN(4, "PLGPIO4"),	\
149d1e77afeSViresh Kumar 	PINCTRL_PIN(5, "PLGPIO5"),	\
150d1e77afeSViresh Kumar 	PINCTRL_PIN(6, "PLGPIO6"),	\
151d1e77afeSViresh Kumar 	PINCTRL_PIN(7, "PLGPIO7"),	\
152d1e77afeSViresh Kumar 	PINCTRL_PIN(8, "PLGPIO8"),	\
153d1e77afeSViresh Kumar 	PINCTRL_PIN(9, "PLGPIO9"),	\
154d1e77afeSViresh Kumar 	PINCTRL_PIN(10, "PLGPIO10"),	\
155d1e77afeSViresh Kumar 	PINCTRL_PIN(11, "PLGPIO11"),	\
156d1e77afeSViresh Kumar 	PINCTRL_PIN(12, "PLGPIO12"),	\
157d1e77afeSViresh Kumar 	PINCTRL_PIN(13, "PLGPIO13"),	\
158d1e77afeSViresh Kumar 	PINCTRL_PIN(14, "PLGPIO14"),	\
159d1e77afeSViresh Kumar 	PINCTRL_PIN(15, "PLGPIO15"),	\
160d1e77afeSViresh Kumar 	PINCTRL_PIN(16, "PLGPIO16"),	\
161d1e77afeSViresh Kumar 	PINCTRL_PIN(17, "PLGPIO17"),	\
162d1e77afeSViresh Kumar 	PINCTRL_PIN(18, "PLGPIO18"),	\
163d1e77afeSViresh Kumar 	PINCTRL_PIN(19, "PLGPIO19"),	\
164d1e77afeSViresh Kumar 	PINCTRL_PIN(20, "PLGPIO20"),	\
165d1e77afeSViresh Kumar 	PINCTRL_PIN(21, "PLGPIO21"),	\
166d1e77afeSViresh Kumar 	PINCTRL_PIN(22, "PLGPIO22"),	\
167d1e77afeSViresh Kumar 	PINCTRL_PIN(23, "PLGPIO23"),	\
168d1e77afeSViresh Kumar 	PINCTRL_PIN(24, "PLGPIO24"),	\
169d1e77afeSViresh Kumar 	PINCTRL_PIN(25, "PLGPIO25"),	\
170d1e77afeSViresh Kumar 	PINCTRL_PIN(26, "PLGPIO26"),	\
171d1e77afeSViresh Kumar 	PINCTRL_PIN(27, "PLGPIO27"),	\
172d1e77afeSViresh Kumar 	PINCTRL_PIN(28, "PLGPIO28"),	\
173d1e77afeSViresh Kumar 	PINCTRL_PIN(29, "PLGPIO29"),	\
174d1e77afeSViresh Kumar 	PINCTRL_PIN(30, "PLGPIO30"),	\
175d1e77afeSViresh Kumar 	PINCTRL_PIN(31, "PLGPIO31"),	\
176d1e77afeSViresh Kumar 	PINCTRL_PIN(32, "PLGPIO32"),	\
177d1e77afeSViresh Kumar 	PINCTRL_PIN(33, "PLGPIO33"),	\
178d1e77afeSViresh Kumar 	PINCTRL_PIN(34, "PLGPIO34"),	\
179d1e77afeSViresh Kumar 	PINCTRL_PIN(35, "PLGPIO35"),	\
180d1e77afeSViresh Kumar 	PINCTRL_PIN(36, "PLGPIO36"),	\
181d1e77afeSViresh Kumar 	PINCTRL_PIN(37, "PLGPIO37"),	\
182d1e77afeSViresh Kumar 	PINCTRL_PIN(38, "PLGPIO38"),	\
183d1e77afeSViresh Kumar 	PINCTRL_PIN(39, "PLGPIO39"),	\
184d1e77afeSViresh Kumar 	PINCTRL_PIN(40, "PLGPIO40"),	\
185d1e77afeSViresh Kumar 	PINCTRL_PIN(41, "PLGPIO41"),	\
186d1e77afeSViresh Kumar 	PINCTRL_PIN(42, "PLGPIO42"),	\
187d1e77afeSViresh Kumar 	PINCTRL_PIN(43, "PLGPIO43"),	\
188d1e77afeSViresh Kumar 	PINCTRL_PIN(44, "PLGPIO44"),	\
189d1e77afeSViresh Kumar 	PINCTRL_PIN(45, "PLGPIO45"),	\
190d1e77afeSViresh Kumar 	PINCTRL_PIN(46, "PLGPIO46"),	\
191d1e77afeSViresh Kumar 	PINCTRL_PIN(47, "PLGPIO47"),	\
192d1e77afeSViresh Kumar 	PINCTRL_PIN(48, "PLGPIO48"),	\
193d1e77afeSViresh Kumar 	PINCTRL_PIN(49, "PLGPIO49"),	\
194d1e77afeSViresh Kumar 	PINCTRL_PIN(50, "PLGPIO50"),	\
195d1e77afeSViresh Kumar 	PINCTRL_PIN(51, "PLGPIO51"),	\
196d1e77afeSViresh Kumar 	PINCTRL_PIN(52, "PLGPIO52"),	\
197d1e77afeSViresh Kumar 	PINCTRL_PIN(53, "PLGPIO53"),	\
198d1e77afeSViresh Kumar 	PINCTRL_PIN(54, "PLGPIO54"),	\
199d1e77afeSViresh Kumar 	PINCTRL_PIN(55, "PLGPIO55"),	\
200d1e77afeSViresh Kumar 	PINCTRL_PIN(56, "PLGPIO56"),	\
201d1e77afeSViresh Kumar 	PINCTRL_PIN(57, "PLGPIO57"),	\
202d1e77afeSViresh Kumar 	PINCTRL_PIN(58, "PLGPIO58"),	\
203d1e77afeSViresh Kumar 	PINCTRL_PIN(59, "PLGPIO59"),	\
204d1e77afeSViresh Kumar 	PINCTRL_PIN(60, "PLGPIO60"),	\
205d1e77afeSViresh Kumar 	PINCTRL_PIN(61, "PLGPIO61"),	\
206d1e77afeSViresh Kumar 	PINCTRL_PIN(62, "PLGPIO62"),	\
207d1e77afeSViresh Kumar 	PINCTRL_PIN(63, "PLGPIO63"),	\
208d1e77afeSViresh Kumar 	PINCTRL_PIN(64, "PLGPIO64"),	\
209d1e77afeSViresh Kumar 	PINCTRL_PIN(65, "PLGPIO65"),	\
210d1e77afeSViresh Kumar 	PINCTRL_PIN(66, "PLGPIO66"),	\
211d1e77afeSViresh Kumar 	PINCTRL_PIN(67, "PLGPIO67"),	\
212d1e77afeSViresh Kumar 	PINCTRL_PIN(68, "PLGPIO68"),	\
213d1e77afeSViresh Kumar 	PINCTRL_PIN(69, "PLGPIO69"),	\
214d1e77afeSViresh Kumar 	PINCTRL_PIN(70, "PLGPIO70"),	\
215d1e77afeSViresh Kumar 	PINCTRL_PIN(71, "PLGPIO71"),	\
216d1e77afeSViresh Kumar 	PINCTRL_PIN(72, "PLGPIO72"),	\
217d1e77afeSViresh Kumar 	PINCTRL_PIN(73, "PLGPIO73"),	\
218d1e77afeSViresh Kumar 	PINCTRL_PIN(74, "PLGPIO74"),	\
219d1e77afeSViresh Kumar 	PINCTRL_PIN(75, "PLGPIO75"),	\
220d1e77afeSViresh Kumar 	PINCTRL_PIN(76, "PLGPIO76"),	\
221d1e77afeSViresh Kumar 	PINCTRL_PIN(77, "PLGPIO77"),	\
222d1e77afeSViresh Kumar 	PINCTRL_PIN(78, "PLGPIO78"),	\
223d1e77afeSViresh Kumar 	PINCTRL_PIN(79, "PLGPIO79"),	\
224d1e77afeSViresh Kumar 	PINCTRL_PIN(80, "PLGPIO80"),	\
225d1e77afeSViresh Kumar 	PINCTRL_PIN(81, "PLGPIO81"),	\
226d1e77afeSViresh Kumar 	PINCTRL_PIN(82, "PLGPIO82"),	\
227d1e77afeSViresh Kumar 	PINCTRL_PIN(83, "PLGPIO83"),	\
228d1e77afeSViresh Kumar 	PINCTRL_PIN(84, "PLGPIO84"),	\
229d1e77afeSViresh Kumar 	PINCTRL_PIN(85, "PLGPIO85"),	\
230d1e77afeSViresh Kumar 	PINCTRL_PIN(86, "PLGPIO86"),	\
231d1e77afeSViresh Kumar 	PINCTRL_PIN(87, "PLGPIO87"),	\
232d1e77afeSViresh Kumar 	PINCTRL_PIN(88, "PLGPIO88"),	\
233d1e77afeSViresh Kumar 	PINCTRL_PIN(89, "PLGPIO89"),	\
234d1e77afeSViresh Kumar 	PINCTRL_PIN(90, "PLGPIO90"),	\
235d1e77afeSViresh Kumar 	PINCTRL_PIN(91, "PLGPIO91"),	\
236d1e77afeSViresh Kumar 	PINCTRL_PIN(92, "PLGPIO92"),	\
237d1e77afeSViresh Kumar 	PINCTRL_PIN(93, "PLGPIO93"),	\
238d1e77afeSViresh Kumar 	PINCTRL_PIN(94, "PLGPIO94"),	\
239d1e77afeSViresh Kumar 	PINCTRL_PIN(95, "PLGPIO95"),	\
240d1e77afeSViresh Kumar 	PINCTRL_PIN(96, "PLGPIO96"),	\
241d1e77afeSViresh Kumar 	PINCTRL_PIN(97, "PLGPIO97"),	\
242d1e77afeSViresh Kumar 	PINCTRL_PIN(98, "PLGPIO98"),	\
243d1e77afeSViresh Kumar 	PINCTRL_PIN(99, "PLGPIO99"),	\
244d1e77afeSViresh Kumar 	PINCTRL_PIN(100, "PLGPIO100"),	\
245d1e77afeSViresh Kumar 	PINCTRL_PIN(101, "PLGPIO101")
246d1e77afeSViresh Kumar 
24785ed41a7SViresh Kumar #define SPEAR_PIN_102_TO_245		\
24885ed41a7SViresh Kumar 	PINCTRL_PIN(102, "PLGPIO102"),	\
24985ed41a7SViresh Kumar 	PINCTRL_PIN(103, "PLGPIO103"),	\
25085ed41a7SViresh Kumar 	PINCTRL_PIN(104, "PLGPIO104"),	\
25185ed41a7SViresh Kumar 	PINCTRL_PIN(105, "PLGPIO105"),	\
25285ed41a7SViresh Kumar 	PINCTRL_PIN(106, "PLGPIO106"),	\
25385ed41a7SViresh Kumar 	PINCTRL_PIN(107, "PLGPIO107"),	\
25485ed41a7SViresh Kumar 	PINCTRL_PIN(108, "PLGPIO108"),	\
25585ed41a7SViresh Kumar 	PINCTRL_PIN(109, "PLGPIO109"),	\
25685ed41a7SViresh Kumar 	PINCTRL_PIN(110, "PLGPIO110"),	\
25785ed41a7SViresh Kumar 	PINCTRL_PIN(111, "PLGPIO111"),	\
25885ed41a7SViresh Kumar 	PINCTRL_PIN(112, "PLGPIO112"),	\
25985ed41a7SViresh Kumar 	PINCTRL_PIN(113, "PLGPIO113"),	\
26085ed41a7SViresh Kumar 	PINCTRL_PIN(114, "PLGPIO114"),	\
26185ed41a7SViresh Kumar 	PINCTRL_PIN(115, "PLGPIO115"),	\
26285ed41a7SViresh Kumar 	PINCTRL_PIN(116, "PLGPIO116"),	\
26385ed41a7SViresh Kumar 	PINCTRL_PIN(117, "PLGPIO117"),	\
26485ed41a7SViresh Kumar 	PINCTRL_PIN(118, "PLGPIO118"),	\
26585ed41a7SViresh Kumar 	PINCTRL_PIN(119, "PLGPIO119"),	\
26685ed41a7SViresh Kumar 	PINCTRL_PIN(120, "PLGPIO120"),	\
26785ed41a7SViresh Kumar 	PINCTRL_PIN(121, "PLGPIO121"),	\
26885ed41a7SViresh Kumar 	PINCTRL_PIN(122, "PLGPIO122"),	\
26985ed41a7SViresh Kumar 	PINCTRL_PIN(123, "PLGPIO123"),	\
27085ed41a7SViresh Kumar 	PINCTRL_PIN(124, "PLGPIO124"),	\
27185ed41a7SViresh Kumar 	PINCTRL_PIN(125, "PLGPIO125"),	\
27285ed41a7SViresh Kumar 	PINCTRL_PIN(126, "PLGPIO126"),	\
27385ed41a7SViresh Kumar 	PINCTRL_PIN(127, "PLGPIO127"),	\
27485ed41a7SViresh Kumar 	PINCTRL_PIN(128, "PLGPIO128"),	\
27585ed41a7SViresh Kumar 	PINCTRL_PIN(129, "PLGPIO129"),	\
27685ed41a7SViresh Kumar 	PINCTRL_PIN(130, "PLGPIO130"),	\
27785ed41a7SViresh Kumar 	PINCTRL_PIN(131, "PLGPIO131"),	\
27885ed41a7SViresh Kumar 	PINCTRL_PIN(132, "PLGPIO132"),	\
27985ed41a7SViresh Kumar 	PINCTRL_PIN(133, "PLGPIO133"),	\
28085ed41a7SViresh Kumar 	PINCTRL_PIN(134, "PLGPIO134"),	\
28185ed41a7SViresh Kumar 	PINCTRL_PIN(135, "PLGPIO135"),	\
28285ed41a7SViresh Kumar 	PINCTRL_PIN(136, "PLGPIO136"),	\
28385ed41a7SViresh Kumar 	PINCTRL_PIN(137, "PLGPIO137"),	\
28485ed41a7SViresh Kumar 	PINCTRL_PIN(138, "PLGPIO138"),	\
28585ed41a7SViresh Kumar 	PINCTRL_PIN(139, "PLGPIO139"),	\
28685ed41a7SViresh Kumar 	PINCTRL_PIN(140, "PLGPIO140"),	\
28785ed41a7SViresh Kumar 	PINCTRL_PIN(141, "PLGPIO141"),	\
28885ed41a7SViresh Kumar 	PINCTRL_PIN(142, "PLGPIO142"),	\
28985ed41a7SViresh Kumar 	PINCTRL_PIN(143, "PLGPIO143"),	\
29085ed41a7SViresh Kumar 	PINCTRL_PIN(144, "PLGPIO144"),	\
29185ed41a7SViresh Kumar 	PINCTRL_PIN(145, "PLGPIO145"),	\
29285ed41a7SViresh Kumar 	PINCTRL_PIN(146, "PLGPIO146"),	\
29385ed41a7SViresh Kumar 	PINCTRL_PIN(147, "PLGPIO147"),	\
29485ed41a7SViresh Kumar 	PINCTRL_PIN(148, "PLGPIO148"),	\
29585ed41a7SViresh Kumar 	PINCTRL_PIN(149, "PLGPIO149"),	\
29685ed41a7SViresh Kumar 	PINCTRL_PIN(150, "PLGPIO150"),	\
29785ed41a7SViresh Kumar 	PINCTRL_PIN(151, "PLGPIO151"),	\
29885ed41a7SViresh Kumar 	PINCTRL_PIN(152, "PLGPIO152"),	\
29985ed41a7SViresh Kumar 	PINCTRL_PIN(153, "PLGPIO153"),	\
30085ed41a7SViresh Kumar 	PINCTRL_PIN(154, "PLGPIO154"),	\
30185ed41a7SViresh Kumar 	PINCTRL_PIN(155, "PLGPIO155"),	\
30285ed41a7SViresh Kumar 	PINCTRL_PIN(156, "PLGPIO156"),	\
30385ed41a7SViresh Kumar 	PINCTRL_PIN(157, "PLGPIO157"),	\
30485ed41a7SViresh Kumar 	PINCTRL_PIN(158, "PLGPIO158"),	\
30585ed41a7SViresh Kumar 	PINCTRL_PIN(159, "PLGPIO159"),	\
30685ed41a7SViresh Kumar 	PINCTRL_PIN(160, "PLGPIO160"),	\
30785ed41a7SViresh Kumar 	PINCTRL_PIN(161, "PLGPIO161"),	\
30885ed41a7SViresh Kumar 	PINCTRL_PIN(162, "PLGPIO162"),	\
30985ed41a7SViresh Kumar 	PINCTRL_PIN(163, "PLGPIO163"),	\
31085ed41a7SViresh Kumar 	PINCTRL_PIN(164, "PLGPIO164"),	\
31185ed41a7SViresh Kumar 	PINCTRL_PIN(165, "PLGPIO165"),	\
31285ed41a7SViresh Kumar 	PINCTRL_PIN(166, "PLGPIO166"),	\
31385ed41a7SViresh Kumar 	PINCTRL_PIN(167, "PLGPIO167"),	\
31485ed41a7SViresh Kumar 	PINCTRL_PIN(168, "PLGPIO168"),	\
31585ed41a7SViresh Kumar 	PINCTRL_PIN(169, "PLGPIO169"),	\
31685ed41a7SViresh Kumar 	PINCTRL_PIN(170, "PLGPIO170"),	\
31785ed41a7SViresh Kumar 	PINCTRL_PIN(171, "PLGPIO171"),	\
31885ed41a7SViresh Kumar 	PINCTRL_PIN(172, "PLGPIO172"),	\
31985ed41a7SViresh Kumar 	PINCTRL_PIN(173, "PLGPIO173"),	\
32085ed41a7SViresh Kumar 	PINCTRL_PIN(174, "PLGPIO174"),	\
32185ed41a7SViresh Kumar 	PINCTRL_PIN(175, "PLGPIO175"),	\
32285ed41a7SViresh Kumar 	PINCTRL_PIN(176, "PLGPIO176"),	\
32385ed41a7SViresh Kumar 	PINCTRL_PIN(177, "PLGPIO177"),	\
32485ed41a7SViresh Kumar 	PINCTRL_PIN(178, "PLGPIO178"),	\
32585ed41a7SViresh Kumar 	PINCTRL_PIN(179, "PLGPIO179"),	\
32685ed41a7SViresh Kumar 	PINCTRL_PIN(180, "PLGPIO180"),	\
32785ed41a7SViresh Kumar 	PINCTRL_PIN(181, "PLGPIO181"),	\
32885ed41a7SViresh Kumar 	PINCTRL_PIN(182, "PLGPIO182"),	\
32985ed41a7SViresh Kumar 	PINCTRL_PIN(183, "PLGPIO183"),	\
33085ed41a7SViresh Kumar 	PINCTRL_PIN(184, "PLGPIO184"),	\
33185ed41a7SViresh Kumar 	PINCTRL_PIN(185, "PLGPIO185"),	\
33285ed41a7SViresh Kumar 	PINCTRL_PIN(186, "PLGPIO186"),	\
33385ed41a7SViresh Kumar 	PINCTRL_PIN(187, "PLGPIO187"),	\
33485ed41a7SViresh Kumar 	PINCTRL_PIN(188, "PLGPIO188"),	\
33585ed41a7SViresh Kumar 	PINCTRL_PIN(189, "PLGPIO189"),	\
33685ed41a7SViresh Kumar 	PINCTRL_PIN(190, "PLGPIO190"),	\
33785ed41a7SViresh Kumar 	PINCTRL_PIN(191, "PLGPIO191"),	\
33885ed41a7SViresh Kumar 	PINCTRL_PIN(192, "PLGPIO192"),	\
33985ed41a7SViresh Kumar 	PINCTRL_PIN(193, "PLGPIO193"),	\
34085ed41a7SViresh Kumar 	PINCTRL_PIN(194, "PLGPIO194"),	\
34185ed41a7SViresh Kumar 	PINCTRL_PIN(195, "PLGPIO195"),	\
34285ed41a7SViresh Kumar 	PINCTRL_PIN(196, "PLGPIO196"),	\
34385ed41a7SViresh Kumar 	PINCTRL_PIN(197, "PLGPIO197"),	\
34485ed41a7SViresh Kumar 	PINCTRL_PIN(198, "PLGPIO198"),	\
34585ed41a7SViresh Kumar 	PINCTRL_PIN(199, "PLGPIO199"),	\
34685ed41a7SViresh Kumar 	PINCTRL_PIN(200, "PLGPIO200"),	\
34785ed41a7SViresh Kumar 	PINCTRL_PIN(201, "PLGPIO201"),	\
34885ed41a7SViresh Kumar 	PINCTRL_PIN(202, "PLGPIO202"),	\
34985ed41a7SViresh Kumar 	PINCTRL_PIN(203, "PLGPIO203"),	\
35085ed41a7SViresh Kumar 	PINCTRL_PIN(204, "PLGPIO204"),	\
35185ed41a7SViresh Kumar 	PINCTRL_PIN(205, "PLGPIO205"),	\
35285ed41a7SViresh Kumar 	PINCTRL_PIN(206, "PLGPIO206"),	\
35385ed41a7SViresh Kumar 	PINCTRL_PIN(207, "PLGPIO207"),	\
35485ed41a7SViresh Kumar 	PINCTRL_PIN(208, "PLGPIO208"),	\
35585ed41a7SViresh Kumar 	PINCTRL_PIN(209, "PLGPIO209"),	\
35685ed41a7SViresh Kumar 	PINCTRL_PIN(210, "PLGPIO210"),	\
35785ed41a7SViresh Kumar 	PINCTRL_PIN(211, "PLGPIO211"),	\
35885ed41a7SViresh Kumar 	PINCTRL_PIN(212, "PLGPIO212"),	\
35985ed41a7SViresh Kumar 	PINCTRL_PIN(213, "PLGPIO213"),	\
36085ed41a7SViresh Kumar 	PINCTRL_PIN(214, "PLGPIO214"),	\
36185ed41a7SViresh Kumar 	PINCTRL_PIN(215, "PLGPIO215"),	\
36285ed41a7SViresh Kumar 	PINCTRL_PIN(216, "PLGPIO216"),	\
36385ed41a7SViresh Kumar 	PINCTRL_PIN(217, "PLGPIO217"),	\
36485ed41a7SViresh Kumar 	PINCTRL_PIN(218, "PLGPIO218"),	\
36585ed41a7SViresh Kumar 	PINCTRL_PIN(219, "PLGPIO219"),	\
36685ed41a7SViresh Kumar 	PINCTRL_PIN(220, "PLGPIO220"),	\
36785ed41a7SViresh Kumar 	PINCTRL_PIN(221, "PLGPIO221"),	\
36885ed41a7SViresh Kumar 	PINCTRL_PIN(222, "PLGPIO222"),	\
36985ed41a7SViresh Kumar 	PINCTRL_PIN(223, "PLGPIO223"),	\
37085ed41a7SViresh Kumar 	PINCTRL_PIN(224, "PLGPIO224"),	\
37185ed41a7SViresh Kumar 	PINCTRL_PIN(225, "PLGPIO225"),	\
37285ed41a7SViresh Kumar 	PINCTRL_PIN(226, "PLGPIO226"),	\
37385ed41a7SViresh Kumar 	PINCTRL_PIN(227, "PLGPIO227"),	\
37485ed41a7SViresh Kumar 	PINCTRL_PIN(228, "PLGPIO228"),	\
37585ed41a7SViresh Kumar 	PINCTRL_PIN(229, "PLGPIO229"),	\
37685ed41a7SViresh Kumar 	PINCTRL_PIN(230, "PLGPIO230"),	\
37785ed41a7SViresh Kumar 	PINCTRL_PIN(231, "PLGPIO231"),	\
37885ed41a7SViresh Kumar 	PINCTRL_PIN(232, "PLGPIO232"),	\
37985ed41a7SViresh Kumar 	PINCTRL_PIN(233, "PLGPIO233"),	\
38085ed41a7SViresh Kumar 	PINCTRL_PIN(234, "PLGPIO234"),	\
38185ed41a7SViresh Kumar 	PINCTRL_PIN(235, "PLGPIO235"),	\
38285ed41a7SViresh Kumar 	PINCTRL_PIN(236, "PLGPIO236"),	\
38385ed41a7SViresh Kumar 	PINCTRL_PIN(237, "PLGPIO237"),	\
38485ed41a7SViresh Kumar 	PINCTRL_PIN(238, "PLGPIO238"),	\
38585ed41a7SViresh Kumar 	PINCTRL_PIN(239, "PLGPIO239"),	\
38685ed41a7SViresh Kumar 	PINCTRL_PIN(240, "PLGPIO240"),	\
38785ed41a7SViresh Kumar 	PINCTRL_PIN(241, "PLGPIO241"),	\
38885ed41a7SViresh Kumar 	PINCTRL_PIN(242, "PLGPIO242"),	\
38985ed41a7SViresh Kumar 	PINCTRL_PIN(243, "PLGPIO243"),	\
39085ed41a7SViresh Kumar 	PINCTRL_PIN(244, "PLGPIO244"),	\
39185ed41a7SViresh Kumar 	PINCTRL_PIN(245, "PLGPIO245")
39285ed41a7SViresh Kumar 
393deda8287SViresh Kumar #endif /* __PINMUX_SPEAR_H__ */
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