1 /*
2  * S3C64xx specific support for pinctrl-samsung driver.
3  *
4  * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
5  *
6  * Based on pinctrl-exynos.c, please see the file for original copyrights.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This file contains the Samsung S3C64xx specific information required by the
14  * the Samsung pinctrl/gpiolib driver. It also includes the implementation of
15  * external gpio and wakeup interrupt support.
16  */
17 
18 #include <linux/init.h>
19 #include <linux/device.h>
20 #include <linux/interrupt.h>
21 #include <linux/irqdomain.h>
22 #include <linux/irq.h>
23 #include <linux/of_irq.h>
24 #include <linux/io.h>
25 #include <linux/irqchip/chained_irq.h>
26 #include <linux/slab.h>
27 #include <linux/err.h>
28 
29 #include "pinctrl-samsung.h"
30 
31 #define NUM_EINT0		28
32 #define NUM_EINT0_IRQ		4
33 #define EINT_MAX_PER_REG	16
34 #define EINT_MAX_PER_GROUP	16
35 
36 /* External GPIO and wakeup interrupt related definitions */
37 #define SVC_GROUP_SHIFT		4
38 #define SVC_GROUP_MASK		0xf
39 #define SVC_NUM_MASK		0xf
40 #define SVC_GROUP(x)		((x >> SVC_GROUP_SHIFT) & \
41 						SVC_GROUP_MASK)
42 
43 #define EINT12CON_REG		0x200
44 #define EINT12MASK_REG		0x240
45 #define EINT12PEND_REG		0x260
46 
47 #define EINT_OFFS(i)		((i) % (2 * EINT_MAX_PER_GROUP))
48 #define EINT_GROUP(i)		((i) / EINT_MAX_PER_GROUP)
49 #define EINT_REG(g)		(4 * ((g) / 2))
50 
51 #define EINTCON_REG(i)		(EINT12CON_REG + EINT_REG(EINT_GROUP(i)))
52 #define EINTMASK_REG(i)		(EINT12MASK_REG + EINT_REG(EINT_GROUP(i)))
53 #define EINTPEND_REG(i)		(EINT12PEND_REG + EINT_REG(EINT_GROUP(i)))
54 
55 #define SERVICE_REG		0x284
56 #define SERVICEPEND_REG		0x288
57 
58 #define EINT0CON0_REG		0x900
59 #define EINT0MASK_REG		0x920
60 #define EINT0PEND_REG		0x924
61 
62 /* S3C64xx specific external interrupt trigger types */
63 #define EINT_LEVEL_LOW		0
64 #define EINT_LEVEL_HIGH		1
65 #define EINT_EDGE_FALLING	2
66 #define EINT_EDGE_RISING	4
67 #define EINT_EDGE_BOTH		6
68 #define EINT_CON_MASK		0xF
69 #define EINT_CON_LEN		4
70 
71 static const struct samsung_pin_bank_type bank_type_4bit_off = {
72 	.fld_width = { 4, 1, 2, 0, 2, 2, },
73 	.reg_offset = { 0x00, 0x04, 0x08, 0, 0x0c, 0x10, },
74 };
75 
76 static const struct samsung_pin_bank_type bank_type_4bit_alive = {
77 	.fld_width = { 4, 1, 2, },
78 	.reg_offset = { 0x00, 0x04, 0x08, },
79 };
80 
81 static const struct samsung_pin_bank_type bank_type_4bit2_off = {
82 	.fld_width = { 4, 1, 2, 0, 2, 2, },
83 	.reg_offset = { 0x00, 0x08, 0x0c, 0, 0x10, 0x14, },
84 };
85 
86 static const struct samsung_pin_bank_type bank_type_4bit2_alive = {
87 	.fld_width = { 4, 1, 2, },
88 	.reg_offset = { 0x00, 0x08, 0x0c, },
89 };
90 
91 static const struct samsung_pin_bank_type bank_type_2bit_off = {
92 	.fld_width = { 2, 1, 2, 0, 2, 2, },
93 	.reg_offset = { 0x00, 0x04, 0x08, 0, 0x0c, 0x10, },
94 };
95 
96 static const struct samsung_pin_bank_type bank_type_2bit_alive = {
97 	.fld_width = { 2, 1, 2, },
98 	.reg_offset = { 0x00, 0x04, 0x08, },
99 };
100 
101 #define PIN_BANK_4BIT(pins, reg, id)			\
102 	{						\
103 		.type		= &bank_type_4bit_off,	\
104 		.pctl_offset	= reg,			\
105 		.nr_pins	= pins,			\
106 		.eint_type	= EINT_TYPE_NONE,	\
107 		.name		= id			\
108 	}
109 
110 #define PIN_BANK_4BIT_EINTG(pins, reg, id, eoffs)	\
111 	{						\
112 		.type		= &bank_type_4bit_off,	\
113 		.pctl_offset	= reg,			\
114 		.nr_pins	= pins,			\
115 		.eint_type	= EINT_TYPE_GPIO,	\
116 		.eint_func	= 7,			\
117 		.eint_mask	= (1 << (pins)) - 1,	\
118 		.eint_offset	= eoffs,		\
119 		.name		= id			\
120 	}
121 
122 #define PIN_BANK_4BIT_EINTW(pins, reg, id, eoffs, emask) \
123 	{						\
124 		.type		= &bank_type_4bit_alive,\
125 		.pctl_offset	= reg,			\
126 		.nr_pins	= pins,			\
127 		.eint_type	= EINT_TYPE_WKUP,	\
128 		.eint_func	= 3,			\
129 		.eint_mask	= emask,		\
130 		.eint_offset	= eoffs,		\
131 		.name		= id			\
132 	}
133 
134 #define PIN_BANK_4BIT2_EINTG(pins, reg, id, eoffs)	\
135 	{						\
136 		.type		= &bank_type_4bit2_off,	\
137 		.pctl_offset	= reg,			\
138 		.nr_pins	= pins,			\
139 		.eint_type	= EINT_TYPE_GPIO,	\
140 		.eint_func	= 7,			\
141 		.eint_mask	= (1 << (pins)) - 1,	\
142 		.eint_offset	= eoffs,		\
143 		.name		= id			\
144 	}
145 
146 #define PIN_BANK_4BIT2_EINTW(pins, reg, id, eoffs, emask) \
147 	{						\
148 		.type		= &bank_type_4bit2_alive,\
149 		.pctl_offset	= reg,			\
150 		.nr_pins	= pins,			\
151 		.eint_type	= EINT_TYPE_WKUP,	\
152 		.eint_func	= 3,			\
153 		.eint_mask	= emask,		\
154 		.eint_offset	= eoffs,		\
155 		.name		= id			\
156 	}
157 
158 #define PIN_BANK_4BIT2_ALIVE(pins, reg, id)		\
159 	{						\
160 		.type		= &bank_type_4bit2_alive,\
161 		.pctl_offset	= reg,			\
162 		.nr_pins	= pins,			\
163 		.eint_type	= EINT_TYPE_NONE,	\
164 		.name		= id			\
165 	}
166 
167 #define PIN_BANK_2BIT(pins, reg, id)			\
168 	{						\
169 		.type		= &bank_type_2bit_off,	\
170 		.pctl_offset	= reg,			\
171 		.nr_pins	= pins,			\
172 		.eint_type	= EINT_TYPE_NONE,	\
173 		.name		= id			\
174 	}
175 
176 #define PIN_BANK_2BIT_EINTG(pins, reg, id, eoffs, emask) \
177 	{						\
178 		.type		= &bank_type_2bit_off,	\
179 		.pctl_offset	= reg,			\
180 		.nr_pins	= pins,			\
181 		.eint_type	= EINT_TYPE_GPIO,	\
182 		.eint_func	= 3,			\
183 		.eint_mask	= emask,		\
184 		.eint_offset	= eoffs,		\
185 		.name		= id			\
186 	}
187 
188 #define PIN_BANK_2BIT_EINTW(pins, reg, id, eoffs)	\
189 	{						\
190 		.type		= &bank_type_2bit_alive,\
191 		.pctl_offset	= reg,			\
192 		.nr_pins	= pins,			\
193 		.eint_type	= EINT_TYPE_WKUP,	\
194 		.eint_func	= 2,			\
195 		.eint_mask	= (1 << (pins)) - 1,	\
196 		.eint_offset	= eoffs,		\
197 		.name		= id			\
198 	}
199 
200 /**
201  * struct s3c64xx_eint0_data: EINT0 common data
202  * @drvdata: pin controller driver data
203  * @domains: IRQ domains of particular EINT0 interrupts
204  * @pins: pin offsets inside of banks of particular EINT0 interrupts
205  */
206 struct s3c64xx_eint0_data {
207 	struct samsung_pinctrl_drv_data *drvdata;
208 	struct irq_domain *domains[NUM_EINT0];
209 	u8 pins[NUM_EINT0];
210 };
211 
212 /**
213  * struct s3c64xx_eint0_domain_data: EINT0 per-domain data
214  * @bank: pin bank related to the domain
215  * @eints: EINT0 interrupts related to the domain
216  */
217 struct s3c64xx_eint0_domain_data {
218 	struct samsung_pin_bank *bank;
219 	u8 eints[];
220 };
221 
222 /**
223  * struct s3c64xx_eint_gpio_data: GPIO EINT data
224  * @drvdata: pin controller driver data
225  * @domains: array of domains related to EINT interrupt groups
226  */
227 struct s3c64xx_eint_gpio_data {
228 	struct samsung_pinctrl_drv_data *drvdata;
229 	struct irq_domain *domains[];
230 };
231 
232 /*
233  * Common functions for S3C64xx EINT configuration
234  */
235 
236 static int s3c64xx_irq_get_trigger(unsigned int type)
237 {
238 	int trigger;
239 
240 	switch (type) {
241 	case IRQ_TYPE_EDGE_RISING:
242 		trigger = EINT_EDGE_RISING;
243 		break;
244 	case IRQ_TYPE_EDGE_FALLING:
245 		trigger = EINT_EDGE_FALLING;
246 		break;
247 	case IRQ_TYPE_EDGE_BOTH:
248 		trigger = EINT_EDGE_BOTH;
249 		break;
250 	case IRQ_TYPE_LEVEL_HIGH:
251 		trigger = EINT_LEVEL_HIGH;
252 		break;
253 	case IRQ_TYPE_LEVEL_LOW:
254 		trigger = EINT_LEVEL_LOW;
255 		break;
256 	default:
257 		return -EINVAL;
258 	}
259 
260 	return trigger;
261 }
262 
263 static void s3c64xx_irq_set_handler(struct irq_data *d, unsigned int type)
264 {
265 	/* Edge- and level-triggered interrupts need different handlers */
266 	if (type & IRQ_TYPE_EDGE_BOTH)
267 		irq_set_handler_locked(d, handle_edge_irq);
268 	else
269 		irq_set_handler_locked(d, handle_level_irq);
270 }
271 
272 static void s3c64xx_irq_set_function(struct samsung_pinctrl_drv_data *d,
273 					struct samsung_pin_bank *bank, int pin)
274 {
275 	const struct samsung_pin_bank_type *bank_type = bank->type;
276 	unsigned long flags;
277 	void __iomem *reg;
278 	u8 shift;
279 	u32 mask;
280 	u32 val;
281 
282 	/* Make sure that pin is configured as interrupt */
283 	reg = d->virt_base + bank->pctl_offset;
284 	shift = pin;
285 	if (bank_type->fld_width[PINCFG_TYPE_FUNC] * shift >= 32) {
286 		/* 4-bit bank type with 2 con regs */
287 		reg += 4;
288 		shift -= 8;
289 	}
290 
291 	shift = shift * bank_type->fld_width[PINCFG_TYPE_FUNC];
292 	mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
293 
294 	spin_lock_irqsave(&bank->slock, flags);
295 
296 	val = readl(reg);
297 	val &= ~(mask << shift);
298 	val |= bank->eint_func << shift;
299 	writel(val, reg);
300 
301 	spin_unlock_irqrestore(&bank->slock, flags);
302 }
303 
304 /*
305  * Functions for EINT GPIO configuration (EINT groups 1-9)
306  */
307 
308 static inline void s3c64xx_gpio_irq_set_mask(struct irq_data *irqd, bool mask)
309 {
310 	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
311 	struct samsung_pinctrl_drv_data *d = bank->drvdata;
312 	unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq;
313 	void __iomem *reg = d->virt_base + EINTMASK_REG(bank->eint_offset);
314 	u32 val;
315 
316 	val = readl(reg);
317 	if (mask)
318 		val |= 1 << index;
319 	else
320 		val &= ~(1 << index);
321 	writel(val, reg);
322 }
323 
324 static void s3c64xx_gpio_irq_unmask(struct irq_data *irqd)
325 {
326 	s3c64xx_gpio_irq_set_mask(irqd, false);
327 }
328 
329 static void s3c64xx_gpio_irq_mask(struct irq_data *irqd)
330 {
331 	s3c64xx_gpio_irq_set_mask(irqd, true);
332 }
333 
334 static void s3c64xx_gpio_irq_ack(struct irq_data *irqd)
335 {
336 	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
337 	struct samsung_pinctrl_drv_data *d = bank->drvdata;
338 	unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq;
339 	void __iomem *reg = d->virt_base + EINTPEND_REG(bank->eint_offset);
340 
341 	writel(1 << index, reg);
342 }
343 
344 static int s3c64xx_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
345 {
346 	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
347 	struct samsung_pinctrl_drv_data *d = bank->drvdata;
348 	void __iomem *reg;
349 	int trigger;
350 	u8 shift;
351 	u32 val;
352 
353 	trigger = s3c64xx_irq_get_trigger(type);
354 	if (trigger < 0) {
355 		pr_err("unsupported external interrupt type\n");
356 		return -EINVAL;
357 	}
358 
359 	s3c64xx_irq_set_handler(irqd, type);
360 
361 	/* Set up interrupt trigger */
362 	reg = d->virt_base + EINTCON_REG(bank->eint_offset);
363 	shift = EINT_OFFS(bank->eint_offset) + irqd->hwirq;
364 	shift = 4 * (shift / 4); /* 4 EINTs per trigger selector */
365 
366 	val = readl(reg);
367 	val &= ~(EINT_CON_MASK << shift);
368 	val |= trigger << shift;
369 	writel(val, reg);
370 
371 	s3c64xx_irq_set_function(d, bank, irqd->hwirq);
372 
373 	return 0;
374 }
375 
376 /*
377  * irq_chip for gpio interrupts.
378  */
379 static struct irq_chip s3c64xx_gpio_irq_chip = {
380 	.name		= "GPIO",
381 	.irq_unmask	= s3c64xx_gpio_irq_unmask,
382 	.irq_mask	= s3c64xx_gpio_irq_mask,
383 	.irq_ack	= s3c64xx_gpio_irq_ack,
384 	.irq_set_type	= s3c64xx_gpio_irq_set_type,
385 };
386 
387 static int s3c64xx_gpio_irq_map(struct irq_domain *h, unsigned int virq,
388 					irq_hw_number_t hw)
389 {
390 	struct samsung_pin_bank *bank = h->host_data;
391 
392 	if (!(bank->eint_mask & (1 << hw)))
393 		return -EINVAL;
394 
395 	irq_set_chip_and_handler(virq,
396 				&s3c64xx_gpio_irq_chip, handle_level_irq);
397 	irq_set_chip_data(virq, bank);
398 
399 	return 0;
400 }
401 
402 /*
403  * irq domain callbacks for external gpio interrupt controller.
404  */
405 static const struct irq_domain_ops s3c64xx_gpio_irqd_ops = {
406 	.map	= s3c64xx_gpio_irq_map,
407 	.xlate	= irq_domain_xlate_twocell,
408 };
409 
410 static void s3c64xx_eint_gpio_irq(struct irq_desc *desc)
411 {
412 	struct irq_chip *chip = irq_desc_get_chip(desc);
413 	struct s3c64xx_eint_gpio_data *data = irq_desc_get_handler_data(desc);
414 	struct samsung_pinctrl_drv_data *drvdata = data->drvdata;
415 
416 	chained_irq_enter(chip, desc);
417 
418 	do {
419 		unsigned int svc;
420 		unsigned int group;
421 		unsigned int pin;
422 		unsigned int virq;
423 
424 		svc = readl(drvdata->virt_base + SERVICE_REG);
425 		group = SVC_GROUP(svc);
426 		pin = svc & SVC_NUM_MASK;
427 
428 		if (!group)
429 			break;
430 
431 		/* Group 1 is used for two pin banks */
432 		if (group == 1) {
433 			if (pin < 8)
434 				group = 0;
435 			else
436 				pin -= 8;
437 		}
438 
439 		virq = irq_linear_revmap(data->domains[group], pin);
440 		/*
441 		 * Something must be really wrong if an unmapped EINT
442 		 * was unmasked...
443 		 */
444 		BUG_ON(!virq);
445 
446 		generic_handle_irq(virq);
447 	} while (1);
448 
449 	chained_irq_exit(chip, desc);
450 }
451 
452 /**
453  * s3c64xx_eint_gpio_init() - setup handling of external gpio interrupts.
454  * @d: driver data of samsung pinctrl driver.
455  */
456 static int s3c64xx_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
457 {
458 	struct s3c64xx_eint_gpio_data *data;
459 	struct samsung_pin_bank *bank;
460 	struct device *dev = d->dev;
461 	unsigned int nr_domains;
462 	unsigned int i;
463 
464 	if (!d->irq) {
465 		dev_err(dev, "irq number not available\n");
466 		return -EINVAL;
467 	}
468 
469 	nr_domains = 0;
470 	bank = d->pin_banks;
471 	for (i = 0; i < d->nr_banks; ++i, ++bank) {
472 		unsigned int nr_eints;
473 		unsigned int mask;
474 
475 		if (bank->eint_type != EINT_TYPE_GPIO)
476 			continue;
477 
478 		mask = bank->eint_mask;
479 		nr_eints = fls(mask);
480 
481 		bank->irq_domain = irq_domain_add_linear(bank->of_node,
482 					nr_eints, &s3c64xx_gpio_irqd_ops, bank);
483 		if (!bank->irq_domain) {
484 			dev_err(dev, "gpio irq domain add failed\n");
485 			return -ENXIO;
486 		}
487 
488 		++nr_domains;
489 	}
490 
491 	data = devm_kzalloc(dev, sizeof(*data)
492 			+ nr_domains * sizeof(*data->domains), GFP_KERNEL);
493 	if (!data)
494 		return -ENOMEM;
495 	data->drvdata = d;
496 
497 	bank = d->pin_banks;
498 	nr_domains = 0;
499 	for (i = 0; i < d->nr_banks; ++i, ++bank) {
500 		if (bank->eint_type != EINT_TYPE_GPIO)
501 			continue;
502 
503 		data->domains[nr_domains++] = bank->irq_domain;
504 	}
505 
506 	irq_set_chained_handler_and_data(d->irq, s3c64xx_eint_gpio_irq, data);
507 
508 	return 0;
509 }
510 
511 /*
512  * Functions for configuration of EINT0 wake-up interrupts
513  */
514 
515 static inline void s3c64xx_eint0_irq_set_mask(struct irq_data *irqd, bool mask)
516 {
517 	struct s3c64xx_eint0_domain_data *ddata =
518 					irq_data_get_irq_chip_data(irqd);
519 	struct samsung_pinctrl_drv_data *d = ddata->bank->drvdata;
520 	u32 val;
521 
522 	val = readl(d->virt_base + EINT0MASK_REG);
523 	if (mask)
524 		val |= 1 << ddata->eints[irqd->hwirq];
525 	else
526 		val &= ~(1 << ddata->eints[irqd->hwirq]);
527 	writel(val, d->virt_base + EINT0MASK_REG);
528 }
529 
530 static void s3c64xx_eint0_irq_unmask(struct irq_data *irqd)
531 {
532 	s3c64xx_eint0_irq_set_mask(irqd, false);
533 }
534 
535 static void s3c64xx_eint0_irq_mask(struct irq_data *irqd)
536 {
537 	s3c64xx_eint0_irq_set_mask(irqd, true);
538 }
539 
540 static void s3c64xx_eint0_irq_ack(struct irq_data *irqd)
541 {
542 	struct s3c64xx_eint0_domain_data *ddata =
543 					irq_data_get_irq_chip_data(irqd);
544 	struct samsung_pinctrl_drv_data *d = ddata->bank->drvdata;
545 
546 	writel(1 << ddata->eints[irqd->hwirq],
547 					d->virt_base + EINT0PEND_REG);
548 }
549 
550 static int s3c64xx_eint0_irq_set_type(struct irq_data *irqd, unsigned int type)
551 {
552 	struct s3c64xx_eint0_domain_data *ddata =
553 					irq_data_get_irq_chip_data(irqd);
554 	struct samsung_pin_bank *bank = ddata->bank;
555 	struct samsung_pinctrl_drv_data *d = bank->drvdata;
556 	void __iomem *reg;
557 	int trigger;
558 	u8 shift;
559 	u32 val;
560 
561 	trigger = s3c64xx_irq_get_trigger(type);
562 	if (trigger < 0) {
563 		pr_err("unsupported external interrupt type\n");
564 		return -EINVAL;
565 	}
566 
567 	s3c64xx_irq_set_handler(irqd, type);
568 
569 	/* Set up interrupt trigger */
570 	reg = d->virt_base + EINT0CON0_REG;
571 	shift = ddata->eints[irqd->hwirq];
572 	if (shift >= EINT_MAX_PER_REG) {
573 		reg += 4;
574 		shift -= EINT_MAX_PER_REG;
575 	}
576 	shift = EINT_CON_LEN * (shift / 2);
577 
578 	val = readl(reg);
579 	val &= ~(EINT_CON_MASK << shift);
580 	val |= trigger << shift;
581 	writel(val, reg);
582 
583 	s3c64xx_irq_set_function(d, bank, irqd->hwirq);
584 
585 	return 0;
586 }
587 
588 /*
589  * irq_chip for wakeup interrupts
590  */
591 static struct irq_chip s3c64xx_eint0_irq_chip = {
592 	.name		= "EINT0",
593 	.irq_unmask	= s3c64xx_eint0_irq_unmask,
594 	.irq_mask	= s3c64xx_eint0_irq_mask,
595 	.irq_ack	= s3c64xx_eint0_irq_ack,
596 	.irq_set_type	= s3c64xx_eint0_irq_set_type,
597 };
598 
599 static inline void s3c64xx_irq_demux_eint(struct irq_desc *desc, u32 range)
600 {
601 	struct irq_chip *chip = irq_desc_get_chip(desc);
602 	struct s3c64xx_eint0_data *data = irq_desc_get_handler_data(desc);
603 	struct samsung_pinctrl_drv_data *drvdata = data->drvdata;
604 	unsigned int pend, mask;
605 
606 	chained_irq_enter(chip, desc);
607 
608 	pend = readl(drvdata->virt_base + EINT0PEND_REG);
609 	mask = readl(drvdata->virt_base + EINT0MASK_REG);
610 
611 	pend = pend & range & ~mask;
612 	pend &= range;
613 
614 	while (pend) {
615 		unsigned int virq, irq;
616 
617 		irq = fls(pend) - 1;
618 		pend &= ~(1 << irq);
619 		virq = irq_linear_revmap(data->domains[irq], data->pins[irq]);
620 		/*
621 		 * Something must be really wrong if an unmapped EINT
622 		 * was unmasked...
623 		 */
624 		BUG_ON(!virq);
625 
626 		generic_handle_irq(virq);
627 	}
628 
629 	chained_irq_exit(chip, desc);
630 }
631 
632 static void s3c64xx_demux_eint0_3(struct irq_desc *desc)
633 {
634 	s3c64xx_irq_demux_eint(desc, 0xf);
635 }
636 
637 static void s3c64xx_demux_eint4_11(struct irq_desc *desc)
638 {
639 	s3c64xx_irq_demux_eint(desc, 0xff0);
640 }
641 
642 static void s3c64xx_demux_eint12_19(struct irq_desc *desc)
643 {
644 	s3c64xx_irq_demux_eint(desc, 0xff000);
645 }
646 
647 static void s3c64xx_demux_eint20_27(struct irq_desc *desc)
648 {
649 	s3c64xx_irq_demux_eint(desc, 0xff00000);
650 }
651 
652 static irq_flow_handler_t s3c64xx_eint0_handlers[NUM_EINT0_IRQ] = {
653 	s3c64xx_demux_eint0_3,
654 	s3c64xx_demux_eint4_11,
655 	s3c64xx_demux_eint12_19,
656 	s3c64xx_demux_eint20_27,
657 };
658 
659 static int s3c64xx_eint0_irq_map(struct irq_domain *h, unsigned int virq,
660 					irq_hw_number_t hw)
661 {
662 	struct s3c64xx_eint0_domain_data *ddata = h->host_data;
663 	struct samsung_pin_bank *bank = ddata->bank;
664 
665 	if (!(bank->eint_mask & (1 << hw)))
666 		return -EINVAL;
667 
668 	irq_set_chip_and_handler(virq,
669 				&s3c64xx_eint0_irq_chip, handle_level_irq);
670 	irq_set_chip_data(virq, ddata);
671 
672 	return 0;
673 }
674 
675 /*
676  * irq domain callbacks for external wakeup interrupt controller.
677  */
678 static const struct irq_domain_ops s3c64xx_eint0_irqd_ops = {
679 	.map	= s3c64xx_eint0_irq_map,
680 	.xlate	= irq_domain_xlate_twocell,
681 };
682 
683 /* list of external wakeup controllers supported */
684 static const struct of_device_id s3c64xx_eint0_irq_ids[] = {
685 	{ .compatible = "samsung,s3c64xx-wakeup-eint", },
686 	{ }
687 };
688 
689 /**
690  * s3c64xx_eint_eint0_init() - setup handling of external wakeup interrupts.
691  * @d: driver data of samsung pinctrl driver.
692  */
693 static int s3c64xx_eint_eint0_init(struct samsung_pinctrl_drv_data *d)
694 {
695 	struct device *dev = d->dev;
696 	struct device_node *eint0_np = NULL;
697 	struct device_node *np;
698 	struct samsung_pin_bank *bank;
699 	struct s3c64xx_eint0_data *data;
700 	unsigned int i;
701 
702 	for_each_child_of_node(dev->of_node, np) {
703 		if (of_match_node(s3c64xx_eint0_irq_ids, np)) {
704 			eint0_np = np;
705 			break;
706 		}
707 	}
708 	if (!eint0_np)
709 		return -ENODEV;
710 
711 	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
712 	if (!data)
713 		return -ENOMEM;
714 	data->drvdata = d;
715 
716 	for (i = 0; i < NUM_EINT0_IRQ; ++i) {
717 		unsigned int irq;
718 
719 		irq = irq_of_parse_and_map(eint0_np, i);
720 		if (!irq) {
721 			dev_err(dev, "failed to get wakeup EINT IRQ %d\n", i);
722 			return -ENXIO;
723 		}
724 
725 		irq_set_chained_handler_and_data(irq,
726 						 s3c64xx_eint0_handlers[i],
727 						 data);
728 	}
729 
730 	bank = d->pin_banks;
731 	for (i = 0; i < d->nr_banks; ++i, ++bank) {
732 		struct s3c64xx_eint0_domain_data *ddata;
733 		unsigned int nr_eints;
734 		unsigned int mask;
735 		unsigned int irq;
736 		unsigned int pin;
737 
738 		if (bank->eint_type != EINT_TYPE_WKUP)
739 			continue;
740 
741 		mask = bank->eint_mask;
742 		nr_eints = fls(mask);
743 
744 		ddata = devm_kzalloc(dev,
745 				sizeof(*ddata) + nr_eints, GFP_KERNEL);
746 		if (!ddata)
747 			return -ENOMEM;
748 		ddata->bank = bank;
749 
750 		bank->irq_domain = irq_domain_add_linear(bank->of_node,
751 				nr_eints, &s3c64xx_eint0_irqd_ops, ddata);
752 		if (!bank->irq_domain) {
753 			dev_err(dev, "wkup irq domain add failed\n");
754 			return -ENXIO;
755 		}
756 
757 		irq = bank->eint_offset;
758 		mask = bank->eint_mask;
759 		for (pin = 0; mask; ++pin, mask >>= 1) {
760 			if (!(mask & 1))
761 				continue;
762 			data->domains[irq] = bank->irq_domain;
763 			data->pins[irq] = pin;
764 			ddata->eints[pin] = irq;
765 			++irq;
766 		}
767 	}
768 
769 	return 0;
770 }
771 
772 /* pin banks of s3c64xx pin-controller 0 */
773 static const struct samsung_pin_bank_data s3c64xx_pin_banks0[] __initconst = {
774 	PIN_BANK_4BIT_EINTG(8, 0x000, "gpa", 0),
775 	PIN_BANK_4BIT_EINTG(7, 0x020, "gpb", 8),
776 	PIN_BANK_4BIT_EINTG(8, 0x040, "gpc", 16),
777 	PIN_BANK_4BIT_EINTG(5, 0x060, "gpd", 32),
778 	PIN_BANK_4BIT(5, 0x080, "gpe"),
779 	PIN_BANK_2BIT_EINTG(16, 0x0a0, "gpf", 48, 0x3fff),
780 	PIN_BANK_4BIT_EINTG(7, 0x0c0, "gpg", 64),
781 	PIN_BANK_4BIT2_EINTG(10, 0x0e0, "gph", 80),
782 	PIN_BANK_2BIT(16, 0x100, "gpi"),
783 	PIN_BANK_2BIT(12, 0x120, "gpj"),
784 	PIN_BANK_4BIT2_ALIVE(16, 0x800, "gpk"),
785 	PIN_BANK_4BIT2_EINTW(15, 0x810, "gpl", 16, 0x7f00),
786 	PIN_BANK_4BIT_EINTW(6, 0x820, "gpm", 23, 0x1f),
787 	PIN_BANK_2BIT_EINTW(16, 0x830, "gpn", 0),
788 	PIN_BANK_2BIT_EINTG(16, 0x140, "gpo", 96, 0xffff),
789 	PIN_BANK_2BIT_EINTG(15, 0x160, "gpp", 112, 0x7fff),
790 	PIN_BANK_2BIT_EINTG(9, 0x180, "gpq", 128, 0x1ff),
791 };
792 
793 /*
794  * Samsung pinctrl driver data for S3C64xx SoC. S3C64xx SoC includes
795  * one gpio/pin-mux/pinconfig controller.
796  */
797 const struct samsung_pin_ctrl s3c64xx_pin_ctrl[] __initconst = {
798 	{
799 		/* pin-controller instance 1 data */
800 		.pin_banks	= s3c64xx_pin_banks0,
801 		.nr_banks	= ARRAY_SIZE(s3c64xx_pin_banks0),
802 		.eint_gpio_init = s3c64xx_eint_gpio_init,
803 		.eint_wkup_init = s3c64xx_eint_eint0_init,
804 	},
805 };
806