1 /* 2 * Exynos specific definitions for Samsung pinctrl and gpiolib driver. 3 * 4 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 5 * http://www.samsung.com 6 * Copyright (c) 2012 Linaro Ltd 7 * http://www.linaro.org 8 * 9 * This file contains the Exynos specific definitions for the Samsung 10 * pinctrl/gpiolib interface drivers. 11 * 12 * Author: Thomas Abraham <thomas.ab@samsung.com> 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License as published by 16 * the Free Software Foundation; either version 2 of the License, or 17 * (at your option) any later version. 18 */ 19 20 /* External GPIO and wakeup interrupt related definitions */ 21 #define EXYNOS_GPIO_ECON_OFFSET 0x700 22 #define EXYNOS_GPIO_EFLTCON_OFFSET 0x800 23 #define EXYNOS_GPIO_EMASK_OFFSET 0x900 24 #define EXYNOS_GPIO_EPEND_OFFSET 0xA00 25 #define EXYNOS_WKUP_ECON_OFFSET 0xE00 26 #define EXYNOS_WKUP_EMASK_OFFSET 0xF00 27 #define EXYNOS_WKUP_EPEND_OFFSET 0xF40 28 #define EXYNOS_SVC_OFFSET 0xB08 29 #define EXYNOS_EINT_FUNC 0xF 30 31 /* helpers to access interrupt service register */ 32 #define EXYNOS_SVC_GROUP_SHIFT 3 33 #define EXYNOS_SVC_GROUP_MASK 0x1f 34 #define EXYNOS_SVC_NUM_MASK 7 35 #define EXYNOS_SVC_GROUP(x) ((x >> EXYNOS_SVC_GROUP_SHIFT) & \ 36 EXYNOS_SVC_GROUP_MASK) 37 38 /* Exynos specific external interrupt trigger types */ 39 #define EXYNOS_EINT_LEVEL_LOW 0 40 #define EXYNOS_EINT_LEVEL_HIGH 1 41 #define EXYNOS_EINT_EDGE_FALLING 2 42 #define EXYNOS_EINT_EDGE_RISING 3 43 #define EXYNOS_EINT_EDGE_BOTH 4 44 #define EXYNOS_EINT_CON_MASK 0xF 45 #define EXYNOS_EINT_CON_LEN 4 46 47 #define EXYNOS_EINT_MAX_PER_BANK 8 48 #define EXYNOS_EINT_NR_WKUP_EINT 49 50 #define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \ 51 { \ 52 .type = &bank_type_off, \ 53 .pctl_offset = reg, \ 54 .nr_pins = pins, \ 55 .eint_type = EINT_TYPE_NONE, \ 56 .name = id \ 57 } 58 59 #define EXYNOS_PIN_BANK_EINTG(pins, reg, id, offs) \ 60 { \ 61 .type = &bank_type_off, \ 62 .pctl_offset = reg, \ 63 .nr_pins = pins, \ 64 .eint_type = EINT_TYPE_GPIO, \ 65 .eint_offset = offs, \ 66 .name = id \ 67 } 68 69 #define EXYNOS_PIN_BANK_EINTW(pins, reg, id, offs) \ 70 { \ 71 .type = &bank_type_alive, \ 72 .pctl_offset = reg, \ 73 .nr_pins = pins, \ 74 .eint_type = EINT_TYPE_WKUP, \ 75 .eint_offset = offs, \ 76 .name = id \ 77 } 78 79 /** 80 * struct exynos_weint_data: irq specific data for all the wakeup interrupts 81 * generated by the external wakeup interrupt controller. 82 * @irq: interrupt number within the domain. 83 * @bank: bank responsible for this interrupt 84 */ 85 struct exynos_weint_data { 86 unsigned int irq; 87 struct samsung_pin_bank *bank; 88 }; 89 90 /** 91 * struct exynos_muxed_weint_data: irq specific data for muxed wakeup interrupts 92 * generated by the external wakeup interrupt controller. 93 * @nr_banks: count of banks being part of the mux 94 * @banks: array of banks being part of the mux 95 */ 96 struct exynos_muxed_weint_data { 97 unsigned int nr_banks; 98 struct samsung_pin_bank *banks[]; 99 }; 100