1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Exynos specific definitions for Samsung pinctrl and gpiolib driver. 4 * 5 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 6 * http://www.samsung.com 7 * Copyright (c) 2012 Linaro Ltd 8 * http://www.linaro.org 9 * 10 * This file contains the Exynos specific definitions for the Samsung 11 * pinctrl/gpiolib interface drivers. 12 * 13 * Author: Thomas Abraham <thomas.ab@samsung.com> 14 */ 15 16 #ifndef __PINCTRL_SAMSUNG_EXYNOS_H 17 #define __PINCTRL_SAMSUNG_EXYNOS_H 18 19 /* External GPIO and wakeup interrupt related definitions */ 20 #define EXYNOS_GPIO_ECON_OFFSET 0x700 21 #define EXYNOS_GPIO_EFLTCON_OFFSET 0x800 22 #define EXYNOS_GPIO_EMASK_OFFSET 0x900 23 #define EXYNOS_GPIO_EPEND_OFFSET 0xA00 24 #define EXYNOS_WKUP_ECON_OFFSET 0xE00 25 #define EXYNOS_WKUP_EMASK_OFFSET 0xF00 26 #define EXYNOS_WKUP_EPEND_OFFSET 0xF40 27 #define EXYNOS7_WKUP_ECON_OFFSET 0x700 28 #define EXYNOS7_WKUP_EMASK_OFFSET 0x900 29 #define EXYNOS7_WKUP_EPEND_OFFSET 0xA00 30 #define EXYNOS_SVC_OFFSET 0xB08 31 32 /* helpers to access interrupt service register */ 33 #define EXYNOS_SVC_GROUP_SHIFT 3 34 #define EXYNOS_SVC_GROUP_MASK 0x1f 35 #define EXYNOS_SVC_NUM_MASK 7 36 #define EXYNOS_SVC_GROUP(x) ((x >> EXYNOS_SVC_GROUP_SHIFT) & \ 37 EXYNOS_SVC_GROUP_MASK) 38 39 /* Exynos specific external interrupt trigger types */ 40 #define EXYNOS_EINT_LEVEL_LOW 0 41 #define EXYNOS_EINT_LEVEL_HIGH 1 42 #define EXYNOS_EINT_EDGE_FALLING 2 43 #define EXYNOS_EINT_EDGE_RISING 3 44 #define EXYNOS_EINT_EDGE_BOTH 4 45 #define EXYNOS_EINT_CON_MASK 0xF 46 #define EXYNOS_EINT_CON_LEN 4 47 48 #define EXYNOS_EINT_MAX_PER_BANK 8 49 #define EXYNOS_EINT_NR_WKUP_EINT 50 51 #define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \ 52 { \ 53 .type = &bank_type_off, \ 54 .pctl_offset = reg, \ 55 .nr_pins = pins, \ 56 .eint_type = EINT_TYPE_NONE, \ 57 .name = id \ 58 } 59 60 #define EXYNOS_PIN_BANK_EINTG(pins, reg, id, offs) \ 61 { \ 62 .type = &bank_type_off, \ 63 .pctl_offset = reg, \ 64 .nr_pins = pins, \ 65 .eint_type = EINT_TYPE_GPIO, \ 66 .eint_offset = offs, \ 67 .name = id \ 68 } 69 70 #define EXYNOS_PIN_BANK_EINTW(pins, reg, id, offs) \ 71 { \ 72 .type = &bank_type_alive, \ 73 .pctl_offset = reg, \ 74 .nr_pins = pins, \ 75 .eint_type = EINT_TYPE_WKUP, \ 76 .eint_offset = offs, \ 77 .name = id \ 78 } 79 80 #define EXYNOS5433_PIN_BANK_EINTG(pins, reg, id, offs) \ 81 { \ 82 .type = &exynos5433_bank_type_off, \ 83 .pctl_offset = reg, \ 84 .nr_pins = pins, \ 85 .eint_type = EINT_TYPE_GPIO, \ 86 .eint_offset = offs, \ 87 .name = id \ 88 } 89 90 #define EXYNOS5433_PIN_BANK_EINTW(pins, reg, id, offs) \ 91 { \ 92 .type = &exynos5433_bank_type_alive, \ 93 .pctl_offset = reg, \ 94 .nr_pins = pins, \ 95 .eint_type = EINT_TYPE_WKUP, \ 96 .eint_offset = offs, \ 97 .name = id \ 98 } 99 100 #define EXYNOS5433_PIN_BANK_EINTW_EXT(pins, reg, id, offs, pctl_idx) \ 101 { \ 102 .type = &exynos5433_bank_type_off, \ 103 .pctl_offset = reg, \ 104 .nr_pins = pins, \ 105 .eint_type = EINT_TYPE_WKUP, \ 106 .eint_offset = offs, \ 107 .name = id, \ 108 .pctl_res_idx = pctl_idx, \ 109 } \ 110 111 /** 112 * struct exynos_weint_data: irq specific data for all the wakeup interrupts 113 * generated by the external wakeup interrupt controller. 114 * @irq: interrupt number within the domain. 115 * @bank: bank responsible for this interrupt 116 */ 117 struct exynos_weint_data { 118 unsigned int irq; 119 struct samsung_pin_bank *bank; 120 }; 121 122 /** 123 * struct exynos_muxed_weint_data: irq specific data for muxed wakeup interrupts 124 * generated by the external wakeup interrupt controller. 125 * @nr_banks: count of banks being part of the mux 126 * @banks: array of banks being part of the mux 127 */ 128 struct exynos_muxed_weint_data { 129 unsigned int nr_banks; 130 struct samsung_pin_bank *banks[]; 131 }; 132 133 int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d); 134 int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d); 135 void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata); 136 void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata); 137 struct samsung_retention_ctrl * 138 exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata, 139 const struct samsung_retention_data *data); 140 141 #endif /* __PINCTRL_SAMSUNG_EXYNOS_H */ 142