1 /* 2 * Exynos specific support for Samsung pinctrl/gpiolib driver with eint support. 3 * 4 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 5 * http://www.samsung.com 6 * Copyright (c) 2012 Linaro Ltd 7 * http://www.linaro.org 8 * 9 * Author: Thomas Abraham <thomas.ab@samsung.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * This file contains the Samsung Exynos specific information required by the 17 * the Samsung pinctrl/gpiolib driver. It also includes the implementation of 18 * external gpio and wakeup interrupt support. 19 */ 20 21 #include <linux/module.h> 22 #include <linux/device.h> 23 #include <linux/interrupt.h> 24 #include <linux/irqdomain.h> 25 #include <linux/irq.h> 26 #include <linux/irqchip/chained_irq.h> 27 #include <linux/of_irq.h> 28 #include <linux/io.h> 29 #include <linux/slab.h> 30 #include <linux/spinlock.h> 31 #include <linux/err.h> 32 33 #include "pinctrl-samsung.h" 34 #include "pinctrl-exynos.h" 35 36 struct exynos_irq_chip { 37 struct irq_chip chip; 38 39 u32 eint_con; 40 u32 eint_mask; 41 u32 eint_pend; 42 }; 43 44 static inline struct exynos_irq_chip *to_exynos_irq_chip(struct irq_chip *chip) 45 { 46 return container_of(chip, struct exynos_irq_chip, chip); 47 } 48 49 static const struct samsung_pin_bank_type bank_type_off = { 50 .fld_width = { 4, 1, 2, 2, 2, 2, }, 51 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, 52 }; 53 54 static const struct samsung_pin_bank_type bank_type_alive = { 55 .fld_width = { 4, 1, 2, 2, }, 56 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, 57 }; 58 59 /* Exynos5433 has the 4bit widths for PINCFG_TYPE_DRV bitfields. */ 60 static const struct samsung_pin_bank_type exynos5433_bank_type_off = { 61 .fld_width = { 4, 1, 2, 4, 2, 2, }, 62 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, 63 }; 64 65 static const struct samsung_pin_bank_type exynos5433_bank_type_alive = { 66 .fld_width = { 4, 1, 2, 4, }, 67 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, 68 }; 69 70 static void exynos_irq_mask(struct irq_data *irqd) 71 { 72 struct irq_chip *chip = irq_data_get_irq_chip(irqd); 73 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); 74 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 75 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; 76 unsigned long mask; 77 unsigned long flags; 78 79 spin_lock_irqsave(&bank->slock, flags); 80 81 mask = readl(bank->eint_base + reg_mask); 82 mask |= 1 << irqd->hwirq; 83 writel(mask, bank->eint_base + reg_mask); 84 85 spin_unlock_irqrestore(&bank->slock, flags); 86 } 87 88 static void exynos_irq_ack(struct irq_data *irqd) 89 { 90 struct irq_chip *chip = irq_data_get_irq_chip(irqd); 91 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); 92 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 93 unsigned long reg_pend = our_chip->eint_pend + bank->eint_offset; 94 95 writel(1 << irqd->hwirq, bank->eint_base + reg_pend); 96 } 97 98 static void exynos_irq_unmask(struct irq_data *irqd) 99 { 100 struct irq_chip *chip = irq_data_get_irq_chip(irqd); 101 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); 102 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 103 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; 104 unsigned long mask; 105 unsigned long flags; 106 107 /* 108 * Ack level interrupts right before unmask 109 * 110 * If we don't do this we'll get a double-interrupt. Level triggered 111 * interrupts must not fire an interrupt if the level is not 112 * _currently_ active, even if it was active while the interrupt was 113 * masked. 114 */ 115 if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK) 116 exynos_irq_ack(irqd); 117 118 spin_lock_irqsave(&bank->slock, flags); 119 120 mask = readl(bank->eint_base + reg_mask); 121 mask &= ~(1 << irqd->hwirq); 122 writel(mask, bank->eint_base + reg_mask); 123 124 spin_unlock_irqrestore(&bank->slock, flags); 125 } 126 127 static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type) 128 { 129 struct irq_chip *chip = irq_data_get_irq_chip(irqd); 130 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); 131 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 132 unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq; 133 unsigned int con, trig_type; 134 unsigned long reg_con = our_chip->eint_con + bank->eint_offset; 135 136 switch (type) { 137 case IRQ_TYPE_EDGE_RISING: 138 trig_type = EXYNOS_EINT_EDGE_RISING; 139 break; 140 case IRQ_TYPE_EDGE_FALLING: 141 trig_type = EXYNOS_EINT_EDGE_FALLING; 142 break; 143 case IRQ_TYPE_EDGE_BOTH: 144 trig_type = EXYNOS_EINT_EDGE_BOTH; 145 break; 146 case IRQ_TYPE_LEVEL_HIGH: 147 trig_type = EXYNOS_EINT_LEVEL_HIGH; 148 break; 149 case IRQ_TYPE_LEVEL_LOW: 150 trig_type = EXYNOS_EINT_LEVEL_LOW; 151 break; 152 default: 153 pr_err("unsupported external interrupt type\n"); 154 return -EINVAL; 155 } 156 157 if (type & IRQ_TYPE_EDGE_BOTH) 158 irq_set_handler_locked(irqd, handle_edge_irq); 159 else 160 irq_set_handler_locked(irqd, handle_level_irq); 161 162 con = readl(bank->eint_base + reg_con); 163 con &= ~(EXYNOS_EINT_CON_MASK << shift); 164 con |= trig_type << shift; 165 writel(con, bank->eint_base + reg_con); 166 167 return 0; 168 } 169 170 static int exynos_irq_request_resources(struct irq_data *irqd) 171 { 172 struct irq_chip *chip = irq_data_get_irq_chip(irqd); 173 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); 174 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 175 const struct samsung_pin_bank_type *bank_type = bank->type; 176 unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq; 177 unsigned long reg_con = our_chip->eint_con + bank->eint_offset; 178 unsigned long flags; 179 unsigned int mask; 180 unsigned int con; 181 int ret; 182 183 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irqd->hwirq); 184 if (ret) { 185 dev_err(bank->gpio_chip.parent, 186 "unable to lock pin %s-%lu IRQ\n", 187 bank->name, irqd->hwirq); 188 return ret; 189 } 190 191 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; 192 shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC]; 193 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; 194 195 spin_lock_irqsave(&bank->slock, flags); 196 197 con = readl(bank->eint_base + reg_con); 198 con &= ~(mask << shift); 199 con |= EXYNOS_EINT_FUNC << shift; 200 writel(con, bank->eint_base + reg_con); 201 202 spin_unlock_irqrestore(&bank->slock, flags); 203 204 exynos_irq_unmask(irqd); 205 206 return 0; 207 } 208 209 static void exynos_irq_release_resources(struct irq_data *irqd) 210 { 211 struct irq_chip *chip = irq_data_get_irq_chip(irqd); 212 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); 213 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 214 const struct samsung_pin_bank_type *bank_type = bank->type; 215 unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq; 216 unsigned long reg_con = our_chip->eint_con + bank->eint_offset; 217 unsigned long flags; 218 unsigned int mask; 219 unsigned int con; 220 221 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; 222 shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC]; 223 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; 224 225 exynos_irq_mask(irqd); 226 227 spin_lock_irqsave(&bank->slock, flags); 228 229 con = readl(bank->eint_base + reg_con); 230 con &= ~(mask << shift); 231 con |= FUNC_INPUT << shift; 232 writel(con, bank->eint_base + reg_con); 233 234 spin_unlock_irqrestore(&bank->slock, flags); 235 236 gpiochip_unlock_as_irq(&bank->gpio_chip, irqd->hwirq); 237 } 238 239 /* 240 * irq_chip for gpio interrupts. 241 */ 242 static struct exynos_irq_chip exynos_gpio_irq_chip = { 243 .chip = { 244 .name = "exynos_gpio_irq_chip", 245 .irq_unmask = exynos_irq_unmask, 246 .irq_mask = exynos_irq_mask, 247 .irq_ack = exynos_irq_ack, 248 .irq_set_type = exynos_irq_set_type, 249 .irq_request_resources = exynos_irq_request_resources, 250 .irq_release_resources = exynos_irq_release_resources, 251 }, 252 .eint_con = EXYNOS_GPIO_ECON_OFFSET, 253 .eint_mask = EXYNOS_GPIO_EMASK_OFFSET, 254 .eint_pend = EXYNOS_GPIO_EPEND_OFFSET, 255 }; 256 257 static int exynos_eint_irq_map(struct irq_domain *h, unsigned int virq, 258 irq_hw_number_t hw) 259 { 260 struct samsung_pin_bank *b = h->host_data; 261 262 irq_set_chip_data(virq, b); 263 irq_set_chip_and_handler(virq, &b->irq_chip->chip, 264 handle_level_irq); 265 return 0; 266 } 267 268 /* 269 * irq domain callbacks for external gpio and wakeup interrupt controllers. 270 */ 271 static const struct irq_domain_ops exynos_eint_irqd_ops = { 272 .map = exynos_eint_irq_map, 273 .xlate = irq_domain_xlate_twocell, 274 }; 275 276 static irqreturn_t exynos_eint_gpio_irq(int irq, void *data) 277 { 278 struct samsung_pinctrl_drv_data *d = data; 279 struct samsung_pin_bank *bank = d->pin_banks; 280 unsigned int svc, group, pin, virq; 281 282 svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET); 283 group = EXYNOS_SVC_GROUP(svc); 284 pin = svc & EXYNOS_SVC_NUM_MASK; 285 286 if (!group) 287 return IRQ_HANDLED; 288 bank += (group - 1); 289 290 virq = irq_linear_revmap(bank->irq_domain, pin); 291 if (!virq) 292 return IRQ_NONE; 293 generic_handle_irq(virq); 294 return IRQ_HANDLED; 295 } 296 297 struct exynos_eint_gpio_save { 298 u32 eint_con; 299 u32 eint_fltcon0; 300 u32 eint_fltcon1; 301 }; 302 303 /* 304 * exynos_eint_gpio_init() - setup handling of external gpio interrupts. 305 * @d: driver data of samsung pinctrl driver. 306 */ 307 static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d) 308 { 309 struct samsung_pin_bank *bank; 310 struct device *dev = d->dev; 311 int ret; 312 int i; 313 314 if (!d->irq) { 315 dev_err(dev, "irq number not available\n"); 316 return -EINVAL; 317 } 318 319 ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq, 320 0, dev_name(dev), d); 321 if (ret) { 322 dev_err(dev, "irq request failed\n"); 323 return -ENXIO; 324 } 325 326 bank = d->pin_banks; 327 for (i = 0; i < d->nr_banks; ++i, ++bank) { 328 if (bank->eint_type != EINT_TYPE_GPIO) 329 continue; 330 bank->irq_domain = irq_domain_add_linear(bank->of_node, 331 bank->nr_pins, &exynos_eint_irqd_ops, bank); 332 if (!bank->irq_domain) { 333 dev_err(dev, "gpio irq domain add failed\n"); 334 ret = -ENXIO; 335 goto err_domains; 336 } 337 338 bank->soc_priv = devm_kzalloc(d->dev, 339 sizeof(struct exynos_eint_gpio_save), GFP_KERNEL); 340 if (!bank->soc_priv) { 341 irq_domain_remove(bank->irq_domain); 342 ret = -ENOMEM; 343 goto err_domains; 344 } 345 346 bank->irq_chip = &exynos_gpio_irq_chip; 347 } 348 349 return 0; 350 351 err_domains: 352 for (--i, --bank; i >= 0; --i, --bank) { 353 if (bank->eint_type != EINT_TYPE_GPIO) 354 continue; 355 irq_domain_remove(bank->irq_domain); 356 } 357 358 return ret; 359 } 360 361 static u32 exynos_eint_wake_mask = 0xffffffff; 362 363 u32 exynos_get_eint_wake_mask(void) 364 { 365 return exynos_eint_wake_mask; 366 } 367 368 static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on) 369 { 370 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 371 unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq); 372 373 pr_info("wake %s for irq %d\n", on ? "enabled" : "disabled", irqd->irq); 374 375 if (!on) 376 exynos_eint_wake_mask |= bit; 377 else 378 exynos_eint_wake_mask &= ~bit; 379 380 return 0; 381 } 382 383 /* 384 * irq_chip for wakeup interrupts 385 */ 386 static struct exynos_irq_chip exynos4210_wkup_irq_chip __initdata = { 387 .chip = { 388 .name = "exynos4210_wkup_irq_chip", 389 .irq_unmask = exynos_irq_unmask, 390 .irq_mask = exynos_irq_mask, 391 .irq_ack = exynos_irq_ack, 392 .irq_set_type = exynos_irq_set_type, 393 .irq_set_wake = exynos_wkup_irq_set_wake, 394 .irq_request_resources = exynos_irq_request_resources, 395 .irq_release_resources = exynos_irq_release_resources, 396 }, 397 .eint_con = EXYNOS_WKUP_ECON_OFFSET, 398 .eint_mask = EXYNOS_WKUP_EMASK_OFFSET, 399 .eint_pend = EXYNOS_WKUP_EPEND_OFFSET, 400 }; 401 402 static struct exynos_irq_chip exynos7_wkup_irq_chip __initdata = { 403 .chip = { 404 .name = "exynos7_wkup_irq_chip", 405 .irq_unmask = exynos_irq_unmask, 406 .irq_mask = exynos_irq_mask, 407 .irq_ack = exynos_irq_ack, 408 .irq_set_type = exynos_irq_set_type, 409 .irq_set_wake = exynos_wkup_irq_set_wake, 410 .irq_request_resources = exynos_irq_request_resources, 411 .irq_release_resources = exynos_irq_release_resources, 412 }, 413 .eint_con = EXYNOS7_WKUP_ECON_OFFSET, 414 .eint_mask = EXYNOS7_WKUP_EMASK_OFFSET, 415 .eint_pend = EXYNOS7_WKUP_EPEND_OFFSET, 416 }; 417 418 /* list of external wakeup controllers supported */ 419 static const struct of_device_id exynos_wkup_irq_ids[] = { 420 { .compatible = "samsung,exynos4210-wakeup-eint", 421 .data = &exynos4210_wkup_irq_chip }, 422 { .compatible = "samsung,exynos7-wakeup-eint", 423 .data = &exynos7_wkup_irq_chip }, 424 { } 425 }; 426 427 /* interrupt handler for wakeup interrupts 0..15 */ 428 static void exynos_irq_eint0_15(struct irq_desc *desc) 429 { 430 struct exynos_weint_data *eintd = irq_desc_get_handler_data(desc); 431 struct samsung_pin_bank *bank = eintd->bank; 432 struct irq_chip *chip = irq_desc_get_chip(desc); 433 int eint_irq; 434 435 chained_irq_enter(chip, desc); 436 437 eint_irq = irq_linear_revmap(bank->irq_domain, eintd->irq); 438 generic_handle_irq(eint_irq); 439 440 chained_irq_exit(chip, desc); 441 } 442 443 static inline void exynos_irq_demux_eint(unsigned long pend, 444 struct irq_domain *domain) 445 { 446 unsigned int irq; 447 448 while (pend) { 449 irq = fls(pend) - 1; 450 generic_handle_irq(irq_find_mapping(domain, irq)); 451 pend &= ~(1 << irq); 452 } 453 } 454 455 /* interrupt handler for wakeup interrupt 16 */ 456 static void exynos_irq_demux_eint16_31(struct irq_desc *desc) 457 { 458 struct irq_chip *chip = irq_desc_get_chip(desc); 459 struct exynos_muxed_weint_data *eintd = irq_desc_get_handler_data(desc); 460 unsigned long pend; 461 unsigned long mask; 462 int i; 463 464 chained_irq_enter(chip, desc); 465 466 for (i = 0; i < eintd->nr_banks; ++i) { 467 struct samsung_pin_bank *b = eintd->banks[i]; 468 pend = readl(b->eint_base + b->irq_chip->eint_pend 469 + b->eint_offset); 470 mask = readl(b->eint_base + b->irq_chip->eint_mask 471 + b->eint_offset); 472 exynos_irq_demux_eint(pend & ~mask, b->irq_domain); 473 } 474 475 chained_irq_exit(chip, desc); 476 } 477 478 /* 479 * exynos_eint_wkup_init() - setup handling of external wakeup interrupts. 480 * @d: driver data of samsung pinctrl driver. 481 */ 482 static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) 483 { 484 struct device *dev = d->dev; 485 struct device_node *wkup_np = NULL; 486 struct device_node *np; 487 struct samsung_pin_bank *bank; 488 struct exynos_weint_data *weint_data; 489 struct exynos_muxed_weint_data *muxed_data; 490 struct exynos_irq_chip *irq_chip; 491 unsigned int muxed_banks = 0; 492 unsigned int i; 493 int idx, irq; 494 495 for_each_child_of_node(dev->of_node, np) { 496 const struct of_device_id *match; 497 498 match = of_match_node(exynos_wkup_irq_ids, np); 499 if (match) { 500 irq_chip = kmemdup(match->data, 501 sizeof(*irq_chip), GFP_KERNEL); 502 wkup_np = np; 503 break; 504 } 505 } 506 if (!wkup_np) 507 return -ENODEV; 508 509 bank = d->pin_banks; 510 for (i = 0; i < d->nr_banks; ++i, ++bank) { 511 if (bank->eint_type != EINT_TYPE_WKUP) 512 continue; 513 514 bank->irq_domain = irq_domain_add_linear(bank->of_node, 515 bank->nr_pins, &exynos_eint_irqd_ops, bank); 516 if (!bank->irq_domain) { 517 dev_err(dev, "wkup irq domain add failed\n"); 518 return -ENXIO; 519 } 520 521 bank->irq_chip = irq_chip; 522 523 if (!of_find_property(bank->of_node, "interrupts", NULL)) { 524 bank->eint_type = EINT_TYPE_WKUP_MUX; 525 ++muxed_banks; 526 continue; 527 } 528 529 weint_data = devm_kzalloc(dev, bank->nr_pins 530 * sizeof(*weint_data), GFP_KERNEL); 531 if (!weint_data) { 532 dev_err(dev, "could not allocate memory for weint_data\n"); 533 return -ENOMEM; 534 } 535 536 for (idx = 0; idx < bank->nr_pins; ++idx) { 537 irq = irq_of_parse_and_map(bank->of_node, idx); 538 if (!irq) { 539 dev_err(dev, "irq number for eint-%s-%d not found\n", 540 bank->name, idx); 541 continue; 542 } 543 weint_data[idx].irq = idx; 544 weint_data[idx].bank = bank; 545 irq_set_chained_handler_and_data(irq, 546 exynos_irq_eint0_15, 547 &weint_data[idx]); 548 } 549 } 550 551 if (!muxed_banks) 552 return 0; 553 554 irq = irq_of_parse_and_map(wkup_np, 0); 555 if (!irq) { 556 dev_err(dev, "irq number for muxed EINTs not found\n"); 557 return 0; 558 } 559 560 muxed_data = devm_kzalloc(dev, sizeof(*muxed_data) 561 + muxed_banks*sizeof(struct samsung_pin_bank *), GFP_KERNEL); 562 if (!muxed_data) { 563 dev_err(dev, "could not allocate memory for muxed_data\n"); 564 return -ENOMEM; 565 } 566 567 irq_set_chained_handler_and_data(irq, exynos_irq_demux_eint16_31, 568 muxed_data); 569 570 bank = d->pin_banks; 571 idx = 0; 572 for (i = 0; i < d->nr_banks; ++i, ++bank) { 573 if (bank->eint_type != EINT_TYPE_WKUP_MUX) 574 continue; 575 576 muxed_data->banks[idx++] = bank; 577 } 578 muxed_data->nr_banks = muxed_banks; 579 580 return 0; 581 } 582 583 static void exynos_pinctrl_suspend_bank( 584 struct samsung_pinctrl_drv_data *drvdata, 585 struct samsung_pin_bank *bank) 586 { 587 struct exynos_eint_gpio_save *save = bank->soc_priv; 588 void __iomem *regs = bank->eint_base; 589 590 save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET 591 + bank->eint_offset); 592 save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET 593 + 2 * bank->eint_offset); 594 save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET 595 + 2 * bank->eint_offset + 4); 596 597 pr_debug("%s: save con %#010x\n", bank->name, save->eint_con); 598 pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0); 599 pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1); 600 } 601 602 static void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) 603 { 604 struct samsung_pin_bank *bank = drvdata->pin_banks; 605 int i; 606 607 for (i = 0; i < drvdata->nr_banks; ++i, ++bank) 608 if (bank->eint_type == EINT_TYPE_GPIO) 609 exynos_pinctrl_suspend_bank(drvdata, bank); 610 } 611 612 static void exynos_pinctrl_resume_bank( 613 struct samsung_pinctrl_drv_data *drvdata, 614 struct samsung_pin_bank *bank) 615 { 616 struct exynos_eint_gpio_save *save = bank->soc_priv; 617 void __iomem *regs = bank->eint_base; 618 619 pr_debug("%s: con %#010x => %#010x\n", bank->name, 620 readl(regs + EXYNOS_GPIO_ECON_OFFSET 621 + bank->eint_offset), save->eint_con); 622 pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name, 623 readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET 624 + 2 * bank->eint_offset), save->eint_fltcon0); 625 pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name, 626 readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET 627 + 2 * bank->eint_offset + 4), save->eint_fltcon1); 628 629 writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET 630 + bank->eint_offset); 631 writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET 632 + 2 * bank->eint_offset); 633 writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET 634 + 2 * bank->eint_offset + 4); 635 } 636 637 static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) 638 { 639 struct samsung_pin_bank *bank = drvdata->pin_banks; 640 int i; 641 642 for (i = 0; i < drvdata->nr_banks; ++i, ++bank) 643 if (bank->eint_type == EINT_TYPE_GPIO) 644 exynos_pinctrl_resume_bank(drvdata, bank); 645 } 646 647 /* pin banks of s5pv210 pin-controller */ 648 static const struct samsung_pin_bank_data s5pv210_pin_bank[] __initconst = { 649 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 650 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04), 651 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), 652 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), 653 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), 654 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14), 655 EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18), 656 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe0", 0x1c), 657 EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpe1", 0x20), 658 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpf0", 0x24), 659 EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpf1", 0x28), 660 EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpf2", 0x2c), 661 EXYNOS_PIN_BANK_EINTG(6, 0x180, "gpf3", 0x30), 662 EXYNOS_PIN_BANK_EINTG(7, 0x1a0, "gpg0", 0x34), 663 EXYNOS_PIN_BANK_EINTG(7, 0x1c0, "gpg1", 0x38), 664 EXYNOS_PIN_BANK_EINTG(7, 0x1e0, "gpg2", 0x3c), 665 EXYNOS_PIN_BANK_EINTG(7, 0x200, "gpg3", 0x40), 666 EXYNOS_PIN_BANK_EINTN(7, 0x220, "gpi"), 667 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x44), 668 EXYNOS_PIN_BANK_EINTG(6, 0x260, "gpj1", 0x48), 669 EXYNOS_PIN_BANK_EINTG(8, 0x280, "gpj2", 0x4c), 670 EXYNOS_PIN_BANK_EINTG(8, 0x2a0, "gpj3", 0x50), 671 EXYNOS_PIN_BANK_EINTG(5, 0x2c0, "gpj4", 0x54), 672 EXYNOS_PIN_BANK_EINTN(8, 0x2e0, "mp01"), 673 EXYNOS_PIN_BANK_EINTN(4, 0x300, "mp02"), 674 EXYNOS_PIN_BANK_EINTN(8, 0x320, "mp03"), 675 EXYNOS_PIN_BANK_EINTN(8, 0x340, "mp04"), 676 EXYNOS_PIN_BANK_EINTN(8, 0x360, "mp05"), 677 EXYNOS_PIN_BANK_EINTN(8, 0x380, "mp06"), 678 EXYNOS_PIN_BANK_EINTN(8, 0x3a0, "mp07"), 679 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gph0", 0x00), 680 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gph1", 0x04), 681 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gph2", 0x08), 682 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gph3", 0x0c), 683 }; 684 685 const struct samsung_pin_ctrl s5pv210_pin_ctrl[] __initconst = { 686 { 687 /* pin-controller instance 0 data */ 688 .pin_banks = s5pv210_pin_bank, 689 .nr_banks = ARRAY_SIZE(s5pv210_pin_bank), 690 .eint_gpio_init = exynos_eint_gpio_init, 691 .eint_wkup_init = exynos_eint_wkup_init, 692 .suspend = exynos_pinctrl_suspend, 693 .resume = exynos_pinctrl_resume, 694 }, 695 }; 696 697 /* pin banks of exynos3250 pin-controller 0 */ 698 static const struct samsung_pin_bank_data exynos3250_pin_banks0[] __initconst = { 699 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 700 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 701 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), 702 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), 703 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), 704 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14), 705 EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpd1", 0x18), 706 }; 707 708 /* pin banks of exynos3250 pin-controller 1 */ 709 static const struct samsung_pin_bank_data exynos3250_pin_banks1[] __initconst = { 710 EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpe0"), 711 EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpe1"), 712 EXYNOS_PIN_BANK_EINTN(3, 0x180, "gpe2"), 713 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08), 714 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), 715 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), 716 EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpl0", 0x18), 717 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24), 718 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28), 719 EXYNOS_PIN_BANK_EINTG(5, 0x2a0, "gpm2", 0x2c), 720 EXYNOS_PIN_BANK_EINTG(8, 0x2c0, "gpm3", 0x30), 721 EXYNOS_PIN_BANK_EINTG(8, 0x2e0, "gpm4", 0x34), 722 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00), 723 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04), 724 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08), 725 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c), 726 }; 727 728 /* 729 * Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes 730 * two gpio/pin-mux/pinconfig controllers. 731 */ 732 const struct samsung_pin_ctrl exynos3250_pin_ctrl[] __initconst = { 733 { 734 /* pin-controller instance 0 data */ 735 .pin_banks = exynos3250_pin_banks0, 736 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks0), 737 .eint_gpio_init = exynos_eint_gpio_init, 738 .suspend = exynos_pinctrl_suspend, 739 .resume = exynos_pinctrl_resume, 740 }, { 741 /* pin-controller instance 1 data */ 742 .pin_banks = exynos3250_pin_banks1, 743 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks1), 744 .eint_gpio_init = exynos_eint_gpio_init, 745 .eint_wkup_init = exynos_eint_wkup_init, 746 .suspend = exynos_pinctrl_suspend, 747 .resume = exynos_pinctrl_resume, 748 }, 749 }; 750 751 /* pin banks of exynos4210 pin-controller 0 */ 752 static const struct samsung_pin_bank_data exynos4210_pin_banks0[] __initconst = { 753 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 754 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 755 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), 756 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), 757 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), 758 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14), 759 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18), 760 EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0", 0x1c), 761 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20), 762 EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2", 0x24), 763 EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3", 0x28), 764 EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4", 0x2c), 765 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30), 766 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34), 767 EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38), 768 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c), 769 }; 770 771 /* pin banks of exynos4210 pin-controller 1 */ 772 static const struct samsung_pin_bank_data exynos4210_pin_banks1[] __initconst = { 773 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00), 774 EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04), 775 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08), 776 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), 777 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), 778 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14), 779 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0", 0x18), 780 EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1", 0x1c), 781 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20), 782 EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"), 783 EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"), 784 EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"), 785 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"), 786 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"), 787 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"), 788 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"), 789 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), 790 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), 791 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), 792 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), 793 }; 794 795 /* pin banks of exynos4210 pin-controller 2 */ 796 static const struct samsung_pin_bank_data exynos4210_pin_banks2[] __initconst = { 797 EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"), 798 }; 799 800 /* 801 * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes 802 * three gpio/pin-mux/pinconfig controllers. 803 */ 804 const struct samsung_pin_ctrl exynos4210_pin_ctrl[] __initconst = { 805 { 806 /* pin-controller instance 0 data */ 807 .pin_banks = exynos4210_pin_banks0, 808 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks0), 809 .eint_gpio_init = exynos_eint_gpio_init, 810 .suspend = exynos_pinctrl_suspend, 811 .resume = exynos_pinctrl_resume, 812 }, { 813 /* pin-controller instance 1 data */ 814 .pin_banks = exynos4210_pin_banks1, 815 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks1), 816 .eint_gpio_init = exynos_eint_gpio_init, 817 .eint_wkup_init = exynos_eint_wkup_init, 818 .suspend = exynos_pinctrl_suspend, 819 .resume = exynos_pinctrl_resume, 820 }, { 821 /* pin-controller instance 2 data */ 822 .pin_banks = exynos4210_pin_banks2, 823 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks2), 824 }, 825 }; 826 827 /* pin banks of exynos4x12 pin-controller 0 */ 828 static const struct samsung_pin_bank_data exynos4x12_pin_banks0[] __initconst = { 829 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 830 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 831 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), 832 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), 833 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), 834 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14), 835 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18), 836 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30), 837 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34), 838 EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38), 839 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c), 840 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x40), 841 EXYNOS_PIN_BANK_EINTG(5, 0x260, "gpj1", 0x44), 842 }; 843 844 /* pin banks of exynos4x12 pin-controller 1 */ 845 static const struct samsung_pin_bank_data exynos4x12_pin_banks1[] __initconst = { 846 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08), 847 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), 848 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), 849 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14), 850 EXYNOS_PIN_BANK_EINTG(7, 0x0C0, "gpl0", 0x18), 851 EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpl1", 0x1c), 852 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20), 853 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24), 854 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28), 855 EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c), 856 EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30), 857 EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34), 858 EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"), 859 EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"), 860 EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"), 861 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"), 862 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"), 863 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"), 864 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"), 865 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), 866 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), 867 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), 868 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), 869 }; 870 871 /* pin banks of exynos4x12 pin-controller 2 */ 872 static const struct samsung_pin_bank_data exynos4x12_pin_banks2[] __initconst = { 873 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), 874 }; 875 876 /* pin banks of exynos4x12 pin-controller 3 */ 877 static const struct samsung_pin_bank_data exynos4x12_pin_banks3[] __initconst = { 878 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), 879 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), 880 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08), 881 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv3", 0x0c), 882 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpv4", 0x10), 883 }; 884 885 /* 886 * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes 887 * four gpio/pin-mux/pinconfig controllers. 888 */ 889 const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] __initconst = { 890 { 891 /* pin-controller instance 0 data */ 892 .pin_banks = exynos4x12_pin_banks0, 893 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks0), 894 .eint_gpio_init = exynos_eint_gpio_init, 895 .suspend = exynos_pinctrl_suspend, 896 .resume = exynos_pinctrl_resume, 897 }, { 898 /* pin-controller instance 1 data */ 899 .pin_banks = exynos4x12_pin_banks1, 900 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks1), 901 .eint_gpio_init = exynos_eint_gpio_init, 902 .eint_wkup_init = exynos_eint_wkup_init, 903 .suspend = exynos_pinctrl_suspend, 904 .resume = exynos_pinctrl_resume, 905 }, { 906 /* pin-controller instance 2 data */ 907 .pin_banks = exynos4x12_pin_banks2, 908 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks2), 909 .eint_gpio_init = exynos_eint_gpio_init, 910 .suspend = exynos_pinctrl_suspend, 911 .resume = exynos_pinctrl_resume, 912 }, { 913 /* pin-controller instance 3 data */ 914 .pin_banks = exynos4x12_pin_banks3, 915 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks3), 916 .eint_gpio_init = exynos_eint_gpio_init, 917 .suspend = exynos_pinctrl_suspend, 918 .resume = exynos_pinctrl_resume, 919 }, 920 }; 921 922 /* pin banks of exynos4415 pin-controller 0 */ 923 static const struct samsung_pin_bank_data exynos4415_pin_banks0[] = { 924 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 925 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 926 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), 927 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), 928 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), 929 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14), 930 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18), 931 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30), 932 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34), 933 EXYNOS_PIN_BANK_EINTG(1, 0x1C0, "gpf2", 0x38), 934 }; 935 936 /* pin banks of exynos4415 pin-controller 1 */ 937 static const struct samsung_pin_bank_data exynos4415_pin_banks1[] = { 938 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08), 939 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), 940 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), 941 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14), 942 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpl0", 0x18), 943 EXYNOS_PIN_BANK_EINTN(6, 0x120, "mp00"), 944 EXYNOS_PIN_BANK_EINTN(4, 0x140, "mp01"), 945 EXYNOS_PIN_BANK_EINTN(6, 0x160, "mp02"), 946 EXYNOS_PIN_BANK_EINTN(8, 0x180, "mp03"), 947 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "mp04"), 948 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "mp05"), 949 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "mp06"), 950 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24), 951 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28), 952 EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c), 953 EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30), 954 EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34), 955 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), 956 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), 957 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), 958 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), 959 }; 960 961 /* pin banks of exynos4415 pin-controller 2 */ 962 static const struct samsung_pin_bank_data exynos4415_pin_banks2[] = { 963 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), 964 EXYNOS_PIN_BANK_EINTN(2, 0x000, "etc1"), 965 }; 966 967 /* 968 * Samsung pinctrl driver data for Exynos4415 SoC. Exynos4415 SoC includes 969 * three gpio/pin-mux/pinconfig controllers. 970 */ 971 const struct samsung_pin_ctrl exynos4415_pin_ctrl[] = { 972 { 973 /* pin-controller instance 0 data */ 974 .pin_banks = exynos4415_pin_banks0, 975 .nr_banks = ARRAY_SIZE(exynos4415_pin_banks0), 976 .eint_gpio_init = exynos_eint_gpio_init, 977 .suspend = exynos_pinctrl_suspend, 978 .resume = exynos_pinctrl_resume, 979 }, { 980 /* pin-controller instance 1 data */ 981 .pin_banks = exynos4415_pin_banks1, 982 .nr_banks = ARRAY_SIZE(exynos4415_pin_banks1), 983 .eint_gpio_init = exynos_eint_gpio_init, 984 .eint_wkup_init = exynos_eint_wkup_init, 985 .suspend = exynos_pinctrl_suspend, 986 .resume = exynos_pinctrl_resume, 987 }, { 988 /* pin-controller instance 2 data */ 989 .pin_banks = exynos4415_pin_banks2, 990 .nr_banks = ARRAY_SIZE(exynos4415_pin_banks2), 991 .eint_gpio_init = exynos_eint_gpio_init, 992 .suspend = exynos_pinctrl_suspend, 993 .resume = exynos_pinctrl_resume, 994 }, 995 }; 996 997 /* pin banks of exynos5250 pin-controller 0 */ 998 static const struct samsung_pin_bank_data exynos5250_pin_banks0[] __initconst = { 999 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 1000 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 1001 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), 1002 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), 1003 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10), 1004 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14), 1005 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18), 1006 EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c), 1007 EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20), 1008 EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24), 1009 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28), 1010 EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c), 1011 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30), 1012 EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34), 1013 EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"), 1014 EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"), 1015 EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"), 1016 EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"), 1017 EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"), 1018 EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"), 1019 EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"), 1020 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), 1021 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), 1022 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), 1023 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), 1024 }; 1025 1026 /* pin banks of exynos5250 pin-controller 1 */ 1027 static const struct samsung_pin_bank_data exynos5250_pin_banks1[] __initconst = { 1028 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00), 1029 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04), 1030 EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08), 1031 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c), 1032 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10), 1033 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14), 1034 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18), 1035 EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c), 1036 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20), 1037 }; 1038 1039 /* pin banks of exynos5250 pin-controller 2 */ 1040 static const struct samsung_pin_bank_data exynos5250_pin_banks2[] __initconst = { 1041 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), 1042 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), 1043 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08), 1044 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c), 1045 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10), 1046 }; 1047 1048 /* pin banks of exynos5250 pin-controller 3 */ 1049 static const struct samsung_pin_bank_data exynos5250_pin_banks3[] __initconst = { 1050 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), 1051 }; 1052 1053 /* 1054 * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes 1055 * four gpio/pin-mux/pinconfig controllers. 1056 */ 1057 const struct samsung_pin_ctrl exynos5250_pin_ctrl[] __initconst = { 1058 { 1059 /* pin-controller instance 0 data */ 1060 .pin_banks = exynos5250_pin_banks0, 1061 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks0), 1062 .eint_gpio_init = exynos_eint_gpio_init, 1063 .eint_wkup_init = exynos_eint_wkup_init, 1064 .suspend = exynos_pinctrl_suspend, 1065 .resume = exynos_pinctrl_resume, 1066 }, { 1067 /* pin-controller instance 1 data */ 1068 .pin_banks = exynos5250_pin_banks1, 1069 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks1), 1070 .eint_gpio_init = exynos_eint_gpio_init, 1071 .suspend = exynos_pinctrl_suspend, 1072 .resume = exynos_pinctrl_resume, 1073 }, { 1074 /* pin-controller instance 2 data */ 1075 .pin_banks = exynos5250_pin_banks2, 1076 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks2), 1077 .eint_gpio_init = exynos_eint_gpio_init, 1078 .suspend = exynos_pinctrl_suspend, 1079 .resume = exynos_pinctrl_resume, 1080 }, { 1081 /* pin-controller instance 3 data */ 1082 .pin_banks = exynos5250_pin_banks3, 1083 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks3), 1084 .eint_gpio_init = exynos_eint_gpio_init, 1085 .suspend = exynos_pinctrl_suspend, 1086 .resume = exynos_pinctrl_resume, 1087 }, 1088 }; 1089 1090 /* pin banks of exynos5260 pin-controller 0 */ 1091 static const struct samsung_pin_bank_data exynos5260_pin_banks0[] __initconst = { 1092 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00), 1093 EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04), 1094 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), 1095 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), 1096 EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10), 1097 EXYNOS_PIN_BANK_EINTG(5, 0x0a0, "gpb2", 0x14), 1098 EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpb3", 0x18), 1099 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpb4", 0x1c), 1100 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20), 1101 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24), 1102 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28), 1103 EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c), 1104 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30), 1105 EXYNOS_PIN_BANK_EINTG(5, 0x1a0, "gpe1", 0x34), 1106 EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38), 1107 EXYNOS_PIN_BANK_EINTG(8, 0x1e0, "gpf1", 0x3c), 1108 EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40), 1109 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00), 1110 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04), 1111 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08), 1112 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c), 1113 }; 1114 1115 /* pin banks of exynos5260 pin-controller 1 */ 1116 static const struct samsung_pin_bank_data exynos5260_pin_banks1[] __initconst = { 1117 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00), 1118 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04), 1119 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08), 1120 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c), 1121 EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10), 1122 }; 1123 1124 /* pin banks of exynos5260 pin-controller 2 */ 1125 static const struct samsung_pin_bank_data exynos5260_pin_banks2[] __initconst = { 1126 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), 1127 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), 1128 }; 1129 1130 /* 1131 * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes 1132 * three gpio/pin-mux/pinconfig controllers. 1133 */ 1134 const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = { 1135 { 1136 /* pin-controller instance 0 data */ 1137 .pin_banks = exynos5260_pin_banks0, 1138 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks0), 1139 .eint_gpio_init = exynos_eint_gpio_init, 1140 .eint_wkup_init = exynos_eint_wkup_init, 1141 }, { 1142 /* pin-controller instance 1 data */ 1143 .pin_banks = exynos5260_pin_banks1, 1144 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks1), 1145 .eint_gpio_init = exynos_eint_gpio_init, 1146 }, { 1147 /* pin-controller instance 2 data */ 1148 .pin_banks = exynos5260_pin_banks2, 1149 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks2), 1150 .eint_gpio_init = exynos_eint_gpio_init, 1151 }, 1152 }; 1153 1154 /* pin banks of exynos5410 pin-controller 0 */ 1155 static const struct samsung_pin_bank_data exynos5410_pin_banks0[] __initconst = { 1156 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 1157 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 1158 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), 1159 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), 1160 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10), 1161 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14), 1162 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18), 1163 EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c), 1164 EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc3", 0x20), 1165 EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc1", 0x24), 1166 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc2", 0x28), 1167 EXYNOS_PIN_BANK_EINTN(2, 0x160, "gpm5"), 1168 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x2c), 1169 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpe0", 0x30), 1170 EXYNOS_PIN_BANK_EINTG(2, 0x1C0, "gpe1", 0x34), 1171 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf0", 0x38), 1172 EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpf1", 0x3c), 1173 EXYNOS_PIN_BANK_EINTG(8, 0x220, "gpg0", 0x40), 1174 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpg1", 0x44), 1175 EXYNOS_PIN_BANK_EINTG(2, 0x260, "gpg2", 0x48), 1176 EXYNOS_PIN_BANK_EINTG(4, 0x280, "gph0", 0x4c), 1177 EXYNOS_PIN_BANK_EINTG(8, 0x2A0, "gph1", 0x50), 1178 EXYNOS_PIN_BANK_EINTN(8, 0x2C0, "gpm7"), 1179 EXYNOS_PIN_BANK_EINTN(6, 0x2E0, "gpy0"), 1180 EXYNOS_PIN_BANK_EINTN(4, 0x300, "gpy1"), 1181 EXYNOS_PIN_BANK_EINTN(6, 0x320, "gpy2"), 1182 EXYNOS_PIN_BANK_EINTN(8, 0x340, "gpy3"), 1183 EXYNOS_PIN_BANK_EINTN(8, 0x360, "gpy4"), 1184 EXYNOS_PIN_BANK_EINTN(8, 0x380, "gpy5"), 1185 EXYNOS_PIN_BANK_EINTN(8, 0x3A0, "gpy6"), 1186 EXYNOS_PIN_BANK_EINTN(8, 0x3C0, "gpy7"), 1187 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), 1188 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), 1189 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), 1190 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), 1191 }; 1192 1193 /* pin banks of exynos5410 pin-controller 1 */ 1194 static const struct samsung_pin_bank_data exynos5410_pin_banks1[] __initconst = { 1195 EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpj0", 0x00), 1196 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpj1", 0x04), 1197 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpj2", 0x08), 1198 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpj3", 0x0c), 1199 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpj4", 0x10), 1200 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpk0", 0x14), 1201 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpk1", 0x18), 1202 EXYNOS_PIN_BANK_EINTG(8, 0x0E0, "gpk2", 0x1c), 1203 EXYNOS_PIN_BANK_EINTG(7, 0x100, "gpk3", 0x20), 1204 }; 1205 1206 /* pin banks of exynos5410 pin-controller 2 */ 1207 static const struct samsung_pin_bank_data exynos5410_pin_banks2[] __initconst = { 1208 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), 1209 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), 1210 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08), 1211 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c), 1212 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10), 1213 }; 1214 1215 /* pin banks of exynos5410 pin-controller 3 */ 1216 static const struct samsung_pin_bank_data exynos5410_pin_banks3[] __initconst = { 1217 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), 1218 }; 1219 1220 /* 1221 * Samsung pinctrl driver data for Exynos5410 SoC. Exynos5410 SoC includes 1222 * four gpio/pin-mux/pinconfig controllers. 1223 */ 1224 const struct samsung_pin_ctrl exynos5410_pin_ctrl[] __initconst = { 1225 { 1226 /* pin-controller instance 0 data */ 1227 .pin_banks = exynos5410_pin_banks0, 1228 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks0), 1229 .eint_gpio_init = exynos_eint_gpio_init, 1230 .eint_wkup_init = exynos_eint_wkup_init, 1231 .suspend = exynos_pinctrl_suspend, 1232 .resume = exynos_pinctrl_resume, 1233 }, { 1234 /* pin-controller instance 1 data */ 1235 .pin_banks = exynos5410_pin_banks1, 1236 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks1), 1237 .eint_gpio_init = exynos_eint_gpio_init, 1238 .suspend = exynos_pinctrl_suspend, 1239 .resume = exynos_pinctrl_resume, 1240 }, { 1241 /* pin-controller instance 2 data */ 1242 .pin_banks = exynos5410_pin_banks2, 1243 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks2), 1244 .eint_gpio_init = exynos_eint_gpio_init, 1245 .suspend = exynos_pinctrl_suspend, 1246 .resume = exynos_pinctrl_resume, 1247 }, { 1248 /* pin-controller instance 3 data */ 1249 .pin_banks = exynos5410_pin_banks3, 1250 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks3), 1251 .eint_gpio_init = exynos_eint_gpio_init, 1252 .suspend = exynos_pinctrl_suspend, 1253 .resume = exynos_pinctrl_resume, 1254 }, 1255 }; 1256 1257 /* pin banks of exynos5420 pin-controller 0 */ 1258 static const struct samsung_pin_bank_data exynos5420_pin_banks0[] __initconst = { 1259 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00), 1260 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), 1261 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), 1262 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), 1263 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), 1264 }; 1265 1266 /* pin banks of exynos5420 pin-controller 1 */ 1267 static const struct samsung_pin_bank_data exynos5420_pin_banks1[] __initconst = { 1268 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00), 1269 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04), 1270 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08), 1271 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c), 1272 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpc4", 0x10), 1273 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpd1", 0x14), 1274 EXYNOS_PIN_BANK_EINTN(6, 0x0C0, "gpy0"), 1275 EXYNOS_PIN_BANK_EINTN(4, 0x0E0, "gpy1"), 1276 EXYNOS_PIN_BANK_EINTN(6, 0x100, "gpy2"), 1277 EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpy3"), 1278 EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpy4"), 1279 EXYNOS_PIN_BANK_EINTN(8, 0x160, "gpy5"), 1280 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy6"), 1281 }; 1282 1283 /* pin banks of exynos5420 pin-controller 2 */ 1284 static const struct samsung_pin_bank_data exynos5420_pin_banks2[] __initconst = { 1285 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00), 1286 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04), 1287 EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08), 1288 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpf1", 0x0c), 1289 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10), 1290 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14), 1291 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18), 1292 EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gpj4", 0x1c), 1293 }; 1294 1295 /* pin banks of exynos5420 pin-controller 3 */ 1296 static const struct samsung_pin_bank_data exynos5420_pin_banks3[] __initconst = { 1297 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 1298 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 1299 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), 1300 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), 1301 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10), 1302 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14), 1303 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18), 1304 EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpb4", 0x1c), 1305 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph0", 0x20), 1306 }; 1307 1308 /* pin banks of exynos5420 pin-controller 4 */ 1309 static const struct samsung_pin_bank_data exynos5420_pin_banks4[] __initconst = { 1310 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), 1311 }; 1312 1313 /* 1314 * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes 1315 * four gpio/pin-mux/pinconfig controllers. 1316 */ 1317 const struct samsung_pin_ctrl exynos5420_pin_ctrl[] __initconst = { 1318 { 1319 /* pin-controller instance 0 data */ 1320 .pin_banks = exynos5420_pin_banks0, 1321 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks0), 1322 .eint_gpio_init = exynos_eint_gpio_init, 1323 .eint_wkup_init = exynos_eint_wkup_init, 1324 }, { 1325 /* pin-controller instance 1 data */ 1326 .pin_banks = exynos5420_pin_banks1, 1327 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks1), 1328 .eint_gpio_init = exynos_eint_gpio_init, 1329 }, { 1330 /* pin-controller instance 2 data */ 1331 .pin_banks = exynos5420_pin_banks2, 1332 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks2), 1333 .eint_gpio_init = exynos_eint_gpio_init, 1334 }, { 1335 /* pin-controller instance 3 data */ 1336 .pin_banks = exynos5420_pin_banks3, 1337 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks3), 1338 .eint_gpio_init = exynos_eint_gpio_init, 1339 }, { 1340 /* pin-controller instance 4 data */ 1341 .pin_banks = exynos5420_pin_banks4, 1342 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks4), 1343 .eint_gpio_init = exynos_eint_gpio_init, 1344 }, 1345 }; 1346 1347 /* pin banks of exynos5433 pin-controller - ALIVE */ 1348 static const struct samsung_pin_bank_data exynos5433_pin_banks0[] = { 1349 EXYNOS5433_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), 1350 EXYNOS5433_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), 1351 EXYNOS5433_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), 1352 EXYNOS5433_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), 1353 EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x020, "gpf1", 0x1004, 1), 1354 EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x040, "gpf2", 0x1008, 1), 1355 EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x060, "gpf3", 0x100c, 1), 1356 EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x080, "gpf4", 0x1010, 1), 1357 EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x0a0, "gpf5", 0x1014, 1), 1358 }; 1359 1360 /* pin banks of exynos5433 pin-controller - AUD */ 1361 static const struct samsung_pin_bank_data exynos5433_pin_banks1[] = { 1362 EXYNOS5433_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), 1363 EXYNOS5433_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), 1364 }; 1365 1366 /* pin banks of exynos5433 pin-controller - CPIF */ 1367 static const struct samsung_pin_bank_data exynos5433_pin_banks2[] = { 1368 EXYNOS5433_PIN_BANK_EINTG(2, 0x000, "gpv6", 0x00), 1369 }; 1370 1371 /* pin banks of exynos5433 pin-controller - eSE */ 1372 static const struct samsung_pin_bank_data exynos5433_pin_banks3[] = { 1373 EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj2", 0x00), 1374 }; 1375 1376 /* pin banks of exynos5433 pin-controller - FINGER */ 1377 static const struct samsung_pin_bank_data exynos5433_pin_banks4[] = { 1378 EXYNOS5433_PIN_BANK_EINTG(4, 0x000, "gpd5", 0x00), 1379 }; 1380 1381 /* pin banks of exynos5433 pin-controller - FSYS */ 1382 static const struct samsung_pin_bank_data exynos5433_pin_banks5[] = { 1383 EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gph1", 0x00), 1384 EXYNOS5433_PIN_BANK_EINTG(7, 0x020, "gpr4", 0x04), 1385 EXYNOS5433_PIN_BANK_EINTG(5, 0x040, "gpr0", 0x08), 1386 EXYNOS5433_PIN_BANK_EINTG(8, 0x060, "gpr1", 0x0c), 1387 EXYNOS5433_PIN_BANK_EINTG(2, 0x080, "gpr2", 0x10), 1388 EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpr3", 0x14), 1389 }; 1390 1391 /* pin banks of exynos5433 pin-controller - IMEM */ 1392 static const struct samsung_pin_bank_data exynos5433_pin_banks6[] = { 1393 EXYNOS5433_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00), 1394 }; 1395 1396 /* pin banks of exynos5433 pin-controller - NFC */ 1397 static const struct samsung_pin_bank_data exynos5433_pin_banks7[] = { 1398 EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00), 1399 }; 1400 1401 /* pin banks of exynos5433 pin-controller - PERIC */ 1402 static const struct samsung_pin_bank_data exynos5433_pin_banks8[] = { 1403 EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gpv7", 0x00), 1404 EXYNOS5433_PIN_BANK_EINTG(5, 0x020, "gpb0", 0x04), 1405 EXYNOS5433_PIN_BANK_EINTG(8, 0x040, "gpc0", 0x08), 1406 EXYNOS5433_PIN_BANK_EINTG(2, 0x060, "gpc1", 0x0c), 1407 EXYNOS5433_PIN_BANK_EINTG(6, 0x080, "gpc2", 0x10), 1408 EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpc3", 0x14), 1409 EXYNOS5433_PIN_BANK_EINTG(2, 0x0c0, "gpg0", 0x18), 1410 EXYNOS5433_PIN_BANK_EINTG(4, 0x0e0, "gpd0", 0x1c), 1411 EXYNOS5433_PIN_BANK_EINTG(6, 0x100, "gpd1", 0x20), 1412 EXYNOS5433_PIN_BANK_EINTG(8, 0x120, "gpd2", 0x24), 1413 EXYNOS5433_PIN_BANK_EINTG(5, 0x140, "gpd4", 0x28), 1414 EXYNOS5433_PIN_BANK_EINTG(2, 0x160, "gpd8", 0x2c), 1415 EXYNOS5433_PIN_BANK_EINTG(7, 0x180, "gpd6", 0x30), 1416 EXYNOS5433_PIN_BANK_EINTG(3, 0x1a0, "gpd7", 0x34), 1417 EXYNOS5433_PIN_BANK_EINTG(5, 0x1c0, "gpg1", 0x38), 1418 EXYNOS5433_PIN_BANK_EINTG(2, 0x1e0, "gpg2", 0x3c), 1419 EXYNOS5433_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40), 1420 }; 1421 1422 /* pin banks of exynos5433 pin-controller - TOUCH */ 1423 static const struct samsung_pin_bank_data exynos5433_pin_banks9[] = { 1424 EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00), 1425 }; 1426 1427 /* 1428 * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes 1429 * ten gpio/pin-mux/pinconfig controllers. 1430 */ 1431 const struct samsung_pin_ctrl exynos5433_pin_ctrl[] = { 1432 { 1433 /* pin-controller instance 0 data */ 1434 .pin_banks = exynos5433_pin_banks0, 1435 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks0), 1436 .eint_wkup_init = exynos_eint_wkup_init, 1437 .suspend = exynos_pinctrl_suspend, 1438 .resume = exynos_pinctrl_resume, 1439 .nr_ext_resources = 1, 1440 }, { 1441 /* pin-controller instance 1 data */ 1442 .pin_banks = exynos5433_pin_banks1, 1443 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks1), 1444 .eint_gpio_init = exynos_eint_gpio_init, 1445 .suspend = exynos_pinctrl_suspend, 1446 .resume = exynos_pinctrl_resume, 1447 }, { 1448 /* pin-controller instance 2 data */ 1449 .pin_banks = exynos5433_pin_banks2, 1450 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks2), 1451 .eint_gpio_init = exynos_eint_gpio_init, 1452 .suspend = exynos_pinctrl_suspend, 1453 .resume = exynos_pinctrl_resume, 1454 }, { 1455 /* pin-controller instance 3 data */ 1456 .pin_banks = exynos5433_pin_banks3, 1457 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks3), 1458 .eint_gpio_init = exynos_eint_gpio_init, 1459 .suspend = exynos_pinctrl_suspend, 1460 .resume = exynos_pinctrl_resume, 1461 }, { 1462 /* pin-controller instance 4 data */ 1463 .pin_banks = exynos5433_pin_banks4, 1464 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks4), 1465 .eint_gpio_init = exynos_eint_gpio_init, 1466 .suspend = exynos_pinctrl_suspend, 1467 .resume = exynos_pinctrl_resume, 1468 }, { 1469 /* pin-controller instance 5 data */ 1470 .pin_banks = exynos5433_pin_banks5, 1471 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks5), 1472 .eint_gpio_init = exynos_eint_gpio_init, 1473 .suspend = exynos_pinctrl_suspend, 1474 .resume = exynos_pinctrl_resume, 1475 }, { 1476 /* pin-controller instance 6 data */ 1477 .pin_banks = exynos5433_pin_banks6, 1478 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks6), 1479 .eint_gpio_init = exynos_eint_gpio_init, 1480 .suspend = exynos_pinctrl_suspend, 1481 .resume = exynos_pinctrl_resume, 1482 }, { 1483 /* pin-controller instance 7 data */ 1484 .pin_banks = exynos5433_pin_banks7, 1485 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks7), 1486 .eint_gpio_init = exynos_eint_gpio_init, 1487 .suspend = exynos_pinctrl_suspend, 1488 .resume = exynos_pinctrl_resume, 1489 }, { 1490 /* pin-controller instance 8 data */ 1491 .pin_banks = exynos5433_pin_banks8, 1492 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks8), 1493 .eint_gpio_init = exynos_eint_gpio_init, 1494 .suspend = exynos_pinctrl_suspend, 1495 .resume = exynos_pinctrl_resume, 1496 }, { 1497 /* pin-controller instance 9 data */ 1498 .pin_banks = exynos5433_pin_banks9, 1499 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks9), 1500 .eint_gpio_init = exynos_eint_gpio_init, 1501 .suspend = exynos_pinctrl_suspend, 1502 .resume = exynos_pinctrl_resume, 1503 }, 1504 }; 1505 1506 /* pin banks of exynos7 pin-controller - ALIVE */ 1507 static const struct samsung_pin_bank_data exynos7_pin_banks0[] __initconst = { 1508 EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), 1509 EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), 1510 EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), 1511 EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), 1512 }; 1513 1514 /* pin banks of exynos7 pin-controller - BUS0 */ 1515 static const struct samsung_pin_bank_data exynos7_pin_banks1[] __initconst = { 1516 EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), 1517 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc0", 0x04), 1518 EXYNOS_PIN_BANK_EINTG(2, 0x040, "gpc1", 0x08), 1519 EXYNOS_PIN_BANK_EINTG(6, 0x060, "gpc2", 0x0c), 1520 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10), 1521 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14), 1522 EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18), 1523 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpd2", 0x1c), 1524 EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpd4", 0x20), 1525 EXYNOS_PIN_BANK_EINTG(4, 0x120, "gpd5", 0x24), 1526 EXYNOS_PIN_BANK_EINTG(6, 0x140, "gpd6", 0x28), 1527 EXYNOS_PIN_BANK_EINTG(3, 0x160, "gpd7", 0x2c), 1528 EXYNOS_PIN_BANK_EINTG(2, 0x180, "gpd8", 0x30), 1529 EXYNOS_PIN_BANK_EINTG(2, 0x1a0, "gpg0", 0x34), 1530 EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpg3", 0x38), 1531 }; 1532 1533 /* pin banks of exynos7 pin-controller - NFC */ 1534 static const struct samsung_pin_bank_data exynos7_pin_banks2[] __initconst = { 1535 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00), 1536 }; 1537 1538 /* pin banks of exynos7 pin-controller - TOUCH */ 1539 static const struct samsung_pin_bank_data exynos7_pin_banks3[] __initconst = { 1540 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00), 1541 }; 1542 1543 /* pin banks of exynos7 pin-controller - FF */ 1544 static const struct samsung_pin_bank_data exynos7_pin_banks4[] __initconst = { 1545 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpg4", 0x00), 1546 }; 1547 1548 /* pin banks of exynos7 pin-controller - ESE */ 1549 static const struct samsung_pin_bank_data exynos7_pin_banks5[] __initconst = { 1550 EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpv7", 0x00), 1551 }; 1552 1553 /* pin banks of exynos7 pin-controller - FSYS0 */ 1554 static const struct samsung_pin_bank_data exynos7_pin_banks6[] __initconst = { 1555 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpr4", 0x00), 1556 }; 1557 1558 /* pin banks of exynos7 pin-controller - FSYS1 */ 1559 static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = { 1560 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpr0", 0x00), 1561 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpr1", 0x04), 1562 EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr2", 0x08), 1563 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c), 1564 }; 1565 1566 /* pin banks of exynos7 pin-controller - BUS1 */ 1567 static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = { 1568 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00), 1569 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpf1", 0x04), 1570 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf2", 0x08), 1571 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpf3", 0x0c), 1572 EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpf4", 0x10), 1573 EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf5", 0x14), 1574 EXYNOS_PIN_BANK_EINTG(5, 0x0e0, "gpg1", 0x18), 1575 EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpg2", 0x1c), 1576 EXYNOS_PIN_BANK_EINTG(6, 0x120, "gph1", 0x20), 1577 EXYNOS_PIN_BANK_EINTG(3, 0x140, "gpv6", 0x24), 1578 }; 1579 1580 static const struct samsung_pin_bank_data exynos7_pin_banks9[] __initconst = { 1581 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), 1582 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), 1583 }; 1584 1585 const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = { 1586 { 1587 /* pin-controller instance 0 Alive data */ 1588 .pin_banks = exynos7_pin_banks0, 1589 .nr_banks = ARRAY_SIZE(exynos7_pin_banks0), 1590 .eint_wkup_init = exynos_eint_wkup_init, 1591 }, { 1592 /* pin-controller instance 1 BUS0 data */ 1593 .pin_banks = exynos7_pin_banks1, 1594 .nr_banks = ARRAY_SIZE(exynos7_pin_banks1), 1595 .eint_gpio_init = exynos_eint_gpio_init, 1596 }, { 1597 /* pin-controller instance 2 NFC data */ 1598 .pin_banks = exynos7_pin_banks2, 1599 .nr_banks = ARRAY_SIZE(exynos7_pin_banks2), 1600 .eint_gpio_init = exynos_eint_gpio_init, 1601 }, { 1602 /* pin-controller instance 3 TOUCH data */ 1603 .pin_banks = exynos7_pin_banks3, 1604 .nr_banks = ARRAY_SIZE(exynos7_pin_banks3), 1605 .eint_gpio_init = exynos_eint_gpio_init, 1606 }, { 1607 /* pin-controller instance 4 FF data */ 1608 .pin_banks = exynos7_pin_banks4, 1609 .nr_banks = ARRAY_SIZE(exynos7_pin_banks4), 1610 .eint_gpio_init = exynos_eint_gpio_init, 1611 }, { 1612 /* pin-controller instance 5 ESE data */ 1613 .pin_banks = exynos7_pin_banks5, 1614 .nr_banks = ARRAY_SIZE(exynos7_pin_banks5), 1615 .eint_gpio_init = exynos_eint_gpio_init, 1616 }, { 1617 /* pin-controller instance 6 FSYS0 data */ 1618 .pin_banks = exynos7_pin_banks6, 1619 .nr_banks = ARRAY_SIZE(exynos7_pin_banks6), 1620 .eint_gpio_init = exynos_eint_gpio_init, 1621 }, { 1622 /* pin-controller instance 7 FSYS1 data */ 1623 .pin_banks = exynos7_pin_banks7, 1624 .nr_banks = ARRAY_SIZE(exynos7_pin_banks7), 1625 .eint_gpio_init = exynos_eint_gpio_init, 1626 }, { 1627 /* pin-controller instance 8 BUS1 data */ 1628 .pin_banks = exynos7_pin_banks8, 1629 .nr_banks = ARRAY_SIZE(exynos7_pin_banks8), 1630 .eint_gpio_init = exynos_eint_gpio_init, 1631 }, { 1632 /* pin-controller instance 9 AUD data */ 1633 .pin_banks = exynos7_pin_banks9, 1634 .nr_banks = ARRAY_SIZE(exynos7_pin_banks9), 1635 .eint_gpio_init = exynos_eint_gpio_init, 1636 }, 1637 }; 1638