1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Exynos specific support for Samsung pinctrl/gpiolib driver with eint support. 4 // 5 // Copyright (c) 2012 Samsung Electronics Co., Ltd. 6 // http://www.samsung.com 7 // Copyright (c) 2012 Linaro Ltd 8 // http://www.linaro.org 9 // 10 // Author: Thomas Abraham <thomas.ab@samsung.com> 11 // 12 // This file contains the Samsung Exynos specific information required by the 13 // the Samsung pinctrl/gpiolib driver. It also includes the implementation of 14 // external gpio and wakeup interrupt support. 15 16 #include <linux/device.h> 17 #include <linux/interrupt.h> 18 #include <linux/irqdomain.h> 19 #include <linux/irq.h> 20 #include <linux/irqchip/chained_irq.h> 21 #include <linux/of.h> 22 #include <linux/of_irq.h> 23 #include <linux/slab.h> 24 #include <linux/spinlock.h> 25 #include <linux/regmap.h> 26 #include <linux/err.h> 27 #include <linux/soc/samsung/exynos-pmu.h> 28 #include <linux/soc/samsung/exynos-regs-pmu.h> 29 30 #include <dt-bindings/pinctrl/samsung.h> 31 32 #include "pinctrl-samsung.h" 33 #include "pinctrl-exynos.h" 34 35 struct exynos_irq_chip { 36 struct irq_chip chip; 37 38 u32 eint_con; 39 u32 eint_mask; 40 u32 eint_pend; 41 u32 eint_wake_mask_value; 42 u32 eint_wake_mask_reg; 43 void (*set_eint_wakeup_mask)(struct samsung_pinctrl_drv_data *drvdata, 44 struct exynos_irq_chip *irq_chip); 45 }; 46 47 static inline struct exynos_irq_chip *to_exynos_irq_chip(struct irq_chip *chip) 48 { 49 return container_of(chip, struct exynos_irq_chip, chip); 50 } 51 52 static void exynos_irq_mask(struct irq_data *irqd) 53 { 54 struct irq_chip *chip = irq_data_get_irq_chip(irqd); 55 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); 56 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 57 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; 58 unsigned long mask; 59 unsigned long flags; 60 61 spin_lock_irqsave(&bank->slock, flags); 62 63 mask = readl(bank->eint_base + reg_mask); 64 mask |= 1 << irqd->hwirq; 65 writel(mask, bank->eint_base + reg_mask); 66 67 spin_unlock_irqrestore(&bank->slock, flags); 68 } 69 70 static void exynos_irq_ack(struct irq_data *irqd) 71 { 72 struct irq_chip *chip = irq_data_get_irq_chip(irqd); 73 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); 74 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 75 unsigned long reg_pend = our_chip->eint_pend + bank->eint_offset; 76 77 writel(1 << irqd->hwirq, bank->eint_base + reg_pend); 78 } 79 80 static void exynos_irq_unmask(struct irq_data *irqd) 81 { 82 struct irq_chip *chip = irq_data_get_irq_chip(irqd); 83 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); 84 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 85 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; 86 unsigned long mask; 87 unsigned long flags; 88 89 /* 90 * Ack level interrupts right before unmask 91 * 92 * If we don't do this we'll get a double-interrupt. Level triggered 93 * interrupts must not fire an interrupt if the level is not 94 * _currently_ active, even if it was active while the interrupt was 95 * masked. 96 */ 97 if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK) 98 exynos_irq_ack(irqd); 99 100 spin_lock_irqsave(&bank->slock, flags); 101 102 mask = readl(bank->eint_base + reg_mask); 103 mask &= ~(1 << irqd->hwirq); 104 writel(mask, bank->eint_base + reg_mask); 105 106 spin_unlock_irqrestore(&bank->slock, flags); 107 } 108 109 static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type) 110 { 111 struct irq_chip *chip = irq_data_get_irq_chip(irqd); 112 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); 113 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 114 unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq; 115 unsigned int con, trig_type; 116 unsigned long reg_con = our_chip->eint_con + bank->eint_offset; 117 118 switch (type) { 119 case IRQ_TYPE_EDGE_RISING: 120 trig_type = EXYNOS_EINT_EDGE_RISING; 121 break; 122 case IRQ_TYPE_EDGE_FALLING: 123 trig_type = EXYNOS_EINT_EDGE_FALLING; 124 break; 125 case IRQ_TYPE_EDGE_BOTH: 126 trig_type = EXYNOS_EINT_EDGE_BOTH; 127 break; 128 case IRQ_TYPE_LEVEL_HIGH: 129 trig_type = EXYNOS_EINT_LEVEL_HIGH; 130 break; 131 case IRQ_TYPE_LEVEL_LOW: 132 trig_type = EXYNOS_EINT_LEVEL_LOW; 133 break; 134 default: 135 pr_err("unsupported external interrupt type\n"); 136 return -EINVAL; 137 } 138 139 if (type & IRQ_TYPE_EDGE_BOTH) 140 irq_set_handler_locked(irqd, handle_edge_irq); 141 else 142 irq_set_handler_locked(irqd, handle_level_irq); 143 144 con = readl(bank->eint_base + reg_con); 145 con &= ~(EXYNOS_EINT_CON_MASK << shift); 146 con |= trig_type << shift; 147 writel(con, bank->eint_base + reg_con); 148 149 return 0; 150 } 151 152 static int exynos_irq_request_resources(struct irq_data *irqd) 153 { 154 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 155 const struct samsung_pin_bank_type *bank_type = bank->type; 156 unsigned long reg_con, flags; 157 unsigned int shift, mask, con; 158 int ret; 159 160 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irqd->hwirq); 161 if (ret) { 162 dev_err(bank->gpio_chip.parent, 163 "unable to lock pin %s-%lu IRQ\n", 164 bank->name, irqd->hwirq); 165 return ret; 166 } 167 168 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; 169 shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC]; 170 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; 171 172 spin_lock_irqsave(&bank->slock, flags); 173 174 con = readl(bank->pctl_base + reg_con); 175 con &= ~(mask << shift); 176 con |= EXYNOS_PIN_FUNC_EINT << shift; 177 writel(con, bank->pctl_base + reg_con); 178 179 spin_unlock_irqrestore(&bank->slock, flags); 180 181 return 0; 182 } 183 184 static void exynos_irq_release_resources(struct irq_data *irqd) 185 { 186 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 187 const struct samsung_pin_bank_type *bank_type = bank->type; 188 unsigned long reg_con, flags; 189 unsigned int shift, mask, con; 190 191 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; 192 shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC]; 193 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; 194 195 spin_lock_irqsave(&bank->slock, flags); 196 197 con = readl(bank->pctl_base + reg_con); 198 con &= ~(mask << shift); 199 con |= EXYNOS_PIN_FUNC_INPUT << shift; 200 writel(con, bank->pctl_base + reg_con); 201 202 spin_unlock_irqrestore(&bank->slock, flags); 203 204 gpiochip_unlock_as_irq(&bank->gpio_chip, irqd->hwirq); 205 } 206 207 /* 208 * irq_chip for gpio interrupts. 209 */ 210 static struct exynos_irq_chip exynos_gpio_irq_chip = { 211 .chip = { 212 .name = "exynos_gpio_irq_chip", 213 .irq_unmask = exynos_irq_unmask, 214 .irq_mask = exynos_irq_mask, 215 .irq_ack = exynos_irq_ack, 216 .irq_set_type = exynos_irq_set_type, 217 .irq_request_resources = exynos_irq_request_resources, 218 .irq_release_resources = exynos_irq_release_resources, 219 }, 220 .eint_con = EXYNOS_GPIO_ECON_OFFSET, 221 .eint_mask = EXYNOS_GPIO_EMASK_OFFSET, 222 .eint_pend = EXYNOS_GPIO_EPEND_OFFSET, 223 /* eint_wake_mask_value not used */ 224 }; 225 226 static int exynos_eint_irq_map(struct irq_domain *h, unsigned int virq, 227 irq_hw_number_t hw) 228 { 229 struct samsung_pin_bank *b = h->host_data; 230 231 irq_set_chip_data(virq, b); 232 irq_set_chip_and_handler(virq, &b->irq_chip->chip, 233 handle_level_irq); 234 return 0; 235 } 236 237 /* 238 * irq domain callbacks for external gpio and wakeup interrupt controllers. 239 */ 240 static const struct irq_domain_ops exynos_eint_irqd_ops = { 241 .map = exynos_eint_irq_map, 242 .xlate = irq_domain_xlate_twocell, 243 }; 244 245 static irqreturn_t exynos_eint_gpio_irq(int irq, void *data) 246 { 247 struct samsung_pinctrl_drv_data *d = data; 248 struct samsung_pin_bank *bank = d->pin_banks; 249 unsigned int svc, group, pin, virq; 250 251 svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET); 252 group = EXYNOS_SVC_GROUP(svc); 253 pin = svc & EXYNOS_SVC_NUM_MASK; 254 255 if (!group) 256 return IRQ_HANDLED; 257 bank += (group - 1); 258 259 virq = irq_linear_revmap(bank->irq_domain, pin); 260 if (!virq) 261 return IRQ_NONE; 262 generic_handle_irq(virq); 263 return IRQ_HANDLED; 264 } 265 266 struct exynos_eint_gpio_save { 267 u32 eint_con; 268 u32 eint_fltcon0; 269 u32 eint_fltcon1; 270 u32 eint_mask; 271 }; 272 273 /* 274 * exynos_eint_gpio_init() - setup handling of external gpio interrupts. 275 * @d: driver data of samsung pinctrl driver. 276 */ 277 int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d) 278 { 279 struct samsung_pin_bank *bank; 280 struct device *dev = d->dev; 281 int ret; 282 int i; 283 284 if (!d->irq) { 285 dev_err(dev, "irq number not available\n"); 286 return -EINVAL; 287 } 288 289 ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq, 290 0, dev_name(dev), d); 291 if (ret) { 292 dev_err(dev, "irq request failed\n"); 293 return -ENXIO; 294 } 295 296 bank = d->pin_banks; 297 for (i = 0; i < d->nr_banks; ++i, ++bank) { 298 if (bank->eint_type != EINT_TYPE_GPIO) 299 continue; 300 bank->irq_domain = irq_domain_add_linear(bank->of_node, 301 bank->nr_pins, &exynos_eint_irqd_ops, bank); 302 if (!bank->irq_domain) { 303 dev_err(dev, "gpio irq domain add failed\n"); 304 ret = -ENXIO; 305 goto err_domains; 306 } 307 308 bank->soc_priv = devm_kzalloc(d->dev, 309 sizeof(struct exynos_eint_gpio_save), GFP_KERNEL); 310 if (!bank->soc_priv) { 311 irq_domain_remove(bank->irq_domain); 312 ret = -ENOMEM; 313 goto err_domains; 314 } 315 316 bank->irq_chip = &exynos_gpio_irq_chip; 317 } 318 319 return 0; 320 321 err_domains: 322 for (--i, --bank; i >= 0; --i, --bank) { 323 if (bank->eint_type != EINT_TYPE_GPIO) 324 continue; 325 irq_domain_remove(bank->irq_domain); 326 } 327 328 return ret; 329 } 330 331 static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on) 332 { 333 struct irq_chip *chip = irq_data_get_irq_chip(irqd); 334 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); 335 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 336 unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq); 337 338 pr_info("wake %s for irq %d\n", on ? "enabled" : "disabled", irqd->irq); 339 340 if (!on) 341 our_chip->eint_wake_mask_value |= bit; 342 else 343 our_chip->eint_wake_mask_value &= ~bit; 344 345 return 0; 346 } 347 348 static void 349 exynos_pinctrl_set_eint_wakeup_mask(struct samsung_pinctrl_drv_data *drvdata, 350 struct exynos_irq_chip *irq_chip) 351 { 352 struct regmap *pmu_regs; 353 354 if (!drvdata->retention_ctrl || !drvdata->retention_ctrl->priv) { 355 dev_warn(drvdata->dev, 356 "No retention data configured bank with external wakeup interrupt. Wake-up mask will not be set.\n"); 357 return; 358 } 359 360 pmu_regs = drvdata->retention_ctrl->priv; 361 dev_info(drvdata->dev, 362 "Setting external wakeup interrupt mask: 0x%x\n", 363 irq_chip->eint_wake_mask_value); 364 365 regmap_write(pmu_regs, irq_chip->eint_wake_mask_reg, 366 irq_chip->eint_wake_mask_value); 367 } 368 369 static void 370 s5pv210_pinctrl_set_eint_wakeup_mask(struct samsung_pinctrl_drv_data *drvdata, 371 struct exynos_irq_chip *irq_chip) 372 373 { 374 void __iomem *clk_base; 375 376 if (!drvdata->retention_ctrl || !drvdata->retention_ctrl->priv) { 377 dev_warn(drvdata->dev, 378 "No retention data configured bank with external wakeup interrupt. Wake-up mask will not be set.\n"); 379 return; 380 } 381 382 383 clk_base = (void __iomem *) drvdata->retention_ctrl->priv; 384 385 __raw_writel(irq_chip->eint_wake_mask_value, 386 clk_base + irq_chip->eint_wake_mask_reg); 387 } 388 389 /* 390 * irq_chip for wakeup interrupts 391 */ 392 static const struct exynos_irq_chip s5pv210_wkup_irq_chip __initconst = { 393 .chip = { 394 .name = "s5pv210_wkup_irq_chip", 395 .irq_unmask = exynos_irq_unmask, 396 .irq_mask = exynos_irq_mask, 397 .irq_ack = exynos_irq_ack, 398 .irq_set_type = exynos_irq_set_type, 399 .irq_set_wake = exynos_wkup_irq_set_wake, 400 .irq_request_resources = exynos_irq_request_resources, 401 .irq_release_resources = exynos_irq_release_resources, 402 }, 403 .eint_con = EXYNOS_WKUP_ECON_OFFSET, 404 .eint_mask = EXYNOS_WKUP_EMASK_OFFSET, 405 .eint_pend = EXYNOS_WKUP_EPEND_OFFSET, 406 .eint_wake_mask_value = EXYNOS_EINT_WAKEUP_MASK_DISABLED, 407 /* Only differences with exynos4210_wkup_irq_chip: */ 408 .eint_wake_mask_reg = S5PV210_EINT_WAKEUP_MASK, 409 .set_eint_wakeup_mask = s5pv210_pinctrl_set_eint_wakeup_mask, 410 }; 411 412 static const struct exynos_irq_chip exynos4210_wkup_irq_chip __initconst = { 413 .chip = { 414 .name = "exynos4210_wkup_irq_chip", 415 .irq_unmask = exynos_irq_unmask, 416 .irq_mask = exynos_irq_mask, 417 .irq_ack = exynos_irq_ack, 418 .irq_set_type = exynos_irq_set_type, 419 .irq_set_wake = exynos_wkup_irq_set_wake, 420 .irq_request_resources = exynos_irq_request_resources, 421 .irq_release_resources = exynos_irq_release_resources, 422 }, 423 .eint_con = EXYNOS_WKUP_ECON_OFFSET, 424 .eint_mask = EXYNOS_WKUP_EMASK_OFFSET, 425 .eint_pend = EXYNOS_WKUP_EPEND_OFFSET, 426 .eint_wake_mask_value = EXYNOS_EINT_WAKEUP_MASK_DISABLED, 427 .eint_wake_mask_reg = EXYNOS_EINT_WAKEUP_MASK, 428 .set_eint_wakeup_mask = exynos_pinctrl_set_eint_wakeup_mask, 429 }; 430 431 static const struct exynos_irq_chip exynos7_wkup_irq_chip __initconst = { 432 .chip = { 433 .name = "exynos7_wkup_irq_chip", 434 .irq_unmask = exynos_irq_unmask, 435 .irq_mask = exynos_irq_mask, 436 .irq_ack = exynos_irq_ack, 437 .irq_set_type = exynos_irq_set_type, 438 .irq_set_wake = exynos_wkup_irq_set_wake, 439 .irq_request_resources = exynos_irq_request_resources, 440 .irq_release_resources = exynos_irq_release_resources, 441 }, 442 .eint_con = EXYNOS7_WKUP_ECON_OFFSET, 443 .eint_mask = EXYNOS7_WKUP_EMASK_OFFSET, 444 .eint_pend = EXYNOS7_WKUP_EPEND_OFFSET, 445 .eint_wake_mask_value = EXYNOS_EINT_WAKEUP_MASK_DISABLED, 446 .eint_wake_mask_reg = EXYNOS5433_EINT_WAKEUP_MASK, 447 .set_eint_wakeup_mask = exynos_pinctrl_set_eint_wakeup_mask, 448 }; 449 450 /* list of external wakeup controllers supported */ 451 static const struct of_device_id exynos_wkup_irq_ids[] = { 452 { .compatible = "samsung,s5pv210-wakeup-eint", 453 .data = &s5pv210_wkup_irq_chip }, 454 { .compatible = "samsung,exynos4210-wakeup-eint", 455 .data = &exynos4210_wkup_irq_chip }, 456 { .compatible = "samsung,exynos7-wakeup-eint", 457 .data = &exynos7_wkup_irq_chip }, 458 { } 459 }; 460 461 /* interrupt handler for wakeup interrupts 0..15 */ 462 static void exynos_irq_eint0_15(struct irq_desc *desc) 463 { 464 struct exynos_weint_data *eintd = irq_desc_get_handler_data(desc); 465 struct samsung_pin_bank *bank = eintd->bank; 466 struct irq_chip *chip = irq_desc_get_chip(desc); 467 int eint_irq; 468 469 chained_irq_enter(chip, desc); 470 471 eint_irq = irq_linear_revmap(bank->irq_domain, eintd->irq); 472 generic_handle_irq(eint_irq); 473 474 chained_irq_exit(chip, desc); 475 } 476 477 static inline void exynos_irq_demux_eint(unsigned long pend, 478 struct irq_domain *domain) 479 { 480 unsigned int irq; 481 482 while (pend) { 483 irq = fls(pend) - 1; 484 generic_handle_irq(irq_find_mapping(domain, irq)); 485 pend &= ~(1 << irq); 486 } 487 } 488 489 /* interrupt handler for wakeup interrupt 16 */ 490 static void exynos_irq_demux_eint16_31(struct irq_desc *desc) 491 { 492 struct irq_chip *chip = irq_desc_get_chip(desc); 493 struct exynos_muxed_weint_data *eintd = irq_desc_get_handler_data(desc); 494 unsigned long pend; 495 unsigned long mask; 496 int i; 497 498 chained_irq_enter(chip, desc); 499 500 for (i = 0; i < eintd->nr_banks; ++i) { 501 struct samsung_pin_bank *b = eintd->banks[i]; 502 pend = readl(b->eint_base + b->irq_chip->eint_pend 503 + b->eint_offset); 504 mask = readl(b->eint_base + b->irq_chip->eint_mask 505 + b->eint_offset); 506 exynos_irq_demux_eint(pend & ~mask, b->irq_domain); 507 } 508 509 chained_irq_exit(chip, desc); 510 } 511 512 /* 513 * exynos_eint_wkup_init() - setup handling of external wakeup interrupts. 514 * @d: driver data of samsung pinctrl driver. 515 */ 516 int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) 517 { 518 struct device *dev = d->dev; 519 struct device_node *wkup_np = NULL; 520 struct device_node *np; 521 struct samsung_pin_bank *bank; 522 struct exynos_weint_data *weint_data; 523 struct exynos_muxed_weint_data *muxed_data; 524 struct exynos_irq_chip *irq_chip; 525 unsigned int muxed_banks = 0; 526 unsigned int i; 527 int idx, irq; 528 529 for_each_child_of_node(dev->of_node, np) { 530 const struct of_device_id *match; 531 532 match = of_match_node(exynos_wkup_irq_ids, np); 533 if (match) { 534 irq_chip = kmemdup(match->data, 535 sizeof(*irq_chip), GFP_KERNEL); 536 if (!irq_chip) { 537 of_node_put(np); 538 return -ENOMEM; 539 } 540 wkup_np = np; 541 break; 542 } 543 } 544 if (!wkup_np) 545 return -ENODEV; 546 547 bank = d->pin_banks; 548 for (i = 0; i < d->nr_banks; ++i, ++bank) { 549 if (bank->eint_type != EINT_TYPE_WKUP) 550 continue; 551 552 bank->irq_domain = irq_domain_add_linear(bank->of_node, 553 bank->nr_pins, &exynos_eint_irqd_ops, bank); 554 if (!bank->irq_domain) { 555 dev_err(dev, "wkup irq domain add failed\n"); 556 of_node_put(wkup_np); 557 return -ENXIO; 558 } 559 560 bank->irq_chip = irq_chip; 561 562 if (!of_find_property(bank->of_node, "interrupts", NULL)) { 563 bank->eint_type = EINT_TYPE_WKUP_MUX; 564 ++muxed_banks; 565 continue; 566 } 567 568 weint_data = devm_kcalloc(dev, 569 bank->nr_pins, sizeof(*weint_data), 570 GFP_KERNEL); 571 if (!weint_data) { 572 of_node_put(wkup_np); 573 return -ENOMEM; 574 } 575 576 for (idx = 0; idx < bank->nr_pins; ++idx) { 577 irq = irq_of_parse_and_map(bank->of_node, idx); 578 if (!irq) { 579 dev_err(dev, "irq number for eint-%s-%d not found\n", 580 bank->name, idx); 581 continue; 582 } 583 weint_data[idx].irq = idx; 584 weint_data[idx].bank = bank; 585 irq_set_chained_handler_and_data(irq, 586 exynos_irq_eint0_15, 587 &weint_data[idx]); 588 } 589 } 590 591 if (!muxed_banks) { 592 of_node_put(wkup_np); 593 return 0; 594 } 595 596 irq = irq_of_parse_and_map(wkup_np, 0); 597 of_node_put(wkup_np); 598 if (!irq) { 599 dev_err(dev, "irq number for muxed EINTs not found\n"); 600 return 0; 601 } 602 603 muxed_data = devm_kzalloc(dev, sizeof(*muxed_data) 604 + muxed_banks*sizeof(struct samsung_pin_bank *), GFP_KERNEL); 605 if (!muxed_data) 606 return -ENOMEM; 607 608 irq_set_chained_handler_and_data(irq, exynos_irq_demux_eint16_31, 609 muxed_data); 610 611 bank = d->pin_banks; 612 idx = 0; 613 for (i = 0; i < d->nr_banks; ++i, ++bank) { 614 if (bank->eint_type != EINT_TYPE_WKUP_MUX) 615 continue; 616 617 muxed_data->banks[idx++] = bank; 618 } 619 muxed_data->nr_banks = muxed_banks; 620 621 return 0; 622 } 623 624 static void exynos_pinctrl_suspend_bank( 625 struct samsung_pinctrl_drv_data *drvdata, 626 struct samsung_pin_bank *bank) 627 { 628 struct exynos_eint_gpio_save *save = bank->soc_priv; 629 void __iomem *regs = bank->eint_base; 630 631 save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET 632 + bank->eint_offset); 633 save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET 634 + 2 * bank->eint_offset); 635 save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET 636 + 2 * bank->eint_offset + 4); 637 save->eint_mask = readl(regs + bank->irq_chip->eint_mask 638 + bank->eint_offset); 639 640 pr_debug("%s: save con %#010x\n", bank->name, save->eint_con); 641 pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0); 642 pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1); 643 pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask); 644 } 645 646 void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) 647 { 648 struct samsung_pin_bank *bank = drvdata->pin_banks; 649 struct exynos_irq_chip *irq_chip = NULL; 650 int i; 651 652 for (i = 0; i < drvdata->nr_banks; ++i, ++bank) { 653 if (bank->eint_type == EINT_TYPE_GPIO) 654 exynos_pinctrl_suspend_bank(drvdata, bank); 655 else if (bank->eint_type == EINT_TYPE_WKUP) { 656 if (!irq_chip) { 657 irq_chip = bank->irq_chip; 658 irq_chip->set_eint_wakeup_mask(drvdata, 659 irq_chip); 660 } else if (bank->irq_chip != irq_chip) { 661 dev_warn(drvdata->dev, 662 "More than one external wakeup interrupt chip configured (bank: %s). This is not supported by hardware nor by driver.\n", 663 bank->name); 664 } 665 } 666 } 667 } 668 669 static void exynos_pinctrl_resume_bank( 670 struct samsung_pinctrl_drv_data *drvdata, 671 struct samsung_pin_bank *bank) 672 { 673 struct exynos_eint_gpio_save *save = bank->soc_priv; 674 void __iomem *regs = bank->eint_base; 675 676 pr_debug("%s: con %#010x => %#010x\n", bank->name, 677 readl(regs + EXYNOS_GPIO_ECON_OFFSET 678 + bank->eint_offset), save->eint_con); 679 pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name, 680 readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET 681 + 2 * bank->eint_offset), save->eint_fltcon0); 682 pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name, 683 readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET 684 + 2 * bank->eint_offset + 4), save->eint_fltcon1); 685 pr_debug("%s: mask %#010x => %#010x\n", bank->name, 686 readl(regs + bank->irq_chip->eint_mask 687 + bank->eint_offset), save->eint_mask); 688 689 writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET 690 + bank->eint_offset); 691 writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET 692 + 2 * bank->eint_offset); 693 writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET 694 + 2 * bank->eint_offset + 4); 695 writel(save->eint_mask, regs + bank->irq_chip->eint_mask 696 + bank->eint_offset); 697 } 698 699 void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) 700 { 701 struct samsung_pin_bank *bank = drvdata->pin_banks; 702 int i; 703 704 for (i = 0; i < drvdata->nr_banks; ++i, ++bank) 705 if (bank->eint_type == EINT_TYPE_GPIO) 706 exynos_pinctrl_resume_bank(drvdata, bank); 707 } 708 709 static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata) 710 { 711 if (drvdata->retention_ctrl->refcnt) 712 atomic_inc(drvdata->retention_ctrl->refcnt); 713 } 714 715 static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata) 716 { 717 struct samsung_retention_ctrl *ctrl = drvdata->retention_ctrl; 718 struct regmap *pmu_regs = ctrl->priv; 719 int i; 720 721 if (ctrl->refcnt && !atomic_dec_and_test(ctrl->refcnt)) 722 return; 723 724 for (i = 0; i < ctrl->nr_regs; i++) 725 regmap_write(pmu_regs, ctrl->regs[i], ctrl->value); 726 } 727 728 struct samsung_retention_ctrl * 729 exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata, 730 const struct samsung_retention_data *data) 731 { 732 struct samsung_retention_ctrl *ctrl; 733 struct regmap *pmu_regs; 734 int i; 735 736 ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL); 737 if (!ctrl) 738 return ERR_PTR(-ENOMEM); 739 740 pmu_regs = exynos_get_pmu_regmap(); 741 if (IS_ERR(pmu_regs)) 742 return ERR_CAST(pmu_regs); 743 744 ctrl->priv = pmu_regs; 745 ctrl->regs = data->regs; 746 ctrl->nr_regs = data->nr_regs; 747 ctrl->value = data->value; 748 ctrl->refcnt = data->refcnt; 749 ctrl->enable = exynos_retention_enable; 750 ctrl->disable = exynos_retention_disable; 751 752 /* Ensure that retention is disabled on driver init */ 753 for (i = 0; i < ctrl->nr_regs; i++) 754 regmap_write(pmu_regs, ctrl->regs[i], ctrl->value); 755 756 return ctrl; 757 } 758