1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Exynos specific support for Samsung pinctrl/gpiolib driver with eint support. 4 // 5 // Copyright (c) 2012 Samsung Electronics Co., Ltd. 6 // http://www.samsung.com 7 // Copyright (c) 2012 Linaro Ltd 8 // http://www.linaro.org 9 // 10 // Author: Thomas Abraham <thomas.ab@samsung.com> 11 // 12 // This file contains the Samsung Exynos specific information required by the 13 // the Samsung pinctrl/gpiolib driver. It also includes the implementation of 14 // external gpio and wakeup interrupt support. 15 16 #include <linux/device.h> 17 #include <linux/interrupt.h> 18 #include <linux/irqdomain.h> 19 #include <linux/irq.h> 20 #include <linux/irqchip/chained_irq.h> 21 #include <linux/of.h> 22 #include <linux/of_irq.h> 23 #include <linux/slab.h> 24 #include <linux/spinlock.h> 25 #include <linux/regmap.h> 26 #include <linux/err.h> 27 #include <linux/soc/samsung/exynos-pmu.h> 28 #include <linux/soc/samsung/exynos-regs-pmu.h> 29 30 #include <dt-bindings/pinctrl/samsung.h> 31 32 #include "pinctrl-samsung.h" 33 #include "pinctrl-exynos.h" 34 35 struct exynos_irq_chip { 36 struct irq_chip chip; 37 38 u32 eint_con; 39 u32 eint_mask; 40 u32 eint_pend; 41 u32 eint_wake_mask_value; 42 u32 eint_wake_mask_reg; 43 }; 44 45 static inline struct exynos_irq_chip *to_exynos_irq_chip(struct irq_chip *chip) 46 { 47 return container_of(chip, struct exynos_irq_chip, chip); 48 } 49 50 static void exynos_irq_mask(struct irq_data *irqd) 51 { 52 struct irq_chip *chip = irq_data_get_irq_chip(irqd); 53 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); 54 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 55 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; 56 unsigned long mask; 57 unsigned long flags; 58 59 spin_lock_irqsave(&bank->slock, flags); 60 61 mask = readl(bank->eint_base + reg_mask); 62 mask |= 1 << irqd->hwirq; 63 writel(mask, bank->eint_base + reg_mask); 64 65 spin_unlock_irqrestore(&bank->slock, flags); 66 } 67 68 static void exynos_irq_ack(struct irq_data *irqd) 69 { 70 struct irq_chip *chip = irq_data_get_irq_chip(irqd); 71 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); 72 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 73 unsigned long reg_pend = our_chip->eint_pend + bank->eint_offset; 74 75 writel(1 << irqd->hwirq, bank->eint_base + reg_pend); 76 } 77 78 static void exynos_irq_unmask(struct irq_data *irqd) 79 { 80 struct irq_chip *chip = irq_data_get_irq_chip(irqd); 81 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); 82 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 83 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; 84 unsigned long mask; 85 unsigned long flags; 86 87 /* 88 * Ack level interrupts right before unmask 89 * 90 * If we don't do this we'll get a double-interrupt. Level triggered 91 * interrupts must not fire an interrupt if the level is not 92 * _currently_ active, even if it was active while the interrupt was 93 * masked. 94 */ 95 if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK) 96 exynos_irq_ack(irqd); 97 98 spin_lock_irqsave(&bank->slock, flags); 99 100 mask = readl(bank->eint_base + reg_mask); 101 mask &= ~(1 << irqd->hwirq); 102 writel(mask, bank->eint_base + reg_mask); 103 104 spin_unlock_irqrestore(&bank->slock, flags); 105 } 106 107 static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type) 108 { 109 struct irq_chip *chip = irq_data_get_irq_chip(irqd); 110 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); 111 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 112 unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq; 113 unsigned int con, trig_type; 114 unsigned long reg_con = our_chip->eint_con + bank->eint_offset; 115 116 switch (type) { 117 case IRQ_TYPE_EDGE_RISING: 118 trig_type = EXYNOS_EINT_EDGE_RISING; 119 break; 120 case IRQ_TYPE_EDGE_FALLING: 121 trig_type = EXYNOS_EINT_EDGE_FALLING; 122 break; 123 case IRQ_TYPE_EDGE_BOTH: 124 trig_type = EXYNOS_EINT_EDGE_BOTH; 125 break; 126 case IRQ_TYPE_LEVEL_HIGH: 127 trig_type = EXYNOS_EINT_LEVEL_HIGH; 128 break; 129 case IRQ_TYPE_LEVEL_LOW: 130 trig_type = EXYNOS_EINT_LEVEL_LOW; 131 break; 132 default: 133 pr_err("unsupported external interrupt type\n"); 134 return -EINVAL; 135 } 136 137 if (type & IRQ_TYPE_EDGE_BOTH) 138 irq_set_handler_locked(irqd, handle_edge_irq); 139 else 140 irq_set_handler_locked(irqd, handle_level_irq); 141 142 con = readl(bank->eint_base + reg_con); 143 con &= ~(EXYNOS_EINT_CON_MASK << shift); 144 con |= trig_type << shift; 145 writel(con, bank->eint_base + reg_con); 146 147 return 0; 148 } 149 150 static int exynos_irq_request_resources(struct irq_data *irqd) 151 { 152 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 153 const struct samsung_pin_bank_type *bank_type = bank->type; 154 unsigned long reg_con, flags; 155 unsigned int shift, mask, con; 156 int ret; 157 158 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irqd->hwirq); 159 if (ret) { 160 dev_err(bank->gpio_chip.parent, 161 "unable to lock pin %s-%lu IRQ\n", 162 bank->name, irqd->hwirq); 163 return ret; 164 } 165 166 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; 167 shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC]; 168 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; 169 170 spin_lock_irqsave(&bank->slock, flags); 171 172 con = readl(bank->pctl_base + reg_con); 173 con &= ~(mask << shift); 174 con |= EXYNOS_PIN_FUNC_EINT << shift; 175 writel(con, bank->pctl_base + reg_con); 176 177 spin_unlock_irqrestore(&bank->slock, flags); 178 179 return 0; 180 } 181 182 static void exynos_irq_release_resources(struct irq_data *irqd) 183 { 184 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 185 const struct samsung_pin_bank_type *bank_type = bank->type; 186 unsigned long reg_con, flags; 187 unsigned int shift, mask, con; 188 189 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; 190 shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC]; 191 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; 192 193 spin_lock_irqsave(&bank->slock, flags); 194 195 con = readl(bank->pctl_base + reg_con); 196 con &= ~(mask << shift); 197 con |= EXYNOS_PIN_FUNC_INPUT << shift; 198 writel(con, bank->pctl_base + reg_con); 199 200 spin_unlock_irqrestore(&bank->slock, flags); 201 202 gpiochip_unlock_as_irq(&bank->gpio_chip, irqd->hwirq); 203 } 204 205 /* 206 * irq_chip for gpio interrupts. 207 */ 208 static struct exynos_irq_chip exynos_gpio_irq_chip = { 209 .chip = { 210 .name = "exynos_gpio_irq_chip", 211 .irq_unmask = exynos_irq_unmask, 212 .irq_mask = exynos_irq_mask, 213 .irq_ack = exynos_irq_ack, 214 .irq_set_type = exynos_irq_set_type, 215 .irq_request_resources = exynos_irq_request_resources, 216 .irq_release_resources = exynos_irq_release_resources, 217 }, 218 .eint_con = EXYNOS_GPIO_ECON_OFFSET, 219 .eint_mask = EXYNOS_GPIO_EMASK_OFFSET, 220 .eint_pend = EXYNOS_GPIO_EPEND_OFFSET, 221 /* eint_wake_mask_value not used */ 222 }; 223 224 static int exynos_eint_irq_map(struct irq_domain *h, unsigned int virq, 225 irq_hw_number_t hw) 226 { 227 struct samsung_pin_bank *b = h->host_data; 228 229 irq_set_chip_data(virq, b); 230 irq_set_chip_and_handler(virq, &b->irq_chip->chip, 231 handle_level_irq); 232 return 0; 233 } 234 235 /* 236 * irq domain callbacks for external gpio and wakeup interrupt controllers. 237 */ 238 static const struct irq_domain_ops exynos_eint_irqd_ops = { 239 .map = exynos_eint_irq_map, 240 .xlate = irq_domain_xlate_twocell, 241 }; 242 243 static irqreturn_t exynos_eint_gpio_irq(int irq, void *data) 244 { 245 struct samsung_pinctrl_drv_data *d = data; 246 struct samsung_pin_bank *bank = d->pin_banks; 247 unsigned int svc, group, pin, virq; 248 249 svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET); 250 group = EXYNOS_SVC_GROUP(svc); 251 pin = svc & EXYNOS_SVC_NUM_MASK; 252 253 if (!group) 254 return IRQ_HANDLED; 255 bank += (group - 1); 256 257 virq = irq_linear_revmap(bank->irq_domain, pin); 258 if (!virq) 259 return IRQ_NONE; 260 generic_handle_irq(virq); 261 return IRQ_HANDLED; 262 } 263 264 struct exynos_eint_gpio_save { 265 u32 eint_con; 266 u32 eint_fltcon0; 267 u32 eint_fltcon1; 268 }; 269 270 /* 271 * exynos_eint_gpio_init() - setup handling of external gpio interrupts. 272 * @d: driver data of samsung pinctrl driver. 273 */ 274 int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d) 275 { 276 struct samsung_pin_bank *bank; 277 struct device *dev = d->dev; 278 int ret; 279 int i; 280 281 if (!d->irq) { 282 dev_err(dev, "irq number not available\n"); 283 return -EINVAL; 284 } 285 286 ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq, 287 0, dev_name(dev), d); 288 if (ret) { 289 dev_err(dev, "irq request failed\n"); 290 return -ENXIO; 291 } 292 293 bank = d->pin_banks; 294 for (i = 0; i < d->nr_banks; ++i, ++bank) { 295 if (bank->eint_type != EINT_TYPE_GPIO) 296 continue; 297 bank->irq_domain = irq_domain_add_linear(bank->of_node, 298 bank->nr_pins, &exynos_eint_irqd_ops, bank); 299 if (!bank->irq_domain) { 300 dev_err(dev, "gpio irq domain add failed\n"); 301 ret = -ENXIO; 302 goto err_domains; 303 } 304 305 bank->soc_priv = devm_kzalloc(d->dev, 306 sizeof(struct exynos_eint_gpio_save), GFP_KERNEL); 307 if (!bank->soc_priv) { 308 irq_domain_remove(bank->irq_domain); 309 ret = -ENOMEM; 310 goto err_domains; 311 } 312 313 bank->irq_chip = &exynos_gpio_irq_chip; 314 } 315 316 return 0; 317 318 err_domains: 319 for (--i, --bank; i >= 0; --i, --bank) { 320 if (bank->eint_type != EINT_TYPE_GPIO) 321 continue; 322 irq_domain_remove(bank->irq_domain); 323 } 324 325 return ret; 326 } 327 328 static u32 exynos_eint_wake_mask = 0xffffffff; 329 330 u32 exynos_get_eint_wake_mask(void) 331 { 332 return exynos_eint_wake_mask; 333 } 334 335 static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on) 336 { 337 struct irq_chip *chip = irq_data_get_irq_chip(irqd); 338 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); 339 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 340 unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq); 341 342 pr_info("wake %s for irq %d\n", on ? "enabled" : "disabled", irqd->irq); 343 344 if (!on) 345 exynos_eint_wake_mask |= bit; 346 else 347 exynos_eint_wake_mask &= ~bit; 348 our_chip->eint_wake_mask_value = exynos_eint_wake_mask; 349 350 return 0; 351 } 352 353 /* 354 * irq_chip for wakeup interrupts 355 */ 356 static const struct exynos_irq_chip s5pv210_wkup_irq_chip __initconst = { 357 .chip = { 358 .name = "s5pv210_wkup_irq_chip", 359 .irq_unmask = exynos_irq_unmask, 360 .irq_mask = exynos_irq_mask, 361 .irq_ack = exynos_irq_ack, 362 .irq_set_type = exynos_irq_set_type, 363 .irq_set_wake = exynos_wkup_irq_set_wake, 364 .irq_request_resources = exynos_irq_request_resources, 365 .irq_release_resources = exynos_irq_release_resources, 366 }, 367 .eint_con = EXYNOS_WKUP_ECON_OFFSET, 368 .eint_mask = EXYNOS_WKUP_EMASK_OFFSET, 369 .eint_pend = EXYNOS_WKUP_EPEND_OFFSET, 370 .eint_wake_mask_value = EXYNOS_EINT_WAKEUP_MASK_DISABLED, 371 /* Only difference with exynos4210_wkup_irq_chip: */ 372 .eint_wake_mask_reg = S5PV210_EINT_WAKEUP_MASK, 373 }; 374 375 static const struct exynos_irq_chip exynos4210_wkup_irq_chip __initconst = { 376 .chip = { 377 .name = "exynos4210_wkup_irq_chip", 378 .irq_unmask = exynos_irq_unmask, 379 .irq_mask = exynos_irq_mask, 380 .irq_ack = exynos_irq_ack, 381 .irq_set_type = exynos_irq_set_type, 382 .irq_set_wake = exynos_wkup_irq_set_wake, 383 .irq_request_resources = exynos_irq_request_resources, 384 .irq_release_resources = exynos_irq_release_resources, 385 }, 386 .eint_con = EXYNOS_WKUP_ECON_OFFSET, 387 .eint_mask = EXYNOS_WKUP_EMASK_OFFSET, 388 .eint_pend = EXYNOS_WKUP_EPEND_OFFSET, 389 .eint_wake_mask_value = EXYNOS_EINT_WAKEUP_MASK_DISABLED, 390 .eint_wake_mask_reg = EXYNOS_EINT_WAKEUP_MASK, 391 }; 392 393 static const struct exynos_irq_chip exynos7_wkup_irq_chip __initconst = { 394 .chip = { 395 .name = "exynos7_wkup_irq_chip", 396 .irq_unmask = exynos_irq_unmask, 397 .irq_mask = exynos_irq_mask, 398 .irq_ack = exynos_irq_ack, 399 .irq_set_type = exynos_irq_set_type, 400 .irq_set_wake = exynos_wkup_irq_set_wake, 401 .irq_request_resources = exynos_irq_request_resources, 402 .irq_release_resources = exynos_irq_release_resources, 403 }, 404 .eint_con = EXYNOS7_WKUP_ECON_OFFSET, 405 .eint_mask = EXYNOS7_WKUP_EMASK_OFFSET, 406 .eint_pend = EXYNOS7_WKUP_EPEND_OFFSET, 407 .eint_wake_mask_value = EXYNOS_EINT_WAKEUP_MASK_DISABLED, 408 .eint_wake_mask_reg = EXYNOS5433_EINT_WAKEUP_MASK, 409 }; 410 411 /* list of external wakeup controllers supported */ 412 static const struct of_device_id exynos_wkup_irq_ids[] = { 413 { .compatible = "samsung,s5pv210-wakeup-eint", 414 .data = &s5pv210_wkup_irq_chip }, 415 { .compatible = "samsung,exynos4210-wakeup-eint", 416 .data = &exynos4210_wkup_irq_chip }, 417 { .compatible = "samsung,exynos7-wakeup-eint", 418 .data = &exynos7_wkup_irq_chip }, 419 { } 420 }; 421 422 /* interrupt handler for wakeup interrupts 0..15 */ 423 static void exynos_irq_eint0_15(struct irq_desc *desc) 424 { 425 struct exynos_weint_data *eintd = irq_desc_get_handler_data(desc); 426 struct samsung_pin_bank *bank = eintd->bank; 427 struct irq_chip *chip = irq_desc_get_chip(desc); 428 int eint_irq; 429 430 chained_irq_enter(chip, desc); 431 432 eint_irq = irq_linear_revmap(bank->irq_domain, eintd->irq); 433 generic_handle_irq(eint_irq); 434 435 chained_irq_exit(chip, desc); 436 } 437 438 static inline void exynos_irq_demux_eint(unsigned long pend, 439 struct irq_domain *domain) 440 { 441 unsigned int irq; 442 443 while (pend) { 444 irq = fls(pend) - 1; 445 generic_handle_irq(irq_find_mapping(domain, irq)); 446 pend &= ~(1 << irq); 447 } 448 } 449 450 /* interrupt handler for wakeup interrupt 16 */ 451 static void exynos_irq_demux_eint16_31(struct irq_desc *desc) 452 { 453 struct irq_chip *chip = irq_desc_get_chip(desc); 454 struct exynos_muxed_weint_data *eintd = irq_desc_get_handler_data(desc); 455 unsigned long pend; 456 unsigned long mask; 457 int i; 458 459 chained_irq_enter(chip, desc); 460 461 for (i = 0; i < eintd->nr_banks; ++i) { 462 struct samsung_pin_bank *b = eintd->banks[i]; 463 pend = readl(b->eint_base + b->irq_chip->eint_pend 464 + b->eint_offset); 465 mask = readl(b->eint_base + b->irq_chip->eint_mask 466 + b->eint_offset); 467 exynos_irq_demux_eint(pend & ~mask, b->irq_domain); 468 } 469 470 chained_irq_exit(chip, desc); 471 } 472 473 /* 474 * exynos_eint_wkup_init() - setup handling of external wakeup interrupts. 475 * @d: driver data of samsung pinctrl driver. 476 */ 477 int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) 478 { 479 struct device *dev = d->dev; 480 struct device_node *wkup_np = NULL; 481 struct device_node *np; 482 struct samsung_pin_bank *bank; 483 struct exynos_weint_data *weint_data; 484 struct exynos_muxed_weint_data *muxed_data; 485 struct exynos_irq_chip *irq_chip; 486 unsigned int muxed_banks = 0; 487 unsigned int i; 488 int idx, irq; 489 490 for_each_child_of_node(dev->of_node, np) { 491 const struct of_device_id *match; 492 493 match = of_match_node(exynos_wkup_irq_ids, np); 494 if (match) { 495 irq_chip = kmemdup(match->data, 496 sizeof(*irq_chip), GFP_KERNEL); 497 if (!irq_chip) 498 return -ENOMEM; 499 wkup_np = np; 500 break; 501 } 502 } 503 if (!wkup_np) 504 return -ENODEV; 505 506 bank = d->pin_banks; 507 for (i = 0; i < d->nr_banks; ++i, ++bank) { 508 if (bank->eint_type != EINT_TYPE_WKUP) 509 continue; 510 511 bank->irq_domain = irq_domain_add_linear(bank->of_node, 512 bank->nr_pins, &exynos_eint_irqd_ops, bank); 513 if (!bank->irq_domain) { 514 dev_err(dev, "wkup irq domain add failed\n"); 515 return -ENXIO; 516 } 517 518 bank->irq_chip = irq_chip; 519 520 if (!of_find_property(bank->of_node, "interrupts", NULL)) { 521 bank->eint_type = EINT_TYPE_WKUP_MUX; 522 ++muxed_banks; 523 continue; 524 } 525 526 weint_data = devm_kcalloc(dev, 527 bank->nr_pins, sizeof(*weint_data), 528 GFP_KERNEL); 529 if (!weint_data) 530 return -ENOMEM; 531 532 for (idx = 0; idx < bank->nr_pins; ++idx) { 533 irq = irq_of_parse_and_map(bank->of_node, idx); 534 if (!irq) { 535 dev_err(dev, "irq number for eint-%s-%d not found\n", 536 bank->name, idx); 537 continue; 538 } 539 weint_data[idx].irq = idx; 540 weint_data[idx].bank = bank; 541 irq_set_chained_handler_and_data(irq, 542 exynos_irq_eint0_15, 543 &weint_data[idx]); 544 } 545 } 546 547 if (!muxed_banks) 548 return 0; 549 550 irq = irq_of_parse_and_map(wkup_np, 0); 551 if (!irq) { 552 dev_err(dev, "irq number for muxed EINTs not found\n"); 553 return 0; 554 } 555 556 muxed_data = devm_kzalloc(dev, sizeof(*muxed_data) 557 + muxed_banks*sizeof(struct samsung_pin_bank *), GFP_KERNEL); 558 if (!muxed_data) 559 return -ENOMEM; 560 561 irq_set_chained_handler_and_data(irq, exynos_irq_demux_eint16_31, 562 muxed_data); 563 564 bank = d->pin_banks; 565 idx = 0; 566 for (i = 0; i < d->nr_banks; ++i, ++bank) { 567 if (bank->eint_type != EINT_TYPE_WKUP_MUX) 568 continue; 569 570 muxed_data->banks[idx++] = bank; 571 } 572 muxed_data->nr_banks = muxed_banks; 573 574 return 0; 575 } 576 577 static void 578 exynos_pinctrl_set_eint_wakeup_mask(struct samsung_pinctrl_drv_data *drvdata, 579 struct exynos_irq_chip *irq_chip) 580 { 581 struct regmap *pmu_regs; 582 583 if (!drvdata->retention_ctrl || !drvdata->retention_ctrl->priv) { 584 dev_warn(drvdata->dev, 585 "No retention data configured bank with external wakeup interrupt. Wake-up mask will not be set.\n"); 586 return; 587 } 588 589 pmu_regs = drvdata->retention_ctrl->priv; 590 dev_info(drvdata->dev, 591 "Setting external wakeup interrupt mask: 0x%x\n", 592 irq_chip->eint_wake_mask_value); 593 594 regmap_write(pmu_regs, irq_chip->eint_wake_mask_reg, 595 irq_chip->eint_wake_mask_value); 596 } 597 598 static void exynos_pinctrl_suspend_bank( 599 struct samsung_pinctrl_drv_data *drvdata, 600 struct samsung_pin_bank *bank) 601 { 602 struct exynos_eint_gpio_save *save = bank->soc_priv; 603 void __iomem *regs = bank->eint_base; 604 605 save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET 606 + bank->eint_offset); 607 save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET 608 + 2 * bank->eint_offset); 609 save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET 610 + 2 * bank->eint_offset + 4); 611 612 pr_debug("%s: save con %#010x\n", bank->name, save->eint_con); 613 pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0); 614 pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1); 615 } 616 617 void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) 618 { 619 struct samsung_pin_bank *bank = drvdata->pin_banks; 620 struct exynos_irq_chip *irq_chip = NULL; 621 int i; 622 623 for (i = 0; i < drvdata->nr_banks; ++i, ++bank) { 624 if (bank->eint_type == EINT_TYPE_GPIO) 625 exynos_pinctrl_suspend_bank(drvdata, bank); 626 else if (bank->eint_type == EINT_TYPE_WKUP) { 627 if (!irq_chip) { 628 irq_chip = bank->irq_chip; 629 exynos_pinctrl_set_eint_wakeup_mask(drvdata, 630 irq_chip); 631 } else if (bank->irq_chip != irq_chip) { 632 dev_warn(drvdata->dev, 633 "More than one external wakeup interrupt chip configured (bank: %s). This is not supported by hardware nor by driver.\n", 634 bank->name); 635 } 636 } 637 } 638 } 639 640 static void exynos_pinctrl_resume_bank( 641 struct samsung_pinctrl_drv_data *drvdata, 642 struct samsung_pin_bank *bank) 643 { 644 struct exynos_eint_gpio_save *save = bank->soc_priv; 645 void __iomem *regs = bank->eint_base; 646 647 pr_debug("%s: con %#010x => %#010x\n", bank->name, 648 readl(regs + EXYNOS_GPIO_ECON_OFFSET 649 + bank->eint_offset), save->eint_con); 650 pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name, 651 readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET 652 + 2 * bank->eint_offset), save->eint_fltcon0); 653 pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name, 654 readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET 655 + 2 * bank->eint_offset + 4), save->eint_fltcon1); 656 657 writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET 658 + bank->eint_offset); 659 writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET 660 + 2 * bank->eint_offset); 661 writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET 662 + 2 * bank->eint_offset + 4); 663 } 664 665 void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) 666 { 667 struct samsung_pin_bank *bank = drvdata->pin_banks; 668 int i; 669 670 for (i = 0; i < drvdata->nr_banks; ++i, ++bank) 671 if (bank->eint_type == EINT_TYPE_GPIO) 672 exynos_pinctrl_resume_bank(drvdata, bank); 673 } 674 675 static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata) 676 { 677 if (drvdata->retention_ctrl->refcnt) 678 atomic_inc(drvdata->retention_ctrl->refcnt); 679 } 680 681 static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata) 682 { 683 struct samsung_retention_ctrl *ctrl = drvdata->retention_ctrl; 684 struct regmap *pmu_regs = ctrl->priv; 685 int i; 686 687 if (ctrl->refcnt && !atomic_dec_and_test(ctrl->refcnt)) 688 return; 689 690 for (i = 0; i < ctrl->nr_regs; i++) 691 regmap_write(pmu_regs, ctrl->regs[i], ctrl->value); 692 } 693 694 struct samsung_retention_ctrl * 695 exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata, 696 const struct samsung_retention_data *data) 697 { 698 struct samsung_retention_ctrl *ctrl; 699 struct regmap *pmu_regs; 700 int i; 701 702 ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL); 703 if (!ctrl) 704 return ERR_PTR(-ENOMEM); 705 706 pmu_regs = exynos_get_pmu_regmap(); 707 if (IS_ERR(pmu_regs)) 708 return ERR_CAST(pmu_regs); 709 710 ctrl->priv = pmu_regs; 711 ctrl->regs = data->regs; 712 ctrl->nr_regs = data->nr_regs; 713 ctrl->value = data->value; 714 ctrl->refcnt = data->refcnt; 715 ctrl->enable = exynos_retention_enable; 716 ctrl->disable = exynos_retention_disable; 717 718 /* Ensure that retention is disabled on driver init */ 719 for (i = 0; i < ctrl->nr_regs; i++) 720 regmap_write(pmu_regs, ctrl->regs[i], ctrl->value); 721 722 return ctrl; 723 } 724