1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Exynos specific support for Samsung pinctrl/gpiolib driver with eint support.
4 //
5 // Copyright (c) 2012 Samsung Electronics Co., Ltd.
6 //		http://www.samsung.com
7 // Copyright (c) 2012 Linaro Ltd
8 //		http://www.linaro.org
9 //
10 // Author: Thomas Abraham <thomas.ab@samsung.com>
11 //
12 // This file contains the Samsung Exynos specific information required by the
13 // the Samsung pinctrl/gpiolib driver. It also includes the implementation of
14 // external gpio and wakeup interrupt support.
15 
16 #include <linux/device.h>
17 #include <linux/interrupt.h>
18 #include <linux/irqdomain.h>
19 #include <linux/irq.h>
20 #include <linux/irqchip/chained_irq.h>
21 #include <linux/of.h>
22 #include <linux/of_irq.h>
23 #include <linux/slab.h>
24 #include <linux/spinlock.h>
25 #include <linux/regmap.h>
26 #include <linux/err.h>
27 #include <linux/soc/samsung/exynos-pmu.h>
28 #include <linux/soc/samsung/exynos-regs-pmu.h>
29 
30 #include "pinctrl-samsung.h"
31 #include "pinctrl-exynos.h"
32 
33 struct exynos_irq_chip {
34 	struct irq_chip chip;
35 
36 	u32 eint_con;
37 	u32 eint_mask;
38 	u32 eint_pend;
39 	u32 *eint_wake_mask_value;
40 	u32 eint_wake_mask_reg;
41 	void (*set_eint_wakeup_mask)(struct samsung_pinctrl_drv_data *drvdata,
42 				     struct exynos_irq_chip *irq_chip);
43 };
44 
45 static inline struct exynos_irq_chip *to_exynos_irq_chip(struct irq_chip *chip)
46 {
47 	return container_of(chip, struct exynos_irq_chip, chip);
48 }
49 
50 static void exynos_irq_mask(struct irq_data *irqd)
51 {
52 	struct irq_chip *chip = irq_data_get_irq_chip(irqd);
53 	struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
54 	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
55 	unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset;
56 	unsigned int mask;
57 	unsigned long flags;
58 
59 	raw_spin_lock_irqsave(&bank->slock, flags);
60 
61 	mask = readl(bank->eint_base + reg_mask);
62 	mask |= 1 << irqd->hwirq;
63 	writel(mask, bank->eint_base + reg_mask);
64 
65 	raw_spin_unlock_irqrestore(&bank->slock, flags);
66 }
67 
68 static void exynos_irq_ack(struct irq_data *irqd)
69 {
70 	struct irq_chip *chip = irq_data_get_irq_chip(irqd);
71 	struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
72 	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
73 	unsigned long reg_pend = our_chip->eint_pend + bank->eint_offset;
74 
75 	writel(1 << irqd->hwirq, bank->eint_base + reg_pend);
76 }
77 
78 static void exynos_irq_unmask(struct irq_data *irqd)
79 {
80 	struct irq_chip *chip = irq_data_get_irq_chip(irqd);
81 	struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
82 	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
83 	unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset;
84 	unsigned int mask;
85 	unsigned long flags;
86 
87 	/*
88 	 * Ack level interrupts right before unmask
89 	 *
90 	 * If we don't do this we'll get a double-interrupt.  Level triggered
91 	 * interrupts must not fire an interrupt if the level is not
92 	 * _currently_ active, even if it was active while the interrupt was
93 	 * masked.
94 	 */
95 	if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK)
96 		exynos_irq_ack(irqd);
97 
98 	raw_spin_lock_irqsave(&bank->slock, flags);
99 
100 	mask = readl(bank->eint_base + reg_mask);
101 	mask &= ~(1 << irqd->hwirq);
102 	writel(mask, bank->eint_base + reg_mask);
103 
104 	raw_spin_unlock_irqrestore(&bank->slock, flags);
105 }
106 
107 static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type)
108 {
109 	struct irq_chip *chip = irq_data_get_irq_chip(irqd);
110 	struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
111 	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
112 	unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
113 	unsigned int con, trig_type;
114 	unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
115 
116 	switch (type) {
117 	case IRQ_TYPE_EDGE_RISING:
118 		trig_type = EXYNOS_EINT_EDGE_RISING;
119 		break;
120 	case IRQ_TYPE_EDGE_FALLING:
121 		trig_type = EXYNOS_EINT_EDGE_FALLING;
122 		break;
123 	case IRQ_TYPE_EDGE_BOTH:
124 		trig_type = EXYNOS_EINT_EDGE_BOTH;
125 		break;
126 	case IRQ_TYPE_LEVEL_HIGH:
127 		trig_type = EXYNOS_EINT_LEVEL_HIGH;
128 		break;
129 	case IRQ_TYPE_LEVEL_LOW:
130 		trig_type = EXYNOS_EINT_LEVEL_LOW;
131 		break;
132 	default:
133 		pr_err("unsupported external interrupt type\n");
134 		return -EINVAL;
135 	}
136 
137 	if (type & IRQ_TYPE_EDGE_BOTH)
138 		irq_set_handler_locked(irqd, handle_edge_irq);
139 	else
140 		irq_set_handler_locked(irqd, handle_level_irq);
141 
142 	con = readl(bank->eint_base + reg_con);
143 	con &= ~(EXYNOS_EINT_CON_MASK << shift);
144 	con |= trig_type << shift;
145 	writel(con, bank->eint_base + reg_con);
146 
147 	return 0;
148 }
149 
150 static int exynos_irq_request_resources(struct irq_data *irqd)
151 {
152 	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
153 	const struct samsung_pin_bank_type *bank_type = bank->type;
154 	unsigned long reg_con, flags;
155 	unsigned int shift, mask, con;
156 	int ret;
157 
158 	ret = gpiochip_lock_as_irq(&bank->gpio_chip, irqd->hwirq);
159 	if (ret) {
160 		dev_err(bank->gpio_chip.parent,
161 			"unable to lock pin %s-%lu IRQ\n",
162 			bank->name, irqd->hwirq);
163 		return ret;
164 	}
165 
166 	reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
167 	shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
168 	mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
169 
170 	raw_spin_lock_irqsave(&bank->slock, flags);
171 
172 	con = readl(bank->pctl_base + reg_con);
173 	con &= ~(mask << shift);
174 	con |= EXYNOS_PIN_CON_FUNC_EINT << shift;
175 	writel(con, bank->pctl_base + reg_con);
176 
177 	raw_spin_unlock_irqrestore(&bank->slock, flags);
178 
179 	return 0;
180 }
181 
182 static void exynos_irq_release_resources(struct irq_data *irqd)
183 {
184 	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
185 	const struct samsung_pin_bank_type *bank_type = bank->type;
186 	unsigned long reg_con, flags;
187 	unsigned int shift, mask, con;
188 
189 	reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
190 	shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
191 	mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
192 
193 	raw_spin_lock_irqsave(&bank->slock, flags);
194 
195 	con = readl(bank->pctl_base + reg_con);
196 	con &= ~(mask << shift);
197 	con |= PIN_CON_FUNC_INPUT << shift;
198 	writel(con, bank->pctl_base + reg_con);
199 
200 	raw_spin_unlock_irqrestore(&bank->slock, flags);
201 
202 	gpiochip_unlock_as_irq(&bank->gpio_chip, irqd->hwirq);
203 }
204 
205 /*
206  * irq_chip for gpio interrupts.
207  */
208 static const struct exynos_irq_chip exynos_gpio_irq_chip __initconst = {
209 	.chip = {
210 		.name = "exynos_gpio_irq_chip",
211 		.irq_unmask = exynos_irq_unmask,
212 		.irq_mask = exynos_irq_mask,
213 		.irq_ack = exynos_irq_ack,
214 		.irq_set_type = exynos_irq_set_type,
215 		.irq_request_resources = exynos_irq_request_resources,
216 		.irq_release_resources = exynos_irq_release_resources,
217 	},
218 	.eint_con = EXYNOS_GPIO_ECON_OFFSET,
219 	.eint_mask = EXYNOS_GPIO_EMASK_OFFSET,
220 	.eint_pend = EXYNOS_GPIO_EPEND_OFFSET,
221 	/* eint_wake_mask_value not used */
222 };
223 
224 static int exynos_eint_irq_map(struct irq_domain *h, unsigned int virq,
225 					irq_hw_number_t hw)
226 {
227 	struct samsung_pin_bank *b = h->host_data;
228 
229 	irq_set_chip_data(virq, b);
230 	irq_set_chip_and_handler(virq, &b->irq_chip->chip,
231 					handle_level_irq);
232 	return 0;
233 }
234 
235 /*
236  * irq domain callbacks for external gpio and wakeup interrupt controllers.
237  */
238 static const struct irq_domain_ops exynos_eint_irqd_ops = {
239 	.map	= exynos_eint_irq_map,
240 	.xlate	= irq_domain_xlate_twocell,
241 };
242 
243 static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
244 {
245 	struct samsung_pinctrl_drv_data *d = data;
246 	struct samsung_pin_bank *bank = d->pin_banks;
247 	unsigned int svc, group, pin;
248 	int ret;
249 
250 	svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET);
251 	group = EXYNOS_SVC_GROUP(svc);
252 	pin = svc & EXYNOS_SVC_NUM_MASK;
253 
254 	if (!group)
255 		return IRQ_HANDLED;
256 	bank += (group - 1);
257 
258 	ret = generic_handle_domain_irq(bank->irq_domain, pin);
259 	if (ret)
260 		return IRQ_NONE;
261 
262 	return IRQ_HANDLED;
263 }
264 
265 struct exynos_eint_gpio_save {
266 	u32 eint_con;
267 	u32 eint_fltcon0;
268 	u32 eint_fltcon1;
269 	u32 eint_mask;
270 };
271 
272 /*
273  * exynos_eint_gpio_init() - setup handling of external gpio interrupts.
274  * @d: driver data of samsung pinctrl driver.
275  */
276 __init int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
277 {
278 	struct samsung_pin_bank *bank;
279 	struct device *dev = d->dev;
280 	int ret;
281 	int i;
282 
283 	if (!d->irq) {
284 		dev_err(dev, "irq number not available\n");
285 		return -EINVAL;
286 	}
287 
288 	ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq,
289 					0, dev_name(dev), d);
290 	if (ret) {
291 		dev_err(dev, "irq request failed\n");
292 		return -ENXIO;
293 	}
294 
295 	bank = d->pin_banks;
296 	for (i = 0; i < d->nr_banks; ++i, ++bank) {
297 		if (bank->eint_type != EINT_TYPE_GPIO)
298 			continue;
299 
300 		bank->irq_chip = devm_kmemdup(dev, &exynos_gpio_irq_chip,
301 					   sizeof(*bank->irq_chip), GFP_KERNEL);
302 		if (!bank->irq_chip) {
303 			ret = -ENOMEM;
304 			goto err_domains;
305 		}
306 		bank->irq_chip->chip.name = bank->name;
307 
308 		bank->irq_domain = irq_domain_create_linear(bank->fwnode,
309 				bank->nr_pins, &exynos_eint_irqd_ops, bank);
310 		if (!bank->irq_domain) {
311 			dev_err(dev, "gpio irq domain add failed\n");
312 			ret = -ENXIO;
313 			goto err_domains;
314 		}
315 
316 		bank->soc_priv = devm_kzalloc(d->dev,
317 			sizeof(struct exynos_eint_gpio_save), GFP_KERNEL);
318 		if (!bank->soc_priv) {
319 			irq_domain_remove(bank->irq_domain);
320 			ret = -ENOMEM;
321 			goto err_domains;
322 		}
323 
324 	}
325 
326 	return 0;
327 
328 err_domains:
329 	for (--i, --bank; i >= 0; --i, --bank) {
330 		if (bank->eint_type != EINT_TYPE_GPIO)
331 			continue;
332 		irq_domain_remove(bank->irq_domain);
333 	}
334 
335 	return ret;
336 }
337 
338 static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on)
339 {
340 	struct irq_chip *chip = irq_data_get_irq_chip(irqd);
341 	struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
342 	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
343 	unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq);
344 
345 	pr_info("wake %s for irq %u (%s-%lu)\n", on ? "enabled" : "disabled",
346 		irqd->irq, bank->name, irqd->hwirq);
347 
348 	if (!on)
349 		*our_chip->eint_wake_mask_value |= bit;
350 	else
351 		*our_chip->eint_wake_mask_value &= ~bit;
352 
353 	return 0;
354 }
355 
356 static void
357 exynos_pinctrl_set_eint_wakeup_mask(struct samsung_pinctrl_drv_data *drvdata,
358 				    struct exynos_irq_chip *irq_chip)
359 {
360 	struct regmap *pmu_regs;
361 
362 	if (!drvdata->retention_ctrl || !drvdata->retention_ctrl->priv) {
363 		dev_warn(drvdata->dev,
364 			 "No retention data configured bank with external wakeup interrupt. Wake-up mask will not be set.\n");
365 		return;
366 	}
367 
368 	pmu_regs = drvdata->retention_ctrl->priv;
369 	dev_info(drvdata->dev,
370 		 "Setting external wakeup interrupt mask: 0x%x\n",
371 		 *irq_chip->eint_wake_mask_value);
372 
373 	regmap_write(pmu_regs, irq_chip->eint_wake_mask_reg,
374 		     *irq_chip->eint_wake_mask_value);
375 }
376 
377 static void
378 s5pv210_pinctrl_set_eint_wakeup_mask(struct samsung_pinctrl_drv_data *drvdata,
379 				    struct exynos_irq_chip *irq_chip)
380 
381 {
382 	void __iomem *clk_base;
383 
384 	if (!drvdata->retention_ctrl || !drvdata->retention_ctrl->priv) {
385 		dev_warn(drvdata->dev,
386 			 "No retention data configured bank with external wakeup interrupt. Wake-up mask will not be set.\n");
387 		return;
388 	}
389 
390 
391 	clk_base = (void __iomem *) drvdata->retention_ctrl->priv;
392 
393 	__raw_writel(*irq_chip->eint_wake_mask_value,
394 		     clk_base + irq_chip->eint_wake_mask_reg);
395 }
396 
397 static u32 eint_wake_mask_value = EXYNOS_EINT_WAKEUP_MASK_DISABLED;
398 /*
399  * irq_chip for wakeup interrupts
400  */
401 static const struct exynos_irq_chip s5pv210_wkup_irq_chip __initconst = {
402 	.chip = {
403 		.name = "s5pv210_wkup_irq_chip",
404 		.irq_unmask = exynos_irq_unmask,
405 		.irq_mask = exynos_irq_mask,
406 		.irq_ack = exynos_irq_ack,
407 		.irq_set_type = exynos_irq_set_type,
408 		.irq_set_wake = exynos_wkup_irq_set_wake,
409 		.irq_request_resources = exynos_irq_request_resources,
410 		.irq_release_resources = exynos_irq_release_resources,
411 	},
412 	.eint_con = EXYNOS_WKUP_ECON_OFFSET,
413 	.eint_mask = EXYNOS_WKUP_EMASK_OFFSET,
414 	.eint_pend = EXYNOS_WKUP_EPEND_OFFSET,
415 	.eint_wake_mask_value = &eint_wake_mask_value,
416 	/* Only differences with exynos4210_wkup_irq_chip: */
417 	.eint_wake_mask_reg = S5PV210_EINT_WAKEUP_MASK,
418 	.set_eint_wakeup_mask = s5pv210_pinctrl_set_eint_wakeup_mask,
419 };
420 
421 static const struct exynos_irq_chip exynos4210_wkup_irq_chip __initconst = {
422 	.chip = {
423 		.name = "exynos4210_wkup_irq_chip",
424 		.irq_unmask = exynos_irq_unmask,
425 		.irq_mask = exynos_irq_mask,
426 		.irq_ack = exynos_irq_ack,
427 		.irq_set_type = exynos_irq_set_type,
428 		.irq_set_wake = exynos_wkup_irq_set_wake,
429 		.irq_request_resources = exynos_irq_request_resources,
430 		.irq_release_resources = exynos_irq_release_resources,
431 	},
432 	.eint_con = EXYNOS_WKUP_ECON_OFFSET,
433 	.eint_mask = EXYNOS_WKUP_EMASK_OFFSET,
434 	.eint_pend = EXYNOS_WKUP_EPEND_OFFSET,
435 	.eint_wake_mask_value = &eint_wake_mask_value,
436 	.eint_wake_mask_reg = EXYNOS_EINT_WAKEUP_MASK,
437 	.set_eint_wakeup_mask = exynos_pinctrl_set_eint_wakeup_mask,
438 };
439 
440 static const struct exynos_irq_chip exynos7_wkup_irq_chip __initconst = {
441 	.chip = {
442 		.name = "exynos7_wkup_irq_chip",
443 		.irq_unmask = exynos_irq_unmask,
444 		.irq_mask = exynos_irq_mask,
445 		.irq_ack = exynos_irq_ack,
446 		.irq_set_type = exynos_irq_set_type,
447 		.irq_set_wake = exynos_wkup_irq_set_wake,
448 		.irq_request_resources = exynos_irq_request_resources,
449 		.irq_release_resources = exynos_irq_release_resources,
450 	},
451 	.eint_con = EXYNOS7_WKUP_ECON_OFFSET,
452 	.eint_mask = EXYNOS7_WKUP_EMASK_OFFSET,
453 	.eint_pend = EXYNOS7_WKUP_EPEND_OFFSET,
454 	.eint_wake_mask_value = &eint_wake_mask_value,
455 	.eint_wake_mask_reg = EXYNOS5433_EINT_WAKEUP_MASK,
456 	.set_eint_wakeup_mask = exynos_pinctrl_set_eint_wakeup_mask,
457 };
458 
459 /* list of external wakeup controllers supported */
460 static const struct of_device_id exynos_wkup_irq_ids[] = {
461 	{ .compatible = "samsung,s5pv210-wakeup-eint",
462 			.data = &s5pv210_wkup_irq_chip },
463 	{ .compatible = "samsung,exynos4210-wakeup-eint",
464 			.data = &exynos4210_wkup_irq_chip },
465 	{ .compatible = "samsung,exynos7-wakeup-eint",
466 			.data = &exynos7_wkup_irq_chip },
467 	{ .compatible = "samsung,exynos850-wakeup-eint",
468 			.data = &exynos7_wkup_irq_chip },
469 	{ .compatible = "samsung,exynosautov9-wakeup-eint",
470 			.data = &exynos7_wkup_irq_chip },
471 	{ }
472 };
473 
474 /* interrupt handler for wakeup interrupts 0..15 */
475 static void exynos_irq_eint0_15(struct irq_desc *desc)
476 {
477 	struct exynos_weint_data *eintd = irq_desc_get_handler_data(desc);
478 	struct samsung_pin_bank *bank = eintd->bank;
479 	struct irq_chip *chip = irq_desc_get_chip(desc);
480 
481 	chained_irq_enter(chip, desc);
482 
483 	generic_handle_domain_irq(bank->irq_domain, eintd->irq);
484 
485 	chained_irq_exit(chip, desc);
486 }
487 
488 static inline void exynos_irq_demux_eint(unsigned int pend,
489 						struct irq_domain *domain)
490 {
491 	unsigned int irq;
492 
493 	while (pend) {
494 		irq = fls(pend) - 1;
495 		generic_handle_domain_irq(domain, irq);
496 		pend &= ~(1 << irq);
497 	}
498 }
499 
500 /* interrupt handler for wakeup interrupt 16 */
501 static void exynos_irq_demux_eint16_31(struct irq_desc *desc)
502 {
503 	struct irq_chip *chip = irq_desc_get_chip(desc);
504 	struct exynos_muxed_weint_data *eintd = irq_desc_get_handler_data(desc);
505 	unsigned int pend;
506 	unsigned int mask;
507 	int i;
508 
509 	chained_irq_enter(chip, desc);
510 
511 	for (i = 0; i < eintd->nr_banks; ++i) {
512 		struct samsung_pin_bank *b = eintd->banks[i];
513 		pend = readl(b->eint_base + b->irq_chip->eint_pend
514 				+ b->eint_offset);
515 		mask = readl(b->eint_base + b->irq_chip->eint_mask
516 				+ b->eint_offset);
517 		exynos_irq_demux_eint(pend & ~mask, b->irq_domain);
518 	}
519 
520 	chained_irq_exit(chip, desc);
521 }
522 
523 /*
524  * exynos_eint_wkup_init() - setup handling of external wakeup interrupts.
525  * @d: driver data of samsung pinctrl driver.
526  */
527 __init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
528 {
529 	struct device *dev = d->dev;
530 	struct device_node *wkup_np = NULL;
531 	struct device_node *np;
532 	struct samsung_pin_bank *bank;
533 	struct exynos_weint_data *weint_data;
534 	struct exynos_muxed_weint_data *muxed_data;
535 	const struct exynos_irq_chip *irq_chip;
536 	unsigned int muxed_banks = 0;
537 	unsigned int i;
538 	int idx, irq;
539 
540 	for_each_child_of_node(dev->of_node, np) {
541 		const struct of_device_id *match;
542 
543 		match = of_match_node(exynos_wkup_irq_ids, np);
544 		if (match) {
545 			irq_chip = match->data;
546 			wkup_np = np;
547 			break;
548 		}
549 	}
550 	if (!wkup_np)
551 		return -ENODEV;
552 
553 	bank = d->pin_banks;
554 	for (i = 0; i < d->nr_banks; ++i, ++bank) {
555 		if (bank->eint_type != EINT_TYPE_WKUP)
556 			continue;
557 
558 		bank->irq_chip = devm_kmemdup(dev, irq_chip, sizeof(*irq_chip),
559 					      GFP_KERNEL);
560 		if (!bank->irq_chip) {
561 			of_node_put(wkup_np);
562 			return -ENOMEM;
563 		}
564 		bank->irq_chip->chip.name = bank->name;
565 
566 		bank->irq_domain = irq_domain_create_linear(bank->fwnode,
567 				bank->nr_pins, &exynos_eint_irqd_ops, bank);
568 		if (!bank->irq_domain) {
569 			dev_err(dev, "wkup irq domain add failed\n");
570 			of_node_put(wkup_np);
571 			return -ENXIO;
572 		}
573 
574 		if (!fwnode_property_present(bank->fwnode, "interrupts")) {
575 			bank->eint_type = EINT_TYPE_WKUP_MUX;
576 			++muxed_banks;
577 			continue;
578 		}
579 
580 		weint_data = devm_kcalloc(dev,
581 					  bank->nr_pins, sizeof(*weint_data),
582 					  GFP_KERNEL);
583 		if (!weint_data) {
584 			of_node_put(wkup_np);
585 			return -ENOMEM;
586 		}
587 
588 		for (idx = 0; idx < bank->nr_pins; ++idx) {
589 			irq = irq_of_parse_and_map(to_of_node(bank->fwnode), idx);
590 			if (!irq) {
591 				dev_err(dev, "irq number for eint-%s-%d not found\n",
592 							bank->name, idx);
593 				continue;
594 			}
595 			weint_data[idx].irq = idx;
596 			weint_data[idx].bank = bank;
597 			irq_set_chained_handler_and_data(irq,
598 							 exynos_irq_eint0_15,
599 							 &weint_data[idx]);
600 		}
601 	}
602 
603 	if (!muxed_banks) {
604 		of_node_put(wkup_np);
605 		return 0;
606 	}
607 
608 	irq = irq_of_parse_and_map(wkup_np, 0);
609 	of_node_put(wkup_np);
610 	if (!irq) {
611 		dev_err(dev, "irq number for muxed EINTs not found\n");
612 		return 0;
613 	}
614 
615 	muxed_data = devm_kzalloc(dev, sizeof(*muxed_data)
616 		+ muxed_banks*sizeof(struct samsung_pin_bank *), GFP_KERNEL);
617 	if (!muxed_data)
618 		return -ENOMEM;
619 
620 	irq_set_chained_handler_and_data(irq, exynos_irq_demux_eint16_31,
621 					 muxed_data);
622 
623 	bank = d->pin_banks;
624 	idx = 0;
625 	for (i = 0; i < d->nr_banks; ++i, ++bank) {
626 		if (bank->eint_type != EINT_TYPE_WKUP_MUX)
627 			continue;
628 
629 		muxed_data->banks[idx++] = bank;
630 	}
631 	muxed_data->nr_banks = muxed_banks;
632 
633 	return 0;
634 }
635 
636 static void exynos_pinctrl_suspend_bank(
637 				struct samsung_pinctrl_drv_data *drvdata,
638 				struct samsung_pin_bank *bank)
639 {
640 	struct exynos_eint_gpio_save *save = bank->soc_priv;
641 	void __iomem *regs = bank->eint_base;
642 
643 	save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET
644 						+ bank->eint_offset);
645 	save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
646 						+ 2 * bank->eint_offset);
647 	save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
648 						+ 2 * bank->eint_offset + 4);
649 	save->eint_mask = readl(regs + bank->irq_chip->eint_mask
650 						+ bank->eint_offset);
651 
652 	pr_debug("%s: save     con %#010x\n", bank->name, save->eint_con);
653 	pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0);
654 	pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1);
655 	pr_debug("%s: save    mask %#010x\n", bank->name, save->eint_mask);
656 }
657 
658 void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
659 {
660 	struct samsung_pin_bank *bank = drvdata->pin_banks;
661 	struct exynos_irq_chip *irq_chip = NULL;
662 	int i;
663 
664 	for (i = 0; i < drvdata->nr_banks; ++i, ++bank) {
665 		if (bank->eint_type == EINT_TYPE_GPIO)
666 			exynos_pinctrl_suspend_bank(drvdata, bank);
667 		else if (bank->eint_type == EINT_TYPE_WKUP) {
668 			if (!irq_chip) {
669 				irq_chip = bank->irq_chip;
670 				irq_chip->set_eint_wakeup_mask(drvdata,
671 							       irq_chip);
672 			}
673 		}
674 	}
675 }
676 
677 static void exynos_pinctrl_resume_bank(
678 				struct samsung_pinctrl_drv_data *drvdata,
679 				struct samsung_pin_bank *bank)
680 {
681 	struct exynos_eint_gpio_save *save = bank->soc_priv;
682 	void __iomem *regs = bank->eint_base;
683 
684 	pr_debug("%s:     con %#010x => %#010x\n", bank->name,
685 			readl(regs + EXYNOS_GPIO_ECON_OFFSET
686 			+ bank->eint_offset), save->eint_con);
687 	pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,
688 			readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
689 			+ 2 * bank->eint_offset), save->eint_fltcon0);
690 	pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,
691 			readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
692 			+ 2 * bank->eint_offset + 4), save->eint_fltcon1);
693 	pr_debug("%s:    mask %#010x => %#010x\n", bank->name,
694 			readl(regs + bank->irq_chip->eint_mask
695 			+ bank->eint_offset), save->eint_mask);
696 
697 	writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET
698 						+ bank->eint_offset);
699 	writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET
700 						+ 2 * bank->eint_offset);
701 	writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET
702 						+ 2 * bank->eint_offset + 4);
703 	writel(save->eint_mask, regs + bank->irq_chip->eint_mask
704 						+ bank->eint_offset);
705 }
706 
707 void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
708 {
709 	struct samsung_pin_bank *bank = drvdata->pin_banks;
710 	int i;
711 
712 	for (i = 0; i < drvdata->nr_banks; ++i, ++bank)
713 		if (bank->eint_type == EINT_TYPE_GPIO)
714 			exynos_pinctrl_resume_bank(drvdata, bank);
715 }
716 
717 static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata)
718 {
719 	if (drvdata->retention_ctrl->refcnt)
720 		atomic_inc(drvdata->retention_ctrl->refcnt);
721 }
722 
723 static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
724 {
725 	struct samsung_retention_ctrl *ctrl = drvdata->retention_ctrl;
726 	struct regmap *pmu_regs = ctrl->priv;
727 	int i;
728 
729 	if (ctrl->refcnt && !atomic_dec_and_test(ctrl->refcnt))
730 		return;
731 
732 	for (i = 0; i < ctrl->nr_regs; i++)
733 		regmap_write(pmu_regs, ctrl->regs[i], ctrl->value);
734 }
735 
736 struct samsung_retention_ctrl *
737 exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata,
738 		      const struct samsung_retention_data *data)
739 {
740 	struct samsung_retention_ctrl *ctrl;
741 	struct regmap *pmu_regs;
742 	int i;
743 
744 	ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL);
745 	if (!ctrl)
746 		return ERR_PTR(-ENOMEM);
747 
748 	pmu_regs = exynos_get_pmu_regmap();
749 	if (IS_ERR(pmu_regs))
750 		return ERR_CAST(pmu_regs);
751 
752 	ctrl->priv = pmu_regs;
753 	ctrl->regs = data->regs;
754 	ctrl->nr_regs = data->nr_regs;
755 	ctrl->value = data->value;
756 	ctrl->refcnt = data->refcnt;
757 	ctrl->enable = exynos_retention_enable;
758 	ctrl->disable = exynos_retention_disable;
759 
760 	/* Ensure that retention is disabled on driver init */
761 	for (i = 0; i < ctrl->nr_regs; i++)
762 		regmap_write(pmu_regs, ctrl->regs[i], ctrl->value);
763 
764 	return ctrl;
765 }
766