1 /* 2 * Exynos specific support for Samsung pinctrl/gpiolib driver with eint support. 3 * 4 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 5 * http://www.samsung.com 6 * Copyright (c) 2012 Linaro Ltd 7 * http://www.linaro.org 8 * 9 * Author: Thomas Abraham <thomas.ab@samsung.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * This file contains the Samsung Exynos specific information required by the 17 * the Samsung pinctrl/gpiolib driver. It also includes the implementation of 18 * external gpio and wakeup interrupt support. 19 */ 20 21 #include <linux/module.h> 22 #include <linux/device.h> 23 #include <linux/interrupt.h> 24 #include <linux/irqdomain.h> 25 #include <linux/irq.h> 26 #include <linux/irqchip/chained_irq.h> 27 #include <linux/of_address.h> 28 #include <linux/of_irq.h> 29 #include <linux/io.h> 30 #include <linux/slab.h> 31 #include <linux/spinlock.h> 32 #include <linux/regmap.h> 33 #include <linux/err.h> 34 #include <linux/soc/samsung/exynos-pmu.h> 35 #include <linux/soc/samsung/exynos-regs-pmu.h> 36 37 #include "pinctrl-samsung.h" 38 #include "pinctrl-exynos.h" 39 40 struct exynos_irq_chip { 41 struct irq_chip chip; 42 43 u32 eint_con; 44 u32 eint_mask; 45 u32 eint_pend; 46 }; 47 48 static inline struct exynos_irq_chip *to_exynos_irq_chip(struct irq_chip *chip) 49 { 50 return container_of(chip, struct exynos_irq_chip, chip); 51 } 52 53 static const struct samsung_pin_bank_type bank_type_off = { 54 .fld_width = { 4, 1, 2, 2, 2, 2, }, 55 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, 56 }; 57 58 static const struct samsung_pin_bank_type bank_type_alive = { 59 .fld_width = { 4, 1, 2, 2, }, 60 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, 61 }; 62 63 /* Exynos5433 has the 4bit widths for PINCFG_TYPE_DRV bitfields. */ 64 static const struct samsung_pin_bank_type exynos5433_bank_type_off = { 65 .fld_width = { 4, 1, 2, 4, 2, 2, }, 66 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, 67 }; 68 69 static const struct samsung_pin_bank_type exynos5433_bank_type_alive = { 70 .fld_width = { 4, 1, 2, 4, }, 71 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, 72 }; 73 74 static void exynos_irq_mask(struct irq_data *irqd) 75 { 76 struct irq_chip *chip = irq_data_get_irq_chip(irqd); 77 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); 78 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 79 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; 80 unsigned long mask; 81 unsigned long flags; 82 83 spin_lock_irqsave(&bank->slock, flags); 84 85 mask = readl(bank->eint_base + reg_mask); 86 mask |= 1 << irqd->hwirq; 87 writel(mask, bank->eint_base + reg_mask); 88 89 spin_unlock_irqrestore(&bank->slock, flags); 90 } 91 92 static void exynos_irq_ack(struct irq_data *irqd) 93 { 94 struct irq_chip *chip = irq_data_get_irq_chip(irqd); 95 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); 96 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 97 unsigned long reg_pend = our_chip->eint_pend + bank->eint_offset; 98 99 writel(1 << irqd->hwirq, bank->eint_base + reg_pend); 100 } 101 102 static void exynos_irq_unmask(struct irq_data *irqd) 103 { 104 struct irq_chip *chip = irq_data_get_irq_chip(irqd); 105 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); 106 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 107 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; 108 unsigned long mask; 109 unsigned long flags; 110 111 /* 112 * Ack level interrupts right before unmask 113 * 114 * If we don't do this we'll get a double-interrupt. Level triggered 115 * interrupts must not fire an interrupt if the level is not 116 * _currently_ active, even if it was active while the interrupt was 117 * masked. 118 */ 119 if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK) 120 exynos_irq_ack(irqd); 121 122 spin_lock_irqsave(&bank->slock, flags); 123 124 mask = readl(bank->eint_base + reg_mask); 125 mask &= ~(1 << irqd->hwirq); 126 writel(mask, bank->eint_base + reg_mask); 127 128 spin_unlock_irqrestore(&bank->slock, flags); 129 } 130 131 static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type) 132 { 133 struct irq_chip *chip = irq_data_get_irq_chip(irqd); 134 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); 135 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 136 unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq; 137 unsigned int con, trig_type; 138 unsigned long reg_con = our_chip->eint_con + bank->eint_offset; 139 140 switch (type) { 141 case IRQ_TYPE_EDGE_RISING: 142 trig_type = EXYNOS_EINT_EDGE_RISING; 143 break; 144 case IRQ_TYPE_EDGE_FALLING: 145 trig_type = EXYNOS_EINT_EDGE_FALLING; 146 break; 147 case IRQ_TYPE_EDGE_BOTH: 148 trig_type = EXYNOS_EINT_EDGE_BOTH; 149 break; 150 case IRQ_TYPE_LEVEL_HIGH: 151 trig_type = EXYNOS_EINT_LEVEL_HIGH; 152 break; 153 case IRQ_TYPE_LEVEL_LOW: 154 trig_type = EXYNOS_EINT_LEVEL_LOW; 155 break; 156 default: 157 pr_err("unsupported external interrupt type\n"); 158 return -EINVAL; 159 } 160 161 if (type & IRQ_TYPE_EDGE_BOTH) 162 irq_set_handler_locked(irqd, handle_edge_irq); 163 else 164 irq_set_handler_locked(irqd, handle_level_irq); 165 166 con = readl(bank->eint_base + reg_con); 167 con &= ~(EXYNOS_EINT_CON_MASK << shift); 168 con |= trig_type << shift; 169 writel(con, bank->eint_base + reg_con); 170 171 return 0; 172 } 173 174 static int exynos_irq_request_resources(struct irq_data *irqd) 175 { 176 struct irq_chip *chip = irq_data_get_irq_chip(irqd); 177 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); 178 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 179 const struct samsung_pin_bank_type *bank_type = bank->type; 180 unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq; 181 unsigned long reg_con = our_chip->eint_con + bank->eint_offset; 182 unsigned long flags; 183 unsigned int mask; 184 unsigned int con; 185 int ret; 186 187 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irqd->hwirq); 188 if (ret) { 189 dev_err(bank->gpio_chip.parent, 190 "unable to lock pin %s-%lu IRQ\n", 191 bank->name, irqd->hwirq); 192 return ret; 193 } 194 195 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; 196 shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC]; 197 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; 198 199 spin_lock_irqsave(&bank->slock, flags); 200 201 con = readl(bank->eint_base + reg_con); 202 con &= ~(mask << shift); 203 con |= EXYNOS_EINT_FUNC << shift; 204 writel(con, bank->eint_base + reg_con); 205 206 spin_unlock_irqrestore(&bank->slock, flags); 207 208 exynos_irq_unmask(irqd); 209 210 return 0; 211 } 212 213 static void exynos_irq_release_resources(struct irq_data *irqd) 214 { 215 struct irq_chip *chip = irq_data_get_irq_chip(irqd); 216 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); 217 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 218 const struct samsung_pin_bank_type *bank_type = bank->type; 219 unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq; 220 unsigned long reg_con = our_chip->eint_con + bank->eint_offset; 221 unsigned long flags; 222 unsigned int mask; 223 unsigned int con; 224 225 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; 226 shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC]; 227 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; 228 229 exynos_irq_mask(irqd); 230 231 spin_lock_irqsave(&bank->slock, flags); 232 233 con = readl(bank->eint_base + reg_con); 234 con &= ~(mask << shift); 235 con |= FUNC_INPUT << shift; 236 writel(con, bank->eint_base + reg_con); 237 238 spin_unlock_irqrestore(&bank->slock, flags); 239 240 gpiochip_unlock_as_irq(&bank->gpio_chip, irqd->hwirq); 241 } 242 243 /* 244 * irq_chip for gpio interrupts. 245 */ 246 static struct exynos_irq_chip exynos_gpio_irq_chip = { 247 .chip = { 248 .name = "exynos_gpio_irq_chip", 249 .irq_unmask = exynos_irq_unmask, 250 .irq_mask = exynos_irq_mask, 251 .irq_ack = exynos_irq_ack, 252 .irq_set_type = exynos_irq_set_type, 253 .irq_request_resources = exynos_irq_request_resources, 254 .irq_release_resources = exynos_irq_release_resources, 255 }, 256 .eint_con = EXYNOS_GPIO_ECON_OFFSET, 257 .eint_mask = EXYNOS_GPIO_EMASK_OFFSET, 258 .eint_pend = EXYNOS_GPIO_EPEND_OFFSET, 259 }; 260 261 static int exynos_eint_irq_map(struct irq_domain *h, unsigned int virq, 262 irq_hw_number_t hw) 263 { 264 struct samsung_pin_bank *b = h->host_data; 265 266 irq_set_chip_data(virq, b); 267 irq_set_chip_and_handler(virq, &b->irq_chip->chip, 268 handle_level_irq); 269 return 0; 270 } 271 272 /* 273 * irq domain callbacks for external gpio and wakeup interrupt controllers. 274 */ 275 static const struct irq_domain_ops exynos_eint_irqd_ops = { 276 .map = exynos_eint_irq_map, 277 .xlate = irq_domain_xlate_twocell, 278 }; 279 280 static irqreturn_t exynos_eint_gpio_irq(int irq, void *data) 281 { 282 struct samsung_pinctrl_drv_data *d = data; 283 struct samsung_pin_bank *bank = d->pin_banks; 284 unsigned int svc, group, pin, virq; 285 286 svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET); 287 group = EXYNOS_SVC_GROUP(svc); 288 pin = svc & EXYNOS_SVC_NUM_MASK; 289 290 if (!group) 291 return IRQ_HANDLED; 292 bank += (group - 1); 293 294 virq = irq_linear_revmap(bank->irq_domain, pin); 295 if (!virq) 296 return IRQ_NONE; 297 generic_handle_irq(virq); 298 return IRQ_HANDLED; 299 } 300 301 struct exynos_eint_gpio_save { 302 u32 eint_con; 303 u32 eint_fltcon0; 304 u32 eint_fltcon1; 305 }; 306 307 /* 308 * exynos_eint_gpio_init() - setup handling of external gpio interrupts. 309 * @d: driver data of samsung pinctrl driver. 310 */ 311 static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d) 312 { 313 struct samsung_pin_bank *bank; 314 struct device *dev = d->dev; 315 int ret; 316 int i; 317 318 if (!d->irq) { 319 dev_err(dev, "irq number not available\n"); 320 return -EINVAL; 321 } 322 323 ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq, 324 0, dev_name(dev), d); 325 if (ret) { 326 dev_err(dev, "irq request failed\n"); 327 return -ENXIO; 328 } 329 330 bank = d->pin_banks; 331 for (i = 0; i < d->nr_banks; ++i, ++bank) { 332 if (bank->eint_type != EINT_TYPE_GPIO) 333 continue; 334 bank->irq_domain = irq_domain_add_linear(bank->of_node, 335 bank->nr_pins, &exynos_eint_irqd_ops, bank); 336 if (!bank->irq_domain) { 337 dev_err(dev, "gpio irq domain add failed\n"); 338 ret = -ENXIO; 339 goto err_domains; 340 } 341 342 bank->soc_priv = devm_kzalloc(d->dev, 343 sizeof(struct exynos_eint_gpio_save), GFP_KERNEL); 344 if (!bank->soc_priv) { 345 irq_domain_remove(bank->irq_domain); 346 ret = -ENOMEM; 347 goto err_domains; 348 } 349 350 bank->irq_chip = &exynos_gpio_irq_chip; 351 } 352 353 return 0; 354 355 err_domains: 356 for (--i, --bank; i >= 0; --i, --bank) { 357 if (bank->eint_type != EINT_TYPE_GPIO) 358 continue; 359 irq_domain_remove(bank->irq_domain); 360 } 361 362 return ret; 363 } 364 365 static u32 exynos_eint_wake_mask = 0xffffffff; 366 367 u32 exynos_get_eint_wake_mask(void) 368 { 369 return exynos_eint_wake_mask; 370 } 371 372 static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on) 373 { 374 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 375 unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq); 376 377 pr_info("wake %s for irq %d\n", on ? "enabled" : "disabled", irqd->irq); 378 379 if (!on) 380 exynos_eint_wake_mask |= bit; 381 else 382 exynos_eint_wake_mask &= ~bit; 383 384 return 0; 385 } 386 387 /* 388 * irq_chip for wakeup interrupts 389 */ 390 static struct exynos_irq_chip exynos4210_wkup_irq_chip __initdata = { 391 .chip = { 392 .name = "exynos4210_wkup_irq_chip", 393 .irq_unmask = exynos_irq_unmask, 394 .irq_mask = exynos_irq_mask, 395 .irq_ack = exynos_irq_ack, 396 .irq_set_type = exynos_irq_set_type, 397 .irq_set_wake = exynos_wkup_irq_set_wake, 398 .irq_request_resources = exynos_irq_request_resources, 399 .irq_release_resources = exynos_irq_release_resources, 400 }, 401 .eint_con = EXYNOS_WKUP_ECON_OFFSET, 402 .eint_mask = EXYNOS_WKUP_EMASK_OFFSET, 403 .eint_pend = EXYNOS_WKUP_EPEND_OFFSET, 404 }; 405 406 static struct exynos_irq_chip exynos7_wkup_irq_chip __initdata = { 407 .chip = { 408 .name = "exynos7_wkup_irq_chip", 409 .irq_unmask = exynos_irq_unmask, 410 .irq_mask = exynos_irq_mask, 411 .irq_ack = exynos_irq_ack, 412 .irq_set_type = exynos_irq_set_type, 413 .irq_set_wake = exynos_wkup_irq_set_wake, 414 .irq_request_resources = exynos_irq_request_resources, 415 .irq_release_resources = exynos_irq_release_resources, 416 }, 417 .eint_con = EXYNOS7_WKUP_ECON_OFFSET, 418 .eint_mask = EXYNOS7_WKUP_EMASK_OFFSET, 419 .eint_pend = EXYNOS7_WKUP_EPEND_OFFSET, 420 }; 421 422 /* list of external wakeup controllers supported */ 423 static const struct of_device_id exynos_wkup_irq_ids[] = { 424 { .compatible = "samsung,exynos4210-wakeup-eint", 425 .data = &exynos4210_wkup_irq_chip }, 426 { .compatible = "samsung,exynos7-wakeup-eint", 427 .data = &exynos7_wkup_irq_chip }, 428 { } 429 }; 430 431 /* interrupt handler for wakeup interrupts 0..15 */ 432 static void exynos_irq_eint0_15(struct irq_desc *desc) 433 { 434 struct exynos_weint_data *eintd = irq_desc_get_handler_data(desc); 435 struct samsung_pin_bank *bank = eintd->bank; 436 struct irq_chip *chip = irq_desc_get_chip(desc); 437 int eint_irq; 438 439 chained_irq_enter(chip, desc); 440 441 eint_irq = irq_linear_revmap(bank->irq_domain, eintd->irq); 442 generic_handle_irq(eint_irq); 443 444 chained_irq_exit(chip, desc); 445 } 446 447 static inline void exynos_irq_demux_eint(unsigned long pend, 448 struct irq_domain *domain) 449 { 450 unsigned int irq; 451 452 while (pend) { 453 irq = fls(pend) - 1; 454 generic_handle_irq(irq_find_mapping(domain, irq)); 455 pend &= ~(1 << irq); 456 } 457 } 458 459 /* interrupt handler for wakeup interrupt 16 */ 460 static void exynos_irq_demux_eint16_31(struct irq_desc *desc) 461 { 462 struct irq_chip *chip = irq_desc_get_chip(desc); 463 struct exynos_muxed_weint_data *eintd = irq_desc_get_handler_data(desc); 464 unsigned long pend; 465 unsigned long mask; 466 int i; 467 468 chained_irq_enter(chip, desc); 469 470 for (i = 0; i < eintd->nr_banks; ++i) { 471 struct samsung_pin_bank *b = eintd->banks[i]; 472 pend = readl(b->eint_base + b->irq_chip->eint_pend 473 + b->eint_offset); 474 mask = readl(b->eint_base + b->irq_chip->eint_mask 475 + b->eint_offset); 476 exynos_irq_demux_eint(pend & ~mask, b->irq_domain); 477 } 478 479 chained_irq_exit(chip, desc); 480 } 481 482 /* 483 * exynos_eint_wkup_init() - setup handling of external wakeup interrupts. 484 * @d: driver data of samsung pinctrl driver. 485 */ 486 static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) 487 { 488 struct device *dev = d->dev; 489 struct device_node *wkup_np = NULL; 490 struct device_node *np; 491 struct samsung_pin_bank *bank; 492 struct exynos_weint_data *weint_data; 493 struct exynos_muxed_weint_data *muxed_data; 494 struct exynos_irq_chip *irq_chip; 495 unsigned int muxed_banks = 0; 496 unsigned int i; 497 int idx, irq; 498 499 for_each_child_of_node(dev->of_node, np) { 500 const struct of_device_id *match; 501 502 match = of_match_node(exynos_wkup_irq_ids, np); 503 if (match) { 504 irq_chip = kmemdup(match->data, 505 sizeof(*irq_chip), GFP_KERNEL); 506 wkup_np = np; 507 break; 508 } 509 } 510 if (!wkup_np) 511 return -ENODEV; 512 513 bank = d->pin_banks; 514 for (i = 0; i < d->nr_banks; ++i, ++bank) { 515 if (bank->eint_type != EINT_TYPE_WKUP) 516 continue; 517 518 bank->irq_domain = irq_domain_add_linear(bank->of_node, 519 bank->nr_pins, &exynos_eint_irqd_ops, bank); 520 if (!bank->irq_domain) { 521 dev_err(dev, "wkup irq domain add failed\n"); 522 return -ENXIO; 523 } 524 525 bank->irq_chip = irq_chip; 526 527 if (!of_find_property(bank->of_node, "interrupts", NULL)) { 528 bank->eint_type = EINT_TYPE_WKUP_MUX; 529 ++muxed_banks; 530 continue; 531 } 532 533 weint_data = devm_kzalloc(dev, bank->nr_pins 534 * sizeof(*weint_data), GFP_KERNEL); 535 if (!weint_data) 536 return -ENOMEM; 537 538 for (idx = 0; idx < bank->nr_pins; ++idx) { 539 irq = irq_of_parse_and_map(bank->of_node, idx); 540 if (!irq) { 541 dev_err(dev, "irq number for eint-%s-%d not found\n", 542 bank->name, idx); 543 continue; 544 } 545 weint_data[idx].irq = idx; 546 weint_data[idx].bank = bank; 547 irq_set_chained_handler_and_data(irq, 548 exynos_irq_eint0_15, 549 &weint_data[idx]); 550 } 551 } 552 553 if (!muxed_banks) 554 return 0; 555 556 irq = irq_of_parse_and_map(wkup_np, 0); 557 if (!irq) { 558 dev_err(dev, "irq number for muxed EINTs not found\n"); 559 return 0; 560 } 561 562 muxed_data = devm_kzalloc(dev, sizeof(*muxed_data) 563 + muxed_banks*sizeof(struct samsung_pin_bank *), GFP_KERNEL); 564 if (!muxed_data) 565 return -ENOMEM; 566 567 irq_set_chained_handler_and_data(irq, exynos_irq_demux_eint16_31, 568 muxed_data); 569 570 bank = d->pin_banks; 571 idx = 0; 572 for (i = 0; i < d->nr_banks; ++i, ++bank) { 573 if (bank->eint_type != EINT_TYPE_WKUP_MUX) 574 continue; 575 576 muxed_data->banks[idx++] = bank; 577 } 578 muxed_data->nr_banks = muxed_banks; 579 580 return 0; 581 } 582 583 static void exynos_pinctrl_suspend_bank( 584 struct samsung_pinctrl_drv_data *drvdata, 585 struct samsung_pin_bank *bank) 586 { 587 struct exynos_eint_gpio_save *save = bank->soc_priv; 588 void __iomem *regs = bank->eint_base; 589 590 save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET 591 + bank->eint_offset); 592 save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET 593 + 2 * bank->eint_offset); 594 save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET 595 + 2 * bank->eint_offset + 4); 596 597 pr_debug("%s: save con %#010x\n", bank->name, save->eint_con); 598 pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0); 599 pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1); 600 } 601 602 static void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) 603 { 604 struct samsung_pin_bank *bank = drvdata->pin_banks; 605 int i; 606 607 for (i = 0; i < drvdata->nr_banks; ++i, ++bank) 608 if (bank->eint_type == EINT_TYPE_GPIO) 609 exynos_pinctrl_suspend_bank(drvdata, bank); 610 } 611 612 static void exynos_pinctrl_resume_bank( 613 struct samsung_pinctrl_drv_data *drvdata, 614 struct samsung_pin_bank *bank) 615 { 616 struct exynos_eint_gpio_save *save = bank->soc_priv; 617 void __iomem *regs = bank->eint_base; 618 619 pr_debug("%s: con %#010x => %#010x\n", bank->name, 620 readl(regs + EXYNOS_GPIO_ECON_OFFSET 621 + bank->eint_offset), save->eint_con); 622 pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name, 623 readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET 624 + 2 * bank->eint_offset), save->eint_fltcon0); 625 pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name, 626 readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET 627 + 2 * bank->eint_offset + 4), save->eint_fltcon1); 628 629 writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET 630 + bank->eint_offset); 631 writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET 632 + 2 * bank->eint_offset); 633 writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET 634 + 2 * bank->eint_offset + 4); 635 } 636 637 static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) 638 { 639 struct samsung_pin_bank *bank = drvdata->pin_banks; 640 int i; 641 642 for (i = 0; i < drvdata->nr_banks; ++i, ++bank) 643 if (bank->eint_type == EINT_TYPE_GPIO) 644 exynos_pinctrl_resume_bank(drvdata, bank); 645 } 646 647 /* Retention control for S5PV210 are located at the end of clock controller */ 648 #define S5P_OTHERS 0xE000 649 650 #define S5P_OTHERS_RET_IO (1 << 31) 651 #define S5P_OTHERS_RET_CF (1 << 30) 652 #define S5P_OTHERS_RET_MMC (1 << 29) 653 #define S5P_OTHERS_RET_UART (1 << 28) 654 655 static void s5pv210_retention_disable(struct samsung_pinctrl_drv_data *drvdata) 656 { 657 void *clk_base = drvdata->retention_ctrl->priv; 658 u32 tmp; 659 660 tmp = __raw_readl(clk_base + S5P_OTHERS); 661 tmp |= (S5P_OTHERS_RET_IO | S5P_OTHERS_RET_CF | S5P_OTHERS_RET_MMC | 662 S5P_OTHERS_RET_UART); 663 __raw_writel(tmp, clk_base + S5P_OTHERS); 664 } 665 666 static struct samsung_retention_ctrl * 667 s5pv210_retention_init(struct samsung_pinctrl_drv_data *drvdata, 668 const struct samsung_retention_data *data) 669 { 670 struct samsung_retention_ctrl *ctrl; 671 struct device_node *np; 672 void *clk_base; 673 674 ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL); 675 if (!ctrl) 676 return ERR_PTR(-ENOMEM); 677 678 np = of_find_compatible_node(NULL, NULL, "samsung,s5pv210-clock"); 679 if (!np) { 680 pr_err("%s: failed to find clock controller DT node\n", 681 __func__); 682 return ERR_PTR(-ENODEV); 683 } 684 685 clk_base = of_iomap(np, 0); 686 if (!clk_base) { 687 pr_err("%s: failed to map clock registers\n", __func__); 688 return ERR_PTR(-EINVAL); 689 } 690 691 ctrl->priv = clk_base; 692 ctrl->disable = s5pv210_retention_disable; 693 694 return ctrl; 695 } 696 697 static const struct samsung_retention_data s5pv210_retention_data __initconst = { 698 .init = s5pv210_retention_init, 699 }; 700 701 /* pin banks of s5pv210 pin-controller */ 702 static const struct samsung_pin_bank_data s5pv210_pin_bank[] __initconst = { 703 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 704 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04), 705 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), 706 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), 707 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), 708 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14), 709 EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18), 710 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe0", 0x1c), 711 EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpe1", 0x20), 712 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpf0", 0x24), 713 EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpf1", 0x28), 714 EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpf2", 0x2c), 715 EXYNOS_PIN_BANK_EINTG(6, 0x180, "gpf3", 0x30), 716 EXYNOS_PIN_BANK_EINTG(7, 0x1a0, "gpg0", 0x34), 717 EXYNOS_PIN_BANK_EINTG(7, 0x1c0, "gpg1", 0x38), 718 EXYNOS_PIN_BANK_EINTG(7, 0x1e0, "gpg2", 0x3c), 719 EXYNOS_PIN_BANK_EINTG(7, 0x200, "gpg3", 0x40), 720 EXYNOS_PIN_BANK_EINTN(7, 0x220, "gpi"), 721 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x44), 722 EXYNOS_PIN_BANK_EINTG(6, 0x260, "gpj1", 0x48), 723 EXYNOS_PIN_BANK_EINTG(8, 0x280, "gpj2", 0x4c), 724 EXYNOS_PIN_BANK_EINTG(8, 0x2a0, "gpj3", 0x50), 725 EXYNOS_PIN_BANK_EINTG(5, 0x2c0, "gpj4", 0x54), 726 EXYNOS_PIN_BANK_EINTN(8, 0x2e0, "mp01"), 727 EXYNOS_PIN_BANK_EINTN(4, 0x300, "mp02"), 728 EXYNOS_PIN_BANK_EINTN(8, 0x320, "mp03"), 729 EXYNOS_PIN_BANK_EINTN(8, 0x340, "mp04"), 730 EXYNOS_PIN_BANK_EINTN(8, 0x360, "mp05"), 731 EXYNOS_PIN_BANK_EINTN(8, 0x380, "mp06"), 732 EXYNOS_PIN_BANK_EINTN(8, 0x3a0, "mp07"), 733 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gph0", 0x00), 734 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gph1", 0x04), 735 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gph2", 0x08), 736 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gph3", 0x0c), 737 }; 738 739 const struct samsung_pin_ctrl s5pv210_pin_ctrl[] __initconst = { 740 { 741 /* pin-controller instance 0 data */ 742 .pin_banks = s5pv210_pin_bank, 743 .nr_banks = ARRAY_SIZE(s5pv210_pin_bank), 744 .eint_gpio_init = exynos_eint_gpio_init, 745 .eint_wkup_init = exynos_eint_wkup_init, 746 .suspend = exynos_pinctrl_suspend, 747 .resume = exynos_pinctrl_resume, 748 .retention_data = &s5pv210_retention_data, 749 }, 750 }; 751 752 /* Pad retention control code for accessing PMU regmap */ 753 static atomic_t exynos_shared_retention_refcnt; 754 755 static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata) 756 { 757 if (drvdata->retention_ctrl->refcnt) 758 atomic_inc(drvdata->retention_ctrl->refcnt); 759 } 760 761 static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata) 762 { 763 struct samsung_retention_ctrl *ctrl = drvdata->retention_ctrl; 764 struct regmap *pmu_regs = ctrl->priv; 765 int i; 766 767 if (ctrl->refcnt && !atomic_dec_and_test(ctrl->refcnt)) 768 return; 769 770 for (i = 0; i < ctrl->nr_regs; i++) 771 regmap_write(pmu_regs, ctrl->regs[i], ctrl->value); 772 } 773 774 static struct samsung_retention_ctrl * 775 exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata, 776 const struct samsung_retention_data *data) 777 { 778 struct samsung_retention_ctrl *ctrl; 779 struct regmap *pmu_regs; 780 781 ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL); 782 if (!ctrl) 783 return ERR_PTR(-ENOMEM); 784 785 pmu_regs = exynos_get_pmu_regmap(); 786 if (IS_ERR(pmu_regs)) 787 return ERR_CAST(pmu_regs); 788 789 ctrl->priv = pmu_regs; 790 ctrl->regs = data->regs; 791 ctrl->nr_regs = data->nr_regs; 792 ctrl->value = data->value; 793 ctrl->refcnt = data->refcnt; 794 ctrl->enable = exynos_retention_enable; 795 ctrl->disable = exynos_retention_disable; 796 797 return ctrl; 798 } 799 800 /* pin banks of exynos3250 pin-controller 0 */ 801 static const struct samsung_pin_bank_data exynos3250_pin_banks0[] __initconst = { 802 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 803 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 804 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), 805 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), 806 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), 807 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14), 808 EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpd1", 0x18), 809 }; 810 811 /* pin banks of exynos3250 pin-controller 1 */ 812 static const struct samsung_pin_bank_data exynos3250_pin_banks1[] __initconst = { 813 EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpe0"), 814 EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpe1"), 815 EXYNOS_PIN_BANK_EINTN(3, 0x180, "gpe2"), 816 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08), 817 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), 818 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), 819 EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpl0", 0x18), 820 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24), 821 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28), 822 EXYNOS_PIN_BANK_EINTG(5, 0x2a0, "gpm2", 0x2c), 823 EXYNOS_PIN_BANK_EINTG(8, 0x2c0, "gpm3", 0x30), 824 EXYNOS_PIN_BANK_EINTG(8, 0x2e0, "gpm4", 0x34), 825 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00), 826 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04), 827 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08), 828 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c), 829 }; 830 831 /* 832 * PMU pad retention groups for Exynos3250 doesn't match pin banks, so handle 833 * them all together 834 */ 835 static const u32 exynos3250_retention_regs[] = { 836 S5P_PAD_RET_MAUDIO_OPTION, 837 S5P_PAD_RET_GPIO_OPTION, 838 S5P_PAD_RET_UART_OPTION, 839 S5P_PAD_RET_MMCA_OPTION, 840 S5P_PAD_RET_MMCB_OPTION, 841 S5P_PAD_RET_EBIA_OPTION, 842 S5P_PAD_RET_EBIB_OPTION, 843 S5P_PAD_RET_MMC2_OPTION, 844 S5P_PAD_RET_SPI_OPTION, 845 }; 846 847 static const struct samsung_retention_data exynos3250_retention_data __initconst = { 848 .regs = exynos3250_retention_regs, 849 .nr_regs = ARRAY_SIZE(exynos3250_retention_regs), 850 .value = EXYNOS_WAKEUP_FROM_LOWPWR, 851 .refcnt = &exynos_shared_retention_refcnt, 852 .init = exynos_retention_init, 853 }; 854 855 /* 856 * Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes 857 * two gpio/pin-mux/pinconfig controllers. 858 */ 859 const struct samsung_pin_ctrl exynos3250_pin_ctrl[] __initconst = { 860 { 861 /* pin-controller instance 0 data */ 862 .pin_banks = exynos3250_pin_banks0, 863 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks0), 864 .eint_gpio_init = exynos_eint_gpio_init, 865 .suspend = exynos_pinctrl_suspend, 866 .resume = exynos_pinctrl_resume, 867 .retention_data = &exynos3250_retention_data, 868 }, { 869 /* pin-controller instance 1 data */ 870 .pin_banks = exynos3250_pin_banks1, 871 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks1), 872 .eint_gpio_init = exynos_eint_gpio_init, 873 .eint_wkup_init = exynos_eint_wkup_init, 874 .suspend = exynos_pinctrl_suspend, 875 .resume = exynos_pinctrl_resume, 876 .retention_data = &exynos3250_retention_data, 877 }, 878 }; 879 880 /* pin banks of exynos4210 pin-controller 0 */ 881 static const struct samsung_pin_bank_data exynos4210_pin_banks0[] __initconst = { 882 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 883 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 884 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), 885 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), 886 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), 887 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14), 888 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18), 889 EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0", 0x1c), 890 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20), 891 EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2", 0x24), 892 EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3", 0x28), 893 EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4", 0x2c), 894 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30), 895 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34), 896 EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38), 897 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c), 898 }; 899 900 /* pin banks of exynos4210 pin-controller 1 */ 901 static const struct samsung_pin_bank_data exynos4210_pin_banks1[] __initconst = { 902 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00), 903 EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04), 904 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08), 905 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), 906 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), 907 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14), 908 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0", 0x18), 909 EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1", 0x1c), 910 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20), 911 EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"), 912 EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"), 913 EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"), 914 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"), 915 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"), 916 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"), 917 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"), 918 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), 919 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), 920 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), 921 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), 922 }; 923 924 /* pin banks of exynos4210 pin-controller 2 */ 925 static const struct samsung_pin_bank_data exynos4210_pin_banks2[] __initconst = { 926 EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"), 927 }; 928 929 /* PMU pad retention groups registers for Exynos4 (without audio) */ 930 static const u32 exynos4_retention_regs[] = { 931 S5P_PAD_RET_GPIO_OPTION, 932 S5P_PAD_RET_UART_OPTION, 933 S5P_PAD_RET_MMCA_OPTION, 934 S5P_PAD_RET_MMCB_OPTION, 935 S5P_PAD_RET_EBIA_OPTION, 936 S5P_PAD_RET_EBIB_OPTION, 937 }; 938 939 static const struct samsung_retention_data exynos4_retention_data __initconst = { 940 .regs = exynos4_retention_regs, 941 .nr_regs = ARRAY_SIZE(exynos4_retention_regs), 942 .value = EXYNOS_WAKEUP_FROM_LOWPWR, 943 .refcnt = &exynos_shared_retention_refcnt, 944 .init = exynos_retention_init, 945 }; 946 947 /* PMU retention control for audio pins can be tied to audio pin bank */ 948 static const u32 exynos4_audio_retention_regs[] = { 949 S5P_PAD_RET_MAUDIO_OPTION, 950 }; 951 952 static const struct samsung_retention_data exynos4_audio_retention_data __initconst = { 953 .regs = exynos4_audio_retention_regs, 954 .nr_regs = ARRAY_SIZE(exynos4_audio_retention_regs), 955 .value = EXYNOS_WAKEUP_FROM_LOWPWR, 956 .init = exynos_retention_init, 957 }; 958 959 /* 960 * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes 961 * three gpio/pin-mux/pinconfig controllers. 962 */ 963 const struct samsung_pin_ctrl exynos4210_pin_ctrl[] __initconst = { 964 { 965 /* pin-controller instance 0 data */ 966 .pin_banks = exynos4210_pin_banks0, 967 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks0), 968 .eint_gpio_init = exynos_eint_gpio_init, 969 .suspend = exynos_pinctrl_suspend, 970 .resume = exynos_pinctrl_resume, 971 .retention_data = &exynos4_retention_data, 972 }, { 973 /* pin-controller instance 1 data */ 974 .pin_banks = exynos4210_pin_banks1, 975 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks1), 976 .eint_gpio_init = exynos_eint_gpio_init, 977 .eint_wkup_init = exynos_eint_wkup_init, 978 .suspend = exynos_pinctrl_suspend, 979 .resume = exynos_pinctrl_resume, 980 .retention_data = &exynos4_retention_data, 981 }, { 982 /* pin-controller instance 2 data */ 983 .pin_banks = exynos4210_pin_banks2, 984 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks2), 985 .retention_data = &exynos4_audio_retention_data, 986 }, 987 }; 988 989 /* pin banks of exynos4x12 pin-controller 0 */ 990 static const struct samsung_pin_bank_data exynos4x12_pin_banks0[] __initconst = { 991 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 992 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 993 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), 994 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), 995 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), 996 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14), 997 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18), 998 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30), 999 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34), 1000 EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38), 1001 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c), 1002 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x40), 1003 EXYNOS_PIN_BANK_EINTG(5, 0x260, "gpj1", 0x44), 1004 }; 1005 1006 /* pin banks of exynos4x12 pin-controller 1 */ 1007 static const struct samsung_pin_bank_data exynos4x12_pin_banks1[] __initconst = { 1008 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08), 1009 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), 1010 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), 1011 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14), 1012 EXYNOS_PIN_BANK_EINTG(7, 0x0C0, "gpl0", 0x18), 1013 EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpl1", 0x1c), 1014 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20), 1015 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24), 1016 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28), 1017 EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c), 1018 EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30), 1019 EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34), 1020 EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"), 1021 EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"), 1022 EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"), 1023 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"), 1024 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"), 1025 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"), 1026 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"), 1027 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), 1028 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), 1029 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), 1030 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), 1031 }; 1032 1033 /* pin banks of exynos4x12 pin-controller 2 */ 1034 static const struct samsung_pin_bank_data exynos4x12_pin_banks2[] __initconst = { 1035 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), 1036 }; 1037 1038 /* pin banks of exynos4x12 pin-controller 3 */ 1039 static const struct samsung_pin_bank_data exynos4x12_pin_banks3[] __initconst = { 1040 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), 1041 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), 1042 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08), 1043 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv3", 0x0c), 1044 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpv4", 0x10), 1045 }; 1046 1047 /* 1048 * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes 1049 * four gpio/pin-mux/pinconfig controllers. 1050 */ 1051 const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] __initconst = { 1052 { 1053 /* pin-controller instance 0 data */ 1054 .pin_banks = exynos4x12_pin_banks0, 1055 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks0), 1056 .eint_gpio_init = exynos_eint_gpio_init, 1057 .suspend = exynos_pinctrl_suspend, 1058 .resume = exynos_pinctrl_resume, 1059 .retention_data = &exynos4_retention_data, 1060 }, { 1061 /* pin-controller instance 1 data */ 1062 .pin_banks = exynos4x12_pin_banks1, 1063 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks1), 1064 .eint_gpio_init = exynos_eint_gpio_init, 1065 .eint_wkup_init = exynos_eint_wkup_init, 1066 .suspend = exynos_pinctrl_suspend, 1067 .resume = exynos_pinctrl_resume, 1068 .retention_data = &exynos4_retention_data, 1069 }, { 1070 /* pin-controller instance 2 data */ 1071 .pin_banks = exynos4x12_pin_banks2, 1072 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks2), 1073 .eint_gpio_init = exynos_eint_gpio_init, 1074 .suspend = exynos_pinctrl_suspend, 1075 .resume = exynos_pinctrl_resume, 1076 .retention_data = &exynos4_audio_retention_data, 1077 }, { 1078 /* pin-controller instance 3 data */ 1079 .pin_banks = exynos4x12_pin_banks3, 1080 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks3), 1081 .eint_gpio_init = exynos_eint_gpio_init, 1082 .suspend = exynos_pinctrl_suspend, 1083 .resume = exynos_pinctrl_resume, 1084 }, 1085 }; 1086 1087 /* pin banks of exynos5250 pin-controller 0 */ 1088 static const struct samsung_pin_bank_data exynos5250_pin_banks0[] __initconst = { 1089 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 1090 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 1091 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), 1092 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), 1093 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10), 1094 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14), 1095 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18), 1096 EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c), 1097 EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20), 1098 EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24), 1099 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28), 1100 EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c), 1101 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30), 1102 EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34), 1103 EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"), 1104 EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"), 1105 EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"), 1106 EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"), 1107 EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"), 1108 EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"), 1109 EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"), 1110 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), 1111 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), 1112 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), 1113 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), 1114 }; 1115 1116 /* pin banks of exynos5250 pin-controller 1 */ 1117 static const struct samsung_pin_bank_data exynos5250_pin_banks1[] __initconst = { 1118 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00), 1119 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04), 1120 EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08), 1121 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c), 1122 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10), 1123 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14), 1124 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18), 1125 EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c), 1126 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20), 1127 }; 1128 1129 /* pin banks of exynos5250 pin-controller 2 */ 1130 static const struct samsung_pin_bank_data exynos5250_pin_banks2[] __initconst = { 1131 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), 1132 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), 1133 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08), 1134 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c), 1135 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10), 1136 }; 1137 1138 /* pin banks of exynos5250 pin-controller 3 */ 1139 static const struct samsung_pin_bank_data exynos5250_pin_banks3[] __initconst = { 1140 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), 1141 }; 1142 1143 /* 1144 * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes 1145 * four gpio/pin-mux/pinconfig controllers. 1146 */ 1147 const struct samsung_pin_ctrl exynos5250_pin_ctrl[] __initconst = { 1148 { 1149 /* pin-controller instance 0 data */ 1150 .pin_banks = exynos5250_pin_banks0, 1151 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks0), 1152 .eint_gpio_init = exynos_eint_gpio_init, 1153 .eint_wkup_init = exynos_eint_wkup_init, 1154 .suspend = exynos_pinctrl_suspend, 1155 .resume = exynos_pinctrl_resume, 1156 .retention_data = &exynos4_retention_data, 1157 }, { 1158 /* pin-controller instance 1 data */ 1159 .pin_banks = exynos5250_pin_banks1, 1160 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks1), 1161 .eint_gpio_init = exynos_eint_gpio_init, 1162 .suspend = exynos_pinctrl_suspend, 1163 .resume = exynos_pinctrl_resume, 1164 .retention_data = &exynos4_retention_data, 1165 }, { 1166 /* pin-controller instance 2 data */ 1167 .pin_banks = exynos5250_pin_banks2, 1168 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks2), 1169 .eint_gpio_init = exynos_eint_gpio_init, 1170 .suspend = exynos_pinctrl_suspend, 1171 .resume = exynos_pinctrl_resume, 1172 }, { 1173 /* pin-controller instance 3 data */ 1174 .pin_banks = exynos5250_pin_banks3, 1175 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks3), 1176 .eint_gpio_init = exynos_eint_gpio_init, 1177 .suspend = exynos_pinctrl_suspend, 1178 .resume = exynos_pinctrl_resume, 1179 .retention_data = &exynos4_audio_retention_data, 1180 }, 1181 }; 1182 1183 /* pin banks of exynos5260 pin-controller 0 */ 1184 static const struct samsung_pin_bank_data exynos5260_pin_banks0[] __initconst = { 1185 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00), 1186 EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04), 1187 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), 1188 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), 1189 EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10), 1190 EXYNOS_PIN_BANK_EINTG(5, 0x0a0, "gpb2", 0x14), 1191 EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpb3", 0x18), 1192 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpb4", 0x1c), 1193 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20), 1194 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24), 1195 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28), 1196 EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c), 1197 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30), 1198 EXYNOS_PIN_BANK_EINTG(5, 0x1a0, "gpe1", 0x34), 1199 EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38), 1200 EXYNOS_PIN_BANK_EINTG(8, 0x1e0, "gpf1", 0x3c), 1201 EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40), 1202 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00), 1203 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04), 1204 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08), 1205 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c), 1206 }; 1207 1208 /* pin banks of exynos5260 pin-controller 1 */ 1209 static const struct samsung_pin_bank_data exynos5260_pin_banks1[] __initconst = { 1210 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00), 1211 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04), 1212 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08), 1213 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c), 1214 EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10), 1215 }; 1216 1217 /* pin banks of exynos5260 pin-controller 2 */ 1218 static const struct samsung_pin_bank_data exynos5260_pin_banks2[] __initconst = { 1219 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), 1220 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), 1221 }; 1222 1223 /* 1224 * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes 1225 * three gpio/pin-mux/pinconfig controllers. 1226 */ 1227 const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = { 1228 { 1229 /* pin-controller instance 0 data */ 1230 .pin_banks = exynos5260_pin_banks0, 1231 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks0), 1232 .eint_gpio_init = exynos_eint_gpio_init, 1233 .eint_wkup_init = exynos_eint_wkup_init, 1234 }, { 1235 /* pin-controller instance 1 data */ 1236 .pin_banks = exynos5260_pin_banks1, 1237 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks1), 1238 .eint_gpio_init = exynos_eint_gpio_init, 1239 }, { 1240 /* pin-controller instance 2 data */ 1241 .pin_banks = exynos5260_pin_banks2, 1242 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks2), 1243 .eint_gpio_init = exynos_eint_gpio_init, 1244 }, 1245 }; 1246 1247 /* pin banks of exynos5410 pin-controller 0 */ 1248 static const struct samsung_pin_bank_data exynos5410_pin_banks0[] __initconst = { 1249 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 1250 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 1251 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), 1252 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), 1253 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10), 1254 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14), 1255 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18), 1256 EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c), 1257 EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc3", 0x20), 1258 EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc1", 0x24), 1259 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc2", 0x28), 1260 EXYNOS_PIN_BANK_EINTN(2, 0x160, "gpm5"), 1261 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x2c), 1262 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpe0", 0x30), 1263 EXYNOS_PIN_BANK_EINTG(2, 0x1C0, "gpe1", 0x34), 1264 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf0", 0x38), 1265 EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpf1", 0x3c), 1266 EXYNOS_PIN_BANK_EINTG(8, 0x220, "gpg0", 0x40), 1267 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpg1", 0x44), 1268 EXYNOS_PIN_BANK_EINTG(2, 0x260, "gpg2", 0x48), 1269 EXYNOS_PIN_BANK_EINTG(4, 0x280, "gph0", 0x4c), 1270 EXYNOS_PIN_BANK_EINTG(8, 0x2A0, "gph1", 0x50), 1271 EXYNOS_PIN_BANK_EINTN(8, 0x2C0, "gpm7"), 1272 EXYNOS_PIN_BANK_EINTN(6, 0x2E0, "gpy0"), 1273 EXYNOS_PIN_BANK_EINTN(4, 0x300, "gpy1"), 1274 EXYNOS_PIN_BANK_EINTN(6, 0x320, "gpy2"), 1275 EXYNOS_PIN_BANK_EINTN(8, 0x340, "gpy3"), 1276 EXYNOS_PIN_BANK_EINTN(8, 0x360, "gpy4"), 1277 EXYNOS_PIN_BANK_EINTN(8, 0x380, "gpy5"), 1278 EXYNOS_PIN_BANK_EINTN(8, 0x3A0, "gpy6"), 1279 EXYNOS_PIN_BANK_EINTN(8, 0x3C0, "gpy7"), 1280 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), 1281 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), 1282 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), 1283 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), 1284 }; 1285 1286 /* pin banks of exynos5410 pin-controller 1 */ 1287 static const struct samsung_pin_bank_data exynos5410_pin_banks1[] __initconst = { 1288 EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpj0", 0x00), 1289 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpj1", 0x04), 1290 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpj2", 0x08), 1291 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpj3", 0x0c), 1292 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpj4", 0x10), 1293 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpk0", 0x14), 1294 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpk1", 0x18), 1295 EXYNOS_PIN_BANK_EINTG(8, 0x0E0, "gpk2", 0x1c), 1296 EXYNOS_PIN_BANK_EINTG(7, 0x100, "gpk3", 0x20), 1297 }; 1298 1299 /* pin banks of exynos5410 pin-controller 2 */ 1300 static const struct samsung_pin_bank_data exynos5410_pin_banks2[] __initconst = { 1301 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), 1302 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), 1303 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08), 1304 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c), 1305 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10), 1306 }; 1307 1308 /* pin banks of exynos5410 pin-controller 3 */ 1309 static const struct samsung_pin_bank_data exynos5410_pin_banks3[] __initconst = { 1310 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), 1311 }; 1312 1313 /* 1314 * Samsung pinctrl driver data for Exynos5410 SoC. Exynos5410 SoC includes 1315 * four gpio/pin-mux/pinconfig controllers. 1316 */ 1317 const struct samsung_pin_ctrl exynos5410_pin_ctrl[] __initconst = { 1318 { 1319 /* pin-controller instance 0 data */ 1320 .pin_banks = exynos5410_pin_banks0, 1321 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks0), 1322 .eint_gpio_init = exynos_eint_gpio_init, 1323 .eint_wkup_init = exynos_eint_wkup_init, 1324 .suspend = exynos_pinctrl_suspend, 1325 .resume = exynos_pinctrl_resume, 1326 }, { 1327 /* pin-controller instance 1 data */ 1328 .pin_banks = exynos5410_pin_banks1, 1329 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks1), 1330 .eint_gpio_init = exynos_eint_gpio_init, 1331 .suspend = exynos_pinctrl_suspend, 1332 .resume = exynos_pinctrl_resume, 1333 }, { 1334 /* pin-controller instance 2 data */ 1335 .pin_banks = exynos5410_pin_banks2, 1336 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks2), 1337 .eint_gpio_init = exynos_eint_gpio_init, 1338 .suspend = exynos_pinctrl_suspend, 1339 .resume = exynos_pinctrl_resume, 1340 }, { 1341 /* pin-controller instance 3 data */ 1342 .pin_banks = exynos5410_pin_banks3, 1343 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks3), 1344 .eint_gpio_init = exynos_eint_gpio_init, 1345 .suspend = exynos_pinctrl_suspend, 1346 .resume = exynos_pinctrl_resume, 1347 }, 1348 }; 1349 1350 /* pin banks of exynos5420 pin-controller 0 */ 1351 static const struct samsung_pin_bank_data exynos5420_pin_banks0[] __initconst = { 1352 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00), 1353 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), 1354 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), 1355 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), 1356 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), 1357 }; 1358 1359 /* pin banks of exynos5420 pin-controller 1 */ 1360 static const struct samsung_pin_bank_data exynos5420_pin_banks1[] __initconst = { 1361 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00), 1362 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04), 1363 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08), 1364 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c), 1365 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpc4", 0x10), 1366 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpd1", 0x14), 1367 EXYNOS_PIN_BANK_EINTN(6, 0x0C0, "gpy0"), 1368 EXYNOS_PIN_BANK_EINTN(4, 0x0E0, "gpy1"), 1369 EXYNOS_PIN_BANK_EINTN(6, 0x100, "gpy2"), 1370 EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpy3"), 1371 EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpy4"), 1372 EXYNOS_PIN_BANK_EINTN(8, 0x160, "gpy5"), 1373 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy6"), 1374 }; 1375 1376 /* pin banks of exynos5420 pin-controller 2 */ 1377 static const struct samsung_pin_bank_data exynos5420_pin_banks2[] __initconst = { 1378 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00), 1379 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04), 1380 EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08), 1381 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpf1", 0x0c), 1382 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10), 1383 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14), 1384 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18), 1385 EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gpj4", 0x1c), 1386 }; 1387 1388 /* pin banks of exynos5420 pin-controller 3 */ 1389 static const struct samsung_pin_bank_data exynos5420_pin_banks3[] __initconst = { 1390 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 1391 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 1392 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), 1393 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), 1394 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10), 1395 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14), 1396 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18), 1397 EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpb4", 0x1c), 1398 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph0", 0x20), 1399 }; 1400 1401 /* pin banks of exynos5420 pin-controller 4 */ 1402 static const struct samsung_pin_bank_data exynos5420_pin_banks4[] __initconst = { 1403 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), 1404 }; 1405 1406 /* PMU pad retention groups registers for Exynos5420 (without audio) */ 1407 static const u32 exynos5420_retention_regs[] = { 1408 EXYNOS_PAD_RET_DRAM_OPTION, 1409 EXYNOS_PAD_RET_JTAG_OPTION, 1410 EXYNOS5420_PAD_RET_GPIO_OPTION, 1411 EXYNOS5420_PAD_RET_UART_OPTION, 1412 EXYNOS5420_PAD_RET_MMCA_OPTION, 1413 EXYNOS5420_PAD_RET_MMCB_OPTION, 1414 EXYNOS5420_PAD_RET_MMCC_OPTION, 1415 EXYNOS5420_PAD_RET_HSI_OPTION, 1416 EXYNOS_PAD_RET_EBIA_OPTION, 1417 EXYNOS_PAD_RET_EBIB_OPTION, 1418 EXYNOS5420_PAD_RET_SPI_OPTION, 1419 EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION, 1420 }; 1421 1422 static const struct samsung_retention_data exynos5420_retention_data __initconst = { 1423 .regs = exynos5420_retention_regs, 1424 .nr_regs = ARRAY_SIZE(exynos5420_retention_regs), 1425 .value = EXYNOS_WAKEUP_FROM_LOWPWR, 1426 .refcnt = &exynos_shared_retention_refcnt, 1427 .init = exynos_retention_init, 1428 }; 1429 1430 /* 1431 * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes 1432 * four gpio/pin-mux/pinconfig controllers. 1433 */ 1434 const struct samsung_pin_ctrl exynos5420_pin_ctrl[] __initconst = { 1435 { 1436 /* pin-controller instance 0 data */ 1437 .pin_banks = exynos5420_pin_banks0, 1438 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks0), 1439 .eint_gpio_init = exynos_eint_gpio_init, 1440 .eint_wkup_init = exynos_eint_wkup_init, 1441 .retention_data = &exynos5420_retention_data, 1442 }, { 1443 /* pin-controller instance 1 data */ 1444 .pin_banks = exynos5420_pin_banks1, 1445 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks1), 1446 .eint_gpio_init = exynos_eint_gpio_init, 1447 .retention_data = &exynos5420_retention_data, 1448 }, { 1449 /* pin-controller instance 2 data */ 1450 .pin_banks = exynos5420_pin_banks2, 1451 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks2), 1452 .eint_gpio_init = exynos_eint_gpio_init, 1453 .retention_data = &exynos5420_retention_data, 1454 }, { 1455 /* pin-controller instance 3 data */ 1456 .pin_banks = exynos5420_pin_banks3, 1457 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks3), 1458 .eint_gpio_init = exynos_eint_gpio_init, 1459 .retention_data = &exynos5420_retention_data, 1460 }, { 1461 /* pin-controller instance 4 data */ 1462 .pin_banks = exynos5420_pin_banks4, 1463 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks4), 1464 .eint_gpio_init = exynos_eint_gpio_init, 1465 .retention_data = &exynos4_audio_retention_data, 1466 }, 1467 }; 1468 1469 /* pin banks of exynos5433 pin-controller - ALIVE */ 1470 static const struct samsung_pin_bank_data exynos5433_pin_banks0[] __initconst = { 1471 EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), 1472 EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), 1473 EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), 1474 EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), 1475 EXYNOS_PIN_BANK_EINTW_EXT(8, 0x020, "gpf1", 0x1004, 1), 1476 EXYNOS_PIN_BANK_EINTW_EXT(4, 0x040, "gpf2", 0x1008, 1), 1477 EXYNOS_PIN_BANK_EINTW_EXT(4, 0x060, "gpf3", 0x100c, 1), 1478 EXYNOS_PIN_BANK_EINTW_EXT(8, 0x080, "gpf4", 0x1010, 1), 1479 EXYNOS_PIN_BANK_EINTW_EXT(8, 0x0a0, "gpf5", 0x1014, 1), 1480 }; 1481 1482 /* pin banks of exynos5433 pin-controller - AUD */ 1483 static const struct samsung_pin_bank_data exynos5433_pin_banks1[] __initconst = { 1484 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), 1485 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), 1486 }; 1487 1488 /* pin banks of exynos5433 pin-controller - CPIF */ 1489 static const struct samsung_pin_bank_data exynos5433_pin_banks2[] __initconst = { 1490 EXYNOS_PIN_BANK_EINTG(2, 0x000, "gpv6", 0x00), 1491 }; 1492 1493 /* pin banks of exynos5433 pin-controller - eSE */ 1494 static const struct samsung_pin_bank_data exynos5433_pin_banks3[] __initconst = { 1495 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj2", 0x00), 1496 }; 1497 1498 /* pin banks of exynos5433 pin-controller - FINGER */ 1499 static const struct samsung_pin_bank_data exynos5433_pin_banks4[] __initconst = { 1500 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpd5", 0x00), 1501 }; 1502 1503 /* pin banks of exynos5433 pin-controller - FSYS */ 1504 static const struct samsung_pin_bank_data exynos5433_pin_banks5[] __initconst = { 1505 EXYNOS_PIN_BANK_EINTG(6, 0x000, "gph1", 0x00), 1506 EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpr4", 0x04), 1507 EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr0", 0x08), 1508 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr1", 0x0c), 1509 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpr2", 0x10), 1510 EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpr3", 0x14), 1511 }; 1512 1513 /* pin banks of exynos5433 pin-controller - IMEM */ 1514 static const struct samsung_pin_bank_data exynos5433_pin_banks6[] __initconst = { 1515 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00), 1516 }; 1517 1518 /* pin banks of exynos5433 pin-controller - NFC */ 1519 static const struct samsung_pin_bank_data exynos5433_pin_banks7[] __initconst = { 1520 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00), 1521 }; 1522 1523 /* pin banks of exynos5433 pin-controller - PERIC */ 1524 static const struct samsung_pin_bank_data exynos5433_pin_banks8[] __initconst = { 1525 EXYNOS_PIN_BANK_EINTG(6, 0x000, "gpv7", 0x00), 1526 EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpb0", 0x04), 1527 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpc0", 0x08), 1528 EXYNOS_PIN_BANK_EINTG(2, 0x060, "gpc1", 0x0c), 1529 EXYNOS_PIN_BANK_EINTG(6, 0x080, "gpc2", 0x10), 1530 EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpc3", 0x14), 1531 EXYNOS_PIN_BANK_EINTG(2, 0x0c0, "gpg0", 0x18), 1532 EXYNOS_PIN_BANK_EINTG(4, 0x0e0, "gpd0", 0x1c), 1533 EXYNOS_PIN_BANK_EINTG(6, 0x100, "gpd1", 0x20), 1534 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd2", 0x24), 1535 EXYNOS_PIN_BANK_EINTG(5, 0x140, "gpd4", 0x28), 1536 EXYNOS_PIN_BANK_EINTG(2, 0x160, "gpd8", 0x2c), 1537 EXYNOS_PIN_BANK_EINTG(7, 0x180, "gpd6", 0x30), 1538 EXYNOS_PIN_BANK_EINTG(3, 0x1a0, "gpd7", 0x34), 1539 EXYNOS_PIN_BANK_EINTG(5, 0x1c0, "gpg1", 0x38), 1540 EXYNOS_PIN_BANK_EINTG(2, 0x1e0, "gpg2", 0x3c), 1541 EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40), 1542 }; 1543 1544 /* pin banks of exynos5433 pin-controller - TOUCH */ 1545 static const struct samsung_pin_bank_data exynos5433_pin_banks9[] __initconst = { 1546 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00), 1547 }; 1548 1549 /* 1550 * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes 1551 * ten gpio/pin-mux/pinconfig controllers. 1552 */ 1553 const struct samsung_pin_ctrl exynos5433_pin_ctrl[] __initconst = { 1554 { 1555 /* pin-controller instance 0 data */ 1556 .pin_banks = exynos5433_pin_banks0, 1557 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks0), 1558 .eint_wkup_init = exynos_eint_wkup_init, 1559 .suspend = exynos_pinctrl_suspend, 1560 .resume = exynos_pinctrl_resume, 1561 .nr_ext_resources = 1, 1562 }, { 1563 /* pin-controller instance 1 data */ 1564 .pin_banks = exynos5433_pin_banks1, 1565 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks1), 1566 .eint_gpio_init = exynos_eint_gpio_init, 1567 .suspend = exynos_pinctrl_suspend, 1568 .resume = exynos_pinctrl_resume, 1569 }, { 1570 /* pin-controller instance 2 data */ 1571 .pin_banks = exynos5433_pin_banks2, 1572 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks2), 1573 .eint_gpio_init = exynos_eint_gpio_init, 1574 .suspend = exynos_pinctrl_suspend, 1575 .resume = exynos_pinctrl_resume, 1576 }, { 1577 /* pin-controller instance 3 data */ 1578 .pin_banks = exynos5433_pin_banks3, 1579 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks3), 1580 .eint_gpio_init = exynos_eint_gpio_init, 1581 .suspend = exynos_pinctrl_suspend, 1582 .resume = exynos_pinctrl_resume, 1583 }, { 1584 /* pin-controller instance 4 data */ 1585 .pin_banks = exynos5433_pin_banks4, 1586 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks4), 1587 .eint_gpio_init = exynos_eint_gpio_init, 1588 .suspend = exynos_pinctrl_suspend, 1589 .resume = exynos_pinctrl_resume, 1590 }, { 1591 /* pin-controller instance 5 data */ 1592 .pin_banks = exynos5433_pin_banks5, 1593 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks5), 1594 .eint_gpio_init = exynos_eint_gpio_init, 1595 .suspend = exynos_pinctrl_suspend, 1596 .resume = exynos_pinctrl_resume, 1597 }, { 1598 /* pin-controller instance 6 data */ 1599 .pin_banks = exynos5433_pin_banks6, 1600 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks6), 1601 .eint_gpio_init = exynos_eint_gpio_init, 1602 .suspend = exynos_pinctrl_suspend, 1603 .resume = exynos_pinctrl_resume, 1604 }, { 1605 /* pin-controller instance 7 data */ 1606 .pin_banks = exynos5433_pin_banks7, 1607 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks7), 1608 .eint_gpio_init = exynos_eint_gpio_init, 1609 .suspend = exynos_pinctrl_suspend, 1610 .resume = exynos_pinctrl_resume, 1611 }, { 1612 /* pin-controller instance 8 data */ 1613 .pin_banks = exynos5433_pin_banks8, 1614 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks8), 1615 .eint_gpio_init = exynos_eint_gpio_init, 1616 .suspend = exynos_pinctrl_suspend, 1617 .resume = exynos_pinctrl_resume, 1618 }, { 1619 /* pin-controller instance 9 data */ 1620 .pin_banks = exynos5433_pin_banks9, 1621 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks9), 1622 .eint_gpio_init = exynos_eint_gpio_init, 1623 .suspend = exynos_pinctrl_suspend, 1624 .resume = exynos_pinctrl_resume, 1625 }, 1626 }; 1627 1628 /* pin banks of exynos7 pin-controller - ALIVE */ 1629 static const struct samsung_pin_bank_data exynos7_pin_banks0[] __initconst = { 1630 EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), 1631 EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), 1632 EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), 1633 EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), 1634 }; 1635 1636 /* pin banks of exynos7 pin-controller - BUS0 */ 1637 static const struct samsung_pin_bank_data exynos7_pin_banks1[] __initconst = { 1638 EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), 1639 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc0", 0x04), 1640 EXYNOS_PIN_BANK_EINTG(2, 0x040, "gpc1", 0x08), 1641 EXYNOS_PIN_BANK_EINTG(6, 0x060, "gpc2", 0x0c), 1642 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10), 1643 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14), 1644 EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18), 1645 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpd2", 0x1c), 1646 EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpd4", 0x20), 1647 EXYNOS_PIN_BANK_EINTG(4, 0x120, "gpd5", 0x24), 1648 EXYNOS_PIN_BANK_EINTG(6, 0x140, "gpd6", 0x28), 1649 EXYNOS_PIN_BANK_EINTG(3, 0x160, "gpd7", 0x2c), 1650 EXYNOS_PIN_BANK_EINTG(2, 0x180, "gpd8", 0x30), 1651 EXYNOS_PIN_BANK_EINTG(2, 0x1a0, "gpg0", 0x34), 1652 EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpg3", 0x38), 1653 }; 1654 1655 /* pin banks of exynos7 pin-controller - NFC */ 1656 static const struct samsung_pin_bank_data exynos7_pin_banks2[] __initconst = { 1657 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00), 1658 }; 1659 1660 /* pin banks of exynos7 pin-controller - TOUCH */ 1661 static const struct samsung_pin_bank_data exynos7_pin_banks3[] __initconst = { 1662 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00), 1663 }; 1664 1665 /* pin banks of exynos7 pin-controller - FF */ 1666 static const struct samsung_pin_bank_data exynos7_pin_banks4[] __initconst = { 1667 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpg4", 0x00), 1668 }; 1669 1670 /* pin banks of exynos7 pin-controller - ESE */ 1671 static const struct samsung_pin_bank_data exynos7_pin_banks5[] __initconst = { 1672 EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpv7", 0x00), 1673 }; 1674 1675 /* pin banks of exynos7 pin-controller - FSYS0 */ 1676 static const struct samsung_pin_bank_data exynos7_pin_banks6[] __initconst = { 1677 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpr4", 0x00), 1678 }; 1679 1680 /* pin banks of exynos7 pin-controller - FSYS1 */ 1681 static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = { 1682 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpr0", 0x00), 1683 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpr1", 0x04), 1684 EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr2", 0x08), 1685 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c), 1686 }; 1687 1688 /* pin banks of exynos7 pin-controller - BUS1 */ 1689 static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = { 1690 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00), 1691 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpf1", 0x04), 1692 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf2", 0x08), 1693 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpf3", 0x0c), 1694 EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpf4", 0x10), 1695 EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf5", 0x14), 1696 EXYNOS_PIN_BANK_EINTG(5, 0x0e0, "gpg1", 0x18), 1697 EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpg2", 0x1c), 1698 EXYNOS_PIN_BANK_EINTG(6, 0x120, "gph1", 0x20), 1699 EXYNOS_PIN_BANK_EINTG(3, 0x140, "gpv6", 0x24), 1700 }; 1701 1702 static const struct samsung_pin_bank_data exynos7_pin_banks9[] __initconst = { 1703 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), 1704 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), 1705 }; 1706 1707 const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = { 1708 { 1709 /* pin-controller instance 0 Alive data */ 1710 .pin_banks = exynos7_pin_banks0, 1711 .nr_banks = ARRAY_SIZE(exynos7_pin_banks0), 1712 .eint_wkup_init = exynos_eint_wkup_init, 1713 }, { 1714 /* pin-controller instance 1 BUS0 data */ 1715 .pin_banks = exynos7_pin_banks1, 1716 .nr_banks = ARRAY_SIZE(exynos7_pin_banks1), 1717 .eint_gpio_init = exynos_eint_gpio_init, 1718 }, { 1719 /* pin-controller instance 2 NFC data */ 1720 .pin_banks = exynos7_pin_banks2, 1721 .nr_banks = ARRAY_SIZE(exynos7_pin_banks2), 1722 .eint_gpio_init = exynos_eint_gpio_init, 1723 }, { 1724 /* pin-controller instance 3 TOUCH data */ 1725 .pin_banks = exynos7_pin_banks3, 1726 .nr_banks = ARRAY_SIZE(exynos7_pin_banks3), 1727 .eint_gpio_init = exynos_eint_gpio_init, 1728 }, { 1729 /* pin-controller instance 4 FF data */ 1730 .pin_banks = exynos7_pin_banks4, 1731 .nr_banks = ARRAY_SIZE(exynos7_pin_banks4), 1732 .eint_gpio_init = exynos_eint_gpio_init, 1733 }, { 1734 /* pin-controller instance 5 ESE data */ 1735 .pin_banks = exynos7_pin_banks5, 1736 .nr_banks = ARRAY_SIZE(exynos7_pin_banks5), 1737 .eint_gpio_init = exynos_eint_gpio_init, 1738 }, { 1739 /* pin-controller instance 6 FSYS0 data */ 1740 .pin_banks = exynos7_pin_banks6, 1741 .nr_banks = ARRAY_SIZE(exynos7_pin_banks6), 1742 .eint_gpio_init = exynos_eint_gpio_init, 1743 }, { 1744 /* pin-controller instance 7 FSYS1 data */ 1745 .pin_banks = exynos7_pin_banks7, 1746 .nr_banks = ARRAY_SIZE(exynos7_pin_banks7), 1747 .eint_gpio_init = exynos_eint_gpio_init, 1748 }, { 1749 /* pin-controller instance 8 BUS1 data */ 1750 .pin_banks = exynos7_pin_banks8, 1751 .nr_banks = ARRAY_SIZE(exynos7_pin_banks8), 1752 .eint_gpio_init = exynos_eint_gpio_init, 1753 }, { 1754 /* pin-controller instance 9 AUD data */ 1755 .pin_banks = exynos7_pin_banks9, 1756 .nr_banks = ARRAY_SIZE(exynos7_pin_banks9), 1757 .eint_gpio_init = exynos_eint_gpio_init, 1758 }, 1759 }; 1760