1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Exynos ARMv8 specific support for Samsung pinctrl/gpiolib driver 4 // with eint support. 5 // 6 // Copyright (c) 2012 Samsung Electronics Co., Ltd. 7 // http://www.samsung.com 8 // Copyright (c) 2012 Linaro Ltd 9 // http://www.linaro.org 10 // Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org> 11 // 12 // This file contains the Samsung Exynos specific information required by the 13 // the Samsung pinctrl/gpiolib driver. It also includes the implementation of 14 // external gpio and wakeup interrupt support. 15 16 #include <linux/slab.h> 17 #include <linux/soc/samsung/exynos-regs-pmu.h> 18 19 #include "pinctrl-samsung.h" 20 #include "pinctrl-exynos.h" 21 22 static const struct samsung_pin_bank_type bank_type_off = { 23 .fld_width = { 4, 1, 2, 2, 2, 2, }, 24 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, 25 }; 26 27 static const struct samsung_pin_bank_type bank_type_alive = { 28 .fld_width = { 4, 1, 2, 2, }, 29 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, 30 }; 31 32 /* Exynos5433 has the 4bit widths for PINCFG_TYPE_DRV bitfields. */ 33 static const struct samsung_pin_bank_type exynos5433_bank_type_off = { 34 .fld_width = { 4, 1, 2, 4, 2, 2, }, 35 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, 36 }; 37 38 static const struct samsung_pin_bank_type exynos5433_bank_type_alive = { 39 .fld_width = { 4, 1, 2, 4, }, 40 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, 41 }; 42 43 /* Pad retention control code for accessing PMU regmap */ 44 static atomic_t exynos_shared_retention_refcnt; 45 46 /* pin banks of exynos5433 pin-controller - ALIVE */ 47 static const struct samsung_pin_bank_data exynos5433_pin_banks0[] __initconst = { 48 EXYNOS5433_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), 49 EXYNOS5433_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), 50 EXYNOS5433_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), 51 EXYNOS5433_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), 52 EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x020, "gpf1", 0x1004, 1), 53 EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x040, "gpf2", 0x1008, 1), 54 EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x060, "gpf3", 0x100c, 1), 55 EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x080, "gpf4", 0x1010, 1), 56 EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x0a0, "gpf5", 0x1014, 1), 57 }; 58 59 /* pin banks of exynos5433 pin-controller - AUD */ 60 static const struct samsung_pin_bank_data exynos5433_pin_banks1[] __initconst = { 61 EXYNOS5433_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), 62 EXYNOS5433_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), 63 }; 64 65 /* pin banks of exynos5433 pin-controller - CPIF */ 66 static const struct samsung_pin_bank_data exynos5433_pin_banks2[] __initconst = { 67 EXYNOS5433_PIN_BANK_EINTG(2, 0x000, "gpv6", 0x00), 68 }; 69 70 /* pin banks of exynos5433 pin-controller - eSE */ 71 static const struct samsung_pin_bank_data exynos5433_pin_banks3[] __initconst = { 72 EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj2", 0x00), 73 }; 74 75 /* pin banks of exynos5433 pin-controller - FINGER */ 76 static const struct samsung_pin_bank_data exynos5433_pin_banks4[] __initconst = { 77 EXYNOS5433_PIN_BANK_EINTG(4, 0x000, "gpd5", 0x00), 78 }; 79 80 /* pin banks of exynos5433 pin-controller - FSYS */ 81 static const struct samsung_pin_bank_data exynos5433_pin_banks5[] __initconst = { 82 EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gph1", 0x00), 83 EXYNOS5433_PIN_BANK_EINTG(7, 0x020, "gpr4", 0x04), 84 EXYNOS5433_PIN_BANK_EINTG(5, 0x040, "gpr0", 0x08), 85 EXYNOS5433_PIN_BANK_EINTG(8, 0x060, "gpr1", 0x0c), 86 EXYNOS5433_PIN_BANK_EINTG(2, 0x080, "gpr2", 0x10), 87 EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpr3", 0x14), 88 }; 89 90 /* pin banks of exynos5433 pin-controller - IMEM */ 91 static const struct samsung_pin_bank_data exynos5433_pin_banks6[] __initconst = { 92 EXYNOS5433_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00), 93 }; 94 95 /* pin banks of exynos5433 pin-controller - NFC */ 96 static const struct samsung_pin_bank_data exynos5433_pin_banks7[] __initconst = { 97 EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00), 98 }; 99 100 /* pin banks of exynos5433 pin-controller - PERIC */ 101 static const struct samsung_pin_bank_data exynos5433_pin_banks8[] __initconst = { 102 EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gpv7", 0x00), 103 EXYNOS5433_PIN_BANK_EINTG(5, 0x020, "gpb0", 0x04), 104 EXYNOS5433_PIN_BANK_EINTG(8, 0x040, "gpc0", 0x08), 105 EXYNOS5433_PIN_BANK_EINTG(2, 0x060, "gpc1", 0x0c), 106 EXYNOS5433_PIN_BANK_EINTG(6, 0x080, "gpc2", 0x10), 107 EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpc3", 0x14), 108 EXYNOS5433_PIN_BANK_EINTG(2, 0x0c0, "gpg0", 0x18), 109 EXYNOS5433_PIN_BANK_EINTG(4, 0x0e0, "gpd0", 0x1c), 110 EXYNOS5433_PIN_BANK_EINTG(6, 0x100, "gpd1", 0x20), 111 EXYNOS5433_PIN_BANK_EINTG(8, 0x120, "gpd2", 0x24), 112 EXYNOS5433_PIN_BANK_EINTG(5, 0x140, "gpd4", 0x28), 113 EXYNOS5433_PIN_BANK_EINTG(2, 0x160, "gpd8", 0x2c), 114 EXYNOS5433_PIN_BANK_EINTG(7, 0x180, "gpd6", 0x30), 115 EXYNOS5433_PIN_BANK_EINTG(3, 0x1a0, "gpd7", 0x34), 116 EXYNOS5433_PIN_BANK_EINTG(5, 0x1c0, "gpg1", 0x38), 117 EXYNOS5433_PIN_BANK_EINTG(2, 0x1e0, "gpg2", 0x3c), 118 EXYNOS5433_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40), 119 }; 120 121 /* pin banks of exynos5433 pin-controller - TOUCH */ 122 static const struct samsung_pin_bank_data exynos5433_pin_banks9[] __initconst = { 123 EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00), 124 }; 125 126 /* PMU pin retention groups registers for Exynos5433 (without audio & fsys) */ 127 static const u32 exynos5433_retention_regs[] = { 128 EXYNOS5433_PAD_RETENTION_TOP_OPTION, 129 EXYNOS5433_PAD_RETENTION_UART_OPTION, 130 EXYNOS5433_PAD_RETENTION_EBIA_OPTION, 131 EXYNOS5433_PAD_RETENTION_EBIB_OPTION, 132 EXYNOS5433_PAD_RETENTION_SPI_OPTION, 133 EXYNOS5433_PAD_RETENTION_MIF_OPTION, 134 EXYNOS5433_PAD_RETENTION_USBXTI_OPTION, 135 EXYNOS5433_PAD_RETENTION_BOOTLDO_OPTION, 136 EXYNOS5433_PAD_RETENTION_UFS_OPTION, 137 EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION, 138 }; 139 140 static const struct samsung_retention_data exynos5433_retention_data __initconst = { 141 .regs = exynos5433_retention_regs, 142 .nr_regs = ARRAY_SIZE(exynos5433_retention_regs), 143 .value = EXYNOS_WAKEUP_FROM_LOWPWR, 144 .refcnt = &exynos_shared_retention_refcnt, 145 .init = exynos_retention_init, 146 }; 147 148 /* PMU retention control for audio pins can be tied to audio pin bank */ 149 static const u32 exynos5433_audio_retention_regs[] = { 150 EXYNOS5433_PAD_RETENTION_AUD_OPTION, 151 }; 152 153 static const struct samsung_retention_data exynos5433_audio_retention_data __initconst = { 154 .regs = exynos5433_audio_retention_regs, 155 .nr_regs = ARRAY_SIZE(exynos5433_audio_retention_regs), 156 .value = EXYNOS_WAKEUP_FROM_LOWPWR, 157 .init = exynos_retention_init, 158 }; 159 160 /* PMU retention control for mmc pins can be tied to fsys pin bank */ 161 static const u32 exynos5433_fsys_retention_regs[] = { 162 EXYNOS5433_PAD_RETENTION_MMC0_OPTION, 163 EXYNOS5433_PAD_RETENTION_MMC1_OPTION, 164 EXYNOS5433_PAD_RETENTION_MMC2_OPTION, 165 }; 166 167 static const struct samsung_retention_data exynos5433_fsys_retention_data __initconst = { 168 .regs = exynos5433_fsys_retention_regs, 169 .nr_regs = ARRAY_SIZE(exynos5433_fsys_retention_regs), 170 .value = EXYNOS_WAKEUP_FROM_LOWPWR, 171 .init = exynos_retention_init, 172 }; 173 174 /* 175 * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes 176 * ten gpio/pin-mux/pinconfig controllers. 177 */ 178 static const struct samsung_pin_ctrl exynos5433_pin_ctrl[] __initconst = { 179 { 180 /* pin-controller instance 0 data */ 181 .pin_banks = exynos5433_pin_banks0, 182 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks0), 183 .eint_wkup_init = exynos_eint_wkup_init, 184 .suspend = exynos_pinctrl_suspend, 185 .resume = exynos_pinctrl_resume, 186 .nr_ext_resources = 1, 187 .retention_data = &exynos5433_retention_data, 188 }, { 189 /* pin-controller instance 1 data */ 190 .pin_banks = exynos5433_pin_banks1, 191 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks1), 192 .eint_gpio_init = exynos_eint_gpio_init, 193 .suspend = exynos_pinctrl_suspend, 194 .resume = exynos_pinctrl_resume, 195 .retention_data = &exynos5433_audio_retention_data, 196 }, { 197 /* pin-controller instance 2 data */ 198 .pin_banks = exynos5433_pin_banks2, 199 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks2), 200 .eint_gpio_init = exynos_eint_gpio_init, 201 .suspend = exynos_pinctrl_suspend, 202 .resume = exynos_pinctrl_resume, 203 .retention_data = &exynos5433_retention_data, 204 }, { 205 /* pin-controller instance 3 data */ 206 .pin_banks = exynos5433_pin_banks3, 207 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks3), 208 .eint_gpio_init = exynos_eint_gpio_init, 209 .suspend = exynos_pinctrl_suspend, 210 .resume = exynos_pinctrl_resume, 211 .retention_data = &exynos5433_retention_data, 212 }, { 213 /* pin-controller instance 4 data */ 214 .pin_banks = exynos5433_pin_banks4, 215 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks4), 216 .eint_gpio_init = exynos_eint_gpio_init, 217 .suspend = exynos_pinctrl_suspend, 218 .resume = exynos_pinctrl_resume, 219 .retention_data = &exynos5433_retention_data, 220 }, { 221 /* pin-controller instance 5 data */ 222 .pin_banks = exynos5433_pin_banks5, 223 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks5), 224 .eint_gpio_init = exynos_eint_gpio_init, 225 .suspend = exynos_pinctrl_suspend, 226 .resume = exynos_pinctrl_resume, 227 .retention_data = &exynos5433_fsys_retention_data, 228 }, { 229 /* pin-controller instance 6 data */ 230 .pin_banks = exynos5433_pin_banks6, 231 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks6), 232 .eint_gpio_init = exynos_eint_gpio_init, 233 .suspend = exynos_pinctrl_suspend, 234 .resume = exynos_pinctrl_resume, 235 .retention_data = &exynos5433_retention_data, 236 }, { 237 /* pin-controller instance 7 data */ 238 .pin_banks = exynos5433_pin_banks7, 239 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks7), 240 .eint_gpio_init = exynos_eint_gpio_init, 241 .suspend = exynos_pinctrl_suspend, 242 .resume = exynos_pinctrl_resume, 243 .retention_data = &exynos5433_retention_data, 244 }, { 245 /* pin-controller instance 8 data */ 246 .pin_banks = exynos5433_pin_banks8, 247 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks8), 248 .eint_gpio_init = exynos_eint_gpio_init, 249 .suspend = exynos_pinctrl_suspend, 250 .resume = exynos_pinctrl_resume, 251 .retention_data = &exynos5433_retention_data, 252 }, { 253 /* pin-controller instance 9 data */ 254 .pin_banks = exynos5433_pin_banks9, 255 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks9), 256 .eint_gpio_init = exynos_eint_gpio_init, 257 .suspend = exynos_pinctrl_suspend, 258 .resume = exynos_pinctrl_resume, 259 .retention_data = &exynos5433_retention_data, 260 }, 261 }; 262 263 const struct samsung_pinctrl_of_match_data exynos5433_of_data __initconst = { 264 .ctrl = exynos5433_pin_ctrl, 265 .num_ctrl = ARRAY_SIZE(exynos5433_pin_ctrl), 266 }; 267 268 /* pin banks of exynos7 pin-controller - ALIVE */ 269 static const struct samsung_pin_bank_data exynos7_pin_banks0[] __initconst = { 270 EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), 271 EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), 272 EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), 273 EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), 274 }; 275 276 /* pin banks of exynos7 pin-controller - BUS0 */ 277 static const struct samsung_pin_bank_data exynos7_pin_banks1[] __initconst = { 278 EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), 279 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc0", 0x04), 280 EXYNOS_PIN_BANK_EINTG(2, 0x040, "gpc1", 0x08), 281 EXYNOS_PIN_BANK_EINTG(6, 0x060, "gpc2", 0x0c), 282 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10), 283 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14), 284 EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18), 285 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpd2", 0x1c), 286 EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpd4", 0x20), 287 EXYNOS_PIN_BANK_EINTG(4, 0x120, "gpd5", 0x24), 288 EXYNOS_PIN_BANK_EINTG(6, 0x140, "gpd6", 0x28), 289 EXYNOS_PIN_BANK_EINTG(3, 0x160, "gpd7", 0x2c), 290 EXYNOS_PIN_BANK_EINTG(2, 0x180, "gpd8", 0x30), 291 EXYNOS_PIN_BANK_EINTG(2, 0x1a0, "gpg0", 0x34), 292 EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpg3", 0x38), 293 }; 294 295 /* pin banks of exynos7 pin-controller - NFC */ 296 static const struct samsung_pin_bank_data exynos7_pin_banks2[] __initconst = { 297 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00), 298 }; 299 300 /* pin banks of exynos7 pin-controller - TOUCH */ 301 static const struct samsung_pin_bank_data exynos7_pin_banks3[] __initconst = { 302 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00), 303 }; 304 305 /* pin banks of exynos7 pin-controller - FF */ 306 static const struct samsung_pin_bank_data exynos7_pin_banks4[] __initconst = { 307 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpg4", 0x00), 308 }; 309 310 /* pin banks of exynos7 pin-controller - ESE */ 311 static const struct samsung_pin_bank_data exynos7_pin_banks5[] __initconst = { 312 EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpv7", 0x00), 313 }; 314 315 /* pin banks of exynos7 pin-controller - FSYS0 */ 316 static const struct samsung_pin_bank_data exynos7_pin_banks6[] __initconst = { 317 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpr4", 0x00), 318 }; 319 320 /* pin banks of exynos7 pin-controller - FSYS1 */ 321 static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = { 322 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpr0", 0x00), 323 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpr1", 0x04), 324 EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr2", 0x08), 325 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c), 326 }; 327 328 /* pin banks of exynos7 pin-controller - BUS1 */ 329 static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = { 330 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00), 331 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpf1", 0x04), 332 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf2", 0x08), 333 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpf3", 0x0c), 334 EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpf4", 0x10), 335 EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf5", 0x14), 336 EXYNOS_PIN_BANK_EINTG(5, 0x0e0, "gpg1", 0x18), 337 EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpg2", 0x1c), 338 EXYNOS_PIN_BANK_EINTG(6, 0x120, "gph1", 0x20), 339 EXYNOS_PIN_BANK_EINTG(3, 0x140, "gpv6", 0x24), 340 }; 341 342 static const struct samsung_pin_bank_data exynos7_pin_banks9[] __initconst = { 343 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), 344 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), 345 }; 346 347 static const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = { 348 { 349 /* pin-controller instance 0 Alive data */ 350 .pin_banks = exynos7_pin_banks0, 351 .nr_banks = ARRAY_SIZE(exynos7_pin_banks0), 352 .eint_wkup_init = exynos_eint_wkup_init, 353 }, { 354 /* pin-controller instance 1 BUS0 data */ 355 .pin_banks = exynos7_pin_banks1, 356 .nr_banks = ARRAY_SIZE(exynos7_pin_banks1), 357 .eint_gpio_init = exynos_eint_gpio_init, 358 }, { 359 /* pin-controller instance 2 NFC data */ 360 .pin_banks = exynos7_pin_banks2, 361 .nr_banks = ARRAY_SIZE(exynos7_pin_banks2), 362 .eint_gpio_init = exynos_eint_gpio_init, 363 }, { 364 /* pin-controller instance 3 TOUCH data */ 365 .pin_banks = exynos7_pin_banks3, 366 .nr_banks = ARRAY_SIZE(exynos7_pin_banks3), 367 .eint_gpio_init = exynos_eint_gpio_init, 368 }, { 369 /* pin-controller instance 4 FF data */ 370 .pin_banks = exynos7_pin_banks4, 371 .nr_banks = ARRAY_SIZE(exynos7_pin_banks4), 372 .eint_gpio_init = exynos_eint_gpio_init, 373 }, { 374 /* pin-controller instance 5 ESE data */ 375 .pin_banks = exynos7_pin_banks5, 376 .nr_banks = ARRAY_SIZE(exynos7_pin_banks5), 377 .eint_gpio_init = exynos_eint_gpio_init, 378 }, { 379 /* pin-controller instance 6 FSYS0 data */ 380 .pin_banks = exynos7_pin_banks6, 381 .nr_banks = ARRAY_SIZE(exynos7_pin_banks6), 382 .eint_gpio_init = exynos_eint_gpio_init, 383 }, { 384 /* pin-controller instance 7 FSYS1 data */ 385 .pin_banks = exynos7_pin_banks7, 386 .nr_banks = ARRAY_SIZE(exynos7_pin_banks7), 387 .eint_gpio_init = exynos_eint_gpio_init, 388 }, { 389 /* pin-controller instance 8 BUS1 data */ 390 .pin_banks = exynos7_pin_banks8, 391 .nr_banks = ARRAY_SIZE(exynos7_pin_banks8), 392 .eint_gpio_init = exynos_eint_gpio_init, 393 }, { 394 /* pin-controller instance 9 AUD data */ 395 .pin_banks = exynos7_pin_banks9, 396 .nr_banks = ARRAY_SIZE(exynos7_pin_banks9), 397 .eint_gpio_init = exynos_eint_gpio_init, 398 }, 399 }; 400 401 const struct samsung_pinctrl_of_match_data exynos7_of_data __initconst = { 402 .ctrl = exynos7_pin_ctrl, 403 .num_ctrl = ARRAY_SIZE(exynos7_pin_ctrl), 404 }; 405