1 /* 2 * Exynos specific support for Samsung pinctrl/gpiolib driver with eint support. 3 * 4 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 5 * http://www.samsung.com 6 * Copyright (c) 2012 Linaro Ltd 7 * http://www.linaro.org 8 * 9 * Author: Thomas Abraham <thomas.ab@samsung.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * This file contains the Samsung Exynos specific information required by the 17 * the Samsung pinctrl/gpiolib driver. It also includes the implementation of 18 * external gpio and wakeup interrupt support. 19 */ 20 21 #include <linux/device.h> 22 #include <linux/of_address.h> 23 #include <linux/slab.h> 24 #include <linux/err.h> 25 #include <linux/soc/samsung/exynos-regs-pmu.h> 26 27 #include "pinctrl-samsung.h" 28 #include "pinctrl-exynos.h" 29 30 static const struct samsung_pin_bank_type bank_type_off = { 31 .fld_width = { 4, 1, 2, 2, 2, 2, }, 32 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, 33 }; 34 35 static const struct samsung_pin_bank_type bank_type_alive = { 36 .fld_width = { 4, 1, 2, 2, }, 37 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, 38 }; 39 40 /* Retention control for S5PV210 are located at the end of clock controller */ 41 #define S5P_OTHERS 0xE000 42 43 #define S5P_OTHERS_RET_IO (1 << 31) 44 #define S5P_OTHERS_RET_CF (1 << 30) 45 #define S5P_OTHERS_RET_MMC (1 << 29) 46 #define S5P_OTHERS_RET_UART (1 << 28) 47 48 static void s5pv210_retention_disable(struct samsung_pinctrl_drv_data *drvdata) 49 { 50 void __iomem *clk_base = (void __iomem *)drvdata->retention_ctrl->priv; 51 u32 tmp; 52 53 tmp = __raw_readl(clk_base + S5P_OTHERS); 54 tmp |= (S5P_OTHERS_RET_IO | S5P_OTHERS_RET_CF | S5P_OTHERS_RET_MMC | 55 S5P_OTHERS_RET_UART); 56 __raw_writel(tmp, clk_base + S5P_OTHERS); 57 } 58 59 static struct samsung_retention_ctrl * 60 s5pv210_retention_init(struct samsung_pinctrl_drv_data *drvdata, 61 const struct samsung_retention_data *data) 62 { 63 struct samsung_retention_ctrl *ctrl; 64 struct device_node *np; 65 void __iomem *clk_base; 66 67 ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL); 68 if (!ctrl) 69 return ERR_PTR(-ENOMEM); 70 71 np = of_find_compatible_node(NULL, NULL, "samsung,s5pv210-clock"); 72 if (!np) { 73 pr_err("%s: failed to find clock controller DT node\n", 74 __func__); 75 return ERR_PTR(-ENODEV); 76 } 77 78 clk_base = of_iomap(np, 0); 79 if (!clk_base) { 80 pr_err("%s: failed to map clock registers\n", __func__); 81 return ERR_PTR(-EINVAL); 82 } 83 84 ctrl->priv = (void __force *)clk_base; 85 ctrl->disable = s5pv210_retention_disable; 86 87 return ctrl; 88 } 89 90 static const struct samsung_retention_data s5pv210_retention_data __initconst = { 91 .init = s5pv210_retention_init, 92 }; 93 94 /* pin banks of s5pv210 pin-controller */ 95 static const struct samsung_pin_bank_data s5pv210_pin_bank[] __initconst = { 96 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 97 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04), 98 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), 99 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), 100 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), 101 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14), 102 EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18), 103 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe0", 0x1c), 104 EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpe1", 0x20), 105 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpf0", 0x24), 106 EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpf1", 0x28), 107 EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpf2", 0x2c), 108 EXYNOS_PIN_BANK_EINTG(6, 0x180, "gpf3", 0x30), 109 EXYNOS_PIN_BANK_EINTG(7, 0x1a0, "gpg0", 0x34), 110 EXYNOS_PIN_BANK_EINTG(7, 0x1c0, "gpg1", 0x38), 111 EXYNOS_PIN_BANK_EINTG(7, 0x1e0, "gpg2", 0x3c), 112 EXYNOS_PIN_BANK_EINTG(7, 0x200, "gpg3", 0x40), 113 EXYNOS_PIN_BANK_EINTN(7, 0x220, "gpi"), 114 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x44), 115 EXYNOS_PIN_BANK_EINTG(6, 0x260, "gpj1", 0x48), 116 EXYNOS_PIN_BANK_EINTG(8, 0x280, "gpj2", 0x4c), 117 EXYNOS_PIN_BANK_EINTG(8, 0x2a0, "gpj3", 0x50), 118 EXYNOS_PIN_BANK_EINTG(5, 0x2c0, "gpj4", 0x54), 119 EXYNOS_PIN_BANK_EINTN(8, 0x2e0, "mp01"), 120 EXYNOS_PIN_BANK_EINTN(4, 0x300, "mp02"), 121 EXYNOS_PIN_BANK_EINTN(8, 0x320, "mp03"), 122 EXYNOS_PIN_BANK_EINTN(8, 0x340, "mp04"), 123 EXYNOS_PIN_BANK_EINTN(8, 0x360, "mp05"), 124 EXYNOS_PIN_BANK_EINTN(8, 0x380, "mp06"), 125 EXYNOS_PIN_BANK_EINTN(8, 0x3a0, "mp07"), 126 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gph0", 0x00), 127 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gph1", 0x04), 128 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gph2", 0x08), 129 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gph3", 0x0c), 130 }; 131 132 const struct samsung_pin_ctrl s5pv210_pin_ctrl[] __initconst = { 133 { 134 /* pin-controller instance 0 data */ 135 .pin_banks = s5pv210_pin_bank, 136 .nr_banks = ARRAY_SIZE(s5pv210_pin_bank), 137 .eint_gpio_init = exynos_eint_gpio_init, 138 .eint_wkup_init = exynos_eint_wkup_init, 139 .suspend = exynos_pinctrl_suspend, 140 .resume = exynos_pinctrl_resume, 141 .retention_data = &s5pv210_retention_data, 142 }, 143 }; 144 145 /* Pad retention control code for accessing PMU regmap */ 146 static atomic_t exynos_shared_retention_refcnt; 147 148 /* pin banks of exynos3250 pin-controller 0 */ 149 static const struct samsung_pin_bank_data exynos3250_pin_banks0[] __initconst = { 150 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 151 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 152 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), 153 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), 154 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), 155 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14), 156 EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpd1", 0x18), 157 }; 158 159 /* pin banks of exynos3250 pin-controller 1 */ 160 static const struct samsung_pin_bank_data exynos3250_pin_banks1[] __initconst = { 161 EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpe0"), 162 EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpe1"), 163 EXYNOS_PIN_BANK_EINTN(3, 0x180, "gpe2"), 164 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08), 165 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), 166 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), 167 EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpl0", 0x18), 168 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24), 169 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28), 170 EXYNOS_PIN_BANK_EINTG(5, 0x2a0, "gpm2", 0x2c), 171 EXYNOS_PIN_BANK_EINTG(8, 0x2c0, "gpm3", 0x30), 172 EXYNOS_PIN_BANK_EINTG(8, 0x2e0, "gpm4", 0x34), 173 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00), 174 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04), 175 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08), 176 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c), 177 }; 178 179 /* 180 * PMU pad retention groups for Exynos3250 doesn't match pin banks, so handle 181 * them all together 182 */ 183 static const u32 exynos3250_retention_regs[] = { 184 S5P_PAD_RET_MAUDIO_OPTION, 185 S5P_PAD_RET_GPIO_OPTION, 186 S5P_PAD_RET_UART_OPTION, 187 S5P_PAD_RET_MMCA_OPTION, 188 S5P_PAD_RET_MMCB_OPTION, 189 S5P_PAD_RET_EBIA_OPTION, 190 S5P_PAD_RET_EBIB_OPTION, 191 S5P_PAD_RET_MMC2_OPTION, 192 S5P_PAD_RET_SPI_OPTION, 193 }; 194 195 static const struct samsung_retention_data exynos3250_retention_data __initconst = { 196 .regs = exynos3250_retention_regs, 197 .nr_regs = ARRAY_SIZE(exynos3250_retention_regs), 198 .value = EXYNOS_WAKEUP_FROM_LOWPWR, 199 .refcnt = &exynos_shared_retention_refcnt, 200 .init = exynos_retention_init, 201 }; 202 203 /* 204 * Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes 205 * two gpio/pin-mux/pinconfig controllers. 206 */ 207 const struct samsung_pin_ctrl exynos3250_pin_ctrl[] __initconst = { 208 { 209 /* pin-controller instance 0 data */ 210 .pin_banks = exynos3250_pin_banks0, 211 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks0), 212 .eint_gpio_init = exynos_eint_gpio_init, 213 .suspend = exynos_pinctrl_suspend, 214 .resume = exynos_pinctrl_resume, 215 .retention_data = &exynos3250_retention_data, 216 }, { 217 /* pin-controller instance 1 data */ 218 .pin_banks = exynos3250_pin_banks1, 219 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks1), 220 .eint_gpio_init = exynos_eint_gpio_init, 221 .eint_wkup_init = exynos_eint_wkup_init, 222 .suspend = exynos_pinctrl_suspend, 223 .resume = exynos_pinctrl_resume, 224 .retention_data = &exynos3250_retention_data, 225 }, 226 }; 227 228 /* pin banks of exynos4210 pin-controller 0 */ 229 static const struct samsung_pin_bank_data exynos4210_pin_banks0[] __initconst = { 230 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 231 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 232 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), 233 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), 234 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), 235 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14), 236 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18), 237 EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0", 0x1c), 238 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20), 239 EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2", 0x24), 240 EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3", 0x28), 241 EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4", 0x2c), 242 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30), 243 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34), 244 EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38), 245 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c), 246 }; 247 248 /* pin banks of exynos4210 pin-controller 1 */ 249 static const struct samsung_pin_bank_data exynos4210_pin_banks1[] __initconst = { 250 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00), 251 EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04), 252 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08), 253 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), 254 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), 255 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14), 256 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0", 0x18), 257 EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1", 0x1c), 258 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20), 259 EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"), 260 EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"), 261 EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"), 262 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"), 263 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"), 264 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"), 265 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"), 266 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), 267 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), 268 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), 269 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), 270 }; 271 272 /* pin banks of exynos4210 pin-controller 2 */ 273 static const struct samsung_pin_bank_data exynos4210_pin_banks2[] __initconst = { 274 EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"), 275 }; 276 277 /* PMU pad retention groups registers for Exynos4 (without audio) */ 278 static const u32 exynos4_retention_regs[] = { 279 S5P_PAD_RET_GPIO_OPTION, 280 S5P_PAD_RET_UART_OPTION, 281 S5P_PAD_RET_MMCA_OPTION, 282 S5P_PAD_RET_MMCB_OPTION, 283 S5P_PAD_RET_EBIA_OPTION, 284 S5P_PAD_RET_EBIB_OPTION, 285 }; 286 287 static const struct samsung_retention_data exynos4_retention_data __initconst = { 288 .regs = exynos4_retention_regs, 289 .nr_regs = ARRAY_SIZE(exynos4_retention_regs), 290 .value = EXYNOS_WAKEUP_FROM_LOWPWR, 291 .refcnt = &exynos_shared_retention_refcnt, 292 .init = exynos_retention_init, 293 }; 294 295 /* PMU retention control for audio pins can be tied to audio pin bank */ 296 static const u32 exynos4_audio_retention_regs[] = { 297 S5P_PAD_RET_MAUDIO_OPTION, 298 }; 299 300 static const struct samsung_retention_data exynos4_audio_retention_data __initconst = { 301 .regs = exynos4_audio_retention_regs, 302 .nr_regs = ARRAY_SIZE(exynos4_audio_retention_regs), 303 .value = EXYNOS_WAKEUP_FROM_LOWPWR, 304 .init = exynos_retention_init, 305 }; 306 307 /* 308 * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes 309 * three gpio/pin-mux/pinconfig controllers. 310 */ 311 const struct samsung_pin_ctrl exynos4210_pin_ctrl[] __initconst = { 312 { 313 /* pin-controller instance 0 data */ 314 .pin_banks = exynos4210_pin_banks0, 315 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks0), 316 .eint_gpio_init = exynos_eint_gpio_init, 317 .suspend = exynos_pinctrl_suspend, 318 .resume = exynos_pinctrl_resume, 319 .retention_data = &exynos4_retention_data, 320 }, { 321 /* pin-controller instance 1 data */ 322 .pin_banks = exynos4210_pin_banks1, 323 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks1), 324 .eint_gpio_init = exynos_eint_gpio_init, 325 .eint_wkup_init = exynos_eint_wkup_init, 326 .suspend = exynos_pinctrl_suspend, 327 .resume = exynos_pinctrl_resume, 328 .retention_data = &exynos4_retention_data, 329 }, { 330 /* pin-controller instance 2 data */ 331 .pin_banks = exynos4210_pin_banks2, 332 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks2), 333 .retention_data = &exynos4_audio_retention_data, 334 }, 335 }; 336 337 /* pin banks of exynos4x12 pin-controller 0 */ 338 static const struct samsung_pin_bank_data exynos4x12_pin_banks0[] __initconst = { 339 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 340 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 341 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), 342 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), 343 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), 344 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14), 345 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18), 346 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30), 347 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34), 348 EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38), 349 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c), 350 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x40), 351 EXYNOS_PIN_BANK_EINTG(5, 0x260, "gpj1", 0x44), 352 }; 353 354 /* pin banks of exynos4x12 pin-controller 1 */ 355 static const struct samsung_pin_bank_data exynos4x12_pin_banks1[] __initconst = { 356 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08), 357 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), 358 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), 359 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14), 360 EXYNOS_PIN_BANK_EINTG(7, 0x0C0, "gpl0", 0x18), 361 EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpl1", 0x1c), 362 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20), 363 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24), 364 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28), 365 EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c), 366 EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30), 367 EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34), 368 EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"), 369 EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"), 370 EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"), 371 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"), 372 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"), 373 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"), 374 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"), 375 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), 376 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), 377 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), 378 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), 379 }; 380 381 /* pin banks of exynos4x12 pin-controller 2 */ 382 static const struct samsung_pin_bank_data exynos4x12_pin_banks2[] __initconst = { 383 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), 384 }; 385 386 /* pin banks of exynos4x12 pin-controller 3 */ 387 static const struct samsung_pin_bank_data exynos4x12_pin_banks3[] __initconst = { 388 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), 389 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), 390 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08), 391 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv3", 0x0c), 392 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpv4", 0x10), 393 }; 394 395 /* 396 * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes 397 * four gpio/pin-mux/pinconfig controllers. 398 */ 399 const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] __initconst = { 400 { 401 /* pin-controller instance 0 data */ 402 .pin_banks = exynos4x12_pin_banks0, 403 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks0), 404 .eint_gpio_init = exynos_eint_gpio_init, 405 .suspend = exynos_pinctrl_suspend, 406 .resume = exynos_pinctrl_resume, 407 .retention_data = &exynos4_retention_data, 408 }, { 409 /* pin-controller instance 1 data */ 410 .pin_banks = exynos4x12_pin_banks1, 411 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks1), 412 .eint_gpio_init = exynos_eint_gpio_init, 413 .eint_wkup_init = exynos_eint_wkup_init, 414 .suspend = exynos_pinctrl_suspend, 415 .resume = exynos_pinctrl_resume, 416 .retention_data = &exynos4_retention_data, 417 }, { 418 /* pin-controller instance 2 data */ 419 .pin_banks = exynos4x12_pin_banks2, 420 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks2), 421 .eint_gpio_init = exynos_eint_gpio_init, 422 .suspend = exynos_pinctrl_suspend, 423 .resume = exynos_pinctrl_resume, 424 .retention_data = &exynos4_audio_retention_data, 425 }, { 426 /* pin-controller instance 3 data */ 427 .pin_banks = exynos4x12_pin_banks3, 428 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks3), 429 .eint_gpio_init = exynos_eint_gpio_init, 430 .suspend = exynos_pinctrl_suspend, 431 .resume = exynos_pinctrl_resume, 432 }, 433 }; 434 435 /* pin banks of exynos5250 pin-controller 0 */ 436 static const struct samsung_pin_bank_data exynos5250_pin_banks0[] __initconst = { 437 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 438 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 439 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), 440 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), 441 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10), 442 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14), 443 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18), 444 EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c), 445 EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20), 446 EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24), 447 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28), 448 EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c), 449 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30), 450 EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34), 451 EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"), 452 EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"), 453 EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"), 454 EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"), 455 EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"), 456 EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"), 457 EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"), 458 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), 459 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), 460 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), 461 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), 462 }; 463 464 /* pin banks of exynos5250 pin-controller 1 */ 465 static const struct samsung_pin_bank_data exynos5250_pin_banks1[] __initconst = { 466 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00), 467 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04), 468 EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08), 469 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c), 470 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10), 471 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14), 472 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18), 473 EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c), 474 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20), 475 }; 476 477 /* pin banks of exynos5250 pin-controller 2 */ 478 static const struct samsung_pin_bank_data exynos5250_pin_banks2[] __initconst = { 479 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), 480 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), 481 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08), 482 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c), 483 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10), 484 }; 485 486 /* pin banks of exynos5250 pin-controller 3 */ 487 static const struct samsung_pin_bank_data exynos5250_pin_banks3[] __initconst = { 488 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), 489 }; 490 491 /* 492 * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes 493 * four gpio/pin-mux/pinconfig controllers. 494 */ 495 const struct samsung_pin_ctrl exynos5250_pin_ctrl[] __initconst = { 496 { 497 /* pin-controller instance 0 data */ 498 .pin_banks = exynos5250_pin_banks0, 499 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks0), 500 .eint_gpio_init = exynos_eint_gpio_init, 501 .eint_wkup_init = exynos_eint_wkup_init, 502 .suspend = exynos_pinctrl_suspend, 503 .resume = exynos_pinctrl_resume, 504 .retention_data = &exynos4_retention_data, 505 }, { 506 /* pin-controller instance 1 data */ 507 .pin_banks = exynos5250_pin_banks1, 508 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks1), 509 .eint_gpio_init = exynos_eint_gpio_init, 510 .suspend = exynos_pinctrl_suspend, 511 .resume = exynos_pinctrl_resume, 512 .retention_data = &exynos4_retention_data, 513 }, { 514 /* pin-controller instance 2 data */ 515 .pin_banks = exynos5250_pin_banks2, 516 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks2), 517 .eint_gpio_init = exynos_eint_gpio_init, 518 .suspend = exynos_pinctrl_suspend, 519 .resume = exynos_pinctrl_resume, 520 }, { 521 /* pin-controller instance 3 data */ 522 .pin_banks = exynos5250_pin_banks3, 523 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks3), 524 .eint_gpio_init = exynos_eint_gpio_init, 525 .suspend = exynos_pinctrl_suspend, 526 .resume = exynos_pinctrl_resume, 527 .retention_data = &exynos4_audio_retention_data, 528 }, 529 }; 530 531 /* pin banks of exynos5260 pin-controller 0 */ 532 static const struct samsung_pin_bank_data exynos5260_pin_banks0[] __initconst = { 533 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00), 534 EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04), 535 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), 536 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), 537 EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10), 538 EXYNOS_PIN_BANK_EINTG(5, 0x0a0, "gpb2", 0x14), 539 EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpb3", 0x18), 540 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpb4", 0x1c), 541 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20), 542 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24), 543 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28), 544 EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c), 545 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30), 546 EXYNOS_PIN_BANK_EINTG(5, 0x1a0, "gpe1", 0x34), 547 EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38), 548 EXYNOS_PIN_BANK_EINTG(8, 0x1e0, "gpf1", 0x3c), 549 EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40), 550 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00), 551 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04), 552 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08), 553 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c), 554 }; 555 556 /* pin banks of exynos5260 pin-controller 1 */ 557 static const struct samsung_pin_bank_data exynos5260_pin_banks1[] __initconst = { 558 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00), 559 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04), 560 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08), 561 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c), 562 EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10), 563 }; 564 565 /* pin banks of exynos5260 pin-controller 2 */ 566 static const struct samsung_pin_bank_data exynos5260_pin_banks2[] __initconst = { 567 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), 568 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), 569 }; 570 571 /* 572 * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes 573 * three gpio/pin-mux/pinconfig controllers. 574 */ 575 const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = { 576 { 577 /* pin-controller instance 0 data */ 578 .pin_banks = exynos5260_pin_banks0, 579 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks0), 580 .eint_gpio_init = exynos_eint_gpio_init, 581 .eint_wkup_init = exynos_eint_wkup_init, 582 }, { 583 /* pin-controller instance 1 data */ 584 .pin_banks = exynos5260_pin_banks1, 585 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks1), 586 .eint_gpio_init = exynos_eint_gpio_init, 587 }, { 588 /* pin-controller instance 2 data */ 589 .pin_banks = exynos5260_pin_banks2, 590 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks2), 591 .eint_gpio_init = exynos_eint_gpio_init, 592 }, 593 }; 594 595 /* pin banks of exynos5410 pin-controller 0 */ 596 static const struct samsung_pin_bank_data exynos5410_pin_banks0[] __initconst = { 597 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 598 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 599 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), 600 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), 601 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10), 602 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14), 603 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18), 604 EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c), 605 EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc3", 0x20), 606 EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc1", 0x24), 607 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc2", 0x28), 608 EXYNOS_PIN_BANK_EINTN(2, 0x160, "gpm5"), 609 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x2c), 610 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpe0", 0x30), 611 EXYNOS_PIN_BANK_EINTG(2, 0x1C0, "gpe1", 0x34), 612 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf0", 0x38), 613 EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpf1", 0x3c), 614 EXYNOS_PIN_BANK_EINTG(8, 0x220, "gpg0", 0x40), 615 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpg1", 0x44), 616 EXYNOS_PIN_BANK_EINTG(2, 0x260, "gpg2", 0x48), 617 EXYNOS_PIN_BANK_EINTG(4, 0x280, "gph0", 0x4c), 618 EXYNOS_PIN_BANK_EINTG(8, 0x2A0, "gph1", 0x50), 619 EXYNOS_PIN_BANK_EINTN(8, 0x2C0, "gpm7"), 620 EXYNOS_PIN_BANK_EINTN(6, 0x2E0, "gpy0"), 621 EXYNOS_PIN_BANK_EINTN(4, 0x300, "gpy1"), 622 EXYNOS_PIN_BANK_EINTN(6, 0x320, "gpy2"), 623 EXYNOS_PIN_BANK_EINTN(8, 0x340, "gpy3"), 624 EXYNOS_PIN_BANK_EINTN(8, 0x360, "gpy4"), 625 EXYNOS_PIN_BANK_EINTN(8, 0x380, "gpy5"), 626 EXYNOS_PIN_BANK_EINTN(8, 0x3A0, "gpy6"), 627 EXYNOS_PIN_BANK_EINTN(8, 0x3C0, "gpy7"), 628 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), 629 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), 630 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), 631 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), 632 }; 633 634 /* pin banks of exynos5410 pin-controller 1 */ 635 static const struct samsung_pin_bank_data exynos5410_pin_banks1[] __initconst = { 636 EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpj0", 0x00), 637 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpj1", 0x04), 638 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpj2", 0x08), 639 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpj3", 0x0c), 640 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpj4", 0x10), 641 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpk0", 0x14), 642 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpk1", 0x18), 643 EXYNOS_PIN_BANK_EINTG(8, 0x0E0, "gpk2", 0x1c), 644 EXYNOS_PIN_BANK_EINTG(7, 0x100, "gpk3", 0x20), 645 }; 646 647 /* pin banks of exynos5410 pin-controller 2 */ 648 static const struct samsung_pin_bank_data exynos5410_pin_banks2[] __initconst = { 649 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), 650 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), 651 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08), 652 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c), 653 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10), 654 }; 655 656 /* pin banks of exynos5410 pin-controller 3 */ 657 static const struct samsung_pin_bank_data exynos5410_pin_banks3[] __initconst = { 658 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), 659 }; 660 661 /* 662 * Samsung pinctrl driver data for Exynos5410 SoC. Exynos5410 SoC includes 663 * four gpio/pin-mux/pinconfig controllers. 664 */ 665 const struct samsung_pin_ctrl exynos5410_pin_ctrl[] __initconst = { 666 { 667 /* pin-controller instance 0 data */ 668 .pin_banks = exynos5410_pin_banks0, 669 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks0), 670 .eint_gpio_init = exynos_eint_gpio_init, 671 .eint_wkup_init = exynos_eint_wkup_init, 672 .suspend = exynos_pinctrl_suspend, 673 .resume = exynos_pinctrl_resume, 674 }, { 675 /* pin-controller instance 1 data */ 676 .pin_banks = exynos5410_pin_banks1, 677 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks1), 678 .eint_gpio_init = exynos_eint_gpio_init, 679 .suspend = exynos_pinctrl_suspend, 680 .resume = exynos_pinctrl_resume, 681 }, { 682 /* pin-controller instance 2 data */ 683 .pin_banks = exynos5410_pin_banks2, 684 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks2), 685 .eint_gpio_init = exynos_eint_gpio_init, 686 .suspend = exynos_pinctrl_suspend, 687 .resume = exynos_pinctrl_resume, 688 }, { 689 /* pin-controller instance 3 data */ 690 .pin_banks = exynos5410_pin_banks3, 691 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks3), 692 .eint_gpio_init = exynos_eint_gpio_init, 693 .suspend = exynos_pinctrl_suspend, 694 .resume = exynos_pinctrl_resume, 695 }, 696 }; 697 698 /* pin banks of exynos5420 pin-controller 0 */ 699 static const struct samsung_pin_bank_data exynos5420_pin_banks0[] __initconst = { 700 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00), 701 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), 702 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), 703 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), 704 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), 705 }; 706 707 /* pin banks of exynos5420 pin-controller 1 */ 708 static const struct samsung_pin_bank_data exynos5420_pin_banks1[] __initconst = { 709 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00), 710 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04), 711 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08), 712 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c), 713 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpc4", 0x10), 714 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpd1", 0x14), 715 EXYNOS_PIN_BANK_EINTN(6, 0x0C0, "gpy0"), 716 EXYNOS_PIN_BANK_EINTN(4, 0x0E0, "gpy1"), 717 EXYNOS_PIN_BANK_EINTN(6, 0x100, "gpy2"), 718 EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpy3"), 719 EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpy4"), 720 EXYNOS_PIN_BANK_EINTN(8, 0x160, "gpy5"), 721 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy6"), 722 }; 723 724 /* pin banks of exynos5420 pin-controller 2 */ 725 static const struct samsung_pin_bank_data exynos5420_pin_banks2[] __initconst = { 726 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00), 727 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04), 728 EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08), 729 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpf1", 0x0c), 730 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10), 731 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14), 732 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18), 733 EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gpj4", 0x1c), 734 }; 735 736 /* pin banks of exynos5420 pin-controller 3 */ 737 static const struct samsung_pin_bank_data exynos5420_pin_banks3[] __initconst = { 738 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 739 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 740 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), 741 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), 742 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10), 743 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14), 744 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18), 745 EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpb4", 0x1c), 746 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph0", 0x20), 747 }; 748 749 /* pin banks of exynos5420 pin-controller 4 */ 750 static const struct samsung_pin_bank_data exynos5420_pin_banks4[] __initconst = { 751 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), 752 }; 753 754 /* PMU pad retention groups registers for Exynos5420 (without audio) */ 755 static const u32 exynos5420_retention_regs[] = { 756 EXYNOS_PAD_RET_DRAM_OPTION, 757 EXYNOS_PAD_RET_JTAG_OPTION, 758 EXYNOS5420_PAD_RET_GPIO_OPTION, 759 EXYNOS5420_PAD_RET_UART_OPTION, 760 EXYNOS5420_PAD_RET_MMCA_OPTION, 761 EXYNOS5420_PAD_RET_MMCB_OPTION, 762 EXYNOS5420_PAD_RET_MMCC_OPTION, 763 EXYNOS5420_PAD_RET_HSI_OPTION, 764 EXYNOS_PAD_RET_EBIA_OPTION, 765 EXYNOS_PAD_RET_EBIB_OPTION, 766 EXYNOS5420_PAD_RET_SPI_OPTION, 767 EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION, 768 }; 769 770 static const struct samsung_retention_data exynos5420_retention_data __initconst = { 771 .regs = exynos5420_retention_regs, 772 .nr_regs = ARRAY_SIZE(exynos5420_retention_regs), 773 .value = EXYNOS_WAKEUP_FROM_LOWPWR, 774 .refcnt = &exynos_shared_retention_refcnt, 775 .init = exynos_retention_init, 776 }; 777 778 /* 779 * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes 780 * four gpio/pin-mux/pinconfig controllers. 781 */ 782 const struct samsung_pin_ctrl exynos5420_pin_ctrl[] __initconst = { 783 { 784 /* pin-controller instance 0 data */ 785 .pin_banks = exynos5420_pin_banks0, 786 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks0), 787 .eint_gpio_init = exynos_eint_gpio_init, 788 .eint_wkup_init = exynos_eint_wkup_init, 789 .retention_data = &exynos5420_retention_data, 790 }, { 791 /* pin-controller instance 1 data */ 792 .pin_banks = exynos5420_pin_banks1, 793 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks1), 794 .eint_gpio_init = exynos_eint_gpio_init, 795 .retention_data = &exynos5420_retention_data, 796 }, { 797 /* pin-controller instance 2 data */ 798 .pin_banks = exynos5420_pin_banks2, 799 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks2), 800 .eint_gpio_init = exynos_eint_gpio_init, 801 .retention_data = &exynos5420_retention_data, 802 }, { 803 /* pin-controller instance 3 data */ 804 .pin_banks = exynos5420_pin_banks3, 805 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks3), 806 .eint_gpio_init = exynos_eint_gpio_init, 807 .retention_data = &exynos5420_retention_data, 808 }, { 809 /* pin-controller instance 4 data */ 810 .pin_banks = exynos5420_pin_banks4, 811 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks4), 812 .eint_gpio_init = exynos_eint_gpio_init, 813 .retention_data = &exynos4_audio_retention_data, 814 }, 815 }; 816