1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * SuperH Pin Function Controller Support 4 * 5 * Copyright (c) 2008 Magnus Damm 6 */ 7 8 #ifndef __SH_PFC_H 9 #define __SH_PFC_H 10 11 #include <linux/bug.h> 12 #include <linux/pinctrl/pinconf-generic.h> 13 #include <linux/spinlock.h> 14 #include <linux/stringify.h> 15 16 enum { 17 PINMUX_TYPE_NONE, 18 PINMUX_TYPE_FUNCTION, 19 PINMUX_TYPE_GPIO, 20 PINMUX_TYPE_OUTPUT, 21 PINMUX_TYPE_INPUT, 22 }; 23 24 #define SH_PFC_PIN_NONE U16_MAX 25 26 #define SH_PFC_PIN_CFG_INPUT (1 << 0) 27 #define SH_PFC_PIN_CFG_OUTPUT (1 << 1) 28 #define SH_PFC_PIN_CFG_PULL_UP (1 << 2) 29 #define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3) 30 #define SH_PFC_PIN_CFG_PULL_UP_DOWN (SH_PFC_PIN_CFG_PULL_UP | \ 31 SH_PFC_PIN_CFG_PULL_DOWN) 32 #define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4) 33 #define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5) 34 35 #define SH_PFC_PIN_VOLTAGE_18_33 (0 << 6) 36 #define SH_PFC_PIN_VOLTAGE_25_33 (1 << 6) 37 38 #define SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \ 39 SH_PFC_PIN_VOLTAGE_18_33) 40 #define SH_PFC_PIN_CFG_IO_VOLTAGE_25_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \ 41 SH_PFC_PIN_VOLTAGE_25_33) 42 43 #define SH_PFC_PIN_CFG_NO_GPIO (1 << 31) 44 45 struct sh_pfc_pin { 46 const char *name; 47 unsigned int configs; 48 u16 pin; 49 u16 enum_id; 50 }; 51 52 #define SH_PFC_PIN_GROUP_ALIAS(alias, _name) { \ 53 .name = #alias, \ 54 .pins = _name##_pins, \ 55 .mux = _name##_mux, \ 56 .nr_pins = ARRAY_SIZE(_name##_pins) + \ 57 BUILD_BUG_ON_ZERO(sizeof(_name##_pins) != sizeof(_name##_mux)), \ 58 } 59 #define SH_PFC_PIN_GROUP(name) SH_PFC_PIN_GROUP_ALIAS(name, name) 60 61 /* 62 * Define a pin group referring to a subset of an array of pins. 63 */ 64 #define SH_PFC_PIN_GROUP_SUBSET(_name, data, first, n) { \ 65 .name = #_name, \ 66 .pins = data##_pins + first, \ 67 .mux = data##_mux + first, \ 68 .nr_pins = n + \ 69 BUILD_BUG_ON_ZERO(first + n > ARRAY_SIZE(data##_pins)) + \ 70 BUILD_BUG_ON_ZERO(first + n > ARRAY_SIZE(data##_mux)), \ 71 } 72 73 /* 74 * Define a pin group for the data pins of a resizable bus. 75 * An optional 'suffix' argument is accepted, to be used when the same group 76 * can appear on a different set of pins. 77 */ 78 #define BUS_DATA_PIN_GROUP(base, n, ...) \ 79 SH_PFC_PIN_GROUP_SUBSET(base##n##__VA_ARGS__, base##__VA_ARGS__, 0, n) 80 81 struct sh_pfc_pin_group { 82 const char *name; 83 const unsigned int *pins; 84 const unsigned int *mux; 85 unsigned int nr_pins; 86 }; 87 88 #define SH_PFC_FUNCTION(n) { \ 89 .name = #n, \ 90 .groups = n##_groups, \ 91 .nr_groups = ARRAY_SIZE(n##_groups), \ 92 } 93 94 struct sh_pfc_function { 95 const char *name; 96 const char * const *groups; 97 unsigned int nr_groups; 98 }; 99 100 struct pinmux_func { 101 u16 enum_id; 102 const char *name; 103 }; 104 105 struct pinmux_cfg_reg { 106 u32 reg; 107 u8 reg_width, field_width; 108 #ifdef DEBUG 109 u16 nr_enum_ids; /* for variable width regs only */ 110 #define SET_NR_ENUM_IDS(n) .nr_enum_ids = n, 111 #else 112 #define SET_NR_ENUM_IDS(n) 113 #endif 114 const u16 *enum_ids; 115 const u8 *var_field_width; 116 }; 117 118 #define GROUP(...) __VA_ARGS__ 119 120 /* 121 * Describe a config register consisting of several fields of the same width 122 * - name: Register name (unused, for documentation purposes only) 123 * - r: Physical register address 124 * - r_width: Width of the register (in bits) 125 * - f_width: Width of the fixed-width register fields (in bits) 126 * - ids: For each register field (from left to right, i.e. MSB to LSB), 127 * 2^f_width enum IDs must be specified, one for each possible 128 * combination of the register field bit values, all wrapped using 129 * the GROUP() macro. 130 */ 131 #define PINMUX_CFG_REG(name, r, r_width, f_width, ids) \ 132 .reg = r, .reg_width = r_width, \ 133 .field_width = f_width + BUILD_BUG_ON_ZERO(r_width % f_width) + \ 134 BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \ 135 (r_width / f_width) * (1 << f_width)), \ 136 .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)]) \ 137 { ids } 138 139 /* 140 * Describe a config register consisting of several fields of different widths 141 * - name: Register name (unused, for documentation purposes only) 142 * - r: Physical register address 143 * - r_width: Width of the register (in bits) 144 * - f_widths: List of widths of the register fields (in bits), from left 145 * to right (i.e. MSB to LSB), wrapped using the GROUP() macro. 146 * - ids: For each register field (from left to right, i.e. MSB to LSB), 147 * 2^f_widths[i] enum IDs must be specified, one for each possible 148 * combination of the register field bit values, all wrapped using 149 * the GROUP() macro. 150 */ 151 #define PINMUX_CFG_REG_VAR(name, r, r_width, f_widths, ids) \ 152 .reg = r, .reg_width = r_width, \ 153 .var_field_width = (const u8 []) { f_widths, 0 }, \ 154 SET_NR_ENUM_IDS(sizeof((const u16 []) { ids }) / sizeof(u16)) \ 155 .enum_ids = (const u16 []) { ids } 156 157 struct pinmux_drive_reg_field { 158 u16 pin; 159 u8 offset; 160 u8 size; 161 }; 162 163 struct pinmux_drive_reg { 164 u32 reg; 165 const struct pinmux_drive_reg_field fields[8]; 166 }; 167 168 #define PINMUX_DRIVE_REG(name, r) \ 169 .reg = r, \ 170 .fields = 171 172 struct pinmux_bias_reg { /* At least one of puen/pud must exist */ 173 u32 puen; /* Pull-enable or pull-up control register */ 174 u32 pud; /* Pull-up/down or pull-down control register */ 175 const u16 pins[32]; 176 }; 177 178 #define PINMUX_BIAS_REG(name1, r1, name2, r2) \ 179 .puen = r1, \ 180 .pud = r2, \ 181 .pins = 182 183 struct pinmux_ioctrl_reg { 184 u32 reg; 185 }; 186 187 struct pinmux_data_reg { 188 u32 reg; 189 u8 reg_width; 190 const u16 *enum_ids; 191 }; 192 193 /* 194 * Describe a data register 195 * - name: Register name (unused, for documentation purposes only) 196 * - r: Physical register address 197 * - r_width: Width of the register (in bits) 198 * - ids: For each register bit (from left to right, i.e. MSB to LSB), one 199 * enum ID must be specified, all wrapped using the GROUP() macro. 200 */ 201 #define PINMUX_DATA_REG(name, r, r_width, ids) \ 202 .reg = r, .reg_width = r_width + \ 203 BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \ 204 r_width), \ 205 .enum_ids = (const u16 [r_width]) { ids } 206 207 struct pinmux_irq { 208 const short *gpios; 209 }; 210 211 /* 212 * Describe the mapping from GPIOs to a single IRQ 213 * - ids...: List of GPIOs that are mapped to the same IRQ 214 */ 215 #define PINMUX_IRQ(ids...) { \ 216 .gpios = (const short []) { ids, -1 } \ 217 } 218 219 struct pinmux_range { 220 u16 begin; 221 u16 end; 222 u16 force; 223 }; 224 225 struct sh_pfc_window { 226 phys_addr_t phys; 227 void __iomem *virt; 228 unsigned long size; 229 }; 230 231 struct sh_pfc_pin_range; 232 233 struct sh_pfc { 234 struct device *dev; 235 const struct sh_pfc_soc_info *info; 236 spinlock_t lock; 237 238 unsigned int num_windows; 239 struct sh_pfc_window *windows; 240 unsigned int num_irqs; 241 unsigned int *irqs; 242 243 struct sh_pfc_pin_range *ranges; 244 unsigned int nr_ranges; 245 246 unsigned int nr_gpio_pins; 247 248 struct sh_pfc_chip *gpio; 249 u32 *saved_regs; 250 }; 251 252 struct sh_pfc_soc_operations { 253 int (*init)(struct sh_pfc *pfc); 254 unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin); 255 void (*set_bias)(struct sh_pfc *pfc, unsigned int pin, 256 unsigned int bias); 257 int (*pin_to_pocctrl)(unsigned int pin, u32 *pocctrl); 258 int (*pin_to_portcr)(unsigned int pin); 259 }; 260 261 struct sh_pfc_soc_info { 262 const char *name; 263 const struct sh_pfc_soc_operations *ops; 264 265 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO 266 struct pinmux_range input; 267 struct pinmux_range output; 268 const struct pinmux_irq *gpio_irq; 269 unsigned int gpio_irq_size; 270 #endif 271 272 struct pinmux_range function; 273 274 const struct sh_pfc_pin *pins; 275 unsigned int nr_pins; 276 const struct sh_pfc_pin_group *groups; 277 unsigned int nr_groups; 278 const struct sh_pfc_function *functions; 279 unsigned int nr_functions; 280 281 #ifdef CONFIG_PINCTRL_SH_FUNC_GPIO 282 const struct pinmux_func *func_gpios; 283 unsigned int nr_func_gpios; 284 #endif 285 286 const struct pinmux_cfg_reg *cfg_regs; 287 const struct pinmux_drive_reg *drive_regs; 288 const struct pinmux_bias_reg *bias_regs; 289 const struct pinmux_ioctrl_reg *ioctrl_regs; 290 const struct pinmux_data_reg *data_regs; 291 292 const u16 *pinmux_data; 293 unsigned int pinmux_data_size; 294 295 u32 unlock_reg; /* can be literal address or mask */ 296 }; 297 298 extern const struct sh_pfc_soc_info emev2_pinmux_info; 299 extern const struct sh_pfc_soc_info r8a73a4_pinmux_info; 300 extern const struct sh_pfc_soc_info r8a7740_pinmux_info; 301 extern const struct sh_pfc_soc_info r8a7742_pinmux_info; 302 extern const struct sh_pfc_soc_info r8a7743_pinmux_info; 303 extern const struct sh_pfc_soc_info r8a7744_pinmux_info; 304 extern const struct sh_pfc_soc_info r8a7745_pinmux_info; 305 extern const struct sh_pfc_soc_info r8a77470_pinmux_info; 306 extern const struct sh_pfc_soc_info r8a774a1_pinmux_info; 307 extern const struct sh_pfc_soc_info r8a774b1_pinmux_info; 308 extern const struct sh_pfc_soc_info r8a774c0_pinmux_info; 309 extern const struct sh_pfc_soc_info r8a774e1_pinmux_info; 310 extern const struct sh_pfc_soc_info r8a7778_pinmux_info; 311 extern const struct sh_pfc_soc_info r8a7779_pinmux_info; 312 extern const struct sh_pfc_soc_info r8a7790_pinmux_info; 313 extern const struct sh_pfc_soc_info r8a7791_pinmux_info; 314 extern const struct sh_pfc_soc_info r8a7792_pinmux_info; 315 extern const struct sh_pfc_soc_info r8a7793_pinmux_info; 316 extern const struct sh_pfc_soc_info r8a7794_pinmux_info; 317 extern const struct sh_pfc_soc_info r8a77950_pinmux_info; 318 extern const struct sh_pfc_soc_info r8a77951_pinmux_info; 319 extern const struct sh_pfc_soc_info r8a77960_pinmux_info; 320 extern const struct sh_pfc_soc_info r8a77961_pinmux_info; 321 extern const struct sh_pfc_soc_info r8a77965_pinmux_info; 322 extern const struct sh_pfc_soc_info r8a77970_pinmux_info; 323 extern const struct sh_pfc_soc_info r8a77980_pinmux_info; 324 extern const struct sh_pfc_soc_info r8a77990_pinmux_info; 325 extern const struct sh_pfc_soc_info r8a77995_pinmux_info; 326 extern const struct sh_pfc_soc_info r8a779a0_pinmux_info; 327 extern const struct sh_pfc_soc_info r8a779f0_pinmux_info; 328 extern const struct sh_pfc_soc_info sh7203_pinmux_info; 329 extern const struct sh_pfc_soc_info sh7264_pinmux_info; 330 extern const struct sh_pfc_soc_info sh7269_pinmux_info; 331 extern const struct sh_pfc_soc_info sh73a0_pinmux_info; 332 extern const struct sh_pfc_soc_info sh7720_pinmux_info; 333 extern const struct sh_pfc_soc_info sh7722_pinmux_info; 334 extern const struct sh_pfc_soc_info sh7723_pinmux_info; 335 extern const struct sh_pfc_soc_info sh7724_pinmux_info; 336 extern const struct sh_pfc_soc_info sh7734_pinmux_info; 337 extern const struct sh_pfc_soc_info sh7757_pinmux_info; 338 extern const struct sh_pfc_soc_info sh7785_pinmux_info; 339 extern const struct sh_pfc_soc_info sh7786_pinmux_info; 340 extern const struct sh_pfc_soc_info shx3_pinmux_info; 341 342 /* ----------------------------------------------------------------------------- 343 * Helper macros to create pin and port lists 344 */ 345 346 /* 347 * sh_pfc_soc_info pinmux_data array macros 348 */ 349 350 /* 351 * Describe generic pinmux data 352 * - data_or_mark: *_DATA or *_MARK enum ID 353 * - ids...: List of enum IDs to associate with data_or_mark 354 */ 355 #define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0 356 357 /* 358 * Describe a pinmux configuration without GPIO function that needs 359 * configuration in a Peripheral Function Select Register (IPSR) 360 * - ipsr: IPSR field (unused, for documentation purposes only) 361 * - fn: Function name, referring to a field in the IPSR 362 */ 363 #define PINMUX_IPSR_NOGP(ipsr, fn) \ 364 PINMUX_DATA(fn##_MARK, FN_##fn) 365 366 /* 367 * Describe a pinmux configuration with GPIO function that needs configuration 368 * in both a Peripheral Function Select Register (IPSR) and in a 369 * GPIO/Peripheral Function Select Register (GPSR) 370 * - ipsr: IPSR field 371 * - fn: Function name, also referring to the IPSR field 372 */ 373 #define PINMUX_IPSR_GPSR(ipsr, fn) \ 374 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr) 375 376 /* 377 * Describe a pinmux configuration without GPIO function that needs 378 * configuration in a Peripheral Function Select Register (IPSR), and where the 379 * pinmux function has a representation in a Module Select Register (MOD_SEL). 380 * - ipsr: IPSR field (unused, for documentation purposes only) 381 * - fn: Function name, also referring to the IPSR field 382 * - msel: Module selector 383 */ 384 #define PINMUX_IPSR_NOGM(ipsr, fn, msel) \ 385 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##msel) 386 387 /* 388 * Describe a pinmux configuration with GPIO function where the pinmux function 389 * has no representation in a Peripheral Function Select Register (IPSR), but 390 * instead solely depends on a group selection. 391 * - gpsr: GPSR field 392 * - fn: Function name, also referring to the GPSR field 393 * - gsel: Group selector 394 */ 395 #define PINMUX_IPSR_NOFN(gpsr, fn, gsel) \ 396 PINMUX_DATA(fn##_MARK, FN_##gpsr, FN_##gsel) 397 398 /* 399 * Describe a pinmux configuration with GPIO function that needs configuration 400 * in both a Peripheral Function Select Register (IPSR) and a GPIO/Peripheral 401 * Function Select Register (GPSR), and where the pinmux function has a 402 * representation in a Module Select Register (MOD_SEL). 403 * - ipsr: IPSR field 404 * - fn: Function name, also referring to the IPSR field 405 * - msel: Module selector 406 */ 407 #define PINMUX_IPSR_MSEL(ipsr, fn, msel) \ 408 PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr) 409 410 /* 411 * Describe a pinmux configuration similar to PINMUX_IPSR_MSEL, but with 412 * an additional select register that controls physical multiplexing 413 * with another pin. 414 * - ipsr: IPSR field 415 * - fn: Function name, also referring to the IPSR field 416 * - psel: Physical multiplexing selector 417 * - msel: Module selector 418 */ 419 #define PINMUX_IPSR_PHYS_MSEL(ipsr, fn, psel, msel) \ 420 PINMUX_DATA(fn##_MARK, FN_##psel, FN_##msel, FN_##fn, FN_##ipsr) 421 422 /* 423 * Describe a pinmux configuration in which a pin is physically multiplexed 424 * with other pins. 425 * - ipsr: IPSR field 426 * - fn: Function name 427 * - psel: Physical multiplexing selector 428 */ 429 #define PINMUX_IPSR_PHYS(ipsr, fn, psel) \ 430 PINMUX_DATA(fn##_MARK, FN_##psel, FN_##ipsr) 431 432 /* 433 * Describe a pinmux configuration for a single-function pin with GPIO 434 * capability. 435 * - fn: Function name 436 */ 437 #define PINMUX_SINGLE(fn) \ 438 PINMUX_DATA(fn##_MARK, FN_##fn) 439 440 /* 441 * GP port style (32 ports banks) 442 */ 443 444 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \ 445 fn(bank, pin, GP_##bank##_##pin, sfx, cfg) 446 #define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0) 447 448 #define PORT_GP_CFG_2(bank, fn, sfx, cfg) \ 449 PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \ 450 PORT_GP_CFG_1(bank, 1, fn, sfx, cfg) 451 #define PORT_GP_2(bank, fn, sfx) PORT_GP_CFG_2(bank, fn, sfx, 0) 452 453 #define PORT_GP_CFG_4(bank, fn, sfx, cfg) \ 454 PORT_GP_CFG_2(bank, fn, sfx, cfg), \ 455 PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \ 456 PORT_GP_CFG_1(bank, 3, fn, sfx, cfg) 457 #define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0) 458 459 #define PORT_GP_CFG_6(bank, fn, sfx, cfg) \ 460 PORT_GP_CFG_4(bank, fn, sfx, cfg), \ 461 PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \ 462 PORT_GP_CFG_1(bank, 5, fn, sfx, cfg) 463 #define PORT_GP_6(bank, fn, sfx) PORT_GP_CFG_6(bank, fn, sfx, 0) 464 465 #define PORT_GP_CFG_7(bank, fn, sfx, cfg) \ 466 PORT_GP_CFG_6(bank, fn, sfx, cfg), \ 467 PORT_GP_CFG_1(bank, 6, fn, sfx, cfg) 468 #define PORT_GP_7(bank, fn, sfx) PORT_GP_CFG_7(bank, fn, sfx, 0) 469 470 #define PORT_GP_CFG_8(bank, fn, sfx, cfg) \ 471 PORT_GP_CFG_7(bank, fn, sfx, cfg), \ 472 PORT_GP_CFG_1(bank, 7, fn, sfx, cfg) 473 #define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0) 474 475 #define PORT_GP_CFG_9(bank, fn, sfx, cfg) \ 476 PORT_GP_CFG_8(bank, fn, sfx, cfg), \ 477 PORT_GP_CFG_1(bank, 8, fn, sfx, cfg) 478 #define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0) 479 480 #define PORT_GP_CFG_10(bank, fn, sfx, cfg) \ 481 PORT_GP_CFG_9(bank, fn, sfx, cfg), \ 482 PORT_GP_CFG_1(bank, 9, fn, sfx, cfg) 483 #define PORT_GP_10(bank, fn, sfx) PORT_GP_CFG_10(bank, fn, sfx, 0) 484 485 #define PORT_GP_CFG_11(bank, fn, sfx, cfg) \ 486 PORT_GP_CFG_10(bank, fn, sfx, cfg), \ 487 PORT_GP_CFG_1(bank, 10, fn, sfx, cfg) 488 #define PORT_GP_11(bank, fn, sfx) PORT_GP_CFG_11(bank, fn, sfx, 0) 489 490 #define PORT_GP_CFG_12(bank, fn, sfx, cfg) \ 491 PORT_GP_CFG_11(bank, fn, sfx, cfg), \ 492 PORT_GP_CFG_1(bank, 11, fn, sfx, cfg) 493 #define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0) 494 495 #define PORT_GP_CFG_14(bank, fn, sfx, cfg) \ 496 PORT_GP_CFG_12(bank, fn, sfx, cfg), \ 497 PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), \ 498 PORT_GP_CFG_1(bank, 13, fn, sfx, cfg) 499 #define PORT_GP_14(bank, fn, sfx) PORT_GP_CFG_14(bank, fn, sfx, 0) 500 501 #define PORT_GP_CFG_15(bank, fn, sfx, cfg) \ 502 PORT_GP_CFG_14(bank, fn, sfx, cfg), \ 503 PORT_GP_CFG_1(bank, 14, fn, sfx, cfg) 504 #define PORT_GP_15(bank, fn, sfx) PORT_GP_CFG_15(bank, fn, sfx, 0) 505 506 #define PORT_GP_CFG_16(bank, fn, sfx, cfg) \ 507 PORT_GP_CFG_15(bank, fn, sfx, cfg), \ 508 PORT_GP_CFG_1(bank, 15, fn, sfx, cfg) 509 #define PORT_GP_16(bank, fn, sfx) PORT_GP_CFG_16(bank, fn, sfx, 0) 510 511 #define PORT_GP_CFG_17(bank, fn, sfx, cfg) \ 512 PORT_GP_CFG_16(bank, fn, sfx, cfg), \ 513 PORT_GP_CFG_1(bank, 16, fn, sfx, cfg) 514 #define PORT_GP_17(bank, fn, sfx) PORT_GP_CFG_17(bank, fn, sfx, 0) 515 516 #define PORT_GP_CFG_18(bank, fn, sfx, cfg) \ 517 PORT_GP_CFG_17(bank, fn, sfx, cfg), \ 518 PORT_GP_CFG_1(bank, 17, fn, sfx, cfg) 519 #define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0) 520 521 #define PORT_GP_CFG_19(bank, fn, sfx, cfg) \ 522 PORT_GP_CFG_18(bank, fn, sfx, cfg), \ 523 PORT_GP_CFG_1(bank, 18, fn, sfx, cfg) 524 #define PORT_GP_19(bank, fn, sfx) PORT_GP_CFG_19(bank, fn, sfx, 0) 525 526 #define PORT_GP_CFG_20(bank, fn, sfx, cfg) \ 527 PORT_GP_CFG_19(bank, fn, sfx, cfg), \ 528 PORT_GP_CFG_1(bank, 19, fn, sfx, cfg) 529 #define PORT_GP_20(bank, fn, sfx) PORT_GP_CFG_20(bank, fn, sfx, 0) 530 531 #define PORT_GP_CFG_21(bank, fn, sfx, cfg) \ 532 PORT_GP_CFG_20(bank, fn, sfx, cfg), \ 533 PORT_GP_CFG_1(bank, 20, fn, sfx, cfg) 534 #define PORT_GP_21(bank, fn, sfx) PORT_GP_CFG_21(bank, fn, sfx, 0) 535 536 #define PORT_GP_CFG_22(bank, fn, sfx, cfg) \ 537 PORT_GP_CFG_21(bank, fn, sfx, cfg), \ 538 PORT_GP_CFG_1(bank, 21, fn, sfx, cfg) 539 #define PORT_GP_22(bank, fn, sfx) PORT_GP_CFG_22(bank, fn, sfx, 0) 540 541 #define PORT_GP_CFG_23(bank, fn, sfx, cfg) \ 542 PORT_GP_CFG_22(bank, fn, sfx, cfg), \ 543 PORT_GP_CFG_1(bank, 22, fn, sfx, cfg) 544 #define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0) 545 546 #define PORT_GP_CFG_24(bank, fn, sfx, cfg) \ 547 PORT_GP_CFG_23(bank, fn, sfx, cfg), \ 548 PORT_GP_CFG_1(bank, 23, fn, sfx, cfg) 549 #define PORT_GP_24(bank, fn, sfx) PORT_GP_CFG_24(bank, fn, sfx, 0) 550 551 #define PORT_GP_CFG_25(bank, fn, sfx, cfg) \ 552 PORT_GP_CFG_24(bank, fn, sfx, cfg), \ 553 PORT_GP_CFG_1(bank, 24, fn, sfx, cfg) 554 #define PORT_GP_25(bank, fn, sfx) PORT_GP_CFG_25(bank, fn, sfx, 0) 555 556 #define PORT_GP_CFG_26(bank, fn, sfx, cfg) \ 557 PORT_GP_CFG_25(bank, fn, sfx, cfg), \ 558 PORT_GP_CFG_1(bank, 25, fn, sfx, cfg) 559 #define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0) 560 561 #define PORT_GP_CFG_27(bank, fn, sfx, cfg) \ 562 PORT_GP_CFG_26(bank, fn, sfx, cfg), \ 563 PORT_GP_CFG_1(bank, 26, fn, sfx, cfg) 564 #define PORT_GP_27(bank, fn, sfx) PORT_GP_CFG_27(bank, fn, sfx, 0) 565 566 #define PORT_GP_CFG_28(bank, fn, sfx, cfg) \ 567 PORT_GP_CFG_27(bank, fn, sfx, cfg), \ 568 PORT_GP_CFG_1(bank, 27, fn, sfx, cfg) 569 #define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0) 570 571 #define PORT_GP_CFG_29(bank, fn, sfx, cfg) \ 572 PORT_GP_CFG_28(bank, fn, sfx, cfg), \ 573 PORT_GP_CFG_1(bank, 28, fn, sfx, cfg) 574 #define PORT_GP_29(bank, fn, sfx) PORT_GP_CFG_29(bank, fn, sfx, 0) 575 576 #define PORT_GP_CFG_30(bank, fn, sfx, cfg) \ 577 PORT_GP_CFG_29(bank, fn, sfx, cfg), \ 578 PORT_GP_CFG_1(bank, 29, fn, sfx, cfg) 579 #define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0) 580 581 #define PORT_GP_CFG_31(bank, fn, sfx, cfg) \ 582 PORT_GP_CFG_30(bank, fn, sfx, cfg), \ 583 PORT_GP_CFG_1(bank, 30, fn, sfx, cfg) 584 #define PORT_GP_31(bank, fn, sfx) PORT_GP_CFG_31(bank, fn, sfx, 0) 585 586 #define PORT_GP_CFG_32(bank, fn, sfx, cfg) \ 587 PORT_GP_CFG_31(bank, fn, sfx, cfg), \ 588 PORT_GP_CFG_1(bank, 31, fn, sfx, cfg) 589 #define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0) 590 591 #define PORT_GP_32_REV(bank, fn, sfx) \ 592 PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \ 593 PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \ 594 PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \ 595 PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \ 596 PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \ 597 PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \ 598 PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \ 599 PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \ 600 PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \ 601 PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \ 602 PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \ 603 PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \ 604 PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \ 605 PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \ 606 PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \ 607 PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx) 608 609 /* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */ 610 #define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx 611 #define GP_ALL(str) CPU_ALL_GP(_GP_ALL, str) 612 613 /* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */ 614 #define _GP_GPIO(bank, _pin, _name, sfx, cfg) { \ 615 .pin = (bank * 32) + _pin, \ 616 .name = __stringify(_name), \ 617 .enum_id = _name##_DATA, \ 618 .configs = cfg, \ 619 } 620 #define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused) 621 622 /* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */ 623 #define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN) 624 #define PINMUX_DATA_GP_ALL() CPU_ALL_GP(_GP_DATA, unused) 625 626 /* 627 * GP_ASSIGN_LAST() - Expand to an enum definition for the last GP pin 628 * 629 * The largest GP pin index is obtained by taking the size of a union, 630 * containing one array per GP pin, sized by the corresponding pin index. 631 * As the fields in the CPU_ALL_GP() macro definition are separated by commas, 632 * while the members of a union must be terminated by semicolons, the commas 633 * are absorbed by wrapping them inside dummy attributes. 634 */ 635 #define _GP_ENTRY(bank, pin, name, sfx, cfg) \ 636 deprecated)); char name[(bank * 32) + pin] __attribute__((deprecated 637 #define GP_ASSIGN_LAST() \ 638 GP_LAST = sizeof(union { \ 639 char dummy[0] __attribute__((deprecated, \ 640 CPU_ALL_GP(_GP_ENTRY, unused), \ 641 deprecated)); \ 642 }) 643 644 /* 645 * PORT style (linear pin space) 646 */ 647 648 #define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx) 649 650 #define PORT_10(pn, fn, pfx, sfx) \ 651 PORT_1(pn, fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx), \ 652 PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx), \ 653 PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx), \ 654 PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx), \ 655 PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx) 656 657 #define PORT_90(pn, fn, pfx, sfx) \ 658 PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \ 659 PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \ 660 PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \ 661 PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \ 662 PORT_10(pn+90, fn, pfx##9, sfx) 663 664 /* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */ 665 #define _PORT_ALL(pn, pfx, sfx) pfx##_##sfx 666 #define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str) 667 668 /* PINMUX_GPIO - Expand to a sh_pfc_pin entry */ 669 #define PINMUX_GPIO(_pin) \ 670 [GPIO_##_pin] = { \ 671 .pin = (u16)-1, \ 672 .name = __stringify(GPIO_##_pin), \ 673 .enum_id = _pin##_DATA, \ 674 } 675 676 /* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */ 677 #define SH_PFC_PIN_CFG(_pin, cfgs) { \ 678 .pin = _pin, \ 679 .name = __stringify(PORT##_pin), \ 680 .enum_id = PORT##_pin##_DATA, \ 681 .configs = cfgs, \ 682 } 683 684 /* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0, 685 * PORT_name_OUT, PORT_name_IN marks 686 */ 687 #define _PORT_DATA(pn, pfx, sfx) \ 688 PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0, \ 689 PORT##pfx##_OUT, PORT##pfx##_IN) 690 #define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused) 691 692 /* 693 * PORT_ASSIGN_LAST() - Expand to an enum definition for the last PORT pin 694 * 695 * The largest PORT pin index is obtained by taking the size of a union, 696 * containing one array per PORT pin, sized by the corresponding pin index. 697 * As the fields in the CPU_ALL_PORT() macro definition are separated by 698 * commas, while the members of a union must be terminated by semicolons, the 699 * commas are absorbed by wrapping them inside dummy attributes. 700 */ 701 #define _PORT_ENTRY(pn, pfx, sfx) \ 702 deprecated)); char pfx[pn] __attribute__((deprecated 703 #define PORT_ASSIGN_LAST() \ 704 PORT_LAST = sizeof(union { \ 705 char dummy[0] __attribute__((deprecated, \ 706 CPU_ALL_PORT(_PORT_ENTRY, PORT, unused), \ 707 deprecated)); \ 708 }) 709 710 /* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */ 711 #define PINMUX_GPIO_FN(gpio, base, data_or_mark) \ 712 [gpio - (base)] = { \ 713 .name = __stringify(gpio), \ 714 .enum_id = data_or_mark, \ 715 } 716 #define GPIO_FN(str) \ 717 PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK) 718 719 /* 720 * Pins not associated with a GPIO port 721 */ 722 723 #define PIN_NOGP_CFG(pin, name, fn, cfg) fn(pin, name, cfg) 724 #define PIN_NOGP(pin, name, fn) fn(pin, name, 0) 725 726 /* NOGP_ALL - Expand to a list of PIN_id */ 727 #define _NOGP_ALL(pin, name, cfg) PIN_##pin 728 #define NOGP_ALL() CPU_ALL_NOGP(_NOGP_ALL) 729 730 /* PINMUX_NOGP_ALL - Expand to a list of sh_pfc_pin entries */ 731 #define _NOGP_PINMUX(_pin, _name, cfg) { \ 732 .pin = PIN_##_pin, \ 733 .name = "PIN_" _name, \ 734 .configs = SH_PFC_PIN_CFG_NO_GPIO | cfg, \ 735 } 736 #define PINMUX_NOGP_ALL() CPU_ALL_NOGP(_NOGP_PINMUX) 737 738 /* 739 * PORTnCR helper macro for SH-Mobile/R-Mobile 740 */ 741 #define PORTCR(nr, reg) { \ 742 PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, GROUP(2, 2, 1, 3), \ 743 GROUP( \ 744 /* PULMD[1:0], handled by .set_bias() */ \ 745 0, 0, 0, 0, \ 746 /* IE and OE */ \ 747 0, PORT##nr##_OUT, PORT##nr##_IN, 0, \ 748 /* SEC, not supported */ \ 749 0, 0, \ 750 /* PTMD[2:0] */ \ 751 PORT##nr##_FN0, PORT##nr##_FN1, \ 752 PORT##nr##_FN2, PORT##nr##_FN3, \ 753 PORT##nr##_FN4, PORT##nr##_FN5, \ 754 PORT##nr##_FN6, PORT##nr##_FN7 \ 755 )) \ 756 } 757 758 /* 759 * GPIO number helper macro for R-Car 760 */ 761 #define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin)) 762 763 /* 764 * Bias helpers 765 */ 766 const struct pinmux_bias_reg * 767 rcar_pin_to_bias_reg(const struct sh_pfc_soc_info *info, unsigned int pin, 768 unsigned int *bit); 769 unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin); 770 void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, 771 unsigned int bias); 772 773 unsigned int rmobile_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin); 774 void rmobile_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, 775 unsigned int bias); 776 777 #endif /* __SH_PFC_H */ 778