1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SuperH Pin Function Controller pinmux support. 4 * 5 * Copyright (C) 2012 Paul Mundt 6 */ 7 8 #define DRV_NAME "sh-pfc" 9 10 #include <linux/device.h> 11 #include <linux/err.h> 12 #include <linux/io.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/seq_file.h> 16 #include <linux/slab.h> 17 #include <linux/spinlock.h> 18 19 #include <linux/pinctrl/consumer.h> 20 #include <linux/pinctrl/machine.h> 21 #include <linux/pinctrl/pinconf-generic.h> 22 #include <linux/pinctrl/pinconf.h> 23 #include <linux/pinctrl/pinctrl.h> 24 #include <linux/pinctrl/pinmux.h> 25 26 #include "core.h" 27 #include "../core.h" 28 #include "../pinconf.h" 29 30 struct sh_pfc_pin_config { 31 u16 gpio_enabled:1; 32 u16 mux_mark:15; 33 }; 34 35 struct sh_pfc_pinctrl { 36 struct pinctrl_dev *pctl; 37 struct pinctrl_desc pctl_desc; 38 39 struct sh_pfc *pfc; 40 41 struct pinctrl_pin_desc *pins; 42 struct sh_pfc_pin_config *configs; 43 44 const char *func_prop_name; 45 const char *groups_prop_name; 46 const char *pins_prop_name; 47 }; 48 49 static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev) 50 { 51 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 52 53 return pmx->pfc->info->nr_groups; 54 } 55 56 static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev, 57 unsigned selector) 58 { 59 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 60 61 return pmx->pfc->info->groups[selector].name; 62 } 63 64 static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, 65 const unsigned **pins, unsigned *num_pins) 66 { 67 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 68 69 *pins = pmx->pfc->info->groups[selector].pins; 70 *num_pins = pmx->pfc->info->groups[selector].nr_pins; 71 72 return 0; 73 } 74 75 static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 76 unsigned offset) 77 { 78 seq_puts(s, DRV_NAME); 79 } 80 81 #ifdef CONFIG_OF 82 static int sh_pfc_map_add_config(struct pinctrl_map *map, 83 const char *group_or_pin, 84 enum pinctrl_map_type type, 85 unsigned long *configs, 86 unsigned int num_configs) 87 { 88 unsigned long *cfgs; 89 90 cfgs = kmemdup(configs, num_configs * sizeof(*cfgs), 91 GFP_KERNEL); 92 if (cfgs == NULL) 93 return -ENOMEM; 94 95 map->type = type; 96 map->data.configs.group_or_pin = group_or_pin; 97 map->data.configs.configs = cfgs; 98 map->data.configs.num_configs = num_configs; 99 100 return 0; 101 } 102 103 static int sh_pfc_dt_subnode_to_map(struct pinctrl_dev *pctldev, 104 struct device_node *np, 105 struct pinctrl_map **map, 106 unsigned int *num_maps, unsigned int *index) 107 { 108 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 109 struct device *dev = pmx->pfc->dev; 110 struct pinctrl_map *maps = *map; 111 unsigned int nmaps = *num_maps; 112 unsigned int idx = *index; 113 unsigned int num_configs; 114 const char *function = NULL; 115 unsigned long *configs; 116 struct property *prop; 117 unsigned int num_groups; 118 unsigned int num_pins; 119 const char *group; 120 const char *pin; 121 int ret; 122 123 /* Support both the old Renesas-specific properties and the new standard 124 * properties. Mixing old and new properties isn't allowed, neither 125 * inside a subnode nor across subnodes. 126 */ 127 if (!pmx->func_prop_name) { 128 if (of_find_property(np, "groups", NULL) || 129 of_find_property(np, "pins", NULL)) { 130 pmx->func_prop_name = "function"; 131 pmx->groups_prop_name = "groups"; 132 pmx->pins_prop_name = "pins"; 133 } else { 134 pmx->func_prop_name = "renesas,function"; 135 pmx->groups_prop_name = "renesas,groups"; 136 pmx->pins_prop_name = "renesas,pins"; 137 } 138 } 139 140 /* Parse the function and configuration properties. At least a function 141 * or one configuration must be specified. 142 */ 143 ret = of_property_read_string(np, pmx->func_prop_name, &function); 144 if (ret < 0 && ret != -EINVAL) { 145 dev_err(dev, "Invalid function in DT\n"); 146 return ret; 147 } 148 149 ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs); 150 if (ret < 0) 151 return ret; 152 153 if (!function && num_configs == 0) { 154 dev_err(dev, 155 "DT node must contain at least a function or config\n"); 156 ret = -ENODEV; 157 goto done; 158 } 159 160 /* Count the number of pins and groups and reallocate mappings. */ 161 ret = of_property_count_strings(np, pmx->pins_prop_name); 162 if (ret == -EINVAL) { 163 num_pins = 0; 164 } else if (ret < 0) { 165 dev_err(dev, "Invalid pins list in DT\n"); 166 goto done; 167 } else { 168 num_pins = ret; 169 } 170 171 ret = of_property_count_strings(np, pmx->groups_prop_name); 172 if (ret == -EINVAL) { 173 num_groups = 0; 174 } else if (ret < 0) { 175 dev_err(dev, "Invalid pin groups list in DT\n"); 176 goto done; 177 } else { 178 num_groups = ret; 179 } 180 181 if (!num_pins && !num_groups) { 182 dev_err(dev, "No pin or group provided in DT node\n"); 183 ret = -ENODEV; 184 goto done; 185 } 186 187 if (function) 188 nmaps += num_groups; 189 if (configs) 190 nmaps += num_pins + num_groups; 191 192 maps = krealloc(maps, sizeof(*maps) * nmaps, GFP_KERNEL); 193 if (maps == NULL) { 194 ret = -ENOMEM; 195 goto done; 196 } 197 198 *map = maps; 199 *num_maps = nmaps; 200 201 /* Iterate over pins and groups and create the mappings. */ 202 of_property_for_each_string(np, pmx->groups_prop_name, prop, group) { 203 if (function) { 204 maps[idx].type = PIN_MAP_TYPE_MUX_GROUP; 205 maps[idx].data.mux.group = group; 206 maps[idx].data.mux.function = function; 207 idx++; 208 } 209 210 if (configs) { 211 ret = sh_pfc_map_add_config(&maps[idx], group, 212 PIN_MAP_TYPE_CONFIGS_GROUP, 213 configs, num_configs); 214 if (ret < 0) 215 goto done; 216 217 idx++; 218 } 219 } 220 221 if (!configs) { 222 ret = 0; 223 goto done; 224 } 225 226 of_property_for_each_string(np, pmx->pins_prop_name, prop, pin) { 227 ret = sh_pfc_map_add_config(&maps[idx], pin, 228 PIN_MAP_TYPE_CONFIGS_PIN, 229 configs, num_configs); 230 if (ret < 0) 231 goto done; 232 233 idx++; 234 } 235 236 done: 237 *index = idx; 238 kfree(configs); 239 return ret; 240 } 241 242 static void sh_pfc_dt_free_map(struct pinctrl_dev *pctldev, 243 struct pinctrl_map *map, unsigned num_maps) 244 { 245 unsigned int i; 246 247 if (map == NULL) 248 return; 249 250 for (i = 0; i < num_maps; ++i) { 251 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP || 252 map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) 253 kfree(map[i].data.configs.configs); 254 } 255 256 kfree(map); 257 } 258 259 static int sh_pfc_dt_node_to_map(struct pinctrl_dev *pctldev, 260 struct device_node *np, 261 struct pinctrl_map **map, unsigned *num_maps) 262 { 263 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 264 struct device *dev = pmx->pfc->dev; 265 struct device_node *child; 266 unsigned int index; 267 int ret; 268 269 *map = NULL; 270 *num_maps = 0; 271 index = 0; 272 273 for_each_child_of_node(np, child) { 274 ret = sh_pfc_dt_subnode_to_map(pctldev, child, map, num_maps, 275 &index); 276 if (ret < 0) { 277 of_node_put(child); 278 goto done; 279 } 280 } 281 282 /* If no mapping has been found in child nodes try the config node. */ 283 if (*num_maps == 0) { 284 ret = sh_pfc_dt_subnode_to_map(pctldev, np, map, num_maps, 285 &index); 286 if (ret < 0) 287 goto done; 288 } 289 290 if (*num_maps) 291 return 0; 292 293 dev_err(dev, "no mapping found in node %pOF\n", np); 294 ret = -EINVAL; 295 296 done: 297 if (ret < 0) 298 sh_pfc_dt_free_map(pctldev, *map, *num_maps); 299 300 return ret; 301 } 302 #endif /* CONFIG_OF */ 303 304 static const struct pinctrl_ops sh_pfc_pinctrl_ops = { 305 .get_groups_count = sh_pfc_get_groups_count, 306 .get_group_name = sh_pfc_get_group_name, 307 .get_group_pins = sh_pfc_get_group_pins, 308 .pin_dbg_show = sh_pfc_pin_dbg_show, 309 #ifdef CONFIG_OF 310 .dt_node_to_map = sh_pfc_dt_node_to_map, 311 .dt_free_map = sh_pfc_dt_free_map, 312 #endif 313 }; 314 315 static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev) 316 { 317 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 318 319 return pmx->pfc->info->nr_functions; 320 } 321 322 static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev, 323 unsigned selector) 324 { 325 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 326 327 return pmx->pfc->info->functions[selector].name; 328 } 329 330 static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev, 331 unsigned selector, 332 const char * const **groups, 333 unsigned * const num_groups) 334 { 335 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 336 337 *groups = pmx->pfc->info->functions[selector].groups; 338 *num_groups = pmx->pfc->info->functions[selector].nr_groups; 339 340 return 0; 341 } 342 343 static int sh_pfc_func_set_mux(struct pinctrl_dev *pctldev, unsigned selector, 344 unsigned group) 345 { 346 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 347 struct sh_pfc *pfc = pmx->pfc; 348 const struct sh_pfc_pin_group *grp = &pfc->info->groups[group]; 349 unsigned long flags; 350 unsigned int i; 351 int ret = 0; 352 353 dev_dbg(pctldev->dev, "Configuring pin group %s\n", grp->name); 354 355 spin_lock_irqsave(&pfc->lock, flags); 356 357 for (i = 0; i < grp->nr_pins; ++i) { 358 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]); 359 struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; 360 361 /* 362 * This driver cannot manage both gpio and mux when the gpio 363 * pin is already enabled. So, this function fails. 364 */ 365 if (cfg->gpio_enabled) { 366 ret = -EBUSY; 367 goto done; 368 } 369 370 ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION); 371 if (ret < 0) 372 goto done; 373 } 374 375 /* All group pins are configured, mark the pins as muxed */ 376 for (i = 0; i < grp->nr_pins; ++i) { 377 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]); 378 struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; 379 380 cfg->mux_mark = grp->mux[i]; 381 } 382 383 done: 384 spin_unlock_irqrestore(&pfc->lock, flags); 385 return ret; 386 } 387 388 static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev, 389 struct pinctrl_gpio_range *range, 390 unsigned offset) 391 { 392 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 393 struct sh_pfc *pfc = pmx->pfc; 394 int idx = sh_pfc_get_pin_index(pfc, offset); 395 struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; 396 unsigned long flags; 397 int ret; 398 399 spin_lock_irqsave(&pfc->lock, flags); 400 401 if (!pfc->gpio && !cfg->mux_mark) { 402 /* If GPIOs are handled externally the pin mux type needs to be 403 * set to GPIO here. 404 */ 405 const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; 406 407 ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO); 408 if (ret < 0) 409 goto done; 410 } 411 412 cfg->gpio_enabled = true; 413 414 ret = 0; 415 416 done: 417 spin_unlock_irqrestore(&pfc->lock, flags); 418 419 return ret; 420 } 421 422 static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev, 423 struct pinctrl_gpio_range *range, 424 unsigned offset) 425 { 426 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 427 struct sh_pfc *pfc = pmx->pfc; 428 int idx = sh_pfc_get_pin_index(pfc, offset); 429 struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; 430 unsigned long flags; 431 432 spin_lock_irqsave(&pfc->lock, flags); 433 cfg->gpio_enabled = false; 434 /* If mux is already set, this configures it here */ 435 if (cfg->mux_mark) 436 sh_pfc_config_mux(pfc, cfg->mux_mark, PINMUX_TYPE_FUNCTION); 437 spin_unlock_irqrestore(&pfc->lock, flags); 438 } 439 440 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO 441 static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev, 442 struct pinctrl_gpio_range *range, 443 unsigned offset, bool input) 444 { 445 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 446 struct sh_pfc *pfc = pmx->pfc; 447 int new_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT; 448 int idx = sh_pfc_get_pin_index(pfc, offset); 449 const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; 450 unsigned long flags; 451 unsigned int dir; 452 int ret; 453 454 /* Check if the requested direction is supported by the pin. Not all 455 * SoCs provide pin config data, so perform the check conditionally. 456 */ 457 if (pin->configs) { 458 dir = input ? SH_PFC_PIN_CFG_INPUT : SH_PFC_PIN_CFG_OUTPUT; 459 if (!(pin->configs & dir)) 460 return -EINVAL; 461 } 462 463 spin_lock_irqsave(&pfc->lock, flags); 464 ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type); 465 spin_unlock_irqrestore(&pfc->lock, flags); 466 return ret; 467 } 468 #else 469 #define sh_pfc_gpio_set_direction NULL 470 #endif 471 472 static const struct pinmux_ops sh_pfc_pinmux_ops = { 473 .get_functions_count = sh_pfc_get_functions_count, 474 .get_function_name = sh_pfc_get_function_name, 475 .get_function_groups = sh_pfc_get_function_groups, 476 .set_mux = sh_pfc_func_set_mux, 477 .gpio_request_enable = sh_pfc_gpio_request_enable, 478 .gpio_disable_free = sh_pfc_gpio_disable_free, 479 .gpio_set_direction = sh_pfc_gpio_set_direction, 480 }; 481 482 static u32 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc, 483 unsigned int pin, unsigned int *offset, unsigned int *size) 484 { 485 const struct pinmux_drive_reg_field *field; 486 const struct pinmux_drive_reg *reg; 487 unsigned int i; 488 489 for (reg = pfc->info->drive_regs; reg->reg; ++reg) { 490 for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) { 491 field = ®->fields[i]; 492 493 if (field->size && field->pin == pin) { 494 *offset = field->offset; 495 *size = field->size; 496 497 return reg->reg; 498 } 499 } 500 } 501 502 return 0; 503 } 504 505 static int sh_pfc_pinconf_get_drive_strength(struct sh_pfc *pfc, 506 unsigned int pin) 507 { 508 unsigned int offset; 509 unsigned int size; 510 u32 reg; 511 u32 val; 512 513 reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size); 514 if (!reg) 515 return -EINVAL; 516 517 val = (sh_pfc_read(pfc, reg) >> offset) & GENMASK(size - 1, 0); 518 519 /* Convert the value to mA based on a full drive strength value of 24mA. 520 * We can make the full value configurable later if needed. 521 */ 522 return (val + 1) * (size == 2 ? 6 : 3); 523 } 524 525 static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc, 526 unsigned int pin, u16 strength) 527 { 528 unsigned long flags; 529 unsigned int offset; 530 unsigned int size; 531 unsigned int step; 532 u32 reg; 533 u32 val; 534 535 reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size); 536 if (!reg) 537 return -EINVAL; 538 539 step = size == 2 ? 6 : 3; 540 541 if (strength < step || strength > 24) 542 return -EINVAL; 543 544 /* Convert the value from mA based on a full drive strength value of 545 * 24mA. We can make the full value configurable later if needed. 546 */ 547 strength = strength / step - 1; 548 549 spin_lock_irqsave(&pfc->lock, flags); 550 551 val = sh_pfc_read(pfc, reg); 552 val &= ~GENMASK(offset + size - 1, offset); 553 val |= strength << offset; 554 555 sh_pfc_write(pfc, reg, val); 556 557 spin_unlock_irqrestore(&pfc->lock, flags); 558 559 return 0; 560 } 561 562 /* Check whether the requested parameter is supported for a pin. */ 563 static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin, 564 enum pin_config_param param) 565 { 566 int idx = sh_pfc_get_pin_index(pfc, _pin); 567 const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; 568 569 switch (param) { 570 case PIN_CONFIG_BIAS_DISABLE: 571 return pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN; 572 573 case PIN_CONFIG_BIAS_PULL_UP: 574 return pin->configs & SH_PFC_PIN_CFG_PULL_UP; 575 576 case PIN_CONFIG_BIAS_PULL_DOWN: 577 return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN; 578 579 case PIN_CONFIG_DRIVE_STRENGTH: 580 return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH; 581 582 case PIN_CONFIG_POWER_SOURCE: 583 return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE; 584 585 default: 586 return false; 587 } 588 } 589 590 static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin, 591 unsigned long *config) 592 { 593 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 594 struct sh_pfc *pfc = pmx->pfc; 595 enum pin_config_param param = pinconf_to_config_param(*config); 596 unsigned long flags; 597 unsigned int arg; 598 599 if (!sh_pfc_pinconf_validate(pfc, _pin, param)) 600 return -ENOTSUPP; 601 602 switch (param) { 603 case PIN_CONFIG_BIAS_DISABLE: 604 case PIN_CONFIG_BIAS_PULL_UP: 605 case PIN_CONFIG_BIAS_PULL_DOWN: { 606 unsigned int bias; 607 608 if (!pfc->info->ops || !pfc->info->ops->get_bias) 609 return -ENOTSUPP; 610 611 spin_lock_irqsave(&pfc->lock, flags); 612 bias = pfc->info->ops->get_bias(pfc, _pin); 613 spin_unlock_irqrestore(&pfc->lock, flags); 614 615 if (bias != param) 616 return -EINVAL; 617 618 arg = 0; 619 break; 620 } 621 622 case PIN_CONFIG_DRIVE_STRENGTH: { 623 int ret; 624 625 ret = sh_pfc_pinconf_get_drive_strength(pfc, _pin); 626 if (ret < 0) 627 return ret; 628 629 arg = ret; 630 break; 631 } 632 633 case PIN_CONFIG_POWER_SOURCE: { 634 int idx = sh_pfc_get_pin_index(pfc, _pin); 635 const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; 636 unsigned int lower_voltage; 637 u32 pocctrl, val; 638 int bit; 639 640 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl) 641 return -ENOTSUPP; 642 643 bit = pfc->info->ops->pin_to_pocctrl(_pin, &pocctrl); 644 if (WARN(bit < 0, "invalid pin %#x", _pin)) 645 return bit; 646 647 val = sh_pfc_read(pfc, pocctrl); 648 649 lower_voltage = (pin->configs & SH_PFC_PIN_VOLTAGE_25_33) ? 650 2500 : 1800; 651 652 arg = (val & BIT(bit)) ? 3300 : lower_voltage; 653 break; 654 } 655 656 default: 657 return -ENOTSUPP; 658 } 659 660 *config = pinconf_to_config_packed(param, arg); 661 return 0; 662 } 663 664 static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin, 665 unsigned long *configs, unsigned num_configs) 666 { 667 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 668 struct sh_pfc *pfc = pmx->pfc; 669 enum pin_config_param param; 670 unsigned long flags; 671 unsigned int i; 672 673 for (i = 0; i < num_configs; i++) { 674 param = pinconf_to_config_param(configs[i]); 675 676 if (!sh_pfc_pinconf_validate(pfc, _pin, param)) 677 return -ENOTSUPP; 678 679 switch (param) { 680 case PIN_CONFIG_BIAS_PULL_UP: 681 case PIN_CONFIG_BIAS_PULL_DOWN: 682 case PIN_CONFIG_BIAS_DISABLE: 683 if (!pfc->info->ops || !pfc->info->ops->set_bias) 684 return -ENOTSUPP; 685 686 spin_lock_irqsave(&pfc->lock, flags); 687 pfc->info->ops->set_bias(pfc, _pin, param); 688 spin_unlock_irqrestore(&pfc->lock, flags); 689 690 break; 691 692 case PIN_CONFIG_DRIVE_STRENGTH: { 693 unsigned int arg = 694 pinconf_to_config_argument(configs[i]); 695 int ret; 696 697 ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg); 698 if (ret < 0) 699 return ret; 700 701 break; 702 } 703 704 case PIN_CONFIG_POWER_SOURCE: { 705 unsigned int mV = pinconf_to_config_argument(configs[i]); 706 int idx = sh_pfc_get_pin_index(pfc, _pin); 707 const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; 708 unsigned int lower_voltage; 709 u32 pocctrl, val; 710 int bit; 711 712 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl) 713 return -ENOTSUPP; 714 715 bit = pfc->info->ops->pin_to_pocctrl(_pin, &pocctrl); 716 if (WARN(bit < 0, "invalid pin %#x", _pin)) 717 return bit; 718 719 lower_voltage = (pin->configs & SH_PFC_PIN_VOLTAGE_25_33) ? 720 2500 : 1800; 721 722 if (mV != lower_voltage && mV != 3300) 723 return -EINVAL; 724 725 spin_lock_irqsave(&pfc->lock, flags); 726 val = sh_pfc_read(pfc, pocctrl); 727 if (mV == 3300) 728 val |= BIT(bit); 729 else 730 val &= ~BIT(bit); 731 sh_pfc_write(pfc, pocctrl, val); 732 spin_unlock_irqrestore(&pfc->lock, flags); 733 734 break; 735 } 736 737 default: 738 return -ENOTSUPP; 739 } 740 } /* for each config */ 741 742 return 0; 743 } 744 745 static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group, 746 unsigned long *configs, 747 unsigned num_configs) 748 { 749 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 750 const unsigned int *pins; 751 unsigned int num_pins; 752 unsigned int i, ret; 753 754 pins = pmx->pfc->info->groups[group].pins; 755 num_pins = pmx->pfc->info->groups[group].nr_pins; 756 757 for (i = 0; i < num_pins; ++i) { 758 ret = sh_pfc_pinconf_set(pctldev, pins[i], configs, num_configs); 759 if (ret) 760 return ret; 761 } 762 763 return 0; 764 } 765 766 static const struct pinconf_ops sh_pfc_pinconf_ops = { 767 .is_generic = true, 768 .pin_config_get = sh_pfc_pinconf_get, 769 .pin_config_set = sh_pfc_pinconf_set, 770 .pin_config_group_set = sh_pfc_pinconf_group_set, 771 .pin_config_config_dbg_show = pinconf_generic_dump_config, 772 }; 773 774 /* PFC ranges -> pinctrl pin descs */ 775 static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) 776 { 777 unsigned int i; 778 779 /* Allocate and initialize the pins and configs arrays. */ 780 pmx->pins = devm_kcalloc(pfc->dev, 781 pfc->info->nr_pins, sizeof(*pmx->pins), 782 GFP_KERNEL); 783 if (unlikely(!pmx->pins)) 784 return -ENOMEM; 785 786 pmx->configs = devm_kcalloc(pfc->dev, 787 pfc->info->nr_pins, sizeof(*pmx->configs), 788 GFP_KERNEL); 789 if (unlikely(!pmx->configs)) 790 return -ENOMEM; 791 792 for (i = 0; i < pfc->info->nr_pins; ++i) { 793 const struct sh_pfc_pin *info = &pfc->info->pins[i]; 794 struct pinctrl_pin_desc *pin = &pmx->pins[i]; 795 796 /* If the pin number is equal to -1 all pins are considered */ 797 pin->number = info->pin != (u16)-1 ? info->pin : i; 798 pin->name = info->name; 799 } 800 801 return 0; 802 } 803 804 int sh_pfc_register_pinctrl(struct sh_pfc *pfc) 805 { 806 struct sh_pfc_pinctrl *pmx; 807 int ret; 808 809 pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL); 810 if (unlikely(!pmx)) 811 return -ENOMEM; 812 813 pmx->pfc = pfc; 814 815 ret = sh_pfc_map_pins(pfc, pmx); 816 if (ret < 0) 817 return ret; 818 819 pmx->pctl_desc.name = DRV_NAME; 820 pmx->pctl_desc.owner = THIS_MODULE; 821 pmx->pctl_desc.pctlops = &sh_pfc_pinctrl_ops; 822 pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops; 823 pmx->pctl_desc.confops = &sh_pfc_pinconf_ops; 824 pmx->pctl_desc.pins = pmx->pins; 825 pmx->pctl_desc.npins = pfc->info->nr_pins; 826 827 ret = devm_pinctrl_register_and_init(pfc->dev, &pmx->pctl_desc, pmx, 828 &pmx->pctl); 829 if (ret) { 830 dev_err(pfc->dev, "could not register: %i\n", ret); 831 832 return ret; 833 } 834 835 return pinctrl_enable(pmx->pctl); 836 } 837 838 const struct pinmux_bias_reg * 839 rcar_pin_to_bias_reg(const struct sh_pfc_soc_info *info, unsigned int pin, 840 unsigned int *bit) 841 { 842 unsigned int i, j; 843 844 for (i = 0; info->bias_regs[i].puen || info->bias_regs[i].pud; i++) { 845 for (j = 0; j < ARRAY_SIZE(info->bias_regs[i].pins); j++) { 846 if (info->bias_regs[i].pins[j] == pin) { 847 *bit = j; 848 return &info->bias_regs[i]; 849 } 850 } 851 } 852 853 WARN_ONCE(1, "Pin %u is not in bias info list\n", pin); 854 855 return NULL; 856 } 857 858 unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) 859 { 860 const struct pinmux_bias_reg *reg; 861 unsigned int bit; 862 863 reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit); 864 if (!reg) 865 return PIN_CONFIG_BIAS_DISABLE; 866 867 if (reg->puen) { 868 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) 869 return PIN_CONFIG_BIAS_DISABLE; 870 else if (!reg->pud || (sh_pfc_read(pfc, reg->pud) & BIT(bit))) 871 return PIN_CONFIG_BIAS_PULL_UP; 872 else 873 return PIN_CONFIG_BIAS_PULL_DOWN; 874 } else { 875 if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) 876 return PIN_CONFIG_BIAS_PULL_DOWN; 877 else 878 return PIN_CONFIG_BIAS_DISABLE; 879 } 880 } 881 882 void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, 883 unsigned int bias) 884 { 885 const struct pinmux_bias_reg *reg; 886 u32 enable, updown; 887 unsigned int bit; 888 889 reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit); 890 if (!reg) 891 return; 892 893 if (reg->puen) { 894 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); 895 if (bias != PIN_CONFIG_BIAS_DISABLE) { 896 enable |= BIT(bit); 897 898 if (reg->pud) { 899 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); 900 if (bias == PIN_CONFIG_BIAS_PULL_UP) 901 updown |= BIT(bit); 902 903 sh_pfc_write(pfc, reg->pud, updown); 904 } 905 } 906 sh_pfc_write(pfc, reg->puen, enable); 907 } else { 908 enable = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); 909 if (bias == PIN_CONFIG_BIAS_PULL_DOWN) 910 enable |= BIT(bit); 911 912 sh_pfc_write(pfc, reg->pud, enable); 913 } 914 } 915 916 #define PORTnCR_PULMD_OFF (0 << 6) 917 #define PORTnCR_PULMD_DOWN (2 << 6) 918 #define PORTnCR_PULMD_UP (3 << 6) 919 #define PORTnCR_PULMD_MASK (3 << 6) 920 921 unsigned int rmobile_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) 922 { 923 void __iomem *reg = pfc->windows->virt + 924 pfc->info->ops->pin_to_portcr(pin); 925 u32 value = ioread8(reg) & PORTnCR_PULMD_MASK; 926 927 switch (value) { 928 case PORTnCR_PULMD_UP: 929 return PIN_CONFIG_BIAS_PULL_UP; 930 case PORTnCR_PULMD_DOWN: 931 return PIN_CONFIG_BIAS_PULL_DOWN; 932 case PORTnCR_PULMD_OFF: 933 default: 934 return PIN_CONFIG_BIAS_DISABLE; 935 } 936 } 937 938 void rmobile_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, 939 unsigned int bias) 940 { 941 void __iomem *reg = pfc->windows->virt + 942 pfc->info->ops->pin_to_portcr(pin); 943 u32 value = ioread8(reg) & ~PORTnCR_PULMD_MASK; 944 945 switch (bias) { 946 case PIN_CONFIG_BIAS_PULL_UP: 947 value |= PORTnCR_PULMD_UP; 948 break; 949 case PIN_CONFIG_BIAS_PULL_DOWN: 950 value |= PORTnCR_PULMD_DOWN; 951 break; 952 } 953 954 iowrite8(value, reg); 955 } 956