1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * SuperH Pin Function Controller pinmux support.
4  *
5  * Copyright (C) 2012  Paul Mundt
6  */
7 
8 #define DRV_NAME "sh-pfc"
9 
10 #include <linux/device.h>
11 #include <linux/err.h>
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/pinctrl/consumer.h>
16 #include <linux/pinctrl/machine.h>
17 #include <linux/pinctrl/pinconf.h>
18 #include <linux/pinctrl/pinconf-generic.h>
19 #include <linux/pinctrl/pinctrl.h>
20 #include <linux/pinctrl/pinmux.h>
21 #include <linux/slab.h>
22 #include <linux/spinlock.h>
23 
24 #include "core.h"
25 #include "../core.h"
26 #include "../pinconf.h"
27 
28 struct sh_pfc_pin_config {
29 	u16 gpio_enabled:1;
30 	u16 mux_mark:15;
31 };
32 
33 struct sh_pfc_pinctrl {
34 	struct pinctrl_dev *pctl;
35 	struct pinctrl_desc pctl_desc;
36 
37 	struct sh_pfc *pfc;
38 
39 	struct pinctrl_pin_desc *pins;
40 	struct sh_pfc_pin_config *configs;
41 
42 	const char *func_prop_name;
43 	const char *groups_prop_name;
44 	const char *pins_prop_name;
45 };
46 
47 static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev)
48 {
49 	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
50 
51 	return pmx->pfc->info->nr_groups;
52 }
53 
54 static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev,
55 					 unsigned selector)
56 {
57 	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
58 
59 	return pmx->pfc->info->groups[selector].name;
60 }
61 
62 static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
63 				 const unsigned **pins, unsigned *num_pins)
64 {
65 	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
66 
67 	*pins = pmx->pfc->info->groups[selector].pins;
68 	*num_pins = pmx->pfc->info->groups[selector].nr_pins;
69 
70 	return 0;
71 }
72 
73 static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
74 				unsigned offset)
75 {
76 	seq_puts(s, DRV_NAME);
77 }
78 
79 #ifdef CONFIG_OF
80 static int sh_pfc_map_add_config(struct pinctrl_map *map,
81 				 const char *group_or_pin,
82 				 enum pinctrl_map_type type,
83 				 unsigned long *configs,
84 				 unsigned int num_configs)
85 {
86 	unsigned long *cfgs;
87 
88 	cfgs = kmemdup(configs, num_configs * sizeof(*cfgs),
89 		       GFP_KERNEL);
90 	if (cfgs == NULL)
91 		return -ENOMEM;
92 
93 	map->type = type;
94 	map->data.configs.group_or_pin = group_or_pin;
95 	map->data.configs.configs = cfgs;
96 	map->data.configs.num_configs = num_configs;
97 
98 	return 0;
99 }
100 
101 static int sh_pfc_dt_subnode_to_map(struct pinctrl_dev *pctldev,
102 				    struct device_node *np,
103 				    struct pinctrl_map **map,
104 				    unsigned int *num_maps, unsigned int *index)
105 {
106 	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
107 	struct device *dev = pmx->pfc->dev;
108 	struct pinctrl_map *maps = *map;
109 	unsigned int nmaps = *num_maps;
110 	unsigned int idx = *index;
111 	unsigned int num_configs;
112 	const char *function = NULL;
113 	unsigned long *configs;
114 	struct property *prop;
115 	unsigned int num_groups;
116 	unsigned int num_pins;
117 	const char *group;
118 	const char *pin;
119 	int ret;
120 
121 	/* Support both the old Renesas-specific properties and the new standard
122 	 * properties. Mixing old and new properties isn't allowed, neither
123 	 * inside a subnode nor across subnodes.
124 	 */
125 	if (!pmx->func_prop_name) {
126 		if (of_find_property(np, "groups", NULL) ||
127 		    of_find_property(np, "pins", NULL)) {
128 			pmx->func_prop_name = "function";
129 			pmx->groups_prop_name = "groups";
130 			pmx->pins_prop_name = "pins";
131 		} else {
132 			pmx->func_prop_name = "renesas,function";
133 			pmx->groups_prop_name = "renesas,groups";
134 			pmx->pins_prop_name = "renesas,pins";
135 		}
136 	}
137 
138 	/* Parse the function and configuration properties. At least a function
139 	 * or one configuration must be specified.
140 	 */
141 	ret = of_property_read_string(np, pmx->func_prop_name, &function);
142 	if (ret < 0 && ret != -EINVAL) {
143 		dev_err(dev, "Invalid function in DT\n");
144 		return ret;
145 	}
146 
147 	ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs);
148 	if (ret < 0)
149 		return ret;
150 
151 	if (!function && num_configs == 0) {
152 		dev_err(dev,
153 			"DT node must contain at least a function or config\n");
154 		ret = -ENODEV;
155 		goto done;
156 	}
157 
158 	/* Count the number of pins and groups and reallocate mappings. */
159 	ret = of_property_count_strings(np, pmx->pins_prop_name);
160 	if (ret == -EINVAL) {
161 		num_pins = 0;
162 	} else if (ret < 0) {
163 		dev_err(dev, "Invalid pins list in DT\n");
164 		goto done;
165 	} else {
166 		num_pins = ret;
167 	}
168 
169 	ret = of_property_count_strings(np, pmx->groups_prop_name);
170 	if (ret == -EINVAL) {
171 		num_groups = 0;
172 	} else if (ret < 0) {
173 		dev_err(dev, "Invalid pin groups list in DT\n");
174 		goto done;
175 	} else {
176 		num_groups = ret;
177 	}
178 
179 	if (!num_pins && !num_groups) {
180 		dev_err(dev, "No pin or group provided in DT node\n");
181 		ret = -ENODEV;
182 		goto done;
183 	}
184 
185 	if (function)
186 		nmaps += num_groups;
187 	if (configs)
188 		nmaps += num_pins + num_groups;
189 
190 	maps = krealloc(maps, sizeof(*maps) * nmaps, GFP_KERNEL);
191 	if (maps == NULL) {
192 		ret = -ENOMEM;
193 		goto done;
194 	}
195 
196 	*map = maps;
197 	*num_maps = nmaps;
198 
199 	/* Iterate over pins and groups and create the mappings. */
200 	of_property_for_each_string(np, pmx->groups_prop_name, prop, group) {
201 		if (function) {
202 			maps[idx].type = PIN_MAP_TYPE_MUX_GROUP;
203 			maps[idx].data.mux.group = group;
204 			maps[idx].data.mux.function = function;
205 			idx++;
206 		}
207 
208 		if (configs) {
209 			ret = sh_pfc_map_add_config(&maps[idx], group,
210 						    PIN_MAP_TYPE_CONFIGS_GROUP,
211 						    configs, num_configs);
212 			if (ret < 0)
213 				goto done;
214 
215 			idx++;
216 		}
217 	}
218 
219 	if (!configs) {
220 		ret = 0;
221 		goto done;
222 	}
223 
224 	of_property_for_each_string(np, pmx->pins_prop_name, prop, pin) {
225 		ret = sh_pfc_map_add_config(&maps[idx], pin,
226 					    PIN_MAP_TYPE_CONFIGS_PIN,
227 					    configs, num_configs);
228 		if (ret < 0)
229 			goto done;
230 
231 		idx++;
232 	}
233 
234 done:
235 	*index = idx;
236 	kfree(configs);
237 	return ret;
238 }
239 
240 static void sh_pfc_dt_free_map(struct pinctrl_dev *pctldev,
241 			       struct pinctrl_map *map, unsigned num_maps)
242 {
243 	unsigned int i;
244 
245 	if (map == NULL)
246 		return;
247 
248 	for (i = 0; i < num_maps; ++i) {
249 		if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP ||
250 		    map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
251 			kfree(map[i].data.configs.configs);
252 	}
253 
254 	kfree(map);
255 }
256 
257 static int sh_pfc_dt_node_to_map(struct pinctrl_dev *pctldev,
258 				 struct device_node *np,
259 				 struct pinctrl_map **map, unsigned *num_maps)
260 {
261 	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
262 	struct device *dev = pmx->pfc->dev;
263 	struct device_node *child;
264 	unsigned int index;
265 	int ret;
266 
267 	*map = NULL;
268 	*num_maps = 0;
269 	index = 0;
270 
271 	for_each_child_of_node(np, child) {
272 		ret = sh_pfc_dt_subnode_to_map(pctldev, child, map, num_maps,
273 					       &index);
274 		if (ret < 0) {
275 			of_node_put(child);
276 			goto done;
277 		}
278 	}
279 
280 	/* If no mapping has been found in child nodes try the config node. */
281 	if (*num_maps == 0) {
282 		ret = sh_pfc_dt_subnode_to_map(pctldev, np, map, num_maps,
283 					       &index);
284 		if (ret < 0)
285 			goto done;
286 	}
287 
288 	if (*num_maps)
289 		return 0;
290 
291 	dev_err(dev, "no mapping found in node %pOF\n", np);
292 	ret = -EINVAL;
293 
294 done:
295 	if (ret < 0)
296 		sh_pfc_dt_free_map(pctldev, *map, *num_maps);
297 
298 	return ret;
299 }
300 #endif /* CONFIG_OF */
301 
302 static const struct pinctrl_ops sh_pfc_pinctrl_ops = {
303 	.get_groups_count	= sh_pfc_get_groups_count,
304 	.get_group_name		= sh_pfc_get_group_name,
305 	.get_group_pins		= sh_pfc_get_group_pins,
306 	.pin_dbg_show		= sh_pfc_pin_dbg_show,
307 #ifdef CONFIG_OF
308 	.dt_node_to_map		= sh_pfc_dt_node_to_map,
309 	.dt_free_map		= sh_pfc_dt_free_map,
310 #endif
311 };
312 
313 static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev)
314 {
315 	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
316 
317 	return pmx->pfc->info->nr_functions;
318 }
319 
320 static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev,
321 					    unsigned selector)
322 {
323 	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
324 
325 	return pmx->pfc->info->functions[selector].name;
326 }
327 
328 static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev,
329 				      unsigned selector,
330 				      const char * const **groups,
331 				      unsigned * const num_groups)
332 {
333 	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
334 
335 	*groups = pmx->pfc->info->functions[selector].groups;
336 	*num_groups = pmx->pfc->info->functions[selector].nr_groups;
337 
338 	return 0;
339 }
340 
341 static int sh_pfc_func_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
342 			       unsigned group)
343 {
344 	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
345 	struct sh_pfc *pfc = pmx->pfc;
346 	const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
347 	unsigned long flags;
348 	unsigned int i;
349 	int ret = 0;
350 
351 	dev_dbg(pctldev->dev, "Configuring pin group %s\n", grp->name);
352 
353 	spin_lock_irqsave(&pfc->lock, flags);
354 
355 	for (i = 0; i < grp->nr_pins; ++i) {
356 		int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
357 		struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
358 
359 		/*
360 		 * This driver cannot manage both gpio and mux when the gpio
361 		 * pin is already enabled. So, this function fails.
362 		 */
363 		if (cfg->gpio_enabled) {
364 			ret = -EBUSY;
365 			goto done;
366 		}
367 
368 		ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
369 		if (ret < 0)
370 			goto done;
371 	}
372 
373 	/* All group pins are configured, mark the pins as muxed */
374 	for (i = 0; i < grp->nr_pins; ++i) {
375 		int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
376 		struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
377 
378 		cfg->mux_mark = grp->mux[i];
379 	}
380 
381 done:
382 	spin_unlock_irqrestore(&pfc->lock, flags);
383 	return ret;
384 }
385 
386 static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
387 				      struct pinctrl_gpio_range *range,
388 				      unsigned offset)
389 {
390 	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
391 	struct sh_pfc *pfc = pmx->pfc;
392 	int idx = sh_pfc_get_pin_index(pfc, offset);
393 	struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
394 	unsigned long flags;
395 	int ret;
396 
397 	spin_lock_irqsave(&pfc->lock, flags);
398 
399 	if (!pfc->gpio) {
400 		/* If GPIOs are handled externally the pin mux type needs to be
401 		 * set to GPIO here.
402 		 */
403 		const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
404 
405 		ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
406 		if (ret < 0)
407 			goto done;
408 	}
409 
410 	cfg->gpio_enabled = true;
411 
412 	ret = 0;
413 
414 done:
415 	spin_unlock_irqrestore(&pfc->lock, flags);
416 
417 	return ret;
418 }
419 
420 static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
421 				     struct pinctrl_gpio_range *range,
422 				     unsigned offset)
423 {
424 	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
425 	struct sh_pfc *pfc = pmx->pfc;
426 	int idx = sh_pfc_get_pin_index(pfc, offset);
427 	struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
428 	unsigned long flags;
429 
430 	spin_lock_irqsave(&pfc->lock, flags);
431 	cfg->gpio_enabled = false;
432 	/* If mux is already set, this configures it here */
433 	if (cfg->mux_mark)
434 		sh_pfc_config_mux(pfc, cfg->mux_mark, PINMUX_TYPE_FUNCTION);
435 	spin_unlock_irqrestore(&pfc->lock, flags);
436 }
437 
438 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO
439 static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
440 				     struct pinctrl_gpio_range *range,
441 				     unsigned offset, bool input)
442 {
443 	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
444 	struct sh_pfc *pfc = pmx->pfc;
445 	int new_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;
446 	int idx = sh_pfc_get_pin_index(pfc, offset);
447 	const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
448 	unsigned long flags;
449 	unsigned int dir;
450 	int ret;
451 
452 	/* Check if the requested direction is supported by the pin. Not all
453 	 * SoCs provide pin config data, so perform the check conditionally.
454 	 */
455 	if (pin->configs) {
456 		dir = input ? SH_PFC_PIN_CFG_INPUT : SH_PFC_PIN_CFG_OUTPUT;
457 		if (!(pin->configs & dir))
458 			return -EINVAL;
459 	}
460 
461 	spin_lock_irqsave(&pfc->lock, flags);
462 	ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type);
463 	spin_unlock_irqrestore(&pfc->lock, flags);
464 	return ret;
465 }
466 #else
467 #define sh_pfc_gpio_set_direction	NULL
468 #endif
469 
470 static const struct pinmux_ops sh_pfc_pinmux_ops = {
471 	.get_functions_count	= sh_pfc_get_functions_count,
472 	.get_function_name	= sh_pfc_get_function_name,
473 	.get_function_groups	= sh_pfc_get_function_groups,
474 	.set_mux		= sh_pfc_func_set_mux,
475 	.gpio_request_enable	= sh_pfc_gpio_request_enable,
476 	.gpio_disable_free	= sh_pfc_gpio_disable_free,
477 	.gpio_set_direction	= sh_pfc_gpio_set_direction,
478 };
479 
480 static u32 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc,
481 		unsigned int pin, unsigned int *offset, unsigned int *size)
482 {
483 	const struct pinmux_drive_reg_field *field;
484 	const struct pinmux_drive_reg *reg;
485 	unsigned int i;
486 
487 	for (reg = pfc->info->drive_regs; reg->reg; ++reg) {
488 		for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) {
489 			field = &reg->fields[i];
490 
491 			if (field->size && field->pin == pin) {
492 				*offset = field->offset;
493 				*size = field->size;
494 
495 				return reg->reg;
496 			}
497 		}
498 	}
499 
500 	return 0;
501 }
502 
503 static int sh_pfc_pinconf_get_drive_strength(struct sh_pfc *pfc,
504 					     unsigned int pin)
505 {
506 	unsigned long flags;
507 	unsigned int offset;
508 	unsigned int size;
509 	u32 reg;
510 	u32 val;
511 
512 	reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
513 	if (!reg)
514 		return -EINVAL;
515 
516 	spin_lock_irqsave(&pfc->lock, flags);
517 	val = sh_pfc_read(pfc, reg);
518 	spin_unlock_irqrestore(&pfc->lock, flags);
519 
520 	val = (val >> offset) & GENMASK(size - 1, 0);
521 
522 	/* Convert the value to mA based on a full drive strength value of 24mA.
523 	 * We can make the full value configurable later if needed.
524 	 */
525 	return (val + 1) * (size == 2 ? 6 : 3);
526 }
527 
528 static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
529 					     unsigned int pin, u16 strength)
530 {
531 	unsigned long flags;
532 	unsigned int offset;
533 	unsigned int size;
534 	unsigned int step;
535 	u32 reg;
536 	u32 val;
537 
538 	reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
539 	if (!reg)
540 		return -EINVAL;
541 
542 	step = size == 2 ? 6 : 3;
543 
544 	if (strength < step || strength > 24)
545 		return -EINVAL;
546 
547 	/* Convert the value from mA based on a full drive strength value of
548 	 * 24mA. We can make the full value configurable later if needed.
549 	 */
550 	strength = strength / step - 1;
551 
552 	spin_lock_irqsave(&pfc->lock, flags);
553 
554 	val = sh_pfc_read(pfc, reg);
555 	val &= ~GENMASK(offset + size - 1, offset);
556 	val |= strength << offset;
557 
558 	sh_pfc_write(pfc, reg, val);
559 
560 	spin_unlock_irqrestore(&pfc->lock, flags);
561 
562 	return 0;
563 }
564 
565 /* Check whether the requested parameter is supported for a pin. */
566 static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
567 				    enum pin_config_param param)
568 {
569 	int idx = sh_pfc_get_pin_index(pfc, _pin);
570 	const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
571 
572 	switch (param) {
573 	case PIN_CONFIG_BIAS_DISABLE:
574 		return pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN;
575 
576 	case PIN_CONFIG_BIAS_PULL_UP:
577 		return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
578 
579 	case PIN_CONFIG_BIAS_PULL_DOWN:
580 		return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
581 
582 	case PIN_CONFIG_DRIVE_STRENGTH:
583 		return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH;
584 
585 	case PIN_CONFIG_POWER_SOURCE:
586 		return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
587 
588 	default:
589 		return false;
590 	}
591 }
592 
593 static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
594 			      unsigned long *config)
595 {
596 	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
597 	struct sh_pfc *pfc = pmx->pfc;
598 	enum pin_config_param param = pinconf_to_config_param(*config);
599 	unsigned long flags;
600 	unsigned int arg;
601 
602 	if (!sh_pfc_pinconf_validate(pfc, _pin, param))
603 		return -ENOTSUPP;
604 
605 	switch (param) {
606 	case PIN_CONFIG_BIAS_DISABLE:
607 	case PIN_CONFIG_BIAS_PULL_UP:
608 	case PIN_CONFIG_BIAS_PULL_DOWN: {
609 		unsigned int bias;
610 
611 		if (!pfc->info->ops || !pfc->info->ops->get_bias)
612 			return -ENOTSUPP;
613 
614 		spin_lock_irqsave(&pfc->lock, flags);
615 		bias = pfc->info->ops->get_bias(pfc, _pin);
616 		spin_unlock_irqrestore(&pfc->lock, flags);
617 
618 		if (bias != param)
619 			return -EINVAL;
620 
621 		arg = 0;
622 		break;
623 	}
624 
625 	case PIN_CONFIG_DRIVE_STRENGTH: {
626 		int ret;
627 
628 		ret = sh_pfc_pinconf_get_drive_strength(pfc, _pin);
629 		if (ret < 0)
630 			return ret;
631 
632 		arg = ret;
633 		break;
634 	}
635 
636 	case PIN_CONFIG_POWER_SOURCE: {
637 		int idx = sh_pfc_get_pin_index(pfc, _pin);
638 		const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
639 		unsigned int lower_voltage;
640 		u32 pocctrl, val;
641 		int bit;
642 
643 		if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
644 			return -ENOTSUPP;
645 
646 		bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &pocctrl);
647 		if (WARN(bit < 0, "invalid pin %#x", _pin))
648 			return bit;
649 
650 		spin_lock_irqsave(&pfc->lock, flags);
651 		val = sh_pfc_read(pfc, pocctrl);
652 		spin_unlock_irqrestore(&pfc->lock, flags);
653 
654 		lower_voltage = (pin->configs & SH_PFC_PIN_VOLTAGE_25_33) ?
655 			2500 : 1800;
656 
657 		arg = (val & BIT(bit)) ? 3300 : lower_voltage;
658 		break;
659 	}
660 
661 	default:
662 		return -ENOTSUPP;
663 	}
664 
665 	*config = pinconf_to_config_packed(param, arg);
666 	return 0;
667 }
668 
669 static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
670 			      unsigned long *configs, unsigned num_configs)
671 {
672 	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
673 	struct sh_pfc *pfc = pmx->pfc;
674 	enum pin_config_param param;
675 	unsigned long flags;
676 	unsigned int i;
677 
678 	for (i = 0; i < num_configs; i++) {
679 		param = pinconf_to_config_param(configs[i]);
680 
681 		if (!sh_pfc_pinconf_validate(pfc, _pin, param))
682 			return -ENOTSUPP;
683 
684 		switch (param) {
685 		case PIN_CONFIG_BIAS_PULL_UP:
686 		case PIN_CONFIG_BIAS_PULL_DOWN:
687 		case PIN_CONFIG_BIAS_DISABLE:
688 			if (!pfc->info->ops || !pfc->info->ops->set_bias)
689 				return -ENOTSUPP;
690 
691 			spin_lock_irqsave(&pfc->lock, flags);
692 			pfc->info->ops->set_bias(pfc, _pin, param);
693 			spin_unlock_irqrestore(&pfc->lock, flags);
694 
695 			break;
696 
697 		case PIN_CONFIG_DRIVE_STRENGTH: {
698 			unsigned int arg =
699 				pinconf_to_config_argument(configs[i]);
700 			int ret;
701 
702 			ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg);
703 			if (ret < 0)
704 				return ret;
705 
706 			break;
707 		}
708 
709 		case PIN_CONFIG_POWER_SOURCE: {
710 			unsigned int mV = pinconf_to_config_argument(configs[i]);
711 			int idx = sh_pfc_get_pin_index(pfc, _pin);
712 			const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
713 			unsigned int lower_voltage;
714 			u32 pocctrl, val;
715 			int bit;
716 
717 			if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
718 				return -ENOTSUPP;
719 
720 			bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &pocctrl);
721 			if (WARN(bit < 0, "invalid pin %#x", _pin))
722 				return bit;
723 
724 			lower_voltage = (pin->configs & SH_PFC_PIN_VOLTAGE_25_33) ?
725 				2500 : 1800;
726 
727 			if (mV != lower_voltage && mV != 3300)
728 				return -EINVAL;
729 
730 			spin_lock_irqsave(&pfc->lock, flags);
731 			val = sh_pfc_read(pfc, pocctrl);
732 			if (mV == 3300)
733 				val |= BIT(bit);
734 			else
735 				val &= ~BIT(bit);
736 			sh_pfc_write(pfc, pocctrl, val);
737 			spin_unlock_irqrestore(&pfc->lock, flags);
738 
739 			break;
740 		}
741 
742 		default:
743 			return -ENOTSUPP;
744 		}
745 	} /* for each config */
746 
747 	return 0;
748 }
749 
750 static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
751 				    unsigned long *configs,
752 				    unsigned num_configs)
753 {
754 	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
755 	const unsigned int *pins;
756 	unsigned int num_pins;
757 	unsigned int i, ret;
758 
759 	pins = pmx->pfc->info->groups[group].pins;
760 	num_pins = pmx->pfc->info->groups[group].nr_pins;
761 
762 	for (i = 0; i < num_pins; ++i) {
763 		ret = sh_pfc_pinconf_set(pctldev, pins[i], configs, num_configs);
764 		if (ret)
765 			return ret;
766 	}
767 
768 	return 0;
769 }
770 
771 static const struct pinconf_ops sh_pfc_pinconf_ops = {
772 	.is_generic			= true,
773 	.pin_config_get			= sh_pfc_pinconf_get,
774 	.pin_config_set			= sh_pfc_pinconf_set,
775 	.pin_config_group_set		= sh_pfc_pinconf_group_set,
776 	.pin_config_config_dbg_show	= pinconf_generic_dump_config,
777 };
778 
779 /* PFC ranges -> pinctrl pin descs */
780 static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
781 {
782 	unsigned int i;
783 
784 	/* Allocate and initialize the pins and configs arrays. */
785 	pmx->pins = devm_kcalloc(pfc->dev,
786 				 pfc->info->nr_pins, sizeof(*pmx->pins),
787 				 GFP_KERNEL);
788 	if (unlikely(!pmx->pins))
789 		return -ENOMEM;
790 
791 	pmx->configs = devm_kcalloc(pfc->dev,
792 				    pfc->info->nr_pins, sizeof(*pmx->configs),
793 				    GFP_KERNEL);
794 	if (unlikely(!pmx->configs))
795 		return -ENOMEM;
796 
797 	for (i = 0; i < pfc->info->nr_pins; ++i) {
798 		const struct sh_pfc_pin *info = &pfc->info->pins[i];
799 		struct pinctrl_pin_desc *pin = &pmx->pins[i];
800 
801 		/* If the pin number is equal to -1 all pins are considered */
802 		pin->number = info->pin != (u16)-1 ? info->pin : i;
803 		pin->name = info->name;
804 	}
805 
806 	return 0;
807 }
808 
809 int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
810 {
811 	struct sh_pfc_pinctrl *pmx;
812 	int ret;
813 
814 	pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL);
815 	if (unlikely(!pmx))
816 		return -ENOMEM;
817 
818 	pmx->pfc = pfc;
819 
820 	ret = sh_pfc_map_pins(pfc, pmx);
821 	if (ret < 0)
822 		return ret;
823 
824 	pmx->pctl_desc.name = DRV_NAME;
825 	pmx->pctl_desc.owner = THIS_MODULE;
826 	pmx->pctl_desc.pctlops = &sh_pfc_pinctrl_ops;
827 	pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops;
828 	pmx->pctl_desc.confops = &sh_pfc_pinconf_ops;
829 	pmx->pctl_desc.pins = pmx->pins;
830 	pmx->pctl_desc.npins = pfc->info->nr_pins;
831 
832 	ret = devm_pinctrl_register_and_init(pfc->dev, &pmx->pctl_desc, pmx,
833 					     &pmx->pctl);
834 	if (ret) {
835 		dev_err(pfc->dev, "could not register: %i\n", ret);
836 
837 		return ret;
838 	}
839 
840 	return pinctrl_enable(pmx->pctl);
841 }
842 
843 unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
844 {
845 	const struct pinmux_bias_reg *reg;
846 	unsigned int bit;
847 
848 	reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
849 	if (!reg)
850 		return PIN_CONFIG_BIAS_DISABLE;
851 
852 	if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
853 		return PIN_CONFIG_BIAS_DISABLE;
854 	else if (!reg->pud || (sh_pfc_read(pfc, reg->pud) & BIT(bit)))
855 		return PIN_CONFIG_BIAS_PULL_UP;
856 	else
857 		return PIN_CONFIG_BIAS_PULL_DOWN;
858 }
859 
860 void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
861 			  unsigned int bias)
862 {
863 	const struct pinmux_bias_reg *reg;
864 	u32 enable, updown;
865 	unsigned int bit;
866 
867 	reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
868 	if (!reg)
869 		return;
870 
871 	enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
872 	if (bias != PIN_CONFIG_BIAS_DISABLE)
873 		enable |= BIT(bit);
874 
875 	if (reg->pud) {
876 		updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
877 		if (bias == PIN_CONFIG_BIAS_PULL_UP)
878 			updown |= BIT(bit);
879 
880 		sh_pfc_write(pfc, reg->pud, updown);
881 	}
882 
883 	sh_pfc_write(pfc, reg->puen, enable);
884 }
885