1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas RZ/V2M Pin Control and GPIO driver core 4 * 5 * Based on: 6 * Renesas RZ/G2L Pin Control and GPIO driver core 7 * 8 * Copyright (C) 2022 Renesas Electronics Corporation. 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/bitops.h> 13 #include <linux/clk.h> 14 #include <linux/gpio/driver.h> 15 #include <linux/io.h> 16 #include <linux/module.h> 17 #include <linux/of_device.h> 18 #include <linux/spinlock.h> 19 20 #include <linux/pinctrl/consumer.h> 21 #include <linux/pinctrl/pinconf-generic.h> 22 #include <linux/pinctrl/pinconf.h> 23 #include <linux/pinctrl/pinctrl.h> 24 #include <linux/pinctrl/pinmux.h> 25 26 #include <dt-bindings/pinctrl/rzv2m-pinctrl.h> 27 28 #include "../core.h" 29 #include "../pinconf.h" 30 #include "../pinmux.h" 31 32 #define DRV_NAME "pinctrl-rzv2m" 33 34 /* 35 * Use 16 lower bits [15:0] for pin identifier 36 * Use 16 higher bits [31:16] for pin mux function 37 */ 38 #define MUX_PIN_ID_MASK GENMASK(15, 0) 39 #define MUX_FUNC_MASK GENMASK(31, 16) 40 #define MUX_FUNC(pinconf) FIELD_GET(MUX_FUNC_MASK, (pinconf)) 41 42 /* PIN capabilities */ 43 #define PIN_CFG_GRP_1_8V_2 1 44 #define PIN_CFG_GRP_1_8V_3 2 45 #define PIN_CFG_GRP_SWIO_1 3 46 #define PIN_CFG_GRP_SWIO_2 4 47 #define PIN_CFG_GRP_3_3V 5 48 #define PIN_CFG_GRP_MASK GENMASK(2, 0) 49 #define PIN_CFG_BIAS BIT(3) 50 #define PIN_CFG_DRV BIT(4) 51 #define PIN_CFG_SLEW BIT(5) 52 53 #define RZV2M_MPXED_PIN_FUNCS (PIN_CFG_BIAS | \ 54 PIN_CFG_DRV | \ 55 PIN_CFG_SLEW) 56 57 /* 58 * n indicates number of pins in the port, a is the register index 59 * and f is pin configuration capabilities supported. 60 */ 61 #define RZV2M_GPIO_PORT_PACK(n, a, f) (((n) << 24) | ((a) << 16) | (f)) 62 #define RZV2M_GPIO_PORT_GET_PINCNT(x) FIELD_GET(GENMASK(31, 24), (x)) 63 #define RZV2M_GPIO_PORT_GET_INDEX(x) FIELD_GET(GENMASK(23, 16), (x)) 64 #define RZV2M_GPIO_PORT_GET_CFGS(x) FIELD_GET(GENMASK(15, 0), (x)) 65 66 #define RZV2M_DEDICATED_PORT_IDX 22 67 68 /* 69 * BIT(31) indicates dedicated pin, b is the register bits (b * 16) 70 * and f is the pin configuration capabilities supported. 71 */ 72 #define RZV2M_SINGLE_PIN BIT(31) 73 #define RZV2M_SINGLE_PIN_PACK(b, f) (RZV2M_SINGLE_PIN | \ 74 ((RZV2M_DEDICATED_PORT_IDX) << 24) | \ 75 ((b) << 16) | (f)) 76 #define RZV2M_SINGLE_PIN_GET_PORT(x) FIELD_GET(GENMASK(30, 24), (x)) 77 #define RZV2M_SINGLE_PIN_GET_BIT(x) FIELD_GET(GENMASK(23, 16), (x)) 78 #define RZV2M_SINGLE_PIN_GET_CFGS(x) FIELD_GET(GENMASK(15, 0), (x)) 79 80 #define RZV2M_PIN_ID_TO_PORT(id) ((id) / RZV2M_PINS_PER_PORT) 81 #define RZV2M_PIN_ID_TO_PIN(id) ((id) % RZV2M_PINS_PER_PORT) 82 83 #define DO(n) (0x00 + (n) * 0x40) 84 #define OE(n) (0x04 + (n) * 0x40) 85 #define IE(n) (0x08 + (n) * 0x40) 86 #define PFSEL(n) (0x10 + (n) * 0x40) 87 #define DI(n) (0x20 + (n) * 0x40) 88 #define PUPD(n) (0x24 + (n) * 0x40) 89 #define DRV(n) ((n) < RZV2M_DEDICATED_PORT_IDX ? (0x28 + (n) * 0x40) \ 90 : 0x590) 91 #define SR(n) ((n) < RZV2M_DEDICATED_PORT_IDX ? (0x2c + (n) * 0x40) \ 92 : 0x594) 93 #define DI_MSK(n) (0x30 + (n) * 0x40) 94 #define EN_MSK(n) (0x34 + (n) * 0x40) 95 96 #define PFC_MASK 0x07 97 #define PUPD_MASK 0x03 98 #define DRV_MASK 0x03 99 100 struct rzv2m_dedicated_configs { 101 const char *name; 102 u32 config; 103 }; 104 105 struct rzv2m_pinctrl_data { 106 const char * const *port_pins; 107 const u32 *port_pin_configs; 108 const struct rzv2m_dedicated_configs *dedicated_pins; 109 unsigned int n_port_pins; 110 unsigned int n_dedicated_pins; 111 }; 112 113 struct rzv2m_pinctrl { 114 struct pinctrl_dev *pctl; 115 struct pinctrl_desc desc; 116 struct pinctrl_pin_desc *pins; 117 118 const struct rzv2m_pinctrl_data *data; 119 void __iomem *base; 120 struct device *dev; 121 struct clk *clk; 122 123 struct gpio_chip gpio_chip; 124 struct pinctrl_gpio_range gpio_range; 125 126 spinlock_t lock; 127 }; 128 129 static const unsigned int drv_1_8V_group2_uA[] = { 1800, 3800, 7800, 11000 }; 130 static const unsigned int drv_1_8V_group3_uA[] = { 1600, 3200, 6400, 9600 }; 131 static const unsigned int drv_SWIO_group2_3_3V_uA[] = { 9000, 11000, 13000, 18000 }; 132 static const unsigned int drv_3_3V_group_uA[] = { 2000, 4000, 8000, 12000 }; 133 134 /* Helper for registers that have a write enable bit in the upper word */ 135 static void rzv2m_writel_we(void __iomem *addr, u8 shift, u8 value) 136 { 137 writel((BIT(16) | value) << shift, addr); 138 } 139 140 static void rzv2m_pinctrl_set_pfc_mode(struct rzv2m_pinctrl *pctrl, 141 u8 port, u8 pin, u8 func) 142 { 143 void __iomem *addr; 144 145 /* Mask input/output */ 146 rzv2m_writel_we(pctrl->base + DI_MSK(port), pin, 1); 147 rzv2m_writel_we(pctrl->base + EN_MSK(port), pin, 1); 148 149 /* Select the function and set the write enable bits */ 150 addr = pctrl->base + PFSEL(port) + (pin / 4) * 4; 151 writel(((PFC_MASK << 16) | func) << ((pin % 4) * 4), addr); 152 153 /* Unmask input/output */ 154 rzv2m_writel_we(pctrl->base + EN_MSK(port), pin, 0); 155 rzv2m_writel_we(pctrl->base + DI_MSK(port), pin, 0); 156 }; 157 158 static int rzv2m_pinctrl_set_mux(struct pinctrl_dev *pctldev, 159 unsigned int func_selector, 160 unsigned int group_selector) 161 { 162 struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 163 struct function_desc *func; 164 unsigned int i, *psel_val; 165 struct group_desc *group; 166 int *pins; 167 168 func = pinmux_generic_get_function(pctldev, func_selector); 169 if (!func) 170 return -EINVAL; 171 group = pinctrl_generic_get_group(pctldev, group_selector); 172 if (!group) 173 return -EINVAL; 174 175 psel_val = func->data; 176 pins = group->pins; 177 178 for (i = 0; i < group->num_pins; i++) { 179 dev_dbg(pctrl->dev, "port:%u pin: %u PSEL:%u\n", 180 RZV2M_PIN_ID_TO_PORT(pins[i]), RZV2M_PIN_ID_TO_PIN(pins[i]), 181 psel_val[i]); 182 rzv2m_pinctrl_set_pfc_mode(pctrl, RZV2M_PIN_ID_TO_PORT(pins[i]), 183 RZV2M_PIN_ID_TO_PIN(pins[i]), psel_val[i]); 184 } 185 186 return 0; 187 }; 188 189 static int rzv2m_map_add_config(struct pinctrl_map *map, 190 const char *group_or_pin, 191 enum pinctrl_map_type type, 192 unsigned long *configs, 193 unsigned int num_configs) 194 { 195 unsigned long *cfgs; 196 197 cfgs = kmemdup(configs, num_configs * sizeof(*cfgs), 198 GFP_KERNEL); 199 if (!cfgs) 200 return -ENOMEM; 201 202 map->type = type; 203 map->data.configs.group_or_pin = group_or_pin; 204 map->data.configs.configs = cfgs; 205 map->data.configs.num_configs = num_configs; 206 207 return 0; 208 } 209 210 static int rzv2m_dt_subnode_to_map(struct pinctrl_dev *pctldev, 211 struct device_node *np, 212 struct device_node *parent, 213 struct pinctrl_map **map, 214 unsigned int *num_maps, 215 unsigned int *index) 216 { 217 struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 218 struct pinctrl_map *maps = *map; 219 unsigned int nmaps = *num_maps; 220 unsigned long *configs = NULL; 221 unsigned int *pins, *psel_val; 222 unsigned int num_pinmux = 0; 223 unsigned int idx = *index; 224 unsigned int num_pins, i; 225 unsigned int num_configs; 226 struct property *pinmux; 227 struct property *prop; 228 int ret, gsel, fsel; 229 const char **pin_fn; 230 const char *name; 231 const char *pin; 232 233 pinmux = of_find_property(np, "pinmux", NULL); 234 if (pinmux) 235 num_pinmux = pinmux->length / sizeof(u32); 236 237 ret = of_property_count_strings(np, "pins"); 238 if (ret == -EINVAL) { 239 num_pins = 0; 240 } else if (ret < 0) { 241 dev_err(pctrl->dev, "Invalid pins list in DT\n"); 242 return ret; 243 } else { 244 num_pins = ret; 245 } 246 247 if (!num_pinmux && !num_pins) 248 return 0; 249 250 if (num_pinmux && num_pins) { 251 dev_err(pctrl->dev, 252 "DT node must contain either a pinmux or pins and not both\n"); 253 return -EINVAL; 254 } 255 256 ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs); 257 if (ret < 0) 258 return ret; 259 260 if (num_pins && !num_configs) { 261 dev_err(pctrl->dev, "DT node must contain a config\n"); 262 ret = -ENODEV; 263 goto done; 264 } 265 266 if (num_pinmux) 267 nmaps += 1; 268 269 if (num_pins) 270 nmaps += num_pins; 271 272 maps = krealloc_array(maps, nmaps, sizeof(*maps), GFP_KERNEL); 273 if (!maps) { 274 ret = -ENOMEM; 275 goto done; 276 } 277 278 *map = maps; 279 *num_maps = nmaps; 280 if (num_pins) { 281 of_property_for_each_string(np, "pins", prop, pin) { 282 ret = rzv2m_map_add_config(&maps[idx], pin, 283 PIN_MAP_TYPE_CONFIGS_PIN, 284 configs, num_configs); 285 if (ret < 0) 286 goto done; 287 288 idx++; 289 } 290 ret = 0; 291 goto done; 292 } 293 294 pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL); 295 psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val), 296 GFP_KERNEL); 297 pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL); 298 if (!pins || !psel_val || !pin_fn) { 299 ret = -ENOMEM; 300 goto done; 301 } 302 303 /* Collect pin locations and mux settings from DT properties */ 304 for (i = 0; i < num_pinmux; ++i) { 305 u32 value; 306 307 ret = of_property_read_u32_index(np, "pinmux", i, &value); 308 if (ret) 309 goto done; 310 pins[i] = value & MUX_PIN_ID_MASK; 311 psel_val[i] = MUX_FUNC(value); 312 } 313 314 if (parent) { 315 name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn", 316 parent, np); 317 if (!name) { 318 ret = -ENOMEM; 319 goto done; 320 } 321 } else { 322 name = np->name; 323 } 324 325 /* Register a single pin group listing all the pins we read from DT */ 326 gsel = pinctrl_generic_add_group(pctldev, name, pins, num_pinmux, NULL); 327 if (gsel < 0) { 328 ret = gsel; 329 goto done; 330 } 331 332 /* 333 * Register a single group function where the 'data' is an array PSEL 334 * register values read from DT. 335 */ 336 pin_fn[0] = name; 337 fsel = pinmux_generic_add_function(pctldev, name, pin_fn, 1, psel_val); 338 if (fsel < 0) { 339 ret = fsel; 340 goto remove_group; 341 } 342 343 maps[idx].type = PIN_MAP_TYPE_MUX_GROUP; 344 maps[idx].data.mux.group = name; 345 maps[idx].data.mux.function = name; 346 idx++; 347 348 dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux); 349 ret = 0; 350 goto done; 351 352 remove_group: 353 pinctrl_generic_remove_group(pctldev, gsel); 354 done: 355 *index = idx; 356 kfree(configs); 357 return ret; 358 } 359 360 static void rzv2m_dt_free_map(struct pinctrl_dev *pctldev, 361 struct pinctrl_map *map, 362 unsigned int num_maps) 363 { 364 unsigned int i; 365 366 if (!map) 367 return; 368 369 for (i = 0; i < num_maps; ++i) { 370 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP || 371 map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) 372 kfree(map[i].data.configs.configs); 373 } 374 kfree(map); 375 } 376 377 static int rzv2m_dt_node_to_map(struct pinctrl_dev *pctldev, 378 struct device_node *np, 379 struct pinctrl_map **map, 380 unsigned int *num_maps) 381 { 382 struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 383 struct device_node *child; 384 unsigned int index; 385 int ret; 386 387 *map = NULL; 388 *num_maps = 0; 389 index = 0; 390 391 for_each_child_of_node(np, child) { 392 ret = rzv2m_dt_subnode_to_map(pctldev, child, np, map, 393 num_maps, &index); 394 if (ret < 0) { 395 of_node_put(child); 396 goto done; 397 } 398 } 399 400 if (*num_maps == 0) { 401 ret = rzv2m_dt_subnode_to_map(pctldev, np, NULL, map, 402 num_maps, &index); 403 if (ret < 0) 404 goto done; 405 } 406 407 if (*num_maps) 408 return 0; 409 410 dev_err(pctrl->dev, "no mapping found in node %pOF\n", np); 411 ret = -EINVAL; 412 413 done: 414 rzv2m_dt_free_map(pctldev, *map, *num_maps); 415 416 return ret; 417 } 418 419 static int rzv2m_validate_gpio_pin(struct rzv2m_pinctrl *pctrl, 420 u32 cfg, u32 port, u8 bit) 421 { 422 u8 pincount = RZV2M_GPIO_PORT_GET_PINCNT(cfg); 423 u32 port_index = RZV2M_GPIO_PORT_GET_INDEX(cfg); 424 u32 data; 425 426 if (bit >= pincount || port >= pctrl->data->n_port_pins) 427 return -EINVAL; 428 429 data = pctrl->data->port_pin_configs[port]; 430 if (port_index != RZV2M_GPIO_PORT_GET_INDEX(data)) 431 return -EINVAL; 432 433 return 0; 434 } 435 436 static void rzv2m_rmw_pin_config(struct rzv2m_pinctrl *pctrl, u32 offset, 437 u8 shift, u32 mask, u32 val) 438 { 439 void __iomem *addr = pctrl->base + offset; 440 unsigned long flags; 441 u32 reg; 442 443 spin_lock_irqsave(&pctrl->lock, flags); 444 reg = readl(addr) & ~(mask << shift); 445 writel(reg | (val << shift), addr); 446 spin_unlock_irqrestore(&pctrl->lock, flags); 447 } 448 449 static int rzv2m_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, 450 unsigned int _pin, 451 unsigned long *config) 452 { 453 struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 454 enum pin_config_param param = pinconf_to_config_param(*config); 455 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; 456 unsigned int *pin_data = pin->drv_data; 457 unsigned int arg = 0; 458 u32 port; 459 u32 cfg; 460 u8 bit; 461 u32 val; 462 463 if (!pin_data) 464 return -EINVAL; 465 466 if (*pin_data & RZV2M_SINGLE_PIN) { 467 port = RZV2M_SINGLE_PIN_GET_PORT(*pin_data); 468 cfg = RZV2M_SINGLE_PIN_GET_CFGS(*pin_data); 469 bit = RZV2M_SINGLE_PIN_GET_BIT(*pin_data); 470 } else { 471 cfg = RZV2M_GPIO_PORT_GET_CFGS(*pin_data); 472 port = RZV2M_PIN_ID_TO_PORT(_pin); 473 bit = RZV2M_PIN_ID_TO_PIN(_pin); 474 475 if (rzv2m_validate_gpio_pin(pctrl, *pin_data, RZV2M_PIN_ID_TO_PORT(_pin), bit)) 476 return -EINVAL; 477 } 478 479 switch (param) { 480 case PIN_CONFIG_BIAS_DISABLE: 481 case PIN_CONFIG_BIAS_PULL_UP: 482 case PIN_CONFIG_BIAS_PULL_DOWN: { 483 enum pin_config_param bias; 484 485 if (!(cfg & PIN_CFG_BIAS)) 486 return -EINVAL; 487 488 /* PUPD uses 2-bits per pin */ 489 bit *= 2; 490 491 switch ((readl(pctrl->base + PUPD(port)) >> bit) & PUPD_MASK) { 492 case 0: 493 bias = PIN_CONFIG_BIAS_PULL_DOWN; 494 break; 495 case 2: 496 bias = PIN_CONFIG_BIAS_PULL_UP; 497 break; 498 default: 499 bias = PIN_CONFIG_BIAS_DISABLE; 500 } 501 502 if (bias != param) 503 return -EINVAL; 504 break; 505 } 506 507 case PIN_CONFIG_DRIVE_STRENGTH_UA: 508 if (!(cfg & PIN_CFG_DRV)) 509 return -EINVAL; 510 511 /* DRV uses 2-bits per pin */ 512 bit *= 2; 513 514 val = (readl(pctrl->base + DRV(port)) >> bit) & DRV_MASK; 515 516 switch (cfg & PIN_CFG_GRP_MASK) { 517 case PIN_CFG_GRP_1_8V_2: 518 arg = drv_1_8V_group2_uA[val]; 519 break; 520 case PIN_CFG_GRP_1_8V_3: 521 arg = drv_1_8V_group3_uA[val]; 522 break; 523 case PIN_CFG_GRP_SWIO_2: 524 arg = drv_SWIO_group2_3_3V_uA[val]; 525 break; 526 case PIN_CFG_GRP_SWIO_1: 527 case PIN_CFG_GRP_3_3V: 528 arg = drv_3_3V_group_uA[val]; 529 break; 530 default: 531 return -EINVAL; 532 } 533 534 break; 535 536 case PIN_CONFIG_SLEW_RATE: 537 if (!(cfg & PIN_CFG_SLEW)) 538 return -EINVAL; 539 540 arg = readl(pctrl->base + SR(port)) & BIT(bit); 541 break; 542 543 default: 544 return -ENOTSUPP; 545 } 546 547 *config = pinconf_to_config_packed(param, arg); 548 549 return 0; 550 }; 551 552 static int rzv2m_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, 553 unsigned int _pin, 554 unsigned long *_configs, 555 unsigned int num_configs) 556 { 557 struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 558 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; 559 unsigned int *pin_data = pin->drv_data; 560 enum pin_config_param param; 561 u32 port; 562 unsigned int i; 563 u32 cfg; 564 u8 bit; 565 u32 val; 566 567 if (!pin_data) 568 return -EINVAL; 569 570 if (*pin_data & RZV2M_SINGLE_PIN) { 571 port = RZV2M_SINGLE_PIN_GET_PORT(*pin_data); 572 cfg = RZV2M_SINGLE_PIN_GET_CFGS(*pin_data); 573 bit = RZV2M_SINGLE_PIN_GET_BIT(*pin_data); 574 } else { 575 cfg = RZV2M_GPIO_PORT_GET_CFGS(*pin_data); 576 port = RZV2M_PIN_ID_TO_PORT(_pin); 577 bit = RZV2M_PIN_ID_TO_PIN(_pin); 578 579 if (rzv2m_validate_gpio_pin(pctrl, *pin_data, RZV2M_PIN_ID_TO_PORT(_pin), bit)) 580 return -EINVAL; 581 } 582 583 for (i = 0; i < num_configs; i++) { 584 param = pinconf_to_config_param(_configs[i]); 585 switch (param) { 586 case PIN_CONFIG_BIAS_DISABLE: 587 case PIN_CONFIG_BIAS_PULL_UP: 588 case PIN_CONFIG_BIAS_PULL_DOWN: 589 if (!(cfg & PIN_CFG_BIAS)) 590 return -EINVAL; 591 592 /* PUPD uses 2-bits per pin */ 593 bit *= 2; 594 595 switch (param) { 596 case PIN_CONFIG_BIAS_PULL_DOWN: 597 val = 0; 598 break; 599 case PIN_CONFIG_BIAS_PULL_UP: 600 val = 2; 601 break; 602 default: 603 val = 1; 604 } 605 606 rzv2m_rmw_pin_config(pctrl, PUPD(port), bit, PUPD_MASK, val); 607 break; 608 609 case PIN_CONFIG_DRIVE_STRENGTH_UA: { 610 unsigned int arg = pinconf_to_config_argument(_configs[i]); 611 const unsigned int *drv_strengths; 612 unsigned int index; 613 614 if (!(cfg & PIN_CFG_DRV)) 615 return -EINVAL; 616 617 switch (cfg & PIN_CFG_GRP_MASK) { 618 case PIN_CFG_GRP_1_8V_2: 619 drv_strengths = drv_1_8V_group2_uA; 620 break; 621 case PIN_CFG_GRP_1_8V_3: 622 drv_strengths = drv_1_8V_group3_uA; 623 break; 624 case PIN_CFG_GRP_SWIO_2: 625 drv_strengths = drv_SWIO_group2_3_3V_uA; 626 break; 627 case PIN_CFG_GRP_SWIO_1: 628 case PIN_CFG_GRP_3_3V: 629 drv_strengths = drv_3_3V_group_uA; 630 break; 631 default: 632 return -EINVAL; 633 } 634 635 for (index = 0; index < 4; index++) { 636 if (arg == drv_strengths[index]) 637 break; 638 } 639 if (index >= 4) 640 return -EINVAL; 641 642 /* DRV uses 2-bits per pin */ 643 bit *= 2; 644 645 rzv2m_rmw_pin_config(pctrl, DRV(port), bit, DRV_MASK, index); 646 break; 647 } 648 649 case PIN_CONFIG_SLEW_RATE: { 650 unsigned int arg = pinconf_to_config_argument(_configs[i]); 651 652 if (!(cfg & PIN_CFG_SLEW)) 653 return -EINVAL; 654 655 rzv2m_writel_we(pctrl->base + SR(port), bit, !arg); 656 break; 657 } 658 659 default: 660 return -EOPNOTSUPP; 661 } 662 } 663 664 return 0; 665 } 666 667 static int rzv2m_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev, 668 unsigned int group, 669 unsigned long *configs, 670 unsigned int num_configs) 671 { 672 const unsigned int *pins; 673 unsigned int i, npins; 674 int ret; 675 676 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 677 if (ret) 678 return ret; 679 680 for (i = 0; i < npins; i++) { 681 ret = rzv2m_pinctrl_pinconf_set(pctldev, pins[i], configs, 682 num_configs); 683 if (ret) 684 return ret; 685 } 686 687 return 0; 688 }; 689 690 static int rzv2m_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev, 691 unsigned int group, 692 unsigned long *config) 693 { 694 const unsigned int *pins; 695 unsigned int i, npins, prev_config = 0; 696 int ret; 697 698 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 699 if (ret) 700 return ret; 701 702 for (i = 0; i < npins; i++) { 703 ret = rzv2m_pinctrl_pinconf_get(pctldev, pins[i], config); 704 if (ret) 705 return ret; 706 707 /* Check config matches previous pins */ 708 if (i && prev_config != *config) 709 return -EOPNOTSUPP; 710 711 prev_config = *config; 712 } 713 714 return 0; 715 }; 716 717 static const struct pinctrl_ops rzv2m_pinctrl_pctlops = { 718 .get_groups_count = pinctrl_generic_get_group_count, 719 .get_group_name = pinctrl_generic_get_group_name, 720 .get_group_pins = pinctrl_generic_get_group_pins, 721 .dt_node_to_map = rzv2m_dt_node_to_map, 722 .dt_free_map = rzv2m_dt_free_map, 723 }; 724 725 static const struct pinmux_ops rzv2m_pinctrl_pmxops = { 726 .get_functions_count = pinmux_generic_get_function_count, 727 .get_function_name = pinmux_generic_get_function_name, 728 .get_function_groups = pinmux_generic_get_function_groups, 729 .set_mux = rzv2m_pinctrl_set_mux, 730 .strict = true, 731 }; 732 733 static const struct pinconf_ops rzv2m_pinctrl_confops = { 734 .is_generic = true, 735 .pin_config_get = rzv2m_pinctrl_pinconf_get, 736 .pin_config_set = rzv2m_pinctrl_pinconf_set, 737 .pin_config_group_set = rzv2m_pinctrl_pinconf_group_set, 738 .pin_config_group_get = rzv2m_pinctrl_pinconf_group_get, 739 .pin_config_config_dbg_show = pinconf_generic_dump_config, 740 }; 741 742 static int rzv2m_gpio_request(struct gpio_chip *chip, unsigned int offset) 743 { 744 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip); 745 u32 port = RZV2M_PIN_ID_TO_PORT(offset); 746 u8 bit = RZV2M_PIN_ID_TO_PIN(offset); 747 int ret; 748 749 ret = pinctrl_gpio_request(chip->base + offset); 750 if (ret) 751 return ret; 752 753 rzv2m_pinctrl_set_pfc_mode(pctrl, port, bit, 0); 754 755 return 0; 756 } 757 758 static void rzv2m_gpio_set_direction(struct rzv2m_pinctrl *pctrl, u32 port, 759 u8 bit, bool output) 760 { 761 rzv2m_writel_we(pctrl->base + OE(port), bit, output); 762 rzv2m_writel_we(pctrl->base + IE(port), bit, !output); 763 } 764 765 static int rzv2m_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 766 { 767 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip); 768 u32 port = RZV2M_PIN_ID_TO_PORT(offset); 769 u8 bit = RZV2M_PIN_ID_TO_PIN(offset); 770 771 if (!(readl(pctrl->base + IE(port)) & BIT(bit))) 772 return GPIO_LINE_DIRECTION_OUT; 773 774 return GPIO_LINE_DIRECTION_IN; 775 } 776 777 static int rzv2m_gpio_direction_input(struct gpio_chip *chip, 778 unsigned int offset) 779 { 780 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip); 781 u32 port = RZV2M_PIN_ID_TO_PORT(offset); 782 u8 bit = RZV2M_PIN_ID_TO_PIN(offset); 783 784 rzv2m_gpio_set_direction(pctrl, port, bit, false); 785 786 return 0; 787 } 788 789 static void rzv2m_gpio_set(struct gpio_chip *chip, unsigned int offset, 790 int value) 791 { 792 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip); 793 u32 port = RZV2M_PIN_ID_TO_PORT(offset); 794 u8 bit = RZV2M_PIN_ID_TO_PIN(offset); 795 796 rzv2m_writel_we(pctrl->base + DO(port), bit, !!value); 797 } 798 799 static int rzv2m_gpio_direction_output(struct gpio_chip *chip, 800 unsigned int offset, int value) 801 { 802 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip); 803 u32 port = RZV2M_PIN_ID_TO_PORT(offset); 804 u8 bit = RZV2M_PIN_ID_TO_PIN(offset); 805 806 rzv2m_gpio_set(chip, offset, value); 807 rzv2m_gpio_set_direction(pctrl, port, bit, true); 808 809 return 0; 810 } 811 812 static int rzv2m_gpio_get(struct gpio_chip *chip, unsigned int offset) 813 { 814 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip); 815 u32 port = RZV2M_PIN_ID_TO_PORT(offset); 816 u8 bit = RZV2M_PIN_ID_TO_PIN(offset); 817 int direction = rzv2m_gpio_get_direction(chip, offset); 818 819 if (direction == GPIO_LINE_DIRECTION_IN) 820 return !!(readl(pctrl->base + DI(port)) & BIT(bit)); 821 else 822 return !!(readl(pctrl->base + DO(port)) & BIT(bit)); 823 } 824 825 static void rzv2m_gpio_free(struct gpio_chip *chip, unsigned int offset) 826 { 827 pinctrl_gpio_free(chip->base + offset); 828 829 /* 830 * Set the GPIO as an input to ensure that the next GPIO request won't 831 * drive the GPIO pin as an output. 832 */ 833 rzv2m_gpio_direction_input(chip, offset); 834 } 835 836 static const char * const rzv2m_gpio_names[] = { 837 "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7", 838 "P0_8", "P0_9", "P0_10", "P0_11", "P0_12", "P0_13", "P0_14", "P0_15", 839 "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7", 840 "P1_8", "P1_9", "P1_10", "P1_11", "P1_12", "P1_13", "P1_14", "P1_15", 841 "P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7", 842 "P2_8", "P2_9", "P2_10", "P2_11", "P2_12", "P2_13", "P2_14", "P2_15", 843 "P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7", 844 "P3_8", "P3_9", "P3_10", "P3_11", "P3_12", "P3_13", "P3_14", "P3_15", 845 "P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7", 846 "P4_8", "P4_9", "P4_10", "P4_11", "P4_12", "P4_13", "P4_14", "P4_15", 847 "P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7", 848 "P5_8", "P5_9", "P5_10", "P5_11", "P5_12", "P5_13", "P5_14", "P5_15", 849 "P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7", 850 "P6_8", "P6_9", "P6_10", "P6_11", "P6_12", "P6_13", "P6_14", "P6_15", 851 "P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7", 852 "P7_8", "P7_9", "P7_10", "P7_11", "P7_12", "P7_13", "P7_14", "P7_15", 853 "P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7", 854 "P8_8", "P8_9", "P8_10", "P8_11", "P8_12", "P8_13", "P8_14", "P8_15", 855 "P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7", 856 "P9_8", "P9_9", "P9_10", "P9_11", "P9_12", "P9_13", "P9_14", "P9_15", 857 "P10_0", "P10_1", "P10_2", "P10_3", "P10_4", "P10_5", "P10_6", "P10_7", 858 "P10_8", "P10_9", "P10_10", "P10_11", "P10_12", "P10_13", "P10_14", "P10_15", 859 "P11_0", "P11_1", "P11_2", "P11_3", "P11_4", "P11_5", "P11_6", "P11_7", 860 "P11_8", "P11_9", "P11_10", "P11_11", "P11_12", "P11_13", "P11_14", "P11_15", 861 "P12_0", "P12_1", "P12_2", "P12_3", "P12_4", "P12_5", "P12_6", "P12_7", 862 "P12_8", "P12_9", "P12_10", "P12_11", "P12_12", "P12_13", "P12_14", "P12_15", 863 "P13_0", "P13_1", "P13_2", "P13_3", "P13_4", "P13_5", "P13_6", "P13_7", 864 "P13_8", "P13_9", "P13_10", "P13_11", "P13_12", "P13_13", "P13_14", "P13_15", 865 "P14_0", "P14_1", "P14_2", "P14_3", "P14_4", "P14_5", "P14_6", "P14_7", 866 "P14_8", "P14_9", "P14_10", "P14_11", "P14_12", "P14_13", "P14_14", "P14_15", 867 "P15_0", "P15_1", "P15_2", "P15_3", "P15_4", "P15_5", "P15_6", "P15_7", 868 "P15_8", "P15_9", "P15_10", "P15_11", "P15_12", "P15_13", "P15_14", "P15_15", 869 "P16_0", "P16_1", "P16_2", "P16_3", "P16_4", "P16_5", "P16_6", "P16_7", 870 "P16_8", "P16_9", "P16_10", "P16_11", "P16_12", "P16_13", "P16_14", "P16_15", 871 "P17_0", "P17_1", "P17_2", "P17_3", "P17_4", "P17_5", "P17_6", "P17_7", 872 "P17_8", "P17_9", "P17_10", "P17_11", "P17_12", "P17_13", "P17_14", "P17_15", 873 "P18_0", "P18_1", "P18_2", "P18_3", "P18_4", "P18_5", "P18_6", "P18_7", 874 "P18_8", "P18_9", "P18_10", "P18_11", "P18_12", "P18_13", "P18_14", "P18_15", 875 "P19_0", "P19_1", "P19_2", "P19_3", "P19_4", "P19_5", "P19_6", "P19_7", 876 "P19_8", "P19_9", "P19_10", "P19_11", "P19_12", "P19_13", "P19_14", "P19_15", 877 "P20_0", "P20_1", "P20_2", "P20_3", "P20_4", "P20_5", "P20_6", "P20_7", 878 "P20_8", "P20_9", "P20_10", "P20_11", "P20_12", "P20_13", "P20_14", "P20_15", 879 "P21_0", "P21_1", "P21_2", "P21_3", "P21_4", "P21_5", "P21_6", "P21_7", 880 "P21_8", "P21_9", "P21_10", "P21_11", "P21_12", "P21_13", "P21_14", "P21_15", 881 }; 882 883 static const u32 rzv2m_gpio_configs[] = { 884 RZV2M_GPIO_PORT_PACK(14, 0, PIN_CFG_GRP_SWIO_2 | RZV2M_MPXED_PIN_FUNCS), 885 RZV2M_GPIO_PORT_PACK(16, 1, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS), 886 RZV2M_GPIO_PORT_PACK(8, 2, PIN_CFG_GRP_1_8V_3 | RZV2M_MPXED_PIN_FUNCS), 887 RZV2M_GPIO_PORT_PACK(16, 3, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS), 888 RZV2M_GPIO_PORT_PACK(8, 4, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS), 889 RZV2M_GPIO_PORT_PACK(4, 5, PIN_CFG_GRP_1_8V_3 | RZV2M_MPXED_PIN_FUNCS), 890 RZV2M_GPIO_PORT_PACK(12, 6, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS), 891 RZV2M_GPIO_PORT_PACK(6, 7, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS), 892 RZV2M_GPIO_PORT_PACK(8, 8, PIN_CFG_GRP_SWIO_2 | RZV2M_MPXED_PIN_FUNCS), 893 RZV2M_GPIO_PORT_PACK(8, 9, PIN_CFG_GRP_SWIO_2 | RZV2M_MPXED_PIN_FUNCS), 894 RZV2M_GPIO_PORT_PACK(9, 10, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS), 895 RZV2M_GPIO_PORT_PACK(9, 11, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS), 896 RZV2M_GPIO_PORT_PACK(4, 12, PIN_CFG_GRP_3_3V | RZV2M_MPXED_PIN_FUNCS), 897 RZV2M_GPIO_PORT_PACK(12, 13, PIN_CFG_GRP_3_3V | RZV2M_MPXED_PIN_FUNCS), 898 RZV2M_GPIO_PORT_PACK(8, 14, PIN_CFG_GRP_3_3V | RZV2M_MPXED_PIN_FUNCS), 899 RZV2M_GPIO_PORT_PACK(16, 15, PIN_CFG_GRP_SWIO_2 | RZV2M_MPXED_PIN_FUNCS), 900 RZV2M_GPIO_PORT_PACK(14, 16, PIN_CFG_GRP_SWIO_2 | RZV2M_MPXED_PIN_FUNCS), 901 RZV2M_GPIO_PORT_PACK(1, 17, PIN_CFG_GRP_SWIO_2 | RZV2M_MPXED_PIN_FUNCS), 902 RZV2M_GPIO_PORT_PACK(0, 18, 0), 903 RZV2M_GPIO_PORT_PACK(0, 19, 0), 904 RZV2M_GPIO_PORT_PACK(3, 20, PIN_CFG_GRP_1_8V_2 | PIN_CFG_DRV), 905 RZV2M_GPIO_PORT_PACK(1, 21, PIN_CFG_GRP_SWIO_1 | PIN_CFG_DRV | PIN_CFG_SLEW), 906 }; 907 908 static const struct rzv2m_dedicated_configs rzv2m_dedicated_pins[] = { 909 { "NAWPN", RZV2M_SINGLE_PIN_PACK(0, 910 (PIN_CFG_GRP_SWIO_2 | PIN_CFG_DRV | PIN_CFG_SLEW)) }, 911 { "IM0CLK", RZV2M_SINGLE_PIN_PACK(1, 912 (PIN_CFG_GRP_SWIO_1 | PIN_CFG_DRV | PIN_CFG_SLEW)) }, 913 { "IM1CLK", RZV2M_SINGLE_PIN_PACK(2, 914 (PIN_CFG_GRP_SWIO_1 | PIN_CFG_DRV | PIN_CFG_SLEW)) }, 915 { "DETDO", RZV2M_SINGLE_PIN_PACK(5, 916 (PIN_CFG_GRP_1_8V_3 | PIN_CFG_DRV | PIN_CFG_SLEW)) }, 917 { "DETMS", RZV2M_SINGLE_PIN_PACK(6, 918 (PIN_CFG_GRP_1_8V_3 | PIN_CFG_DRV | PIN_CFG_SLEW)) }, 919 { "PCRSTOUTB", RZV2M_SINGLE_PIN_PACK(12, 920 (PIN_CFG_GRP_3_3V | PIN_CFG_DRV | PIN_CFG_SLEW)) }, 921 { "USPWEN", RZV2M_SINGLE_PIN_PACK(14, 922 (PIN_CFG_GRP_3_3V | PIN_CFG_DRV | PIN_CFG_SLEW)) }, 923 }; 924 925 static int rzv2m_gpio_register(struct rzv2m_pinctrl *pctrl) 926 { 927 struct device_node *np = pctrl->dev->of_node; 928 struct gpio_chip *chip = &pctrl->gpio_chip; 929 const char *name = dev_name(pctrl->dev); 930 struct of_phandle_args of_args; 931 int ret; 932 933 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args); 934 if (ret) { 935 dev_err(pctrl->dev, "Unable to parse gpio-ranges\n"); 936 return ret; 937 } 938 939 if (of_args.args[0] != 0 || of_args.args[1] != 0 || 940 of_args.args[2] != pctrl->data->n_port_pins) { 941 dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n"); 942 return -EINVAL; 943 } 944 945 chip->names = pctrl->data->port_pins; 946 chip->request = rzv2m_gpio_request; 947 chip->free = rzv2m_gpio_free; 948 chip->get_direction = rzv2m_gpio_get_direction; 949 chip->direction_input = rzv2m_gpio_direction_input; 950 chip->direction_output = rzv2m_gpio_direction_output; 951 chip->get = rzv2m_gpio_get; 952 chip->set = rzv2m_gpio_set; 953 chip->label = name; 954 chip->parent = pctrl->dev; 955 chip->owner = THIS_MODULE; 956 chip->base = -1; 957 chip->ngpio = of_args.args[2]; 958 959 pctrl->gpio_range.id = 0; 960 pctrl->gpio_range.pin_base = 0; 961 pctrl->gpio_range.base = 0; 962 pctrl->gpio_range.npins = chip->ngpio; 963 pctrl->gpio_range.name = chip->label; 964 pctrl->gpio_range.gc = chip; 965 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); 966 if (ret) { 967 dev_err(pctrl->dev, "failed to add GPIO controller\n"); 968 return ret; 969 } 970 971 dev_dbg(pctrl->dev, "Registered gpio controller\n"); 972 973 return 0; 974 } 975 976 static int rzv2m_pinctrl_register(struct rzv2m_pinctrl *pctrl) 977 { 978 struct pinctrl_pin_desc *pins; 979 unsigned int i, j; 980 u32 *pin_data; 981 int ret; 982 983 pctrl->desc.name = DRV_NAME; 984 pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins; 985 pctrl->desc.pctlops = &rzv2m_pinctrl_pctlops; 986 pctrl->desc.pmxops = &rzv2m_pinctrl_pmxops; 987 pctrl->desc.confops = &rzv2m_pinctrl_confops; 988 pctrl->desc.owner = THIS_MODULE; 989 990 pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL); 991 if (!pins) 992 return -ENOMEM; 993 994 pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins, 995 sizeof(*pin_data), GFP_KERNEL); 996 if (!pin_data) 997 return -ENOMEM; 998 999 pctrl->pins = pins; 1000 pctrl->desc.pins = pins; 1001 1002 for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) { 1003 pins[i].number = i; 1004 pins[i].name = pctrl->data->port_pins[i]; 1005 if (i && !(i % RZV2M_PINS_PER_PORT)) 1006 j++; 1007 pin_data[i] = pctrl->data->port_pin_configs[j]; 1008 pins[i].drv_data = &pin_data[i]; 1009 } 1010 1011 for (i = 0; i < pctrl->data->n_dedicated_pins; i++) { 1012 unsigned int index = pctrl->data->n_port_pins + i; 1013 1014 pins[index].number = index; 1015 pins[index].name = pctrl->data->dedicated_pins[i].name; 1016 pin_data[index] = pctrl->data->dedicated_pins[i].config; 1017 pins[index].drv_data = &pin_data[index]; 1018 } 1019 1020 ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl, 1021 &pctrl->pctl); 1022 if (ret) { 1023 dev_err(pctrl->dev, "pinctrl registration failed\n"); 1024 return ret; 1025 } 1026 1027 ret = pinctrl_enable(pctrl->pctl); 1028 if (ret) { 1029 dev_err(pctrl->dev, "pinctrl enable failed\n"); 1030 return ret; 1031 } 1032 1033 ret = rzv2m_gpio_register(pctrl); 1034 if (ret) { 1035 dev_err(pctrl->dev, "failed to add GPIO chip: %i\n", ret); 1036 return ret; 1037 } 1038 1039 return 0; 1040 } 1041 1042 static void rzv2m_pinctrl_clk_disable(void *data) 1043 { 1044 clk_disable_unprepare(data); 1045 } 1046 1047 static int rzv2m_pinctrl_probe(struct platform_device *pdev) 1048 { 1049 struct rzv2m_pinctrl *pctrl; 1050 int ret; 1051 1052 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 1053 if (!pctrl) 1054 return -ENOMEM; 1055 1056 pctrl->dev = &pdev->dev; 1057 1058 pctrl->data = of_device_get_match_data(&pdev->dev); 1059 if (!pctrl->data) 1060 return -EINVAL; 1061 1062 pctrl->base = devm_platform_ioremap_resource(pdev, 0); 1063 if (IS_ERR(pctrl->base)) 1064 return PTR_ERR(pctrl->base); 1065 1066 pctrl->clk = devm_clk_get(pctrl->dev, NULL); 1067 if (IS_ERR(pctrl->clk)) { 1068 ret = PTR_ERR(pctrl->clk); 1069 dev_err(pctrl->dev, "failed to get GPIO clk : %i\n", ret); 1070 return ret; 1071 } 1072 1073 spin_lock_init(&pctrl->lock); 1074 1075 platform_set_drvdata(pdev, pctrl); 1076 1077 ret = clk_prepare_enable(pctrl->clk); 1078 if (ret) { 1079 dev_err(pctrl->dev, "failed to enable GPIO clk: %i\n", ret); 1080 return ret; 1081 } 1082 1083 ret = devm_add_action_or_reset(&pdev->dev, rzv2m_pinctrl_clk_disable, 1084 pctrl->clk); 1085 if (ret) { 1086 dev_err(pctrl->dev, 1087 "failed to register GPIO clk disable action, %i\n", 1088 ret); 1089 return ret; 1090 } 1091 1092 ret = rzv2m_pinctrl_register(pctrl); 1093 if (ret) 1094 return ret; 1095 1096 dev_info(pctrl->dev, "%s support registered\n", DRV_NAME); 1097 return 0; 1098 } 1099 1100 static struct rzv2m_pinctrl_data r9a09g011_data = { 1101 .port_pins = rzv2m_gpio_names, 1102 .port_pin_configs = rzv2m_gpio_configs, 1103 .dedicated_pins = rzv2m_dedicated_pins, 1104 .n_port_pins = ARRAY_SIZE(rzv2m_gpio_configs) * RZV2M_PINS_PER_PORT, 1105 .n_dedicated_pins = ARRAY_SIZE(rzv2m_dedicated_pins), 1106 }; 1107 1108 static const struct of_device_id rzv2m_pinctrl_of_table[] = { 1109 { 1110 .compatible = "renesas,r9a09g011-pinctrl", 1111 .data = &r9a09g011_data, 1112 }, 1113 { /* sentinel */ } 1114 }; 1115 1116 static struct platform_driver rzv2m_pinctrl_driver = { 1117 .driver = { 1118 .name = DRV_NAME, 1119 .of_match_table = of_match_ptr(rzv2m_pinctrl_of_table), 1120 }, 1121 .probe = rzv2m_pinctrl_probe, 1122 }; 1123 1124 static int __init rzv2m_pinctrl_init(void) 1125 { 1126 return platform_driver_register(&rzv2m_pinctrl_driver); 1127 } 1128 core_initcall(rzv2m_pinctrl_init); 1129 1130 MODULE_AUTHOR("Phil Edworthy <phil.edworthy@renesas.com>"); 1131 MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/V2M"); 1132