1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas RZ/G2L Pin Control and GPIO driver core 4 * 5 * Copyright (C) 2021 Renesas Electronics Corporation. 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/clk.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/module.h> 14 #include <linux/of_device.h> 15 #include <linux/of_irq.h> 16 #include <linux/seq_file.h> 17 #include <linux/spinlock.h> 18 19 #include <linux/pinctrl/consumer.h> 20 #include <linux/pinctrl/pinconf-generic.h> 21 #include <linux/pinctrl/pinconf.h> 22 #include <linux/pinctrl/pinctrl.h> 23 #include <linux/pinctrl/pinmux.h> 24 25 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 26 27 #include "../core.h" 28 #include "../pinconf.h" 29 #include "../pinmux.h" 30 31 #define DRV_NAME "pinctrl-rzg2l" 32 33 /* 34 * Use 16 lower bits [15:0] for pin identifier 35 * Use 16 higher bits [31:16] for pin mux function 36 */ 37 #define MUX_PIN_ID_MASK GENMASK(15, 0) 38 #define MUX_FUNC_MASK GENMASK(31, 16) 39 #define MUX_FUNC_OFFS 16 40 #define MUX_FUNC(pinconf) (((pinconf) & MUX_FUNC_MASK) >> MUX_FUNC_OFFS) 41 42 /* PIN capabilities */ 43 #define PIN_CFG_IOLH_A BIT(0) 44 #define PIN_CFG_IOLH_B BIT(1) 45 #define PIN_CFG_SR BIT(2) 46 #define PIN_CFG_IEN BIT(3) 47 #define PIN_CFG_PUPD BIT(4) 48 #define PIN_CFG_IO_VMC_SD0 BIT(5) 49 #define PIN_CFG_IO_VMC_SD1 BIT(6) 50 #define PIN_CFG_IO_VMC_QSPI BIT(7) 51 #define PIN_CFG_IO_VMC_ETH0 BIT(8) 52 #define PIN_CFG_IO_VMC_ETH1 BIT(9) 53 #define PIN_CFG_FILONOFF BIT(10) 54 #define PIN_CFG_FILNUM BIT(11) 55 #define PIN_CFG_FILCLKSEL BIT(12) 56 57 #define RZG2L_MPXED_PIN_FUNCS (PIN_CFG_IOLH_A | \ 58 PIN_CFG_SR | \ 59 PIN_CFG_PUPD | \ 60 PIN_CFG_FILONOFF | \ 61 PIN_CFG_FILNUM | \ 62 PIN_CFG_FILCLKSEL) 63 64 #define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | \ 65 PIN_CFG_FILONOFF | \ 66 PIN_CFG_FILNUM | \ 67 PIN_CFG_FILCLKSEL) 68 69 /* 70 * n indicates number of pins in the port, a is the register index 71 * and f is pin configuration capabilities supported. 72 */ 73 #define RZG2L_GPIO_PORT_PACK(n, a, f) (((n) << 28) | ((a) << 20) | (f)) 74 #define RZG2L_GPIO_PORT_GET_PINCNT(x) (((x) & GENMASK(30, 28)) >> 28) 75 #define RZG2L_GPIO_PORT_GET_INDEX(x) (((x) & GENMASK(26, 20)) >> 20) 76 #define RZG2L_GPIO_PORT_GET_CFGS(x) ((x) & GENMASK(19, 0)) 77 78 /* 79 * BIT(31) indicates dedicated pin, p is the register index while 80 * referencing to SR/IEN/IOLH/FILxx registers, b is the register bits 81 * (b * 8) and f is the pin configuration capabilities supported. 82 */ 83 #define RZG2L_SINGLE_PIN BIT(31) 84 #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ 85 ((p) << 24) | ((b) << 20) | (f)) 86 #define RZG2L_SINGLE_PIN_GET_PORT_OFFSET(x) (((x) & GENMASK(30, 24)) >> 24) 87 #define RZG2L_SINGLE_PIN_GET_BIT(x) (((x) & GENMASK(22, 20)) >> 20) 88 #define RZG2L_SINGLE_PIN_GET_CFGS(x) ((x) & GENMASK(19, 0)) 89 90 #define P(n) (0x0000 + 0x10 + (n)) 91 #define PM(n) (0x0100 + 0x20 + (n) * 2) 92 #define PMC(n) (0x0200 + 0x10 + (n)) 93 #define PFC(n) (0x0400 + 0x40 + (n) * 4) 94 #define PIN(n) (0x0800 + 0x10 + (n)) 95 #define IOLH(n) (0x1000 + (n) * 8) 96 #define IEN(n) (0x1800 + (n) * 8) 97 #define ISEL(n) (0x2c80 + (n) * 8) 98 #define PWPR (0x3014) 99 #define SD_CH(n) (0x3000 + (n) * 4) 100 #define QSPI (0x3008) 101 102 #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */ 103 #define PVDD_3300 0 /* I/O domain voltage >= 3.3V */ 104 105 #define PWPR_B0WI BIT(7) /* Bit Write Disable */ 106 #define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */ 107 108 #define PM_MASK 0x03 109 #define PVDD_MASK 0x01 110 #define PFC_MASK 0x07 111 #define IEN_MASK 0x01 112 #define IOLH_MASK 0x03 113 114 #define PM_INPUT 0x1 115 #define PM_OUTPUT 0x2 116 117 #define RZG2L_PIN_ID_TO_PORT(id) ((id) / RZG2L_PINS_PER_PORT) 118 #define RZG2L_PIN_ID_TO_PORT_OFFSET(id) (RZG2L_PIN_ID_TO_PORT(id) + 0x10) 119 #define RZG2L_PIN_ID_TO_PIN(id) ((id) % RZG2L_PINS_PER_PORT) 120 121 #define RZG2L_TINT_MAX_INTERRUPT 32 122 #define RZG2L_TINT_IRQ_START_INDEX 9 123 #define RZG2L_PACK_HWIRQ(t, i) (((t) << 16) | (i)) 124 125 struct rzg2l_dedicated_configs { 126 const char *name; 127 u32 config; 128 }; 129 130 struct rzg2l_pinctrl_data { 131 const char * const *port_pins; 132 const u32 *port_pin_configs; 133 unsigned int n_ports; 134 struct rzg2l_dedicated_configs *dedicated_pins; 135 unsigned int n_port_pins; 136 unsigned int n_dedicated_pins; 137 }; 138 139 struct rzg2l_pinctrl { 140 struct pinctrl_dev *pctl; 141 struct pinctrl_desc desc; 142 struct pinctrl_pin_desc *pins; 143 144 const struct rzg2l_pinctrl_data *data; 145 void __iomem *base; 146 struct device *dev; 147 struct clk *clk; 148 149 struct gpio_chip gpio_chip; 150 struct pinctrl_gpio_range gpio_range; 151 DECLARE_BITMAP(tint_slot, RZG2L_TINT_MAX_INTERRUPT); 152 spinlock_t bitmap_lock; 153 unsigned int hwirq[RZG2L_TINT_MAX_INTERRUPT]; 154 155 spinlock_t lock; 156 }; 157 158 static const unsigned int iolh_groupa_mA[] = { 2, 4, 8, 12 }; 159 static const unsigned int iolh_groupb_oi[] = { 100, 66, 50, 33 }; 160 161 static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, 162 u8 port, u8 pin, u8 func) 163 { 164 unsigned long flags; 165 u32 reg; 166 167 spin_lock_irqsave(&pctrl->lock, flags); 168 169 /* Set pin to 'Non-use (Hi-Z input protection)' */ 170 reg = readw(pctrl->base + PM(port)); 171 reg &= ~(PM_MASK << (pin * 2)); 172 writew(reg, pctrl->base + PM(port)); 173 174 /* Temporarily switch to GPIO mode with PMC register */ 175 reg = readb(pctrl->base + PMC(port)); 176 writeb(reg & ~BIT(pin), pctrl->base + PMC(port)); 177 178 /* Set the PWPR register to allow PFC register to write */ 179 writel(0x0, pctrl->base + PWPR); /* B0WI=0, PFCWE=0 */ 180 writel(PWPR_PFCWE, pctrl->base + PWPR); /* B0WI=0, PFCWE=1 */ 181 182 /* Select Pin function mode with PFC register */ 183 reg = readl(pctrl->base + PFC(port)); 184 reg &= ~(PFC_MASK << (pin * 4)); 185 writel(reg | (func << (pin * 4)), pctrl->base + PFC(port)); 186 187 /* Set the PWPR register to be write-protected */ 188 writel(0x0, pctrl->base + PWPR); /* B0WI=0, PFCWE=0 */ 189 writel(PWPR_B0WI, pctrl->base + PWPR); /* B0WI=1, PFCWE=0 */ 190 191 /* Switch to Peripheral pin function with PMC register */ 192 reg = readb(pctrl->base + PMC(port)); 193 writeb(reg | BIT(pin), pctrl->base + PMC(port)); 194 195 spin_unlock_irqrestore(&pctrl->lock, flags); 196 }; 197 198 static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, 199 unsigned int func_selector, 200 unsigned int group_selector) 201 { 202 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 203 struct function_desc *func; 204 unsigned int i, *psel_val; 205 struct group_desc *group; 206 int *pins; 207 208 func = pinmux_generic_get_function(pctldev, func_selector); 209 if (!func) 210 return -EINVAL; 211 group = pinctrl_generic_get_group(pctldev, group_selector); 212 if (!group) 213 return -EINVAL; 214 215 psel_val = func->data; 216 pins = group->pins; 217 218 for (i = 0; i < group->num_pins; i++) { 219 dev_dbg(pctrl->dev, "port:%u pin: %u PSEL:%u\n", 220 RZG2L_PIN_ID_TO_PORT(pins[i]), RZG2L_PIN_ID_TO_PIN(pins[i]), 221 psel_val[i]); 222 rzg2l_pinctrl_set_pfc_mode(pctrl, RZG2L_PIN_ID_TO_PORT(pins[i]), 223 RZG2L_PIN_ID_TO_PIN(pins[i]), psel_val[i]); 224 } 225 226 return 0; 227 }; 228 229 static int rzg2l_map_add_config(struct pinctrl_map *map, 230 const char *group_or_pin, 231 enum pinctrl_map_type type, 232 unsigned long *configs, 233 unsigned int num_configs) 234 { 235 unsigned long *cfgs; 236 237 cfgs = kmemdup(configs, num_configs * sizeof(*cfgs), 238 GFP_KERNEL); 239 if (!cfgs) 240 return -ENOMEM; 241 242 map->type = type; 243 map->data.configs.group_or_pin = group_or_pin; 244 map->data.configs.configs = cfgs; 245 map->data.configs.num_configs = num_configs; 246 247 return 0; 248 } 249 250 static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev, 251 struct device_node *np, 252 struct pinctrl_map **map, 253 unsigned int *num_maps, 254 unsigned int *index) 255 { 256 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 257 struct pinctrl_map *maps = *map; 258 unsigned int nmaps = *num_maps; 259 unsigned long *configs = NULL; 260 unsigned int *pins, *psel_val; 261 unsigned int num_pinmux = 0; 262 unsigned int idx = *index; 263 unsigned int num_pins, i; 264 unsigned int num_configs; 265 struct property *pinmux; 266 struct property *prop; 267 int ret, gsel, fsel; 268 const char **pin_fn; 269 const char *pin; 270 271 pinmux = of_find_property(np, "pinmux", NULL); 272 if (pinmux) 273 num_pinmux = pinmux->length / sizeof(u32); 274 275 ret = of_property_count_strings(np, "pins"); 276 if (ret == -EINVAL) { 277 num_pins = 0; 278 } else if (ret < 0) { 279 dev_err(pctrl->dev, "Invalid pins list in DT\n"); 280 return ret; 281 } else { 282 num_pins = ret; 283 } 284 285 if (!num_pinmux && !num_pins) 286 return 0; 287 288 if (num_pinmux && num_pins) { 289 dev_err(pctrl->dev, 290 "DT node must contain either a pinmux or pins and not both\n"); 291 return -EINVAL; 292 } 293 294 ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs); 295 if (ret < 0) 296 return ret; 297 298 if (num_pins && !num_configs) { 299 dev_err(pctrl->dev, "DT node must contain a config\n"); 300 ret = -ENODEV; 301 goto done; 302 } 303 304 if (num_pinmux) 305 nmaps += 1; 306 307 if (num_pins) 308 nmaps += num_pins; 309 310 maps = krealloc_array(maps, nmaps, sizeof(*maps), GFP_KERNEL); 311 if (!maps) { 312 ret = -ENOMEM; 313 goto done; 314 } 315 316 *map = maps; 317 *num_maps = nmaps; 318 if (num_pins) { 319 of_property_for_each_string(np, "pins", prop, pin) { 320 ret = rzg2l_map_add_config(&maps[idx], pin, 321 PIN_MAP_TYPE_CONFIGS_PIN, 322 configs, num_configs); 323 if (ret < 0) 324 goto done; 325 326 idx++; 327 } 328 ret = 0; 329 goto done; 330 } 331 332 pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL); 333 psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val), 334 GFP_KERNEL); 335 pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL); 336 if (!pins || !psel_val || !pin_fn) { 337 ret = -ENOMEM; 338 goto done; 339 } 340 341 /* Collect pin locations and mux settings from DT properties */ 342 for (i = 0; i < num_pinmux; ++i) { 343 u32 value; 344 345 ret = of_property_read_u32_index(np, "pinmux", i, &value); 346 if (ret) 347 goto done; 348 pins[i] = value & MUX_PIN_ID_MASK; 349 psel_val[i] = MUX_FUNC(value); 350 } 351 352 /* Register a single pin group listing all the pins we read from DT */ 353 gsel = pinctrl_generic_add_group(pctldev, np->name, pins, num_pinmux, NULL); 354 if (gsel < 0) { 355 ret = gsel; 356 goto done; 357 } 358 359 /* 360 * Register a single group function where the 'data' is an array PSEL 361 * register values read from DT. 362 */ 363 pin_fn[0] = np->name; 364 fsel = pinmux_generic_add_function(pctldev, np->name, pin_fn, 1, 365 psel_val); 366 if (fsel < 0) { 367 ret = fsel; 368 goto remove_group; 369 } 370 371 maps[idx].type = PIN_MAP_TYPE_MUX_GROUP; 372 maps[idx].data.mux.group = np->name; 373 maps[idx].data.mux.function = np->name; 374 idx++; 375 376 dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux); 377 ret = 0; 378 goto done; 379 380 remove_group: 381 pinctrl_generic_remove_group(pctldev, gsel); 382 done: 383 *index = idx; 384 kfree(configs); 385 return ret; 386 } 387 388 static void rzg2l_dt_free_map(struct pinctrl_dev *pctldev, 389 struct pinctrl_map *map, 390 unsigned int num_maps) 391 { 392 unsigned int i; 393 394 if (!map) 395 return; 396 397 for (i = 0; i < num_maps; ++i) { 398 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP || 399 map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) 400 kfree(map[i].data.configs.configs); 401 } 402 kfree(map); 403 } 404 405 static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev, 406 struct device_node *np, 407 struct pinctrl_map **map, 408 unsigned int *num_maps) 409 { 410 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 411 struct device_node *child; 412 unsigned int index; 413 int ret; 414 415 *map = NULL; 416 *num_maps = 0; 417 index = 0; 418 419 for_each_child_of_node(np, child) { 420 ret = rzg2l_dt_subnode_to_map(pctldev, child, map, 421 num_maps, &index); 422 if (ret < 0) { 423 of_node_put(child); 424 goto done; 425 } 426 } 427 428 if (*num_maps == 0) { 429 ret = rzg2l_dt_subnode_to_map(pctldev, np, map, 430 num_maps, &index); 431 if (ret < 0) 432 goto done; 433 } 434 435 if (*num_maps) 436 return 0; 437 438 dev_err(pctrl->dev, "no mapping found in node %pOF\n", np); 439 ret = -EINVAL; 440 441 done: 442 rzg2l_dt_free_map(pctldev, *map, *num_maps); 443 444 return ret; 445 } 446 447 static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl, 448 u32 cfg, u32 port, u8 bit) 449 { 450 u8 pincount = RZG2L_GPIO_PORT_GET_PINCNT(cfg); 451 u32 port_index = RZG2L_GPIO_PORT_GET_INDEX(cfg); 452 u32 data; 453 454 if (bit >= pincount || port >= pctrl->data->n_port_pins) 455 return -EINVAL; 456 457 data = pctrl->data->port_pin_configs[port]; 458 if (port_index != RZG2L_GPIO_PORT_GET_INDEX(data)) 459 return -EINVAL; 460 461 return 0; 462 } 463 464 static u32 rzg2l_read_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, 465 u8 bit, u32 mask) 466 { 467 void __iomem *addr = pctrl->base + offset; 468 469 /* handle _L/_H for 32-bit register read/write */ 470 if (bit >= 4) { 471 bit -= 4; 472 addr += 4; 473 } 474 475 return (readl(addr) >> (bit * 8)) & mask; 476 } 477 478 static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, 479 u8 bit, u32 mask, u32 val) 480 { 481 void __iomem *addr = pctrl->base + offset; 482 unsigned long flags; 483 u32 reg; 484 485 /* handle _L/_H for 32-bit register read/write */ 486 if (bit >= 4) { 487 bit -= 4; 488 addr += 4; 489 } 490 491 spin_lock_irqsave(&pctrl->lock, flags); 492 reg = readl(addr) & ~(mask << (bit * 8)); 493 writel(reg | (val << (bit * 8)), addr); 494 spin_unlock_irqrestore(&pctrl->lock, flags); 495 } 496 497 static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, 498 unsigned int _pin, 499 unsigned long *config) 500 { 501 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 502 enum pin_config_param param = pinconf_to_config_param(*config); 503 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; 504 unsigned int *pin_data = pin->drv_data; 505 unsigned int arg = 0; 506 unsigned long flags; 507 void __iomem *addr; 508 u32 port_offset; 509 u32 cfg = 0; 510 u8 bit = 0; 511 512 if (!pin_data) 513 return -EINVAL; 514 515 if (*pin_data & RZG2L_SINGLE_PIN) { 516 port_offset = RZG2L_SINGLE_PIN_GET_PORT_OFFSET(*pin_data); 517 cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data); 518 bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data); 519 } else { 520 cfg = RZG2L_GPIO_PORT_GET_CFGS(*pin_data); 521 port_offset = RZG2L_PIN_ID_TO_PORT_OFFSET(_pin); 522 bit = RZG2L_PIN_ID_TO_PIN(_pin); 523 524 if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) 525 return -EINVAL; 526 } 527 528 switch (param) { 529 case PIN_CONFIG_INPUT_ENABLE: 530 if (!(cfg & PIN_CFG_IEN)) 531 return -EINVAL; 532 arg = rzg2l_read_pin_config(pctrl, IEN(port_offset), bit, IEN_MASK); 533 if (!arg) 534 return -EINVAL; 535 break; 536 537 case PIN_CONFIG_POWER_SOURCE: { 538 u32 pwr_reg = 0x0; 539 540 if (cfg & PIN_CFG_IO_VMC_SD0) 541 pwr_reg = SD_CH(0); 542 else if (cfg & PIN_CFG_IO_VMC_SD1) 543 pwr_reg = SD_CH(1); 544 else if (cfg & PIN_CFG_IO_VMC_QSPI) 545 pwr_reg = QSPI; 546 else 547 return -EINVAL; 548 549 spin_lock_irqsave(&pctrl->lock, flags); 550 addr = pctrl->base + pwr_reg; 551 arg = (readl(addr) & PVDD_MASK) ? 1800 : 3300; 552 spin_unlock_irqrestore(&pctrl->lock, flags); 553 break; 554 } 555 556 case PIN_CONFIG_DRIVE_STRENGTH: { 557 unsigned int index; 558 559 if (!(cfg & PIN_CFG_IOLH_A)) 560 return -EINVAL; 561 562 index = rzg2l_read_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK); 563 arg = iolh_groupa_mA[index]; 564 break; 565 } 566 567 case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: { 568 unsigned int index; 569 570 if (!(cfg & PIN_CFG_IOLH_B)) 571 return -EINVAL; 572 573 index = rzg2l_read_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK); 574 arg = iolh_groupb_oi[index]; 575 break; 576 } 577 578 default: 579 return -ENOTSUPP; 580 } 581 582 *config = pinconf_to_config_packed(param, arg); 583 584 return 0; 585 }; 586 587 static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, 588 unsigned int _pin, 589 unsigned long *_configs, 590 unsigned int num_configs) 591 { 592 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 593 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; 594 unsigned int *pin_data = pin->drv_data; 595 enum pin_config_param param; 596 unsigned long flags; 597 void __iomem *addr; 598 u32 port_offset; 599 unsigned int i; 600 u32 cfg = 0; 601 u8 bit = 0; 602 603 if (!pin_data) 604 return -EINVAL; 605 606 if (*pin_data & RZG2L_SINGLE_PIN) { 607 port_offset = RZG2L_SINGLE_PIN_GET_PORT_OFFSET(*pin_data); 608 cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data); 609 bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data); 610 } else { 611 cfg = RZG2L_GPIO_PORT_GET_CFGS(*pin_data); 612 port_offset = RZG2L_PIN_ID_TO_PORT_OFFSET(_pin); 613 bit = RZG2L_PIN_ID_TO_PIN(_pin); 614 615 if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) 616 return -EINVAL; 617 } 618 619 for (i = 0; i < num_configs; i++) { 620 param = pinconf_to_config_param(_configs[i]); 621 switch (param) { 622 case PIN_CONFIG_INPUT_ENABLE: { 623 unsigned int arg = 624 pinconf_to_config_argument(_configs[i]); 625 626 if (!(cfg & PIN_CFG_IEN)) 627 return -EINVAL; 628 629 rzg2l_rmw_pin_config(pctrl, IEN(port_offset), bit, IEN_MASK, !!arg); 630 break; 631 } 632 633 case PIN_CONFIG_POWER_SOURCE: { 634 unsigned int mV = pinconf_to_config_argument(_configs[i]); 635 u32 pwr_reg = 0x0; 636 637 if (mV != 1800 && mV != 3300) 638 return -EINVAL; 639 640 if (cfg & PIN_CFG_IO_VMC_SD0) 641 pwr_reg = SD_CH(0); 642 else if (cfg & PIN_CFG_IO_VMC_SD1) 643 pwr_reg = SD_CH(1); 644 else if (cfg & PIN_CFG_IO_VMC_QSPI) 645 pwr_reg = QSPI; 646 else 647 return -EINVAL; 648 649 addr = pctrl->base + pwr_reg; 650 spin_lock_irqsave(&pctrl->lock, flags); 651 writel((mV == 1800) ? PVDD_1800 : PVDD_3300, addr); 652 spin_unlock_irqrestore(&pctrl->lock, flags); 653 break; 654 } 655 656 case PIN_CONFIG_DRIVE_STRENGTH: { 657 unsigned int arg = pinconf_to_config_argument(_configs[i]); 658 unsigned int index; 659 660 if (!(cfg & PIN_CFG_IOLH_A)) 661 return -EINVAL; 662 663 for (index = 0; index < ARRAY_SIZE(iolh_groupa_mA); index++) { 664 if (arg == iolh_groupa_mA[index]) 665 break; 666 } 667 if (index >= ARRAY_SIZE(iolh_groupa_mA)) 668 return -EINVAL; 669 670 rzg2l_rmw_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK, index); 671 break; 672 } 673 674 case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: { 675 unsigned int arg = pinconf_to_config_argument(_configs[i]); 676 unsigned int index; 677 678 if (!(cfg & PIN_CFG_IOLH_B)) 679 return -EINVAL; 680 681 for (index = 0; index < ARRAY_SIZE(iolh_groupb_oi); index++) { 682 if (arg == iolh_groupb_oi[index]) 683 break; 684 } 685 if (index >= ARRAY_SIZE(iolh_groupb_oi)) 686 return -EINVAL; 687 688 rzg2l_rmw_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK, index); 689 break; 690 } 691 692 default: 693 return -EOPNOTSUPP; 694 } 695 } 696 697 return 0; 698 } 699 700 static int rzg2l_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev, 701 unsigned int group, 702 unsigned long *configs, 703 unsigned int num_configs) 704 { 705 const unsigned int *pins; 706 unsigned int i, npins; 707 int ret; 708 709 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 710 if (ret) 711 return ret; 712 713 for (i = 0; i < npins; i++) { 714 ret = rzg2l_pinctrl_pinconf_set(pctldev, pins[i], configs, 715 num_configs); 716 if (ret) 717 return ret; 718 } 719 720 return 0; 721 }; 722 723 static int rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev, 724 unsigned int group, 725 unsigned long *config) 726 { 727 const unsigned int *pins; 728 unsigned int i, npins, prev_config = 0; 729 int ret; 730 731 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 732 if (ret) 733 return ret; 734 735 for (i = 0; i < npins; i++) { 736 ret = rzg2l_pinctrl_pinconf_get(pctldev, pins[i], config); 737 if (ret) 738 return ret; 739 740 /* Check config matching between to pin */ 741 if (i && prev_config != *config) 742 return -EOPNOTSUPP; 743 744 prev_config = *config; 745 } 746 747 return 0; 748 }; 749 750 static const struct pinctrl_ops rzg2l_pinctrl_pctlops = { 751 .get_groups_count = pinctrl_generic_get_group_count, 752 .get_group_name = pinctrl_generic_get_group_name, 753 .get_group_pins = pinctrl_generic_get_group_pins, 754 .dt_node_to_map = rzg2l_dt_node_to_map, 755 .dt_free_map = rzg2l_dt_free_map, 756 }; 757 758 static const struct pinmux_ops rzg2l_pinctrl_pmxops = { 759 .get_functions_count = pinmux_generic_get_function_count, 760 .get_function_name = pinmux_generic_get_function_name, 761 .get_function_groups = pinmux_generic_get_function_groups, 762 .set_mux = rzg2l_pinctrl_set_mux, 763 .strict = true, 764 }; 765 766 static const struct pinconf_ops rzg2l_pinctrl_confops = { 767 .is_generic = true, 768 .pin_config_get = rzg2l_pinctrl_pinconf_get, 769 .pin_config_set = rzg2l_pinctrl_pinconf_set, 770 .pin_config_group_set = rzg2l_pinctrl_pinconf_group_set, 771 .pin_config_group_get = rzg2l_pinctrl_pinconf_group_get, 772 .pin_config_config_dbg_show = pinconf_generic_dump_config, 773 }; 774 775 static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset) 776 { 777 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 778 u32 port = RZG2L_PIN_ID_TO_PORT(offset); 779 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 780 unsigned long flags; 781 u8 reg8; 782 int ret; 783 784 ret = pinctrl_gpio_request(chip->base + offset); 785 if (ret) 786 return ret; 787 788 spin_lock_irqsave(&pctrl->lock, flags); 789 790 /* Select GPIO mode in PMC Register */ 791 reg8 = readb(pctrl->base + PMC(port)); 792 reg8 &= ~BIT(bit); 793 writeb(reg8, pctrl->base + PMC(port)); 794 795 spin_unlock_irqrestore(&pctrl->lock, flags); 796 797 return 0; 798 } 799 800 static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 port, 801 u8 bit, bool output) 802 { 803 unsigned long flags; 804 u16 reg16; 805 806 spin_lock_irqsave(&pctrl->lock, flags); 807 808 reg16 = readw(pctrl->base + PM(port)); 809 reg16 &= ~(PM_MASK << (bit * 2)); 810 811 reg16 |= (output ? PM_OUTPUT : PM_INPUT) << (bit * 2); 812 writew(reg16, pctrl->base + PM(port)); 813 814 spin_unlock_irqrestore(&pctrl->lock, flags); 815 } 816 817 static int rzg2l_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 818 { 819 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 820 u32 port = RZG2L_PIN_ID_TO_PORT(offset); 821 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 822 823 if (!(readb(pctrl->base + PMC(port)) & BIT(bit))) { 824 u16 reg16; 825 826 reg16 = readw(pctrl->base + PM(port)); 827 reg16 = (reg16 >> (bit * 2)) & PM_MASK; 828 if (reg16 == PM_OUTPUT) 829 return GPIO_LINE_DIRECTION_OUT; 830 } 831 832 return GPIO_LINE_DIRECTION_IN; 833 } 834 835 static int rzg2l_gpio_direction_input(struct gpio_chip *chip, 836 unsigned int offset) 837 { 838 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 839 u32 port = RZG2L_PIN_ID_TO_PORT(offset); 840 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 841 842 rzg2l_gpio_set_direction(pctrl, port, bit, false); 843 844 return 0; 845 } 846 847 static void rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset, 848 int value) 849 { 850 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 851 u32 port = RZG2L_PIN_ID_TO_PORT(offset); 852 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 853 unsigned long flags; 854 u8 reg8; 855 856 spin_lock_irqsave(&pctrl->lock, flags); 857 858 reg8 = readb(pctrl->base + P(port)); 859 860 if (value) 861 writeb(reg8 | BIT(bit), pctrl->base + P(port)); 862 else 863 writeb(reg8 & ~BIT(bit), pctrl->base + P(port)); 864 865 spin_unlock_irqrestore(&pctrl->lock, flags); 866 } 867 868 static int rzg2l_gpio_direction_output(struct gpio_chip *chip, 869 unsigned int offset, int value) 870 { 871 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 872 u32 port = RZG2L_PIN_ID_TO_PORT(offset); 873 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 874 875 rzg2l_gpio_set(chip, offset, value); 876 rzg2l_gpio_set_direction(pctrl, port, bit, true); 877 878 return 0; 879 } 880 881 static int rzg2l_gpio_get(struct gpio_chip *chip, unsigned int offset) 882 { 883 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 884 u32 port = RZG2L_PIN_ID_TO_PORT(offset); 885 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 886 u16 reg16; 887 888 reg16 = readw(pctrl->base + PM(port)); 889 reg16 = (reg16 >> (bit * 2)) & PM_MASK; 890 891 if (reg16 == PM_INPUT) 892 return !!(readb(pctrl->base + PIN(port)) & BIT(bit)); 893 else if (reg16 == PM_OUTPUT) 894 return !!(readb(pctrl->base + P(port)) & BIT(bit)); 895 else 896 return -EINVAL; 897 } 898 899 static void rzg2l_gpio_free(struct gpio_chip *chip, unsigned int offset) 900 { 901 unsigned int virq; 902 903 pinctrl_gpio_free(chip->base + offset); 904 905 virq = irq_find_mapping(chip->irq.domain, offset); 906 if (virq) 907 irq_dispose_mapping(virq); 908 909 /* 910 * Set the GPIO as an input to ensure that the next GPIO request won't 911 * drive the GPIO pin as an output. 912 */ 913 rzg2l_gpio_direction_input(chip, offset); 914 } 915 916 static const char * const rzg2l_gpio_names[] = { 917 "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7", 918 "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7", 919 "P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7", 920 "P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7", 921 "P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7", 922 "P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7", 923 "P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7", 924 "P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7", 925 "P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7", 926 "P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7", 927 "P10_0", "P10_1", "P10_2", "P10_3", "P10_4", "P10_5", "P10_6", "P10_7", 928 "P11_0", "P11_1", "P11_2", "P11_3", "P11_4", "P11_5", "P11_6", "P11_7", 929 "P12_0", "P12_1", "P12_2", "P12_3", "P12_4", "P12_5", "P12_6", "P12_7", 930 "P13_0", "P13_1", "P13_2", "P13_3", "P13_4", "P13_5", "P13_6", "P13_7", 931 "P14_0", "P14_1", "P14_2", "P14_3", "P14_4", "P14_5", "P14_6", "P14_7", 932 "P15_0", "P15_1", "P15_2", "P15_3", "P15_4", "P15_5", "P15_6", "P15_7", 933 "P16_0", "P16_1", "P16_2", "P16_3", "P16_4", "P16_5", "P16_6", "P16_7", 934 "P17_0", "P17_1", "P17_2", "P17_3", "P17_4", "P17_5", "P17_6", "P17_7", 935 "P18_0", "P18_1", "P18_2", "P18_3", "P18_4", "P18_5", "P18_6", "P18_7", 936 "P19_0", "P19_1", "P19_2", "P19_3", "P19_4", "P19_5", "P19_6", "P19_7", 937 "P20_0", "P20_1", "P20_2", "P20_3", "P20_4", "P20_5", "P20_6", "P20_7", 938 "P21_0", "P21_1", "P21_2", "P21_3", "P21_4", "P21_5", "P21_6", "P21_7", 939 "P22_0", "P22_1", "P22_2", "P22_3", "P22_4", "P22_5", "P22_6", "P22_7", 940 "P23_0", "P23_1", "P23_2", "P23_3", "P23_4", "P23_5", "P23_6", "P23_7", 941 "P24_0", "P24_1", "P24_2", "P24_3", "P24_4", "P24_5", "P24_6", "P24_7", 942 "P25_0", "P25_1", "P25_2", "P25_3", "P25_4", "P25_5", "P25_6", "P25_7", 943 "P26_0", "P26_1", "P26_2", "P26_3", "P26_4", "P26_5", "P26_6", "P26_7", 944 "P27_0", "P27_1", "P27_2", "P27_3", "P27_4", "P27_5", "P27_6", "P27_7", 945 "P28_0", "P28_1", "P28_2", "P28_3", "P28_4", "P28_5", "P28_6", "P28_7", 946 "P29_0", "P29_1", "P29_2", "P29_3", "P29_4", "P29_5", "P29_6", "P29_7", 947 "P30_0", "P30_1", "P30_2", "P30_3", "P30_4", "P30_5", "P30_6", "P30_7", 948 "P31_0", "P31_1", "P31_2", "P31_3", "P31_4", "P31_5", "P31_6", "P31_7", 949 "P32_0", "P32_1", "P32_2", "P32_3", "P32_4", "P32_5", "P32_6", "P32_7", 950 "P33_0", "P33_1", "P33_2", "P33_3", "P33_4", "P33_5", "P33_6", "P33_7", 951 "P34_0", "P34_1", "P34_2", "P34_3", "P34_4", "P34_5", "P34_6", "P34_7", 952 "P35_0", "P35_1", "P35_2", "P35_3", "P35_4", "P35_5", "P35_6", "P35_7", 953 "P36_0", "P36_1", "P36_2", "P36_3", "P36_4", "P36_5", "P36_6", "P36_7", 954 "P37_0", "P37_1", "P37_2", "P37_3", "P37_4", "P37_5", "P37_6", "P37_7", 955 "P38_0", "P38_1", "P38_2", "P38_3", "P38_4", "P38_5", "P38_6", "P38_7", 956 "P39_0", "P39_1", "P39_2", "P39_3", "P39_4", "P39_5", "P39_6", "P39_7", 957 "P40_0", "P40_1", "P40_2", "P40_3", "P40_4", "P40_5", "P40_6", "P40_7", 958 "P41_0", "P41_1", "P41_2", "P41_3", "P41_4", "P41_5", "P41_6", "P41_7", 959 "P42_0", "P42_1", "P42_2", "P42_3", "P42_4", "P42_5", "P42_6", "P42_7", 960 "P43_0", "P43_1", "P43_2", "P43_3", "P43_4", "P43_5", "P43_6", "P43_7", 961 "P44_0", "P44_1", "P44_2", "P44_3", "P44_4", "P44_5", "P44_6", "P44_7", 962 "P45_0", "P45_1", "P45_2", "P45_3", "P45_4", "P45_5", "P45_6", "P45_7", 963 "P46_0", "P46_1", "P46_2", "P46_3", "P46_4", "P46_5", "P46_6", "P46_7", 964 "P47_0", "P47_1", "P47_2", "P47_3", "P47_4", "P47_5", "P47_6", "P47_7", 965 "P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6", "P48_7", 966 }; 967 968 static const u32 rzg2l_gpio_configs[] = { 969 RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS), 970 RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS), 971 RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS), 972 RZG2L_GPIO_PORT_PACK(2, 0x13, RZG2L_MPXED_PIN_FUNCS), 973 RZG2L_GPIO_PORT_PACK(2, 0x14, RZG2L_MPXED_PIN_FUNCS), 974 RZG2L_GPIO_PORT_PACK(3, 0x15, RZG2L_MPXED_PIN_FUNCS), 975 RZG2L_GPIO_PORT_PACK(2, 0x16, RZG2L_MPXED_PIN_FUNCS), 976 RZG2L_GPIO_PORT_PACK(3, 0x17, RZG2L_MPXED_PIN_FUNCS), 977 RZG2L_GPIO_PORT_PACK(3, 0x18, RZG2L_MPXED_PIN_FUNCS), 978 RZG2L_GPIO_PORT_PACK(2, 0x19, RZG2L_MPXED_PIN_FUNCS), 979 RZG2L_GPIO_PORT_PACK(2, 0x1a, RZG2L_MPXED_PIN_FUNCS), 980 RZG2L_GPIO_PORT_PACK(2, 0x1b, RZG2L_MPXED_PIN_FUNCS), 981 RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS), 982 RZG2L_GPIO_PORT_PACK(3, 0x1d, RZG2L_MPXED_PIN_FUNCS), 983 RZG2L_GPIO_PORT_PACK(2, 0x1e, RZG2L_MPXED_PIN_FUNCS), 984 RZG2L_GPIO_PORT_PACK(2, 0x1f, RZG2L_MPXED_PIN_FUNCS), 985 RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), 986 RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS), 987 RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS), 988 RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS), 989 RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 990 RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 991 RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 992 RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 993 RZG2L_GPIO_PORT_PACK(2, 0x28, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 994 RZG2L_GPIO_PORT_PACK(2, 0x29, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 995 RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 996 RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 997 RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 998 RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 999 RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1000 RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1001 RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1002 RZG2L_GPIO_PORT_PACK(2, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1003 RZG2L_GPIO_PORT_PACK(2, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1004 RZG2L_GPIO_PORT_PACK(2, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1005 RZG2L_GPIO_PORT_PACK(2, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1006 RZG2L_GPIO_PORT_PACK(3, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1007 RZG2L_GPIO_PORT_PACK(2, 0x36, RZG2L_MPXED_PIN_FUNCS), 1008 RZG2L_GPIO_PORT_PACK(3, 0x37, RZG2L_MPXED_PIN_FUNCS), 1009 RZG2L_GPIO_PORT_PACK(3, 0x38, RZG2L_MPXED_PIN_FUNCS), 1010 RZG2L_GPIO_PORT_PACK(2, 0x39, RZG2L_MPXED_PIN_FUNCS), 1011 RZG2L_GPIO_PORT_PACK(5, 0x3a, RZG2L_MPXED_PIN_FUNCS), 1012 RZG2L_GPIO_PORT_PACK(4, 0x3b, RZG2L_MPXED_PIN_FUNCS), 1013 RZG2L_GPIO_PORT_PACK(4, 0x3c, RZG2L_MPXED_PIN_FUNCS), 1014 RZG2L_GPIO_PORT_PACK(4, 0x3d, RZG2L_MPXED_PIN_FUNCS), 1015 RZG2L_GPIO_PORT_PACK(4, 0x3e, RZG2L_MPXED_PIN_FUNCS), 1016 RZG2L_GPIO_PORT_PACK(4, 0x3f, RZG2L_MPXED_PIN_FUNCS), 1017 RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS), 1018 }; 1019 1020 static const u32 r9a07g043_gpio_configs[] = { 1021 RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS), 1022 RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1023 RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1024 RZG2L_GPIO_PORT_PACK(4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1025 RZG2L_GPIO_PORT_PACK(6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1026 RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS), 1027 RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS), 1028 RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1029 RZG2L_GPIO_PORT_PACK(5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1030 RZG2L_GPIO_PORT_PACK(4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1031 RZG2L_GPIO_PORT_PACK(5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1032 RZG2L_GPIO_PORT_PACK(4, 0x1b, RZG2L_MPXED_PIN_FUNCS), 1033 RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS), 1034 RZG2L_GPIO_PORT_PACK(5, 0x1d, RZG2L_MPXED_PIN_FUNCS), 1035 RZG2L_GPIO_PORT_PACK(3, 0x1e, RZG2L_MPXED_PIN_FUNCS), 1036 RZG2L_GPIO_PORT_PACK(4, 0x1f, RZG2L_MPXED_PIN_FUNCS), 1037 RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), 1038 RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS), 1039 RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS), 1040 }; 1041 1042 static struct { 1043 struct rzg2l_dedicated_configs common[35]; 1044 struct rzg2l_dedicated_configs rzg2l_pins[7]; 1045 } rzg2l_dedicated_pins = { 1046 .common = { 1047 { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, 1048 (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) }, 1049 { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0, 1050 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) }, 1051 { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0, 1052 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) }, 1053 { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) }, 1054 { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) }, 1055 { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0, 1056 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, 1057 { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1, 1058 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1059 { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2, 1060 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, 1061 { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0, 1062 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1063 { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1, 1064 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1065 { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2, 1066 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1067 { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3, 1068 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1069 { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4, 1070 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1071 { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5, 1072 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1073 { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6, 1074 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1075 { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x7, 7, 1076 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1077 { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0, 1078 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1)) }, 1079 { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x8, 1, 1080 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 1081 { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x9, 0, 1082 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 1083 { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x9, 1, 1084 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 1085 { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x9, 2, 1086 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 1087 { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x9, 3, 1088 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 1089 { "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0, 1090 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1091 { "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1, 1092 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1093 { "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2, 1094 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1095 { "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3, 1096 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1097 { "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4, 1098 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1099 { "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5, 1100 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1101 { "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0, 1102 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1103 { "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1, 1104 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1105 { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) }, 1106 { "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) }, 1107 { "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) }, 1108 { "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) }, 1109 { "RIIC1_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 3, PIN_CFG_IEN) }, 1110 }, 1111 .rzg2l_pins = { 1112 { "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1113 { "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, 1114 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1115 { "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1, 1116 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1117 { "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2, 1118 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1119 { "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3, 1120 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1121 { "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4, 1122 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1123 { "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5, 1124 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1125 } 1126 }; 1127 1128 static int rzg2l_gpio_get_gpioint(unsigned int virq, const struct rzg2l_pinctrl_data *data) 1129 { 1130 unsigned int gpioint; 1131 unsigned int i; 1132 u32 port, bit; 1133 1134 port = virq / 8; 1135 bit = virq % 8; 1136 1137 if (port >= data->n_ports || 1138 bit >= RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[port])) 1139 return -EINVAL; 1140 1141 gpioint = bit; 1142 for (i = 0; i < port; i++) 1143 gpioint += RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[i]); 1144 1145 return gpioint; 1146 } 1147 1148 static void rzg2l_gpio_irq_disable(struct irq_data *d) 1149 { 1150 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1151 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); 1152 unsigned int hwirq = irqd_to_hwirq(d); 1153 unsigned long flags; 1154 void __iomem *addr; 1155 u32 port; 1156 u8 bit; 1157 1158 port = RZG2L_PIN_ID_TO_PORT(hwirq); 1159 bit = RZG2L_PIN_ID_TO_PIN(hwirq); 1160 1161 addr = pctrl->base + ISEL(port); 1162 if (bit >= 4) { 1163 bit -= 4; 1164 addr += 4; 1165 } 1166 1167 spin_lock_irqsave(&pctrl->lock, flags); 1168 writel(readl(addr) & ~BIT(bit * 8), addr); 1169 spin_unlock_irqrestore(&pctrl->lock, flags); 1170 1171 gpiochip_disable_irq(gc, hwirq); 1172 irq_chip_disable_parent(d); 1173 } 1174 1175 static void rzg2l_gpio_irq_enable(struct irq_data *d) 1176 { 1177 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1178 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); 1179 unsigned int hwirq = irqd_to_hwirq(d); 1180 unsigned long flags; 1181 void __iomem *addr; 1182 u32 port; 1183 u8 bit; 1184 1185 gpiochip_enable_irq(gc, hwirq); 1186 1187 port = RZG2L_PIN_ID_TO_PORT(hwirq); 1188 bit = RZG2L_PIN_ID_TO_PIN(hwirq); 1189 1190 addr = pctrl->base + ISEL(port); 1191 if (bit >= 4) { 1192 bit -= 4; 1193 addr += 4; 1194 } 1195 1196 spin_lock_irqsave(&pctrl->lock, flags); 1197 writel(readl(addr) | BIT(bit * 8), addr); 1198 spin_unlock_irqrestore(&pctrl->lock, flags); 1199 1200 irq_chip_enable_parent(d); 1201 } 1202 1203 static int rzg2l_gpio_irq_set_type(struct irq_data *d, unsigned int type) 1204 { 1205 return irq_chip_set_type_parent(d, type); 1206 } 1207 1208 static void rzg2l_gpio_irqc_eoi(struct irq_data *d) 1209 { 1210 irq_chip_eoi_parent(d); 1211 } 1212 1213 static void rzg2l_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p) 1214 { 1215 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 1216 1217 seq_printf(p, dev_name(gc->parent)); 1218 } 1219 1220 static const struct irq_chip rzg2l_gpio_irqchip = { 1221 .name = "rzg2l-gpio", 1222 .irq_disable = rzg2l_gpio_irq_disable, 1223 .irq_enable = rzg2l_gpio_irq_enable, 1224 .irq_mask = irq_chip_mask_parent, 1225 .irq_unmask = irq_chip_unmask_parent, 1226 .irq_set_type = rzg2l_gpio_irq_set_type, 1227 .irq_eoi = rzg2l_gpio_irqc_eoi, 1228 .irq_print_chip = rzg2l_gpio_irq_print_chip, 1229 .flags = IRQCHIP_IMMUTABLE, 1230 GPIOCHIP_IRQ_RESOURCE_HELPERS, 1231 }; 1232 1233 static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, 1234 unsigned int child, 1235 unsigned int child_type, 1236 unsigned int *parent, 1237 unsigned int *parent_type) 1238 { 1239 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc); 1240 unsigned long flags; 1241 int gpioint, irq; 1242 1243 gpioint = rzg2l_gpio_get_gpioint(child, pctrl->data); 1244 if (gpioint < 0) 1245 return gpioint; 1246 1247 spin_lock_irqsave(&pctrl->bitmap_lock, flags); 1248 irq = bitmap_find_free_region(pctrl->tint_slot, RZG2L_TINT_MAX_INTERRUPT, get_order(1)); 1249 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); 1250 if (irq < 0) 1251 return -ENOSPC; 1252 pctrl->hwirq[irq] = child; 1253 irq += RZG2L_TINT_IRQ_START_INDEX; 1254 1255 /* All these interrupts are level high in the CPU */ 1256 *parent_type = IRQ_TYPE_LEVEL_HIGH; 1257 *parent = RZG2L_PACK_HWIRQ(gpioint, irq); 1258 return 0; 1259 } 1260 1261 static int rzg2l_gpio_populate_parent_fwspec(struct gpio_chip *chip, 1262 union gpio_irq_fwspec *gfwspec, 1263 unsigned int parent_hwirq, 1264 unsigned int parent_type) 1265 { 1266 struct irq_fwspec *fwspec = &gfwspec->fwspec; 1267 1268 fwspec->fwnode = chip->irq.parent_domain->fwnode; 1269 fwspec->param_count = 2; 1270 fwspec->param[0] = parent_hwirq; 1271 fwspec->param[1] = parent_type; 1272 1273 return 0; 1274 } 1275 1276 static void rzg2l_gpio_irq_domain_free(struct irq_domain *domain, unsigned int virq, 1277 unsigned int nr_irqs) 1278 { 1279 struct irq_data *d; 1280 1281 d = irq_domain_get_irq_data(domain, virq); 1282 if (d) { 1283 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1284 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); 1285 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1286 unsigned long flags; 1287 unsigned int i; 1288 1289 for (i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) { 1290 if (pctrl->hwirq[i] == hwirq) { 1291 spin_lock_irqsave(&pctrl->bitmap_lock, flags); 1292 bitmap_release_region(pctrl->tint_slot, i, get_order(1)); 1293 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); 1294 pctrl->hwirq[i] = 0; 1295 break; 1296 } 1297 } 1298 } 1299 irq_domain_free_irqs_common(domain, virq, nr_irqs); 1300 } 1301 1302 static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc, 1303 unsigned long *valid_mask, 1304 unsigned int ngpios) 1305 { 1306 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc); 1307 struct gpio_chip *chip = &pctrl->gpio_chip; 1308 unsigned int offset; 1309 1310 /* Forbid unused lines to be mapped as IRQs */ 1311 for (offset = 0; offset < chip->ngpio; offset++) { 1312 u32 port, bit; 1313 1314 port = offset / 8; 1315 bit = offset % 8; 1316 1317 if (port >= pctrl->data->n_ports || 1318 bit >= RZG2L_GPIO_PORT_GET_PINCNT(pctrl->data->port_pin_configs[port])) 1319 clear_bit(offset, valid_mask); 1320 } 1321 } 1322 1323 static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) 1324 { 1325 struct device_node *np = pctrl->dev->of_node; 1326 struct gpio_chip *chip = &pctrl->gpio_chip; 1327 const char *name = dev_name(pctrl->dev); 1328 struct irq_domain *parent_domain; 1329 struct of_phandle_args of_args; 1330 struct device_node *parent_np; 1331 struct gpio_irq_chip *girq; 1332 int ret; 1333 1334 parent_np = of_irq_find_parent(np); 1335 if (!parent_np) 1336 return -ENXIO; 1337 1338 parent_domain = irq_find_host(parent_np); 1339 of_node_put(parent_np); 1340 if (!parent_domain) 1341 return -EPROBE_DEFER; 1342 1343 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args); 1344 if (ret) { 1345 dev_err(pctrl->dev, "Unable to parse gpio-ranges\n"); 1346 return ret; 1347 } 1348 1349 if (of_args.args[0] != 0 || of_args.args[1] != 0 || 1350 of_args.args[2] != pctrl->data->n_port_pins) { 1351 dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n"); 1352 return -EINVAL; 1353 } 1354 1355 chip->names = pctrl->data->port_pins; 1356 chip->request = rzg2l_gpio_request; 1357 chip->free = rzg2l_gpio_free; 1358 chip->get_direction = rzg2l_gpio_get_direction; 1359 chip->direction_input = rzg2l_gpio_direction_input; 1360 chip->direction_output = rzg2l_gpio_direction_output; 1361 chip->get = rzg2l_gpio_get; 1362 chip->set = rzg2l_gpio_set; 1363 chip->label = name; 1364 chip->parent = pctrl->dev; 1365 chip->owner = THIS_MODULE; 1366 chip->base = -1; 1367 chip->ngpio = of_args.args[2]; 1368 1369 girq = &chip->irq; 1370 gpio_irq_chip_set_chip(girq, &rzg2l_gpio_irqchip); 1371 girq->fwnode = of_node_to_fwnode(np); 1372 girq->parent_domain = parent_domain; 1373 girq->child_to_parent_hwirq = rzg2l_gpio_child_to_parent_hwirq; 1374 girq->populate_parent_alloc_arg = rzg2l_gpio_populate_parent_fwspec; 1375 girq->child_irq_domain_ops.free = rzg2l_gpio_irq_domain_free; 1376 girq->init_valid_mask = rzg2l_init_irq_valid_mask; 1377 1378 pctrl->gpio_range.id = 0; 1379 pctrl->gpio_range.pin_base = 0; 1380 pctrl->gpio_range.base = 0; 1381 pctrl->gpio_range.npins = chip->ngpio; 1382 pctrl->gpio_range.name = chip->label; 1383 pctrl->gpio_range.gc = chip; 1384 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); 1385 if (ret) { 1386 dev_err(pctrl->dev, "failed to add GPIO controller\n"); 1387 return ret; 1388 } 1389 1390 dev_dbg(pctrl->dev, "Registered gpio controller\n"); 1391 1392 return 0; 1393 } 1394 1395 static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) 1396 { 1397 struct pinctrl_pin_desc *pins; 1398 unsigned int i, j; 1399 u32 *pin_data; 1400 int ret; 1401 1402 pctrl->desc.name = DRV_NAME; 1403 pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins; 1404 pctrl->desc.pctlops = &rzg2l_pinctrl_pctlops; 1405 pctrl->desc.pmxops = &rzg2l_pinctrl_pmxops; 1406 pctrl->desc.confops = &rzg2l_pinctrl_confops; 1407 pctrl->desc.owner = THIS_MODULE; 1408 1409 pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL); 1410 if (!pins) 1411 return -ENOMEM; 1412 1413 pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins, 1414 sizeof(*pin_data), GFP_KERNEL); 1415 if (!pin_data) 1416 return -ENOMEM; 1417 1418 pctrl->pins = pins; 1419 pctrl->desc.pins = pins; 1420 1421 for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) { 1422 pins[i].number = i; 1423 pins[i].name = pctrl->data->port_pins[i]; 1424 if (i && !(i % RZG2L_PINS_PER_PORT)) 1425 j++; 1426 pin_data[i] = pctrl->data->port_pin_configs[j]; 1427 pins[i].drv_data = &pin_data[i]; 1428 } 1429 1430 for (i = 0; i < pctrl->data->n_dedicated_pins; i++) { 1431 unsigned int index = pctrl->data->n_port_pins + i; 1432 1433 pins[index].number = index; 1434 pins[index].name = pctrl->data->dedicated_pins[i].name; 1435 pin_data[index] = pctrl->data->dedicated_pins[i].config; 1436 pins[index].drv_data = &pin_data[index]; 1437 } 1438 1439 ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl, 1440 &pctrl->pctl); 1441 if (ret) { 1442 dev_err(pctrl->dev, "pinctrl registration failed\n"); 1443 return ret; 1444 } 1445 1446 ret = pinctrl_enable(pctrl->pctl); 1447 if (ret) { 1448 dev_err(pctrl->dev, "pinctrl enable failed\n"); 1449 return ret; 1450 } 1451 1452 ret = rzg2l_gpio_register(pctrl); 1453 if (ret) { 1454 dev_err(pctrl->dev, "failed to add GPIO chip: %i\n", ret); 1455 return ret; 1456 } 1457 1458 return 0; 1459 } 1460 1461 static void rzg2l_pinctrl_clk_disable(void *data) 1462 { 1463 clk_disable_unprepare(data); 1464 } 1465 1466 static int rzg2l_pinctrl_probe(struct platform_device *pdev) 1467 { 1468 struct rzg2l_pinctrl *pctrl; 1469 int ret; 1470 1471 BUILD_BUG_ON(ARRAY_SIZE(rzg2l_gpio_configs) * RZG2L_PINS_PER_PORT > 1472 ARRAY_SIZE(rzg2l_gpio_names)); 1473 1474 BUILD_BUG_ON(ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT > 1475 ARRAY_SIZE(rzg2l_gpio_names)); 1476 1477 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 1478 if (!pctrl) 1479 return -ENOMEM; 1480 1481 pctrl->dev = &pdev->dev; 1482 1483 pctrl->data = of_device_get_match_data(&pdev->dev); 1484 if (!pctrl->data) 1485 return -EINVAL; 1486 1487 pctrl->base = devm_platform_ioremap_resource(pdev, 0); 1488 if (IS_ERR(pctrl->base)) 1489 return PTR_ERR(pctrl->base); 1490 1491 pctrl->clk = devm_clk_get(pctrl->dev, NULL); 1492 if (IS_ERR(pctrl->clk)) { 1493 ret = PTR_ERR(pctrl->clk); 1494 dev_err(pctrl->dev, "failed to get GPIO clk : %i\n", ret); 1495 return ret; 1496 } 1497 1498 spin_lock_init(&pctrl->lock); 1499 spin_lock_init(&pctrl->bitmap_lock); 1500 1501 platform_set_drvdata(pdev, pctrl); 1502 1503 ret = clk_prepare_enable(pctrl->clk); 1504 if (ret) { 1505 dev_err(pctrl->dev, "failed to enable GPIO clk: %i\n", ret); 1506 return ret; 1507 } 1508 1509 ret = devm_add_action_or_reset(&pdev->dev, rzg2l_pinctrl_clk_disable, 1510 pctrl->clk); 1511 if (ret) { 1512 dev_err(pctrl->dev, 1513 "failed to register GPIO clk disable action, %i\n", 1514 ret); 1515 return ret; 1516 } 1517 1518 ret = rzg2l_pinctrl_register(pctrl); 1519 if (ret) 1520 return ret; 1521 1522 dev_info(pctrl->dev, "%s support registered\n", DRV_NAME); 1523 return 0; 1524 } 1525 1526 static struct rzg2l_pinctrl_data r9a07g043_data = { 1527 .port_pins = rzg2l_gpio_names, 1528 .port_pin_configs = r9a07g043_gpio_configs, 1529 .n_ports = ARRAY_SIZE(r9a07g043_gpio_configs), 1530 .dedicated_pins = rzg2l_dedicated_pins.common, 1531 .n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT, 1532 .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common), 1533 }; 1534 1535 static struct rzg2l_pinctrl_data r9a07g044_data = { 1536 .port_pins = rzg2l_gpio_names, 1537 .port_pin_configs = rzg2l_gpio_configs, 1538 .n_ports = ARRAY_SIZE(rzg2l_gpio_configs), 1539 .dedicated_pins = rzg2l_dedicated_pins.common, 1540 .n_port_pins = ARRAY_SIZE(rzg2l_gpio_configs) * RZG2L_PINS_PER_PORT, 1541 .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) + 1542 ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins), 1543 }; 1544 1545 static const struct of_device_id rzg2l_pinctrl_of_table[] = { 1546 { 1547 .compatible = "renesas,r9a07g043-pinctrl", 1548 .data = &r9a07g043_data, 1549 }, 1550 { 1551 .compatible = "renesas,r9a07g044-pinctrl", 1552 .data = &r9a07g044_data, 1553 }, 1554 { /* sentinel */ } 1555 }; 1556 1557 static struct platform_driver rzg2l_pinctrl_driver = { 1558 .driver = { 1559 .name = DRV_NAME, 1560 .of_match_table = of_match_ptr(rzg2l_pinctrl_of_table), 1561 }, 1562 .probe = rzg2l_pinctrl_probe, 1563 }; 1564 1565 static int __init rzg2l_pinctrl_init(void) 1566 { 1567 return platform_driver_register(&rzg2l_pinctrl_driver); 1568 } 1569 core_initcall(rzg2l_pinctrl_init); 1570 1571 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>"); 1572 MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/G2L family"); 1573 MODULE_LICENSE("GPL v2"); 1574