1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas RZ/G2L Pin Control and GPIO driver core 4 * 5 * Copyright (C) 2021 Renesas Electronics Corporation. 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/clk.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_irq.h> 16 #include <linux/platform_device.h> 17 #include <linux/seq_file.h> 18 #include <linux/spinlock.h> 19 20 #include <linux/pinctrl/consumer.h> 21 #include <linux/pinctrl/pinconf-generic.h> 22 #include <linux/pinctrl/pinconf.h> 23 #include <linux/pinctrl/pinctrl.h> 24 #include <linux/pinctrl/pinmux.h> 25 26 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 27 28 #include "../core.h" 29 #include "../pinconf.h" 30 #include "../pinmux.h" 31 32 #define DRV_NAME "pinctrl-rzg2l" 33 34 /* 35 * Use 16 lower bits [15:0] for pin identifier 36 * Use 16 higher bits [31:16] for pin mux function 37 */ 38 #define MUX_PIN_ID_MASK GENMASK(15, 0) 39 #define MUX_FUNC_MASK GENMASK(31, 16) 40 #define MUX_FUNC_OFFS 16 41 #define MUX_FUNC(pinconf) (((pinconf) & MUX_FUNC_MASK) >> MUX_FUNC_OFFS) 42 43 /* PIN capabilities */ 44 #define PIN_CFG_IOLH_A BIT(0) 45 #define PIN_CFG_IOLH_B BIT(1) 46 #define PIN_CFG_SR BIT(2) 47 #define PIN_CFG_IEN BIT(3) 48 #define PIN_CFG_PUPD BIT(4) 49 #define PIN_CFG_IO_VMC_SD0 BIT(5) 50 #define PIN_CFG_IO_VMC_SD1 BIT(6) 51 #define PIN_CFG_IO_VMC_QSPI BIT(7) 52 #define PIN_CFG_IO_VMC_ETH0 BIT(8) 53 #define PIN_CFG_IO_VMC_ETH1 BIT(9) 54 #define PIN_CFG_FILONOFF BIT(10) 55 #define PIN_CFG_FILNUM BIT(11) 56 #define PIN_CFG_FILCLKSEL BIT(12) 57 58 #define RZG2L_MPXED_PIN_FUNCS (PIN_CFG_IOLH_A | \ 59 PIN_CFG_SR | \ 60 PIN_CFG_PUPD | \ 61 PIN_CFG_FILONOFF | \ 62 PIN_CFG_FILNUM | \ 63 PIN_CFG_FILCLKSEL) 64 65 #define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | \ 66 PIN_CFG_FILONOFF | \ 67 PIN_CFG_FILNUM | \ 68 PIN_CFG_FILCLKSEL) 69 70 /* 71 * n indicates number of pins in the port, a is the register index 72 * and f is pin configuration capabilities supported. 73 */ 74 #define RZG2L_GPIO_PORT_PACK(n, a, f) (((n) << 28) | ((a) << 20) | (f)) 75 #define RZG2L_GPIO_PORT_GET_PINCNT(x) (((x) & GENMASK(30, 28)) >> 28) 76 #define RZG2L_GPIO_PORT_GET_INDEX(x) (((x) & GENMASK(26, 20)) >> 20) 77 #define RZG2L_GPIO_PORT_GET_CFGS(x) ((x) & GENMASK(19, 0)) 78 79 /* 80 * BIT(31) indicates dedicated pin, p is the register index while 81 * referencing to SR/IEN/IOLH/FILxx registers, b is the register bits 82 * (b * 8) and f is the pin configuration capabilities supported. 83 */ 84 #define RZG2L_SINGLE_PIN BIT(31) 85 #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ 86 ((p) << 24) | ((b) << 20) | (f)) 87 #define RZG2L_SINGLE_PIN_GET_PORT_OFFSET(x) (((x) & GENMASK(30, 24)) >> 24) 88 #define RZG2L_SINGLE_PIN_GET_BIT(x) (((x) & GENMASK(22, 20)) >> 20) 89 #define RZG2L_SINGLE_PIN_GET_CFGS(x) ((x) & GENMASK(19, 0)) 90 91 #define P(n) (0x0000 + 0x10 + (n)) 92 #define PM(n) (0x0100 + 0x20 + (n) * 2) 93 #define PMC(n) (0x0200 + 0x10 + (n)) 94 #define PFC(n) (0x0400 + 0x40 + (n) * 4) 95 #define PIN(n) (0x0800 + 0x10 + (n)) 96 #define IOLH(n) (0x1000 + (n) * 8) 97 #define IEN(n) (0x1800 + (n) * 8) 98 #define ISEL(n) (0x2c80 + (n) * 8) 99 #define PWPR (0x3014) 100 #define SD_CH(n) (0x3000 + (n) * 4) 101 #define QSPI (0x3008) 102 103 #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */ 104 #define PVDD_3300 0 /* I/O domain voltage >= 3.3V */ 105 106 #define PWPR_B0WI BIT(7) /* Bit Write Disable */ 107 #define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */ 108 109 #define PM_MASK 0x03 110 #define PVDD_MASK 0x01 111 #define PFC_MASK 0x07 112 #define IEN_MASK 0x01 113 #define IOLH_MASK 0x03 114 115 #define PM_INPUT 0x1 116 #define PM_OUTPUT 0x2 117 118 #define RZG2L_PIN_ID_TO_PORT(id) ((id) / RZG2L_PINS_PER_PORT) 119 #define RZG2L_PIN_ID_TO_PORT_OFFSET(id) (RZG2L_PIN_ID_TO_PORT(id) + 0x10) 120 #define RZG2L_PIN_ID_TO_PIN(id) ((id) % RZG2L_PINS_PER_PORT) 121 122 #define RZG2L_TINT_MAX_INTERRUPT 32 123 #define RZG2L_TINT_IRQ_START_INDEX 9 124 #define RZG2L_PACK_HWIRQ(t, i) (((t) << 16) | (i)) 125 126 struct rzg2l_dedicated_configs { 127 const char *name; 128 u32 config; 129 }; 130 131 struct rzg2l_pinctrl_data { 132 const char * const *port_pins; 133 const u32 *port_pin_configs; 134 unsigned int n_ports; 135 struct rzg2l_dedicated_configs *dedicated_pins; 136 unsigned int n_port_pins; 137 unsigned int n_dedicated_pins; 138 }; 139 140 struct rzg2l_pinctrl { 141 struct pinctrl_dev *pctl; 142 struct pinctrl_desc desc; 143 struct pinctrl_pin_desc *pins; 144 145 const struct rzg2l_pinctrl_data *data; 146 void __iomem *base; 147 struct device *dev; 148 struct clk *clk; 149 150 struct gpio_chip gpio_chip; 151 struct pinctrl_gpio_range gpio_range; 152 DECLARE_BITMAP(tint_slot, RZG2L_TINT_MAX_INTERRUPT); 153 spinlock_t bitmap_lock; 154 unsigned int hwirq[RZG2L_TINT_MAX_INTERRUPT]; 155 156 spinlock_t lock; 157 }; 158 159 static const unsigned int iolh_groupa_mA[] = { 2, 4, 8, 12 }; 160 static const unsigned int iolh_groupb_oi[] = { 100, 66, 50, 33 }; 161 162 static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, 163 u8 port, u8 pin, u8 func) 164 { 165 unsigned long flags; 166 u32 reg; 167 168 spin_lock_irqsave(&pctrl->lock, flags); 169 170 /* Set pin to 'Non-use (Hi-Z input protection)' */ 171 reg = readw(pctrl->base + PM(port)); 172 reg &= ~(PM_MASK << (pin * 2)); 173 writew(reg, pctrl->base + PM(port)); 174 175 /* Temporarily switch to GPIO mode with PMC register */ 176 reg = readb(pctrl->base + PMC(port)); 177 writeb(reg & ~BIT(pin), pctrl->base + PMC(port)); 178 179 /* Set the PWPR register to allow PFC register to write */ 180 writel(0x0, pctrl->base + PWPR); /* B0WI=0, PFCWE=0 */ 181 writel(PWPR_PFCWE, pctrl->base + PWPR); /* B0WI=0, PFCWE=1 */ 182 183 /* Select Pin function mode with PFC register */ 184 reg = readl(pctrl->base + PFC(port)); 185 reg &= ~(PFC_MASK << (pin * 4)); 186 writel(reg | (func << (pin * 4)), pctrl->base + PFC(port)); 187 188 /* Set the PWPR register to be write-protected */ 189 writel(0x0, pctrl->base + PWPR); /* B0WI=0, PFCWE=0 */ 190 writel(PWPR_B0WI, pctrl->base + PWPR); /* B0WI=1, PFCWE=0 */ 191 192 /* Switch to Peripheral pin function with PMC register */ 193 reg = readb(pctrl->base + PMC(port)); 194 writeb(reg | BIT(pin), pctrl->base + PMC(port)); 195 196 spin_unlock_irqrestore(&pctrl->lock, flags); 197 }; 198 199 static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, 200 unsigned int func_selector, 201 unsigned int group_selector) 202 { 203 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 204 struct function_desc *func; 205 unsigned int i, *psel_val; 206 struct group_desc *group; 207 int *pins; 208 209 func = pinmux_generic_get_function(pctldev, func_selector); 210 if (!func) 211 return -EINVAL; 212 group = pinctrl_generic_get_group(pctldev, group_selector); 213 if (!group) 214 return -EINVAL; 215 216 psel_val = func->data; 217 pins = group->pins; 218 219 for (i = 0; i < group->num_pins; i++) { 220 dev_dbg(pctrl->dev, "port:%u pin: %u PSEL:%u\n", 221 RZG2L_PIN_ID_TO_PORT(pins[i]), RZG2L_PIN_ID_TO_PIN(pins[i]), 222 psel_val[i]); 223 rzg2l_pinctrl_set_pfc_mode(pctrl, RZG2L_PIN_ID_TO_PORT(pins[i]), 224 RZG2L_PIN_ID_TO_PIN(pins[i]), psel_val[i]); 225 } 226 227 return 0; 228 }; 229 230 static int rzg2l_map_add_config(struct pinctrl_map *map, 231 const char *group_or_pin, 232 enum pinctrl_map_type type, 233 unsigned long *configs, 234 unsigned int num_configs) 235 { 236 unsigned long *cfgs; 237 238 cfgs = kmemdup(configs, num_configs * sizeof(*cfgs), 239 GFP_KERNEL); 240 if (!cfgs) 241 return -ENOMEM; 242 243 map->type = type; 244 map->data.configs.group_or_pin = group_or_pin; 245 map->data.configs.configs = cfgs; 246 map->data.configs.num_configs = num_configs; 247 248 return 0; 249 } 250 251 static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev, 252 struct device_node *np, 253 struct pinctrl_map **map, 254 unsigned int *num_maps, 255 unsigned int *index) 256 { 257 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 258 struct pinctrl_map *maps = *map; 259 unsigned int nmaps = *num_maps; 260 unsigned long *configs = NULL; 261 unsigned int *pins, *psel_val; 262 unsigned int num_pinmux = 0; 263 unsigned int idx = *index; 264 unsigned int num_pins, i; 265 unsigned int num_configs; 266 struct property *pinmux; 267 struct property *prop; 268 int ret, gsel, fsel; 269 const char **pin_fn; 270 const char *pin; 271 272 pinmux = of_find_property(np, "pinmux", NULL); 273 if (pinmux) 274 num_pinmux = pinmux->length / sizeof(u32); 275 276 ret = of_property_count_strings(np, "pins"); 277 if (ret == -EINVAL) { 278 num_pins = 0; 279 } else if (ret < 0) { 280 dev_err(pctrl->dev, "Invalid pins list in DT\n"); 281 return ret; 282 } else { 283 num_pins = ret; 284 } 285 286 if (!num_pinmux && !num_pins) 287 return 0; 288 289 if (num_pinmux && num_pins) { 290 dev_err(pctrl->dev, 291 "DT node must contain either a pinmux or pins and not both\n"); 292 return -EINVAL; 293 } 294 295 ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs); 296 if (ret < 0) 297 return ret; 298 299 if (num_pins && !num_configs) { 300 dev_err(pctrl->dev, "DT node must contain a config\n"); 301 ret = -ENODEV; 302 goto done; 303 } 304 305 if (num_pinmux) 306 nmaps += 1; 307 308 if (num_pins) 309 nmaps += num_pins; 310 311 maps = krealloc_array(maps, nmaps, sizeof(*maps), GFP_KERNEL); 312 if (!maps) { 313 ret = -ENOMEM; 314 goto done; 315 } 316 317 *map = maps; 318 *num_maps = nmaps; 319 if (num_pins) { 320 of_property_for_each_string(np, "pins", prop, pin) { 321 ret = rzg2l_map_add_config(&maps[idx], pin, 322 PIN_MAP_TYPE_CONFIGS_PIN, 323 configs, num_configs); 324 if (ret < 0) 325 goto done; 326 327 idx++; 328 } 329 ret = 0; 330 goto done; 331 } 332 333 pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL); 334 psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val), 335 GFP_KERNEL); 336 pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL); 337 if (!pins || !psel_val || !pin_fn) { 338 ret = -ENOMEM; 339 goto done; 340 } 341 342 /* Collect pin locations and mux settings from DT properties */ 343 for (i = 0; i < num_pinmux; ++i) { 344 u32 value; 345 346 ret = of_property_read_u32_index(np, "pinmux", i, &value); 347 if (ret) 348 goto done; 349 pins[i] = value & MUX_PIN_ID_MASK; 350 psel_val[i] = MUX_FUNC(value); 351 } 352 353 /* Register a single pin group listing all the pins we read from DT */ 354 gsel = pinctrl_generic_add_group(pctldev, np->name, pins, num_pinmux, NULL); 355 if (gsel < 0) { 356 ret = gsel; 357 goto done; 358 } 359 360 /* 361 * Register a single group function where the 'data' is an array PSEL 362 * register values read from DT. 363 */ 364 pin_fn[0] = np->name; 365 fsel = pinmux_generic_add_function(pctldev, np->name, pin_fn, 1, 366 psel_val); 367 if (fsel < 0) { 368 ret = fsel; 369 goto remove_group; 370 } 371 372 maps[idx].type = PIN_MAP_TYPE_MUX_GROUP; 373 maps[idx].data.mux.group = np->name; 374 maps[idx].data.mux.function = np->name; 375 idx++; 376 377 dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux); 378 ret = 0; 379 goto done; 380 381 remove_group: 382 pinctrl_generic_remove_group(pctldev, gsel); 383 done: 384 *index = idx; 385 kfree(configs); 386 return ret; 387 } 388 389 static void rzg2l_dt_free_map(struct pinctrl_dev *pctldev, 390 struct pinctrl_map *map, 391 unsigned int num_maps) 392 { 393 unsigned int i; 394 395 if (!map) 396 return; 397 398 for (i = 0; i < num_maps; ++i) { 399 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP || 400 map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) 401 kfree(map[i].data.configs.configs); 402 } 403 kfree(map); 404 } 405 406 static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev, 407 struct device_node *np, 408 struct pinctrl_map **map, 409 unsigned int *num_maps) 410 { 411 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 412 struct device_node *child; 413 unsigned int index; 414 int ret; 415 416 *map = NULL; 417 *num_maps = 0; 418 index = 0; 419 420 for_each_child_of_node(np, child) { 421 ret = rzg2l_dt_subnode_to_map(pctldev, child, map, 422 num_maps, &index); 423 if (ret < 0) { 424 of_node_put(child); 425 goto done; 426 } 427 } 428 429 if (*num_maps == 0) { 430 ret = rzg2l_dt_subnode_to_map(pctldev, np, map, 431 num_maps, &index); 432 if (ret < 0) 433 goto done; 434 } 435 436 if (*num_maps) 437 return 0; 438 439 dev_err(pctrl->dev, "no mapping found in node %pOF\n", np); 440 ret = -EINVAL; 441 442 done: 443 rzg2l_dt_free_map(pctldev, *map, *num_maps); 444 445 return ret; 446 } 447 448 static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl, 449 u32 cfg, u32 port, u8 bit) 450 { 451 u8 pincount = RZG2L_GPIO_PORT_GET_PINCNT(cfg); 452 u32 port_index = RZG2L_GPIO_PORT_GET_INDEX(cfg); 453 u32 data; 454 455 if (bit >= pincount || port >= pctrl->data->n_port_pins) 456 return -EINVAL; 457 458 data = pctrl->data->port_pin_configs[port]; 459 if (port_index != RZG2L_GPIO_PORT_GET_INDEX(data)) 460 return -EINVAL; 461 462 return 0; 463 } 464 465 static u32 rzg2l_read_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, 466 u8 bit, u32 mask) 467 { 468 void __iomem *addr = pctrl->base + offset; 469 470 /* handle _L/_H for 32-bit register read/write */ 471 if (bit >= 4) { 472 bit -= 4; 473 addr += 4; 474 } 475 476 return (readl(addr) >> (bit * 8)) & mask; 477 } 478 479 static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, 480 u8 bit, u32 mask, u32 val) 481 { 482 void __iomem *addr = pctrl->base + offset; 483 unsigned long flags; 484 u32 reg; 485 486 /* handle _L/_H for 32-bit register read/write */ 487 if (bit >= 4) { 488 bit -= 4; 489 addr += 4; 490 } 491 492 spin_lock_irqsave(&pctrl->lock, flags); 493 reg = readl(addr) & ~(mask << (bit * 8)); 494 writel(reg | (val << (bit * 8)), addr); 495 spin_unlock_irqrestore(&pctrl->lock, flags); 496 } 497 498 static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, 499 unsigned int _pin, 500 unsigned long *config) 501 { 502 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 503 enum pin_config_param param = pinconf_to_config_param(*config); 504 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; 505 unsigned int *pin_data = pin->drv_data; 506 unsigned int arg = 0; 507 unsigned long flags; 508 void __iomem *addr; 509 u32 port_offset; 510 u32 cfg = 0; 511 u8 bit = 0; 512 513 if (!pin_data) 514 return -EINVAL; 515 516 if (*pin_data & RZG2L_SINGLE_PIN) { 517 port_offset = RZG2L_SINGLE_PIN_GET_PORT_OFFSET(*pin_data); 518 cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data); 519 bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data); 520 } else { 521 cfg = RZG2L_GPIO_PORT_GET_CFGS(*pin_data); 522 port_offset = RZG2L_PIN_ID_TO_PORT_OFFSET(_pin); 523 bit = RZG2L_PIN_ID_TO_PIN(_pin); 524 525 if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) 526 return -EINVAL; 527 } 528 529 switch (param) { 530 case PIN_CONFIG_INPUT_ENABLE: 531 if (!(cfg & PIN_CFG_IEN)) 532 return -EINVAL; 533 arg = rzg2l_read_pin_config(pctrl, IEN(port_offset), bit, IEN_MASK); 534 if (!arg) 535 return -EINVAL; 536 break; 537 538 case PIN_CONFIG_POWER_SOURCE: { 539 u32 pwr_reg = 0x0; 540 541 if (cfg & PIN_CFG_IO_VMC_SD0) 542 pwr_reg = SD_CH(0); 543 else if (cfg & PIN_CFG_IO_VMC_SD1) 544 pwr_reg = SD_CH(1); 545 else if (cfg & PIN_CFG_IO_VMC_QSPI) 546 pwr_reg = QSPI; 547 else 548 return -EINVAL; 549 550 spin_lock_irqsave(&pctrl->lock, flags); 551 addr = pctrl->base + pwr_reg; 552 arg = (readl(addr) & PVDD_MASK) ? 1800 : 3300; 553 spin_unlock_irqrestore(&pctrl->lock, flags); 554 break; 555 } 556 557 case PIN_CONFIG_DRIVE_STRENGTH: { 558 unsigned int index; 559 560 if (!(cfg & PIN_CFG_IOLH_A)) 561 return -EINVAL; 562 563 index = rzg2l_read_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK); 564 arg = iolh_groupa_mA[index]; 565 break; 566 } 567 568 case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: { 569 unsigned int index; 570 571 if (!(cfg & PIN_CFG_IOLH_B)) 572 return -EINVAL; 573 574 index = rzg2l_read_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK); 575 arg = iolh_groupb_oi[index]; 576 break; 577 } 578 579 default: 580 return -ENOTSUPP; 581 } 582 583 *config = pinconf_to_config_packed(param, arg); 584 585 return 0; 586 }; 587 588 static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, 589 unsigned int _pin, 590 unsigned long *_configs, 591 unsigned int num_configs) 592 { 593 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 594 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; 595 unsigned int *pin_data = pin->drv_data; 596 enum pin_config_param param; 597 unsigned long flags; 598 void __iomem *addr; 599 u32 port_offset; 600 unsigned int i; 601 u32 cfg = 0; 602 u8 bit = 0; 603 604 if (!pin_data) 605 return -EINVAL; 606 607 if (*pin_data & RZG2L_SINGLE_PIN) { 608 port_offset = RZG2L_SINGLE_PIN_GET_PORT_OFFSET(*pin_data); 609 cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data); 610 bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data); 611 } else { 612 cfg = RZG2L_GPIO_PORT_GET_CFGS(*pin_data); 613 port_offset = RZG2L_PIN_ID_TO_PORT_OFFSET(_pin); 614 bit = RZG2L_PIN_ID_TO_PIN(_pin); 615 616 if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) 617 return -EINVAL; 618 } 619 620 for (i = 0; i < num_configs; i++) { 621 param = pinconf_to_config_param(_configs[i]); 622 switch (param) { 623 case PIN_CONFIG_INPUT_ENABLE: { 624 unsigned int arg = 625 pinconf_to_config_argument(_configs[i]); 626 627 if (!(cfg & PIN_CFG_IEN)) 628 return -EINVAL; 629 630 rzg2l_rmw_pin_config(pctrl, IEN(port_offset), bit, IEN_MASK, !!arg); 631 break; 632 } 633 634 case PIN_CONFIG_POWER_SOURCE: { 635 unsigned int mV = pinconf_to_config_argument(_configs[i]); 636 u32 pwr_reg = 0x0; 637 638 if (mV != 1800 && mV != 3300) 639 return -EINVAL; 640 641 if (cfg & PIN_CFG_IO_VMC_SD0) 642 pwr_reg = SD_CH(0); 643 else if (cfg & PIN_CFG_IO_VMC_SD1) 644 pwr_reg = SD_CH(1); 645 else if (cfg & PIN_CFG_IO_VMC_QSPI) 646 pwr_reg = QSPI; 647 else 648 return -EINVAL; 649 650 addr = pctrl->base + pwr_reg; 651 spin_lock_irqsave(&pctrl->lock, flags); 652 writel((mV == 1800) ? PVDD_1800 : PVDD_3300, addr); 653 spin_unlock_irqrestore(&pctrl->lock, flags); 654 break; 655 } 656 657 case PIN_CONFIG_DRIVE_STRENGTH: { 658 unsigned int arg = pinconf_to_config_argument(_configs[i]); 659 unsigned int index; 660 661 if (!(cfg & PIN_CFG_IOLH_A)) 662 return -EINVAL; 663 664 for (index = 0; index < ARRAY_SIZE(iolh_groupa_mA); index++) { 665 if (arg == iolh_groupa_mA[index]) 666 break; 667 } 668 if (index >= ARRAY_SIZE(iolh_groupa_mA)) 669 return -EINVAL; 670 671 rzg2l_rmw_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK, index); 672 break; 673 } 674 675 case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: { 676 unsigned int arg = pinconf_to_config_argument(_configs[i]); 677 unsigned int index; 678 679 if (!(cfg & PIN_CFG_IOLH_B)) 680 return -EINVAL; 681 682 for (index = 0; index < ARRAY_SIZE(iolh_groupb_oi); index++) { 683 if (arg == iolh_groupb_oi[index]) 684 break; 685 } 686 if (index >= ARRAY_SIZE(iolh_groupb_oi)) 687 return -EINVAL; 688 689 rzg2l_rmw_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK, index); 690 break; 691 } 692 693 default: 694 return -EOPNOTSUPP; 695 } 696 } 697 698 return 0; 699 } 700 701 static int rzg2l_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev, 702 unsigned int group, 703 unsigned long *configs, 704 unsigned int num_configs) 705 { 706 const unsigned int *pins; 707 unsigned int i, npins; 708 int ret; 709 710 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 711 if (ret) 712 return ret; 713 714 for (i = 0; i < npins; i++) { 715 ret = rzg2l_pinctrl_pinconf_set(pctldev, pins[i], configs, 716 num_configs); 717 if (ret) 718 return ret; 719 } 720 721 return 0; 722 }; 723 724 static int rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev, 725 unsigned int group, 726 unsigned long *config) 727 { 728 const unsigned int *pins; 729 unsigned int i, npins, prev_config = 0; 730 int ret; 731 732 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 733 if (ret) 734 return ret; 735 736 for (i = 0; i < npins; i++) { 737 ret = rzg2l_pinctrl_pinconf_get(pctldev, pins[i], config); 738 if (ret) 739 return ret; 740 741 /* Check config matching between to pin */ 742 if (i && prev_config != *config) 743 return -EOPNOTSUPP; 744 745 prev_config = *config; 746 } 747 748 return 0; 749 }; 750 751 static const struct pinctrl_ops rzg2l_pinctrl_pctlops = { 752 .get_groups_count = pinctrl_generic_get_group_count, 753 .get_group_name = pinctrl_generic_get_group_name, 754 .get_group_pins = pinctrl_generic_get_group_pins, 755 .dt_node_to_map = rzg2l_dt_node_to_map, 756 .dt_free_map = rzg2l_dt_free_map, 757 }; 758 759 static const struct pinmux_ops rzg2l_pinctrl_pmxops = { 760 .get_functions_count = pinmux_generic_get_function_count, 761 .get_function_name = pinmux_generic_get_function_name, 762 .get_function_groups = pinmux_generic_get_function_groups, 763 .set_mux = rzg2l_pinctrl_set_mux, 764 .strict = true, 765 }; 766 767 static const struct pinconf_ops rzg2l_pinctrl_confops = { 768 .is_generic = true, 769 .pin_config_get = rzg2l_pinctrl_pinconf_get, 770 .pin_config_set = rzg2l_pinctrl_pinconf_set, 771 .pin_config_group_set = rzg2l_pinctrl_pinconf_group_set, 772 .pin_config_group_get = rzg2l_pinctrl_pinconf_group_get, 773 .pin_config_config_dbg_show = pinconf_generic_dump_config, 774 }; 775 776 static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset) 777 { 778 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 779 u32 port = RZG2L_PIN_ID_TO_PORT(offset); 780 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 781 unsigned long flags; 782 u8 reg8; 783 int ret; 784 785 ret = pinctrl_gpio_request(chip->base + offset); 786 if (ret) 787 return ret; 788 789 spin_lock_irqsave(&pctrl->lock, flags); 790 791 /* Select GPIO mode in PMC Register */ 792 reg8 = readb(pctrl->base + PMC(port)); 793 reg8 &= ~BIT(bit); 794 writeb(reg8, pctrl->base + PMC(port)); 795 796 spin_unlock_irqrestore(&pctrl->lock, flags); 797 798 return 0; 799 } 800 801 static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 port, 802 u8 bit, bool output) 803 { 804 unsigned long flags; 805 u16 reg16; 806 807 spin_lock_irqsave(&pctrl->lock, flags); 808 809 reg16 = readw(pctrl->base + PM(port)); 810 reg16 &= ~(PM_MASK << (bit * 2)); 811 812 reg16 |= (output ? PM_OUTPUT : PM_INPUT) << (bit * 2); 813 writew(reg16, pctrl->base + PM(port)); 814 815 spin_unlock_irqrestore(&pctrl->lock, flags); 816 } 817 818 static int rzg2l_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 819 { 820 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 821 u32 port = RZG2L_PIN_ID_TO_PORT(offset); 822 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 823 824 if (!(readb(pctrl->base + PMC(port)) & BIT(bit))) { 825 u16 reg16; 826 827 reg16 = readw(pctrl->base + PM(port)); 828 reg16 = (reg16 >> (bit * 2)) & PM_MASK; 829 if (reg16 == PM_OUTPUT) 830 return GPIO_LINE_DIRECTION_OUT; 831 } 832 833 return GPIO_LINE_DIRECTION_IN; 834 } 835 836 static int rzg2l_gpio_direction_input(struct gpio_chip *chip, 837 unsigned int offset) 838 { 839 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 840 u32 port = RZG2L_PIN_ID_TO_PORT(offset); 841 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 842 843 rzg2l_gpio_set_direction(pctrl, port, bit, false); 844 845 return 0; 846 } 847 848 static void rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset, 849 int value) 850 { 851 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 852 u32 port = RZG2L_PIN_ID_TO_PORT(offset); 853 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 854 unsigned long flags; 855 u8 reg8; 856 857 spin_lock_irqsave(&pctrl->lock, flags); 858 859 reg8 = readb(pctrl->base + P(port)); 860 861 if (value) 862 writeb(reg8 | BIT(bit), pctrl->base + P(port)); 863 else 864 writeb(reg8 & ~BIT(bit), pctrl->base + P(port)); 865 866 spin_unlock_irqrestore(&pctrl->lock, flags); 867 } 868 869 static int rzg2l_gpio_direction_output(struct gpio_chip *chip, 870 unsigned int offset, int value) 871 { 872 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 873 u32 port = RZG2L_PIN_ID_TO_PORT(offset); 874 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 875 876 rzg2l_gpio_set(chip, offset, value); 877 rzg2l_gpio_set_direction(pctrl, port, bit, true); 878 879 return 0; 880 } 881 882 static int rzg2l_gpio_get(struct gpio_chip *chip, unsigned int offset) 883 { 884 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 885 u32 port = RZG2L_PIN_ID_TO_PORT(offset); 886 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 887 u16 reg16; 888 889 reg16 = readw(pctrl->base + PM(port)); 890 reg16 = (reg16 >> (bit * 2)) & PM_MASK; 891 892 if (reg16 == PM_INPUT) 893 return !!(readb(pctrl->base + PIN(port)) & BIT(bit)); 894 else if (reg16 == PM_OUTPUT) 895 return !!(readb(pctrl->base + P(port)) & BIT(bit)); 896 else 897 return -EINVAL; 898 } 899 900 static void rzg2l_gpio_free(struct gpio_chip *chip, unsigned int offset) 901 { 902 unsigned int virq; 903 904 pinctrl_gpio_free(chip->base + offset); 905 906 virq = irq_find_mapping(chip->irq.domain, offset); 907 if (virq) 908 irq_dispose_mapping(virq); 909 910 /* 911 * Set the GPIO as an input to ensure that the next GPIO request won't 912 * drive the GPIO pin as an output. 913 */ 914 rzg2l_gpio_direction_input(chip, offset); 915 } 916 917 static const char * const rzg2l_gpio_names[] = { 918 "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7", 919 "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7", 920 "P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7", 921 "P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7", 922 "P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7", 923 "P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7", 924 "P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7", 925 "P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7", 926 "P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7", 927 "P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7", 928 "P10_0", "P10_1", "P10_2", "P10_3", "P10_4", "P10_5", "P10_6", "P10_7", 929 "P11_0", "P11_1", "P11_2", "P11_3", "P11_4", "P11_5", "P11_6", "P11_7", 930 "P12_0", "P12_1", "P12_2", "P12_3", "P12_4", "P12_5", "P12_6", "P12_7", 931 "P13_0", "P13_1", "P13_2", "P13_3", "P13_4", "P13_5", "P13_6", "P13_7", 932 "P14_0", "P14_1", "P14_2", "P14_3", "P14_4", "P14_5", "P14_6", "P14_7", 933 "P15_0", "P15_1", "P15_2", "P15_3", "P15_4", "P15_5", "P15_6", "P15_7", 934 "P16_0", "P16_1", "P16_2", "P16_3", "P16_4", "P16_5", "P16_6", "P16_7", 935 "P17_0", "P17_1", "P17_2", "P17_3", "P17_4", "P17_5", "P17_6", "P17_7", 936 "P18_0", "P18_1", "P18_2", "P18_3", "P18_4", "P18_5", "P18_6", "P18_7", 937 "P19_0", "P19_1", "P19_2", "P19_3", "P19_4", "P19_5", "P19_6", "P19_7", 938 "P20_0", "P20_1", "P20_2", "P20_3", "P20_4", "P20_5", "P20_6", "P20_7", 939 "P21_0", "P21_1", "P21_2", "P21_3", "P21_4", "P21_5", "P21_6", "P21_7", 940 "P22_0", "P22_1", "P22_2", "P22_3", "P22_4", "P22_5", "P22_6", "P22_7", 941 "P23_0", "P23_1", "P23_2", "P23_3", "P23_4", "P23_5", "P23_6", "P23_7", 942 "P24_0", "P24_1", "P24_2", "P24_3", "P24_4", "P24_5", "P24_6", "P24_7", 943 "P25_0", "P25_1", "P25_2", "P25_3", "P25_4", "P25_5", "P25_6", "P25_7", 944 "P26_0", "P26_1", "P26_2", "P26_3", "P26_4", "P26_5", "P26_6", "P26_7", 945 "P27_0", "P27_1", "P27_2", "P27_3", "P27_4", "P27_5", "P27_6", "P27_7", 946 "P28_0", "P28_1", "P28_2", "P28_3", "P28_4", "P28_5", "P28_6", "P28_7", 947 "P29_0", "P29_1", "P29_2", "P29_3", "P29_4", "P29_5", "P29_6", "P29_7", 948 "P30_0", "P30_1", "P30_2", "P30_3", "P30_4", "P30_5", "P30_6", "P30_7", 949 "P31_0", "P31_1", "P31_2", "P31_3", "P31_4", "P31_5", "P31_6", "P31_7", 950 "P32_0", "P32_1", "P32_2", "P32_3", "P32_4", "P32_5", "P32_6", "P32_7", 951 "P33_0", "P33_1", "P33_2", "P33_3", "P33_4", "P33_5", "P33_6", "P33_7", 952 "P34_0", "P34_1", "P34_2", "P34_3", "P34_4", "P34_5", "P34_6", "P34_7", 953 "P35_0", "P35_1", "P35_2", "P35_3", "P35_4", "P35_5", "P35_6", "P35_7", 954 "P36_0", "P36_1", "P36_2", "P36_3", "P36_4", "P36_5", "P36_6", "P36_7", 955 "P37_0", "P37_1", "P37_2", "P37_3", "P37_4", "P37_5", "P37_6", "P37_7", 956 "P38_0", "P38_1", "P38_2", "P38_3", "P38_4", "P38_5", "P38_6", "P38_7", 957 "P39_0", "P39_1", "P39_2", "P39_3", "P39_4", "P39_5", "P39_6", "P39_7", 958 "P40_0", "P40_1", "P40_2", "P40_3", "P40_4", "P40_5", "P40_6", "P40_7", 959 "P41_0", "P41_1", "P41_2", "P41_3", "P41_4", "P41_5", "P41_6", "P41_7", 960 "P42_0", "P42_1", "P42_2", "P42_3", "P42_4", "P42_5", "P42_6", "P42_7", 961 "P43_0", "P43_1", "P43_2", "P43_3", "P43_4", "P43_5", "P43_6", "P43_7", 962 "P44_0", "P44_1", "P44_2", "P44_3", "P44_4", "P44_5", "P44_6", "P44_7", 963 "P45_0", "P45_1", "P45_2", "P45_3", "P45_4", "P45_5", "P45_6", "P45_7", 964 "P46_0", "P46_1", "P46_2", "P46_3", "P46_4", "P46_5", "P46_6", "P46_7", 965 "P47_0", "P47_1", "P47_2", "P47_3", "P47_4", "P47_5", "P47_6", "P47_7", 966 "P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6", "P48_7", 967 }; 968 969 static const u32 rzg2l_gpio_configs[] = { 970 RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS), 971 RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS), 972 RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS), 973 RZG2L_GPIO_PORT_PACK(2, 0x13, RZG2L_MPXED_PIN_FUNCS), 974 RZG2L_GPIO_PORT_PACK(2, 0x14, RZG2L_MPXED_PIN_FUNCS), 975 RZG2L_GPIO_PORT_PACK(3, 0x15, RZG2L_MPXED_PIN_FUNCS), 976 RZG2L_GPIO_PORT_PACK(2, 0x16, RZG2L_MPXED_PIN_FUNCS), 977 RZG2L_GPIO_PORT_PACK(3, 0x17, RZG2L_MPXED_PIN_FUNCS), 978 RZG2L_GPIO_PORT_PACK(3, 0x18, RZG2L_MPXED_PIN_FUNCS), 979 RZG2L_GPIO_PORT_PACK(2, 0x19, RZG2L_MPXED_PIN_FUNCS), 980 RZG2L_GPIO_PORT_PACK(2, 0x1a, RZG2L_MPXED_PIN_FUNCS), 981 RZG2L_GPIO_PORT_PACK(2, 0x1b, RZG2L_MPXED_PIN_FUNCS), 982 RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS), 983 RZG2L_GPIO_PORT_PACK(3, 0x1d, RZG2L_MPXED_PIN_FUNCS), 984 RZG2L_GPIO_PORT_PACK(2, 0x1e, RZG2L_MPXED_PIN_FUNCS), 985 RZG2L_GPIO_PORT_PACK(2, 0x1f, RZG2L_MPXED_PIN_FUNCS), 986 RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), 987 RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS), 988 RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS), 989 RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS), 990 RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 991 RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 992 RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 993 RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 994 RZG2L_GPIO_PORT_PACK(2, 0x28, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 995 RZG2L_GPIO_PORT_PACK(2, 0x29, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 996 RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 997 RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 998 RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 999 RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1000 RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1001 RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1002 RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1003 RZG2L_GPIO_PORT_PACK(2, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1004 RZG2L_GPIO_PORT_PACK(2, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1005 RZG2L_GPIO_PORT_PACK(2, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1006 RZG2L_GPIO_PORT_PACK(2, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1007 RZG2L_GPIO_PORT_PACK(3, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1008 RZG2L_GPIO_PORT_PACK(2, 0x36, RZG2L_MPXED_PIN_FUNCS), 1009 RZG2L_GPIO_PORT_PACK(3, 0x37, RZG2L_MPXED_PIN_FUNCS), 1010 RZG2L_GPIO_PORT_PACK(3, 0x38, RZG2L_MPXED_PIN_FUNCS), 1011 RZG2L_GPIO_PORT_PACK(2, 0x39, RZG2L_MPXED_PIN_FUNCS), 1012 RZG2L_GPIO_PORT_PACK(5, 0x3a, RZG2L_MPXED_PIN_FUNCS), 1013 RZG2L_GPIO_PORT_PACK(4, 0x3b, RZG2L_MPXED_PIN_FUNCS), 1014 RZG2L_GPIO_PORT_PACK(4, 0x3c, RZG2L_MPXED_PIN_FUNCS), 1015 RZG2L_GPIO_PORT_PACK(4, 0x3d, RZG2L_MPXED_PIN_FUNCS), 1016 RZG2L_GPIO_PORT_PACK(4, 0x3e, RZG2L_MPXED_PIN_FUNCS), 1017 RZG2L_GPIO_PORT_PACK(4, 0x3f, RZG2L_MPXED_PIN_FUNCS), 1018 RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS), 1019 }; 1020 1021 static const u32 r9a07g043_gpio_configs[] = { 1022 RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS), 1023 RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1024 RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1025 RZG2L_GPIO_PORT_PACK(4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1026 RZG2L_GPIO_PORT_PACK(6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1027 RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS), 1028 RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS), 1029 RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1030 RZG2L_GPIO_PORT_PACK(5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1031 RZG2L_GPIO_PORT_PACK(4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1032 RZG2L_GPIO_PORT_PACK(5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1033 RZG2L_GPIO_PORT_PACK(4, 0x1b, RZG2L_MPXED_PIN_FUNCS), 1034 RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS), 1035 RZG2L_GPIO_PORT_PACK(5, 0x1d, RZG2L_MPXED_PIN_FUNCS), 1036 RZG2L_GPIO_PORT_PACK(3, 0x1e, RZG2L_MPXED_PIN_FUNCS), 1037 RZG2L_GPIO_PORT_PACK(4, 0x1f, RZG2L_MPXED_PIN_FUNCS), 1038 RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), 1039 RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS), 1040 RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS), 1041 }; 1042 1043 static struct { 1044 struct rzg2l_dedicated_configs common[35]; 1045 struct rzg2l_dedicated_configs rzg2l_pins[7]; 1046 } rzg2l_dedicated_pins = { 1047 .common = { 1048 { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, 1049 (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) }, 1050 { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0, 1051 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) }, 1052 { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0, 1053 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) }, 1054 { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) }, 1055 { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) }, 1056 { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0, 1057 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, 1058 { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1, 1059 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1060 { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2, 1061 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, 1062 { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0, 1063 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1064 { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1, 1065 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1066 { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2, 1067 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1068 { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3, 1069 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1070 { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4, 1071 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1072 { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5, 1073 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1074 { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6, 1075 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1076 { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x7, 7, 1077 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1078 { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0, 1079 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1)) }, 1080 { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x8, 1, 1081 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 1082 { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x9, 0, 1083 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 1084 { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x9, 1, 1085 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 1086 { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x9, 2, 1087 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 1088 { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x9, 3, 1089 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 1090 { "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0, 1091 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1092 { "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1, 1093 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1094 { "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2, 1095 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1096 { "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3, 1097 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1098 { "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4, 1099 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1100 { "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5, 1101 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1102 { "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0, 1103 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1104 { "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1, 1105 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1106 { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) }, 1107 { "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) }, 1108 { "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) }, 1109 { "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) }, 1110 { "RIIC1_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 3, PIN_CFG_IEN) }, 1111 }, 1112 .rzg2l_pins = { 1113 { "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1114 { "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, 1115 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1116 { "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1, 1117 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1118 { "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2, 1119 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1120 { "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3, 1121 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1122 { "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4, 1123 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1124 { "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5, 1125 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1126 } 1127 }; 1128 1129 static int rzg2l_gpio_get_gpioint(unsigned int virq, const struct rzg2l_pinctrl_data *data) 1130 { 1131 unsigned int gpioint; 1132 unsigned int i; 1133 u32 port, bit; 1134 1135 port = virq / 8; 1136 bit = virq % 8; 1137 1138 if (port >= data->n_ports || 1139 bit >= RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[port])) 1140 return -EINVAL; 1141 1142 gpioint = bit; 1143 for (i = 0; i < port; i++) 1144 gpioint += RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[i]); 1145 1146 return gpioint; 1147 } 1148 1149 static void rzg2l_gpio_irq_disable(struct irq_data *d) 1150 { 1151 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1152 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); 1153 unsigned int hwirq = irqd_to_hwirq(d); 1154 unsigned long flags; 1155 void __iomem *addr; 1156 u32 port; 1157 u8 bit; 1158 1159 port = RZG2L_PIN_ID_TO_PORT(hwirq); 1160 bit = RZG2L_PIN_ID_TO_PIN(hwirq); 1161 1162 addr = pctrl->base + ISEL(port); 1163 if (bit >= 4) { 1164 bit -= 4; 1165 addr += 4; 1166 } 1167 1168 spin_lock_irqsave(&pctrl->lock, flags); 1169 writel(readl(addr) & ~BIT(bit * 8), addr); 1170 spin_unlock_irqrestore(&pctrl->lock, flags); 1171 1172 gpiochip_disable_irq(gc, hwirq); 1173 irq_chip_disable_parent(d); 1174 } 1175 1176 static void rzg2l_gpio_irq_enable(struct irq_data *d) 1177 { 1178 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1179 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); 1180 unsigned int hwirq = irqd_to_hwirq(d); 1181 unsigned long flags; 1182 void __iomem *addr; 1183 u32 port; 1184 u8 bit; 1185 1186 gpiochip_enable_irq(gc, hwirq); 1187 1188 port = RZG2L_PIN_ID_TO_PORT(hwirq); 1189 bit = RZG2L_PIN_ID_TO_PIN(hwirq); 1190 1191 addr = pctrl->base + ISEL(port); 1192 if (bit >= 4) { 1193 bit -= 4; 1194 addr += 4; 1195 } 1196 1197 spin_lock_irqsave(&pctrl->lock, flags); 1198 writel(readl(addr) | BIT(bit * 8), addr); 1199 spin_unlock_irqrestore(&pctrl->lock, flags); 1200 1201 irq_chip_enable_parent(d); 1202 } 1203 1204 static int rzg2l_gpio_irq_set_type(struct irq_data *d, unsigned int type) 1205 { 1206 return irq_chip_set_type_parent(d, type); 1207 } 1208 1209 static void rzg2l_gpio_irqc_eoi(struct irq_data *d) 1210 { 1211 irq_chip_eoi_parent(d); 1212 } 1213 1214 static void rzg2l_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p) 1215 { 1216 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 1217 1218 seq_printf(p, dev_name(gc->parent)); 1219 } 1220 1221 static const struct irq_chip rzg2l_gpio_irqchip = { 1222 .name = "rzg2l-gpio", 1223 .irq_disable = rzg2l_gpio_irq_disable, 1224 .irq_enable = rzg2l_gpio_irq_enable, 1225 .irq_mask = irq_chip_mask_parent, 1226 .irq_unmask = irq_chip_unmask_parent, 1227 .irq_set_type = rzg2l_gpio_irq_set_type, 1228 .irq_eoi = rzg2l_gpio_irqc_eoi, 1229 .irq_print_chip = rzg2l_gpio_irq_print_chip, 1230 .flags = IRQCHIP_IMMUTABLE, 1231 GPIOCHIP_IRQ_RESOURCE_HELPERS, 1232 }; 1233 1234 static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, 1235 unsigned int child, 1236 unsigned int child_type, 1237 unsigned int *parent, 1238 unsigned int *parent_type) 1239 { 1240 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc); 1241 unsigned long flags; 1242 int gpioint, irq; 1243 1244 gpioint = rzg2l_gpio_get_gpioint(child, pctrl->data); 1245 if (gpioint < 0) 1246 return gpioint; 1247 1248 spin_lock_irqsave(&pctrl->bitmap_lock, flags); 1249 irq = bitmap_find_free_region(pctrl->tint_slot, RZG2L_TINT_MAX_INTERRUPT, get_order(1)); 1250 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); 1251 if (irq < 0) 1252 return -ENOSPC; 1253 pctrl->hwirq[irq] = child; 1254 irq += RZG2L_TINT_IRQ_START_INDEX; 1255 1256 /* All these interrupts are level high in the CPU */ 1257 *parent_type = IRQ_TYPE_LEVEL_HIGH; 1258 *parent = RZG2L_PACK_HWIRQ(gpioint, irq); 1259 return 0; 1260 } 1261 1262 static int rzg2l_gpio_populate_parent_fwspec(struct gpio_chip *chip, 1263 union gpio_irq_fwspec *gfwspec, 1264 unsigned int parent_hwirq, 1265 unsigned int parent_type) 1266 { 1267 struct irq_fwspec *fwspec = &gfwspec->fwspec; 1268 1269 fwspec->fwnode = chip->irq.parent_domain->fwnode; 1270 fwspec->param_count = 2; 1271 fwspec->param[0] = parent_hwirq; 1272 fwspec->param[1] = parent_type; 1273 1274 return 0; 1275 } 1276 1277 static void rzg2l_gpio_irq_domain_free(struct irq_domain *domain, unsigned int virq, 1278 unsigned int nr_irqs) 1279 { 1280 struct irq_data *d; 1281 1282 d = irq_domain_get_irq_data(domain, virq); 1283 if (d) { 1284 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1285 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); 1286 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1287 unsigned long flags; 1288 unsigned int i; 1289 1290 for (i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) { 1291 if (pctrl->hwirq[i] == hwirq) { 1292 spin_lock_irqsave(&pctrl->bitmap_lock, flags); 1293 bitmap_release_region(pctrl->tint_slot, i, get_order(1)); 1294 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); 1295 pctrl->hwirq[i] = 0; 1296 break; 1297 } 1298 } 1299 } 1300 irq_domain_free_irqs_common(domain, virq, nr_irqs); 1301 } 1302 1303 static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc, 1304 unsigned long *valid_mask, 1305 unsigned int ngpios) 1306 { 1307 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc); 1308 struct gpio_chip *chip = &pctrl->gpio_chip; 1309 unsigned int offset; 1310 1311 /* Forbid unused lines to be mapped as IRQs */ 1312 for (offset = 0; offset < chip->ngpio; offset++) { 1313 u32 port, bit; 1314 1315 port = offset / 8; 1316 bit = offset % 8; 1317 1318 if (port >= pctrl->data->n_ports || 1319 bit >= RZG2L_GPIO_PORT_GET_PINCNT(pctrl->data->port_pin_configs[port])) 1320 clear_bit(offset, valid_mask); 1321 } 1322 } 1323 1324 static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) 1325 { 1326 struct device_node *np = pctrl->dev->of_node; 1327 struct gpio_chip *chip = &pctrl->gpio_chip; 1328 const char *name = dev_name(pctrl->dev); 1329 struct irq_domain *parent_domain; 1330 struct of_phandle_args of_args; 1331 struct device_node *parent_np; 1332 struct gpio_irq_chip *girq; 1333 int ret; 1334 1335 parent_np = of_irq_find_parent(np); 1336 if (!parent_np) 1337 return -ENXIO; 1338 1339 parent_domain = irq_find_host(parent_np); 1340 of_node_put(parent_np); 1341 if (!parent_domain) 1342 return -EPROBE_DEFER; 1343 1344 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args); 1345 if (ret) { 1346 dev_err(pctrl->dev, "Unable to parse gpio-ranges\n"); 1347 return ret; 1348 } 1349 1350 if (of_args.args[0] != 0 || of_args.args[1] != 0 || 1351 of_args.args[2] != pctrl->data->n_port_pins) { 1352 dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n"); 1353 return -EINVAL; 1354 } 1355 1356 chip->names = pctrl->data->port_pins; 1357 chip->request = rzg2l_gpio_request; 1358 chip->free = rzg2l_gpio_free; 1359 chip->get_direction = rzg2l_gpio_get_direction; 1360 chip->direction_input = rzg2l_gpio_direction_input; 1361 chip->direction_output = rzg2l_gpio_direction_output; 1362 chip->get = rzg2l_gpio_get; 1363 chip->set = rzg2l_gpio_set; 1364 chip->label = name; 1365 chip->parent = pctrl->dev; 1366 chip->owner = THIS_MODULE; 1367 chip->base = -1; 1368 chip->ngpio = of_args.args[2]; 1369 1370 girq = &chip->irq; 1371 gpio_irq_chip_set_chip(girq, &rzg2l_gpio_irqchip); 1372 girq->fwnode = of_node_to_fwnode(np); 1373 girq->parent_domain = parent_domain; 1374 girq->child_to_parent_hwirq = rzg2l_gpio_child_to_parent_hwirq; 1375 girq->populate_parent_alloc_arg = rzg2l_gpio_populate_parent_fwspec; 1376 girq->child_irq_domain_ops.free = rzg2l_gpio_irq_domain_free; 1377 girq->init_valid_mask = rzg2l_init_irq_valid_mask; 1378 1379 pctrl->gpio_range.id = 0; 1380 pctrl->gpio_range.pin_base = 0; 1381 pctrl->gpio_range.base = 0; 1382 pctrl->gpio_range.npins = chip->ngpio; 1383 pctrl->gpio_range.name = chip->label; 1384 pctrl->gpio_range.gc = chip; 1385 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); 1386 if (ret) { 1387 dev_err(pctrl->dev, "failed to add GPIO controller\n"); 1388 return ret; 1389 } 1390 1391 dev_dbg(pctrl->dev, "Registered gpio controller\n"); 1392 1393 return 0; 1394 } 1395 1396 static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) 1397 { 1398 struct pinctrl_pin_desc *pins; 1399 unsigned int i, j; 1400 u32 *pin_data; 1401 int ret; 1402 1403 pctrl->desc.name = DRV_NAME; 1404 pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins; 1405 pctrl->desc.pctlops = &rzg2l_pinctrl_pctlops; 1406 pctrl->desc.pmxops = &rzg2l_pinctrl_pmxops; 1407 pctrl->desc.confops = &rzg2l_pinctrl_confops; 1408 pctrl->desc.owner = THIS_MODULE; 1409 1410 pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL); 1411 if (!pins) 1412 return -ENOMEM; 1413 1414 pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins, 1415 sizeof(*pin_data), GFP_KERNEL); 1416 if (!pin_data) 1417 return -ENOMEM; 1418 1419 pctrl->pins = pins; 1420 pctrl->desc.pins = pins; 1421 1422 for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) { 1423 pins[i].number = i; 1424 pins[i].name = pctrl->data->port_pins[i]; 1425 if (i && !(i % RZG2L_PINS_PER_PORT)) 1426 j++; 1427 pin_data[i] = pctrl->data->port_pin_configs[j]; 1428 pins[i].drv_data = &pin_data[i]; 1429 } 1430 1431 for (i = 0; i < pctrl->data->n_dedicated_pins; i++) { 1432 unsigned int index = pctrl->data->n_port_pins + i; 1433 1434 pins[index].number = index; 1435 pins[index].name = pctrl->data->dedicated_pins[i].name; 1436 pin_data[index] = pctrl->data->dedicated_pins[i].config; 1437 pins[index].drv_data = &pin_data[index]; 1438 } 1439 1440 ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl, 1441 &pctrl->pctl); 1442 if (ret) { 1443 dev_err(pctrl->dev, "pinctrl registration failed\n"); 1444 return ret; 1445 } 1446 1447 ret = pinctrl_enable(pctrl->pctl); 1448 if (ret) { 1449 dev_err(pctrl->dev, "pinctrl enable failed\n"); 1450 return ret; 1451 } 1452 1453 ret = rzg2l_gpio_register(pctrl); 1454 if (ret) { 1455 dev_err(pctrl->dev, "failed to add GPIO chip: %i\n", ret); 1456 return ret; 1457 } 1458 1459 return 0; 1460 } 1461 1462 static void rzg2l_pinctrl_clk_disable(void *data) 1463 { 1464 clk_disable_unprepare(data); 1465 } 1466 1467 static int rzg2l_pinctrl_probe(struct platform_device *pdev) 1468 { 1469 struct rzg2l_pinctrl *pctrl; 1470 int ret; 1471 1472 BUILD_BUG_ON(ARRAY_SIZE(rzg2l_gpio_configs) * RZG2L_PINS_PER_PORT > 1473 ARRAY_SIZE(rzg2l_gpio_names)); 1474 1475 BUILD_BUG_ON(ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT > 1476 ARRAY_SIZE(rzg2l_gpio_names)); 1477 1478 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 1479 if (!pctrl) 1480 return -ENOMEM; 1481 1482 pctrl->dev = &pdev->dev; 1483 1484 pctrl->data = of_device_get_match_data(&pdev->dev); 1485 if (!pctrl->data) 1486 return -EINVAL; 1487 1488 pctrl->base = devm_platform_ioremap_resource(pdev, 0); 1489 if (IS_ERR(pctrl->base)) 1490 return PTR_ERR(pctrl->base); 1491 1492 pctrl->clk = devm_clk_get(pctrl->dev, NULL); 1493 if (IS_ERR(pctrl->clk)) { 1494 ret = PTR_ERR(pctrl->clk); 1495 dev_err(pctrl->dev, "failed to get GPIO clk : %i\n", ret); 1496 return ret; 1497 } 1498 1499 spin_lock_init(&pctrl->lock); 1500 spin_lock_init(&pctrl->bitmap_lock); 1501 1502 platform_set_drvdata(pdev, pctrl); 1503 1504 ret = clk_prepare_enable(pctrl->clk); 1505 if (ret) { 1506 dev_err(pctrl->dev, "failed to enable GPIO clk: %i\n", ret); 1507 return ret; 1508 } 1509 1510 ret = devm_add_action_or_reset(&pdev->dev, rzg2l_pinctrl_clk_disable, 1511 pctrl->clk); 1512 if (ret) { 1513 dev_err(pctrl->dev, 1514 "failed to register GPIO clk disable action, %i\n", 1515 ret); 1516 return ret; 1517 } 1518 1519 ret = rzg2l_pinctrl_register(pctrl); 1520 if (ret) 1521 return ret; 1522 1523 dev_info(pctrl->dev, "%s support registered\n", DRV_NAME); 1524 return 0; 1525 } 1526 1527 static struct rzg2l_pinctrl_data r9a07g043_data = { 1528 .port_pins = rzg2l_gpio_names, 1529 .port_pin_configs = r9a07g043_gpio_configs, 1530 .n_ports = ARRAY_SIZE(r9a07g043_gpio_configs), 1531 .dedicated_pins = rzg2l_dedicated_pins.common, 1532 .n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT, 1533 .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common), 1534 }; 1535 1536 static struct rzg2l_pinctrl_data r9a07g044_data = { 1537 .port_pins = rzg2l_gpio_names, 1538 .port_pin_configs = rzg2l_gpio_configs, 1539 .n_ports = ARRAY_SIZE(rzg2l_gpio_configs), 1540 .dedicated_pins = rzg2l_dedicated_pins.common, 1541 .n_port_pins = ARRAY_SIZE(rzg2l_gpio_configs) * RZG2L_PINS_PER_PORT, 1542 .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) + 1543 ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins), 1544 }; 1545 1546 static const struct of_device_id rzg2l_pinctrl_of_table[] = { 1547 { 1548 .compatible = "renesas,r9a07g043-pinctrl", 1549 .data = &r9a07g043_data, 1550 }, 1551 { 1552 .compatible = "renesas,r9a07g044-pinctrl", 1553 .data = &r9a07g044_data, 1554 }, 1555 { /* sentinel */ } 1556 }; 1557 1558 static struct platform_driver rzg2l_pinctrl_driver = { 1559 .driver = { 1560 .name = DRV_NAME, 1561 .of_match_table = of_match_ptr(rzg2l_pinctrl_of_table), 1562 }, 1563 .probe = rzg2l_pinctrl_probe, 1564 }; 1565 1566 static int __init rzg2l_pinctrl_init(void) 1567 { 1568 return platform_driver_register(&rzg2l_pinctrl_driver); 1569 } 1570 core_initcall(rzg2l_pinctrl_init); 1571 1572 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>"); 1573 MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/G2L family"); 1574