1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Renesas RZ/G2L Pin Control and GPIO driver core
4 *
5 * Copyright (C) 2021 Renesas Electronics Corporation.
6 */
7
8 #include <linux/bitops.h>
9 #include <linux/clk.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/interrupt.h>
12 #include <linux/io.h>
13 #include <linux/module.h>
14 #include <linux/mutex.h>
15 #include <linux/of.h>
16 #include <linux/of_irq.h>
17 #include <linux/platform_device.h>
18 #include <linux/seq_file.h>
19 #include <linux/spinlock.h>
20
21 #include <linux/pinctrl/consumer.h>
22 #include <linux/pinctrl/pinconf-generic.h>
23 #include <linux/pinctrl/pinconf.h>
24 #include <linux/pinctrl/pinctrl.h>
25 #include <linux/pinctrl/pinmux.h>
26
27 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
28
29 #include "../core.h"
30 #include "../pinconf.h"
31 #include "../pinmux.h"
32
33 #define DRV_NAME "pinctrl-rzg2l"
34
35 /*
36 * Use 16 lower bits [15:0] for pin identifier
37 * Use 16 higher bits [31:16] for pin mux function
38 */
39 #define MUX_PIN_ID_MASK GENMASK(15, 0)
40 #define MUX_FUNC_MASK GENMASK(31, 16)
41 #define MUX_FUNC_OFFS 16
42 #define MUX_FUNC(pinconf) (((pinconf) & MUX_FUNC_MASK) >> MUX_FUNC_OFFS)
43
44 /* PIN capabilities */
45 #define PIN_CFG_IOLH_A BIT(0)
46 #define PIN_CFG_IOLH_B BIT(1)
47 #define PIN_CFG_SR BIT(2)
48 #define PIN_CFG_IEN BIT(3)
49 #define PIN_CFG_PUPD BIT(4)
50 #define PIN_CFG_IO_VMC_SD0 BIT(5)
51 #define PIN_CFG_IO_VMC_SD1 BIT(6)
52 #define PIN_CFG_IO_VMC_QSPI BIT(7)
53 #define PIN_CFG_IO_VMC_ETH0 BIT(8)
54 #define PIN_CFG_IO_VMC_ETH1 BIT(9)
55 #define PIN_CFG_FILONOFF BIT(10)
56 #define PIN_CFG_FILNUM BIT(11)
57 #define PIN_CFG_FILCLKSEL BIT(12)
58
59 #define RZG2L_MPXED_PIN_FUNCS (PIN_CFG_IOLH_A | \
60 PIN_CFG_SR | \
61 PIN_CFG_PUPD | \
62 PIN_CFG_FILONOFF | \
63 PIN_CFG_FILNUM | \
64 PIN_CFG_FILCLKSEL)
65
66 #define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | \
67 PIN_CFG_FILONOFF | \
68 PIN_CFG_FILNUM | \
69 PIN_CFG_FILCLKSEL)
70
71 /*
72 * n indicates number of pins in the port, a is the register index
73 * and f is pin configuration capabilities supported.
74 */
75 #define RZG2L_GPIO_PORT_PACK(n, a, f) (((n) << 28) | ((a) << 20) | (f))
76 #define RZG2L_GPIO_PORT_GET_PINCNT(x) (((x) & GENMASK(30, 28)) >> 28)
77 #define RZG2L_GPIO_PORT_GET_INDEX(x) (((x) & GENMASK(26, 20)) >> 20)
78 #define RZG2L_GPIO_PORT_GET_CFGS(x) ((x) & GENMASK(19, 0))
79
80 /*
81 * BIT(31) indicates dedicated pin, p is the register index while
82 * referencing to SR/IEN/IOLH/FILxx registers, b is the register bits
83 * (b * 8) and f is the pin configuration capabilities supported.
84 */
85 #define RZG2L_SINGLE_PIN BIT(31)
86 #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \
87 ((p) << 24) | ((b) << 20) | (f))
88 #define RZG2L_SINGLE_PIN_GET_PORT_OFFSET(x) (((x) & GENMASK(30, 24)) >> 24)
89 #define RZG2L_SINGLE_PIN_GET_BIT(x) (((x) & GENMASK(22, 20)) >> 20)
90 #define RZG2L_SINGLE_PIN_GET_CFGS(x) ((x) & GENMASK(19, 0))
91
92 #define P(n) (0x0000 + 0x10 + (n))
93 #define PM(n) (0x0100 + 0x20 + (n) * 2)
94 #define PMC(n) (0x0200 + 0x10 + (n))
95 #define PFC(n) (0x0400 + 0x40 + (n) * 4)
96 #define PIN(n) (0x0800 + 0x10 + (n))
97 #define IOLH(n) (0x1000 + (n) * 8)
98 #define IEN(n) (0x1800 + (n) * 8)
99 #define ISEL(n) (0x2c80 + (n) * 8)
100 #define PWPR (0x3014)
101 #define SD_CH(n) (0x3000 + (n) * 4)
102 #define QSPI (0x3008)
103
104 #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */
105 #define PVDD_3300 0 /* I/O domain voltage >= 3.3V */
106
107 #define PWPR_B0WI BIT(7) /* Bit Write Disable */
108 #define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */
109
110 #define PM_MASK 0x03
111 #define PVDD_MASK 0x01
112 #define PFC_MASK 0x07
113 #define IEN_MASK 0x01
114 #define IOLH_MASK 0x03
115
116 #define PM_INPUT 0x1
117 #define PM_OUTPUT 0x2
118
119 #define RZG2L_PIN_ID_TO_PORT(id) ((id) / RZG2L_PINS_PER_PORT)
120 #define RZG2L_PIN_ID_TO_PORT_OFFSET(id) (RZG2L_PIN_ID_TO_PORT(id) + 0x10)
121 #define RZG2L_PIN_ID_TO_PIN(id) ((id) % RZG2L_PINS_PER_PORT)
122
123 #define RZG2L_TINT_MAX_INTERRUPT 32
124 #define RZG2L_TINT_IRQ_START_INDEX 9
125 #define RZG2L_PACK_HWIRQ(t, i) (((t) << 16) | (i))
126
127 struct rzg2l_dedicated_configs {
128 const char *name;
129 u32 config;
130 };
131
132 struct rzg2l_pinctrl_data {
133 const char * const *port_pins;
134 const u32 *port_pin_configs;
135 unsigned int n_ports;
136 struct rzg2l_dedicated_configs *dedicated_pins;
137 unsigned int n_port_pins;
138 unsigned int n_dedicated_pins;
139 };
140
141 struct rzg2l_pinctrl {
142 struct pinctrl_dev *pctl;
143 struct pinctrl_desc desc;
144 struct pinctrl_pin_desc *pins;
145
146 const struct rzg2l_pinctrl_data *data;
147 void __iomem *base;
148 struct device *dev;
149
150 struct gpio_chip gpio_chip;
151 struct pinctrl_gpio_range gpio_range;
152 DECLARE_BITMAP(tint_slot, RZG2L_TINT_MAX_INTERRUPT);
153 spinlock_t bitmap_lock; /* protect tint_slot bitmap */
154 unsigned int hwirq[RZG2L_TINT_MAX_INTERRUPT];
155
156 spinlock_t lock; /* lock read/write registers */
157 struct mutex mutex; /* serialize adding groups and functions */
158 };
159
160 static const unsigned int iolh_groupa_mA[] = { 2, 4, 8, 12 };
161 static const unsigned int iolh_groupb_oi[] = { 100, 66, 50, 33 };
162
rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl * pctrl,u8 port,u8 pin,u8 func)163 static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
164 u8 port, u8 pin, u8 func)
165 {
166 unsigned long flags;
167 u32 reg;
168
169 spin_lock_irqsave(&pctrl->lock, flags);
170
171 /* Set pin to 'Non-use (Hi-Z input protection)' */
172 reg = readw(pctrl->base + PM(port));
173 reg &= ~(PM_MASK << (pin * 2));
174 writew(reg, pctrl->base + PM(port));
175
176 /* Temporarily switch to GPIO mode with PMC register */
177 reg = readb(pctrl->base + PMC(port));
178 writeb(reg & ~BIT(pin), pctrl->base + PMC(port));
179
180 /* Set the PWPR register to allow PFC register to write */
181 writel(0x0, pctrl->base + PWPR); /* B0WI=0, PFCWE=0 */
182 writel(PWPR_PFCWE, pctrl->base + PWPR); /* B0WI=0, PFCWE=1 */
183
184 /* Select Pin function mode with PFC register */
185 reg = readl(pctrl->base + PFC(port));
186 reg &= ~(PFC_MASK << (pin * 4));
187 writel(reg | (func << (pin * 4)), pctrl->base + PFC(port));
188
189 /* Set the PWPR register to be write-protected */
190 writel(0x0, pctrl->base + PWPR); /* B0WI=0, PFCWE=0 */
191 writel(PWPR_B0WI, pctrl->base + PWPR); /* B0WI=1, PFCWE=0 */
192
193 /* Switch to Peripheral pin function with PMC register */
194 reg = readb(pctrl->base + PMC(port));
195 writeb(reg | BIT(pin), pctrl->base + PMC(port));
196
197 spin_unlock_irqrestore(&pctrl->lock, flags);
198 };
199
rzg2l_pinctrl_set_mux(struct pinctrl_dev * pctldev,unsigned int func_selector,unsigned int group_selector)200 static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev,
201 unsigned int func_selector,
202 unsigned int group_selector)
203 {
204 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
205 struct function_desc *func;
206 unsigned int i, *psel_val;
207 struct group_desc *group;
208 int *pins;
209
210 func = pinmux_generic_get_function(pctldev, func_selector);
211 if (!func)
212 return -EINVAL;
213 group = pinctrl_generic_get_group(pctldev, group_selector);
214 if (!group)
215 return -EINVAL;
216
217 psel_val = func->data;
218 pins = group->pins;
219
220 for (i = 0; i < group->num_pins; i++) {
221 dev_dbg(pctrl->dev, "port:%u pin: %u PSEL:%u\n",
222 RZG2L_PIN_ID_TO_PORT(pins[i]), RZG2L_PIN_ID_TO_PIN(pins[i]),
223 psel_val[i]);
224 rzg2l_pinctrl_set_pfc_mode(pctrl, RZG2L_PIN_ID_TO_PORT(pins[i]),
225 RZG2L_PIN_ID_TO_PIN(pins[i]), psel_val[i]);
226 }
227
228 return 0;
229 };
230
rzg2l_map_add_config(struct pinctrl_map * map,const char * group_or_pin,enum pinctrl_map_type type,unsigned long * configs,unsigned int num_configs)231 static int rzg2l_map_add_config(struct pinctrl_map *map,
232 const char *group_or_pin,
233 enum pinctrl_map_type type,
234 unsigned long *configs,
235 unsigned int num_configs)
236 {
237 unsigned long *cfgs;
238
239 cfgs = kmemdup(configs, num_configs * sizeof(*cfgs),
240 GFP_KERNEL);
241 if (!cfgs)
242 return -ENOMEM;
243
244 map->type = type;
245 map->data.configs.group_or_pin = group_or_pin;
246 map->data.configs.configs = cfgs;
247 map->data.configs.num_configs = num_configs;
248
249 return 0;
250 }
251
rzg2l_dt_subnode_to_map(struct pinctrl_dev * pctldev,struct device_node * np,struct device_node * parent,struct pinctrl_map ** map,unsigned int * num_maps,unsigned int * index)252 static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev,
253 struct device_node *np,
254 struct device_node *parent,
255 struct pinctrl_map **map,
256 unsigned int *num_maps,
257 unsigned int *index)
258 {
259 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
260 struct pinctrl_map *maps = *map;
261 unsigned int nmaps = *num_maps;
262 unsigned long *configs = NULL;
263 unsigned int *pins, *psel_val;
264 unsigned int num_pinmux = 0;
265 unsigned int idx = *index;
266 unsigned int num_pins, i;
267 unsigned int num_configs;
268 struct property *pinmux;
269 struct property *prop;
270 int ret, gsel, fsel;
271 const char **pin_fn;
272 const char *name;
273 const char *pin;
274
275 pinmux = of_find_property(np, "pinmux", NULL);
276 if (pinmux)
277 num_pinmux = pinmux->length / sizeof(u32);
278
279 ret = of_property_count_strings(np, "pins");
280 if (ret == -EINVAL) {
281 num_pins = 0;
282 } else if (ret < 0) {
283 dev_err(pctrl->dev, "Invalid pins list in DT\n");
284 return ret;
285 } else {
286 num_pins = ret;
287 }
288
289 if (!num_pinmux && !num_pins)
290 return 0;
291
292 if (num_pinmux && num_pins) {
293 dev_err(pctrl->dev,
294 "DT node must contain either a pinmux or pins and not both\n");
295 return -EINVAL;
296 }
297
298 ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs);
299 if (ret < 0)
300 return ret;
301
302 if (num_pins && !num_configs) {
303 dev_err(pctrl->dev, "DT node must contain a config\n");
304 ret = -ENODEV;
305 goto done;
306 }
307
308 if (num_pinmux)
309 nmaps += 1;
310
311 if (num_pins)
312 nmaps += num_pins;
313
314 maps = krealloc_array(maps, nmaps, sizeof(*maps), GFP_KERNEL);
315 if (!maps) {
316 ret = -ENOMEM;
317 goto done;
318 }
319
320 *map = maps;
321 *num_maps = nmaps;
322 if (num_pins) {
323 of_property_for_each_string(np, "pins", prop, pin) {
324 ret = rzg2l_map_add_config(&maps[idx], pin,
325 PIN_MAP_TYPE_CONFIGS_PIN,
326 configs, num_configs);
327 if (ret < 0)
328 goto done;
329
330 idx++;
331 }
332 ret = 0;
333 goto done;
334 }
335
336 pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL);
337 psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val),
338 GFP_KERNEL);
339 pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL);
340 if (!pins || !psel_val || !pin_fn) {
341 ret = -ENOMEM;
342 goto done;
343 }
344
345 /* Collect pin locations and mux settings from DT properties */
346 for (i = 0; i < num_pinmux; ++i) {
347 u32 value;
348
349 ret = of_property_read_u32_index(np, "pinmux", i, &value);
350 if (ret)
351 goto done;
352 pins[i] = value & MUX_PIN_ID_MASK;
353 psel_val[i] = MUX_FUNC(value);
354 }
355
356 if (parent) {
357 name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn",
358 parent, np);
359 if (!name) {
360 ret = -ENOMEM;
361 goto done;
362 }
363 } else {
364 name = np->name;
365 }
366
367 mutex_lock(&pctrl->mutex);
368
369 /* Register a single pin group listing all the pins we read from DT */
370 gsel = pinctrl_generic_add_group(pctldev, name, pins, num_pinmux, NULL);
371 if (gsel < 0) {
372 ret = gsel;
373 goto unlock;
374 }
375
376 /*
377 * Register a single group function where the 'data' is an array PSEL
378 * register values read from DT.
379 */
380 pin_fn[0] = name;
381 fsel = pinmux_generic_add_function(pctldev, name, pin_fn, 1, psel_val);
382 if (fsel < 0) {
383 ret = fsel;
384 goto remove_group;
385 }
386
387 mutex_unlock(&pctrl->mutex);
388
389 maps[idx].type = PIN_MAP_TYPE_MUX_GROUP;
390 maps[idx].data.mux.group = name;
391 maps[idx].data.mux.function = name;
392 idx++;
393
394 dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux);
395 ret = 0;
396 goto done;
397
398 remove_group:
399 pinctrl_generic_remove_group(pctldev, gsel);
400 unlock:
401 mutex_unlock(&pctrl->mutex);
402 done:
403 *index = idx;
404 kfree(configs);
405 return ret;
406 }
407
rzg2l_dt_free_map(struct pinctrl_dev * pctldev,struct pinctrl_map * map,unsigned int num_maps)408 static void rzg2l_dt_free_map(struct pinctrl_dev *pctldev,
409 struct pinctrl_map *map,
410 unsigned int num_maps)
411 {
412 unsigned int i;
413
414 if (!map)
415 return;
416
417 for (i = 0; i < num_maps; ++i) {
418 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP ||
419 map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
420 kfree(map[i].data.configs.configs);
421 }
422 kfree(map);
423 }
424
rzg2l_dt_node_to_map(struct pinctrl_dev * pctldev,struct device_node * np,struct pinctrl_map ** map,unsigned int * num_maps)425 static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev,
426 struct device_node *np,
427 struct pinctrl_map **map,
428 unsigned int *num_maps)
429 {
430 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
431 struct device_node *child;
432 unsigned int index;
433 int ret;
434
435 *map = NULL;
436 *num_maps = 0;
437 index = 0;
438
439 for_each_child_of_node(np, child) {
440 ret = rzg2l_dt_subnode_to_map(pctldev, child, np, map,
441 num_maps, &index);
442 if (ret < 0) {
443 of_node_put(child);
444 goto done;
445 }
446 }
447
448 if (*num_maps == 0) {
449 ret = rzg2l_dt_subnode_to_map(pctldev, np, NULL, map,
450 num_maps, &index);
451 if (ret < 0)
452 goto done;
453 }
454
455 if (*num_maps)
456 return 0;
457
458 dev_err(pctrl->dev, "no mapping found in node %pOF\n", np);
459 ret = -EINVAL;
460
461 done:
462 rzg2l_dt_free_map(pctldev, *map, *num_maps);
463
464 return ret;
465 }
466
rzg2l_validate_gpio_pin(struct rzg2l_pinctrl * pctrl,u32 cfg,u32 port,u8 bit)467 static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl,
468 u32 cfg, u32 port, u8 bit)
469 {
470 u8 pincount = RZG2L_GPIO_PORT_GET_PINCNT(cfg);
471 u32 port_index = RZG2L_GPIO_PORT_GET_INDEX(cfg);
472 u32 data;
473
474 if (bit >= pincount || port >= pctrl->data->n_port_pins)
475 return -EINVAL;
476
477 data = pctrl->data->port_pin_configs[port];
478 if (port_index != RZG2L_GPIO_PORT_GET_INDEX(data))
479 return -EINVAL;
480
481 return 0;
482 }
483
rzg2l_read_pin_config(struct rzg2l_pinctrl * pctrl,u32 offset,u8 bit,u32 mask)484 static u32 rzg2l_read_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset,
485 u8 bit, u32 mask)
486 {
487 void __iomem *addr = pctrl->base + offset;
488
489 /* handle _L/_H for 32-bit register read/write */
490 if (bit >= 4) {
491 bit -= 4;
492 addr += 4;
493 }
494
495 return (readl(addr) >> (bit * 8)) & mask;
496 }
497
rzg2l_rmw_pin_config(struct rzg2l_pinctrl * pctrl,u32 offset,u8 bit,u32 mask,u32 val)498 static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset,
499 u8 bit, u32 mask, u32 val)
500 {
501 void __iomem *addr = pctrl->base + offset;
502 unsigned long flags;
503 u32 reg;
504
505 /* handle _L/_H for 32-bit register read/write */
506 if (bit >= 4) {
507 bit -= 4;
508 addr += 4;
509 }
510
511 spin_lock_irqsave(&pctrl->lock, flags);
512 reg = readl(addr) & ~(mask << (bit * 8));
513 writel(reg | (val << (bit * 8)), addr);
514 spin_unlock_irqrestore(&pctrl->lock, flags);
515 }
516
rzg2l_pinctrl_pinconf_get(struct pinctrl_dev * pctldev,unsigned int _pin,unsigned long * config)517 static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
518 unsigned int _pin,
519 unsigned long *config)
520 {
521 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
522 enum pin_config_param param = pinconf_to_config_param(*config);
523 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
524 unsigned int *pin_data = pin->drv_data;
525 unsigned int arg = 0;
526 unsigned long flags;
527 void __iomem *addr;
528 u32 port_offset;
529 u32 cfg = 0;
530 u8 bit = 0;
531
532 if (!pin_data)
533 return -EINVAL;
534
535 if (*pin_data & RZG2L_SINGLE_PIN) {
536 port_offset = RZG2L_SINGLE_PIN_GET_PORT_OFFSET(*pin_data);
537 cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data);
538 bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data);
539 } else {
540 cfg = RZG2L_GPIO_PORT_GET_CFGS(*pin_data);
541 port_offset = RZG2L_PIN_ID_TO_PORT_OFFSET(_pin);
542 bit = RZG2L_PIN_ID_TO_PIN(_pin);
543
544 if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))
545 return -EINVAL;
546 }
547
548 switch (param) {
549 case PIN_CONFIG_INPUT_ENABLE:
550 if (!(cfg & PIN_CFG_IEN))
551 return -EINVAL;
552 arg = rzg2l_read_pin_config(pctrl, IEN(port_offset), bit, IEN_MASK);
553 if (!arg)
554 return -EINVAL;
555 break;
556
557 case PIN_CONFIG_POWER_SOURCE: {
558 u32 pwr_reg = 0x0;
559
560 if (cfg & PIN_CFG_IO_VMC_SD0)
561 pwr_reg = SD_CH(0);
562 else if (cfg & PIN_CFG_IO_VMC_SD1)
563 pwr_reg = SD_CH(1);
564 else if (cfg & PIN_CFG_IO_VMC_QSPI)
565 pwr_reg = QSPI;
566 else
567 return -EINVAL;
568
569 spin_lock_irqsave(&pctrl->lock, flags);
570 addr = pctrl->base + pwr_reg;
571 arg = (readl(addr) & PVDD_MASK) ? 1800 : 3300;
572 spin_unlock_irqrestore(&pctrl->lock, flags);
573 break;
574 }
575
576 case PIN_CONFIG_DRIVE_STRENGTH: {
577 unsigned int index;
578
579 if (!(cfg & PIN_CFG_IOLH_A))
580 return -EINVAL;
581
582 index = rzg2l_read_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK);
583 arg = iolh_groupa_mA[index];
584 break;
585 }
586
587 case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: {
588 unsigned int index;
589
590 if (!(cfg & PIN_CFG_IOLH_B))
591 return -EINVAL;
592
593 index = rzg2l_read_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK);
594 arg = iolh_groupb_oi[index];
595 break;
596 }
597
598 default:
599 return -ENOTSUPP;
600 }
601
602 *config = pinconf_to_config_packed(param, arg);
603
604 return 0;
605 };
606
rzg2l_pinctrl_pinconf_set(struct pinctrl_dev * pctldev,unsigned int _pin,unsigned long * _configs,unsigned int num_configs)607 static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
608 unsigned int _pin,
609 unsigned long *_configs,
610 unsigned int num_configs)
611 {
612 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
613 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
614 unsigned int *pin_data = pin->drv_data;
615 enum pin_config_param param;
616 unsigned long flags;
617 void __iomem *addr;
618 u32 port_offset;
619 unsigned int i;
620 u32 cfg = 0;
621 u8 bit = 0;
622
623 if (!pin_data)
624 return -EINVAL;
625
626 if (*pin_data & RZG2L_SINGLE_PIN) {
627 port_offset = RZG2L_SINGLE_PIN_GET_PORT_OFFSET(*pin_data);
628 cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data);
629 bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data);
630 } else {
631 cfg = RZG2L_GPIO_PORT_GET_CFGS(*pin_data);
632 port_offset = RZG2L_PIN_ID_TO_PORT_OFFSET(_pin);
633 bit = RZG2L_PIN_ID_TO_PIN(_pin);
634
635 if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))
636 return -EINVAL;
637 }
638
639 for (i = 0; i < num_configs; i++) {
640 param = pinconf_to_config_param(_configs[i]);
641 switch (param) {
642 case PIN_CONFIG_INPUT_ENABLE: {
643 unsigned int arg =
644 pinconf_to_config_argument(_configs[i]);
645
646 if (!(cfg & PIN_CFG_IEN))
647 return -EINVAL;
648
649 rzg2l_rmw_pin_config(pctrl, IEN(port_offset), bit, IEN_MASK, !!arg);
650 break;
651 }
652
653 case PIN_CONFIG_POWER_SOURCE: {
654 unsigned int mV = pinconf_to_config_argument(_configs[i]);
655 u32 pwr_reg = 0x0;
656
657 if (mV != 1800 && mV != 3300)
658 return -EINVAL;
659
660 if (cfg & PIN_CFG_IO_VMC_SD0)
661 pwr_reg = SD_CH(0);
662 else if (cfg & PIN_CFG_IO_VMC_SD1)
663 pwr_reg = SD_CH(1);
664 else if (cfg & PIN_CFG_IO_VMC_QSPI)
665 pwr_reg = QSPI;
666 else
667 return -EINVAL;
668
669 addr = pctrl->base + pwr_reg;
670 spin_lock_irqsave(&pctrl->lock, flags);
671 writel((mV == 1800) ? PVDD_1800 : PVDD_3300, addr);
672 spin_unlock_irqrestore(&pctrl->lock, flags);
673 break;
674 }
675
676 case PIN_CONFIG_DRIVE_STRENGTH: {
677 unsigned int arg = pinconf_to_config_argument(_configs[i]);
678 unsigned int index;
679
680 if (!(cfg & PIN_CFG_IOLH_A))
681 return -EINVAL;
682
683 for (index = 0; index < ARRAY_SIZE(iolh_groupa_mA); index++) {
684 if (arg == iolh_groupa_mA[index])
685 break;
686 }
687 if (index >= ARRAY_SIZE(iolh_groupa_mA))
688 return -EINVAL;
689
690 rzg2l_rmw_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK, index);
691 break;
692 }
693
694 case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: {
695 unsigned int arg = pinconf_to_config_argument(_configs[i]);
696 unsigned int index;
697
698 if (!(cfg & PIN_CFG_IOLH_B))
699 return -EINVAL;
700
701 for (index = 0; index < ARRAY_SIZE(iolh_groupb_oi); index++) {
702 if (arg == iolh_groupb_oi[index])
703 break;
704 }
705 if (index >= ARRAY_SIZE(iolh_groupb_oi))
706 return -EINVAL;
707
708 rzg2l_rmw_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK, index);
709 break;
710 }
711
712 default:
713 return -EOPNOTSUPP;
714 }
715 }
716
717 return 0;
718 }
719
rzg2l_pinctrl_pinconf_group_set(struct pinctrl_dev * pctldev,unsigned int group,unsigned long * configs,unsigned int num_configs)720 static int rzg2l_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev,
721 unsigned int group,
722 unsigned long *configs,
723 unsigned int num_configs)
724 {
725 const unsigned int *pins;
726 unsigned int i, npins;
727 int ret;
728
729 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
730 if (ret)
731 return ret;
732
733 for (i = 0; i < npins; i++) {
734 ret = rzg2l_pinctrl_pinconf_set(pctldev, pins[i], configs,
735 num_configs);
736 if (ret)
737 return ret;
738 }
739
740 return 0;
741 };
742
rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev * pctldev,unsigned int group,unsigned long * config)743 static int rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev,
744 unsigned int group,
745 unsigned long *config)
746 {
747 const unsigned int *pins;
748 unsigned int i, npins, prev_config = 0;
749 int ret;
750
751 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
752 if (ret)
753 return ret;
754
755 for (i = 0; i < npins; i++) {
756 ret = rzg2l_pinctrl_pinconf_get(pctldev, pins[i], config);
757 if (ret)
758 return ret;
759
760 /* Check config matching between to pin */
761 if (i && prev_config != *config)
762 return -EOPNOTSUPP;
763
764 prev_config = *config;
765 }
766
767 return 0;
768 };
769
770 static const struct pinctrl_ops rzg2l_pinctrl_pctlops = {
771 .get_groups_count = pinctrl_generic_get_group_count,
772 .get_group_name = pinctrl_generic_get_group_name,
773 .get_group_pins = pinctrl_generic_get_group_pins,
774 .dt_node_to_map = rzg2l_dt_node_to_map,
775 .dt_free_map = rzg2l_dt_free_map,
776 };
777
778 static const struct pinmux_ops rzg2l_pinctrl_pmxops = {
779 .get_functions_count = pinmux_generic_get_function_count,
780 .get_function_name = pinmux_generic_get_function_name,
781 .get_function_groups = pinmux_generic_get_function_groups,
782 .set_mux = rzg2l_pinctrl_set_mux,
783 .strict = true,
784 };
785
786 static const struct pinconf_ops rzg2l_pinctrl_confops = {
787 .is_generic = true,
788 .pin_config_get = rzg2l_pinctrl_pinconf_get,
789 .pin_config_set = rzg2l_pinctrl_pinconf_set,
790 .pin_config_group_set = rzg2l_pinctrl_pinconf_group_set,
791 .pin_config_group_get = rzg2l_pinctrl_pinconf_group_get,
792 .pin_config_config_dbg_show = pinconf_generic_dump_config,
793 };
794
rzg2l_gpio_request(struct gpio_chip * chip,unsigned int offset)795 static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset)
796 {
797 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
798 u32 port = RZG2L_PIN_ID_TO_PORT(offset);
799 u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
800 unsigned long flags;
801 u8 reg8;
802 int ret;
803
804 ret = pinctrl_gpio_request(chip->base + offset);
805 if (ret)
806 return ret;
807
808 spin_lock_irqsave(&pctrl->lock, flags);
809
810 /* Select GPIO mode in PMC Register */
811 reg8 = readb(pctrl->base + PMC(port));
812 reg8 &= ~BIT(bit);
813 writeb(reg8, pctrl->base + PMC(port));
814
815 spin_unlock_irqrestore(&pctrl->lock, flags);
816
817 return 0;
818 }
819
rzg2l_gpio_set_direction(struct rzg2l_pinctrl * pctrl,u32 port,u8 bit,bool output)820 static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 port,
821 u8 bit, bool output)
822 {
823 unsigned long flags;
824 u16 reg16;
825
826 spin_lock_irqsave(&pctrl->lock, flags);
827
828 reg16 = readw(pctrl->base + PM(port));
829 reg16 &= ~(PM_MASK << (bit * 2));
830
831 reg16 |= (output ? PM_OUTPUT : PM_INPUT) << (bit * 2);
832 writew(reg16, pctrl->base + PM(port));
833
834 spin_unlock_irqrestore(&pctrl->lock, flags);
835 }
836
rzg2l_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)837 static int rzg2l_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
838 {
839 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
840 u32 port = RZG2L_PIN_ID_TO_PORT(offset);
841 u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
842
843 if (!(readb(pctrl->base + PMC(port)) & BIT(bit))) {
844 u16 reg16;
845
846 reg16 = readw(pctrl->base + PM(port));
847 reg16 = (reg16 >> (bit * 2)) & PM_MASK;
848 if (reg16 == PM_OUTPUT)
849 return GPIO_LINE_DIRECTION_OUT;
850 }
851
852 return GPIO_LINE_DIRECTION_IN;
853 }
854
rzg2l_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)855 static int rzg2l_gpio_direction_input(struct gpio_chip *chip,
856 unsigned int offset)
857 {
858 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
859 u32 port = RZG2L_PIN_ID_TO_PORT(offset);
860 u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
861
862 rzg2l_gpio_set_direction(pctrl, port, bit, false);
863
864 return 0;
865 }
866
rzg2l_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)867 static void rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset,
868 int value)
869 {
870 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
871 u32 port = RZG2L_PIN_ID_TO_PORT(offset);
872 u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
873 unsigned long flags;
874 u8 reg8;
875
876 spin_lock_irqsave(&pctrl->lock, flags);
877
878 reg8 = readb(pctrl->base + P(port));
879
880 if (value)
881 writeb(reg8 | BIT(bit), pctrl->base + P(port));
882 else
883 writeb(reg8 & ~BIT(bit), pctrl->base + P(port));
884
885 spin_unlock_irqrestore(&pctrl->lock, flags);
886 }
887
rzg2l_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int value)888 static int rzg2l_gpio_direction_output(struct gpio_chip *chip,
889 unsigned int offset, int value)
890 {
891 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
892 u32 port = RZG2L_PIN_ID_TO_PORT(offset);
893 u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
894
895 rzg2l_gpio_set(chip, offset, value);
896 rzg2l_gpio_set_direction(pctrl, port, bit, true);
897
898 return 0;
899 }
900
rzg2l_gpio_get(struct gpio_chip * chip,unsigned int offset)901 static int rzg2l_gpio_get(struct gpio_chip *chip, unsigned int offset)
902 {
903 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
904 u32 port = RZG2L_PIN_ID_TO_PORT(offset);
905 u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
906 u16 reg16;
907
908 reg16 = readw(pctrl->base + PM(port));
909 reg16 = (reg16 >> (bit * 2)) & PM_MASK;
910
911 if (reg16 == PM_INPUT)
912 return !!(readb(pctrl->base + PIN(port)) & BIT(bit));
913 else if (reg16 == PM_OUTPUT)
914 return !!(readb(pctrl->base + P(port)) & BIT(bit));
915 else
916 return -EINVAL;
917 }
918
rzg2l_gpio_free(struct gpio_chip * chip,unsigned int offset)919 static void rzg2l_gpio_free(struct gpio_chip *chip, unsigned int offset)
920 {
921 unsigned int virq;
922
923 pinctrl_gpio_free(chip->base + offset);
924
925 virq = irq_find_mapping(chip->irq.domain, offset);
926 if (virq)
927 irq_dispose_mapping(virq);
928
929 /*
930 * Set the GPIO as an input to ensure that the next GPIO request won't
931 * drive the GPIO pin as an output.
932 */
933 rzg2l_gpio_direction_input(chip, offset);
934 }
935
936 static const char * const rzg2l_gpio_names[] = {
937 "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7",
938 "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7",
939 "P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7",
940 "P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7",
941 "P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7",
942 "P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7",
943 "P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7",
944 "P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7",
945 "P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7",
946 "P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7",
947 "P10_0", "P10_1", "P10_2", "P10_3", "P10_4", "P10_5", "P10_6", "P10_7",
948 "P11_0", "P11_1", "P11_2", "P11_3", "P11_4", "P11_5", "P11_6", "P11_7",
949 "P12_0", "P12_1", "P12_2", "P12_3", "P12_4", "P12_5", "P12_6", "P12_7",
950 "P13_0", "P13_1", "P13_2", "P13_3", "P13_4", "P13_5", "P13_6", "P13_7",
951 "P14_0", "P14_1", "P14_2", "P14_3", "P14_4", "P14_5", "P14_6", "P14_7",
952 "P15_0", "P15_1", "P15_2", "P15_3", "P15_4", "P15_5", "P15_6", "P15_7",
953 "P16_0", "P16_1", "P16_2", "P16_3", "P16_4", "P16_5", "P16_6", "P16_7",
954 "P17_0", "P17_1", "P17_2", "P17_3", "P17_4", "P17_5", "P17_6", "P17_7",
955 "P18_0", "P18_1", "P18_2", "P18_3", "P18_4", "P18_5", "P18_6", "P18_7",
956 "P19_0", "P19_1", "P19_2", "P19_3", "P19_4", "P19_5", "P19_6", "P19_7",
957 "P20_0", "P20_1", "P20_2", "P20_3", "P20_4", "P20_5", "P20_6", "P20_7",
958 "P21_0", "P21_1", "P21_2", "P21_3", "P21_4", "P21_5", "P21_6", "P21_7",
959 "P22_0", "P22_1", "P22_2", "P22_3", "P22_4", "P22_5", "P22_6", "P22_7",
960 "P23_0", "P23_1", "P23_2", "P23_3", "P23_4", "P23_5", "P23_6", "P23_7",
961 "P24_0", "P24_1", "P24_2", "P24_3", "P24_4", "P24_5", "P24_6", "P24_7",
962 "P25_0", "P25_1", "P25_2", "P25_3", "P25_4", "P25_5", "P25_6", "P25_7",
963 "P26_0", "P26_1", "P26_2", "P26_3", "P26_4", "P26_5", "P26_6", "P26_7",
964 "P27_0", "P27_1", "P27_2", "P27_3", "P27_4", "P27_5", "P27_6", "P27_7",
965 "P28_0", "P28_1", "P28_2", "P28_3", "P28_4", "P28_5", "P28_6", "P28_7",
966 "P29_0", "P29_1", "P29_2", "P29_3", "P29_4", "P29_5", "P29_6", "P29_7",
967 "P30_0", "P30_1", "P30_2", "P30_3", "P30_4", "P30_5", "P30_6", "P30_7",
968 "P31_0", "P31_1", "P31_2", "P31_3", "P31_4", "P31_5", "P31_6", "P31_7",
969 "P32_0", "P32_1", "P32_2", "P32_3", "P32_4", "P32_5", "P32_6", "P32_7",
970 "P33_0", "P33_1", "P33_2", "P33_3", "P33_4", "P33_5", "P33_6", "P33_7",
971 "P34_0", "P34_1", "P34_2", "P34_3", "P34_4", "P34_5", "P34_6", "P34_7",
972 "P35_0", "P35_1", "P35_2", "P35_3", "P35_4", "P35_5", "P35_6", "P35_7",
973 "P36_0", "P36_1", "P36_2", "P36_3", "P36_4", "P36_5", "P36_6", "P36_7",
974 "P37_0", "P37_1", "P37_2", "P37_3", "P37_4", "P37_5", "P37_6", "P37_7",
975 "P38_0", "P38_1", "P38_2", "P38_3", "P38_4", "P38_5", "P38_6", "P38_7",
976 "P39_0", "P39_1", "P39_2", "P39_3", "P39_4", "P39_5", "P39_6", "P39_7",
977 "P40_0", "P40_1", "P40_2", "P40_3", "P40_4", "P40_5", "P40_6", "P40_7",
978 "P41_0", "P41_1", "P41_2", "P41_3", "P41_4", "P41_5", "P41_6", "P41_7",
979 "P42_0", "P42_1", "P42_2", "P42_3", "P42_4", "P42_5", "P42_6", "P42_7",
980 "P43_0", "P43_1", "P43_2", "P43_3", "P43_4", "P43_5", "P43_6", "P43_7",
981 "P44_0", "P44_1", "P44_2", "P44_3", "P44_4", "P44_5", "P44_6", "P44_7",
982 "P45_0", "P45_1", "P45_2", "P45_3", "P45_4", "P45_5", "P45_6", "P45_7",
983 "P46_0", "P46_1", "P46_2", "P46_3", "P46_4", "P46_5", "P46_6", "P46_7",
984 "P47_0", "P47_1", "P47_2", "P47_3", "P47_4", "P47_5", "P47_6", "P47_7",
985 "P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6", "P48_7",
986 };
987
988 static const u32 rzg2l_gpio_configs[] = {
989 RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS),
990 RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS),
991 RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS),
992 RZG2L_GPIO_PORT_PACK(2, 0x13, RZG2L_MPXED_PIN_FUNCS),
993 RZG2L_GPIO_PORT_PACK(2, 0x14, RZG2L_MPXED_PIN_FUNCS),
994 RZG2L_GPIO_PORT_PACK(3, 0x15, RZG2L_MPXED_PIN_FUNCS),
995 RZG2L_GPIO_PORT_PACK(2, 0x16, RZG2L_MPXED_PIN_FUNCS),
996 RZG2L_GPIO_PORT_PACK(3, 0x17, RZG2L_MPXED_PIN_FUNCS),
997 RZG2L_GPIO_PORT_PACK(3, 0x18, RZG2L_MPXED_PIN_FUNCS),
998 RZG2L_GPIO_PORT_PACK(2, 0x19, RZG2L_MPXED_PIN_FUNCS),
999 RZG2L_GPIO_PORT_PACK(2, 0x1a, RZG2L_MPXED_PIN_FUNCS),
1000 RZG2L_GPIO_PORT_PACK(2, 0x1b, RZG2L_MPXED_PIN_FUNCS),
1001 RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS),
1002 RZG2L_GPIO_PORT_PACK(3, 0x1d, RZG2L_MPXED_PIN_FUNCS),
1003 RZG2L_GPIO_PORT_PACK(2, 0x1e, RZG2L_MPXED_PIN_FUNCS),
1004 RZG2L_GPIO_PORT_PACK(2, 0x1f, RZG2L_MPXED_PIN_FUNCS),
1005 RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS),
1006 RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS),
1007 RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS),
1008 RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS),
1009 RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1010 RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1011 RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1012 RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1013 RZG2L_GPIO_PORT_PACK(2, 0x28, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1014 RZG2L_GPIO_PORT_PACK(2, 0x29, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1015 RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1016 RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1017 RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1018 RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1019 RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1020 RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1021 RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1022 RZG2L_GPIO_PORT_PACK(2, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1023 RZG2L_GPIO_PORT_PACK(2, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1024 RZG2L_GPIO_PORT_PACK(2, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1025 RZG2L_GPIO_PORT_PACK(2, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1026 RZG2L_GPIO_PORT_PACK(3, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1027 RZG2L_GPIO_PORT_PACK(2, 0x36, RZG2L_MPXED_PIN_FUNCS),
1028 RZG2L_GPIO_PORT_PACK(3, 0x37, RZG2L_MPXED_PIN_FUNCS),
1029 RZG2L_GPIO_PORT_PACK(3, 0x38, RZG2L_MPXED_PIN_FUNCS),
1030 RZG2L_GPIO_PORT_PACK(2, 0x39, RZG2L_MPXED_PIN_FUNCS),
1031 RZG2L_GPIO_PORT_PACK(5, 0x3a, RZG2L_MPXED_PIN_FUNCS),
1032 RZG2L_GPIO_PORT_PACK(4, 0x3b, RZG2L_MPXED_PIN_FUNCS),
1033 RZG2L_GPIO_PORT_PACK(4, 0x3c, RZG2L_MPXED_PIN_FUNCS),
1034 RZG2L_GPIO_PORT_PACK(4, 0x3d, RZG2L_MPXED_PIN_FUNCS),
1035 RZG2L_GPIO_PORT_PACK(4, 0x3e, RZG2L_MPXED_PIN_FUNCS),
1036 RZG2L_GPIO_PORT_PACK(4, 0x3f, RZG2L_MPXED_PIN_FUNCS),
1037 RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS),
1038 };
1039
1040 static const u32 r9a07g043_gpio_configs[] = {
1041 RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS),
1042 RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1043 RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1044 RZG2L_GPIO_PORT_PACK(4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1045 RZG2L_GPIO_PORT_PACK(6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1046 RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS),
1047 RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS),
1048 RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1049 RZG2L_GPIO_PORT_PACK(5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1050 RZG2L_GPIO_PORT_PACK(4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1051 RZG2L_GPIO_PORT_PACK(5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1052 RZG2L_GPIO_PORT_PACK(4, 0x1b, RZG2L_MPXED_PIN_FUNCS),
1053 RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS),
1054 RZG2L_GPIO_PORT_PACK(5, 0x1d, RZG2L_MPXED_PIN_FUNCS),
1055 RZG2L_GPIO_PORT_PACK(3, 0x1e, RZG2L_MPXED_PIN_FUNCS),
1056 RZG2L_GPIO_PORT_PACK(4, 0x1f, RZG2L_MPXED_PIN_FUNCS),
1057 RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS),
1058 RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS),
1059 RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS),
1060 };
1061
1062 static struct {
1063 struct rzg2l_dedicated_configs common[35];
1064 struct rzg2l_dedicated_configs rzg2l_pins[7];
1065 } rzg2l_dedicated_pins = {
1066 .common = {
1067 { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0,
1068 (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) },
1069 { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0,
1070 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) },
1071 { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0,
1072 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) },
1073 { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) },
1074 { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) },
1075 { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0,
1076 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) },
1077 { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1,
1078 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1079 { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2,
1080 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) },
1081 { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0,
1082 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1083 { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1,
1084 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1085 { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2,
1086 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1087 { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3,
1088 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1089 { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4,
1090 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1091 { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5,
1092 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1093 { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6,
1094 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1095 { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x7, 7,
1096 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1097 { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0,
1098 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1)) },
1099 { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x8, 1,
1100 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
1101 { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x9, 0,
1102 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
1103 { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x9, 1,
1104 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
1105 { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x9, 2,
1106 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
1107 { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x9, 3,
1108 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
1109 { "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0,
1110 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1111 { "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1,
1112 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1113 { "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2,
1114 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1115 { "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3,
1116 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1117 { "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4,
1118 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1119 { "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5,
1120 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1121 { "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0,
1122 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1123 { "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1,
1124 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1125 { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) },
1126 { "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) },
1127 { "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) },
1128 { "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) },
1129 { "RIIC1_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 3, PIN_CFG_IEN) },
1130 },
1131 .rzg2l_pins = {
1132 { "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1133 { "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0,
1134 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1135 { "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1,
1136 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1137 { "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2,
1138 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1139 { "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3,
1140 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1141 { "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4,
1142 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1143 { "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5,
1144 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1145 }
1146 };
1147
rzg2l_gpio_get_gpioint(unsigned int virq,const struct rzg2l_pinctrl_data * data)1148 static int rzg2l_gpio_get_gpioint(unsigned int virq, const struct rzg2l_pinctrl_data *data)
1149 {
1150 unsigned int gpioint;
1151 unsigned int i;
1152 u32 port, bit;
1153
1154 port = virq / 8;
1155 bit = virq % 8;
1156
1157 if (port >= data->n_ports ||
1158 bit >= RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[port]))
1159 return -EINVAL;
1160
1161 gpioint = bit;
1162 for (i = 0; i < port; i++)
1163 gpioint += RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[i]);
1164
1165 return gpioint;
1166 }
1167
rzg2l_gpio_irq_disable(struct irq_data * d)1168 static void rzg2l_gpio_irq_disable(struct irq_data *d)
1169 {
1170 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1171 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip);
1172 unsigned int hwirq = irqd_to_hwirq(d);
1173 unsigned long flags;
1174 void __iomem *addr;
1175 u32 port;
1176 u8 bit;
1177
1178 irq_chip_disable_parent(d);
1179
1180 port = RZG2L_PIN_ID_TO_PORT(hwirq);
1181 bit = RZG2L_PIN_ID_TO_PIN(hwirq);
1182
1183 addr = pctrl->base + ISEL(port);
1184 if (bit >= 4) {
1185 bit -= 4;
1186 addr += 4;
1187 }
1188
1189 spin_lock_irqsave(&pctrl->lock, flags);
1190 writel(readl(addr) & ~BIT(bit * 8), addr);
1191 spin_unlock_irqrestore(&pctrl->lock, flags);
1192
1193 gpiochip_disable_irq(gc, hwirq);
1194 }
1195
rzg2l_gpio_irq_enable(struct irq_data * d)1196 static void rzg2l_gpio_irq_enable(struct irq_data *d)
1197 {
1198 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1199 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip);
1200 unsigned int hwirq = irqd_to_hwirq(d);
1201 unsigned long flags;
1202 void __iomem *addr;
1203 u32 port;
1204 u8 bit;
1205
1206 gpiochip_enable_irq(gc, hwirq);
1207
1208 port = RZG2L_PIN_ID_TO_PORT(hwirq);
1209 bit = RZG2L_PIN_ID_TO_PIN(hwirq);
1210
1211 addr = pctrl->base + ISEL(port);
1212 if (bit >= 4) {
1213 bit -= 4;
1214 addr += 4;
1215 }
1216
1217 spin_lock_irqsave(&pctrl->lock, flags);
1218 writel(readl(addr) | BIT(bit * 8), addr);
1219 spin_unlock_irqrestore(&pctrl->lock, flags);
1220
1221 irq_chip_enable_parent(d);
1222 }
1223
rzg2l_gpio_irq_set_type(struct irq_data * d,unsigned int type)1224 static int rzg2l_gpio_irq_set_type(struct irq_data *d, unsigned int type)
1225 {
1226 return irq_chip_set_type_parent(d, type);
1227 }
1228
rzg2l_gpio_irqc_eoi(struct irq_data * d)1229 static void rzg2l_gpio_irqc_eoi(struct irq_data *d)
1230 {
1231 irq_chip_eoi_parent(d);
1232 }
1233
rzg2l_gpio_irq_print_chip(struct irq_data * data,struct seq_file * p)1234 static void rzg2l_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p)
1235 {
1236 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
1237
1238 seq_printf(p, dev_name(gc->parent));
1239 }
1240
1241 static const struct irq_chip rzg2l_gpio_irqchip = {
1242 .name = "rzg2l-gpio",
1243 .irq_disable = rzg2l_gpio_irq_disable,
1244 .irq_enable = rzg2l_gpio_irq_enable,
1245 .irq_mask = irq_chip_mask_parent,
1246 .irq_unmask = irq_chip_unmask_parent,
1247 .irq_set_type = rzg2l_gpio_irq_set_type,
1248 .irq_eoi = rzg2l_gpio_irqc_eoi,
1249 .irq_print_chip = rzg2l_gpio_irq_print_chip,
1250 .flags = IRQCHIP_IMMUTABLE,
1251 GPIOCHIP_IRQ_RESOURCE_HELPERS,
1252 };
1253
rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip * gc,unsigned int child,unsigned int child_type,unsigned int * parent,unsigned int * parent_type)1254 static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
1255 unsigned int child,
1256 unsigned int child_type,
1257 unsigned int *parent,
1258 unsigned int *parent_type)
1259 {
1260 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc);
1261 unsigned long flags;
1262 int gpioint, irq;
1263
1264 gpioint = rzg2l_gpio_get_gpioint(child, pctrl->data);
1265 if (gpioint < 0)
1266 return gpioint;
1267
1268 spin_lock_irqsave(&pctrl->bitmap_lock, flags);
1269 irq = bitmap_find_free_region(pctrl->tint_slot, RZG2L_TINT_MAX_INTERRUPT, get_order(1));
1270 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags);
1271 if (irq < 0)
1272 return -ENOSPC;
1273 pctrl->hwirq[irq] = child;
1274 irq += RZG2L_TINT_IRQ_START_INDEX;
1275
1276 /* All these interrupts are level high in the CPU */
1277 *parent_type = IRQ_TYPE_LEVEL_HIGH;
1278 *parent = RZG2L_PACK_HWIRQ(gpioint, irq);
1279 return 0;
1280 }
1281
rzg2l_gpio_populate_parent_fwspec(struct gpio_chip * chip,union gpio_irq_fwspec * gfwspec,unsigned int parent_hwirq,unsigned int parent_type)1282 static int rzg2l_gpio_populate_parent_fwspec(struct gpio_chip *chip,
1283 union gpio_irq_fwspec *gfwspec,
1284 unsigned int parent_hwirq,
1285 unsigned int parent_type)
1286 {
1287 struct irq_fwspec *fwspec = &gfwspec->fwspec;
1288
1289 fwspec->fwnode = chip->irq.parent_domain->fwnode;
1290 fwspec->param_count = 2;
1291 fwspec->param[0] = parent_hwirq;
1292 fwspec->param[1] = parent_type;
1293
1294 return 0;
1295 }
1296
rzg2l_gpio_irq_domain_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)1297 static void rzg2l_gpio_irq_domain_free(struct irq_domain *domain, unsigned int virq,
1298 unsigned int nr_irqs)
1299 {
1300 struct irq_data *d;
1301
1302 d = irq_domain_get_irq_data(domain, virq);
1303 if (d) {
1304 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1305 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip);
1306 irq_hw_number_t hwirq = irqd_to_hwirq(d);
1307 unsigned long flags;
1308 unsigned int i;
1309
1310 for (i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) {
1311 if (pctrl->hwirq[i] == hwirq) {
1312 spin_lock_irqsave(&pctrl->bitmap_lock, flags);
1313 bitmap_release_region(pctrl->tint_slot, i, get_order(1));
1314 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags);
1315 pctrl->hwirq[i] = 0;
1316 break;
1317 }
1318 }
1319 }
1320 irq_domain_free_irqs_common(domain, virq, nr_irqs);
1321 }
1322
rzg2l_init_irq_valid_mask(struct gpio_chip * gc,unsigned long * valid_mask,unsigned int ngpios)1323 static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc,
1324 unsigned long *valid_mask,
1325 unsigned int ngpios)
1326 {
1327 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc);
1328 struct gpio_chip *chip = &pctrl->gpio_chip;
1329 unsigned int offset;
1330
1331 /* Forbid unused lines to be mapped as IRQs */
1332 for (offset = 0; offset < chip->ngpio; offset++) {
1333 u32 port, bit;
1334
1335 port = offset / 8;
1336 bit = offset % 8;
1337
1338 if (port >= pctrl->data->n_ports ||
1339 bit >= RZG2L_GPIO_PORT_GET_PINCNT(pctrl->data->port_pin_configs[port]))
1340 clear_bit(offset, valid_mask);
1341 }
1342 }
1343
rzg2l_gpio_register(struct rzg2l_pinctrl * pctrl)1344 static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl)
1345 {
1346 struct device_node *np = pctrl->dev->of_node;
1347 struct gpio_chip *chip = &pctrl->gpio_chip;
1348 const char *name = dev_name(pctrl->dev);
1349 struct irq_domain *parent_domain;
1350 struct of_phandle_args of_args;
1351 struct device_node *parent_np;
1352 struct gpio_irq_chip *girq;
1353 int ret;
1354
1355 parent_np = of_irq_find_parent(np);
1356 if (!parent_np)
1357 return -ENXIO;
1358
1359 parent_domain = irq_find_host(parent_np);
1360 of_node_put(parent_np);
1361 if (!parent_domain)
1362 return -EPROBE_DEFER;
1363
1364 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args);
1365 if (ret) {
1366 dev_err(pctrl->dev, "Unable to parse gpio-ranges\n");
1367 return ret;
1368 }
1369
1370 if (of_args.args[0] != 0 || of_args.args[1] != 0 ||
1371 of_args.args[2] != pctrl->data->n_port_pins) {
1372 dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n");
1373 return -EINVAL;
1374 }
1375
1376 chip->names = pctrl->data->port_pins;
1377 chip->request = rzg2l_gpio_request;
1378 chip->free = rzg2l_gpio_free;
1379 chip->get_direction = rzg2l_gpio_get_direction;
1380 chip->direction_input = rzg2l_gpio_direction_input;
1381 chip->direction_output = rzg2l_gpio_direction_output;
1382 chip->get = rzg2l_gpio_get;
1383 chip->set = rzg2l_gpio_set;
1384 chip->label = name;
1385 chip->parent = pctrl->dev;
1386 chip->owner = THIS_MODULE;
1387 chip->base = -1;
1388 chip->ngpio = of_args.args[2];
1389
1390 girq = &chip->irq;
1391 gpio_irq_chip_set_chip(girq, &rzg2l_gpio_irqchip);
1392 girq->fwnode = of_node_to_fwnode(np);
1393 girq->parent_domain = parent_domain;
1394 girq->child_to_parent_hwirq = rzg2l_gpio_child_to_parent_hwirq;
1395 girq->populate_parent_alloc_arg = rzg2l_gpio_populate_parent_fwspec;
1396 girq->child_irq_domain_ops.free = rzg2l_gpio_irq_domain_free;
1397 girq->init_valid_mask = rzg2l_init_irq_valid_mask;
1398
1399 pctrl->gpio_range.id = 0;
1400 pctrl->gpio_range.pin_base = 0;
1401 pctrl->gpio_range.base = 0;
1402 pctrl->gpio_range.npins = chip->ngpio;
1403 pctrl->gpio_range.name = chip->label;
1404 pctrl->gpio_range.gc = chip;
1405 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
1406 if (ret) {
1407 dev_err(pctrl->dev, "failed to add GPIO controller\n");
1408 return ret;
1409 }
1410
1411 dev_dbg(pctrl->dev, "Registered gpio controller\n");
1412
1413 return 0;
1414 }
1415
rzg2l_pinctrl_register(struct rzg2l_pinctrl * pctrl)1416 static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl)
1417 {
1418 struct pinctrl_pin_desc *pins;
1419 unsigned int i, j;
1420 u32 *pin_data;
1421 int ret;
1422
1423 pctrl->desc.name = DRV_NAME;
1424 pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins;
1425 pctrl->desc.pctlops = &rzg2l_pinctrl_pctlops;
1426 pctrl->desc.pmxops = &rzg2l_pinctrl_pmxops;
1427 pctrl->desc.confops = &rzg2l_pinctrl_confops;
1428 pctrl->desc.owner = THIS_MODULE;
1429
1430 pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL);
1431 if (!pins)
1432 return -ENOMEM;
1433
1434 pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins,
1435 sizeof(*pin_data), GFP_KERNEL);
1436 if (!pin_data)
1437 return -ENOMEM;
1438
1439 pctrl->pins = pins;
1440 pctrl->desc.pins = pins;
1441
1442 for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) {
1443 pins[i].number = i;
1444 pins[i].name = pctrl->data->port_pins[i];
1445 if (i && !(i % RZG2L_PINS_PER_PORT))
1446 j++;
1447 pin_data[i] = pctrl->data->port_pin_configs[j];
1448 pins[i].drv_data = &pin_data[i];
1449 }
1450
1451 for (i = 0; i < pctrl->data->n_dedicated_pins; i++) {
1452 unsigned int index = pctrl->data->n_port_pins + i;
1453
1454 pins[index].number = index;
1455 pins[index].name = pctrl->data->dedicated_pins[i].name;
1456 pin_data[index] = pctrl->data->dedicated_pins[i].config;
1457 pins[index].drv_data = &pin_data[index];
1458 }
1459
1460 ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl,
1461 &pctrl->pctl);
1462 if (ret) {
1463 dev_err(pctrl->dev, "pinctrl registration failed\n");
1464 return ret;
1465 }
1466
1467 ret = pinctrl_enable(pctrl->pctl);
1468 if (ret) {
1469 dev_err(pctrl->dev, "pinctrl enable failed\n");
1470 return ret;
1471 }
1472
1473 ret = rzg2l_gpio_register(pctrl);
1474 if (ret) {
1475 dev_err(pctrl->dev, "failed to add GPIO chip: %i\n", ret);
1476 return ret;
1477 }
1478
1479 return 0;
1480 }
1481
rzg2l_pinctrl_probe(struct platform_device * pdev)1482 static int rzg2l_pinctrl_probe(struct platform_device *pdev)
1483 {
1484 struct rzg2l_pinctrl *pctrl;
1485 struct clk *clk;
1486 int ret;
1487
1488 BUILD_BUG_ON(ARRAY_SIZE(rzg2l_gpio_configs) * RZG2L_PINS_PER_PORT >
1489 ARRAY_SIZE(rzg2l_gpio_names));
1490
1491 BUILD_BUG_ON(ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT >
1492 ARRAY_SIZE(rzg2l_gpio_names));
1493
1494 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1495 if (!pctrl)
1496 return -ENOMEM;
1497
1498 pctrl->dev = &pdev->dev;
1499
1500 pctrl->data = of_device_get_match_data(&pdev->dev);
1501 if (!pctrl->data)
1502 return -EINVAL;
1503
1504 pctrl->base = devm_platform_ioremap_resource(pdev, 0);
1505 if (IS_ERR(pctrl->base))
1506 return PTR_ERR(pctrl->base);
1507
1508 clk = devm_clk_get_enabled(pctrl->dev, NULL);
1509 if (IS_ERR(clk))
1510 return dev_err_probe(pctrl->dev, PTR_ERR(clk),
1511 "failed to enable GPIO clk\n");
1512
1513 spin_lock_init(&pctrl->lock);
1514 spin_lock_init(&pctrl->bitmap_lock);
1515 mutex_init(&pctrl->mutex);
1516
1517 platform_set_drvdata(pdev, pctrl);
1518
1519 ret = rzg2l_pinctrl_register(pctrl);
1520 if (ret)
1521 return ret;
1522
1523 dev_info(pctrl->dev, "%s support registered\n", DRV_NAME);
1524 return 0;
1525 }
1526
1527 static struct rzg2l_pinctrl_data r9a07g043_data = {
1528 .port_pins = rzg2l_gpio_names,
1529 .port_pin_configs = r9a07g043_gpio_configs,
1530 .n_ports = ARRAY_SIZE(r9a07g043_gpio_configs),
1531 .dedicated_pins = rzg2l_dedicated_pins.common,
1532 .n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT,
1533 .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common),
1534 };
1535
1536 static struct rzg2l_pinctrl_data r9a07g044_data = {
1537 .port_pins = rzg2l_gpio_names,
1538 .port_pin_configs = rzg2l_gpio_configs,
1539 .n_ports = ARRAY_SIZE(rzg2l_gpio_configs),
1540 .dedicated_pins = rzg2l_dedicated_pins.common,
1541 .n_port_pins = ARRAY_SIZE(rzg2l_gpio_configs) * RZG2L_PINS_PER_PORT,
1542 .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) +
1543 ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins),
1544 };
1545
1546 static const struct of_device_id rzg2l_pinctrl_of_table[] = {
1547 {
1548 .compatible = "renesas,r9a07g043-pinctrl",
1549 .data = &r9a07g043_data,
1550 },
1551 {
1552 .compatible = "renesas,r9a07g044-pinctrl",
1553 .data = &r9a07g044_data,
1554 },
1555 { /* sentinel */ }
1556 };
1557
1558 static struct platform_driver rzg2l_pinctrl_driver = {
1559 .driver = {
1560 .name = DRV_NAME,
1561 .of_match_table = of_match_ptr(rzg2l_pinctrl_of_table),
1562 },
1563 .probe = rzg2l_pinctrl_probe,
1564 };
1565
rzg2l_pinctrl_init(void)1566 static int __init rzg2l_pinctrl_init(void)
1567 {
1568 return platform_driver_register(&rzg2l_pinctrl_driver);
1569 }
1570 core_initcall(rzg2l_pinctrl_init);
1571
1572 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
1573 MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/G2L family");
1574