1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * R8A779A0 processor support - PFC hardware block.
4  *
5  * Copyright (C) 2021 Renesas Electronics Corp.
6  *
7  * This file is based on the drivers/pinctrl/renesas/pfc-r8a779a0.c
8  */
9 
10 #include <linux/errno.h>
11 #include <linux/io.h>
12 #include <linux/kernel.h>
13 
14 #include "sh_pfc.h"
15 
16 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
17 
18 #define CPU_ALL_GP(fn, sfx)								\
19 	PORT_GP_CFG_19(0,	fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
20 	PORT_GP_CFG_23(1,	fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
21 	PORT_GP_CFG_1(1, 23,	fn, sfx, CFG_FLAGS),					\
22 	PORT_GP_CFG_1(1, 24,	fn, sfx, CFG_FLAGS),					\
23 	PORT_GP_CFG_1(1, 25,	fn, sfx, CFG_FLAGS),					\
24 	PORT_GP_CFG_1(1, 26,	fn, sfx, CFG_FLAGS),					\
25 	PORT_GP_CFG_1(1, 27,	fn, sfx, CFG_FLAGS),					\
26 	PORT_GP_CFG_1(1, 28,	fn, sfx, CFG_FLAGS),					\
27 	PORT_GP_CFG_20(2,	fn, sfx, CFG_FLAGS),					\
28 	PORT_GP_CFG_13(3,	fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
29 	PORT_GP_CFG_1(3, 13,	fn, sfx, CFG_FLAGS),					\
30 	PORT_GP_CFG_1(3, 14,	fn, sfx, CFG_FLAGS),					\
31 	PORT_GP_CFG_1(3, 15,	fn, sfx, CFG_FLAGS),					\
32 	PORT_GP_CFG_1(3, 16,	fn, sfx, CFG_FLAGS),					\
33 	PORT_GP_CFG_1(3, 17,	fn, sfx, CFG_FLAGS),					\
34 	PORT_GP_CFG_1(3, 18,	fn, sfx, CFG_FLAGS),					\
35 	PORT_GP_CFG_1(3, 19,	fn, sfx, CFG_FLAGS),					\
36 	PORT_GP_CFG_1(3, 20,	fn, sfx, CFG_FLAGS),					\
37 	PORT_GP_CFG_1(3, 21,	fn, sfx, CFG_FLAGS),					\
38 	PORT_GP_CFG_1(3, 22,	fn, sfx, CFG_FLAGS),					\
39 	PORT_GP_CFG_1(3, 23,	fn, sfx, CFG_FLAGS),					\
40 	PORT_GP_CFG_1(3, 24,	fn, sfx, CFG_FLAGS),					\
41 	PORT_GP_CFG_1(3, 25,	fn, sfx, CFG_FLAGS),					\
42 	PORT_GP_CFG_1(3, 26,	fn, sfx, CFG_FLAGS),					\
43 	PORT_GP_CFG_1(3, 27,	fn, sfx, CFG_FLAGS),					\
44 	PORT_GP_CFG_1(3, 28,	fn, sfx, CFG_FLAGS),					\
45 	PORT_GP_CFG_1(3, 29,	fn, sfx, CFG_FLAGS),					\
46 	PORT_GP_CFG_25(4,	fn, sfx, CFG_FLAGS),					\
47 	PORT_GP_CFG_21(5,	fn, sfx, CFG_FLAGS),					\
48 	PORT_GP_CFG_21(6,	fn, sfx, CFG_FLAGS),					\
49 	PORT_GP_CFG_21(7,	fn, sfx, CFG_FLAGS),					\
50 	PORT_GP_CFG_14(8,	fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33)
51 
52 /* GPSR0 */
53 #define GPSR0_18	F_(MSIOF2_RXD,		IP2SR0_11_8)
54 #define GPSR0_17	F_(MSIOF2_SCK,		IP2SR0_7_4)
55 #define GPSR0_16	F_(MSIOF2_TXD,		IP2SR0_3_0)
56 #define GPSR0_15	F_(MSIOF2_SYNC,		IP1SR0_31_28)
57 #define GPSR0_14	F_(MSIOF2_SS1,		IP1SR0_27_24)
58 #define GPSR0_13	F_(MSIOF2_SS2,		IP1SR0_23_20)
59 #define GPSR0_12	F_(MSIOF5_RXD,		IP1SR0_19_16)
60 #define GPSR0_11	F_(MSIOF5_SCK,		IP1SR0_15_12)
61 #define GPSR0_10	F_(MSIOF5_TXD,		IP1SR0_11_8)
62 #define GPSR0_9		F_(MSIOF5_SYNC,		IP1SR0_7_4)
63 #define GPSR0_8		F_(MSIOF5_SS1,		IP1SR0_3_0)
64 #define GPSR0_7		F_(MSIOF5_SS2,		IP0SR0_31_28)
65 #define GPSR0_6		F_(IRQ0,		IP0SR0_27_24)
66 #define GPSR0_5		F_(IRQ1,		IP0SR0_23_20)
67 #define GPSR0_4		F_(IRQ2,		IP0SR0_19_16)
68 #define GPSR0_3		F_(IRQ3,		IP0SR0_15_12)
69 #define GPSR0_2		F_(GP0_02,		IP0SR0_11_8)
70 #define GPSR0_1		F_(GP0_01,		IP0SR0_7_4)
71 #define GPSR0_0		F_(GP0_00,		IP0SR0_3_0)
72 
73 /* GPSR1 */
74 #define GPSR1_28	F_(HTX3,		IP3SR1_19_16)
75 #define GPSR1_27	F_(HCTS3_N,		IP3SR1_15_12)
76 #define GPSR1_26	F_(HRTS3_N,		IP3SR1_11_8)
77 #define GPSR1_25	F_(HSCK3,		IP3SR1_7_4)
78 #define GPSR1_24	F_(HRX3,		IP3SR1_3_0)
79 #define GPSR1_23	F_(GP1_23,		IP2SR1_31_28)
80 #define GPSR1_22	F_(AUDIO_CLKIN,		IP2SR1_27_24)
81 #define GPSR1_21	F_(AUDIO_CLKOUT,	IP2SR1_23_20)
82 #define GPSR1_20	F_(SSI_SD,		IP2SR1_19_16)
83 #define GPSR1_19	F_(SSI_WS,		IP2SR1_15_12)
84 #define GPSR1_18	F_(SSI_SCK,		IP2SR1_11_8)
85 #define GPSR1_17	F_(SCIF_CLK,		IP2SR1_7_4)
86 #define GPSR1_16	F_(HRX0,		IP2SR1_3_0)
87 #define GPSR1_15	F_(HSCK0,		IP1SR1_31_28)
88 #define GPSR1_14	F_(HRTS0_N,		IP1SR1_27_24)
89 #define GPSR1_13	F_(HCTS0_N,		IP1SR1_23_20)
90 #define GPSR1_12	F_(HTX0,		IP1SR1_19_16)
91 #define GPSR1_11	F_(MSIOF0_RXD,		IP1SR1_15_12)
92 #define GPSR1_10	F_(MSIOF0_SCK,		IP1SR1_11_8)
93 #define GPSR1_9		F_(MSIOF0_TXD,		IP1SR1_7_4)
94 #define GPSR1_8		F_(MSIOF0_SYNC,		IP1SR1_3_0)
95 #define GPSR1_7		F_(MSIOF0_SS1,		IP0SR1_31_28)
96 #define GPSR1_6		F_(MSIOF0_SS2,		IP0SR1_27_24)
97 #define GPSR1_5		F_(MSIOF1_RXD,		IP0SR1_23_20)
98 #define GPSR1_4		F_(MSIOF1_TXD,		IP0SR1_19_16)
99 #define GPSR1_3		F_(MSIOF1_SCK,		IP0SR1_15_12)
100 #define GPSR1_2		F_(MSIOF1_SYNC,		IP0SR1_11_8)
101 #define GPSR1_1		F_(MSIOF1_SS1,		IP0SR1_7_4)
102 #define GPSR1_0		F_(MSIOF1_SS2,		IP0SR1_3_0)
103 
104 /* GPSR2 */
105 #define GPSR2_19	F_(CANFD7_RX,		IP2SR2_15_12)
106 #define GPSR2_18	F_(CANFD7_TX,		IP2SR2_11_8)
107 #define GPSR2_17	F_(CANFD4_RX,		IP2SR2_7_4)
108 #define GPSR2_16	F_(CANFD4_TX,		IP2SR2_3_0)
109 #define GPSR2_15	F_(CANFD3_RX,		IP1SR2_31_28)
110 #define GPSR2_14	F_(CANFD3_TX,		IP1SR2_27_24)
111 #define GPSR2_13	F_(CANFD2_RX,		IP1SR2_23_20)
112 #define GPSR2_12	F_(CANFD2_TX,		IP1SR2_19_16)
113 #define GPSR2_11	F_(CANFD0_RX,		IP1SR2_15_12)
114 #define GPSR2_10	F_(CANFD0_TX,		IP1SR2_11_8)
115 #define GPSR2_9		F_(CAN_CLK,		IP1SR2_7_4)
116 #define GPSR2_8		F_(TPU0TO0,		IP1SR2_3_0)
117 #define GPSR2_7		F_(TPU0TO1,		IP0SR2_31_28)
118 #define GPSR2_6		F_(FXR_TXDB,		IP0SR2_27_24)
119 #define GPSR2_5		F_(FXR_TXENB_N,		IP0SR2_23_20)
120 #define GPSR2_4		F_(RXDB_EXTFXR,		IP0SR2_19_16)
121 #define GPSR2_3		F_(CLK_EXTFXR,		IP0SR2_15_12)
122 #define GPSR2_2		F_(RXDA_EXTFXR,		IP0SR2_11_8)
123 #define GPSR2_1		F_(FXR_TXENA_N,		IP0SR2_7_4)
124 #define GPSR2_0		F_(FXR_TXDA,		IP0SR2_3_0)
125 
126 /* GPSR3 */
127 #define GPSR3_29	F_(RPC_INT_N,		IP3SR3_23_20)
128 #define GPSR3_28	F_(RPC_WP_N,		IP3SR3_19_16)
129 #define GPSR3_27	F_(RPC_RESET_N,		IP3SR3_15_12)
130 #define GPSR3_26	F_(QSPI1_IO3,		IP3SR3_11_8)
131 #define GPSR3_25	F_(QSPI1_SSL,		IP3SR3_7_4)
132 #define GPSR3_24	F_(QSPI1_IO2,		IP3SR3_3_0)
133 #define GPSR3_23	F_(QSPI1_MISO_IO1,	IP2SR3_31_28)
134 #define GPSR3_22	F_(QSPI1_SPCLK,		IP2SR3_27_24)
135 #define GPSR3_21	F_(QSPI1_MOSI_IO0,	IP2SR3_23_20)
136 #define GPSR3_20	F_(QSPI0_SPCLK,		IP2SR3_19_16)
137 #define GPSR3_19	F_(QSPI0_MOSI_IO0,	IP2SR3_15_12)
138 #define GPSR3_18	F_(QSPI0_MISO_IO1,	IP2SR3_11_8)
139 #define GPSR3_17	F_(QSPI0_IO2,		IP2SR3_7_4)
140 #define GPSR3_16	F_(QSPI0_IO3,		IP2SR3_3_0)
141 #define GPSR3_15	F_(QSPI0_SSL,		IP1SR3_31_28)
142 #define GPSR3_14	F_(IPC_CLKOUT,		IP1SR3_27_24)
143 #define GPSR3_13	F_(IPC_CLKIN,		IP1SR3_23_20)
144 #define GPSR3_12	F_(SD_WP,		IP1SR3_19_16)
145 #define GPSR3_11	F_(SD_CD,		IP1SR3_15_12)
146 #define GPSR3_10	F_(MMC_SD_CMD,		IP1SR3_11_8)
147 #define GPSR3_9		F_(MMC_D6,		IP1SR3_7_4)
148 #define GPSR3_8		F_(MMC_D7,		IP1SR3_3_0)
149 #define GPSR3_7		F_(MMC_D4,		IP0SR3_31_28)
150 #define GPSR3_6		F_(MMC_D5,		IP0SR3_27_24)
151 #define GPSR3_5		F_(MMC_SD_D3,		IP0SR3_23_20)
152 #define GPSR3_4		F_(MMC_DS,		IP0SR3_19_16)
153 #define GPSR3_3		F_(MMC_SD_CLK,		IP0SR3_15_12)
154 #define GPSR3_2		F_(MMC_SD_D2,		IP0SR3_11_8)
155 #define GPSR3_1		F_(MMC_SD_D0,		IP0SR3_7_4)
156 #define GPSR3_0		F_(MMC_SD_D1,		IP0SR3_3_0)
157 
158 /* GPSR4 */
159 #define GPSR4_24	FM(AVS1)
160 #define GPSR4_23	FM(AVS0)
161 #define GPSR4_22	FM(PCIE1_CLKREQ_N)
162 #define GPSR4_21	FM(PCIE0_CLKREQ_N)
163 #define GPSR4_20	FM(TSN0_TXCREFCLK)
164 #define GPSR4_19	FM(TSN0_TD2)
165 #define GPSR4_18	FM(TSN0_TD3)
166 #define GPSR4_17	FM(TSN0_RD2)
167 #define GPSR4_16	FM(TSN0_RD3)
168 #define GPSR4_15	FM(TSN0_TD0)
169 #define GPSR4_14	FM(TSN0_TD1)
170 #define GPSR4_13	FM(TSN0_RD1)
171 #define GPSR4_12	FM(TSN0_TXC)
172 #define GPSR4_11	FM(TSN0_RXC)
173 #define GPSR4_10	FM(TSN0_RD0)
174 #define GPSR4_9		FM(TSN0_TX_CTL)
175 #define GPSR4_8		FM(TSN0_AVTP_PPS0)
176 #define GPSR4_7		FM(TSN0_RX_CTL)
177 #define GPSR4_6		FM(TSN0_AVTP_CAPTURE)
178 #define GPSR4_5		FM(TSN0_AVTP_MATCH)
179 #define GPSR4_4		FM(TSN0_LINK)
180 #define GPSR4_3		FM(TSN0_PHY_INT)
181 #define GPSR4_2		FM(TSN0_AVTP_PPS1)
182 #define GPSR4_1		FM(TSN0_MDC)
183 #define GPSR4_0		FM(TSN0_MDIO)
184 
185 /* GPSR 5 */
186 #define GPSR5_20	FM(AVB2_RX_CTL)
187 #define GPSR5_19	FM(AVB2_TX_CTL)
188 #define GPSR5_18	FM(AVB2_RXC)
189 #define GPSR5_17	FM(AVB2_RD0)
190 #define GPSR5_16	FM(AVB2_TXC)
191 #define GPSR5_15	FM(AVB2_TD0)
192 #define GPSR5_14	FM(AVB2_RD1)
193 #define GPSR5_13	FM(AVB2_RD2)
194 #define GPSR5_12	FM(AVB2_TD1)
195 #define GPSR5_11	FM(AVB2_TD2)
196 #define GPSR5_10	FM(AVB2_MDIO)
197 #define GPSR5_9		FM(AVB2_RD3)
198 #define GPSR5_8		FM(AVB2_TD3)
199 #define GPSR5_7		FM(AVB2_TXCREFCLK)
200 #define GPSR5_6		FM(AVB2_MDC)
201 #define GPSR5_5		FM(AVB2_MAGIC)
202 #define GPSR5_4		FM(AVB2_PHY_INT)
203 #define GPSR5_3		FM(AVB2_LINK)
204 #define GPSR5_2		FM(AVB2_AVTP_MATCH)
205 #define GPSR5_1		FM(AVB2_AVTP_CAPTURE)
206 #define GPSR5_0		FM(AVB2_AVTP_PPS)
207 
208 /* GPSR 6 */
209 #define GPSR6_20	F_(AVB1_TXCREFCLK,		IP2SR6_19_16)
210 #define GPSR6_19	F_(AVB1_RD3,			IP2SR6_15_12)
211 #define GPSR6_18	F_(AVB1_TD3,			IP2SR6_11_8)
212 #define GPSR6_17	F_(AVB1_RD2,			IP2SR6_7_4)
213 #define GPSR6_16	F_(AVB1_TD2,			IP2SR6_3_0)
214 #define GPSR6_15	F_(AVB1_RD0,			IP1SR6_31_28)
215 #define GPSR6_14	F_(AVB1_RD1,			IP1SR6_27_24)
216 #define GPSR6_13	F_(AVB1_TD0,			IP1SR6_23_20)
217 #define GPSR6_12	F_(AVB1_TD1,			IP1SR6_19_16)
218 #define GPSR6_11	F_(AVB1_AVTP_CAPTURE,		IP1SR6_15_12)
219 #define GPSR6_10	F_(AVB1_AVTP_PPS,		IP1SR6_11_8)
220 #define GPSR6_9		F_(AVB1_RX_CTL,			IP1SR6_7_4)
221 #define GPSR6_8		F_(AVB1_RXC,			IP1SR6_3_0)
222 #define GPSR6_7		F_(AVB1_TX_CTL,			IP0SR6_31_28)
223 #define GPSR6_6		F_(AVB1_TXC,			IP0SR6_27_24)
224 #define GPSR6_5		F_(AVB1_AVTP_MATCH,		IP0SR6_23_20)
225 #define GPSR6_4		F_(AVB1_LINK,			IP0SR6_19_16)
226 #define GPSR6_3		F_(AVB1_PHY_INT,		IP0SR6_15_12)
227 #define GPSR6_2		F_(AVB1_MDC,			IP0SR6_11_8)
228 #define GPSR6_1		F_(AVB1_MAGIC,			IP0SR6_7_4)
229 #define GPSR6_0		F_(AVB1_MDIO,			IP0SR6_3_0)
230 
231 /* GPSR7 */
232 #define GPSR7_20	F_(AVB0_RX_CTL,			IP2SR7_19_16)
233 #define GPSR7_19	F_(AVB0_RXC,			IP2SR7_15_12)
234 #define GPSR7_18	F_(AVB0_RD0,			IP2SR7_11_8)
235 #define GPSR7_17	F_(AVB0_RD1,			IP2SR7_7_4)
236 #define GPSR7_16	F_(AVB0_TX_CTL,			IP2SR7_3_0)
237 #define GPSR7_15	F_(AVB0_TXC,			IP1SR7_31_28)
238 #define GPSR7_14	F_(AVB0_MDIO,			IP1SR7_27_24)
239 #define GPSR7_13	F_(AVB0_MDC,			IP1SR7_23_20)
240 #define GPSR7_12	F_(AVB0_RD2,			IP1SR7_19_16)
241 #define GPSR7_11	F_(AVB0_TD0,			IP1SR7_15_12)
242 #define GPSR7_10	F_(AVB0_MAGIC,			IP1SR7_11_8)
243 #define GPSR7_9		F_(AVB0_TXCREFCLK,		IP1SR7_7_4)
244 #define GPSR7_8		F_(AVB0_RD3,			IP1SR7_3_0)
245 #define GPSR7_7		F_(AVB0_TD1,			IP0SR7_31_28)
246 #define GPSR7_6		F_(AVB0_TD2,			IP0SR7_27_24)
247 #define GPSR7_5		F_(AVB0_PHY_INT,		IP0SR7_23_20)
248 #define GPSR7_4		F_(AVB0_LINK,			IP0SR7_19_16)
249 #define GPSR7_3		F_(AVB0_TD3,			IP0SR7_15_12)
250 #define GPSR7_2		F_(AVB0_AVTP_MATCH,		IP0SR7_11_8)
251 #define GPSR7_1		F_(AVB0_AVTP_CAPTURE,		IP0SR7_7_4)
252 #define GPSR7_0		F_(AVB0_AVTP_PPS,		IP0SR7_3_0)
253 
254 /* GPSR8 */
255 #define GPSR8_13	F_(GP8_13,			IP1SR8_23_20)
256 #define GPSR8_12	F_(GP8_12,			IP1SR8_19_16)
257 #define GPSR8_11	F_(SDA5,			IP1SR8_15_12)
258 #define GPSR8_10	F_(SCL5,			IP1SR8_11_8)
259 #define GPSR8_9		F_(SDA4,			IP1SR8_7_4)
260 #define GPSR8_8		F_(SCL4,			IP1SR8_3_0)
261 #define GPSR8_7		F_(SDA3,			IP0SR8_31_28)
262 #define GPSR8_6		F_(SCL3,			IP0SR8_27_24)
263 #define GPSR8_5		F_(SDA2,			IP0SR8_23_20)
264 #define GPSR8_4		F_(SCL2,			IP0SR8_19_16)
265 #define GPSR8_3		F_(SDA1,			IP0SR8_15_12)
266 #define GPSR8_2		F_(SCL1,			IP0SR8_11_8)
267 #define GPSR8_1		F_(SDA0,			IP0SR8_7_4)
268 #define GPSR8_0		F_(SCL0,			IP0SR8_3_0)
269 
270 /* SR0 */
271 /* IP0SR0 */		/* 0 */			/* 1 */			/* 2 */		/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
272 #define IP0SR0_3_0	F_(0, 0)		FM(ERROROUTC_B)		FM(TCLK2_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP0SR0_7_4	F_(0, 0)		FM(MSIOF3_SS1)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274 #define IP0SR0_11_8	F_(0, 0)		FM(MSIOF3_SS2)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275 #define IP0SR0_15_12	FM(IRQ3)		FM(MSIOF3_SCK)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276 #define IP0SR0_19_16	FM(IRQ2)		FM(MSIOF3_TXD)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 #define IP0SR0_23_20	FM(IRQ1)		FM(MSIOF3_RXD)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP0SR0_27_24	FM(IRQ0)		FM(MSIOF3_SYNC)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP0SR0_31_28	FM(MSIOF5_SS2)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 
281 /* IP1SR0 */		/* 0 */			/* 1 */			/* 2 */		/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
282 #define IP1SR0_3_0	FM(MSIOF5_SS1)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP1SR0_7_4	FM(MSIOF5_SYNC)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP1SR0_11_8	FM(MSIOF5_TXD)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP1SR0_15_12	FM(MSIOF5_SCK)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP1SR0_19_16	FM(MSIOF5_RXD)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP1SR0_23_20	FM(MSIOF2_SS2)		FM(TCLK1)		FM(IRQ2_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP1SR0_27_24	FM(MSIOF2_SS1)		FM(HTX1)		FM(TX1)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP1SR0_31_28	FM(MSIOF2_SYNC)		FM(HRX1)		FM(RX1)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 
291 /* IP2SR0 */		/* 0 */			/* 1 */			/* 2 */		/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
292 #define IP2SR0_3_0	FM(MSIOF2_TXD)		FM(HCTS1_N)		FM(CTS1_N)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP2SR0_7_4	FM(MSIOF2_SCK)		FM(HRTS1_N)		FM(RTS1_N)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP2SR0_11_8	FM(MSIOF2_RXD)		FM(HSCK1)		FM(SCK1)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 
296 /* SR1 */
297 /* IP0SR1 */		/* 0 */			/* 1 */			/* 2 */		/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
298 #define IP0SR1_3_0	FM(MSIOF1_SS2)		FM(HTX3_A)		FM(TX3)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP0SR1_7_4	FM(MSIOF1_SS1)		FM(HCTS3_N_A)		FM(RX3)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP0SR1_11_8	FM(MSIOF1_SYNC)		FM(HRTS3_N_A)		FM(RTS3_N)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP0SR1_15_12	FM(MSIOF1_SCK)		FM(HSCK3_A)		FM(CTS3_N)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP0SR1_19_16	FM(MSIOF1_TXD)		FM(HRX3_A)		FM(SCK3)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP0SR1_23_20	FM(MSIOF1_RXD)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP0SR1_27_24	FM(MSIOF0_SS2)		FM(HTX1_X)		FM(TX1_X)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP0SR1_31_28	FM(MSIOF0_SS1)		FM(HRX1_X)		FM(RX1_X)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 
307 /* IP1SR1 */		/* 0 */			/* 1 */			/* 2 */		/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
308 #define IP1SR1_3_0	FM(MSIOF0_SYNC)		FM(HCTS1_N_X)		FM(CTS1_N_X)	FM(CANFD5_TX_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP1SR1_7_4	FM(MSIOF0_TXD)		FM(HRTS1_N_X)		FM(RTS1_N_X)	FM(CANFD5_RX_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP1SR1_11_8	FM(MSIOF0_SCK)		FM(HSCK1_X)		FM(SCK1_X)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP1SR1_15_12	FM(MSIOF0_RXD)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 #define IP1SR1_19_16	FM(HTX0)		FM(TX0)			F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP1SR1_23_20	FM(HCTS0_N)		FM(CTS0_N)		FM(PWM8_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 #define IP1SR1_27_24	FM(HRTS0_N)		FM(RTS0_N)		FM(PWM9_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP1SR1_31_28	FM(HSCK0)		FM(SCK0)		FM(PWM0_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316 
317 /* IP2SR1 */		/* 0 */			/* 1 */			/* 2 */		/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
318 #define IP2SR1_3_0	FM(HRX0)		FM(RX0)			F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319 #define IP2SR1_7_4	FM(SCIF_CLK)		FM(IRQ4_A)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP2SR1_11_8	FM(SSI_SCK)		FM(TCLK3)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP2SR1_15_12	FM(SSI_WS)		FM(TCLK4)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP2SR1_19_16	FM(SSI_SD)		FM(IRQ0_A)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP2SR1_23_20	FM(AUDIO_CLKOUT)	FM(IRQ1_A)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP2SR1_27_24	FM(AUDIO_CLKIN)		FM(PWM3_A)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP2SR1_31_28	F_(0, 0)		FM(TCLK2)		FM(MSIOF4_SS1)	FM(IRQ3_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 
327 /* IP3SR1 */		/* 0 */			/* 1 */			/* 2 */		/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
328 #define IP3SR1_3_0	FM(HRX3)		FM(SCK3_A)		FM(MSIOF4_SS2)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP3SR1_7_4	FM(HSCK3)		FM(CTS3_N_A)		FM(MSIOF4_SCK)	FM(TPU0TO0_A)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP3SR1_11_8	FM(HRTS3_N)		FM(RTS3_N_A)		FM(MSIOF4_TXD)	FM(TPU0TO1_A)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP3SR1_15_12	FM(HCTS3_N)		FM(RX3_A)		FM(MSIOF4_RXD)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 #define IP3SR1_19_16	FM(HTX3)		FM(TX3_A)		FM(MSIOF4_SYNC)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333 
334 /* SR2 */
335 /* IP0SR2 */		/* 0 */			/* 1 */			/* 2 */		/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
336 #define IP0SR2_3_0	FM(FXR_TXDA)		FM(CANFD1_TX)		FM(TPU0TO2_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337 #define IP0SR2_7_4	FM(FXR_TXENA_N)		FM(CANFD1_RX)		FM(TPU0TO3_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 #define IP0SR2_11_8	FM(RXDA_EXTFXR)		FM(CANFD5_TX)		FM(IRQ5)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339 #define IP0SR2_15_12	FM(CLK_EXTFXR)		FM(CANFD5_RX)		FM(IRQ4_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340 #define IP0SR2_19_16	FM(RXDB_EXTFXR)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341 #define IP0SR2_23_20	FM(FXR_TXENB_N)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342 #define IP0SR2_27_24	FM(FXR_TXDB)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 #define IP0SR2_31_28	FM(TPU0TO1)		FM(CANFD6_TX)		F_(0, 0)	FM(TCLK2_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 
345 /* IP1SR2 */		/* 0 */			/* 1 */			/* 2 */		/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
346 #define IP1SR2_3_0	FM(TPU0TO0)		FM(CANFD6_RX)		F_(0, 0)	FM(TCLK1_A)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP1SR2_7_4	FM(CAN_CLK)		FM(FXR_TXENA_N_X)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 #define IP1SR2_11_8	FM(CANFD0_TX)		FM(FXR_TXENB_N_X)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349 #define IP1SR2_15_12	FM(CANFD0_RX)		FM(STPWT_EXTFXR)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350 #define IP1SR2_19_16	FM(CANFD2_TX)		FM(TPU0TO2)		F_(0, 0)	FM(TCLK3_A)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351 #define IP1SR2_23_20	FM(CANFD2_RX)		FM(TPU0TO3)		FM(PWM1_B)	FM(TCLK4_A)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352 #define IP1SR2_27_24	FM(CANFD3_TX)		F_(0, 0)		FM(PWM2_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353 #define IP1SR2_31_28	FM(CANFD3_RX)		F_(0, 0)		FM(PWM3_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354 
355 /* IP2SR2 */		/* 0 */			/* 1 */			/* 2 */		/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
356 #define IP2SR2_3_0	FM(CANFD4_TX)		F_(0, 0)		FM(PWM4)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357 #define IP2SR2_7_4	FM(CANFD4_RX)		F_(0, 0)		FM(PWM5)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358 #define IP2SR2_11_8	FM(CANFD7_TX)		F_(0, 0)		FM(PWM6)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359 #define IP2SR2_15_12	FM(CANFD7_RX)		F_(0, 0)		FM(PWM7)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360 
361 /* SR3 */
362 /* IP0SR3 */		/* 0 */			/* 1 */			/* 2 */		/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
363 #define IP0SR3_3_0	FM(MMC_SD_D1)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364 #define IP0SR3_7_4	FM(MMC_SD_D0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
365 #define IP0SR3_11_8	FM(MMC_SD_D2)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
366 #define IP0SR3_15_12	FM(MMC_SD_CLK)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
367 #define IP0SR3_19_16	FM(MMC_DS)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
368 #define IP0SR3_23_20	FM(MMC_SD_D3)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
369 #define IP0SR3_27_24	FM(MMC_D5)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370 #define IP0SR3_31_28	FM(MMC_D4)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
371 
372 /* IP1SR3 */		/* 0 */			/* 1 */			/* 2 */		/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
373 #define IP1SR3_3_0	FM(MMC_D7)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
374 #define IP1SR3_7_4	FM(MMC_D6)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
375 #define IP1SR3_11_8	FM(MMC_SD_CMD)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
376 #define IP1SR3_15_12	FM(SD_CD)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
377 #define IP1SR3_19_16	FM(SD_WP)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
378 #define IP1SR3_23_20	FM(IPC_CLKIN)		FM(IPC_CLKEN_IN)	FM(PWM1_A)	FM(TCLK3_X)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
379 #define IP1SR3_27_24	FM(IPC_CLKOUT)		FM(IPC_CLKEN_OUT)	FM(ERROROUTC_A)	FM(TCLK4_X)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
380 #define IP1SR3_31_28	FM(QSPI0_SSL)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
381 
382 /* IP2SR3 */		/* 0 */			/* 1 */			/* 2 */		/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
383 #define IP2SR3_3_0	FM(QSPI0_IO3)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
384 #define IP2SR3_7_4	FM(QSPI0_IO2)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
385 #define IP2SR3_11_8	FM(QSPI0_MISO_IO1)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
386 #define IP2SR3_15_12	FM(QSPI0_MOSI_IO0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
387 #define IP2SR3_19_16	FM(QSPI0_SPCLK)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
388 #define IP2SR3_23_20	FM(QSPI1_MOSI_IO0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
389 #define IP2SR3_27_24	FM(QSPI1_SPCLK)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
390 #define IP2SR3_31_28	FM(QSPI1_MISO_IO1)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
391 
392 /* IP3SR3 */		/* 0 */			/* 1 */			/* 2 */		/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
393 #define IP3SR3_3_0	FM(QSPI1_IO2)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
394 #define IP3SR3_7_4	FM(QSPI1_SSL)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
395 #define IP3SR3_11_8	FM(QSPI1_IO3)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
396 #define IP3SR3_15_12	FM(RPC_RESET_N)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
397 #define IP3SR3_19_16	FM(RPC_WP_N)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
398 #define IP3SR3_23_20	FM(RPC_INT_N)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
399 
400 /* SR6 */
401 /* IP0SR6 */		/* 0 */			/* 1 */			/* 2 */		/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
402 #define IP0SR6_3_0	FM(AVB1_MDIO)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
403 #define IP0SR6_7_4	FM(AVB1_MAGIC)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
404 #define IP0SR6_11_8	FM(AVB1_MDC)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
405 #define IP0SR6_15_12	FM(AVB1_PHY_INT)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
406 #define IP0SR6_19_16	FM(AVB1_LINK)		FM(AVB1_MII_TX_ER)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
407 #define IP0SR6_23_20	FM(AVB1_AVTP_MATCH)	FM(AVB1_MII_RX_ER)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
408 #define IP0SR6_27_24	FM(AVB1_TXC)		FM(AVB1_MII_TXC)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
409 #define IP0SR6_31_28	FM(AVB1_TX_CTL)		FM(AVB1_MII_TX_EN)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
410 
411 /* IP1SR6 */		/* 0 */			/* 1 */			/* 2 */		/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
412 #define IP1SR6_3_0	FM(AVB1_RXC)		FM(AVB1_MII_RXC)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
413 #define IP1SR6_7_4	FM(AVB1_RX_CTL)		FM(AVB1_MII_RX_DV)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
414 #define IP1SR6_11_8	FM(AVB1_AVTP_PPS)	FM(AVB1_MII_COL)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
415 #define IP1SR6_15_12	FM(AVB1_AVTP_CAPTURE)	FM(AVB1_MII_CRS)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
416 #define IP1SR6_19_16	FM(AVB1_TD1)		FM(AVB1_MII_TD1)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
417 #define IP1SR6_23_20	FM(AVB1_TD0)		FM(AVB1_MII_TD0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
418 #define IP1SR6_27_24	FM(AVB1_RD1)		FM(AVB1_MII_RD1)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
419 #define IP1SR6_31_28	FM(AVB1_RD0)		FM(AVB1_MII_RD0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
420 
421 /* IP2SR6 */		/* 0 */			/* 1 */			/* 2 */		/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
422 #define IP2SR6_3_0	FM(AVB1_TD2)		FM(AVB1_MII_TD2)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
423 #define IP2SR6_7_4	FM(AVB1_RD2)		FM(AVB1_MII_RD2)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
424 #define IP2SR6_11_8	FM(AVB1_TD3)		FM(AVB1_MII_TD3)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
425 #define IP2SR6_15_12	FM(AVB1_RD3)		FM(AVB1_MII_RD3)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
426 #define IP2SR6_19_16	FM(AVB1_TXCREFCLK)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
427 
428 /* SR7 */
429 /* IP0SR7 */		/* 0 */			/* 1 */			/* 2 */		/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
430 #define IP0SR7_3_0	FM(AVB0_AVTP_PPS)	FM(AVB0_MII_COL)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
431 #define IP0SR7_7_4	FM(AVB0_AVTP_CAPTURE)	FM(AVB0_MII_CRS)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
432 #define IP0SR7_11_8	FM(AVB0_AVTP_MATCH)	FM(AVB0_MII_RX_ER)	FM(CC5_OSCOUT)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
433 #define IP0SR7_15_12	FM(AVB0_TD3)		FM(AVB0_MII_TD3)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
434 #define IP0SR7_19_16	FM(AVB0_LINK)		FM(AVB0_MII_TX_ER)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
435 #define IP0SR7_23_20	FM(AVB0_PHY_INT)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
436 #define IP0SR7_27_24	FM(AVB0_TD2)		FM(AVB0_MII_TD2)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
437 #define IP0SR7_31_28	FM(AVB0_TD1)		FM(AVB0_MII_TD1)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
438 
439 /* IP1SR7 */		/* 0 */			/* 1 */			/* 2 */		/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
440 #define IP1SR7_3_0	FM(AVB0_RD3)		FM(AVB0_MII_RD3)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
441 #define IP1SR7_7_4	FM(AVB0_TXCREFCLK)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
442 #define IP1SR7_11_8	FM(AVB0_MAGIC)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
443 #define IP1SR7_15_12	FM(AVB0_TD0)		FM(AVB0_MII_TD0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
444 #define IP1SR7_19_16	FM(AVB0_RD2)		FM(AVB0_MII_RD2)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
445 #define IP1SR7_23_20	FM(AVB0_MDC)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
446 #define IP1SR7_27_24	FM(AVB0_MDIO)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
447 #define IP1SR7_31_28	FM(AVB0_TXC)		FM(AVB0_MII_TXC)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
448 
449 /* IP2SR7 */		/* 0 */			/* 1 */			/* 2 */		/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
450 #define IP2SR7_3_0	FM(AVB0_TX_CTL)		FM(AVB0_MII_TX_EN)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
451 #define IP2SR7_7_4	FM(AVB0_RD1)		FM(AVB0_MII_RD1)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
452 #define IP2SR7_11_8	FM(AVB0_RD0)		FM(AVB0_MII_RD0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
453 #define IP2SR7_15_12	FM(AVB0_RXC)		FM(AVB0_MII_RXC)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
454 #define IP2SR7_19_16	FM(AVB0_RX_CTL)		FM(AVB0_MII_RX_DV)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
455 
456 /* SR8 */
457 /* IP0SR8 */		/* 0 */			/* 1 */			/* 2 */		/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
458 #define IP0SR8_3_0	FM(SCL0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
459 #define IP0SR8_7_4	FM(SDA0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
460 #define IP0SR8_11_8	FM(SCL1)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
461 #define IP0SR8_15_12	FM(SDA1)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
462 #define IP0SR8_19_16	FM(SCL2)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
463 #define IP0SR8_23_20	FM(SDA2)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
464 #define IP0SR8_27_24	FM(SCL3)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
465 #define IP0SR8_31_28	FM(SDA3)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
466 
467 /* IP1SR8 */		/* 0 */			/* 1 */			/* 2 */		/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
468 #define IP1SR8_3_0	FM(SCL4)		FM(HRX2)		FM(SCK4)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
469 #define IP1SR8_7_4	FM(SDA4)		FM(HTX2)		FM(CTS4_N)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
470 #define IP1SR8_11_8	FM(SCL5)		FM(HRTS2_N)		FM(RTS4_N)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
471 #define IP1SR8_15_12	FM(SDA5)		FM(SCIF_CLK2)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
472 #define IP1SR8_19_16	F_(0, 0)		FM(HCTS2_N)		FM(TX4)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
473 #define IP1SR8_23_20	F_(0, 0)		FM(HSCK2)		FM(RX4)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
474 
475 #define PINMUX_GPSR	\
476 						GPSR3_29											\
477 		GPSR1_28			GPSR3_28											\
478 		GPSR1_27			GPSR3_27											\
479 		GPSR1_26			GPSR3_26											\
480 		GPSR1_25			GPSR3_25											\
481 		GPSR1_24			GPSR3_24	GPSR4_24									\
482 		GPSR1_23			GPSR3_23	GPSR4_23									\
483 		GPSR1_22			GPSR3_22	GPSR4_22									\
484 		GPSR1_21			GPSR3_21	GPSR4_21									\
485 		GPSR1_20			GPSR3_20	GPSR4_20	GPSR5_20	GPSR6_20	GPSR7_20			\
486 		GPSR1_19	GPSR2_19	GPSR3_19	GPSR4_19	GPSR5_19	GPSR6_19	GPSR7_19			\
487 GPSR0_18	GPSR1_18	GPSR2_18	GPSR3_18	GPSR4_18	GPSR5_18	GPSR6_18	GPSR7_18			\
488 GPSR0_17	GPSR1_17	GPSR2_17	GPSR3_17	GPSR4_17	GPSR5_17	GPSR6_17	GPSR7_17			\
489 GPSR0_16	GPSR1_16	GPSR2_16	GPSR3_16	GPSR4_16	GPSR5_16	GPSR6_16	GPSR7_16			\
490 GPSR0_15	GPSR1_15	GPSR2_15	GPSR3_15	GPSR4_15	GPSR5_15	GPSR6_15	GPSR7_15			\
491 GPSR0_14	GPSR1_14	GPSR2_14	GPSR3_14	GPSR4_14	GPSR5_14	GPSR6_14	GPSR7_14			\
492 GPSR0_13	GPSR1_13	GPSR2_13	GPSR3_13	GPSR4_13	GPSR5_13	GPSR6_13	GPSR7_13	GPSR8_13	\
493 GPSR0_12	GPSR1_12	GPSR2_12	GPSR3_12	GPSR4_12	GPSR5_12	GPSR6_12	GPSR7_12	GPSR8_12	\
494 GPSR0_11	GPSR1_11	GPSR2_11	GPSR3_11	GPSR4_11	GPSR5_11	GPSR6_11	GPSR7_11	GPSR8_11	\
495 GPSR0_10	GPSR1_10	GPSR2_10	GPSR3_10	GPSR4_10	GPSR5_10	GPSR6_10	GPSR7_10	GPSR8_10	\
496 GPSR0_9		GPSR1_9		GPSR2_9		GPSR3_9		GPSR4_9		GPSR5_9		GPSR6_9		GPSR7_9		GPSR8_9		\
497 GPSR0_8		GPSR1_8		GPSR2_8		GPSR3_8		GPSR4_8		GPSR5_8		GPSR6_8		GPSR7_8		GPSR8_8		\
498 GPSR0_7		GPSR1_7		GPSR2_7		GPSR3_7		GPSR4_7		GPSR5_7		GPSR6_7		GPSR7_7		GPSR8_7		\
499 GPSR0_6		GPSR1_6		GPSR2_6		GPSR3_6		GPSR4_6		GPSR5_6		GPSR6_6		GPSR7_6		GPSR8_6		\
500 GPSR0_5		GPSR1_5		GPSR2_5		GPSR3_5		GPSR4_5		GPSR5_5		GPSR6_5		GPSR7_5		GPSR8_5		\
501 GPSR0_4		GPSR1_4		GPSR2_4		GPSR3_4		GPSR4_4		GPSR5_4		GPSR6_4		GPSR7_4		GPSR8_4		\
502 GPSR0_3		GPSR1_3		GPSR2_3		GPSR3_3		GPSR4_3		GPSR5_3		GPSR6_3		GPSR7_3		GPSR8_3		\
503 GPSR0_2		GPSR1_2		GPSR2_2		GPSR3_2		GPSR4_2		GPSR5_2		GPSR6_2		GPSR7_2		GPSR8_2		\
504 GPSR0_1		GPSR1_1		GPSR2_1		GPSR3_1		GPSR4_1		GPSR5_1		GPSR6_1		GPSR7_1		GPSR8_1		\
505 GPSR0_0		GPSR1_0		GPSR2_0		GPSR3_0		GPSR4_0		GPSR5_0		GPSR6_0		GPSR7_0		GPSR8_0
506 
507 #define PINMUX_IPSR	\
508 \
509 FM(IP0SR0_3_0)		IP0SR0_3_0	FM(IP1SR0_3_0)		IP1SR0_3_0	FM(IP2SR0_3_0)		IP2SR0_3_0	\
510 FM(IP0SR0_7_4)		IP0SR0_7_4	FM(IP1SR0_7_4)		IP1SR0_7_4	FM(IP2SR0_7_4)		IP2SR0_7_4	\
511 FM(IP0SR0_11_8)		IP0SR0_11_8	FM(IP1SR0_11_8)		IP1SR0_11_8	FM(IP2SR0_11_8)		IP2SR0_11_8	\
512 FM(IP0SR0_15_12)	IP0SR0_15_12	FM(IP1SR0_15_12)	IP1SR0_15_12	\
513 FM(IP0SR0_19_16)	IP0SR0_19_16	FM(IP1SR0_19_16)	IP1SR0_19_16	\
514 FM(IP0SR0_23_20)	IP0SR0_23_20	FM(IP1SR0_23_20)	IP1SR0_23_20	\
515 FM(IP0SR0_27_24)	IP0SR0_27_24	FM(IP1SR0_27_24)	IP1SR0_27_24	\
516 FM(IP0SR0_31_28)	IP0SR0_31_28	FM(IP1SR0_31_28)	IP1SR0_31_28	\
517 \
518 FM(IP0SR1_3_0)		IP0SR1_3_0	FM(IP1SR1_3_0)		IP1SR1_3_0	FM(IP2SR1_3_0)		IP2SR1_3_0	FM(IP3SR1_3_0)		IP3SR1_3_0	\
519 FM(IP0SR1_7_4)		IP0SR1_7_4	FM(IP1SR1_7_4)		IP1SR1_7_4	FM(IP2SR1_7_4)		IP2SR1_7_4	FM(IP3SR1_7_4)		IP3SR1_7_4	\
520 FM(IP0SR1_11_8)		IP0SR1_11_8	FM(IP1SR1_11_8)		IP1SR1_11_8	FM(IP2SR1_11_8)		IP2SR1_11_8	FM(IP3SR1_11_8)		IP3SR1_11_8	\
521 FM(IP0SR1_15_12)	IP0SR1_15_12	FM(IP1SR1_15_12)	IP1SR1_15_12	FM(IP2SR1_15_12)	IP2SR1_15_12	FM(IP3SR1_15_12)	IP3SR1_15_12	\
522 FM(IP0SR1_19_16)	IP0SR1_19_16	FM(IP1SR1_19_16)	IP1SR1_19_16	FM(IP2SR1_19_16)	IP2SR1_19_16	FM(IP3SR1_19_16)	IP3SR1_19_16	\
523 FM(IP0SR1_23_20)	IP0SR1_23_20	FM(IP1SR1_23_20)	IP1SR1_23_20	FM(IP2SR1_23_20)	IP2SR1_23_20	\
524 FM(IP0SR1_27_24)	IP0SR1_27_24	FM(IP1SR1_27_24)	IP1SR1_27_24	FM(IP2SR1_27_24)	IP2SR1_27_24	\
525 FM(IP0SR1_31_28)	IP0SR1_31_28	FM(IP1SR1_31_28)	IP1SR1_31_28	FM(IP2SR1_31_28)	IP2SR1_31_28	\
526 \
527 FM(IP0SR2_3_0)		IP0SR2_3_0	FM(IP1SR2_3_0)		IP1SR2_3_0	FM(IP2SR2_3_0)		IP2SR2_3_0	\
528 FM(IP0SR2_7_4)		IP0SR2_7_4	FM(IP1SR2_7_4)		IP1SR2_7_4	FM(IP2SR2_7_4)		IP2SR2_7_4	\
529 FM(IP0SR2_11_8)		IP0SR2_11_8	FM(IP1SR2_11_8)		IP1SR2_11_8	FM(IP2SR2_11_8)		IP2SR2_11_8	\
530 FM(IP0SR2_15_12)	IP0SR2_15_12	FM(IP1SR2_15_12)	IP1SR2_15_12	FM(IP2SR2_15_12)	IP2SR2_15_12	\
531 FM(IP0SR2_19_16)	IP0SR2_19_16	FM(IP1SR2_19_16)	IP1SR2_19_16	\
532 FM(IP0SR2_23_20)	IP0SR2_23_20	FM(IP1SR2_23_20)	IP1SR2_23_20	\
533 FM(IP0SR2_27_24)	IP0SR2_27_24	FM(IP1SR2_27_24)	IP1SR2_27_24	\
534 FM(IP0SR2_31_28)	IP0SR2_31_28	FM(IP1SR2_31_28)	IP1SR2_31_28	\
535 \
536 FM(IP0SR3_3_0)		IP0SR3_3_0	FM(IP1SR3_3_0)		IP1SR3_3_0	FM(IP2SR3_3_0)		IP2SR3_3_0	FM(IP3SR3_3_0)		IP3SR3_3_0	\
537 FM(IP0SR3_7_4)		IP0SR3_7_4	FM(IP1SR3_7_4)		IP1SR3_7_4	FM(IP2SR3_7_4)		IP2SR3_7_4	FM(IP3SR3_7_4)		IP3SR3_7_4	\
538 FM(IP0SR3_11_8)		IP0SR3_11_8	FM(IP1SR3_11_8)		IP1SR3_11_8	FM(IP2SR3_11_8)		IP2SR3_11_8	FM(IP3SR3_11_8)		IP3SR3_11_8	\
539 FM(IP0SR3_15_12)	IP0SR3_15_12	FM(IP1SR3_15_12)	IP1SR3_15_12	FM(IP2SR3_15_12)	IP2SR3_15_12	FM(IP3SR3_15_12)	IP3SR3_15_12	\
540 FM(IP0SR3_19_16)	IP0SR3_19_16	FM(IP1SR3_19_16)	IP1SR3_19_16	FM(IP2SR3_19_16)	IP2SR3_19_16	FM(IP3SR3_19_16)	IP3SR3_19_16	\
541 FM(IP0SR3_23_20)	IP0SR3_23_20	FM(IP1SR3_23_20)	IP1SR3_23_20	FM(IP2SR3_23_20)	IP2SR3_23_20	FM(IP3SR3_23_20)	IP3SR3_23_20	\
542 FM(IP0SR3_27_24)	IP0SR3_27_24	FM(IP1SR3_27_24)	IP1SR3_27_24	FM(IP2SR3_27_24)	IP2SR3_27_24						\
543 FM(IP0SR3_31_28)	IP0SR3_31_28	FM(IP1SR3_31_28)	IP1SR3_31_28	FM(IP2SR3_31_28)	IP2SR3_31_28						\
544 \
545 FM(IP0SR6_3_0)		IP0SR6_3_0	FM(IP1SR6_3_0)		IP1SR6_3_0	FM(IP2SR6_3_0)		IP2SR6_3_0	\
546 FM(IP0SR6_7_4)		IP0SR6_7_4	FM(IP1SR6_7_4)		IP1SR6_7_4	FM(IP2SR6_7_4)		IP2SR6_7_4	\
547 FM(IP0SR6_11_8)		IP0SR6_11_8	FM(IP1SR6_11_8)		IP1SR6_11_8	FM(IP2SR6_11_8)		IP2SR6_11_8	\
548 FM(IP0SR6_15_12)	IP0SR6_15_12	FM(IP1SR6_15_12)	IP1SR6_15_12	FM(IP2SR6_15_12)	IP2SR6_15_12	\
549 FM(IP0SR6_19_16)	IP0SR6_19_16	FM(IP1SR6_19_16)	IP1SR6_19_16	FM(IP2SR6_19_16)	IP2SR6_19_16	\
550 FM(IP0SR6_23_20)	IP0SR6_23_20	FM(IP1SR6_23_20)	IP1SR6_23_20	\
551 FM(IP0SR6_27_24)	IP0SR6_27_24	FM(IP1SR6_27_24)	IP1SR6_27_24	\
552 FM(IP0SR6_31_28)	IP0SR6_31_28	FM(IP1SR6_31_28)	IP1SR6_31_28	\
553 \
554 FM(IP0SR7_3_0)		IP0SR7_3_0	FM(IP1SR7_3_0)		IP1SR7_3_0	FM(IP2SR7_3_0)		IP2SR7_3_0	\
555 FM(IP0SR7_7_4)		IP0SR7_7_4	FM(IP1SR7_7_4)		IP1SR7_7_4	FM(IP2SR7_7_4)		IP2SR7_7_4	\
556 FM(IP0SR7_11_8)		IP0SR7_11_8	FM(IP1SR7_11_8)		IP1SR7_11_8	FM(IP2SR7_11_8)		IP2SR7_11_8	\
557 FM(IP0SR7_15_12)	IP0SR7_15_12	FM(IP1SR7_15_12)	IP1SR7_15_12	FM(IP2SR7_15_12)	IP2SR7_15_12	\
558 FM(IP0SR7_19_16)	IP0SR7_19_16	FM(IP1SR7_19_16)	IP1SR7_19_16	FM(IP2SR7_19_16)	IP2SR7_19_16	\
559 FM(IP0SR7_23_20)	IP0SR7_23_20	FM(IP1SR7_23_20)	IP1SR7_23_20	\
560 FM(IP0SR7_27_24)	IP0SR7_27_24	FM(IP1SR7_27_24)	IP1SR7_27_24	\
561 FM(IP0SR7_31_28)	IP0SR7_31_28	FM(IP1SR7_31_28)	IP1SR7_31_28	\
562 \
563 FM(IP0SR8_3_0)		IP0SR8_3_0	FM(IP1SR8_3_0)		IP1SR8_3_0	\
564 FM(IP0SR8_7_4)		IP0SR8_7_4	FM(IP1SR8_7_4)		IP1SR8_7_4	\
565 FM(IP0SR8_11_8)		IP0SR8_11_8	FM(IP1SR8_11_8)		IP1SR8_11_8	\
566 FM(IP0SR8_15_12)	IP0SR8_15_12	FM(IP1SR8_15_12)	IP1SR8_15_12	\
567 FM(IP0SR8_19_16)	IP0SR8_19_16	FM(IP1SR8_19_16)	IP1SR8_19_16	\
568 FM(IP0SR8_23_20)	IP0SR8_23_20	FM(IP1SR8_23_20)	IP1SR8_23_20	\
569 FM(IP0SR8_27_24)	IP0SR8_27_24	\
570 FM(IP0SR8_31_28)	IP0SR8_31_28
571 
572 /* MOD_SEL4 */			/* 0 */				/* 1 */
573 #define MOD_SEL4_19		FM(SEL_TSN0_TD2_0)		FM(SEL_TSN0_TD2_1)
574 #define MOD_SEL4_18		FM(SEL_TSN0_TD3_0)		FM(SEL_TSN0_TD3_1)
575 #define MOD_SEL4_15		FM(SEL_TSN0_TD0_0)		FM(SEL_TSN0_TD0_1)
576 #define MOD_SEL4_14		FM(SEL_TSN0_TD1_0)		FM(SEL_TSN0_TD1_1)
577 #define MOD_SEL4_12		FM(SEL_TSN0_TXC_0)		FM(SEL_TSN0_TXC_1)
578 #define MOD_SEL4_9		FM(SEL_TSN0_TX_CTL_0)		FM(SEL_TSN0_TX_CTL_1)
579 #define MOD_SEL4_8		FM(SEL_TSN0_AVTP_PPS0_0)	FM(SEL_TSN0_AVTP_PPS0_1)
580 #define MOD_SEL4_5		FM(SEL_TSN0_AVTP_MATCH_0)	FM(SEL_TSN0_AVTP_MATCH_1)
581 #define MOD_SEL4_2		FM(SEL_TSN0_AVTP_PPS1_0)	FM(SEL_TSN0_AVTP_PPS1_1)
582 #define MOD_SEL4_1		FM(SEL_TSN0_MDC_0)		FM(SEL_TSN0_MDC_1)
583 
584 /* MOD_SEL5 */			/* 0 */				/* 1 */
585 #define MOD_SEL5_19		FM(SEL_AVB2_TX_CTL_0)		FM(SEL_AVB2_TX_CTL_1)
586 #define MOD_SEL5_16		FM(SEL_AVB2_TXC_0)		FM(SEL_AVB2_TXC_1)
587 #define MOD_SEL5_15		FM(SEL_AVB2_TD0_0)		FM(SEL_AVB2_TD0_1)
588 #define MOD_SEL5_12		FM(SEL_AVB2_TD1_0)		FM(SEL_AVB2_TD1_1)
589 #define MOD_SEL5_11		FM(SEL_AVB2_TD2_0)		FM(SEL_AVB2_TD2_1)
590 #define MOD_SEL5_8		FM(SEL_AVB2_TD3_0)		FM(SEL_AVB2_TD3_1)
591 #define MOD_SEL5_6		FM(SEL_AVB2_MDC_0)		FM(SEL_AVB2_MDC_1)
592 #define MOD_SEL5_5		FM(SEL_AVB2_MAGIC_0)		FM(SEL_AVB2_MAGIC_1)
593 #define MOD_SEL5_2		FM(SEL_AVB2_AVTP_MATCH_0)	FM(SEL_AVB2_AVTP_MATCH_1)
594 #define MOD_SEL5_0		FM(SEL_AVB2_AVTP_PPS_0)		FM(SEL_AVB2_AVTP_PPS_1)
595 
596 /* MOD_SEL6 */			/* 0 */				/* 1 */
597 #define MOD_SEL6_18		FM(SEL_AVB1_TD3_0)		FM(SEL_AVB1_TD3_1)
598 #define MOD_SEL6_16		FM(SEL_AVB1_TD2_0)		FM(SEL_AVB1_TD2_1)
599 #define MOD_SEL6_13		FM(SEL_AVB1_TD0_0)		FM(SEL_AVB1_TD0_1)
600 #define MOD_SEL6_12		FM(SEL_AVB1_TD1_0)		FM(SEL_AVB1_TD1_1)
601 #define MOD_SEL6_10		FM(SEL_AVB1_AVTP_PPS_0)		FM(SEL_AVB1_AVTP_PPS_1)
602 #define MOD_SEL6_7		FM(SEL_AVB1_TX_CTL_0)		FM(SEL_AVB1_TX_CTL_1)
603 #define MOD_SEL6_6		FM(SEL_AVB1_TXC_0)		FM(SEL_AVB1_TXC_1)
604 #define MOD_SEL6_5		FM(SEL_AVB1_AVTP_MATCH_0)	FM(SEL_AVB1_AVTP_MATCH_1)
605 #define MOD_SEL6_2		FM(SEL_AVB1_MDC_0)		FM(SEL_AVB1_MDC_1)
606 #define MOD_SEL6_1		FM(SEL_AVB1_MAGIC_0)		FM(SEL_AVB1_MAGIC_1)
607 
608 /* MOD_SEL7 */			/* 0 */				/* 1 */
609 #define MOD_SEL7_16		FM(SEL_AVB0_TX_CTL_0)		FM(SEL_AVB0_TX_CTL_1)
610 #define MOD_SEL7_15		FM(SEL_AVB0_TXC_0)		FM(SEL_AVB0_TXC_1)
611 #define MOD_SEL7_13		FM(SEL_AVB0_MDC_0)		FM(SEL_AVB0_MDC_1)
612 #define MOD_SEL7_11		FM(SEL_AVB0_TD0_0)		FM(SEL_AVB0_TD0_1)
613 #define MOD_SEL7_10		FM(SEL_AVB0_MAGIC_0)		FM(SEL_AVB0_MAGIC_1)
614 #define MOD_SEL7_7		FM(SEL_AVB0_TD1_0)		FM(SEL_AVB0_TD1_1)
615 #define MOD_SEL7_6		FM(SEL_AVB0_TD2_0)		FM(SEL_AVB0_TD2_1)
616 #define MOD_SEL7_3		FM(SEL_AVB0_TD3_0)		FM(SEL_AVB0_TD3_1)
617 #define MOD_SEL7_2		FM(SEL_AVB0_AVTP_MATCH_0)	FM(SEL_AVB0_AVTP_MATCH_1)
618 #define MOD_SEL7_0		FM(SEL_AVB0_AVTP_PPS_0)		FM(SEL_AVB0_AVTP_PPS_1)
619 
620 /* MOD_SEL8 */			/* 0 */				/* 1 */
621 #define MOD_SEL8_11		FM(SEL_SDA5_0)			FM(SEL_SDA5_1)
622 #define MOD_SEL8_10		FM(SEL_SCL5_0)			FM(SEL_SCL5_1)
623 #define MOD_SEL8_9		FM(SEL_SDA4_0)			FM(SEL_SDA4_1)
624 #define MOD_SEL8_8		FM(SEL_SCL4_0)			FM(SEL_SCL4_1)
625 #define MOD_SEL8_7		FM(SEL_SDA3_0)			FM(SEL_SDA3_1)
626 #define MOD_SEL8_6		FM(SEL_SCL3_0)			FM(SEL_SCL3_1)
627 #define MOD_SEL8_5		FM(SEL_SDA2_0)			FM(SEL_SDA2_1)
628 #define MOD_SEL8_4		FM(SEL_SCL2_0)			FM(SEL_SCL2_1)
629 #define MOD_SEL8_3		FM(SEL_SDA1_0)			FM(SEL_SDA1_1)
630 #define MOD_SEL8_2		FM(SEL_SCL1_0)			FM(SEL_SCL1_1)
631 #define MOD_SEL8_1		FM(SEL_SDA0_0)			FM(SEL_SDA0_1)
632 #define MOD_SEL8_0		FM(SEL_SCL0_0)			FM(SEL_SCL0_1)
633 
634 #define PINMUX_MOD_SELS \
635 \
636 MOD_SEL4_19		MOD_SEL5_19										\
637 MOD_SEL4_18					MOD_SEL6_18							\
638 														\
639 			MOD_SEL5_16		MOD_SEL6_16		MOD_SEL7_16				\
640 MOD_SEL4_15		MOD_SEL5_15					MOD_SEL7_15				\
641 MOD_SEL4_14													\
642 						MOD_SEL6_13		MOD_SEL7_13				\
643 MOD_SEL4_12		MOD_SEL5_12		MOD_SEL6_12							\
644 			MOD_SEL5_11					MOD_SEL7_11		MOD_SEL8_11	\
645 						MOD_SEL6_10		MOD_SEL7_10		MOD_SEL8_10	\
646 MOD_SEL4_9											MOD_SEL8_9	\
647 MOD_SEL4_8		MOD_SEL5_8								MOD_SEL8_8	\
648 						MOD_SEL6_7		MOD_SEL7_7		MOD_SEL8_7	\
649 			MOD_SEL5_6		MOD_SEL6_6		MOD_SEL7_6		MOD_SEL8_6	\
650 MOD_SEL4_5		MOD_SEL5_5		MOD_SEL6_5					MOD_SEL8_5	\
651 												MOD_SEL8_4	\
652 									MOD_SEL7_3		MOD_SEL8_3	\
653 MOD_SEL4_2		MOD_SEL5_2		MOD_SEL6_2		MOD_SEL7_2		MOD_SEL8_2	\
654 MOD_SEL4_1					MOD_SEL6_1					MOD_SEL8_1	\
655 			MOD_SEL5_0					MOD_SEL7_0		MOD_SEL8_0
656 
657 enum {
658 	PINMUX_RESERVED = 0,
659 
660 	PINMUX_DATA_BEGIN,
661 	GP_ALL(DATA),
662 	PINMUX_DATA_END,
663 
664 #define F_(x, y)
665 #define FM(x)   FN_##x,
666 	PINMUX_FUNCTION_BEGIN,
667 	GP_ALL(FN),
668 	PINMUX_GPSR
669 	PINMUX_IPSR
670 	PINMUX_MOD_SELS
671 	PINMUX_FUNCTION_END,
672 #undef F_
673 #undef FM
674 
675 #define F_(x, y)
676 #define FM(x)	x##_MARK,
677 	PINMUX_MARK_BEGIN,
678 	PINMUX_GPSR
679 	PINMUX_IPSR
680 	PINMUX_MOD_SELS
681 	PINMUX_MARK_END,
682 #undef F_
683 #undef FM
684 };
685 
686 static const u16 pinmux_data[] = {
687 	PINMUX_DATA_GP_ALL(),
688 
689 	PINMUX_SINGLE(AVS1),
690 	PINMUX_SINGLE(AVS0),
691 	PINMUX_SINGLE(PCIE1_CLKREQ_N),
692 	PINMUX_SINGLE(PCIE0_CLKREQ_N),
693 
694 	/* TSN0 without MODSEL4 */
695 	PINMUX_SINGLE(TSN0_TXCREFCLK),
696 	PINMUX_SINGLE(TSN0_RD2),
697 	PINMUX_SINGLE(TSN0_RD3),
698 	PINMUX_SINGLE(TSN0_RD1),
699 	PINMUX_SINGLE(TSN0_RXC),
700 	PINMUX_SINGLE(TSN0_RD0),
701 	PINMUX_SINGLE(TSN0_RX_CTL),
702 	PINMUX_SINGLE(TSN0_AVTP_CAPTURE),
703 	PINMUX_SINGLE(TSN0_LINK),
704 	PINMUX_SINGLE(TSN0_PHY_INT),
705 	PINMUX_SINGLE(TSN0_MDIO),
706 	/* TSN0 with MODSEL4 */
707 	PINMUX_IPSR_NOGM(0, TSN0_TD2,		SEL_TSN0_TD2_1),
708 	PINMUX_IPSR_NOGM(0, TSN0_TD3,		SEL_TSN0_TD3_1),
709 	PINMUX_IPSR_NOGM(0, TSN0_TD0,		SEL_TSN0_TD0_1),
710 	PINMUX_IPSR_NOGM(0, TSN0_TD1,		SEL_TSN0_TD1_1),
711 	PINMUX_IPSR_NOGM(0, TSN0_TXC,		SEL_TSN0_TXC_1),
712 	PINMUX_IPSR_NOGM(0, TSN0_TX_CTL,	SEL_TSN0_TX_CTL_1),
713 	PINMUX_IPSR_NOGM(0, TSN0_AVTP_PPS0,	SEL_TSN0_AVTP_PPS0_1),
714 	PINMUX_IPSR_NOGM(0, TSN0_AVTP_MATCH,	SEL_TSN0_AVTP_MATCH_1),
715 	PINMUX_IPSR_NOGM(0, TSN0_AVTP_PPS1,	SEL_TSN0_AVTP_PPS1_1),
716 	PINMUX_IPSR_NOGM(0, TSN0_MDC,		SEL_TSN0_MDC_1),
717 
718 	/* TSN0 without MODSEL5 */
719 	PINMUX_SINGLE(AVB2_RX_CTL),
720 	PINMUX_SINGLE(AVB2_RXC),
721 	PINMUX_SINGLE(AVB2_RD0),
722 	PINMUX_SINGLE(AVB2_RD1),
723 	PINMUX_SINGLE(AVB2_RD2),
724 	PINMUX_SINGLE(AVB2_MDIO),
725 	PINMUX_SINGLE(AVB2_RD3),
726 	PINMUX_SINGLE(AVB2_TXCREFCLK),
727 	PINMUX_SINGLE(AVB2_PHY_INT),
728 	PINMUX_SINGLE(AVB2_LINK),
729 	PINMUX_SINGLE(AVB2_AVTP_CAPTURE),
730 	/* TSN0 with MODSEL5 */
731 	PINMUX_IPSR_NOGM(0, AVB2_TX_CTL,	SEL_AVB2_TX_CTL_1),
732 	PINMUX_IPSR_NOGM(0, AVB2_TXC,		SEL_AVB2_TXC_1),
733 	PINMUX_IPSR_NOGM(0, AVB2_TD0,		SEL_AVB2_TD0_1),
734 	PINMUX_IPSR_NOGM(0, AVB2_TD1,		SEL_AVB2_TD1_1),
735 	PINMUX_IPSR_NOGM(0, AVB2_TD2,		SEL_AVB2_TD2_1),
736 	PINMUX_IPSR_NOGM(0, AVB2_TD3,		SEL_AVB2_TD3_1),
737 	PINMUX_IPSR_NOGM(0, AVB2_MDC,		SEL_AVB2_MDC_1),
738 	PINMUX_IPSR_NOGM(0, AVB2_MAGIC,		SEL_AVB2_MAGIC_1),
739 	PINMUX_IPSR_NOGM(0, AVB2_AVTP_MATCH,	SEL_AVB2_AVTP_MATCH_1),
740 	PINMUX_IPSR_NOGM(0, AVB2_AVTP_PPS,	SEL_AVB2_AVTP_PPS_1),
741 
742 	/* IP0SR0 */
743 	PINMUX_IPSR_GPSR(IP0SR0_3_0,	ERROROUTC_B),
744 	PINMUX_IPSR_GPSR(IP0SR0_3_0,	TCLK2_A),
745 
746 	PINMUX_IPSR_GPSR(IP0SR0_7_4,	MSIOF3_SS1),
747 
748 	PINMUX_IPSR_GPSR(IP0SR0_11_8,	MSIOF3_SS2),
749 
750 	PINMUX_IPSR_GPSR(IP0SR0_15_12,	IRQ3),
751 	PINMUX_IPSR_GPSR(IP0SR0_15_12,	MSIOF3_SCK),
752 
753 	PINMUX_IPSR_GPSR(IP0SR0_19_16,	IRQ2),
754 	PINMUX_IPSR_GPSR(IP0SR0_19_16,	MSIOF3_TXD),
755 
756 	PINMUX_IPSR_GPSR(IP0SR0_23_20,	IRQ1),
757 	PINMUX_IPSR_GPSR(IP0SR0_23_20,	MSIOF3_RXD),
758 
759 	PINMUX_IPSR_GPSR(IP0SR0_27_24,	IRQ0),
760 	PINMUX_IPSR_GPSR(IP0SR0_27_24,	MSIOF3_SYNC),
761 
762 	PINMUX_IPSR_GPSR(IP0SR0_31_28,	MSIOF5_SS2),
763 
764 	/* IP1SR0 */
765 	PINMUX_IPSR_GPSR(IP1SR0_3_0,	MSIOF5_SS1),
766 
767 	PINMUX_IPSR_GPSR(IP1SR0_7_4,	MSIOF5_SYNC),
768 
769 	PINMUX_IPSR_GPSR(IP1SR0_11_8,	MSIOF5_TXD),
770 
771 	PINMUX_IPSR_GPSR(IP1SR0_15_12,	MSIOF5_SCK),
772 
773 	PINMUX_IPSR_GPSR(IP1SR0_19_16,	MSIOF5_RXD),
774 
775 	PINMUX_IPSR_GPSR(IP1SR0_23_20,	MSIOF2_SS2),
776 	PINMUX_IPSR_GPSR(IP1SR0_23_20,	TCLK1),
777 	PINMUX_IPSR_GPSR(IP1SR0_23_20,	IRQ2_A),
778 
779 	PINMUX_IPSR_GPSR(IP1SR0_27_24,	MSIOF2_SS1),
780 	PINMUX_IPSR_GPSR(IP1SR0_27_24,	HTX1),
781 	PINMUX_IPSR_GPSR(IP1SR0_27_24,	TX1),
782 
783 	PINMUX_IPSR_GPSR(IP1SR0_31_28,	MSIOF2_SYNC),
784 	PINMUX_IPSR_GPSR(IP1SR0_31_28,	HRX1),
785 	PINMUX_IPSR_GPSR(IP1SR0_31_28,	RX1),
786 
787 	/* IP2SR0 */
788 	PINMUX_IPSR_GPSR(IP2SR0_3_0,	MSIOF2_TXD),
789 	PINMUX_IPSR_GPSR(IP2SR0_3_0,	HCTS1_N),
790 	PINMUX_IPSR_GPSR(IP2SR0_3_0,	CTS1_N),
791 
792 	PINMUX_IPSR_GPSR(IP2SR0_7_4,	MSIOF2_SCK),
793 	PINMUX_IPSR_GPSR(IP2SR0_7_4,	HRTS1_N),
794 	PINMUX_IPSR_GPSR(IP2SR0_7_4,	RTS1_N),
795 
796 	PINMUX_IPSR_GPSR(IP2SR0_11_8,	MSIOF2_RXD),
797 	PINMUX_IPSR_GPSR(IP2SR0_11_8,	HSCK1),
798 	PINMUX_IPSR_GPSR(IP2SR0_11_8,	SCK1),
799 
800 	/* IP0SR1 */
801 	PINMUX_IPSR_GPSR(IP0SR1_3_0,	MSIOF1_SS2),
802 	PINMUX_IPSR_GPSR(IP0SR1_3_0,	HTX3_A),
803 	PINMUX_IPSR_GPSR(IP0SR1_3_0,	TX3),
804 
805 	PINMUX_IPSR_GPSR(IP0SR1_7_4,	MSIOF1_SS1),
806 	PINMUX_IPSR_GPSR(IP0SR1_7_4,	HCTS3_N_A),
807 	PINMUX_IPSR_GPSR(IP0SR1_7_4,	RX3),
808 
809 	PINMUX_IPSR_GPSR(IP0SR1_11_8,	MSIOF1_SYNC),
810 	PINMUX_IPSR_GPSR(IP0SR1_11_8,	HRTS3_N_A),
811 	PINMUX_IPSR_GPSR(IP0SR1_11_8,	RTS3_N),
812 
813 	PINMUX_IPSR_GPSR(IP0SR1_15_12,	MSIOF1_SCK),
814 	PINMUX_IPSR_GPSR(IP0SR1_15_12,	HSCK3_A),
815 	PINMUX_IPSR_GPSR(IP0SR1_15_12,	CTS3_N),
816 
817 	PINMUX_IPSR_GPSR(IP0SR1_19_16,	MSIOF1_TXD),
818 	PINMUX_IPSR_GPSR(IP0SR1_19_16,	HRX3_A),
819 	PINMUX_IPSR_GPSR(IP0SR1_19_16,	SCK3),
820 
821 	PINMUX_IPSR_GPSR(IP0SR1_23_20,	MSIOF1_RXD),
822 
823 	PINMUX_IPSR_GPSR(IP0SR1_27_24,	MSIOF0_SS2),
824 	PINMUX_IPSR_GPSR(IP0SR1_27_24,	HTX1_X),
825 	PINMUX_IPSR_GPSR(IP0SR1_27_24,	TX1_X),
826 
827 	PINMUX_IPSR_GPSR(IP0SR1_31_28,	MSIOF0_SS1),
828 	PINMUX_IPSR_GPSR(IP0SR1_31_28,	HRX1_X),
829 	PINMUX_IPSR_GPSR(IP0SR1_31_28,	RX1_X),
830 
831 	/* IP1SR1 */
832 	PINMUX_IPSR_GPSR(IP1SR1_3_0,	MSIOF0_SYNC),
833 	PINMUX_IPSR_GPSR(IP1SR1_3_0,	HCTS1_N_X),
834 	PINMUX_IPSR_GPSR(IP1SR1_3_0,	CTS1_N_X),
835 	PINMUX_IPSR_GPSR(IP1SR1_3_0,	CANFD5_TX_B),
836 
837 	PINMUX_IPSR_GPSR(IP1SR1_7_4,	MSIOF0_TXD),
838 	PINMUX_IPSR_GPSR(IP1SR1_7_4,	HRTS1_N_X),
839 	PINMUX_IPSR_GPSR(IP1SR1_7_4,	RTS1_N_X),
840 	PINMUX_IPSR_GPSR(IP1SR1_7_4,	CANFD5_RX_B),
841 
842 	PINMUX_IPSR_GPSR(IP1SR1_11_8,	MSIOF0_SCK),
843 	PINMUX_IPSR_GPSR(IP1SR1_11_8,	HSCK1_X),
844 	PINMUX_IPSR_GPSR(IP1SR1_11_8,	SCK1_X),
845 
846 	PINMUX_IPSR_GPSR(IP1SR1_15_12,	MSIOF0_RXD),
847 
848 	PINMUX_IPSR_GPSR(IP1SR1_19_16,	HTX0),
849 	PINMUX_IPSR_GPSR(IP1SR1_19_16,	TX0),
850 
851 	PINMUX_IPSR_GPSR(IP1SR1_23_20,	HCTS0_N),
852 	PINMUX_IPSR_GPSR(IP1SR1_23_20,	CTS0_N),
853 	PINMUX_IPSR_GPSR(IP1SR1_23_20,	PWM8_A),
854 
855 	PINMUX_IPSR_GPSR(IP1SR1_27_24,	HRTS0_N),
856 	PINMUX_IPSR_GPSR(IP1SR1_27_24,	RTS0_N),
857 	PINMUX_IPSR_GPSR(IP1SR1_27_24,	PWM9_A),
858 
859 	PINMUX_IPSR_GPSR(IP1SR1_31_28,	HSCK0),
860 	PINMUX_IPSR_GPSR(IP1SR1_31_28,	SCK0),
861 	PINMUX_IPSR_GPSR(IP1SR1_31_28,	PWM0_A),
862 
863 	/* IP2SR1 */
864 	PINMUX_IPSR_GPSR(IP2SR1_3_0,	HRX0),
865 	PINMUX_IPSR_GPSR(IP2SR1_3_0,	RX0),
866 
867 	PINMUX_IPSR_GPSR(IP2SR1_7_4,	SCIF_CLK),
868 	PINMUX_IPSR_GPSR(IP2SR1_7_4,	IRQ4_A),
869 
870 	PINMUX_IPSR_GPSR(IP2SR1_11_8,	SSI_SCK),
871 	PINMUX_IPSR_GPSR(IP2SR1_11_8,	TCLK3),
872 
873 	PINMUX_IPSR_GPSR(IP2SR1_15_12,	SSI_WS),
874 	PINMUX_IPSR_GPSR(IP2SR1_15_12,	TCLK4),
875 
876 	PINMUX_IPSR_GPSR(IP2SR1_19_16,	SSI_SD),
877 	PINMUX_IPSR_GPSR(IP2SR1_19_16,	IRQ0_A),
878 
879 	PINMUX_IPSR_GPSR(IP2SR1_23_20,	AUDIO_CLKOUT),
880 	PINMUX_IPSR_GPSR(IP2SR1_23_20,	IRQ1_A),
881 
882 	PINMUX_IPSR_GPSR(IP2SR1_27_24,	AUDIO_CLKIN),
883 	PINMUX_IPSR_GPSR(IP2SR1_27_24,	PWM3_A),
884 
885 	PINMUX_IPSR_GPSR(IP2SR1_31_28,	TCLK2),
886 	PINMUX_IPSR_GPSR(IP2SR1_31_28,	MSIOF4_SS1),
887 	PINMUX_IPSR_GPSR(IP2SR1_31_28,	IRQ3_B),
888 
889 	/* IP3SR1 */
890 	PINMUX_IPSR_GPSR(IP3SR1_3_0,	HRX3),
891 	PINMUX_IPSR_GPSR(IP3SR1_3_0,	SCK3_A),
892 	PINMUX_IPSR_GPSR(IP3SR1_3_0,	MSIOF4_SS2),
893 
894 	PINMUX_IPSR_GPSR(IP3SR1_7_4,	HSCK3),
895 	PINMUX_IPSR_GPSR(IP3SR1_7_4,	CTS3_N_A),
896 	PINMUX_IPSR_GPSR(IP3SR1_7_4,	MSIOF4_SCK),
897 	PINMUX_IPSR_GPSR(IP3SR1_7_4,	TPU0TO0_A),
898 
899 	PINMUX_IPSR_GPSR(IP3SR1_11_8,	HRTS3_N),
900 	PINMUX_IPSR_GPSR(IP3SR1_11_8,	RTS3_N_A),
901 	PINMUX_IPSR_GPSR(IP3SR1_11_8,	MSIOF4_TXD),
902 	PINMUX_IPSR_GPSR(IP3SR1_11_8,	TPU0TO1_A),
903 
904 	PINMUX_IPSR_GPSR(IP3SR1_15_12,	HCTS3_N),
905 	PINMUX_IPSR_GPSR(IP3SR1_15_12,	RX3_A),
906 	PINMUX_IPSR_GPSR(IP3SR1_15_12,	MSIOF4_RXD),
907 
908 	PINMUX_IPSR_GPSR(IP3SR1_19_16,	HTX3),
909 	PINMUX_IPSR_GPSR(IP3SR1_19_16,	TX3_A),
910 	PINMUX_IPSR_GPSR(IP3SR1_19_16,	MSIOF4_SYNC),
911 
912 	/* IP0SR2 */
913 	PINMUX_IPSR_GPSR(IP0SR2_3_0,	FXR_TXDA),
914 	PINMUX_IPSR_GPSR(IP0SR2_3_0,	CANFD1_TX),
915 	PINMUX_IPSR_GPSR(IP0SR2_3_0,	TPU0TO2_A),
916 
917 	PINMUX_IPSR_GPSR(IP0SR2_7_4,	FXR_TXENA_N),
918 	PINMUX_IPSR_GPSR(IP0SR2_7_4,	CANFD1_RX),
919 	PINMUX_IPSR_GPSR(IP0SR2_7_4,	TPU0TO3_A),
920 
921 	PINMUX_IPSR_GPSR(IP0SR2_11_8,	RXDA_EXTFXR),
922 	PINMUX_IPSR_GPSR(IP0SR2_11_8,	CANFD5_TX),
923 	PINMUX_IPSR_GPSR(IP0SR2_11_8,	IRQ5),
924 
925 	PINMUX_IPSR_GPSR(IP0SR2_15_12,	CLK_EXTFXR),
926 	PINMUX_IPSR_GPSR(IP0SR2_15_12,	CANFD5_RX),
927 	PINMUX_IPSR_GPSR(IP0SR2_15_12,	IRQ4_B),
928 
929 	PINMUX_IPSR_GPSR(IP0SR2_19_16,	RXDB_EXTFXR),
930 
931 	PINMUX_IPSR_GPSR(IP0SR2_23_20,	FXR_TXENB_N),
932 
933 	PINMUX_IPSR_GPSR(IP0SR2_27_24,	FXR_TXDB),
934 
935 	PINMUX_IPSR_GPSR(IP0SR2_31_28,	TPU0TO1),
936 	PINMUX_IPSR_GPSR(IP0SR2_31_28,	CANFD6_TX),
937 	PINMUX_IPSR_GPSR(IP0SR2_31_28,	TCLK2_B),
938 
939 	/* IP1SR2 */
940 	PINMUX_IPSR_GPSR(IP1SR2_3_0,	TPU0TO0),
941 	PINMUX_IPSR_GPSR(IP1SR2_3_0,	CANFD6_RX),
942 	PINMUX_IPSR_GPSR(IP1SR2_3_0,	TCLK1_A),
943 
944 	PINMUX_IPSR_GPSR(IP1SR2_7_4,	CAN_CLK),
945 	PINMUX_IPSR_GPSR(IP1SR2_7_4,	FXR_TXENA_N_X),
946 
947 	PINMUX_IPSR_GPSR(IP1SR2_11_8,	CANFD0_TX),
948 	PINMUX_IPSR_GPSR(IP1SR2_11_8,	FXR_TXENB_N_X),
949 
950 	PINMUX_IPSR_GPSR(IP1SR2_15_12,	CANFD0_RX),
951 	PINMUX_IPSR_GPSR(IP1SR2_15_12,	STPWT_EXTFXR),
952 
953 	PINMUX_IPSR_GPSR(IP1SR2_19_16,	CANFD2_TX),
954 	PINMUX_IPSR_GPSR(IP1SR2_19_16,	TPU0TO2),
955 	PINMUX_IPSR_GPSR(IP1SR2_19_16,	TCLK3_A),
956 
957 	PINMUX_IPSR_GPSR(IP1SR2_23_20,	CANFD2_RX),
958 	PINMUX_IPSR_GPSR(IP1SR2_23_20,	TPU0TO3),
959 	PINMUX_IPSR_GPSR(IP1SR2_23_20,	PWM1_B),
960 	PINMUX_IPSR_GPSR(IP1SR2_23_20,	TCLK4_A),
961 
962 	PINMUX_IPSR_GPSR(IP1SR2_27_24,	CANFD3_TX),
963 	PINMUX_IPSR_GPSR(IP1SR2_27_24,	PWM2_B),
964 
965 	PINMUX_IPSR_GPSR(IP1SR2_31_28,	CANFD3_RX),
966 	PINMUX_IPSR_GPSR(IP1SR2_31_28,	PWM3_B),
967 
968 	/* IP2SR2 */
969 	PINMUX_IPSR_GPSR(IP2SR2_3_0,	CANFD4_TX),
970 	PINMUX_IPSR_GPSR(IP2SR2_3_0,	PWM4),
971 
972 	PINMUX_IPSR_GPSR(IP2SR2_7_4,	CANFD4_RX),
973 	PINMUX_IPSR_GPSR(IP2SR2_7_4,	PWM5),
974 
975 	PINMUX_IPSR_GPSR(IP2SR2_11_8,	CANFD7_TX),
976 	PINMUX_IPSR_GPSR(IP2SR2_11_8,	PWM6),
977 
978 	PINMUX_IPSR_GPSR(IP2SR2_15_12,	CANFD7_RX),
979 	PINMUX_IPSR_GPSR(IP2SR2_15_12,	PWM7),
980 
981 	/* IP0SR3 */
982 	PINMUX_IPSR_GPSR(IP0SR3_3_0,	MMC_SD_D1),
983 	PINMUX_IPSR_GPSR(IP0SR3_7_4,	MMC_SD_D0),
984 	PINMUX_IPSR_GPSR(IP0SR3_11_8,	MMC_SD_D2),
985 	PINMUX_IPSR_GPSR(IP0SR3_15_12,	MMC_SD_CLK),
986 	PINMUX_IPSR_GPSR(IP0SR3_19_16,	MMC_DS),
987 	PINMUX_IPSR_GPSR(IP0SR3_23_20,	MMC_SD_D3),
988 	PINMUX_IPSR_GPSR(IP0SR3_27_24,	MMC_D5),
989 	PINMUX_IPSR_GPSR(IP0SR3_31_28,	MMC_D4),
990 
991 	/* IP1SR3 */
992 	PINMUX_IPSR_GPSR(IP1SR3_3_0,	MMC_D7),
993 
994 	PINMUX_IPSR_GPSR(IP1SR3_7_4,	MMC_D6),
995 
996 	PINMUX_IPSR_GPSR(IP1SR3_11_8,	MMC_SD_CMD),
997 
998 	PINMUX_IPSR_GPSR(IP1SR3_15_12,	SD_CD),
999 
1000 	PINMUX_IPSR_GPSR(IP1SR3_19_16,	SD_WP),
1001 
1002 	PINMUX_IPSR_GPSR(IP1SR3_23_20,	IPC_CLKIN),
1003 	PINMUX_IPSR_GPSR(IP1SR3_23_20,	IPC_CLKEN_IN),
1004 	PINMUX_IPSR_GPSR(IP1SR3_23_20,	PWM1_A),
1005 	PINMUX_IPSR_GPSR(IP1SR3_23_20,	TCLK3_X),
1006 
1007 	PINMUX_IPSR_GPSR(IP1SR3_27_24,	IPC_CLKOUT),
1008 	PINMUX_IPSR_GPSR(IP1SR3_27_24,	IPC_CLKEN_OUT),
1009 	PINMUX_IPSR_GPSR(IP1SR3_27_24,	ERROROUTC_A),
1010 	PINMUX_IPSR_GPSR(IP1SR3_27_24,	TCLK4_X),
1011 
1012 	PINMUX_IPSR_GPSR(IP1SR3_31_28,	QSPI0_SSL),
1013 
1014 	/* IP2SR3 */
1015 	PINMUX_IPSR_GPSR(IP2SR3_3_0,	QSPI0_IO3),
1016 	PINMUX_IPSR_GPSR(IP2SR3_7_4,	QSPI0_IO2),
1017 	PINMUX_IPSR_GPSR(IP2SR3_11_8,	QSPI0_MISO_IO1),
1018 	PINMUX_IPSR_GPSR(IP2SR3_15_12,	QSPI0_MOSI_IO0),
1019 	PINMUX_IPSR_GPSR(IP2SR3_19_16,	QSPI0_SPCLK),
1020 	PINMUX_IPSR_GPSR(IP2SR3_23_20,	QSPI1_MOSI_IO0),
1021 	PINMUX_IPSR_GPSR(IP2SR3_27_24,	QSPI1_SPCLK),
1022 	PINMUX_IPSR_GPSR(IP2SR3_31_28,	QSPI1_MISO_IO1),
1023 
1024 	/* IP3SR3 */
1025 	PINMUX_IPSR_GPSR(IP3SR3_3_0,	QSPI1_IO2),
1026 	PINMUX_IPSR_GPSR(IP3SR3_7_4,	QSPI1_SSL),
1027 	PINMUX_IPSR_GPSR(IP3SR3_11_8,	QSPI1_IO3),
1028 	PINMUX_IPSR_GPSR(IP3SR3_15_12,	RPC_RESET_N),
1029 	PINMUX_IPSR_GPSR(IP3SR3_19_16,	RPC_WP_N),
1030 	PINMUX_IPSR_GPSR(IP3SR3_23_20,	RPC_INT_N),
1031 
1032 	/* IP0SR6 */
1033 	PINMUX_IPSR_GPSR(IP0SR6_3_0,	AVB1_MDIO),
1034 
1035 	PINMUX_IPSR_MSEL(IP0SR6_7_4,	AVB1_MAGIC,		SEL_AVB1_MAGIC_1),
1036 
1037 	PINMUX_IPSR_MSEL(IP0SR6_11_8,	AVB1_MDC,		SEL_AVB1_MDC_1),
1038 
1039 	PINMUX_IPSR_GPSR(IP0SR6_15_12,	AVB1_PHY_INT),
1040 
1041 	PINMUX_IPSR_GPSR(IP0SR6_19_16,	AVB1_LINK),
1042 	PINMUX_IPSR_GPSR(IP0SR6_19_16,	AVB1_MII_TX_ER),
1043 
1044 	PINMUX_IPSR_MSEL(IP0SR6_23_20,	AVB1_AVTP_MATCH,	SEL_AVB1_AVTP_MATCH_1),
1045 	PINMUX_IPSR_MSEL(IP0SR6_23_20,	AVB1_MII_RX_ER,		SEL_AVB1_AVTP_MATCH_0),
1046 
1047 	PINMUX_IPSR_MSEL(IP0SR6_27_24,	AVB1_TXC,		SEL_AVB1_TXC_1),
1048 	PINMUX_IPSR_MSEL(IP0SR6_27_24,	AVB1_MII_TXC,		SEL_AVB1_TXC_0),
1049 
1050 	PINMUX_IPSR_MSEL(IP0SR6_31_28,	AVB1_TX_CTL,		SEL_AVB1_TX_CTL_1),
1051 	PINMUX_IPSR_MSEL(IP0SR6_31_28,	AVB1_MII_TX_EN,		SEL_AVB1_TX_CTL_0),
1052 
1053 	/* IP1SR6 */
1054 	PINMUX_IPSR_GPSR(IP1SR6_3_0,	AVB1_RXC),
1055 	PINMUX_IPSR_GPSR(IP1SR6_3_0,	AVB1_MII_RXC),
1056 
1057 	PINMUX_IPSR_GPSR(IP1SR6_7_4,	AVB1_RX_CTL),
1058 	PINMUX_IPSR_GPSR(IP1SR6_7_4,	AVB1_MII_RX_DV),
1059 
1060 	PINMUX_IPSR_MSEL(IP1SR6_11_8,	AVB1_AVTP_PPS,		SEL_AVB1_AVTP_PPS_1),
1061 	PINMUX_IPSR_MSEL(IP1SR6_11_8,	AVB1_MII_COL,		SEL_AVB1_AVTP_PPS_0),
1062 
1063 	PINMUX_IPSR_GPSR(IP1SR6_15_12,	AVB1_AVTP_CAPTURE),
1064 	PINMUX_IPSR_GPSR(IP1SR6_15_12,	AVB1_MII_CRS),
1065 
1066 	PINMUX_IPSR_MSEL(IP1SR6_19_16,	AVB1_TD1,		SEL_AVB1_TD1_1),
1067 	PINMUX_IPSR_MSEL(IP1SR6_19_16,	AVB1_MII_TD1,		SEL_AVB1_TD1_0),
1068 
1069 	PINMUX_IPSR_MSEL(IP1SR6_23_20,	AVB1_TD0,		SEL_AVB1_TD0_1),
1070 	PINMUX_IPSR_MSEL(IP1SR6_23_20,	AVB1_MII_TD0,		SEL_AVB1_TD0_0),
1071 
1072 	PINMUX_IPSR_GPSR(IP1SR6_27_24,	AVB1_RD1),
1073 	PINMUX_IPSR_GPSR(IP1SR6_27_24,	AVB1_MII_RD1),
1074 
1075 	PINMUX_IPSR_GPSR(IP1SR6_31_28,	AVB1_RD0),
1076 	PINMUX_IPSR_GPSR(IP1SR6_31_28,	AVB1_MII_RD0),
1077 
1078 	/* IP2SR6 */
1079 	PINMUX_IPSR_MSEL(IP2SR6_3_0,	AVB1_TD2,		SEL_AVB1_TD2_1),
1080 	PINMUX_IPSR_MSEL(IP2SR6_3_0,	AVB1_MII_TD2,		SEL_AVB1_TD2_0),
1081 
1082 	PINMUX_IPSR_GPSR(IP2SR6_7_4,	AVB1_RD2),
1083 	PINMUX_IPSR_GPSR(IP2SR6_7_4,	AVB1_MII_RD2),
1084 
1085 	PINMUX_IPSR_MSEL(IP2SR6_11_8,	AVB1_TD3,		SEL_AVB1_TD3_1),
1086 	PINMUX_IPSR_MSEL(IP2SR6_11_8,	AVB1_MII_TD3,		SEL_AVB1_TD3_0),
1087 
1088 	PINMUX_IPSR_GPSR(IP2SR6_15_12,	AVB1_RD3),
1089 	PINMUX_IPSR_GPSR(IP2SR6_15_12,	AVB1_MII_RD3),
1090 
1091 	PINMUX_IPSR_GPSR(IP2SR6_19_16,	AVB1_TXCREFCLK),
1092 
1093 	/* IP0SR7 */
1094 	PINMUX_IPSR_MSEL(IP0SR7_3_0,	AVB0_AVTP_PPS,		SEL_AVB0_AVTP_PPS_1),
1095 	PINMUX_IPSR_MSEL(IP0SR7_3_0,	AVB0_MII_COL,		SEL_AVB0_AVTP_PPS_0),
1096 
1097 	PINMUX_IPSR_GPSR(IP0SR7_7_4,	AVB0_AVTP_CAPTURE),
1098 	PINMUX_IPSR_GPSR(IP0SR7_7_4,	AVB0_MII_CRS),
1099 
1100 	PINMUX_IPSR_MSEL(IP0SR7_11_8,	AVB0_AVTP_MATCH,	SEL_AVB0_AVTP_MATCH_1),
1101 	PINMUX_IPSR_MSEL(IP0SR7_11_8,	AVB0_MII_RX_ER,		SEL_AVB0_AVTP_MATCH_0),
1102 	PINMUX_IPSR_MSEL(IP0SR7_11_8,	CC5_OSCOUT,		SEL_AVB0_AVTP_MATCH_0),
1103 
1104 	PINMUX_IPSR_MSEL(IP0SR7_15_12,	AVB0_TD3,		SEL_AVB0_TD3_1),
1105 	PINMUX_IPSR_MSEL(IP0SR7_15_12,	AVB0_MII_TD3,		SEL_AVB0_TD3_0),
1106 
1107 	PINMUX_IPSR_GPSR(IP0SR7_19_16,	AVB0_LINK),
1108 	PINMUX_IPSR_GPSR(IP0SR7_19_16,	AVB0_MII_TX_ER),
1109 
1110 	PINMUX_IPSR_GPSR(IP0SR7_23_20,	AVB0_PHY_INT),
1111 
1112 	PINMUX_IPSR_MSEL(IP0SR7_27_24,	AVB0_TD2,		SEL_AVB0_TD2_1),
1113 	PINMUX_IPSR_MSEL(IP0SR7_27_24,	AVB0_MII_TD2,		SEL_AVB0_TD2_0),
1114 
1115 	PINMUX_IPSR_MSEL(IP0SR7_31_28,	AVB0_TD1,		SEL_AVB0_TD1_1),
1116 	PINMUX_IPSR_MSEL(IP0SR7_31_28,	AVB0_MII_TD1,		SEL_AVB0_TD1_0),
1117 
1118 	/* IP1SR7 */
1119 	PINMUX_IPSR_GPSR(IP1SR7_3_0,	AVB0_RD3),
1120 	PINMUX_IPSR_GPSR(IP1SR7_3_0,	AVB0_MII_RD3),
1121 
1122 	PINMUX_IPSR_GPSR(IP1SR7_7_4,	AVB0_TXCREFCLK),
1123 
1124 	PINMUX_IPSR_MSEL(IP1SR7_11_8,	AVB0_MAGIC,		SEL_AVB0_MAGIC_1),
1125 
1126 	PINMUX_IPSR_MSEL(IP1SR7_15_12,	AVB0_TD0,		SEL_AVB0_TD0_1),
1127 	PINMUX_IPSR_MSEL(IP1SR7_15_12,	AVB0_MII_TD0,		SEL_AVB0_TD0_0),
1128 
1129 	PINMUX_IPSR_GPSR(IP1SR7_19_16,	AVB0_RD2),
1130 	PINMUX_IPSR_GPSR(IP1SR7_19_16,	AVB0_MII_RD2),
1131 
1132 	PINMUX_IPSR_MSEL(IP1SR7_23_20,	AVB0_MDC,		SEL_AVB0_MDC_1),
1133 
1134 	PINMUX_IPSR_GPSR(IP1SR7_27_24,	AVB0_MDIO),
1135 
1136 	PINMUX_IPSR_MSEL(IP1SR7_31_28,	AVB0_TXC,		SEL_AVB0_TXC_1),
1137 	PINMUX_IPSR_MSEL(IP1SR7_31_28,	AVB0_MII_TXC,		SEL_AVB0_TXC_0),
1138 
1139 	/* IP2SR7 */
1140 	PINMUX_IPSR_MSEL(IP2SR7_3_0,	AVB0_TX_CTL,		SEL_AVB0_TX_CTL_1),
1141 	PINMUX_IPSR_MSEL(IP2SR7_3_0,	AVB0_MII_TX_EN,		SEL_AVB0_TX_CTL_0),
1142 
1143 	PINMUX_IPSR_GPSR(IP2SR7_7_4,	AVB0_RD1),
1144 	PINMUX_IPSR_GPSR(IP2SR7_7_4,	AVB0_MII_RD1),
1145 
1146 	PINMUX_IPSR_GPSR(IP2SR7_11_8,	AVB0_RD0),
1147 	PINMUX_IPSR_GPSR(IP2SR7_11_8,	AVB0_MII_RD0),
1148 
1149 	PINMUX_IPSR_GPSR(IP2SR7_15_12,	AVB0_RXC),
1150 	PINMUX_IPSR_GPSR(IP2SR7_15_12,	AVB0_MII_RXC),
1151 
1152 	PINMUX_IPSR_GPSR(IP2SR7_19_16,	AVB0_RX_CTL),
1153 	PINMUX_IPSR_GPSR(IP2SR7_19_16,	AVB0_MII_RX_DV),
1154 
1155 	/* IP0SR8 */
1156 	PINMUX_IPSR_MSEL(IP0SR8_3_0,	SCL0,			SEL_SCL0_0),
1157 	PINMUX_IPSR_MSEL(IP0SR8_7_4,	SDA0,			SEL_SDA0_0),
1158 	PINMUX_IPSR_MSEL(IP0SR8_11_8,	SCL1,			SEL_SCL1_0),
1159 	PINMUX_IPSR_MSEL(IP0SR8_15_12,	SDA1,			SEL_SDA1_0),
1160 	PINMUX_IPSR_MSEL(IP0SR8_19_16,	SCL2,			SEL_SCL2_0),
1161 	PINMUX_IPSR_MSEL(IP0SR8_23_20,	SDA2,			SEL_SDA2_0),
1162 	PINMUX_IPSR_MSEL(IP0SR8_27_24,	SCL3,			SEL_SCL3_0),
1163 	PINMUX_IPSR_MSEL(IP0SR8_31_28,	SDA3,			SEL_SDA3_0),
1164 
1165 	/* IP1SR8 */
1166 	PINMUX_IPSR_MSEL(IP1SR8_3_0,	SCL4,			SEL_SCL4_0),
1167 	PINMUX_IPSR_MSEL(IP1SR8_3_0,	HRX2,			SEL_SCL4_0),
1168 	PINMUX_IPSR_MSEL(IP1SR8_3_0,	SCK4,			SEL_SCL4_0),
1169 
1170 	PINMUX_IPSR_MSEL(IP1SR8_7_4,	SDA4,			SEL_SDA4_0),
1171 	PINMUX_IPSR_MSEL(IP1SR8_7_4,	HTX2,			SEL_SDA4_0),
1172 	PINMUX_IPSR_MSEL(IP1SR8_7_4,	CTS4_N,			SEL_SDA4_0),
1173 
1174 	PINMUX_IPSR_MSEL(IP1SR8_11_8,	SCL5,			SEL_SCL5_0),
1175 	PINMUX_IPSR_MSEL(IP1SR8_11_8,	HRTS2_N,		SEL_SCL5_0),
1176 	PINMUX_IPSR_MSEL(IP1SR8_11_8,	RTS4_N,			SEL_SCL5_0),
1177 
1178 	PINMUX_IPSR_MSEL(IP1SR8_15_12,	SDA5,			SEL_SDA5_0),
1179 	PINMUX_IPSR_MSEL(IP1SR8_15_12,	SCIF_CLK2,		SEL_SDA5_0),
1180 
1181 	PINMUX_IPSR_GPSR(IP1SR8_19_16,	HCTS2_N),
1182 	PINMUX_IPSR_GPSR(IP1SR8_19_16,	TX4),
1183 
1184 	PINMUX_IPSR_GPSR(IP1SR8_23_20,	HSCK2),
1185 	PINMUX_IPSR_GPSR(IP1SR8_23_20,	RX4),
1186 };
1187 
1188 /*
1189  * Pins not associated with a GPIO port.
1190  */
1191 enum {
1192 	GP_ASSIGN_LAST(),
1193 };
1194 
1195 static const struct sh_pfc_pin pinmux_pins[] = {
1196 	PINMUX_GPIO_GP_ALL(),
1197 };
1198 
1199 /* - AVB0 ------------------------------------------------ */
1200 static const unsigned int avb0_link_pins[] = {
1201 	/* AVB0_LINK */
1202 	RCAR_GP_PIN(7, 4),
1203 };
1204 static const unsigned int avb0_link_mux[] = {
1205 	AVB0_LINK_MARK,
1206 };
1207 static const unsigned int avb0_magic_pins[] = {
1208 	/* AVB0_MAGIC */
1209 	RCAR_GP_PIN(7, 10),
1210 };
1211 static const unsigned int avb0_magic_mux[] = {
1212 	AVB0_MAGIC_MARK,
1213 };
1214 static const unsigned int avb0_phy_int_pins[] = {
1215 	/* AVB0_PHY_INT */
1216 	RCAR_GP_PIN(7, 5),
1217 };
1218 static const unsigned int avb0_phy_int_mux[] = {
1219 	AVB0_PHY_INT_MARK,
1220 };
1221 static const unsigned int avb0_mdio_pins[] = {
1222 	/* AVB0_MDC, AVB0_MDIO */
1223 	RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14),
1224 };
1225 static const unsigned int avb0_mdio_mux[] = {
1226 	AVB0_MDC_MARK, AVB0_MDIO_MARK,
1227 };
1228 static const unsigned int avb0_rgmii_pins[] = {
1229 	/*
1230 	 * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,
1231 	 * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3,
1232 	 */
1233 	RCAR_GP_PIN(7, 16), RCAR_GP_PIN(7, 15),
1234 	RCAR_GP_PIN(7, 11), RCAR_GP_PIN(7,  7),
1235 	RCAR_GP_PIN(7,  6), RCAR_GP_PIN(7,  3),
1236 	RCAR_GP_PIN(7, 20), RCAR_GP_PIN(7, 19),
1237 	RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),
1238 	RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7,  8),
1239 };
1240 static const unsigned int avb0_rgmii_mux[] = {
1241 	AVB0_TX_CTL_MARK,	AVB0_TXC_MARK,
1242 	AVB0_TD0_MARK,		AVB0_TD1_MARK,
1243 	AVB0_TD2_MARK,		AVB0_TD3_MARK,
1244 	AVB0_RX_CTL_MARK,	AVB0_RXC_MARK,
1245 	AVB0_RD0_MARK,		AVB0_RD1_MARK,
1246 	AVB0_RD2_MARK,		AVB0_RD3_MARK,
1247 };
1248 static const unsigned int avb0_txcrefclk_pins[] = {
1249 	/* AVB0_TXCREFCLK */
1250 	RCAR_GP_PIN(7, 9),
1251 };
1252 static const unsigned int avb0_txcrefclk_mux[] = {
1253 	AVB0_TXCREFCLK_MARK,
1254 };
1255 static const unsigned int avb0_avtp_pps_pins[] = {
1256 	/* AVB0_AVTP_PPS */
1257 	RCAR_GP_PIN(7, 0),
1258 };
1259 static const unsigned int avb0_avtp_pps_mux[] = {
1260 	AVB0_AVTP_PPS_MARK,
1261 };
1262 static const unsigned int avb0_avtp_capture_pins[] = {
1263 	/* AVB0_AVTP_CAPTURE */
1264 	RCAR_GP_PIN(7, 1),
1265 };
1266 static const unsigned int avb0_avtp_capture_mux[] = {
1267 	AVB0_AVTP_CAPTURE_MARK,
1268 };
1269 static const unsigned int avb0_avtp_match_pins[] = {
1270 	/* AVB0_AVTP_MATCH */
1271 	RCAR_GP_PIN(7, 2),
1272 };
1273 static const unsigned int avb0_avtp_match_mux[] = {
1274 	AVB0_AVTP_MATCH_MARK,
1275 };
1276 
1277 /* - AVB1 ------------------------------------------------ */
1278 static const unsigned int avb1_link_pins[] = {
1279 	/* AVB1_LINK */
1280 	RCAR_GP_PIN(6, 4),
1281 };
1282 static const unsigned int avb1_link_mux[] = {
1283 	AVB1_LINK_MARK,
1284 };
1285 static const unsigned int avb1_magic_pins[] = {
1286 	/* AVB1_MAGIC */
1287 	RCAR_GP_PIN(6, 1),
1288 };
1289 static const unsigned int avb1_magic_mux[] = {
1290 	AVB1_MAGIC_MARK,
1291 };
1292 static const unsigned int avb1_phy_int_pins[] = {
1293 	/* AVB1_PHY_INT */
1294 	RCAR_GP_PIN(6, 3),
1295 };
1296 static const unsigned int avb1_phy_int_mux[] = {
1297 	AVB1_PHY_INT_MARK,
1298 };
1299 static const unsigned int avb1_mdio_pins[] = {
1300 	/* AVB1_MDC, AVB1_MDIO */
1301 	RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 0),
1302 };
1303 static const unsigned int avb1_mdio_mux[] = {
1304 	AVB1_MDC_MARK, AVB1_MDIO_MARK,
1305 };
1306 static const unsigned int avb1_rgmii_pins[] = {
1307 	/*
1308 	 * AVB1_TX_CTL, AVB1_TXC, AVB1_TD0, AVB1_TD1, AVB1_TD2, AVB1_TD3,
1309 	 * AVB1_RX_CTL, AVB1_RXC, AVB1_RD0, AVB1_RD1, AVB1_RD2, AVB1_RD3,
1310 	 */
1311 	RCAR_GP_PIN(6,  7), RCAR_GP_PIN(6,  6),
1312 	RCAR_GP_PIN(6, 13), RCAR_GP_PIN(6, 12),
1313 	RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 18),
1314 	RCAR_GP_PIN(6,  9), RCAR_GP_PIN(6,  8),
1315 	RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14),
1316 	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 19),
1317 };
1318 static const unsigned int avb1_rgmii_mux[] = {
1319 	AVB1_TX_CTL_MARK,	AVB1_TXC_MARK,
1320 	AVB1_TD0_MARK,		AVB1_TD1_MARK,
1321 	AVB1_TD2_MARK,		AVB1_TD3_MARK,
1322 	AVB1_RX_CTL_MARK,	AVB1_RXC_MARK,
1323 	AVB1_RD0_MARK,		AVB1_RD1_MARK,
1324 	AVB1_RD2_MARK,		AVB1_RD3_MARK,
1325 };
1326 static const unsigned int avb1_txcrefclk_pins[] = {
1327 	/* AVB1_TXCREFCLK */
1328 	RCAR_GP_PIN(6, 20),
1329 };
1330 static const unsigned int avb1_txcrefclk_mux[] = {
1331 	AVB1_TXCREFCLK_MARK,
1332 };
1333 static const unsigned int avb1_avtp_pps_pins[] = {
1334 	/* AVB1_AVTP_PPS */
1335 	RCAR_GP_PIN(6, 10),
1336 };
1337 static const unsigned int avb1_avtp_pps_mux[] = {
1338 	AVB1_AVTP_PPS_MARK,
1339 };
1340 static const unsigned int avb1_avtp_capture_pins[] = {
1341 	/* AVB1_AVTP_CAPTURE */
1342 	RCAR_GP_PIN(6, 11),
1343 };
1344 static const unsigned int avb1_avtp_capture_mux[] = {
1345 	AVB1_AVTP_CAPTURE_MARK,
1346 };
1347 static const unsigned int avb1_avtp_match_pins[] = {
1348 	/* AVB1_AVTP_MATCH */
1349 	RCAR_GP_PIN(6, 5),
1350 };
1351 static const unsigned int avb1_avtp_match_mux[] = {
1352 	AVB1_AVTP_MATCH_MARK,
1353 };
1354 
1355 /* - AVB2 ------------------------------------------------ */
1356 static const unsigned int avb2_link_pins[] = {
1357 	/* AVB2_LINK */
1358 	RCAR_GP_PIN(5, 3),
1359 };
1360 static const unsigned int avb2_link_mux[] = {
1361 	AVB2_LINK_MARK,
1362 };
1363 static const unsigned int avb2_magic_pins[] = {
1364 	/* AVB2_MAGIC */
1365 	RCAR_GP_PIN(5, 5),
1366 };
1367 static const unsigned int avb2_magic_mux[] = {
1368 	AVB2_MAGIC_MARK,
1369 };
1370 static const unsigned int avb2_phy_int_pins[] = {
1371 	/* AVB2_PHY_INT */
1372 	RCAR_GP_PIN(5, 4),
1373 };
1374 static const unsigned int avb2_phy_int_mux[] = {
1375 	AVB2_PHY_INT_MARK,
1376 };
1377 static const unsigned int avb2_mdio_pins[] = {
1378 	/* AVB2_MDC, AVB2_MDIO */
1379 	RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 10),
1380 };
1381 static const unsigned int avb2_mdio_mux[] = {
1382 	AVB2_MDC_MARK, AVB2_MDIO_MARK,
1383 };
1384 static const unsigned int avb2_rgmii_pins[] = {
1385 	/*
1386 	 * AVB2_TX_CTL, AVB2_TXC, AVB2_TD0, AVB2_TD1, AVB2_TD2, AVB2_TD3,
1387 	 * AVB2_RX_CTL, AVB2_RXC, AVB2_RD0, AVB2_RD1, AVB2_RD2, AVB2_RD3,
1388 	 */
1389 	RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 16),
1390 	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 12),
1391 	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5,  8),
1392 	RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 18),
1393 	RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 14),
1394 	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5,  9),
1395 };
1396 static const unsigned int avb2_rgmii_mux[] = {
1397 	AVB2_TX_CTL_MARK,	AVB2_TXC_MARK,
1398 	AVB2_TD0_MARK,		AVB2_TD1_MARK,
1399 	AVB2_TD2_MARK,		AVB2_TD3_MARK,
1400 	AVB2_RX_CTL_MARK,	AVB2_RXC_MARK,
1401 	AVB2_RD0_MARK,		AVB2_RD1_MARK,
1402 	AVB2_RD2_MARK,		AVB2_RD3_MARK,
1403 };
1404 static const unsigned int avb2_txcrefclk_pins[] = {
1405 	/* AVB2_TXCREFCLK */
1406 	RCAR_GP_PIN(5, 7),
1407 };
1408 static const unsigned int avb2_txcrefclk_mux[] = {
1409 	AVB2_TXCREFCLK_MARK,
1410 };
1411 static const unsigned int avb2_avtp_pps_pins[] = {
1412 	/* AVB2_AVTP_PPS */
1413 	RCAR_GP_PIN(5, 0),
1414 };
1415 static const unsigned int avb2_avtp_pps_mux[] = {
1416 	AVB2_AVTP_PPS_MARK,
1417 };
1418 static const unsigned int avb2_avtp_capture_pins[] = {
1419 	/* AVB2_AVTP_CAPTURE */
1420 	RCAR_GP_PIN(5, 1),
1421 };
1422 static const unsigned int avb2_avtp_capture_mux[] = {
1423 	AVB2_AVTP_CAPTURE_MARK,
1424 };
1425 static const unsigned int avb2_avtp_match_pins[] = {
1426 	/* AVB2_AVTP_MATCH */
1427 	RCAR_GP_PIN(5, 2),
1428 };
1429 static const unsigned int avb2_avtp_match_mux[] = {
1430 	AVB2_AVTP_MATCH_MARK,
1431 };
1432 
1433 /* - CANFD0 ----------------------------------------------------------------- */
1434 static const unsigned int canfd0_data_pins[] = {
1435 	/* CANFD0_TX, CANFD0_RX */
1436 	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1437 };
1438 static const unsigned int canfd0_data_mux[] = {
1439 	CANFD0_TX_MARK, CANFD0_RX_MARK,
1440 };
1441 
1442 /* - CANFD1 ----------------------------------------------------------------- */
1443 static const unsigned int canfd1_data_pins[] = {
1444 	/* CANFD1_TX, CANFD1_RX */
1445 	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1446 };
1447 static const unsigned int canfd1_data_mux[] = {
1448 	CANFD1_TX_MARK, CANFD1_RX_MARK,
1449 };
1450 
1451 /* - CANFD2 ----------------------------------------------------------------- */
1452 static const unsigned int canfd2_data_pins[] = {
1453 	/* CANFD2_TX, CANFD2_RX */
1454 	RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1455 };
1456 static const unsigned int canfd2_data_mux[] = {
1457 	CANFD2_TX_MARK, CANFD2_RX_MARK,
1458 };
1459 
1460 /* - CANFD3 ----------------------------------------------------------------- */
1461 static const unsigned int canfd3_data_pins[] = {
1462 	/* CANFD3_TX, CANFD3_RX */
1463 	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1464 };
1465 static const unsigned int canfd3_data_mux[] = {
1466 	CANFD3_TX_MARK, CANFD3_RX_MARK,
1467 };
1468 
1469 /* - CANFD4 ----------------------------------------------------------------- */
1470 static const unsigned int canfd4_data_pins[] = {
1471 	/* CANFD4_TX, CANFD4_RX */
1472 	RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
1473 };
1474 static const unsigned int canfd4_data_mux[] = {
1475 	CANFD4_TX_MARK, CANFD4_RX_MARK,
1476 };
1477 
1478 /* - CANFD5 ----------------------------------------------------------------- */
1479 static const unsigned int canfd5_data_pins[] = {
1480 	/* CANFD5_TX, CANFD5_RX */
1481 	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
1482 };
1483 static const unsigned int canfd5_data_mux[] = {
1484 	CANFD5_TX_MARK, CANFD5_RX_MARK,
1485 };
1486 
1487 /* - CANFD5_B ----------------------------------------------------------------- */
1488 static const unsigned int canfd5_data_b_pins[] = {
1489 	/* CANFD5_TX_B, CANFD5_RX_B */
1490 	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
1491 };
1492 static const unsigned int canfd5_data_b_mux[] = {
1493 	CANFD5_TX_B_MARK, CANFD5_RX_B_MARK,
1494 };
1495 
1496 /* - CANFD6 ----------------------------------------------------------------- */
1497 static const unsigned int canfd6_data_pins[] = {
1498 	/* CANFD6_TX, CANFD6_RX */
1499 	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
1500 };
1501 static const unsigned int canfd6_data_mux[] = {
1502 	CANFD6_TX_MARK, CANFD6_RX_MARK,
1503 };
1504 
1505 /* - CANFD7 ----------------------------------------------------------------- */
1506 static const unsigned int canfd7_data_pins[] = {
1507 	/* CANFD7_TX, CANFD7_RX */
1508 	RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
1509 };
1510 static const unsigned int canfd7_data_mux[] = {
1511 	CANFD7_TX_MARK, CANFD7_RX_MARK,
1512 };
1513 
1514 /* - CANFD Clock ------------------------------------------------------------ */
1515 static const unsigned int can_clk_pins[] = {
1516 	/* CAN_CLK */
1517 	RCAR_GP_PIN(2, 9),
1518 };
1519 static const unsigned int can_clk_mux[] = {
1520 	CAN_CLK_MARK,
1521 };
1522 
1523 /* - HSCIF0 ----------------------------------------------------------------- */
1524 static const unsigned int hscif0_data_pins[] = {
1525 	/* HRX0, HTX0 */
1526 	RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12),
1527 };
1528 static const unsigned int hscif0_data_mux[] = {
1529 	HRX0_MARK, HTX0_MARK,
1530 };
1531 static const unsigned int hscif0_clk_pins[] = {
1532 	/* HSCK0 */
1533 	RCAR_GP_PIN(1, 15),
1534 };
1535 static const unsigned int hscif0_clk_mux[] = {
1536 	HSCK0_MARK,
1537 };
1538 static const unsigned int hscif0_ctrl_pins[] = {
1539 	/* HRTS0_N, HCTS0_N */
1540 	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1541 };
1542 static const unsigned int hscif0_ctrl_mux[] = {
1543 	HRTS0_N_MARK, HCTS0_N_MARK,
1544 };
1545 
1546 /* - HSCIF1 ----------------------------------------------------------------- */
1547 static const unsigned int hscif1_data_pins[] = {
1548 	/* HRX1, HTX1 */
1549 	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
1550 };
1551 static const unsigned int hscif1_data_mux[] = {
1552 	HRX1_MARK, HTX1_MARK,
1553 };
1554 static const unsigned int hscif1_clk_pins[] = {
1555 	/* HSCK1 */
1556 	RCAR_GP_PIN(0, 18),
1557 };
1558 static const unsigned int hscif1_clk_mux[] = {
1559 	HSCK1_MARK,
1560 };
1561 static const unsigned int hscif1_ctrl_pins[] = {
1562 	/* HRTS1_N, HCTS1_N */
1563 	RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
1564 };
1565 static const unsigned int hscif1_ctrl_mux[] = {
1566 	HRTS1_N_MARK, HCTS1_N_MARK,
1567 };
1568 
1569 /* - HSCIF1_X---------------------------------------------------------------- */
1570 static const unsigned int hscif1_data_x_pins[] = {
1571 	/* HRX1_X, HTX1_X */
1572 	RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
1573 };
1574 static const unsigned int hscif1_data_x_mux[] = {
1575 	HRX1_X_MARK, HTX1_X_MARK,
1576 };
1577 static const unsigned int hscif1_clk_x_pins[] = {
1578 	/* HSCK1_X */
1579 	RCAR_GP_PIN(1, 10),
1580 };
1581 static const unsigned int hscif1_clk_x_mux[] = {
1582 	HSCK1_X_MARK,
1583 };
1584 static const unsigned int hscif1_ctrl_x_pins[] = {
1585 	/* HRTS1_N_X, HCTS1_N_X */
1586 	RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
1587 };
1588 static const unsigned int hscif1_ctrl_x_mux[] = {
1589 	HRTS1_N_X_MARK, HCTS1_N_X_MARK,
1590 };
1591 
1592 /* - HSCIF2 ----------------------------------------------------------------- */
1593 static const unsigned int hscif2_data_pins[] = {
1594 	/* HRX2, HTX2 */
1595 	RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
1596 };
1597 static const unsigned int hscif2_data_mux[] = {
1598 	HRX2_MARK, HTX2_MARK,
1599 };
1600 static const unsigned int hscif2_clk_pins[] = {
1601 	/* HSCK2 */
1602 	RCAR_GP_PIN(8, 13),
1603 };
1604 static const unsigned int hscif2_clk_mux[] = {
1605 	HSCK2_MARK,
1606 };
1607 static const unsigned int hscif2_ctrl_pins[] = {
1608 	/* HRTS2_N, HCTS2_N */
1609 	RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 12),
1610 };
1611 static const unsigned int hscif2_ctrl_mux[] = {
1612 	HRTS2_N_MARK, HCTS2_N_MARK,
1613 };
1614 
1615 /* - HSCIF3 ----------------------------------------------------------------- */
1616 static const unsigned int hscif3_data_pins[] = {
1617 	/* HRX3, HTX3 */
1618 	RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 28),
1619 };
1620 static const unsigned int hscif3_data_mux[] = {
1621 	HRX3_MARK, HTX3_MARK,
1622 };
1623 static const unsigned int hscif3_clk_pins[] = {
1624 	/* HSCK3 */
1625 	RCAR_GP_PIN(1, 25),
1626 };
1627 static const unsigned int hscif3_clk_mux[] = {
1628 	HSCK3_MARK,
1629 };
1630 static const unsigned int hscif3_ctrl_pins[] = {
1631 	/* HRTS3_N, HCTS3_N */
1632 	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27),
1633 };
1634 static const unsigned int hscif3_ctrl_mux[] = {
1635 	HRTS3_N_MARK, HCTS3_N_MARK,
1636 };
1637 
1638 /* - HSCIF3_A ----------------------------------------------------------------- */
1639 static const unsigned int hscif3_data_a_pins[] = {
1640 	/* HRX3_A, HTX3_A */
1641 	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0),
1642 };
1643 static const unsigned int hscif3_data_a_mux[] = {
1644 	HRX3_A_MARK, HTX3_A_MARK,
1645 };
1646 static const unsigned int hscif3_clk_a_pins[] = {
1647 	/* HSCK3_A */
1648 	RCAR_GP_PIN(1, 3),
1649 };
1650 static const unsigned int hscif3_clk_a_mux[] = {
1651 	HSCK3_A_MARK,
1652 };
1653 static const unsigned int hscif3_ctrl_a_pins[] = {
1654 	/* HRTS3_N_A, HCTS3_N_A */
1655 	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
1656 };
1657 static const unsigned int hscif3_ctrl_a_mux[] = {
1658 	HRTS3_N_A_MARK, HCTS3_N_A_MARK,
1659 };
1660 
1661 /* - I2C0 ------------------------------------------------------------------- */
1662 static const unsigned int i2c0_pins[] = {
1663 	/* SDA0, SCL0 */
1664 	RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 0),
1665 };
1666 static const unsigned int i2c0_mux[] = {
1667 	SDA0_MARK, SCL0_MARK,
1668 };
1669 
1670 /* - I2C1 ------------------------------------------------------------------- */
1671 static const unsigned int i2c1_pins[] = {
1672 	/* SDA1, SCL1 */
1673 	RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 2),
1674 };
1675 static const unsigned int i2c1_mux[] = {
1676 	SDA1_MARK, SCL1_MARK,
1677 };
1678 
1679 /* - I2C2 ------------------------------------------------------------------- */
1680 static const unsigned int i2c2_pins[] = {
1681 	/* SDA2, SCL2 */
1682 	RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 4),
1683 };
1684 static const unsigned int i2c2_mux[] = {
1685 	SDA2_MARK, SCL2_MARK,
1686 };
1687 
1688 /* - I2C3 ------------------------------------------------------------------- */
1689 static const unsigned int i2c3_pins[] = {
1690 	/* SDA3, SCL3 */
1691 	RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 6),
1692 };
1693 static const unsigned int i2c3_mux[] = {
1694 	SDA3_MARK, SCL3_MARK,
1695 };
1696 
1697 /* - I2C4 ------------------------------------------------------------------- */
1698 static const unsigned int i2c4_pins[] = {
1699 	/* SDA4, SCL4 */
1700 	RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 8),
1701 };
1702 static const unsigned int i2c4_mux[] = {
1703 	SDA4_MARK, SCL4_MARK,
1704 };
1705 
1706 /* - I2C5 ------------------------------------------------------------------- */
1707 static const unsigned int i2c5_pins[] = {
1708 	/* SDA5, SCL5 */
1709 	RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 10),
1710 };
1711 static const unsigned int i2c5_mux[] = {
1712 	SDA5_MARK, SCL5_MARK,
1713 };
1714 
1715 /* - MMC -------------------------------------------------------------------- */
1716 static const unsigned int mmc_data_pins[] = {
1717 	/* MMC_SD_D[0:3], MMC_D[4:7] */
1718 	RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
1719 	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 5),
1720 	RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6),
1721 	RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
1722 };
1723 static const unsigned int mmc_data_mux[] = {
1724 	MMC_SD_D0_MARK, MMC_SD_D1_MARK,
1725 	MMC_SD_D2_MARK, MMC_SD_D3_MARK,
1726 	MMC_D4_MARK, MMC_D5_MARK,
1727 	MMC_D6_MARK, MMC_D7_MARK,
1728 };
1729 static const unsigned int mmc_ctrl_pins[] = {
1730 	/* MMC_SD_CLK, MMC_SD_CMD */
1731 	RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 10),
1732 };
1733 static const unsigned int mmc_ctrl_mux[] = {
1734 	MMC_SD_CLK_MARK, MMC_SD_CMD_MARK,
1735 };
1736 static const unsigned int mmc_cd_pins[] = {
1737 	/* SD_CD */
1738 	RCAR_GP_PIN(3, 11),
1739 };
1740 static const unsigned int mmc_cd_mux[] = {
1741 	SD_CD_MARK,
1742 };
1743 static const unsigned int mmc_wp_pins[] = {
1744 	/* SD_WP */
1745 	RCAR_GP_PIN(3, 12),
1746 };
1747 static const unsigned int mmc_wp_mux[] = {
1748 	SD_WP_MARK,
1749 };
1750 static const unsigned int mmc_ds_pins[] = {
1751 	/* MMC_DS */
1752 	RCAR_GP_PIN(3, 4),
1753 };
1754 static const unsigned int mmc_ds_mux[] = {
1755 	MMC_DS_MARK,
1756 };
1757 
1758 /* - MSIOF0 ----------------------------------------------------------------- */
1759 static const unsigned int msiof0_clk_pins[] = {
1760 	/* MSIOF0_SCK */
1761 	RCAR_GP_PIN(1, 10),
1762 };
1763 static const unsigned int msiof0_clk_mux[] = {
1764 	MSIOF0_SCK_MARK,
1765 };
1766 static const unsigned int msiof0_sync_pins[] = {
1767 	/* MSIOF0_SYNC */
1768 	RCAR_GP_PIN(1, 8),
1769 };
1770 static const unsigned int msiof0_sync_mux[] = {
1771 	MSIOF0_SYNC_MARK,
1772 };
1773 static const unsigned int msiof0_ss1_pins[] = {
1774 	/* MSIOF0_SS1 */
1775 	RCAR_GP_PIN(1, 7),
1776 };
1777 static const unsigned int msiof0_ss1_mux[] = {
1778 	MSIOF0_SS1_MARK,
1779 };
1780 static const unsigned int msiof0_ss2_pins[] = {
1781 	/* MSIOF0_SS2 */
1782 	RCAR_GP_PIN(1, 6),
1783 };
1784 static const unsigned int msiof0_ss2_mux[] = {
1785 	MSIOF0_SS2_MARK,
1786 };
1787 static const unsigned int msiof0_txd_pins[] = {
1788 	/* MSIOF0_TXD */
1789 	RCAR_GP_PIN(1, 9),
1790 };
1791 static const unsigned int msiof0_txd_mux[] = {
1792 	MSIOF0_TXD_MARK,
1793 };
1794 static const unsigned int msiof0_rxd_pins[] = {
1795 	/* MSIOF0_RXD */
1796 	RCAR_GP_PIN(1, 11),
1797 };
1798 static const unsigned int msiof0_rxd_mux[] = {
1799 	MSIOF0_RXD_MARK,
1800 };
1801 
1802 /* - MSIOF1 ----------------------------------------------------------------- */
1803 static const unsigned int msiof1_clk_pins[] = {
1804 	/* MSIOF1_SCK */
1805 	RCAR_GP_PIN(1, 3),
1806 };
1807 static const unsigned int msiof1_clk_mux[] = {
1808 	MSIOF1_SCK_MARK,
1809 };
1810 static const unsigned int msiof1_sync_pins[] = {
1811 	/* MSIOF1_SYNC */
1812 	RCAR_GP_PIN(1, 2),
1813 };
1814 static const unsigned int msiof1_sync_mux[] = {
1815 	MSIOF1_SYNC_MARK,
1816 };
1817 static const unsigned int msiof1_ss1_pins[] = {
1818 	/* MSIOF1_SS1 */
1819 	RCAR_GP_PIN(1, 1),
1820 };
1821 static const unsigned int msiof1_ss1_mux[] = {
1822 	MSIOF1_SS1_MARK,
1823 };
1824 static const unsigned int msiof1_ss2_pins[] = {
1825 	/* MSIOF1_SS2 */
1826 	RCAR_GP_PIN(1, 0),
1827 };
1828 static const unsigned int msiof1_ss2_mux[] = {
1829 	MSIOF1_SS2_MARK,
1830 };
1831 static const unsigned int msiof1_txd_pins[] = {
1832 	/* MSIOF1_TXD */
1833 	RCAR_GP_PIN(1, 4),
1834 };
1835 static const unsigned int msiof1_txd_mux[] = {
1836 	MSIOF1_TXD_MARK,
1837 };
1838 static const unsigned int msiof1_rxd_pins[] = {
1839 	/* MSIOF1_RXD */
1840 	RCAR_GP_PIN(1, 5),
1841 };
1842 static const unsigned int msiof1_rxd_mux[] = {
1843 	MSIOF1_RXD_MARK,
1844 };
1845 
1846 /* - MSIOF2 ----------------------------------------------------------------- */
1847 static const unsigned int msiof2_clk_pins[] = {
1848 	/* MSIOF2_SCK */
1849 	RCAR_GP_PIN(0, 17),
1850 };
1851 static const unsigned int msiof2_clk_mux[] = {
1852 	MSIOF2_SCK_MARK,
1853 };
1854 static const unsigned int msiof2_sync_pins[] = {
1855 	/* MSIOF2_SYNC */
1856 	RCAR_GP_PIN(0, 15),
1857 };
1858 static const unsigned int msiof2_sync_mux[] = {
1859 	MSIOF2_SYNC_MARK,
1860 };
1861 static const unsigned int msiof2_ss1_pins[] = {
1862 	/* MSIOF2_SS1 */
1863 	RCAR_GP_PIN(0, 14),
1864 };
1865 static const unsigned int msiof2_ss1_mux[] = {
1866 	MSIOF2_SS1_MARK,
1867 };
1868 static const unsigned int msiof2_ss2_pins[] = {
1869 	/* MSIOF2_SS2 */
1870 	RCAR_GP_PIN(0, 13),
1871 };
1872 static const unsigned int msiof2_ss2_mux[] = {
1873 	MSIOF2_SS2_MARK,
1874 };
1875 static const unsigned int msiof2_txd_pins[] = {
1876 	/* MSIOF2_TXD */
1877 	RCAR_GP_PIN(0, 16),
1878 };
1879 static const unsigned int msiof2_txd_mux[] = {
1880 	MSIOF2_TXD_MARK,
1881 };
1882 static const unsigned int msiof2_rxd_pins[] = {
1883 	/* MSIOF2_RXD */
1884 	RCAR_GP_PIN(0, 18),
1885 };
1886 static const unsigned int msiof2_rxd_mux[] = {
1887 	MSIOF2_RXD_MARK,
1888 };
1889 
1890 /* - MSIOF3 ----------------------------------------------------------------- */
1891 static const unsigned int msiof3_clk_pins[] = {
1892 	/* MSIOF3_SCK */
1893 	RCAR_GP_PIN(0, 3),
1894 };
1895 static const unsigned int msiof3_clk_mux[] = {
1896 	MSIOF3_SCK_MARK,
1897 };
1898 static const unsigned int msiof3_sync_pins[] = {
1899 	/* MSIOF3_SYNC */
1900 	RCAR_GP_PIN(0, 6),
1901 };
1902 static const unsigned int msiof3_sync_mux[] = {
1903 	MSIOF3_SYNC_MARK,
1904 };
1905 static const unsigned int msiof3_ss1_pins[] = {
1906 	/* MSIOF3_SS1 */
1907 	RCAR_GP_PIN(0, 1),
1908 };
1909 static const unsigned int msiof3_ss1_mux[] = {
1910 	MSIOF3_SS1_MARK,
1911 };
1912 static const unsigned int msiof3_ss2_pins[] = {
1913 	/* MSIOF3_SS2 */
1914 	RCAR_GP_PIN(0, 2),
1915 };
1916 static const unsigned int msiof3_ss2_mux[] = {
1917 	MSIOF3_SS2_MARK,
1918 };
1919 static const unsigned int msiof3_txd_pins[] = {
1920 	/* MSIOF3_TXD */
1921 	RCAR_GP_PIN(0, 4),
1922 };
1923 static const unsigned int msiof3_txd_mux[] = {
1924 	MSIOF3_TXD_MARK,
1925 };
1926 static const unsigned int msiof3_rxd_pins[] = {
1927 	/* MSIOF3_RXD */
1928 	RCAR_GP_PIN(0, 5),
1929 };
1930 static const unsigned int msiof3_rxd_mux[] = {
1931 	MSIOF3_RXD_MARK,
1932 };
1933 
1934 /* - MSIOF4 ----------------------------------------------------------------- */
1935 static const unsigned int msiof4_clk_pins[] = {
1936 	/* MSIOF4_SCK */
1937 	RCAR_GP_PIN(1, 25),
1938 };
1939 static const unsigned int msiof4_clk_mux[] = {
1940 	MSIOF4_SCK_MARK,
1941 };
1942 static const unsigned int msiof4_sync_pins[] = {
1943 	/* MSIOF4_SYNC */
1944 	RCAR_GP_PIN(1, 28),
1945 };
1946 static const unsigned int msiof4_sync_mux[] = {
1947 	MSIOF4_SYNC_MARK,
1948 };
1949 static const unsigned int msiof4_ss1_pins[] = {
1950 	/* MSIOF4_SS1 */
1951 	RCAR_GP_PIN(1, 23),
1952 };
1953 static const unsigned int msiof4_ss1_mux[] = {
1954 	MSIOF4_SS1_MARK,
1955 };
1956 static const unsigned int msiof4_ss2_pins[] = {
1957 	/* MSIOF4_SS2 */
1958 	RCAR_GP_PIN(1, 24),
1959 };
1960 static const unsigned int msiof4_ss2_mux[] = {
1961 	MSIOF4_SS2_MARK,
1962 };
1963 static const unsigned int msiof4_txd_pins[] = {
1964 	/* MSIOF4_TXD */
1965 	RCAR_GP_PIN(1, 26),
1966 };
1967 static const unsigned int msiof4_txd_mux[] = {
1968 	MSIOF4_TXD_MARK,
1969 };
1970 static const unsigned int msiof4_rxd_pins[] = {
1971 	/* MSIOF4_RXD */
1972 	RCAR_GP_PIN(1, 27),
1973 };
1974 static const unsigned int msiof4_rxd_mux[] = {
1975 	MSIOF4_RXD_MARK,
1976 };
1977 
1978 /* - MSIOF5 ----------------------------------------------------------------- */
1979 static const unsigned int msiof5_clk_pins[] = {
1980 	/* MSIOF5_SCK */
1981 	RCAR_GP_PIN(0, 11),
1982 };
1983 static const unsigned int msiof5_clk_mux[] = {
1984 	MSIOF5_SCK_MARK,
1985 };
1986 static const unsigned int msiof5_sync_pins[] = {
1987 	/* MSIOF5_SYNC */
1988 	RCAR_GP_PIN(0, 9),
1989 };
1990 static const unsigned int msiof5_sync_mux[] = {
1991 	MSIOF5_SYNC_MARK,
1992 };
1993 static const unsigned int msiof5_ss1_pins[] = {
1994 	/* MSIOF5_SS1 */
1995 	RCAR_GP_PIN(0, 8),
1996 };
1997 static const unsigned int msiof5_ss1_mux[] = {
1998 	MSIOF5_SS1_MARK,
1999 };
2000 static const unsigned int msiof5_ss2_pins[] = {
2001 	/* MSIOF5_SS2 */
2002 	RCAR_GP_PIN(0, 7),
2003 };
2004 static const unsigned int msiof5_ss2_mux[] = {
2005 	MSIOF5_SS2_MARK,
2006 };
2007 static const unsigned int msiof5_txd_pins[] = {
2008 	/* MSIOF5_TXD */
2009 	RCAR_GP_PIN(0, 10),
2010 };
2011 static const unsigned int msiof5_txd_mux[] = {
2012 	MSIOF5_TXD_MARK,
2013 };
2014 static const unsigned int msiof5_rxd_pins[] = {
2015 	/* MSIOF5_RXD */
2016 	RCAR_GP_PIN(0, 12),
2017 };
2018 static const unsigned int msiof5_rxd_mux[] = {
2019 	MSIOF5_RXD_MARK,
2020 };
2021 
2022 /* - PCIE ------------------------------------------------------------------- */
2023 static const unsigned int pcie0_clkreq_n_pins[] = {
2024 	/* PCIE0_CLKREQ_N */
2025 	RCAR_GP_PIN(4, 21),
2026 };
2027 
2028 static const unsigned int pcie0_clkreq_n_mux[] = {
2029 	PCIE0_CLKREQ_N_MARK,
2030 };
2031 
2032 static const unsigned int pcie1_clkreq_n_pins[] = {
2033 	/* PCIE1_CLKREQ_N */
2034 	RCAR_GP_PIN(4, 22),
2035 };
2036 
2037 static const unsigned int pcie1_clkreq_n_mux[] = {
2038 	PCIE1_CLKREQ_N_MARK,
2039 };
2040 
2041 /* - PWM0_A ------------------------------------------------------------------- */
2042 static const unsigned int pwm0_a_pins[] = {
2043 	/* PWM0_A */
2044 	RCAR_GP_PIN(1, 15),
2045 };
2046 static const unsigned int pwm0_a_mux[] = {
2047 	PWM0_A_MARK,
2048 };
2049 
2050 /* - PWM1_A ------------------------------------------------------------------- */
2051 static const unsigned int pwm1_a_pins[] = {
2052 	/* PWM1_A */
2053 	RCAR_GP_PIN(3, 13),
2054 };
2055 static const unsigned int pwm1_a_mux[] = {
2056 	PWM1_A_MARK,
2057 };
2058 
2059 /* - PWM1_B ------------------------------------------------------------------- */
2060 static const unsigned int pwm1_b_pins[] = {
2061 	/* PWM1_B */
2062 	RCAR_GP_PIN(2, 13),
2063 };
2064 static const unsigned int pwm1_b_mux[] = {
2065 	PWM1_B_MARK,
2066 };
2067 
2068 /* - PWM2_B ------------------------------------------------------------------- */
2069 static const unsigned int pwm2_b_pins[] = {
2070 	/* PWM2_B */
2071 	RCAR_GP_PIN(2, 14),
2072 };
2073 static const unsigned int pwm2_b_mux[] = {
2074 	PWM2_B_MARK,
2075 };
2076 
2077 /* - PWM3_A ------------------------------------------------------------------- */
2078 static const unsigned int pwm3_a_pins[] = {
2079 	/* PWM3_A */
2080 	RCAR_GP_PIN(1, 22),
2081 };
2082 static const unsigned int pwm3_a_mux[] = {
2083 	PWM3_A_MARK,
2084 };
2085 
2086 /* - PWM3_B ------------------------------------------------------------------- */
2087 static const unsigned int pwm3_b_pins[] = {
2088 	/* PWM3_B */
2089 	RCAR_GP_PIN(2, 15),
2090 };
2091 static const unsigned int pwm3_b_mux[] = {
2092 	PWM3_B_MARK,
2093 };
2094 
2095 /* - PWM4 ------------------------------------------------------------------- */
2096 static const unsigned int pwm4_pins[] = {
2097 	/* PWM4 */
2098 	RCAR_GP_PIN(2, 16),
2099 };
2100 static const unsigned int pwm4_mux[] = {
2101 	PWM4_MARK,
2102 };
2103 
2104 /* - PWM5 ------------------------------------------------------------------- */
2105 static const unsigned int pwm5_pins[] = {
2106 	/* PWM5 */
2107 	RCAR_GP_PIN(2, 17),
2108 };
2109 static const unsigned int pwm5_mux[] = {
2110 	PWM5_MARK,
2111 };
2112 
2113 /* - PWM6 ------------------------------------------------------------------- */
2114 static const unsigned int pwm6_pins[] = {
2115 	/* PWM6 */
2116 	RCAR_GP_PIN(2, 18),
2117 };
2118 static const unsigned int pwm6_mux[] = {
2119 	PWM6_MARK,
2120 };
2121 
2122 /* - PWM7 ------------------------------------------------------------------- */
2123 static const unsigned int pwm7_pins[] = {
2124 	/* PWM7 */
2125 	RCAR_GP_PIN(2, 19),
2126 };
2127 static const unsigned int pwm7_mux[] = {
2128 	PWM7_MARK,
2129 };
2130 
2131 /* - PWM8_A ------------------------------------------------------------------- */
2132 static const unsigned int pwm8_a_pins[] = {
2133 	/* PWM8_A */
2134 	RCAR_GP_PIN(1, 13),
2135 };
2136 static const unsigned int pwm8_a_mux[] = {
2137 	PWM8_A_MARK,
2138 };
2139 
2140 /* - PWM9_A ------------------------------------------------------------------- */
2141 static const unsigned int pwm9_a_pins[] = {
2142 	/* PWM9_A */
2143 	RCAR_GP_PIN(1, 14),
2144 };
2145 static const unsigned int pwm9_a_mux[] = {
2146 	PWM9_A_MARK,
2147 };
2148 
2149 /* - QSPI0 ------------------------------------------------------------------ */
2150 static const unsigned int qspi0_ctrl_pins[] = {
2151 	/* SPCLK, SSL */
2152 	RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 15),
2153 };
2154 static const unsigned int qspi0_ctrl_mux[] = {
2155 	QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
2156 };
2157 static const unsigned int qspi0_data_pins[] = {
2158 	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
2159 	RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
2160 	RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
2161 };
2162 static const unsigned int qspi0_data_mux[] = {
2163 	QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
2164 	QSPI0_IO2_MARK, QSPI0_IO3_MARK
2165 };
2166 
2167 /* - QSPI1 ------------------------------------------------------------------ */
2168 static const unsigned int qspi1_ctrl_pins[] = {
2169 	/* SPCLK, SSL */
2170 	RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 25),
2171 };
2172 static const unsigned int qspi1_ctrl_mux[] = {
2173 	QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
2174 };
2175 static const unsigned int qspi1_data_pins[] = {
2176 	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
2177 	RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 23),
2178 	RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 26),
2179 };
2180 static const unsigned int qspi1_data_mux[] = {
2181 	QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
2182 	QSPI1_IO2_MARK, QSPI1_IO3_MARK
2183 };
2184 
2185 /* - SCIF0 ------------------------------------------------------------------ */
2186 static const unsigned int scif0_data_pins[] = {
2187 	/* RX0, TX0 */
2188 	RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12),
2189 };
2190 static const unsigned int scif0_data_mux[] = {
2191 	RX0_MARK, TX0_MARK,
2192 };
2193 static const unsigned int scif0_clk_pins[] = {
2194 	/* SCK0 */
2195 	RCAR_GP_PIN(1, 15),
2196 };
2197 static const unsigned int scif0_clk_mux[] = {
2198 	SCK0_MARK,
2199 };
2200 static const unsigned int scif0_ctrl_pins[] = {
2201 	/* RTS0_N, CTS0_N */
2202 	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2203 };
2204 static const unsigned int scif0_ctrl_mux[] = {
2205 	RTS0_N_MARK, CTS0_N_MARK,
2206 };
2207 
2208 /* - SCIF1 ------------------------------------------------------------------ */
2209 static const unsigned int scif1_data_pins[] = {
2210 	/* RX1, TX1 */
2211 	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2212 };
2213 static const unsigned int scif1_data_mux[] = {
2214 	RX1_MARK, TX1_MARK,
2215 };
2216 static const unsigned int scif1_clk_pins[] = {
2217 	/* SCK1 */
2218 	RCAR_GP_PIN(0, 18),
2219 };
2220 static const unsigned int scif1_clk_mux[] = {
2221 	SCK1_MARK,
2222 };
2223 static const unsigned int scif1_ctrl_pins[] = {
2224 	/* RTS1_N, CTS1_N */
2225 	RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
2226 };
2227 static const unsigned int scif1_ctrl_mux[] = {
2228 	RTS1_N_MARK, CTS1_N_MARK,
2229 };
2230 
2231 /* - SCIF1_X ------------------------------------------------------------------ */
2232 static const unsigned int scif1_data_x_pins[] = {
2233 	/* RX1_X, TX1_X */
2234 	RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
2235 };
2236 static const unsigned int scif1_data_x_mux[] = {
2237 	RX1_X_MARK, TX1_X_MARK,
2238 };
2239 static const unsigned int scif1_clk_x_pins[] = {
2240 	/* SCK1_X */
2241 	RCAR_GP_PIN(1, 10),
2242 };
2243 static const unsigned int scif1_clk_x_mux[] = {
2244 	SCK1_X_MARK,
2245 };
2246 static const unsigned int scif1_ctrl_x_pins[] = {
2247 	/* RTS1_N_X, CTS1_N_X */
2248 	RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
2249 };
2250 static const unsigned int scif1_ctrl_x_mux[] = {
2251 	RTS1_N_X_MARK, CTS1_N_X_MARK,
2252 };
2253 
2254 /* - SCIF3 ------------------------------------------------------------------ */
2255 static const unsigned int scif3_data_pins[] = {
2256 	/* RX3, TX3 */
2257 	RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2258 };
2259 static const unsigned int scif3_data_mux[] = {
2260 	RX3_MARK, TX3_MARK,
2261 };
2262 static const unsigned int scif3_clk_pins[] = {
2263 	/* SCK3 */
2264 	RCAR_GP_PIN(1, 4),
2265 };
2266 static const unsigned int scif3_clk_mux[] = {
2267 	SCK3_MARK,
2268 };
2269 static const unsigned int scif3_ctrl_pins[] = {
2270 	/* RTS3_N, CTS3_N */
2271 	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
2272 };
2273 static const unsigned int scif3_ctrl_mux[] = {
2274 	RTS3_N_MARK, CTS3_N_MARK,
2275 };
2276 
2277 /* - SCIF3_A ------------------------------------------------------------------ */
2278 static const unsigned int scif3_data_a_pins[] = {
2279 	/* RX3_A, TX3_A */
2280 	RCAR_GP_PIN(1, 27), RCAR_GP_PIN(1, 28),
2281 };
2282 static const unsigned int scif3_data_a_mux[] = {
2283 	RX3_A_MARK, TX3_A_MARK,
2284 };
2285 static const unsigned int scif3_clk_a_pins[] = {
2286 	/* SCK3_A */
2287 	RCAR_GP_PIN(1, 24),
2288 };
2289 static const unsigned int scif3_clk_a_mux[] = {
2290 	SCK3_A_MARK,
2291 };
2292 static const unsigned int scif3_ctrl_a_pins[] = {
2293 	/* RTS3_N_A, CTS3_N_A */
2294 	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2295 };
2296 static const unsigned int scif3_ctrl_a_mux[] = {
2297 	RTS3_N_A_MARK, CTS3_N_A_MARK,
2298 };
2299 
2300 /* - SCIF4 ------------------------------------------------------------------ */
2301 static const unsigned int scif4_data_pins[] = {
2302 	/* RX4, TX4 */
2303 	RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 12),
2304 };
2305 static const unsigned int scif4_data_mux[] = {
2306 	RX4_MARK, TX4_MARK,
2307 };
2308 static const unsigned int scif4_clk_pins[] = {
2309 	/* SCK4 */
2310 	RCAR_GP_PIN(8, 8),
2311 };
2312 static const unsigned int scif4_clk_mux[] = {
2313 	SCK4_MARK,
2314 };
2315 static const unsigned int scif4_ctrl_pins[] = {
2316 	/* RTS4_N, CTS4_N */
2317 	RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 9),
2318 };
2319 static const unsigned int scif4_ctrl_mux[] = {
2320 	RTS4_N_MARK, CTS4_N_MARK,
2321 };
2322 
2323 /* - SCIF Clock ------------------------------------------------------------- */
2324 static const unsigned int scif_clk_pins[] = {
2325 	/* SCIF_CLK */
2326 	RCAR_GP_PIN(1, 17),
2327 };
2328 static const unsigned int scif_clk_mux[] = {
2329 	SCIF_CLK_MARK,
2330 };
2331 
2332 /* - TPU ------------------------------------------------------------------- */
2333 static const unsigned int tpu_to0_pins[] = {
2334 	/* TPU0TO0 */
2335 	RCAR_GP_PIN(2, 8),
2336 };
2337 static const unsigned int tpu_to0_mux[] = {
2338 	TPU0TO0_MARK,
2339 };
2340 static const unsigned int tpu_to1_pins[] = {
2341 	/* TPU0TO1 */
2342 	RCAR_GP_PIN(2, 7),
2343 };
2344 static const unsigned int tpu_to1_mux[] = {
2345 	TPU0TO1_MARK,
2346 };
2347 static const unsigned int tpu_to2_pins[] = {
2348 	/* TPU0TO2 */
2349 	RCAR_GP_PIN(2, 12),
2350 };
2351 static const unsigned int tpu_to2_mux[] = {
2352 	TPU0TO2_MARK,
2353 };
2354 static const unsigned int tpu_to3_pins[] = {
2355 	/* TPU0TO3 */
2356 	RCAR_GP_PIN(2, 13),
2357 };
2358 static const unsigned int tpu_to3_mux[] = {
2359 	TPU0TO3_MARK,
2360 };
2361 
2362 /* - TPU_A ------------------------------------------------------------------- */
2363 static const unsigned int tpu_to0_a_pins[] = {
2364 	/* TPU0TO0_A */
2365 	RCAR_GP_PIN(1, 25),
2366 };
2367 static const unsigned int tpu_to0_a_mux[] = {
2368 	TPU0TO0_A_MARK,
2369 };
2370 static const unsigned int tpu_to1_a_pins[] = {
2371 	/* TPU0TO1_A */
2372 	RCAR_GP_PIN(1, 26),
2373 };
2374 static const unsigned int tpu_to1_a_mux[] = {
2375 	TPU0TO1_A_MARK,
2376 };
2377 static const unsigned int tpu_to2_a_pins[] = {
2378 	/* TPU0TO2_A */
2379 	RCAR_GP_PIN(2, 0),
2380 };
2381 static const unsigned int tpu_to2_a_mux[] = {
2382 	TPU0TO2_A_MARK,
2383 };
2384 static const unsigned int tpu_to3_a_pins[] = {
2385 	/* TPU0TO3_A */
2386 	RCAR_GP_PIN(2, 1),
2387 };
2388 static const unsigned int tpu_to3_a_mux[] = {
2389 	TPU0TO3_A_MARK,
2390 };
2391 
2392 /* - TSN0 ------------------------------------------------ */
2393 static const unsigned int tsn0_link_pins[] = {
2394 	/* TSN0_LINK */
2395 	RCAR_GP_PIN(4, 4),
2396 };
2397 static const unsigned int tsn0_link_mux[] = {
2398 	TSN0_LINK_MARK,
2399 };
2400 static const unsigned int tsn0_phy_int_pins[] = {
2401 	/* TSN0_PHY_INT */
2402 	RCAR_GP_PIN(4, 3),
2403 };
2404 static const unsigned int tsn0_phy_int_mux[] = {
2405 	TSN0_PHY_INT_MARK,
2406 };
2407 static const unsigned int tsn0_mdio_pins[] = {
2408 	/* TSN0_MDC, TSN0_MDIO */
2409 	RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
2410 };
2411 static const unsigned int tsn0_mdio_mux[] = {
2412 	TSN0_MDC_MARK, TSN0_MDIO_MARK,
2413 };
2414 static const unsigned int tsn0_rgmii_pins[] = {
2415 	/*
2416 	 * TSN0_TX_CTL, TSN0_TXC, TSN0_TD0, TSN0_TD1, TSN0_TD2, TSN0_TD3,
2417 	 * TSN0_RX_CTL, TSN0_RXC, TSN0_RD0, TSN0_RD1, TSN0_RD2, TSN0_RD3,
2418 	 */
2419 	RCAR_GP_PIN(4,  9), RCAR_GP_PIN(4, 12),
2420 	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14),
2421 	RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
2422 	RCAR_GP_PIN(4,  7), RCAR_GP_PIN(4, 11),
2423 	RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 13),
2424 	RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
2425 };
2426 static const unsigned int tsn0_rgmii_mux[] = {
2427 	TSN0_TX_CTL_MARK,	TSN0_TXC_MARK,
2428 	TSN0_TD0_MARK,		TSN0_TD1_MARK,
2429 	TSN0_TD2_MARK,		TSN0_TD3_MARK,
2430 	TSN0_RX_CTL_MARK,	TSN0_RXC_MARK,
2431 	TSN0_RD0_MARK,		TSN0_RD1_MARK,
2432 	TSN0_RD2_MARK,		TSN0_RD3_MARK,
2433 };
2434 static const unsigned int tsn0_txcrefclk_pins[] = {
2435 	/* TSN0_TXCREFCLK */
2436 	RCAR_GP_PIN(4, 20),
2437 };
2438 static const unsigned int tsn0_txcrefclk_mux[] = {
2439 	TSN0_TXCREFCLK_MARK,
2440 };
2441 static const unsigned int tsn0_avtp_pps_pins[] = {
2442 	/* TSN0_AVTP_PPS0, TSN0_AVTP_PPS1 */
2443 	RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 2),
2444 };
2445 static const unsigned int tsn0_avtp_pps_mux[] = {
2446 	TSN0_AVTP_PPS0_MARK, TSN0_AVTP_PPS1_MARK,
2447 };
2448 static const unsigned int tsn0_avtp_capture_pins[] = {
2449 	/* TSN0_AVTP_CAPTURE */
2450 	RCAR_GP_PIN(4, 6),
2451 };
2452 static const unsigned int tsn0_avtp_capture_mux[] = {
2453 	TSN0_AVTP_CAPTURE_MARK,
2454 };
2455 static const unsigned int tsn0_avtp_match_pins[] = {
2456 	/* TSN0_AVTP_MATCH */
2457 	RCAR_GP_PIN(4, 5),
2458 };
2459 static const unsigned int tsn0_avtp_match_mux[] = {
2460 	TSN0_AVTP_MATCH_MARK,
2461 };
2462 
2463 static const struct sh_pfc_pin_group pinmux_groups[] = {
2464 	SH_PFC_PIN_GROUP(avb0_link),
2465 	SH_PFC_PIN_GROUP(avb0_magic),
2466 	SH_PFC_PIN_GROUP(avb0_phy_int),
2467 	SH_PFC_PIN_GROUP(avb0_mdio),
2468 	SH_PFC_PIN_GROUP(avb0_rgmii),
2469 	SH_PFC_PIN_GROUP(avb0_txcrefclk),
2470 	SH_PFC_PIN_GROUP(avb0_avtp_pps),
2471 	SH_PFC_PIN_GROUP(avb0_avtp_capture),
2472 	SH_PFC_PIN_GROUP(avb0_avtp_match),
2473 
2474 	SH_PFC_PIN_GROUP(avb1_link),
2475 	SH_PFC_PIN_GROUP(avb1_magic),
2476 	SH_PFC_PIN_GROUP(avb1_phy_int),
2477 	SH_PFC_PIN_GROUP(avb1_mdio),
2478 	SH_PFC_PIN_GROUP(avb1_rgmii),
2479 	SH_PFC_PIN_GROUP(avb1_txcrefclk),
2480 	SH_PFC_PIN_GROUP(avb1_avtp_pps),
2481 	SH_PFC_PIN_GROUP(avb1_avtp_capture),
2482 	SH_PFC_PIN_GROUP(avb1_avtp_match),
2483 
2484 	SH_PFC_PIN_GROUP(avb2_link),
2485 	SH_PFC_PIN_GROUP(avb2_magic),
2486 	SH_PFC_PIN_GROUP(avb2_phy_int),
2487 	SH_PFC_PIN_GROUP(avb2_mdio),
2488 	SH_PFC_PIN_GROUP(avb2_rgmii),
2489 	SH_PFC_PIN_GROUP(avb2_txcrefclk),
2490 	SH_PFC_PIN_GROUP(avb2_avtp_pps),
2491 	SH_PFC_PIN_GROUP(avb2_avtp_capture),
2492 	SH_PFC_PIN_GROUP(avb2_avtp_match),
2493 
2494 	SH_PFC_PIN_GROUP(canfd0_data),
2495 	SH_PFC_PIN_GROUP(canfd1_data),
2496 	SH_PFC_PIN_GROUP(canfd2_data),
2497 	SH_PFC_PIN_GROUP(canfd3_data),
2498 	SH_PFC_PIN_GROUP(canfd4_data),
2499 	SH_PFC_PIN_GROUP(canfd5_data),		/* suffix might be updated */
2500 	SH_PFC_PIN_GROUP(canfd5_data_b),	/* suffix might be updated */
2501 	SH_PFC_PIN_GROUP(canfd6_data),
2502 	SH_PFC_PIN_GROUP(canfd7_data),
2503 	SH_PFC_PIN_GROUP(can_clk),
2504 
2505 	SH_PFC_PIN_GROUP(hscif0_data),
2506 	SH_PFC_PIN_GROUP(hscif0_clk),
2507 	SH_PFC_PIN_GROUP(hscif0_ctrl),
2508 	SH_PFC_PIN_GROUP(hscif1_data),		/* suffix might be updated */
2509 	SH_PFC_PIN_GROUP(hscif1_clk),		/* suffix might be updated */
2510 	SH_PFC_PIN_GROUP(hscif1_ctrl),		/* suffix might be updated */
2511 	SH_PFC_PIN_GROUP(hscif1_data_x),	/* suffix might be updated */
2512 	SH_PFC_PIN_GROUP(hscif1_clk_x),		/* suffix might be updated */
2513 	SH_PFC_PIN_GROUP(hscif1_ctrl_x),	/* suffix might be updated */
2514 	SH_PFC_PIN_GROUP(hscif2_data),
2515 	SH_PFC_PIN_GROUP(hscif2_clk),
2516 	SH_PFC_PIN_GROUP(hscif2_ctrl),
2517 	SH_PFC_PIN_GROUP(hscif3_data),		/* suffix might be updated */
2518 	SH_PFC_PIN_GROUP(hscif3_clk),		/* suffix might be updated */
2519 	SH_PFC_PIN_GROUP(hscif3_ctrl),		/* suffix might be updated */
2520 	SH_PFC_PIN_GROUP(hscif3_data_a),	/* suffix might be updated */
2521 	SH_PFC_PIN_GROUP(hscif3_clk_a),		/* suffix might be updated */
2522 	SH_PFC_PIN_GROUP(hscif3_ctrl_a),	/* suffix might be updated */
2523 
2524 	SH_PFC_PIN_GROUP(i2c0),
2525 	SH_PFC_PIN_GROUP(i2c1),
2526 	SH_PFC_PIN_GROUP(i2c2),
2527 	SH_PFC_PIN_GROUP(i2c3),
2528 	SH_PFC_PIN_GROUP(i2c4),
2529 	SH_PFC_PIN_GROUP(i2c5),
2530 
2531 	BUS_DATA_PIN_GROUP(mmc_data, 1),
2532 	BUS_DATA_PIN_GROUP(mmc_data, 4),
2533 	BUS_DATA_PIN_GROUP(mmc_data, 8),
2534 	SH_PFC_PIN_GROUP(mmc_ctrl),
2535 	SH_PFC_PIN_GROUP(mmc_cd),
2536 	SH_PFC_PIN_GROUP(mmc_wp),
2537 	SH_PFC_PIN_GROUP(mmc_ds),
2538 
2539 	SH_PFC_PIN_GROUP(msiof0_clk),
2540 	SH_PFC_PIN_GROUP(msiof0_sync),
2541 	SH_PFC_PIN_GROUP(msiof0_ss1),
2542 	SH_PFC_PIN_GROUP(msiof0_ss2),
2543 	SH_PFC_PIN_GROUP(msiof0_txd),
2544 	SH_PFC_PIN_GROUP(msiof0_rxd),
2545 
2546 	SH_PFC_PIN_GROUP(msiof1_clk),
2547 	SH_PFC_PIN_GROUP(msiof1_sync),
2548 	SH_PFC_PIN_GROUP(msiof1_ss1),
2549 	SH_PFC_PIN_GROUP(msiof1_ss2),
2550 	SH_PFC_PIN_GROUP(msiof1_txd),
2551 	SH_PFC_PIN_GROUP(msiof1_rxd),
2552 
2553 	SH_PFC_PIN_GROUP(msiof2_clk),
2554 	SH_PFC_PIN_GROUP(msiof2_sync),
2555 	SH_PFC_PIN_GROUP(msiof2_ss1),
2556 	SH_PFC_PIN_GROUP(msiof2_ss2),
2557 	SH_PFC_PIN_GROUP(msiof2_txd),
2558 	SH_PFC_PIN_GROUP(msiof2_rxd),
2559 
2560 	SH_PFC_PIN_GROUP(msiof3_clk),
2561 	SH_PFC_PIN_GROUP(msiof3_sync),
2562 	SH_PFC_PIN_GROUP(msiof3_ss1),
2563 	SH_PFC_PIN_GROUP(msiof3_ss2),
2564 	SH_PFC_PIN_GROUP(msiof3_txd),
2565 	SH_PFC_PIN_GROUP(msiof3_rxd),
2566 
2567 	SH_PFC_PIN_GROUP(msiof4_clk),
2568 	SH_PFC_PIN_GROUP(msiof4_sync),
2569 	SH_PFC_PIN_GROUP(msiof4_ss1),
2570 	SH_PFC_PIN_GROUP(msiof4_ss2),
2571 	SH_PFC_PIN_GROUP(msiof4_txd),
2572 	SH_PFC_PIN_GROUP(msiof4_rxd),
2573 
2574 	SH_PFC_PIN_GROUP(msiof5_clk),
2575 	SH_PFC_PIN_GROUP(msiof5_sync),
2576 	SH_PFC_PIN_GROUP(msiof5_ss1),
2577 	SH_PFC_PIN_GROUP(msiof5_ss2),
2578 	SH_PFC_PIN_GROUP(msiof5_txd),
2579 	SH_PFC_PIN_GROUP(msiof5_rxd),
2580 
2581 	SH_PFC_PIN_GROUP(pcie0_clkreq_n),
2582 	SH_PFC_PIN_GROUP(pcie1_clkreq_n),
2583 
2584 	SH_PFC_PIN_GROUP(pwm0_a),		/* suffix might be updated */
2585 	SH_PFC_PIN_GROUP(pwm1_a),
2586 	SH_PFC_PIN_GROUP(pwm1_b),
2587 	SH_PFC_PIN_GROUP(pwm2_b),		/* suffix might be updated */
2588 	SH_PFC_PIN_GROUP(pwm3_a),
2589 	SH_PFC_PIN_GROUP(pwm3_b),
2590 	SH_PFC_PIN_GROUP(pwm4),
2591 	SH_PFC_PIN_GROUP(pwm5),
2592 	SH_PFC_PIN_GROUP(pwm6),
2593 	SH_PFC_PIN_GROUP(pwm7),
2594 	SH_PFC_PIN_GROUP(pwm8_a),		/* suffix might be updated */
2595 	SH_PFC_PIN_GROUP(pwm9_a),		/* suffix might be updated */
2596 
2597 	SH_PFC_PIN_GROUP(qspi0_ctrl),
2598 	BUS_DATA_PIN_GROUP(qspi0_data, 2),
2599 	BUS_DATA_PIN_GROUP(qspi0_data, 4),
2600 	SH_PFC_PIN_GROUP(qspi1_ctrl),
2601 	BUS_DATA_PIN_GROUP(qspi1_data, 2),
2602 	BUS_DATA_PIN_GROUP(qspi1_data, 4),
2603 
2604 	SH_PFC_PIN_GROUP(scif0_data),
2605 	SH_PFC_PIN_GROUP(scif0_clk),
2606 	SH_PFC_PIN_GROUP(scif0_ctrl),
2607 	SH_PFC_PIN_GROUP(scif1_data),		/* suffix might be updated */
2608 	SH_PFC_PIN_GROUP(scif1_clk),		/* suffix might be updated */
2609 	SH_PFC_PIN_GROUP(scif1_ctrl),		/* suffix might be updated */
2610 	SH_PFC_PIN_GROUP(scif1_data_x),		/* suffix might be updated */
2611 	SH_PFC_PIN_GROUP(scif1_clk_x),		/* suffix might be updated */
2612 	SH_PFC_PIN_GROUP(scif1_ctrl_x),		/* suffix might be updated */
2613 	SH_PFC_PIN_GROUP(scif3_data),		/* suffix might be updated */
2614 	SH_PFC_PIN_GROUP(scif3_clk),		/* suffix might be updated */
2615 	SH_PFC_PIN_GROUP(scif3_ctrl),		/* suffix might be updated */
2616 	SH_PFC_PIN_GROUP(scif3_data_a),		/* suffix might be updated */
2617 	SH_PFC_PIN_GROUP(scif3_clk_a),		/* suffix might be updated */
2618 	SH_PFC_PIN_GROUP(scif3_ctrl_a),		/* suffix might be updated */
2619 	SH_PFC_PIN_GROUP(scif4_data),
2620 	SH_PFC_PIN_GROUP(scif4_clk),
2621 	SH_PFC_PIN_GROUP(scif4_ctrl),
2622 	SH_PFC_PIN_GROUP(scif_clk),
2623 
2624 	SH_PFC_PIN_GROUP(tpu_to0),		/* suffix might be updated */
2625 	SH_PFC_PIN_GROUP(tpu_to0_a),		/* suffix might be updated */
2626 	SH_PFC_PIN_GROUP(tpu_to1),		/* suffix might be updated */
2627 	SH_PFC_PIN_GROUP(tpu_to1_a),		/* suffix might be updated */
2628 	SH_PFC_PIN_GROUP(tpu_to2),		/* suffix might be updated */
2629 	SH_PFC_PIN_GROUP(tpu_to2_a),		/* suffix might be updated */
2630 	SH_PFC_PIN_GROUP(tpu_to3),		/* suffix might be updated */
2631 	SH_PFC_PIN_GROUP(tpu_to3_a),		/* suffix might be updated */
2632 
2633 	SH_PFC_PIN_GROUP(tsn0_link),
2634 	SH_PFC_PIN_GROUP(tsn0_phy_int),
2635 	SH_PFC_PIN_GROUP(tsn0_mdio),
2636 	SH_PFC_PIN_GROUP(tsn0_rgmii),
2637 	SH_PFC_PIN_GROUP(tsn0_txcrefclk),
2638 	SH_PFC_PIN_GROUP(tsn0_avtp_pps),
2639 	SH_PFC_PIN_GROUP(tsn0_avtp_capture),
2640 	SH_PFC_PIN_GROUP(tsn0_avtp_match),
2641 };
2642 
2643 static const char * const avb0_groups[] = {
2644 	"avb0_link",
2645 	"avb0_magic",
2646 	"avb0_phy_int",
2647 	"avb0_mdio",
2648 	"avb0_rgmii",
2649 	"avb0_txcrefclk",
2650 	"avb0_avtp_pps",
2651 	"avb0_avtp_capture",
2652 	"avb0_avtp_match",
2653 };
2654 
2655 static const char * const avb1_groups[] = {
2656 	"avb1_link",
2657 	"avb1_magic",
2658 	"avb1_phy_int",
2659 	"avb1_mdio",
2660 	"avb1_rgmii",
2661 	"avb1_txcrefclk",
2662 	"avb1_avtp_pps",
2663 	"avb1_avtp_capture",
2664 	"avb1_avtp_match",
2665 };
2666 
2667 static const char * const avb2_groups[] = {
2668 	"avb2_link",
2669 	"avb2_magic",
2670 	"avb2_phy_int",
2671 	"avb2_mdio",
2672 	"avb2_rgmii",
2673 	"avb2_txcrefclk",
2674 	"avb2_avtp_pps",
2675 	"avb2_avtp_capture",
2676 	"avb2_avtp_match",
2677 };
2678 
2679 static const char * const canfd0_groups[] = {
2680 	"canfd0_data",
2681 };
2682 
2683 static const char * const canfd1_groups[] = {
2684 	"canfd1_data",
2685 };
2686 
2687 static const char * const canfd2_groups[] = {
2688 	"canfd2_data",
2689 };
2690 
2691 static const char * const canfd3_groups[] = {
2692 	"canfd3_data",
2693 };
2694 
2695 static const char * const canfd4_groups[] = {
2696 	"canfd4_data",
2697 };
2698 
2699 static const char * const canfd5_groups[] = {
2700 	/* suffix might be updated */
2701 	"canfd5_data",
2702 	"canfd5_data_b",
2703 };
2704 
2705 static const char * const canfd6_groups[] = {
2706 	"canfd6_data",
2707 };
2708 
2709 static const char * const canfd7_groups[] = {
2710 	"canfd7_data",
2711 };
2712 
2713 static const char * const can_clk_groups[] = {
2714 	"can_clk",
2715 };
2716 
2717 static const char * const hscif0_groups[] = {
2718 	"hscif0_data",
2719 	"hscif0_clk",
2720 	"hscif0_ctrl",
2721 };
2722 
2723 static const char * const hscif1_groups[] = {
2724 	/* suffix might be updated */
2725 	"hscif1_data",
2726 	"hscif1_clk",
2727 	"hscif1_ctrl",
2728 	"hscif1_data_x",
2729 	"hscif1_clk_x",
2730 	"hscif1_ctrl_x",
2731 };
2732 
2733 static const char * const hscif2_groups[] = {
2734 	"hscif2_data",
2735 	"hscif2_clk",
2736 	"hscif2_ctrl",
2737 };
2738 
2739 static const char * const hscif3_groups[] = {
2740 	/* suffix might be updated */
2741 	"hscif3_data",
2742 	"hscif3_clk",
2743 	"hscif3_ctrl",
2744 	"hscif3_data_a",
2745 	"hscif3_clk_a",
2746 	"hscif3_ctrl_a",
2747 };
2748 
2749 static const char * const i2c0_groups[] = {
2750 	"i2c0",
2751 };
2752 
2753 static const char * const i2c1_groups[] = {
2754 	"i2c1",
2755 };
2756 
2757 static const char * const i2c2_groups[] = {
2758 	"i2c2",
2759 };
2760 
2761 static const char * const i2c3_groups[] = {
2762 	"i2c3",
2763 };
2764 
2765 static const char * const i2c4_groups[] = {
2766 	"i2c4",
2767 };
2768 
2769 static const char * const i2c5_groups[] = {
2770 	"i2c5",
2771 };
2772 
2773 static const char * const mmc_groups[] = {
2774 	"mmc_data1",
2775 	"mmc_data4",
2776 	"mmc_data8",
2777 	"mmc_ctrl",
2778 	"mmc_cd",
2779 	"mmc_wp",
2780 	"mmc_ds",
2781 };
2782 
2783 static const char * const msiof0_groups[] = {
2784 	"msiof0_clk",
2785 	"msiof0_sync",
2786 	"msiof0_ss1",
2787 	"msiof0_ss2",
2788 	"msiof0_txd",
2789 	"msiof0_rxd",
2790 };
2791 
2792 static const char * const msiof1_groups[] = {
2793 	"msiof1_clk",
2794 	"msiof1_sync",
2795 	"msiof1_ss1",
2796 	"msiof1_ss2",
2797 	"msiof1_txd",
2798 	"msiof1_rxd",
2799 };
2800 
2801 static const char * const msiof2_groups[] = {
2802 	"msiof2_clk",
2803 	"msiof2_sync",
2804 	"msiof2_ss1",
2805 	"msiof2_ss2",
2806 	"msiof2_txd",
2807 	"msiof2_rxd",
2808 };
2809 
2810 static const char * const msiof3_groups[] = {
2811 	"msiof3_clk",
2812 	"msiof3_sync",
2813 	"msiof3_ss1",
2814 	"msiof3_ss2",
2815 	"msiof3_txd",
2816 	"msiof3_rxd",
2817 };
2818 
2819 static const char * const msiof4_groups[] = {
2820 	"msiof4_clk",
2821 	"msiof4_sync",
2822 	"msiof4_ss1",
2823 	"msiof4_ss2",
2824 	"msiof4_txd",
2825 	"msiof4_rxd",
2826 };
2827 
2828 static const char * const msiof5_groups[] = {
2829 	"msiof5_clk",
2830 	"msiof5_sync",
2831 	"msiof5_ss1",
2832 	"msiof5_ss2",
2833 	"msiof5_txd",
2834 	"msiof5_rxd",
2835 };
2836 
2837 static const char * const pcie_groups[] = {
2838 	"pcie0_clkreq_n",
2839 	"pcie1_clkreq_n",
2840 };
2841 
2842 static const char * const pwm0_groups[] = {
2843 	/* suffix might be updated */
2844 	"pwm0_a",
2845 };
2846 
2847 static const char * const pwm1_groups[] = {
2848 	"pwm1_a",
2849 	"pwm1_b",
2850 };
2851 
2852 static const char * const pwm2_groups[] = {
2853 	/* suffix might be updated */
2854 	"pwm2_b",
2855 };
2856 
2857 static const char * const pwm3_groups[] = {
2858 	"pwm3_a",
2859 	"pwm3_b",
2860 };
2861 
2862 static const char * const pwm4_groups[] = {
2863 	"pwm4",
2864 };
2865 
2866 static const char * const pwm5_groups[] = {
2867 	"pwm5",
2868 };
2869 
2870 static const char * const pwm6_groups[] = {
2871 	"pwm6",
2872 };
2873 
2874 static const char * const pwm7_groups[] = {
2875 	"pwm7",
2876 };
2877 
2878 static const char * const pwm8_groups[] = {
2879 	/* suffix might be updated */
2880 	"pwm8_a",
2881 };
2882 
2883 static const char * const pwm9_groups[] = {
2884 	/* suffix might be updated */
2885 	"pwm9_a",
2886 };
2887 
2888 static const char * const qspi0_groups[] = {
2889 	"qspi0_ctrl",
2890 	"qspi0_data2",
2891 	"qspi0_data4",
2892 };
2893 
2894 static const char * const qspi1_groups[] = {
2895 	"qspi1_ctrl",
2896 	"qspi1_data2",
2897 	"qspi1_data4",
2898 };
2899 
2900 static const char * const scif0_groups[] = {
2901 	"scif0_data",
2902 	"scif0_clk",
2903 	"scif0_ctrl",
2904 };
2905 
2906 static const char * const scif1_groups[] = {
2907 	/* suffix might be updated */
2908 	"scif1_data",
2909 	"scif1_clk",
2910 	"scif1_ctrl",
2911 	"scif1_data_x",
2912 	"scif1_clk_x",
2913 	"scif1_ctrl_x",
2914 };
2915 
2916 static const char * const scif3_groups[] = {
2917 	/* suffix might be updated */
2918 	"scif3_data",
2919 	"scif3_clk",
2920 	"scif3_ctrl",
2921 	"scif3_data_a",
2922 	"scif3_clk_a",
2923 	"scif3_ctrl_a",
2924 };
2925 
2926 static const char * const scif4_groups[] = {
2927 	"scif4_data",
2928 	"scif4_clk",
2929 	"scif4_ctrl",
2930 };
2931 
2932 static const char * const scif_clk_groups[] = {
2933 	"scif_clk",
2934 };
2935 
2936 static const char * const tpu_groups[] = {
2937 	/* suffix might be updated */
2938 	"tpu_to0",
2939 	"tpu_to0_a",
2940 	"tpu_to1",
2941 	"tpu_to1_a",
2942 	"tpu_to2",
2943 	"tpu_to2_a",
2944 	"tpu_to3",
2945 	"tpu_to3_a",
2946 };
2947 
2948 static const char * const tsn0_groups[] = {
2949 	"tsn0_link",
2950 	"tsn0_phy_int",
2951 	"tsn0_mdio",
2952 	"tsn0_rgmii",
2953 	"tsn0_txcrefclk",
2954 	"tsn0_avtp_pps",
2955 	"tsn0_avtp_capture",
2956 	"tsn0_avtp_match",
2957 };
2958 
2959 static const struct sh_pfc_function pinmux_functions[] = {
2960 	SH_PFC_FUNCTION(avb0),
2961 	SH_PFC_FUNCTION(avb1),
2962 	SH_PFC_FUNCTION(avb2),
2963 
2964 	SH_PFC_FUNCTION(canfd0),
2965 	SH_PFC_FUNCTION(canfd1),
2966 	SH_PFC_FUNCTION(canfd2),
2967 	SH_PFC_FUNCTION(canfd3),
2968 	SH_PFC_FUNCTION(canfd4),
2969 	SH_PFC_FUNCTION(canfd5),
2970 	SH_PFC_FUNCTION(canfd6),
2971 	SH_PFC_FUNCTION(canfd7),
2972 	SH_PFC_FUNCTION(can_clk),
2973 
2974 	SH_PFC_FUNCTION(hscif0),
2975 	SH_PFC_FUNCTION(hscif1),
2976 	SH_PFC_FUNCTION(hscif2),
2977 	SH_PFC_FUNCTION(hscif3),
2978 
2979 	SH_PFC_FUNCTION(i2c0),
2980 	SH_PFC_FUNCTION(i2c1),
2981 	SH_PFC_FUNCTION(i2c2),
2982 	SH_PFC_FUNCTION(i2c3),
2983 	SH_PFC_FUNCTION(i2c4),
2984 	SH_PFC_FUNCTION(i2c5),
2985 
2986 	SH_PFC_FUNCTION(mmc),
2987 
2988 	SH_PFC_FUNCTION(msiof0),
2989 	SH_PFC_FUNCTION(msiof1),
2990 	SH_PFC_FUNCTION(msiof2),
2991 	SH_PFC_FUNCTION(msiof3),
2992 	SH_PFC_FUNCTION(msiof4),
2993 	SH_PFC_FUNCTION(msiof5),
2994 
2995 	SH_PFC_FUNCTION(pcie),
2996 
2997 	SH_PFC_FUNCTION(pwm0),
2998 	SH_PFC_FUNCTION(pwm1),
2999 	SH_PFC_FUNCTION(pwm2),
3000 	SH_PFC_FUNCTION(pwm3),
3001 	SH_PFC_FUNCTION(pwm4),
3002 	SH_PFC_FUNCTION(pwm5),
3003 	SH_PFC_FUNCTION(pwm6),
3004 	SH_PFC_FUNCTION(pwm7),
3005 	SH_PFC_FUNCTION(pwm8),
3006 	SH_PFC_FUNCTION(pwm9),
3007 
3008 	SH_PFC_FUNCTION(qspi0),
3009 	SH_PFC_FUNCTION(qspi1),
3010 
3011 	SH_PFC_FUNCTION(scif0),
3012 	SH_PFC_FUNCTION(scif1),
3013 	SH_PFC_FUNCTION(scif3),
3014 	SH_PFC_FUNCTION(scif4),
3015 	SH_PFC_FUNCTION(scif_clk),
3016 
3017 	SH_PFC_FUNCTION(tpu),
3018 
3019 	SH_PFC_FUNCTION(tsn0),
3020 };
3021 
3022 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3023 #define F_(x, y)	FN_##y
3024 #define FM(x)		FN_##x
3025 	{ PINMUX_CFG_REG_VAR("GPSR0", 0xE6050040, 32,
3026 			     GROUP(-13, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3027 				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3028 			     GROUP(
3029 		/* GP0_31_19 RESERVED */
3030 		GP_0_18_FN,	GPSR0_18,
3031 		GP_0_17_FN,	GPSR0_17,
3032 		GP_0_16_FN,	GPSR0_16,
3033 		GP_0_15_FN,	GPSR0_15,
3034 		GP_0_14_FN,	GPSR0_14,
3035 		GP_0_13_FN,	GPSR0_13,
3036 		GP_0_12_FN,	GPSR0_12,
3037 		GP_0_11_FN,	GPSR0_11,
3038 		GP_0_10_FN,	GPSR0_10,
3039 		GP_0_9_FN,	GPSR0_9,
3040 		GP_0_8_FN,	GPSR0_8,
3041 		GP_0_7_FN,	GPSR0_7,
3042 		GP_0_6_FN,	GPSR0_6,
3043 		GP_0_5_FN,	GPSR0_5,
3044 		GP_0_4_FN,	GPSR0_4,
3045 		GP_0_3_FN,	GPSR0_3,
3046 		GP_0_2_FN,	GPSR0_2,
3047 		GP_0_1_FN,	GPSR0_1,
3048 		GP_0_0_FN,	GPSR0_0, ))
3049 	},
3050 	{ PINMUX_CFG_REG("GPSR1", 0xE6050840, 32, 1, GROUP(
3051 		0, 0,
3052 		0, 0,
3053 		0, 0,
3054 		GP_1_28_FN,	GPSR1_28,
3055 		GP_1_27_FN,	GPSR1_27,
3056 		GP_1_26_FN,	GPSR1_26,
3057 		GP_1_25_FN,	GPSR1_25,
3058 		GP_1_24_FN,	GPSR1_24,
3059 		GP_1_23_FN,	GPSR1_23,
3060 		GP_1_22_FN,	GPSR1_22,
3061 		GP_1_21_FN,	GPSR1_21,
3062 		GP_1_20_FN,	GPSR1_20,
3063 		GP_1_19_FN,	GPSR1_19,
3064 		GP_1_18_FN,	GPSR1_18,
3065 		GP_1_17_FN,	GPSR1_17,
3066 		GP_1_16_FN,	GPSR1_16,
3067 		GP_1_15_FN,	GPSR1_15,
3068 		GP_1_14_FN,	GPSR1_14,
3069 		GP_1_13_FN,	GPSR1_13,
3070 		GP_1_12_FN,	GPSR1_12,
3071 		GP_1_11_FN,	GPSR1_11,
3072 		GP_1_10_FN,	GPSR1_10,
3073 		GP_1_9_FN,	GPSR1_9,
3074 		GP_1_8_FN,	GPSR1_8,
3075 		GP_1_7_FN,	GPSR1_7,
3076 		GP_1_6_FN,	GPSR1_6,
3077 		GP_1_5_FN,	GPSR1_5,
3078 		GP_1_4_FN,	GPSR1_4,
3079 		GP_1_3_FN,	GPSR1_3,
3080 		GP_1_2_FN,	GPSR1_2,
3081 		GP_1_1_FN,	GPSR1_1,
3082 		GP_1_0_FN,	GPSR1_0, ))
3083 	},
3084 	{ PINMUX_CFG_REG_VAR("GPSR2", 0xE6058040, 32,
3085 			     GROUP(-12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3086 				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3087 			     GROUP(
3088 		/* GP2_31_20 RESERVED */
3089 		GP_2_19_FN,	GPSR2_19,
3090 		GP_2_18_FN,	GPSR2_18,
3091 		GP_2_17_FN,	GPSR2_17,
3092 		GP_2_16_FN,	GPSR2_16,
3093 		GP_2_15_FN,	GPSR2_15,
3094 		GP_2_14_FN,	GPSR2_14,
3095 		GP_2_13_FN,	GPSR2_13,
3096 		GP_2_12_FN,	GPSR2_12,
3097 		GP_2_11_FN,	GPSR2_11,
3098 		GP_2_10_FN,	GPSR2_10,
3099 		GP_2_9_FN,	GPSR2_9,
3100 		GP_2_8_FN,	GPSR2_8,
3101 		GP_2_7_FN,	GPSR2_7,
3102 		GP_2_6_FN,	GPSR2_6,
3103 		GP_2_5_FN,	GPSR2_5,
3104 		GP_2_4_FN,	GPSR2_4,
3105 		GP_2_3_FN,	GPSR2_3,
3106 		GP_2_2_FN,	GPSR2_2,
3107 		GP_2_1_FN,	GPSR2_1,
3108 		GP_2_0_FN,	GPSR2_0, ))
3109 	},
3110 	{ PINMUX_CFG_REG("GPSR3", 0xE6058840, 32, 1, GROUP(
3111 		0, 0,
3112 		0, 0,
3113 		GP_3_29_FN,	GPSR3_29,
3114 		GP_3_28_FN,	GPSR3_28,
3115 		GP_3_27_FN,	GPSR3_27,
3116 		GP_3_26_FN,	GPSR3_26,
3117 		GP_3_25_FN,	GPSR3_25,
3118 		GP_3_24_FN,	GPSR3_24,
3119 		GP_3_23_FN,	GPSR3_23,
3120 		GP_3_22_FN,	GPSR3_22,
3121 		GP_3_21_FN,	GPSR3_21,
3122 		GP_3_20_FN,	GPSR3_20,
3123 		GP_3_19_FN,	GPSR3_19,
3124 		GP_3_18_FN,	GPSR3_18,
3125 		GP_3_17_FN,	GPSR3_17,
3126 		GP_3_16_FN,	GPSR3_16,
3127 		GP_3_15_FN,	GPSR3_15,
3128 		GP_3_14_FN,	GPSR3_14,
3129 		GP_3_13_FN,	GPSR3_13,
3130 		GP_3_12_FN,	GPSR3_12,
3131 		GP_3_11_FN,	GPSR3_11,
3132 		GP_3_10_FN,	GPSR3_10,
3133 		GP_3_9_FN,	GPSR3_9,
3134 		GP_3_8_FN,	GPSR3_8,
3135 		GP_3_7_FN,	GPSR3_7,
3136 		GP_3_6_FN,	GPSR3_6,
3137 		GP_3_5_FN,	GPSR3_5,
3138 		GP_3_4_FN,	GPSR3_4,
3139 		GP_3_3_FN,	GPSR3_3,
3140 		GP_3_2_FN,	GPSR3_2,
3141 		GP_3_1_FN,	GPSR3_1,
3142 		GP_3_0_FN,	GPSR3_0, ))
3143 	},
3144 	{ PINMUX_CFG_REG("GPSR4", 0xE6060040, 32, 1, GROUP(
3145 		0, 0,
3146 		0, 0,
3147 		0, 0,
3148 		0, 0,
3149 		0, 0,
3150 		0, 0,
3151 		0, 0,
3152 		GP_4_24_FN,	GPSR4_24,
3153 		GP_4_23_FN,	GPSR4_23,
3154 		GP_4_22_FN,	GPSR4_22,
3155 		GP_4_21_FN,	GPSR4_21,
3156 		GP_4_20_FN,	GPSR4_20,
3157 		GP_4_19_FN,	GPSR4_19,
3158 		GP_4_18_FN,	GPSR4_18,
3159 		GP_4_17_FN,	GPSR4_17,
3160 		GP_4_16_FN,	GPSR4_16,
3161 		GP_4_15_FN,	GPSR4_15,
3162 		GP_4_14_FN,	GPSR4_14,
3163 		GP_4_13_FN,	GPSR4_13,
3164 		GP_4_12_FN,	GPSR4_12,
3165 		GP_4_11_FN,	GPSR4_11,
3166 		GP_4_10_FN,	GPSR4_10,
3167 		GP_4_9_FN,	GPSR4_9,
3168 		GP_4_8_FN,	GPSR4_8,
3169 		GP_4_7_FN,	GPSR4_7,
3170 		GP_4_6_FN,	GPSR4_6,
3171 		GP_4_5_FN,	GPSR4_5,
3172 		GP_4_4_FN,	GPSR4_4,
3173 		GP_4_3_FN,	GPSR4_3,
3174 		GP_4_2_FN,	GPSR4_2,
3175 		GP_4_1_FN,	GPSR4_1,
3176 		GP_4_0_FN,	GPSR4_0, ))
3177 	},
3178 	{ PINMUX_CFG_REG_VAR("GPSR5", 0xE6060840, 32,
3179 			     GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3180 				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3181 			     GROUP(
3182 		/* GP5_31_21 RESERVED */
3183 		GP_5_20_FN,	GPSR5_20,
3184 		GP_5_19_FN,	GPSR5_19,
3185 		GP_5_18_FN,	GPSR5_18,
3186 		GP_5_17_FN,	GPSR5_17,
3187 		GP_5_16_FN,	GPSR5_16,
3188 		GP_5_15_FN,	GPSR5_15,
3189 		GP_5_14_FN,	GPSR5_14,
3190 		GP_5_13_FN,	GPSR5_13,
3191 		GP_5_12_FN,	GPSR5_12,
3192 		GP_5_11_FN,	GPSR5_11,
3193 		GP_5_10_FN,	GPSR5_10,
3194 		GP_5_9_FN,	GPSR5_9,
3195 		GP_5_8_FN,	GPSR5_8,
3196 		GP_5_7_FN,	GPSR5_7,
3197 		GP_5_6_FN,	GPSR5_6,
3198 		GP_5_5_FN,	GPSR5_5,
3199 		GP_5_4_FN,	GPSR5_4,
3200 		GP_5_3_FN,	GPSR5_3,
3201 		GP_5_2_FN,	GPSR5_2,
3202 		GP_5_1_FN,	GPSR5_1,
3203 		GP_5_0_FN,	GPSR5_0, ))
3204 	},
3205 	{ PINMUX_CFG_REG_VAR("GPSR6", 0xE6061040, 32,
3206 			     GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3207 				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3208 			     GROUP(
3209 		/* GP6_31_21 RESERVED */
3210 		GP_6_20_FN,	GPSR6_20,
3211 		GP_6_19_FN,	GPSR6_19,
3212 		GP_6_18_FN,	GPSR6_18,
3213 		GP_6_17_FN,	GPSR6_17,
3214 		GP_6_16_FN,	GPSR6_16,
3215 		GP_6_15_FN,	GPSR6_15,
3216 		GP_6_14_FN,	GPSR6_14,
3217 		GP_6_13_FN,	GPSR6_13,
3218 		GP_6_12_FN,	GPSR6_12,
3219 		GP_6_11_FN,	GPSR6_11,
3220 		GP_6_10_FN,	GPSR6_10,
3221 		GP_6_9_FN,	GPSR6_9,
3222 		GP_6_8_FN,	GPSR6_8,
3223 		GP_6_7_FN,	GPSR6_7,
3224 		GP_6_6_FN,	GPSR6_6,
3225 		GP_6_5_FN,	GPSR6_5,
3226 		GP_6_4_FN,	GPSR6_4,
3227 		GP_6_3_FN,	GPSR6_3,
3228 		GP_6_2_FN,	GPSR6_2,
3229 		GP_6_1_FN,	GPSR6_1,
3230 		GP_6_0_FN,	GPSR6_0, ))
3231 	},
3232 	{ PINMUX_CFG_REG_VAR("GPSR7", 0xE6061840, 32,
3233 			     GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3234 				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3235 			     GROUP(
3236 		/* GP7_31_21 RESERVED */
3237 		GP_7_20_FN,	GPSR7_20,
3238 		GP_7_19_FN,	GPSR7_19,
3239 		GP_7_18_FN,	GPSR7_18,
3240 		GP_7_17_FN,	GPSR7_17,
3241 		GP_7_16_FN,	GPSR7_16,
3242 		GP_7_15_FN,	GPSR7_15,
3243 		GP_7_14_FN,	GPSR7_14,
3244 		GP_7_13_FN,	GPSR7_13,
3245 		GP_7_12_FN,	GPSR7_12,
3246 		GP_7_11_FN,	GPSR7_11,
3247 		GP_7_10_FN,	GPSR7_10,
3248 		GP_7_9_FN,	GPSR7_9,
3249 		GP_7_8_FN,	GPSR7_8,
3250 		GP_7_7_FN,	GPSR7_7,
3251 		GP_7_6_FN,	GPSR7_6,
3252 		GP_7_5_FN,	GPSR7_5,
3253 		GP_7_4_FN,	GPSR7_4,
3254 		GP_7_3_FN,	GPSR7_3,
3255 		GP_7_2_FN,	GPSR7_2,
3256 		GP_7_1_FN,	GPSR7_1,
3257 		GP_7_0_FN,	GPSR7_0, ))
3258 	},
3259 	{ PINMUX_CFG_REG_VAR("GPSR8", 0xE6068040, 32,
3260 			     GROUP(-18, 1, 1, 1, 1,
3261 				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3262 			     GROUP(
3263 		/* GP8_31_14 RESERVED */
3264 		GP_8_13_FN,	GPSR8_13,
3265 		GP_8_12_FN,	GPSR8_12,
3266 		GP_8_11_FN,	GPSR8_11,
3267 		GP_8_10_FN,	GPSR8_10,
3268 		GP_8_9_FN,	GPSR8_9,
3269 		GP_8_8_FN,	GPSR8_8,
3270 		GP_8_7_FN,	GPSR8_7,
3271 		GP_8_6_FN,	GPSR8_6,
3272 		GP_8_5_FN,	GPSR8_5,
3273 		GP_8_4_FN,	GPSR8_4,
3274 		GP_8_3_FN,	GPSR8_3,
3275 		GP_8_2_FN,	GPSR8_2,
3276 		GP_8_1_FN,	GPSR8_1,
3277 		GP_8_0_FN,	GPSR8_0, ))
3278 	},
3279 #undef F_
3280 #undef FM
3281 
3282 #define F_(x, y)	x,
3283 #define FM(x)		FN_##x,
3284 	{ PINMUX_CFG_REG("IP0SR0", 0xE6050060, 32, 4, GROUP(
3285 		IP0SR0_31_28
3286 		IP0SR0_27_24
3287 		IP0SR0_23_20
3288 		IP0SR0_19_16
3289 		IP0SR0_15_12
3290 		IP0SR0_11_8
3291 		IP0SR0_7_4
3292 		IP0SR0_3_0))
3293 	},
3294 	{ PINMUX_CFG_REG("IP1SR0", 0xE6050064, 32, 4, GROUP(
3295 		IP1SR0_31_28
3296 		IP1SR0_27_24
3297 		IP1SR0_23_20
3298 		IP1SR0_19_16
3299 		IP1SR0_15_12
3300 		IP1SR0_11_8
3301 		IP1SR0_7_4
3302 		IP1SR0_3_0))
3303 	},
3304 	{ PINMUX_CFG_REG_VAR("IP2SR0", 0xE6050068, 32,
3305 			     GROUP(-20, 4, 4, 4),
3306 			     GROUP(
3307 		/* IP2SR0_31_12 RESERVED */
3308 		IP2SR0_11_8
3309 		IP2SR0_7_4
3310 		IP2SR0_3_0))
3311 	},
3312 	{ PINMUX_CFG_REG("IP0SR1", 0xE6050860, 32, 4, GROUP(
3313 		IP0SR1_31_28
3314 		IP0SR1_27_24
3315 		IP0SR1_23_20
3316 		IP0SR1_19_16
3317 		IP0SR1_15_12
3318 		IP0SR1_11_8
3319 		IP0SR1_7_4
3320 		IP0SR1_3_0))
3321 	},
3322 	{ PINMUX_CFG_REG("IP1SR1", 0xE6050864, 32, 4, GROUP(
3323 		IP1SR1_31_28
3324 		IP1SR1_27_24
3325 		IP1SR1_23_20
3326 		IP1SR1_19_16
3327 		IP1SR1_15_12
3328 		IP1SR1_11_8
3329 		IP1SR1_7_4
3330 		IP1SR1_3_0))
3331 	},
3332 	{ PINMUX_CFG_REG("IP2SR1", 0xE6050868, 32, 4, GROUP(
3333 		IP2SR1_31_28
3334 		IP2SR1_27_24
3335 		IP2SR1_23_20
3336 		IP2SR1_19_16
3337 		IP2SR1_15_12
3338 		IP2SR1_11_8
3339 		IP2SR1_7_4
3340 		IP2SR1_3_0))
3341 	},
3342 	{ PINMUX_CFG_REG_VAR("IP3SR1", 0xE605086C, 32,
3343 			     GROUP(-12, 4, 4, 4, 4, 4),
3344 			     GROUP(
3345 		/* IP3SR1_31_20 RESERVED */
3346 		IP3SR1_19_16
3347 		IP3SR1_15_12
3348 		IP3SR1_11_8
3349 		IP3SR1_7_4
3350 		IP3SR1_3_0))
3351 	},
3352 	{ PINMUX_CFG_REG("IP0SR2", 0xE6058060, 32, 4, GROUP(
3353 		IP0SR2_31_28
3354 		IP0SR2_27_24
3355 		IP0SR2_23_20
3356 		IP0SR2_19_16
3357 		IP0SR2_15_12
3358 		IP0SR2_11_8
3359 		IP0SR2_7_4
3360 		IP0SR2_3_0))
3361 	},
3362 	{ PINMUX_CFG_REG("IP1SR2", 0xE6058064, 32, 4, GROUP(
3363 		IP1SR2_31_28
3364 		IP1SR2_27_24
3365 		IP1SR2_23_20
3366 		IP1SR2_19_16
3367 		IP1SR2_15_12
3368 		IP1SR2_11_8
3369 		IP1SR2_7_4
3370 		IP1SR2_3_0))
3371 	},
3372 	{ PINMUX_CFG_REG_VAR("IP2SR2", 0xE6058068, 32,
3373 			     GROUP(-16, 4, 4, 4, 4),
3374 			     GROUP(
3375 		/* IP2SR2_31_16 RESERVED */
3376 		IP2SR2_15_12
3377 		IP2SR2_11_8
3378 		IP2SR2_7_4
3379 		IP2SR2_3_0))
3380 	},
3381 	{ PINMUX_CFG_REG("IP0SR3", 0xE6058860, 32, 4, GROUP(
3382 		IP0SR3_31_28
3383 		IP0SR3_27_24
3384 		IP0SR3_23_20
3385 		IP0SR3_19_16
3386 		IP0SR3_15_12
3387 		IP0SR3_11_8
3388 		IP0SR3_7_4
3389 		IP0SR3_3_0))
3390 	},
3391 	{ PINMUX_CFG_REG("IP1SR3", 0xE6058864, 32, 4, GROUP(
3392 		IP1SR3_31_28
3393 		IP1SR3_27_24
3394 		IP1SR3_23_20
3395 		IP1SR3_19_16
3396 		IP1SR3_15_12
3397 		IP1SR3_11_8
3398 		IP1SR3_7_4
3399 		IP1SR3_3_0))
3400 	},
3401 	{ PINMUX_CFG_REG("IP2SR3", 0xE6058868, 32, 4, GROUP(
3402 		IP2SR3_31_28
3403 		IP2SR3_27_24
3404 		IP2SR3_23_20
3405 		IP2SR3_19_16
3406 		IP2SR3_15_12
3407 		IP2SR3_11_8
3408 		IP2SR3_7_4
3409 		IP2SR3_3_0))
3410 	},
3411 	{ PINMUX_CFG_REG_VAR("IP3SR3", 0xE605886C, 32,
3412 			     GROUP(-8, 4, 4, 4, 4, 4, 4),
3413 			     GROUP(
3414 		/* IP3SR3_31_24 RESERVED */
3415 		IP3SR3_23_20
3416 		IP3SR3_19_16
3417 		IP3SR3_15_12
3418 		IP3SR3_11_8
3419 		IP3SR3_7_4
3420 		IP3SR3_3_0))
3421 	},
3422 	{ PINMUX_CFG_REG("IP0SR6", 0xE6061060, 32, 4, GROUP(
3423 		IP0SR6_31_28
3424 		IP0SR6_27_24
3425 		IP0SR6_23_20
3426 		IP0SR6_19_16
3427 		IP0SR6_15_12
3428 		IP0SR6_11_8
3429 		IP0SR6_7_4
3430 		IP0SR6_3_0))
3431 	},
3432 	{ PINMUX_CFG_REG("IP1SR6", 0xE6061064, 32, 4, GROUP(
3433 		IP1SR6_31_28
3434 		IP1SR6_27_24
3435 		IP1SR6_23_20
3436 		IP1SR6_19_16
3437 		IP1SR6_15_12
3438 		IP1SR6_11_8
3439 		IP1SR6_7_4
3440 		IP1SR6_3_0))
3441 	},
3442 	{ PINMUX_CFG_REG_VAR("IP2SR6", 0xE6061068, 32,
3443 			     GROUP(-12, 4, 4, 4, 4, 4),
3444 			     GROUP(
3445 		/* IP2SR6_31_20 RESERVED */
3446 		IP2SR6_19_16
3447 		IP2SR6_15_12
3448 		IP2SR6_11_8
3449 		IP2SR6_7_4
3450 		IP2SR6_3_0))
3451 	},
3452 	{ PINMUX_CFG_REG("IP0SR7", 0xE6061860, 32, 4, GROUP(
3453 		IP0SR7_31_28
3454 		IP0SR7_27_24
3455 		IP0SR7_23_20
3456 		IP0SR7_19_16
3457 		IP0SR7_15_12
3458 		IP0SR7_11_8
3459 		IP0SR7_7_4
3460 		IP0SR7_3_0))
3461 	},
3462 	{ PINMUX_CFG_REG("IP1SR7", 0xE6061864, 32, 4, GROUP(
3463 		IP1SR7_31_28
3464 		IP1SR7_27_24
3465 		IP1SR7_23_20
3466 		IP1SR7_19_16
3467 		IP1SR7_15_12
3468 		IP1SR7_11_8
3469 		IP1SR7_7_4
3470 		IP1SR7_3_0))
3471 	},
3472 	{ PINMUX_CFG_REG_VAR("IP2SR7", 0xE6061868, 32,
3473 			     GROUP(-12, 4, 4, 4, 4, 4),
3474 			     GROUP(
3475 		/* IP2SR7_31_20 RESERVED */
3476 		IP2SR7_19_16
3477 		IP2SR7_15_12
3478 		IP2SR7_11_8
3479 		IP2SR7_7_4
3480 		IP2SR7_3_0))
3481 	},
3482 	{ PINMUX_CFG_REG("IP0SR8", 0xE6068060, 32, 4, GROUP(
3483 		IP0SR8_31_28
3484 		IP0SR8_27_24
3485 		IP0SR8_23_20
3486 		IP0SR8_19_16
3487 		IP0SR8_15_12
3488 		IP0SR8_11_8
3489 		IP0SR8_7_4
3490 		IP0SR8_3_0))
3491 	},
3492 	{ PINMUX_CFG_REG_VAR("IP1SR8", 0xE6068064, 32,
3493 			     GROUP(-8, 4, 4, 4, 4, 4, 4),
3494 			     GROUP(
3495 		/* IP1SR8_31_24 RESERVED */
3496 		IP1SR8_23_20
3497 		IP1SR8_19_16
3498 		IP1SR8_15_12
3499 		IP1SR8_11_8
3500 		IP1SR8_7_4
3501 		IP1SR8_3_0))
3502 	},
3503 #undef F_
3504 #undef FM
3505 
3506 #define F_(x, y)	x,
3507 #define FM(x)		FN_##x,
3508 	{ PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE6060100, 32,
3509 			     GROUP(-12, 1, 1, -2, 1, 1, -1, 1, -2, 1, 1, -2, 1,
3510 				   -2, 1, 1, -1),
3511 			     GROUP(
3512 		/* RESERVED 31-20 */
3513 		MOD_SEL4_19
3514 		MOD_SEL4_18
3515 		/* RESERVED 17-16 */
3516 		MOD_SEL4_15
3517 		MOD_SEL4_14
3518 		/* RESERVED 13 */
3519 		MOD_SEL4_12
3520 		/* RESERVED 11-10 */
3521 		MOD_SEL4_9
3522 		MOD_SEL4_8
3523 		/* RESERVED 7-6 */
3524 		MOD_SEL4_5
3525 		/* RESERVED 4-3 */
3526 		MOD_SEL4_2
3527 		MOD_SEL4_1
3528 		/* RESERVED 0 */
3529 		))
3530 	},
3531 	{ PINMUX_CFG_REG_VAR("MOD_SEL5", 0xE6060900, 32,
3532 			     GROUP(-12, 1, -2, 1, 1, -2, 1, 1, -2, 1, -1,
3533 				   1, 1, -2, 1, -1, 1),
3534 			     GROUP(
3535 		/* RESERVED 31-20 */
3536 		MOD_SEL5_19
3537 		/* RESERVED 18-17 */
3538 		MOD_SEL5_16
3539 		MOD_SEL5_15
3540 		/* RESERVED 14-13 */
3541 		MOD_SEL5_12
3542 		MOD_SEL5_11
3543 		/* RESERVED 10-9 */
3544 		MOD_SEL5_8
3545 		/* RESERVED 7 */
3546 		MOD_SEL5_6
3547 		MOD_SEL5_5
3548 		/* RESERVED 4-3 */
3549 		MOD_SEL5_2
3550 		/* RESERVED 1 */
3551 		MOD_SEL5_0))
3552 	},
3553 	{ PINMUX_CFG_REG_VAR("MOD_SEL6", 0xE6061100, 32,
3554 			     GROUP(-13, 1, -1, 1, -2, 1, 1,
3555 				   -1, 1, -2, 1, 1, 1, -2, 1, 1, -1),
3556 			     GROUP(
3557 		/* RESERVED 31-19 */
3558 		MOD_SEL6_18
3559 		/* RESERVED 17 */
3560 		MOD_SEL6_16
3561 		/* RESERVED 15-14 */
3562 		MOD_SEL6_13
3563 		MOD_SEL6_12
3564 		/* RESERVED 11 */
3565 		MOD_SEL6_10
3566 		/* RESERVED 9-8 */
3567 		MOD_SEL6_7
3568 		MOD_SEL6_6
3569 		MOD_SEL6_5
3570 		/* RESERVED 4-3 */
3571 		MOD_SEL6_2
3572 		MOD_SEL6_1
3573 		/* RESERVED 0 */
3574 		))
3575 	},
3576 	{ PINMUX_CFG_REG_VAR("MOD_SEL7", 0xE6061900, 32,
3577 			     GROUP(-15, 1, 1, -1, 1, -1, 1, 1, -2, 1, 1,
3578 				   -2, 1, 1, -1, 1),
3579 			     GROUP(
3580 		/* RESERVED 31-17 */
3581 		MOD_SEL7_16
3582 		MOD_SEL7_15
3583 		/* RESERVED 14 */
3584 		MOD_SEL7_13
3585 		/* RESERVED 12 */
3586 		MOD_SEL7_11
3587 		MOD_SEL7_10
3588 		/* RESERVED 9-8 */
3589 		MOD_SEL7_7
3590 		MOD_SEL7_6
3591 		/* RESERVED 5-4 */
3592 		MOD_SEL7_3
3593 		MOD_SEL7_2
3594 		/* RESERVED 1 */
3595 		MOD_SEL7_0))
3596 	},
3597 	{ PINMUX_CFG_REG_VAR("MOD_SEL8", 0xE6068100, 32,
3598 			     GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3599 			     GROUP(
3600 		/* RESERVED 31-12 */
3601 		MOD_SEL8_11
3602 		MOD_SEL8_10
3603 		MOD_SEL8_9
3604 		MOD_SEL8_8
3605 		MOD_SEL8_7
3606 		MOD_SEL8_6
3607 		MOD_SEL8_5
3608 		MOD_SEL8_4
3609 		MOD_SEL8_3
3610 		MOD_SEL8_2
3611 		MOD_SEL8_1
3612 		MOD_SEL8_0))
3613 	},
3614 	{ },
3615 };
3616 
3617 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
3618 	{ PINMUX_DRIVE_REG("DRV0CTRL0", 0xE6050080) {
3619 		{ RCAR_GP_PIN(0,  7), 28, 3 },	/* MSIOF5_SS2 */
3620 		{ RCAR_GP_PIN(0,  6), 24, 3 },	/* IRQ0 */
3621 		{ RCAR_GP_PIN(0,  5), 20, 3 },	/* IRQ1 */
3622 		{ RCAR_GP_PIN(0,  4), 16, 3 },	/* IRQ2 */
3623 		{ RCAR_GP_PIN(0,  3), 12, 3 },	/* IRQ3 */
3624 		{ RCAR_GP_PIN(0,  2),  8, 3 },	/* GP0_02 */
3625 		{ RCAR_GP_PIN(0,  1),  4, 3 },	/* GP0_01 */
3626 		{ RCAR_GP_PIN(0,  0),  0, 3 },	/* GP0_00 */
3627 	} },
3628 	{ PINMUX_DRIVE_REG("DRV1CTRL0", 0xE6050084) {
3629 		{ RCAR_GP_PIN(0, 15), 28, 3 },	/* MSIOF2_SYNC */
3630 		{ RCAR_GP_PIN(0, 14), 24, 3 },	/* MSIOF2_SS1 */
3631 		{ RCAR_GP_PIN(0, 13), 20, 3 },	/* MSIOF2_SS2 */
3632 		{ RCAR_GP_PIN(0, 12), 16, 3 },	/* MSIOF5_RXD */
3633 		{ RCAR_GP_PIN(0, 11), 12, 3 },	/* MSIOF5_SCK */
3634 		{ RCAR_GP_PIN(0, 10),  8, 3 },	/* MSIOF5_TXD */
3635 		{ RCAR_GP_PIN(0,  9),  4, 3 },	/* MSIOF5_SYNC */
3636 		{ RCAR_GP_PIN(0,  8),  0, 3 },	/* MSIOF5_SS1 */
3637 	} },
3638 	{ PINMUX_DRIVE_REG("DRV2CTRL0", 0xE6050088) {
3639 		{ RCAR_GP_PIN(0, 18),  8, 3 },	/* MSIOF2_RXD */
3640 		{ RCAR_GP_PIN(0, 17),  4, 3 },	/* MSIOF2_SCK */
3641 		{ RCAR_GP_PIN(0, 16),  0, 3 },	/* MSIOF2_TXD */
3642 	} },
3643 	{ PINMUX_DRIVE_REG("DRV0CTRL1", 0xE6050880) {
3644 		{ RCAR_GP_PIN(1,  7), 28, 3 },	/* MSIOF0_SS1 */
3645 		{ RCAR_GP_PIN(1,  6), 24, 3 },	/* MSIOF0_SS2 */
3646 		{ RCAR_GP_PIN(1,  5), 20, 3 },	/* MSIOF1_RXD */
3647 		{ RCAR_GP_PIN(1,  4), 16, 3 },	/* MSIOF1_TXD */
3648 		{ RCAR_GP_PIN(1,  3), 12, 3 },	/* MSIOF1_SCK */
3649 		{ RCAR_GP_PIN(1,  2),  8, 3 },	/* MSIOF1_SYNC */
3650 		{ RCAR_GP_PIN(1,  1),  4, 3 },	/* MSIOF1_SS1 */
3651 		{ RCAR_GP_PIN(1,  0),  0, 3 },	/* MSIOF1_SS2 */
3652 	} },
3653 	{ PINMUX_DRIVE_REG("DRV1CTRL1", 0xE6050884) {
3654 		{ RCAR_GP_PIN(1, 15), 28, 3 },	/* HSCK0 */
3655 		{ RCAR_GP_PIN(1, 14), 24, 3 },	/* HRTS0_N */
3656 		{ RCAR_GP_PIN(1, 13), 20, 3 },	/* HCTS0_N */
3657 		{ RCAR_GP_PIN(1, 12), 16, 3 },	/* HTX0 */
3658 		{ RCAR_GP_PIN(1, 11), 12, 3 },	/* MSIOF0_RXD */
3659 		{ RCAR_GP_PIN(1, 10),  8, 3 },	/* MSIOF0_SCK */
3660 		{ RCAR_GP_PIN(1,  9),  4, 3 },	/* MSIOF0_TXD */
3661 		{ RCAR_GP_PIN(1,  8),  0, 3 },	/* MSIOF0_SYNC */
3662 	} },
3663 	{ PINMUX_DRIVE_REG("DRV2CTRL1", 0xE6050888) {
3664 		{ RCAR_GP_PIN(1, 23), 28, 3 },	/* GP1_23 */
3665 		{ RCAR_GP_PIN(1, 22), 24, 3 },	/* AUDIO_CLKIN */
3666 		{ RCAR_GP_PIN(1, 21), 20, 3 },	/* AUDIO_CLKOUT */
3667 		{ RCAR_GP_PIN(1, 20), 16, 3 },	/* SSI_SD */
3668 		{ RCAR_GP_PIN(1, 19), 12, 3 },	/* SSI_WS */
3669 		{ RCAR_GP_PIN(1, 18),  8, 3 },	/* SSI_SCK */
3670 		{ RCAR_GP_PIN(1, 17),  4, 3 },	/* SCIF_CLK */
3671 		{ RCAR_GP_PIN(1, 16),  0, 3 },	/* HRX0 */
3672 	} },
3673 	{ PINMUX_DRIVE_REG("DRV3CTRL1", 0xE605088C) {
3674 		{ RCAR_GP_PIN(1, 28), 16, 3 },	/* HTX3 */
3675 		{ RCAR_GP_PIN(1, 27), 12, 3 },	/* HCTS3_N */
3676 		{ RCAR_GP_PIN(1, 26),  8, 3 },	/* HRTS3_N */
3677 		{ RCAR_GP_PIN(1, 25),  4, 3 },	/* HSCK3 */
3678 		{ RCAR_GP_PIN(1, 24),  0, 3 },	/* HRX3 */
3679 	} },
3680 	{ PINMUX_DRIVE_REG("DRV0CTRL2", 0xE6058080) {
3681 		{ RCAR_GP_PIN(2,  7), 28, 3 },	/* TPU0TO1 */
3682 		{ RCAR_GP_PIN(2,  6), 24, 3 },	/* FXR_TXDB */
3683 		{ RCAR_GP_PIN(2,  5), 20, 3 },	/* FXR_TXENB_N */
3684 		{ RCAR_GP_PIN(2,  4), 16, 3 },	/* RXDB_EXTFXR */
3685 		{ RCAR_GP_PIN(2,  3), 12, 3 },	/* CLK_EXTFXR */
3686 		{ RCAR_GP_PIN(2,  2),  8, 3 },	/* RXDA_EXTFXR */
3687 		{ RCAR_GP_PIN(2,  1),  4, 3 },	/* FXR_TXENA_N */
3688 		{ RCAR_GP_PIN(2,  0),  0, 3 },	/* FXR_TXDA */
3689 	} },
3690 	{ PINMUX_DRIVE_REG("DRV1CTRL2", 0xE6058084) {
3691 		{ RCAR_GP_PIN(2, 15), 28, 3 },	/* CANFD3_RX */
3692 		{ RCAR_GP_PIN(2, 14), 24, 3 },	/* CANFD3_TX */
3693 		{ RCAR_GP_PIN(2, 13), 20, 3 },	/* CANFD2_RX */
3694 		{ RCAR_GP_PIN(2, 12), 16, 3 },	/* CANFD2_TX */
3695 		{ RCAR_GP_PIN(2, 11), 12, 3 },	/* CANFD0_RX */
3696 		{ RCAR_GP_PIN(2, 10),  8, 3 },	/* CANFD0_TX */
3697 		{ RCAR_GP_PIN(2,  9),  4, 3 },	/* CAN_CLK */
3698 		{ RCAR_GP_PIN(2,  8),  0, 3 },	/* TPU0TO0 */
3699 	} },
3700 	{ PINMUX_DRIVE_REG("DRV2CTRL2", 0xE6058088) {
3701 		{ RCAR_GP_PIN(2, 19), 12, 3 },	/* CANFD7_RX */
3702 		{ RCAR_GP_PIN(2, 18),  8, 3 },	/* CANFD7_TX */
3703 		{ RCAR_GP_PIN(2, 17),  4, 3 },	/* CANFD4_RX */
3704 		{ RCAR_GP_PIN(2, 16),  0, 3 },	/* CANFD4_TX */
3705 	} },
3706 	{ PINMUX_DRIVE_REG("DRV0CTRL3", 0xE6058880) {
3707 		{ RCAR_GP_PIN(3,  7), 28, 3 },	/* MMC_D4 */
3708 		{ RCAR_GP_PIN(3,  6), 24, 3 },	/* MMC_D5 */
3709 		{ RCAR_GP_PIN(3,  5), 20, 3 },	/* MMC_SD_D3 */
3710 		{ RCAR_GP_PIN(3,  4), 16, 3 },	/* MMC_DS */
3711 		{ RCAR_GP_PIN(3,  3), 12, 3 },	/* MMC_SD_CLK */
3712 		{ RCAR_GP_PIN(3,  2),  8, 3 },	/* MMC_SD_D2 */
3713 		{ RCAR_GP_PIN(3,  1),  4, 3 },	/* MMC_SD_D0 */
3714 		{ RCAR_GP_PIN(3,  0),  0, 3 },	/* MMC_SD_D1 */
3715 	} },
3716 	{ PINMUX_DRIVE_REG("DRV1CTRL3", 0xE6058884) {
3717 		{ RCAR_GP_PIN(3, 15), 28, 2 },	/* QSPI0_SSL */
3718 		{ RCAR_GP_PIN(3, 14), 24, 2 },	/* IPC_CLKOUT */
3719 		{ RCAR_GP_PIN(3, 13), 20, 2 },	/* IPC_CLKIN */
3720 		{ RCAR_GP_PIN(3, 12), 16, 3 },	/* SD_WP */
3721 		{ RCAR_GP_PIN(3, 11), 12, 3 },	/* SD_CD */
3722 		{ RCAR_GP_PIN(3, 10),  8, 3 },	/* MMC_SD_CMD */
3723 		{ RCAR_GP_PIN(3,  9),  4, 3 },	/* MMC_D6*/
3724 		{ RCAR_GP_PIN(3,  8),  0, 3 },	/* MMC_D7 */
3725 	} },
3726 	{ PINMUX_DRIVE_REG("DRV2CTRL3", 0xE6058888) {
3727 		{ RCAR_GP_PIN(3, 23), 28, 2 },	/* QSPI1_MISO_IO1 */
3728 		{ RCAR_GP_PIN(3, 22), 24, 2 },	/* QSPI1_SPCLK */
3729 		{ RCAR_GP_PIN(3, 21), 20, 2 },	/* QSPI1_MOSI_IO0 */
3730 		{ RCAR_GP_PIN(3, 20), 16, 2 },	/* QSPI0_SPCLK */
3731 		{ RCAR_GP_PIN(3, 19), 12, 2 },	/* QSPI0_MOSI_IO0 */
3732 		{ RCAR_GP_PIN(3, 18),  8, 2 },	/* QSPI0_MISO_IO1 */
3733 		{ RCAR_GP_PIN(3, 17),  4, 2 },	/* QSPI0_IO2 */
3734 		{ RCAR_GP_PIN(3, 16),  0, 2 },	/* QSPI0_IO3 */
3735 	} },
3736 	{ PINMUX_DRIVE_REG("DRV3CTRL3", 0xE605888C) {
3737 		{ RCAR_GP_PIN(3, 29), 20, 2 },	/* RPC_INT_N */
3738 		{ RCAR_GP_PIN(3, 28), 16, 2 },	/* RPC_WP_N */
3739 		{ RCAR_GP_PIN(3, 27), 12, 2 },	/* RPC_RESET_N */
3740 		{ RCAR_GP_PIN(3, 26),  8, 2 },	/* QSPI1_IO3 */
3741 		{ RCAR_GP_PIN(3, 25),  4, 2 },	/* QSPI1_SSL */
3742 		{ RCAR_GP_PIN(3, 24),  0, 2 },	/* QSPI1_IO2 */
3743 	} },
3744 	{ PINMUX_DRIVE_REG("DRV0CTRL4", 0xE6060080) {
3745 		{ RCAR_GP_PIN(4,  7), 28, 3 },	/* TSN0_RX_CTL */
3746 		{ RCAR_GP_PIN(4,  6), 24, 3 },	/* TSN0_AVTP_CAPTURE */
3747 		{ RCAR_GP_PIN(4,  5), 20, 3 },	/* TSN0_AVTP_MATCH */
3748 		{ RCAR_GP_PIN(4,  4), 16, 3 },	/* TSN0_LINK */
3749 		{ RCAR_GP_PIN(4,  3), 12, 3 },	/* TSN0_PHY_INT */
3750 		{ RCAR_GP_PIN(4,  2),  8, 3 },	/* TSN0_AVTP_PPS1 */
3751 		{ RCAR_GP_PIN(4,  1),  4, 3 },	/* TSN0_MDC */
3752 		{ RCAR_GP_PIN(4,  0),  0, 3 },	/* TSN0_MDIO */
3753 	} },
3754 	{ PINMUX_DRIVE_REG("DRV1CTRL4", 0xE6060084) {
3755 		{ RCAR_GP_PIN(4, 15), 28, 3 },	/* TSN0_TD0 */
3756 		{ RCAR_GP_PIN(4, 14), 24, 3 },	/* TSN0_TD1 */
3757 		{ RCAR_GP_PIN(4, 13), 20, 3 },	/* TSN0_RD1 */
3758 		{ RCAR_GP_PIN(4, 12), 16, 3 },	/* TSN0_TXC */
3759 		{ RCAR_GP_PIN(4, 11), 12, 3 },	/* TSN0_RXC */
3760 		{ RCAR_GP_PIN(4, 10),  8, 3 },	/* TSN0_RD0 */
3761 		{ RCAR_GP_PIN(4,  9),  4, 3 },	/* TSN0_TX_CTL */
3762 		{ RCAR_GP_PIN(4,  8),  0, 3 },	/* TSN0_AVTP_PPS0 */
3763 	} },
3764 	{ PINMUX_DRIVE_REG("DRV2CTRL4", 0xE6060088) {
3765 		{ RCAR_GP_PIN(4, 23), 28, 3 },	/* AVS0 */
3766 		{ RCAR_GP_PIN(4, 22), 24, 3 },	/* PCIE1_CLKREQ_N */
3767 		{ RCAR_GP_PIN(4, 21), 20, 3 },	/* PCIE0_CLKREQ_N */
3768 		{ RCAR_GP_PIN(4, 20), 16, 3 },	/* TSN0_TXCREFCLK */
3769 		{ RCAR_GP_PIN(4, 19), 12, 3 },	/* TSN0_TD2 */
3770 		{ RCAR_GP_PIN(4, 18),  8, 3 },	/* TSN0_TD3 */
3771 		{ RCAR_GP_PIN(4, 17),  4, 3 },	/* TSN0_RD2 */
3772 		{ RCAR_GP_PIN(4, 16),  0, 3 },	/* TSN0_RD3 */
3773 	} },
3774 	{ PINMUX_DRIVE_REG("DRV3CTRL4", 0xE606008C) {
3775 		{ RCAR_GP_PIN(4, 24),  0, 3 },	/* AVS1 */
3776 	} },
3777 	{ PINMUX_DRIVE_REG("DRV0CTRL5", 0xE6060880) {
3778 		{ RCAR_GP_PIN(5,  7), 28, 3 },	/* AVB2_TXCREFCLK */
3779 		{ RCAR_GP_PIN(5,  6), 24, 3 },	/* AVB2_MDC */
3780 		{ RCAR_GP_PIN(5,  5), 20, 3 },	/* AVB2_MAGIC */
3781 		{ RCAR_GP_PIN(5,  4), 16, 3 },	/* AVB2_PHY_INT */
3782 		{ RCAR_GP_PIN(5,  3), 12, 3 },	/* AVB2_LINK */
3783 		{ RCAR_GP_PIN(5,  2),  8, 3 },	/* AVB2_AVTP_MATCH */
3784 		{ RCAR_GP_PIN(5,  1),  4, 3 },	/* AVB2_AVTP_CAPTURE */
3785 		{ RCAR_GP_PIN(5,  0),  0, 3 },	/* AVB2_AVTP_PPS */
3786 	} },
3787 	{ PINMUX_DRIVE_REG("DRV1CTRL5", 0xE6060884) {
3788 		{ RCAR_GP_PIN(5, 15), 28, 3 },	/* AVB2_TD0 */
3789 		{ RCAR_GP_PIN(5, 14), 24, 3 },	/* AVB2_RD1 */
3790 		{ RCAR_GP_PIN(5, 13), 20, 3 },	/* AVB2_RD2 */
3791 		{ RCAR_GP_PIN(5, 12), 16, 3 },	/* AVB2_TD1 */
3792 		{ RCAR_GP_PIN(5, 11), 12, 3 },	/* AVB2_TD2 */
3793 		{ RCAR_GP_PIN(5, 10),  8, 3 },	/* AVB2_MDIO */
3794 		{ RCAR_GP_PIN(5,  9),  4, 3 },	/* AVB2_RD3 */
3795 		{ RCAR_GP_PIN(5,  8),  0, 3 },	/* AVB2_TD3 */
3796 	} },
3797 	{ PINMUX_DRIVE_REG("DRV2CTRL5", 0xE6060888) {
3798 		{ RCAR_GP_PIN(5, 20), 16, 3 },	/* AVB2_RX_CTL */
3799 		{ RCAR_GP_PIN(5, 19), 12, 3 },	/* AVB2_TX_CTL */
3800 		{ RCAR_GP_PIN(5, 18),  8, 3 },	/* AVB2_RXC */
3801 		{ RCAR_GP_PIN(5, 17),  4, 3 },	/* AVB2_RD0 */
3802 		{ RCAR_GP_PIN(5, 16),  0, 3 },	/* AVB2_TXC */
3803 	} },
3804 	{ PINMUX_DRIVE_REG("DRV0CTRL6", 0xE6061080) {
3805 		{ RCAR_GP_PIN(6,  7), 28, 3 },	/* AVB1_TX_CTL */
3806 		{ RCAR_GP_PIN(6,  6), 24, 3 },	/* AVB1_TXC */
3807 		{ RCAR_GP_PIN(6,  5), 20, 3 },	/* AVB1_AVTP_MATCH */
3808 		{ RCAR_GP_PIN(6,  4), 16, 3 },	/* AVB1_LINK */
3809 		{ RCAR_GP_PIN(6,  3), 12, 3 },	/* AVB1_PHY_INT */
3810 		{ RCAR_GP_PIN(6,  2),  8, 3 },	/* AVB1_MDC */
3811 		{ RCAR_GP_PIN(6,  1),  4, 3 },	/* AVB1_MAGIC */
3812 		{ RCAR_GP_PIN(6,  0),  0, 3 },	/* AVB1_MDIO */
3813 	} },
3814 	{ PINMUX_DRIVE_REG("DRV1CTRL6", 0xE6061084) {
3815 		{ RCAR_GP_PIN(6, 15), 28, 3 },	/* AVB1_RD0 */
3816 		{ RCAR_GP_PIN(6, 14), 24, 3 },	/* AVB1_RD1 */
3817 		{ RCAR_GP_PIN(6, 13), 20, 3 },	/* AVB1_TD0 */
3818 		{ RCAR_GP_PIN(6, 12), 16, 3 },	/* AVB1_TD1 */
3819 		{ RCAR_GP_PIN(6, 11), 12, 3 },	/* AVB1_AVTP_CAPTURE */
3820 		{ RCAR_GP_PIN(6, 10),  8, 3 },	/* AVB1_AVTP_PPS */
3821 		{ RCAR_GP_PIN(6,  9),  4, 3 },	/* AVB1_RX_CTL */
3822 		{ RCAR_GP_PIN(6,  8),  0, 3 },	/* AVB1_RXC */
3823 	} },
3824 	{ PINMUX_DRIVE_REG("DRV2CTRL6", 0xE6061088) {
3825 		{ RCAR_GP_PIN(6, 20), 16, 3 },	/* AVB1_TXCREFCLK */
3826 		{ RCAR_GP_PIN(6, 19), 12, 3 },	/* AVB1_RD3 */
3827 		{ RCAR_GP_PIN(6, 18),  8, 3 },	/* AVB1_TD3 */
3828 		{ RCAR_GP_PIN(6, 17),  4, 3 },	/* AVB1_RD2 */
3829 		{ RCAR_GP_PIN(6, 16),  0, 3 },	/* AVB1_TD2 */
3830 	} },
3831 	{ PINMUX_DRIVE_REG("DRV0CTRL7", 0xE6061880) {
3832 		{ RCAR_GP_PIN(7,  7), 28, 3 },	/* AVB0_TD1 */
3833 		{ RCAR_GP_PIN(7,  6), 24, 3 },	/* AVB0_TD2 */
3834 		{ RCAR_GP_PIN(7,  5), 20, 3 },	/* AVB0_PHY_INT */
3835 		{ RCAR_GP_PIN(7,  4), 16, 3 },	/* AVB0_LINK */
3836 		{ RCAR_GP_PIN(7,  3), 12, 3 },	/* AVB0_TD3 */
3837 		{ RCAR_GP_PIN(7,  2),  8, 3 },	/* AVB0_AVTP_MATCH */
3838 		{ RCAR_GP_PIN(7,  1),  4, 3 },	/* AVB0_AVTP_CAPTURE */
3839 		{ RCAR_GP_PIN(7,  0),  0, 3 },	/* AVB0_AVTP_PPS */
3840 	} },
3841 	{ PINMUX_DRIVE_REG("DRV1CTRL7", 0xE6061884) {
3842 		{ RCAR_GP_PIN(7, 15), 28, 3 },	/* AVB0_TXC */
3843 		{ RCAR_GP_PIN(7, 14), 24, 3 },	/* AVB0_MDIO */
3844 		{ RCAR_GP_PIN(7, 13), 20, 3 },	/* AVB0_MDC */
3845 		{ RCAR_GP_PIN(7, 12), 16, 3 },	/* AVB0_RD2 */
3846 		{ RCAR_GP_PIN(7, 11), 12, 3 },	/* AVB0_TD0 */
3847 		{ RCAR_GP_PIN(7, 10),  8, 3 },	/* AVB0_MAGIC */
3848 		{ RCAR_GP_PIN(7,  9),  4, 3 },	/* AVB0_TXCREFCLK */
3849 		{ RCAR_GP_PIN(7,  8),  0, 3 },	/* AVB0_RD3 */
3850 	} },
3851 	{ PINMUX_DRIVE_REG("DRV2CTRL7", 0xE6061888) {
3852 		{ RCAR_GP_PIN(7, 20), 16, 3 },	/* AVB0_RX_CTL */
3853 		{ RCAR_GP_PIN(7, 19), 12, 3 },	/* AVB0_RXC */
3854 		{ RCAR_GP_PIN(7, 18),  8, 3 },	/* AVB0_RD0 */
3855 		{ RCAR_GP_PIN(7, 17),  4, 3 },	/* AVB0_RD1 */
3856 		{ RCAR_GP_PIN(7, 16),  0, 3 },	/* AVB0_TX_CTL */
3857 	} },
3858 	{ PINMUX_DRIVE_REG("DRV0CTRL8", 0xE6068080) {
3859 		{ RCAR_GP_PIN(8,  7), 28, 3 },	/* SDA3 */
3860 		{ RCAR_GP_PIN(8,  6), 24, 3 },	/* SCL3 */
3861 		{ RCAR_GP_PIN(8,  5), 20, 3 },	/* SDA2 */
3862 		{ RCAR_GP_PIN(8,  4), 16, 3 },	/* SCL2 */
3863 		{ RCAR_GP_PIN(8,  3), 12, 3 },	/* SDA1 */
3864 		{ RCAR_GP_PIN(8,  2),  8, 3 },	/* SCL1 */
3865 		{ RCAR_GP_PIN(8,  1),  4, 3 },	/* SDA0 */
3866 		{ RCAR_GP_PIN(8,  0),  0, 3 },	/* SCL0 */
3867 	} },
3868 	{ PINMUX_DRIVE_REG("DRV1CTRL8", 0xE6068084) {
3869 		{ RCAR_GP_PIN(8, 13), 20, 3 },	/* GP8_13 */
3870 		{ RCAR_GP_PIN(8, 12), 16, 3 },	/* GP8_12 */
3871 		{ RCAR_GP_PIN(8, 11), 12, 3 },	/* SDA5 */
3872 		{ RCAR_GP_PIN(8, 10),  8, 3 },	/* SCL5 */
3873 		{ RCAR_GP_PIN(8,  9),  4, 3 },	/* SDA4 */
3874 		{ RCAR_GP_PIN(8,  8),  0, 3 },	/* SCL4 */
3875 	} },
3876 	{ },
3877 };
3878 
3879 enum ioctrl_regs {
3880 	POC0,
3881 	POC1,
3882 	POC3,
3883 	POC4,
3884 	POC5,
3885 	POC6,
3886 	POC7,
3887 	POC8,
3888 };
3889 
3890 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
3891 	[POC0]		= { 0xE60500A0, },
3892 	[POC1]		= { 0xE60508A0, },
3893 	[POC3]		= { 0xE60588A0, },
3894 	[POC4]		= { 0xE60600A0, },
3895 	[POC5]		= { 0xE60608A0, },
3896 	[POC6]		= { 0xE60610A0, },
3897 	[POC7]		= { 0xE60618A0, },
3898 	[POC8]		= { 0xE60680A0, },
3899 	{ /* sentinel */ },
3900 };
3901 
3902 static int r8a779g0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
3903 {
3904 	int bit = pin & 0x1f;
3905 
3906 	*pocctrl = pinmux_ioctrl_regs[POC0].reg;
3907 	if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 18))
3908 		return bit;
3909 
3910 	*pocctrl = pinmux_ioctrl_regs[POC1].reg;
3911 	if (pin >= RCAR_GP_PIN(1, 0) && pin <= RCAR_GP_PIN(1, 22))
3912 		return bit;
3913 
3914 	*pocctrl = pinmux_ioctrl_regs[POC3].reg;
3915 	if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 12))
3916 		return bit;
3917 
3918 	*pocctrl = pinmux_ioctrl_regs[POC8].reg;
3919 	if (pin >= RCAR_GP_PIN(8, 0) && pin <= RCAR_GP_PIN(8, 13))
3920 		return bit;
3921 
3922 	return -EINVAL;
3923 }
3924 
3925 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
3926 	{ PINMUX_BIAS_REG("PUEN0", 0xE60500C0, "PUD0", 0xE60500E0) {
3927 		[ 0] = RCAR_GP_PIN(0,  0),	/* GP0_00 */
3928 		[ 1] = RCAR_GP_PIN(0,  1),	/* GP0_01 */
3929 		[ 2] = RCAR_GP_PIN(0,  2),	/* GP0_02 */
3930 		[ 3] = RCAR_GP_PIN(0,  3),	/* IRQ3 */
3931 		[ 4] = RCAR_GP_PIN(0,  4),	/* IRQ2 */
3932 		[ 5] = RCAR_GP_PIN(0,  5),	/* IRQ1 */
3933 		[ 6] = RCAR_GP_PIN(0,  6),	/* IRQ0 */
3934 		[ 7] = RCAR_GP_PIN(0,  7),	/* MSIOF5_SS2 */
3935 		[ 8] = RCAR_GP_PIN(0,  8),	/* MSIOF5_SS1 */
3936 		[ 9] = RCAR_GP_PIN(0,  9),	/* MSIOF5_SYNC */
3937 		[10] = RCAR_GP_PIN(0, 10),	/* MSIOF5_TXD */
3938 		[11] = RCAR_GP_PIN(0, 11),	/* MSIOF5_SCK */
3939 		[12] = RCAR_GP_PIN(0, 12),	/* MSIOF5_RXD */
3940 		[13] = RCAR_GP_PIN(0, 13),	/* MSIOF2_SS2 */
3941 		[14] = RCAR_GP_PIN(0, 14),	/* MSIOF2_SS1 */
3942 		[15] = RCAR_GP_PIN(0, 15),	/* MSIOF2_SYNC */
3943 		[16] = RCAR_GP_PIN(0, 16),	/* MSIOF2_TXD */
3944 		[17] = RCAR_GP_PIN(0, 17),	/* MSIOF2_SCK */
3945 		[18] = RCAR_GP_PIN(0, 18),	/* MSIOF2_RXD */
3946 		[19] = SH_PFC_PIN_NONE,
3947 		[20] = SH_PFC_PIN_NONE,
3948 		[21] = SH_PFC_PIN_NONE,
3949 		[22] = SH_PFC_PIN_NONE,
3950 		[23] = SH_PFC_PIN_NONE,
3951 		[24] = SH_PFC_PIN_NONE,
3952 		[25] = SH_PFC_PIN_NONE,
3953 		[26] = SH_PFC_PIN_NONE,
3954 		[27] = SH_PFC_PIN_NONE,
3955 		[28] = SH_PFC_PIN_NONE,
3956 		[29] = SH_PFC_PIN_NONE,
3957 		[30] = SH_PFC_PIN_NONE,
3958 		[31] = SH_PFC_PIN_NONE,
3959 	} },
3960 	{ PINMUX_BIAS_REG("PUEN1", 0xE60508C0, "PUD1", 0xE60508E0) {
3961 		[ 0] = RCAR_GP_PIN(1,  0),	/* MSIOF1_SS2 */
3962 		[ 1] = RCAR_GP_PIN(1,  1),	/* MSIOF1_SS1 */
3963 		[ 2] = RCAR_GP_PIN(1,  2),	/* MSIOF1_SYNC */
3964 		[ 3] = RCAR_GP_PIN(1,  3),	/* MSIOF1_SCK */
3965 		[ 4] = RCAR_GP_PIN(1,  4),	/* MSIOF1_TXD */
3966 		[ 5] = RCAR_GP_PIN(1,  5),	/* MSIOF1_RXD */
3967 		[ 6] = RCAR_GP_PIN(1,  6),	/* MSIOF0_SS2 */
3968 		[ 7] = RCAR_GP_PIN(1,  7),	/* MSIOF0_SS1 */
3969 		[ 8] = RCAR_GP_PIN(1,  8),	/* MSIOF0_SYNC */
3970 		[ 9] = RCAR_GP_PIN(1,  9),	/* MSIOF0_TXD */
3971 		[10] = RCAR_GP_PIN(1, 10),	/* MSIOF0_SCK */
3972 		[11] = RCAR_GP_PIN(1, 11),	/* MSIOF0_RXD */
3973 		[12] = RCAR_GP_PIN(1, 12),	/* HTX0 */
3974 		[13] = RCAR_GP_PIN(1, 13),	/* HCTS0_N */
3975 		[14] = RCAR_GP_PIN(1, 14),	/* HRTS0_N */
3976 		[15] = RCAR_GP_PIN(1, 15),	/* HSCK0 */
3977 		[16] = RCAR_GP_PIN(1, 16),	/* HRX0 */
3978 		[17] = RCAR_GP_PIN(1, 17),	/* SCIF_CLK */
3979 		[18] = RCAR_GP_PIN(1, 18),	/* SSI_SCK */
3980 		[19] = RCAR_GP_PIN(1, 19),	/* SSI_WS */
3981 		[20] = RCAR_GP_PIN(1, 20),	/* SSI_SD */
3982 		[21] = RCAR_GP_PIN(1, 21),	/* AUDIO_CLKOUT */
3983 		[22] = RCAR_GP_PIN(1, 22),	/* AUDIO_CLKIN */
3984 		[23] = RCAR_GP_PIN(1, 23),	/* GP1_23 */
3985 		[24] = RCAR_GP_PIN(1, 24),	/* HRX3 */
3986 		[25] = RCAR_GP_PIN(1, 25),	/* HSCK3 */
3987 		[26] = RCAR_GP_PIN(1, 26),	/* HRTS3_N */
3988 		[27] = RCAR_GP_PIN(1, 27),	/* HCTS3_N */
3989 		[28] = RCAR_GP_PIN(1, 28),	/* HTX3 */
3990 		[29] = SH_PFC_PIN_NONE,
3991 		[30] = SH_PFC_PIN_NONE,
3992 		[31] = SH_PFC_PIN_NONE,
3993 	} },
3994 	{ PINMUX_BIAS_REG("PUEN2", 0xE60580C0, "PUD2", 0xE60580E0) {
3995 		[ 0] = RCAR_GP_PIN(2,  0),	/* FXR_TXDA */
3996 		[ 1] = RCAR_GP_PIN(2,  1),	/* FXR_TXENA_N */
3997 		[ 2] = RCAR_GP_PIN(2,  2),	/* RXDA_EXTFXR */
3998 		[ 3] = RCAR_GP_PIN(2,  3),	/* CLK_EXTFXR */
3999 		[ 4] = RCAR_GP_PIN(2,  4),	/* RXDB_EXTFXR */
4000 		[ 5] = RCAR_GP_PIN(2,  5),	/* FXR_TXENB_N */
4001 		[ 6] = RCAR_GP_PIN(2,  6),	/* FXR_TXDB */
4002 		[ 7] = RCAR_GP_PIN(2,  7),	/* TPU0TO1 */
4003 		[ 8] = RCAR_GP_PIN(2,  8),	/* TPU0TO0 */
4004 		[ 9] = RCAR_GP_PIN(2,  9),	/* CAN_CLK */
4005 		[10] = RCAR_GP_PIN(2, 10),	/* CANFD0_TX */
4006 		[11] = RCAR_GP_PIN(2, 11),	/* CANFD0_RX */
4007 		[12] = RCAR_GP_PIN(2, 12),	/* CANFD2_TX */
4008 		[13] = RCAR_GP_PIN(2, 13),	/* CANFD2_RX */
4009 		[14] = RCAR_GP_PIN(2, 14),	/* CANFD3_TX */
4010 		[15] = RCAR_GP_PIN(2, 15),	/* CANFD3_RX */
4011 		[16] = RCAR_GP_PIN(2, 16),	/* CANFD4_TX */
4012 		[17] = RCAR_GP_PIN(2, 17),	/* CANFD4_RX */
4013 		[18] = RCAR_GP_PIN(2, 18),	/* CANFD7_TX */
4014 		[19] = RCAR_GP_PIN(2, 19),	/* CANFD7_RX */
4015 		[20] = SH_PFC_PIN_NONE,
4016 		[21] = SH_PFC_PIN_NONE,
4017 		[22] = SH_PFC_PIN_NONE,
4018 		[23] = SH_PFC_PIN_NONE,
4019 		[24] = SH_PFC_PIN_NONE,
4020 		[25] = SH_PFC_PIN_NONE,
4021 		[26] = SH_PFC_PIN_NONE,
4022 		[27] = SH_PFC_PIN_NONE,
4023 		[28] = SH_PFC_PIN_NONE,
4024 		[29] = SH_PFC_PIN_NONE,
4025 		[30] = SH_PFC_PIN_NONE,
4026 		[31] = SH_PFC_PIN_NONE,
4027 	} },
4028 	{ PINMUX_BIAS_REG("PUEN3", 0xE60588C0, "PUD3", 0xE60588E0) {
4029 		[ 0] = RCAR_GP_PIN(3,  0),	/* MMC_SD_D1 */
4030 		[ 1] = RCAR_GP_PIN(3,  1),	/* MMC_SD_D0 */
4031 		[ 2] = RCAR_GP_PIN(3,  2),	/* MMC_SD_D2 */
4032 		[ 3] = RCAR_GP_PIN(3,  3),	/* MMC_SD_CLK */
4033 		[ 4] = RCAR_GP_PIN(3,  4),	/* MMC_DS */
4034 		[ 5] = RCAR_GP_PIN(3,  5),	/* MMC_SD_D3 */
4035 		[ 6] = RCAR_GP_PIN(3,  6),	/* MMC_D5 */
4036 		[ 7] = RCAR_GP_PIN(3,  7),	/* MMC_D4 */
4037 		[ 8] = RCAR_GP_PIN(3,  8),	/* MMC_D7 */
4038 		[ 9] = RCAR_GP_PIN(3,  9),	/* MMC_D6 */
4039 		[10] = RCAR_GP_PIN(3, 10),	/* MMC_SD_CMD */
4040 		[11] = RCAR_GP_PIN(3, 11),	/* SD_CD */
4041 		[12] = RCAR_GP_PIN(3, 12),	/* SD_WP */
4042 		[13] = RCAR_GP_PIN(3, 13),	/* IPC_CLKIN */
4043 		[14] = RCAR_GP_PIN(3, 14),	/* IPC_CLKOUT */
4044 		[15] = RCAR_GP_PIN(3, 15),	/* QSPI0_SSL */
4045 		[16] = RCAR_GP_PIN(3, 16),	/* QSPI0_IO3 */
4046 		[17] = RCAR_GP_PIN(3, 17),	/* QSPI0_IO2 */
4047 		[18] = RCAR_GP_PIN(3, 18),	/* QSPI0_MISO_IO1 */
4048 		[19] = RCAR_GP_PIN(3, 19),	/* QSPI0_MOSI_IO0 */
4049 		[20] = RCAR_GP_PIN(3, 20),	/* QSPI0_SPCLK */
4050 		[21] = RCAR_GP_PIN(3, 21),	/* QSPI1_MOSI_IO0 */
4051 		[22] = RCAR_GP_PIN(3, 22),	/* QSPI1_SPCLK */
4052 		[23] = RCAR_GP_PIN(3, 23),	/* QSPI1_MISO_IO1 */
4053 		[24] = RCAR_GP_PIN(3, 24),	/* QSPI1_IO2 */
4054 		[25] = RCAR_GP_PIN(3, 25),	/* QSPI1_SSL */
4055 		[26] = RCAR_GP_PIN(3, 26),	/* QSPI1_IO3 */
4056 		[27] = RCAR_GP_PIN(3, 27),	/* RPC_RESET_N */
4057 		[28] = RCAR_GP_PIN(3, 28),	/* RPC_WP_N */
4058 		[29] = RCAR_GP_PIN(3, 29),	/* RPC_INT_N */
4059 		[30] = SH_PFC_PIN_NONE,
4060 		[31] = SH_PFC_PIN_NONE,
4061 	} },
4062 	{ PINMUX_BIAS_REG("PUEN4", 0xE60600C0, "PUD4", 0xE60600E0) {
4063 		[ 0] = RCAR_GP_PIN(4,  0),	/* TSN0_MDIO */
4064 		[ 1] = RCAR_GP_PIN(4,  1),	/* TSN0_MDC */
4065 		[ 2] = RCAR_GP_PIN(4,  2),	/* TSN0_AVTP_PPS1 */
4066 		[ 3] = RCAR_GP_PIN(4,  3),	/* TSN0_PHY_INT */
4067 		[ 4] = RCAR_GP_PIN(4,  4),	/* TSN0_LINK */
4068 		[ 5] = RCAR_GP_PIN(4,  5),	/* TSN0_AVTP_MATCH */
4069 		[ 6] = RCAR_GP_PIN(4,  6),	/* TSN0_AVTP_CAPTURE */
4070 		[ 7] = RCAR_GP_PIN(4,  7),	/* TSN0_RX_CTL */
4071 		[ 8] = RCAR_GP_PIN(4,  8),	/* TSN0_AVTP_PPS0 */
4072 		[ 9] = RCAR_GP_PIN(4,  9),	/* TSN0_TX_CTL */
4073 		[10] = RCAR_GP_PIN(4, 10),	/* TSN0_RD0 */
4074 		[11] = RCAR_GP_PIN(4, 11),	/* TSN0_RXC */
4075 		[12] = RCAR_GP_PIN(4, 12),	/* TSN0_TXC */
4076 		[13] = RCAR_GP_PIN(4, 13),	/* TSN0_RD1 */
4077 		[14] = RCAR_GP_PIN(4, 14),	/* TSN0_TD1 */
4078 		[15] = RCAR_GP_PIN(4, 15),	/* TSN0_TD0 */
4079 		[16] = RCAR_GP_PIN(4, 16),	/* TSN0_RD3 */
4080 		[17] = RCAR_GP_PIN(4, 17),	/* TSN0_RD2 */
4081 		[18] = RCAR_GP_PIN(4, 18),	/* TSN0_TD3 */
4082 		[19] = RCAR_GP_PIN(4, 19),	/* TSN0_TD2 */
4083 		[20] = RCAR_GP_PIN(4, 20),	/* TSN0_TXCREFCLK */
4084 		[21] = RCAR_GP_PIN(4, 21),	/* PCIE0_CLKREQ_N */
4085 		[22] = RCAR_GP_PIN(4, 22),	/* PCIE1_CLKREQ_N */
4086 		[23] = RCAR_GP_PIN(4, 23),	/* AVS0 */
4087 		[24] = RCAR_GP_PIN(4, 24),	/* AVS1 */
4088 		[25] = SH_PFC_PIN_NONE,
4089 		[26] = SH_PFC_PIN_NONE,
4090 		[27] = SH_PFC_PIN_NONE,
4091 		[28] = SH_PFC_PIN_NONE,
4092 		[29] = SH_PFC_PIN_NONE,
4093 		[30] = SH_PFC_PIN_NONE,
4094 		[31] = SH_PFC_PIN_NONE,
4095 	} },
4096 	{ PINMUX_BIAS_REG("PUEN5", 0xE60608C0, "PUD5", 0xE60608E0) {
4097 		[ 0] = RCAR_GP_PIN(5,  0),	/* AVB2_AVTP_PPS */
4098 		[ 1] = RCAR_GP_PIN(5,  1),	/* AVB0_AVTP_CAPTURE */
4099 		[ 2] = RCAR_GP_PIN(5,  2),	/* AVB2_AVTP_MATCH */
4100 		[ 3] = RCAR_GP_PIN(5,  3),	/* AVB2_LINK */
4101 		[ 4] = RCAR_GP_PIN(5,  4),	/* AVB2_PHY_INT */
4102 		[ 5] = RCAR_GP_PIN(5,  5),	/* AVB2_MAGIC */
4103 		[ 6] = RCAR_GP_PIN(5,  6),	/* AVB2_MDC */
4104 		[ 7] = RCAR_GP_PIN(5,  7),	/* AVB2_TXCREFCLK */
4105 		[ 8] = RCAR_GP_PIN(5,  8),	/* AVB2_TD3 */
4106 		[ 9] = RCAR_GP_PIN(5,  9),	/* AVB2_RD3 */
4107 		[10] = RCAR_GP_PIN(5, 10),	/* AVB2_MDIO */
4108 		[11] = RCAR_GP_PIN(5, 11),	/* AVB2_TD2 */
4109 		[12] = RCAR_GP_PIN(5, 12),	/* AVB2_TD1 */
4110 		[13] = RCAR_GP_PIN(5, 13),	/* AVB2_RD2 */
4111 		[14] = RCAR_GP_PIN(5, 14),	/* AVB2_RD1 */
4112 		[15] = RCAR_GP_PIN(5, 15),	/* AVB2_TD0 */
4113 		[16] = RCAR_GP_PIN(5, 16),	/* AVB2_TXC */
4114 		[17] = RCAR_GP_PIN(5, 17),	/* AVB2_RD0 */
4115 		[18] = RCAR_GP_PIN(5, 18),	/* AVB2_RXC */
4116 		[19] = RCAR_GP_PIN(5, 19),	/* AVB2_TX_CTL */
4117 		[20] = RCAR_GP_PIN(5, 20),	/* AVB2_RX_CTL */
4118 		[21] = SH_PFC_PIN_NONE,
4119 		[22] = SH_PFC_PIN_NONE,
4120 		[23] = SH_PFC_PIN_NONE,
4121 		[24] = SH_PFC_PIN_NONE,
4122 		[25] = SH_PFC_PIN_NONE,
4123 		[26] = SH_PFC_PIN_NONE,
4124 		[27] = SH_PFC_PIN_NONE,
4125 		[28] = SH_PFC_PIN_NONE,
4126 		[29] = SH_PFC_PIN_NONE,
4127 		[30] = SH_PFC_PIN_NONE,
4128 		[31] = SH_PFC_PIN_NONE,
4129 	} },
4130 	{ PINMUX_BIAS_REG("PUEN6", 0xE60610C0, "PUD6", 0xE60610E0) {
4131 		[ 0] = RCAR_GP_PIN(6,  0),	/* AVB1_MDIO */
4132 		[ 1] = RCAR_GP_PIN(6,  1),	/* AVB1_MAGIC */
4133 		[ 2] = RCAR_GP_PIN(6,  2),	/* AVB1_MDC */
4134 		[ 3] = RCAR_GP_PIN(6,  3),	/* AVB1_PHY_INT */
4135 		[ 4] = RCAR_GP_PIN(6,  4),	/* AVB1_LINK */
4136 		[ 5] = RCAR_GP_PIN(6,  5),	/* AVB1_AVTP_MATCH */
4137 		[ 6] = RCAR_GP_PIN(6,  6),	/* AVB1_TXC */
4138 		[ 7] = RCAR_GP_PIN(6,  7),	/* AVB1_TX_CTL */
4139 		[ 8] = RCAR_GP_PIN(6,  8),	/* AVB1_RXC */
4140 		[ 9] = RCAR_GP_PIN(6,  9),	/* AVB1_RX_CTL */
4141 		[10] = RCAR_GP_PIN(6, 10),	/* AVB1_AVTP_PPS */
4142 		[11] = RCAR_GP_PIN(6, 11),	/* AVB1_AVTP_CAPTURE */
4143 		[12] = RCAR_GP_PIN(6, 12),	/* AVB1_TD1 */
4144 		[13] = RCAR_GP_PIN(6, 13),	/* AVB1_TD0 */
4145 		[14] = RCAR_GP_PIN(6, 14),	/* AVB1_RD1*/
4146 		[15] = RCAR_GP_PIN(6, 15),	/* AVB1_RD0 */
4147 		[16] = RCAR_GP_PIN(6, 16),	/* AVB1_TD2 */
4148 		[17] = RCAR_GP_PIN(6, 17),	/* AVB1_RD2 */
4149 		[18] = RCAR_GP_PIN(6, 18),	/* AVB1_TD3 */
4150 		[19] = RCAR_GP_PIN(6, 19),	/* AVB1_RD3 */
4151 		[20] = RCAR_GP_PIN(6, 20),	/* AVB1_TXCREFCLK */
4152 		[21] = SH_PFC_PIN_NONE,
4153 		[22] = SH_PFC_PIN_NONE,
4154 		[23] = SH_PFC_PIN_NONE,
4155 		[24] = SH_PFC_PIN_NONE,
4156 		[25] = SH_PFC_PIN_NONE,
4157 		[26] = SH_PFC_PIN_NONE,
4158 		[27] = SH_PFC_PIN_NONE,
4159 		[28] = SH_PFC_PIN_NONE,
4160 		[29] = SH_PFC_PIN_NONE,
4161 		[30] = SH_PFC_PIN_NONE,
4162 		[31] = SH_PFC_PIN_NONE,
4163 	} },
4164 	{ PINMUX_BIAS_REG("PUEN7", 0xE60618C0, "PUD7", 0xE60618E0) {
4165 		[ 0] = RCAR_GP_PIN(7,  0),	/* AVB0_AVTP_PPS */
4166 		[ 1] = RCAR_GP_PIN(7,  1),	/* AVB0_AVTP_CAPTURE */
4167 		[ 2] = RCAR_GP_PIN(7,  2),	/* AVB0_AVTP_MATCH */
4168 		[ 3] = RCAR_GP_PIN(7,  3),	/* AVB0_TD3 */
4169 		[ 4] = RCAR_GP_PIN(7,  4),	/* AVB0_LINK */
4170 		[ 5] = RCAR_GP_PIN(7,  5),	/* AVB0_PHY_INT */
4171 		[ 6] = RCAR_GP_PIN(7,  6),	/* AVB0_TD2 */
4172 		[ 7] = RCAR_GP_PIN(7,  7),	/* AVB0_TD1 */
4173 		[ 8] = RCAR_GP_PIN(7,  8),	/* AVB0_RD3 */
4174 		[ 9] = RCAR_GP_PIN(7,  9),	/* AVB0_TXCREFCLK */
4175 		[10] = RCAR_GP_PIN(7, 10),	/* AVB0_MAGIC */
4176 		[11] = RCAR_GP_PIN(7, 11),	/* AVB0_TD0 */
4177 		[12] = RCAR_GP_PIN(7, 12),	/* AVB0_RD2 */
4178 		[13] = RCAR_GP_PIN(7, 13),	/* AVB0_MDC */
4179 		[14] = RCAR_GP_PIN(7, 14),	/* AVB0_MDIO */
4180 		[15] = RCAR_GP_PIN(7, 15),	/* AVB0_TXC */
4181 		[16] = RCAR_GP_PIN(7, 16),	/* AVB0_TX_CTL */
4182 		[17] = RCAR_GP_PIN(7, 17),	/* AVB0_RD1 */
4183 		[18] = RCAR_GP_PIN(7, 18),	/* AVB0_RD0 */
4184 		[19] = RCAR_GP_PIN(7, 19),	/* AVB0_RXC */
4185 		[20] = RCAR_GP_PIN(7, 20),	/* AVB0_RX_CTL */
4186 		[21] = SH_PFC_PIN_NONE,
4187 		[22] = SH_PFC_PIN_NONE,
4188 		[23] = SH_PFC_PIN_NONE,
4189 		[24] = SH_PFC_PIN_NONE,
4190 		[25] = SH_PFC_PIN_NONE,
4191 		[26] = SH_PFC_PIN_NONE,
4192 		[27] = SH_PFC_PIN_NONE,
4193 		[28] = SH_PFC_PIN_NONE,
4194 		[29] = SH_PFC_PIN_NONE,
4195 		[30] = SH_PFC_PIN_NONE,
4196 		[31] = SH_PFC_PIN_NONE,
4197 	} },
4198 	{ PINMUX_BIAS_REG("PUEN8", 0xE60680C0, "PUD8", 0xE60680E0) {
4199 		[ 0] = RCAR_GP_PIN(8,  0),	/* SCL0 */
4200 		[ 1] = RCAR_GP_PIN(8,  1),	/* SDA0 */
4201 		[ 2] = RCAR_GP_PIN(8,  2),	/* SCL1 */
4202 		[ 3] = RCAR_GP_PIN(8,  3),	/* SDA1 */
4203 		[ 4] = RCAR_GP_PIN(8,  4),	/* SCL2 */
4204 		[ 5] = RCAR_GP_PIN(8,  5),	/* SDA2 */
4205 		[ 6] = RCAR_GP_PIN(8,  6),	/* SCL3 */
4206 		[ 7] = RCAR_GP_PIN(8,  7),	/* SDA3 */
4207 		[ 8] = RCAR_GP_PIN(8,  8),	/* SCL4 */
4208 		[ 9] = RCAR_GP_PIN(8,  9),	/* SDA4 */
4209 		[10] = RCAR_GP_PIN(8, 10),	/* SCL5 */
4210 		[11] = RCAR_GP_PIN(8, 11),	/* SDA5 */
4211 		[12] = RCAR_GP_PIN(8, 12),	/* GP8_12 */
4212 		[13] = RCAR_GP_PIN(8, 13),	/* GP8_13 */
4213 		[14] = SH_PFC_PIN_NONE,
4214 		[15] = SH_PFC_PIN_NONE,
4215 		[16] = SH_PFC_PIN_NONE,
4216 		[17] = SH_PFC_PIN_NONE,
4217 		[18] = SH_PFC_PIN_NONE,
4218 		[19] = SH_PFC_PIN_NONE,
4219 		[20] = SH_PFC_PIN_NONE,
4220 		[21] = SH_PFC_PIN_NONE,
4221 		[22] = SH_PFC_PIN_NONE,
4222 		[23] = SH_PFC_PIN_NONE,
4223 		[24] = SH_PFC_PIN_NONE,
4224 		[25] = SH_PFC_PIN_NONE,
4225 		[26] = SH_PFC_PIN_NONE,
4226 		[27] = SH_PFC_PIN_NONE,
4227 		[28] = SH_PFC_PIN_NONE,
4228 		[29] = SH_PFC_PIN_NONE,
4229 		[30] = SH_PFC_PIN_NONE,
4230 		[31] = SH_PFC_PIN_NONE,
4231 	} },
4232 	{ /* sentinel */ },
4233 };
4234 
4235 static const struct sh_pfc_soc_operations r8a779g0_pin_ops = {
4236 	.pin_to_pocctrl = r8a779g0_pin_to_pocctrl,
4237 	.get_bias = rcar_pinmux_get_bias,
4238 	.set_bias = rcar_pinmux_set_bias,
4239 };
4240 
4241 const struct sh_pfc_soc_info r8a779g0_pinmux_info = {
4242 	.name = "r8a779g0_pfc",
4243 	.ops = &r8a779g0_pin_ops,
4244 	.unlock_reg = 0x1ff,	/* PMMRn mask */
4245 
4246 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
4247 
4248 	.pins = pinmux_pins,
4249 	.nr_pins = ARRAY_SIZE(pinmux_pins),
4250 	.groups = pinmux_groups,
4251 	.nr_groups = ARRAY_SIZE(pinmux_groups),
4252 	.functions = pinmux_functions,
4253 	.nr_functions = ARRAY_SIZE(pinmux_functions),
4254 
4255 	.cfg_regs = pinmux_config_regs,
4256 	.drive_regs = pinmux_drive_regs,
4257 	.bias_regs = pinmux_bias_regs,
4258 	.ioctrl_regs = pinmux_ioctrl_regs,
4259 
4260 	.pinmux_data = pinmux_data,
4261 	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
4262 };
4263