1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * R8A779A0 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2021 Renesas Electronics Corp.
6 *
7 * This file is based on the drivers/pinctrl/renesas/pfc-r8a779a0.c
8 */
9
10 #include <linux/errno.h>
11 #include <linux/io.h>
12 #include <linux/kernel.h>
13
14 #include "sh_pfc.h"
15
16 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
17
18 #define CPU_ALL_GP(fn, sfx) \
19 PORT_GP_CFG_19(0, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
20 PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
21 PORT_GP_CFG_1(1, 23, fn, sfx, CFG_FLAGS), \
22 PORT_GP_CFG_1(1, 24, fn, sfx, CFG_FLAGS), \
23 PORT_GP_CFG_1(1, 25, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_1(1, 26, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_1(1, 27, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_1(1, 28, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_20(2, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_13(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
29 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_1(3, 16, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_1(3, 17, fn, sfx, CFG_FLAGS), \
34 PORT_GP_CFG_1(3, 18, fn, sfx, CFG_FLAGS), \
35 PORT_GP_CFG_1(3, 19, fn, sfx, CFG_FLAGS), \
36 PORT_GP_CFG_1(3, 20, fn, sfx, CFG_FLAGS), \
37 PORT_GP_CFG_1(3, 21, fn, sfx, CFG_FLAGS), \
38 PORT_GP_CFG_1(3, 22, fn, sfx, CFG_FLAGS), \
39 PORT_GP_CFG_1(3, 23, fn, sfx, CFG_FLAGS), \
40 PORT_GP_CFG_1(3, 24, fn, sfx, CFG_FLAGS), \
41 PORT_GP_CFG_1(3, 25, fn, sfx, CFG_FLAGS), \
42 PORT_GP_CFG_1(3, 26, fn, sfx, CFG_FLAGS), \
43 PORT_GP_CFG_1(3, 27, fn, sfx, CFG_FLAGS), \
44 PORT_GP_CFG_1(3, 28, fn, sfx, CFG_FLAGS), \
45 PORT_GP_CFG_1(3, 29, fn, sfx, CFG_FLAGS), \
46 PORT_GP_CFG_25(4, fn, sfx, CFG_FLAGS), \
47 PORT_GP_CFG_21(5, fn, sfx, CFG_FLAGS), \
48 PORT_GP_CFG_21(6, fn, sfx, CFG_FLAGS), \
49 PORT_GP_CFG_21(7, fn, sfx, CFG_FLAGS), \
50 PORT_GP_CFG_14(8, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33)
51
52 #define CPU_ALL_NOGP(fn) \
53 PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \
54 PIN_NOGP_CFG(VDDQ_AVB1, "VDDQ_AVB1", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \
55 PIN_NOGP_CFG(VDDQ_AVB2, "VDDQ_AVB2", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \
56 PIN_NOGP_CFG(VDDQ_TSN0, "VDDQ_TSN0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25)
57
58 /* GPSR0 */
59 #define GPSR0_18 F_(MSIOF2_RXD, IP2SR0_11_8)
60 #define GPSR0_17 F_(MSIOF2_SCK, IP2SR0_7_4)
61 #define GPSR0_16 F_(MSIOF2_TXD, IP2SR0_3_0)
62 #define GPSR0_15 F_(MSIOF2_SYNC, IP1SR0_31_28)
63 #define GPSR0_14 F_(MSIOF2_SS1, IP1SR0_27_24)
64 #define GPSR0_13 F_(MSIOF2_SS2, IP1SR0_23_20)
65 #define GPSR0_12 F_(MSIOF5_RXD, IP1SR0_19_16)
66 #define GPSR0_11 F_(MSIOF5_SCK, IP1SR0_15_12)
67 #define GPSR0_10 F_(MSIOF5_TXD, IP1SR0_11_8)
68 #define GPSR0_9 F_(MSIOF5_SYNC, IP1SR0_7_4)
69 #define GPSR0_8 F_(MSIOF5_SS1, IP1SR0_3_0)
70 #define GPSR0_7 F_(MSIOF5_SS2, IP0SR0_31_28)
71 #define GPSR0_6 F_(IRQ0_A, IP0SR0_27_24)
72 #define GPSR0_5 F_(IRQ1_A, IP0SR0_23_20)
73 #define GPSR0_4 F_(IRQ2_A, IP0SR0_19_16)
74 #define GPSR0_3 F_(IRQ3_A, IP0SR0_15_12)
75 #define GPSR0_2 F_(GP0_02, IP0SR0_11_8)
76 #define GPSR0_1 F_(GP0_01, IP0SR0_7_4)
77 #define GPSR0_0 F_(GP0_00, IP0SR0_3_0)
78
79 /* GPSR1 */
80 #define GPSR1_28 F_(HTX3_A, IP3SR1_19_16)
81 #define GPSR1_27 F_(HCTS3_N_A, IP3SR1_15_12)
82 #define GPSR1_26 F_(HRTS3_N_A, IP3SR1_11_8)
83 #define GPSR1_25 F_(HSCK3_A, IP3SR1_7_4)
84 #define GPSR1_24 F_(HRX3_A, IP3SR1_3_0)
85 #define GPSR1_23 F_(GP1_23, IP2SR1_31_28)
86 #define GPSR1_22 F_(AUDIO_CLKIN, IP2SR1_27_24)
87 #define GPSR1_21 F_(AUDIO_CLKOUT, IP2SR1_23_20)
88 #define GPSR1_20 F_(SSI_SD, IP2SR1_19_16)
89 #define GPSR1_19 F_(SSI_WS, IP2SR1_15_12)
90 #define GPSR1_18 F_(SSI_SCK, IP2SR1_11_8)
91 #define GPSR1_17 F_(SCIF_CLK, IP2SR1_7_4)
92 #define GPSR1_16 F_(HRX0, IP2SR1_3_0)
93 #define GPSR1_15 F_(HSCK0, IP1SR1_31_28)
94 #define GPSR1_14 F_(HRTS0_N, IP1SR1_27_24)
95 #define GPSR1_13 F_(HCTS0_N, IP1SR1_23_20)
96 #define GPSR1_12 F_(HTX0, IP1SR1_19_16)
97 #define GPSR1_11 F_(MSIOF0_RXD, IP1SR1_15_12)
98 #define GPSR1_10 F_(MSIOF0_SCK, IP1SR1_11_8)
99 #define GPSR1_9 F_(MSIOF0_TXD, IP1SR1_7_4)
100 #define GPSR1_8 F_(MSIOF0_SYNC, IP1SR1_3_0)
101 #define GPSR1_7 F_(MSIOF0_SS1, IP0SR1_31_28)
102 #define GPSR1_6 F_(MSIOF0_SS2, IP0SR1_27_24)
103 #define GPSR1_5 F_(MSIOF1_RXD, IP0SR1_23_20)
104 #define GPSR1_4 F_(MSIOF1_TXD, IP0SR1_19_16)
105 #define GPSR1_3 F_(MSIOF1_SCK, IP0SR1_15_12)
106 #define GPSR1_2 F_(MSIOF1_SYNC, IP0SR1_11_8)
107 #define GPSR1_1 F_(MSIOF1_SS1, IP0SR1_7_4)
108 #define GPSR1_0 F_(MSIOF1_SS2, IP0SR1_3_0)
109
110 /* GPSR2 */
111 #define GPSR2_19 F_(CANFD7_RX, IP2SR2_15_12)
112 #define GPSR2_18 F_(CANFD7_TX, IP2SR2_11_8)
113 #define GPSR2_17 F_(CANFD4_RX, IP2SR2_7_4)
114 #define GPSR2_16 F_(CANFD4_TX, IP2SR2_3_0)
115 #define GPSR2_15 F_(CANFD3_RX, IP1SR2_31_28)
116 #define GPSR2_14 F_(CANFD3_TX, IP1SR2_27_24)
117 #define GPSR2_13 F_(CANFD2_RX, IP1SR2_23_20)
118 #define GPSR2_12 F_(CANFD2_TX, IP1SR2_19_16)
119 #define GPSR2_11 F_(CANFD0_RX, IP1SR2_15_12)
120 #define GPSR2_10 F_(CANFD0_TX, IP1SR2_11_8)
121 #define GPSR2_9 F_(CAN_CLK, IP1SR2_7_4)
122 #define GPSR2_8 F_(TPU0TO0_A, IP1SR2_3_0)
123 #define GPSR2_7 F_(TPU0TO1_A, IP0SR2_31_28)
124 #define GPSR2_6 F_(FXR_TXDB, IP0SR2_27_24)
125 #define GPSR2_5 F_(FXR_TXENB_N_A, IP0SR2_23_20)
126 #define GPSR2_4 F_(RXDB_EXTFXR, IP0SR2_19_16)
127 #define GPSR2_3 F_(CLK_EXTFXR, IP0SR2_15_12)
128 #define GPSR2_2 F_(RXDA_EXTFXR, IP0SR2_11_8)
129 #define GPSR2_1 F_(FXR_TXENA_N_A, IP0SR2_7_4)
130 #define GPSR2_0 F_(FXR_TXDA, IP0SR2_3_0)
131
132 /* GPSR3 */
133 #define GPSR3_29 F_(RPC_INT_N, IP3SR3_23_20)
134 #define GPSR3_28 F_(RPC_WP_N, IP3SR3_19_16)
135 #define GPSR3_27 F_(RPC_RESET_N, IP3SR3_15_12)
136 #define GPSR3_26 F_(QSPI1_IO3, IP3SR3_11_8)
137 #define GPSR3_25 F_(QSPI1_SSL, IP3SR3_7_4)
138 #define GPSR3_24 F_(QSPI1_IO2, IP3SR3_3_0)
139 #define GPSR3_23 F_(QSPI1_MISO_IO1, IP2SR3_31_28)
140 #define GPSR3_22 F_(QSPI1_SPCLK, IP2SR3_27_24)
141 #define GPSR3_21 F_(QSPI1_MOSI_IO0, IP2SR3_23_20)
142 #define GPSR3_20 F_(QSPI0_SPCLK, IP2SR3_19_16)
143 #define GPSR3_19 F_(QSPI0_MOSI_IO0, IP2SR3_15_12)
144 #define GPSR3_18 F_(QSPI0_MISO_IO1, IP2SR3_11_8)
145 #define GPSR3_17 F_(QSPI0_IO2, IP2SR3_7_4)
146 #define GPSR3_16 F_(QSPI0_IO3, IP2SR3_3_0)
147 #define GPSR3_15 F_(QSPI0_SSL, IP1SR3_31_28)
148 #define GPSR3_14 F_(IPC_CLKOUT, IP1SR3_27_24)
149 #define GPSR3_13 F_(IPC_CLKIN, IP1SR3_23_20)
150 #define GPSR3_12 F_(SD_WP, IP1SR3_19_16)
151 #define GPSR3_11 F_(SD_CD, IP1SR3_15_12)
152 #define GPSR3_10 F_(MMC_SD_CMD, IP1SR3_11_8)
153 #define GPSR3_9 F_(MMC_D6, IP1SR3_7_4)
154 #define GPSR3_8 F_(MMC_D7, IP1SR3_3_0)
155 #define GPSR3_7 F_(MMC_D4, IP0SR3_31_28)
156 #define GPSR3_6 F_(MMC_D5, IP0SR3_27_24)
157 #define GPSR3_5 F_(MMC_SD_D3, IP0SR3_23_20)
158 #define GPSR3_4 F_(MMC_DS, IP0SR3_19_16)
159 #define GPSR3_3 F_(MMC_SD_CLK, IP0SR3_15_12)
160 #define GPSR3_2 F_(MMC_SD_D2, IP0SR3_11_8)
161 #define GPSR3_1 F_(MMC_SD_D0, IP0SR3_7_4)
162 #define GPSR3_0 F_(MMC_SD_D1, IP0SR3_3_0)
163
164 /* GPSR4 */
165 #define GPSR4_24 F_(AVS1, IP3SR4_3_0)
166 #define GPSR4_23 F_(AVS0, IP2SR4_31_28)
167 #define GPSR4_22 F_(PCIE1_CLKREQ_N, IP2SR4_27_24)
168 #define GPSR4_21 F_(PCIE0_CLKREQ_N, IP2SR4_23_20)
169 #define GPSR4_20 F_(TSN0_TXCREFCLK, IP2SR4_19_16)
170 #define GPSR4_19 F_(TSN0_TD2, IP2SR4_15_12)
171 #define GPSR4_18 F_(TSN0_TD3, IP2SR4_11_8)
172 #define GPSR4_17 F_(TSN0_RD2, IP2SR4_7_4)
173 #define GPSR4_16 F_(TSN0_RD3, IP2SR4_3_0)
174 #define GPSR4_15 F_(TSN0_TD0, IP1SR4_31_28)
175 #define GPSR4_14 F_(TSN0_TD1, IP1SR4_27_24)
176 #define GPSR4_13 F_(TSN0_RD1, IP1SR4_23_20)
177 #define GPSR4_12 F_(TSN0_TXC, IP1SR4_19_16)
178 #define GPSR4_11 F_(TSN0_RXC, IP1SR4_15_12)
179 #define GPSR4_10 F_(TSN0_RD0, IP1SR4_11_8)
180 #define GPSR4_9 F_(TSN0_TX_CTL, IP1SR4_7_4)
181 #define GPSR4_8 F_(TSN0_AVTP_PPS0, IP1SR4_3_0)
182 #define GPSR4_7 F_(TSN0_RX_CTL, IP0SR4_31_28)
183 #define GPSR4_6 F_(TSN0_AVTP_CAPTURE, IP0SR4_27_24)
184 #define GPSR4_5 F_(TSN0_AVTP_MATCH, IP0SR4_23_20)
185 #define GPSR4_4 F_(TSN0_LINK, IP0SR4_19_16)
186 #define GPSR4_3 F_(TSN0_PHY_INT, IP0SR4_15_12)
187 #define GPSR4_2 F_(TSN0_AVTP_PPS1, IP0SR4_11_8)
188 #define GPSR4_1 F_(TSN0_MDC, IP0SR4_7_4)
189 #define GPSR4_0 F_(TSN0_MDIO, IP0SR4_3_0)
190
191 /* GPSR 5 */
192 #define GPSR5_20 F_(AVB2_RX_CTL, IP2SR5_19_16)
193 #define GPSR5_19 F_(AVB2_TX_CTL, IP2SR5_15_12)
194 #define GPSR5_18 F_(AVB2_RXC, IP2SR5_11_8)
195 #define GPSR5_17 F_(AVB2_RD0, IP2SR5_7_4)
196 #define GPSR5_16 F_(AVB2_TXC, IP2SR5_3_0)
197 #define GPSR5_15 F_(AVB2_TD0, IP1SR5_31_28)
198 #define GPSR5_14 F_(AVB2_RD1, IP1SR5_27_24)
199 #define GPSR5_13 F_(AVB2_RD2, IP1SR5_23_20)
200 #define GPSR5_12 F_(AVB2_TD1, IP1SR5_19_16)
201 #define GPSR5_11 F_(AVB2_TD2, IP1SR5_15_12)
202 #define GPSR5_10 F_(AVB2_MDIO, IP1SR5_11_8)
203 #define GPSR5_9 F_(AVB2_RD3, IP1SR5_7_4)
204 #define GPSR5_8 F_(AVB2_TD3, IP1SR5_3_0)
205 #define GPSR5_7 F_(AVB2_TXCREFCLK, IP0SR5_31_28)
206 #define GPSR5_6 F_(AVB2_MDC, IP0SR5_27_24)
207 #define GPSR5_5 F_(AVB2_MAGIC, IP0SR5_23_20)
208 #define GPSR5_4 F_(AVB2_PHY_INT, IP0SR5_19_16)
209 #define GPSR5_3 F_(AVB2_LINK, IP0SR5_15_12)
210 #define GPSR5_2 F_(AVB2_AVTP_MATCH, IP0SR5_11_8)
211 #define GPSR5_1 F_(AVB2_AVTP_CAPTURE, IP0SR5_7_4)
212 #define GPSR5_0 F_(AVB2_AVTP_PPS, IP0SR5_3_0)
213
214 /* GPSR 6 */
215 #define GPSR6_20 F_(AVB1_TXCREFCLK, IP2SR6_19_16)
216 #define GPSR6_19 F_(AVB1_RD3, IP2SR6_15_12)
217 #define GPSR6_18 F_(AVB1_TD3, IP2SR6_11_8)
218 #define GPSR6_17 F_(AVB1_RD2, IP2SR6_7_4)
219 #define GPSR6_16 F_(AVB1_TD2, IP2SR6_3_0)
220 #define GPSR6_15 F_(AVB1_RD0, IP1SR6_31_28)
221 #define GPSR6_14 F_(AVB1_RD1, IP1SR6_27_24)
222 #define GPSR6_13 F_(AVB1_TD0, IP1SR6_23_20)
223 #define GPSR6_12 F_(AVB1_TD1, IP1SR6_19_16)
224 #define GPSR6_11 F_(AVB1_AVTP_CAPTURE, IP1SR6_15_12)
225 #define GPSR6_10 F_(AVB1_AVTP_PPS, IP1SR6_11_8)
226 #define GPSR6_9 F_(AVB1_RX_CTL, IP1SR6_7_4)
227 #define GPSR6_8 F_(AVB1_RXC, IP1SR6_3_0)
228 #define GPSR6_7 F_(AVB1_TX_CTL, IP0SR6_31_28)
229 #define GPSR6_6 F_(AVB1_TXC, IP0SR6_27_24)
230 #define GPSR6_5 F_(AVB1_AVTP_MATCH, IP0SR6_23_20)
231 #define GPSR6_4 F_(AVB1_LINK, IP0SR6_19_16)
232 #define GPSR6_3 F_(AVB1_PHY_INT, IP0SR6_15_12)
233 #define GPSR6_2 F_(AVB1_MDC, IP0SR6_11_8)
234 #define GPSR6_1 F_(AVB1_MAGIC, IP0SR6_7_4)
235 #define GPSR6_0 F_(AVB1_MDIO, IP0SR6_3_0)
236
237 /* GPSR7 */
238 #define GPSR7_20 F_(AVB0_RX_CTL, IP2SR7_19_16)
239 #define GPSR7_19 F_(AVB0_RXC, IP2SR7_15_12)
240 #define GPSR7_18 F_(AVB0_RD0, IP2SR7_11_8)
241 #define GPSR7_17 F_(AVB0_RD1, IP2SR7_7_4)
242 #define GPSR7_16 F_(AVB0_TX_CTL, IP2SR7_3_0)
243 #define GPSR7_15 F_(AVB0_TXC, IP1SR7_31_28)
244 #define GPSR7_14 F_(AVB0_MDIO, IP1SR7_27_24)
245 #define GPSR7_13 F_(AVB0_MDC, IP1SR7_23_20)
246 #define GPSR7_12 F_(AVB0_RD2, IP1SR7_19_16)
247 #define GPSR7_11 F_(AVB0_TD0, IP1SR7_15_12)
248 #define GPSR7_10 F_(AVB0_MAGIC, IP1SR7_11_8)
249 #define GPSR7_9 F_(AVB0_TXCREFCLK, IP1SR7_7_4)
250 #define GPSR7_8 F_(AVB0_RD3, IP1SR7_3_0)
251 #define GPSR7_7 F_(AVB0_TD1, IP0SR7_31_28)
252 #define GPSR7_6 F_(AVB0_TD2, IP0SR7_27_24)
253 #define GPSR7_5 F_(AVB0_PHY_INT, IP0SR7_23_20)
254 #define GPSR7_4 F_(AVB0_LINK, IP0SR7_19_16)
255 #define GPSR7_3 F_(AVB0_TD3, IP0SR7_15_12)
256 #define GPSR7_2 F_(AVB0_AVTP_MATCH, IP0SR7_11_8)
257 #define GPSR7_1 F_(AVB0_AVTP_CAPTURE, IP0SR7_7_4)
258 #define GPSR7_0 F_(AVB0_AVTP_PPS, IP0SR7_3_0)
259
260 /* GPSR8 */
261 #define GPSR8_13 F_(GP8_13, IP1SR8_23_20)
262 #define GPSR8_12 F_(GP8_12, IP1SR8_19_16)
263 #define GPSR8_11 F_(SDA5, IP1SR8_15_12)
264 #define GPSR8_10 F_(SCL5, IP1SR8_11_8)
265 #define GPSR8_9 F_(SDA4, IP1SR8_7_4)
266 #define GPSR8_8 F_(SCL4, IP1SR8_3_0)
267 #define GPSR8_7 F_(SDA3, IP0SR8_31_28)
268 #define GPSR8_6 F_(SCL3, IP0SR8_27_24)
269 #define GPSR8_5 F_(SDA2, IP0SR8_23_20)
270 #define GPSR8_4 F_(SCL2, IP0SR8_19_16)
271 #define GPSR8_3 F_(SDA1, IP0SR8_15_12)
272 #define GPSR8_2 F_(SCL1, IP0SR8_11_8)
273 #define GPSR8_1 F_(SDA0, IP0SR8_7_4)
274 #define GPSR8_0 F_(SCL0, IP0SR8_3_0)
275
276 /* SR0 */
277 /* IP0SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
278 #define IP0SR0_3_0 F_(0, 0) FM(ERROROUTC_N_B) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP0SR0_7_4 F_(0, 0) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP0SR0_11_8 F_(0, 0) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP0SR0_15_12 FM(IRQ3_A) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP0SR0_19_16 FM(IRQ2_A) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP0SR0_23_20 FM(IRQ1_A) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP0SR0_27_24 FM(IRQ0_A) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP0SR0_31_28 FM(MSIOF5_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286
287 /* IP1SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
288 #define IP1SR0_3_0 FM(MSIOF5_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP1SR0_7_4 FM(MSIOF5_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP1SR0_11_8 FM(MSIOF5_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP1SR0_15_12 FM(MSIOF5_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP1SR0_19_16 FM(MSIOF5_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP1SR0_23_20 FM(MSIOF2_SS2) FM(TCLK1_A) FM(IRQ2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP1SR0_27_24 FM(MSIOF2_SS1) FM(HTX1_A) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP1SR0_31_28 FM(MSIOF2_SYNC) FM(HRX1_A) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296
297 /* IP2SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
298 #define IP2SR0_3_0 FM(MSIOF2_TXD) FM(HCTS1_N_A) FM(CTS1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP2SR0_7_4 FM(MSIOF2_SCK) FM(HRTS1_N_A) FM(RTS1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP2SR0_11_8 FM(MSIOF2_RXD) FM(HSCK1_A) FM(SCK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301
302 /* SR1 */
303 /* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
304 #define IP0SR1_3_0 FM(MSIOF1_SS2) FM(HTX3_B) FM(TX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP0SR1_7_4 FM(MSIOF1_SS1) FM(HCTS3_N_B) FM(RX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP0SR1_11_8 FM(MSIOF1_SYNC) FM(HRTS3_N_B) FM(RTS3_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP0SR1_15_12 FM(MSIOF1_SCK) FM(HSCK3_B) FM(CTS3_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP0SR1_19_16 FM(MSIOF1_TXD) FM(HRX3_B) FM(SCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP0SR1_23_20 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP0SR1_27_24 FM(MSIOF0_SS2) FM(HTX1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP0SR1_31_28 FM(MSIOF0_SS1) FM(HRX1_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312
313 /* IP1SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
314 #define IP1SR1_3_0 FM(MSIOF0_SYNC) FM(HCTS1_N_B) FM(CTS1_N_B) FM(CANFD5_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP1SR1_7_4 FM(MSIOF0_TXD) FM(HRTS1_N_B) FM(RTS1_N_B) FM(CANFD5_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316 #define IP1SR1_11_8 FM(MSIOF0_SCK) FM(HSCK1_B) FM(SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317 #define IP1SR1_15_12 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318 #define IP1SR1_19_16 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319 #define IP1SR1_23_20 FM(HCTS0_N) FM(CTS0_N) FM(PWM8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP1SR1_27_24 FM(HRTS0_N) FM(RTS0_N) FM(PWM9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP1SR1_31_28 FM(HSCK0) FM(SCK0) FM(PWM0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322
323 /* IP2SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
324 #define IP2SR1_3_0 FM(HRX0) FM(RX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP2SR1_7_4 FM(SCIF_CLK) FM(IRQ4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP2SR1_11_8 FM(SSI_SCK) FM(TCLK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP2SR1_15_12 FM(SSI_WS) FM(TCLK4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP2SR1_19_16 FM(SSI_SD) FM(IRQ0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP2SR1_23_20 FM(AUDIO_CLKOUT) FM(IRQ1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP2SR1_27_24 FM(AUDIO_CLKIN) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP2SR1_31_28 F_(0, 0) FM(TCLK2_A) FM(MSIOF4_SS1) FM(IRQ3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332
333 /* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
334 #define IP3SR1_3_0 FM(HRX3_A) FM(SCK3_A) FM(MSIOF4_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 #define IP3SR1_7_4 FM(HSCK3_A) FM(CTS3_N_A) FM(MSIOF4_SCK) FM(TPU0TO0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336 #define IP3SR1_11_8 FM(HRTS3_N_A) FM(RTS3_N_A) FM(MSIOF4_TXD) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337 #define IP3SR1_15_12 FM(HCTS3_N_A) FM(RX3_A) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 #define IP3SR1_19_16 FM(HTX3_A) FM(TX3_A) FM(MSIOF4_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339
340 /* SR2 */
341 /* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
342 #define IP0SR2_3_0 FM(FXR_TXDA) FM(CANFD1_TX) FM(TPU0TO2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 #define IP0SR2_7_4 FM(FXR_TXENA_N_A) FM(CANFD1_RX) FM(TPU0TO3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 #define IP0SR2_11_8 FM(RXDA_EXTFXR) FM(CANFD5_TX_A) FM(IRQ5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 #define IP0SR2_15_12 FM(CLK_EXTFXR) FM(CANFD5_RX_A) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP0SR2_19_16 FM(RXDB_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP0SR2_23_20 FM(FXR_TXENB_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 #define IP0SR2_27_24 FM(FXR_TXDB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349 #define IP0SR2_31_28 FM(TPU0TO1_A) FM(CANFD6_TX) F_(0, 0) FM(TCLK2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350
351 /* IP1SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
352 #define IP1SR2_3_0 FM(TPU0TO0_A) FM(CANFD6_RX) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353 #define IP1SR2_7_4 FM(CAN_CLK) FM(FXR_TXENA_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354 #define IP1SR2_11_8 FM(CANFD0_TX) FM(FXR_TXENB_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355 #define IP1SR2_15_12 FM(CANFD0_RX) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356 #define IP1SR2_19_16 FM(CANFD2_TX) FM(TPU0TO2_A) F_(0, 0) FM(TCLK3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357 #define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3_A) FM(PWM1_B) FM(TCLK4_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358 #define IP1SR2_27_24 FM(CANFD3_TX) F_(0, 0) FM(PWM2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359 #define IP1SR2_31_28 FM(CANFD3_RX) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360
361 /* IP2SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
362 #define IP2SR2_3_0 FM(CANFD4_TX) F_(0, 0) FM(PWM4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363 #define IP2SR2_7_4 FM(CANFD4_RX) F_(0, 0) FM(PWM5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364 #define IP2SR2_11_8 FM(CANFD7_TX) F_(0, 0) FM(PWM6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
365 #define IP2SR2_15_12 FM(CANFD7_RX) F_(0, 0) FM(PWM7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
366
367 /* SR3 */
368 /* IP0SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
369 #define IP0SR3_3_0 FM(MMC_SD_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370 #define IP0SR3_7_4 FM(MMC_SD_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
371 #define IP0SR3_11_8 FM(MMC_SD_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
372 #define IP0SR3_15_12 FM(MMC_SD_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
373 #define IP0SR3_19_16 FM(MMC_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
374 #define IP0SR3_23_20 FM(MMC_SD_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
375 #define IP0SR3_27_24 FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
376 #define IP0SR3_31_28 FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
377
378 /* IP1SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
379 #define IP1SR3_3_0 FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
380 #define IP1SR3_7_4 FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
381 #define IP1SR3_11_8 FM(MMC_SD_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
382 #define IP1SR3_15_12 FM(SD_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
383 #define IP1SR3_19_16 FM(SD_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
384 #define IP1SR3_23_20 FM(IPC_CLKIN) FM(IPC_CLKEN_IN) FM(PWM1_A) FM(TCLK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
385 #define IP1SR3_27_24 FM(IPC_CLKOUT) FM(IPC_CLKEN_OUT) FM(ERROROUTC_N_A) FM(TCLK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
386 #define IP1SR3_31_28 FM(QSPI0_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
387
388 /* IP2SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
389 #define IP2SR3_3_0 FM(QSPI0_IO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
390 #define IP2SR3_7_4 FM(QSPI0_IO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
391 #define IP2SR3_11_8 FM(QSPI0_MISO_IO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
392 #define IP2SR3_15_12 FM(QSPI0_MOSI_IO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
393 #define IP2SR3_19_16 FM(QSPI0_SPCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
394 #define IP2SR3_23_20 FM(QSPI1_MOSI_IO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
395 #define IP2SR3_27_24 FM(QSPI1_SPCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
396 #define IP2SR3_31_28 FM(QSPI1_MISO_IO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
397
398 /* IP3SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
399 #define IP3SR3_3_0 FM(QSPI1_IO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
400 #define IP3SR3_7_4 FM(QSPI1_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
401 #define IP3SR3_11_8 FM(QSPI1_IO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
402 #define IP3SR3_15_12 FM(RPC_RESET_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
403 #define IP3SR3_19_16 FM(RPC_WP_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
404 #define IP3SR3_23_20 FM(RPC_INT_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
405
406 /* SR4 */
407 /* IP0SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
408 #define IP0SR4_3_0 FM(TSN0_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
409 #define IP0SR4_7_4 FM(TSN0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
410 #define IP0SR4_11_8 FM(TSN0_AVTP_PPS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
411 #define IP0SR4_15_12 FM(TSN0_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
412 #define IP0SR4_19_16 FM(TSN0_LINK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
413 #define IP0SR4_23_20 FM(TSN0_AVTP_MATCH) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
414 #define IP0SR4_27_24 FM(TSN0_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
415 #define IP0SR4_31_28 FM(TSN0_RX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
416
417 /* IP1SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
418 #define IP1SR4_3_0 FM(TSN0_AVTP_PPS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
419 #define IP1SR4_7_4 FM(TSN0_TX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
420 #define IP1SR4_11_8 FM(TSN0_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
421 #define IP1SR4_15_12 FM(TSN0_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
422 #define IP1SR4_19_16 FM(TSN0_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
423 #define IP1SR4_23_20 FM(TSN0_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
424 #define IP1SR4_27_24 FM(TSN0_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
425 #define IP1SR4_31_28 FM(TSN0_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
426
427 /* IP2SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
428 #define IP2SR4_3_0 FM(TSN0_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
429 #define IP2SR4_7_4 FM(TSN0_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
430 #define IP2SR4_11_8 FM(TSN0_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
431 #define IP2SR4_15_12 FM(TSN0_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
432 #define IP2SR4_19_16 FM(TSN0_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
433 #define IP2SR4_23_20 FM(PCIE0_CLKREQ_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
434 #define IP2SR4_27_24 FM(PCIE1_CLKREQ_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
435 #define IP2SR4_31_28 FM(AVS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
436
437 /* IP3SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
438 #define IP3SR4_3_0 FM(AVS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
439
440 /* SR5 */
441 /* IP0SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
442 #define IP0SR5_3_0 FM(AVB2_AVTP_PPS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
443 #define IP0SR5_7_4 FM(AVB2_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
444 #define IP0SR5_11_8 FM(AVB2_AVTP_MATCH) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
445 #define IP0SR5_15_12 FM(AVB2_LINK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
446 #define IP0SR5_19_16 FM(AVB2_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
447 #define IP0SR5_23_20 FM(AVB2_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
448 #define IP0SR5_27_24 FM(AVB2_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
449 #define IP0SR5_31_28 FM(AVB2_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
450
451 /* IP1SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
452 #define IP1SR5_3_0 FM(AVB2_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
453 #define IP1SR5_7_4 FM(AVB2_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
454 #define IP1SR5_11_8 FM(AVB2_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
455 #define IP1SR5_15_12 FM(AVB2_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
456 #define IP1SR5_19_16 FM(AVB2_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
457 #define IP1SR5_23_20 FM(AVB2_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
458 #define IP1SR5_27_24 FM(AVB2_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
459 #define IP1SR5_31_28 FM(AVB2_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
460
461 /* IP2SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
462 #define IP2SR5_3_0 FM(AVB2_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
463 #define IP2SR5_7_4 FM(AVB2_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
464 #define IP2SR5_11_8 FM(AVB2_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
465 #define IP2SR5_15_12 FM(AVB2_TX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
466 #define IP2SR5_19_16 FM(AVB2_RX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
467
468 /* SR6 */
469 /* IP0SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
470 #define IP0SR6_3_0 FM(AVB1_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
471 #define IP0SR6_7_4 FM(AVB1_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
472 #define IP0SR6_11_8 FM(AVB1_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
473 #define IP0SR6_15_12 FM(AVB1_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
474 #define IP0SR6_19_16 FM(AVB1_LINK) FM(AVB1_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
475 #define IP0SR6_23_20 FM(AVB1_AVTP_MATCH) FM(AVB1_MII_RX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
476 #define IP0SR6_27_24 FM(AVB1_TXC) FM(AVB1_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
477 #define IP0SR6_31_28 FM(AVB1_TX_CTL) FM(AVB1_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
478
479 /* IP1SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
480 #define IP1SR6_3_0 FM(AVB1_RXC) FM(AVB1_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
481 #define IP1SR6_7_4 FM(AVB1_RX_CTL) FM(AVB1_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
482 #define IP1SR6_11_8 FM(AVB1_AVTP_PPS) FM(AVB1_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
483 #define IP1SR6_15_12 FM(AVB1_AVTP_CAPTURE) FM(AVB1_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
484 #define IP1SR6_19_16 FM(AVB1_TD1) FM(AVB1_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
485 #define IP1SR6_23_20 FM(AVB1_TD0) FM(AVB1_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
486 #define IP1SR6_27_24 FM(AVB1_RD1) FM(AVB1_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
487 #define IP1SR6_31_28 FM(AVB1_RD0) FM(AVB1_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
488
489 /* IP2SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
490 #define IP2SR6_3_0 FM(AVB1_TD2) FM(AVB1_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
491 #define IP2SR6_7_4 FM(AVB1_RD2) FM(AVB1_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
492 #define IP2SR6_11_8 FM(AVB1_TD3) FM(AVB1_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
493 #define IP2SR6_15_12 FM(AVB1_RD3) FM(AVB1_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
494 #define IP2SR6_19_16 FM(AVB1_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
495
496 /* SR7 */
497 /* IP0SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
498 #define IP0SR7_3_0 FM(AVB0_AVTP_PPS) FM(AVB0_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
499 #define IP0SR7_7_4 FM(AVB0_AVTP_CAPTURE) FM(AVB0_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
500 #define IP0SR7_11_8 FM(AVB0_AVTP_MATCH) FM(AVB0_MII_RX_ER) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
501 #define IP0SR7_15_12 FM(AVB0_TD3) FM(AVB0_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
502 #define IP0SR7_19_16 FM(AVB0_LINK) FM(AVB0_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
503 #define IP0SR7_23_20 FM(AVB0_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
504 #define IP0SR7_27_24 FM(AVB0_TD2) FM(AVB0_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
505 #define IP0SR7_31_28 FM(AVB0_TD1) FM(AVB0_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
506
507 /* IP1SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
508 #define IP1SR7_3_0 FM(AVB0_RD3) FM(AVB0_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
509 #define IP1SR7_7_4 FM(AVB0_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
510 #define IP1SR7_11_8 FM(AVB0_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
511 #define IP1SR7_15_12 FM(AVB0_TD0) FM(AVB0_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
512 #define IP1SR7_19_16 FM(AVB0_RD2) FM(AVB0_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
513 #define IP1SR7_23_20 FM(AVB0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
514 #define IP1SR7_27_24 FM(AVB0_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
515 #define IP1SR7_31_28 FM(AVB0_TXC) FM(AVB0_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
516
517 /* IP2SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
518 #define IP2SR7_3_0 FM(AVB0_TX_CTL) FM(AVB0_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
519 #define IP2SR7_7_4 FM(AVB0_RD1) FM(AVB0_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
520 #define IP2SR7_11_8 FM(AVB0_RD0) FM(AVB0_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
521 #define IP2SR7_15_12 FM(AVB0_RXC) FM(AVB0_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
522 #define IP2SR7_19_16 FM(AVB0_RX_CTL) FM(AVB0_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
523
524 /* SR8 */
525 /* IP0SR8 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
526 #define IP0SR8_3_0 FM(SCL0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
527 #define IP0SR8_7_4 FM(SDA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
528 #define IP0SR8_11_8 FM(SCL1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
529 #define IP0SR8_15_12 FM(SDA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
530 #define IP0SR8_19_16 FM(SCL2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
531 #define IP0SR8_23_20 FM(SDA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
532 #define IP0SR8_27_24 FM(SCL3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
533 #define IP0SR8_31_28 FM(SDA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
534
535 /* IP1SR8 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
536 #define IP1SR8_3_0 FM(SCL4) FM(HRX2) FM(SCK4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
537 #define IP1SR8_7_4 FM(SDA4) FM(HTX2) FM(CTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
538 #define IP1SR8_11_8 FM(SCL5) FM(HRTS2_N) FM(RTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
539 #define IP1SR8_15_12 FM(SDA5) FM(SCIF_CLK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
540 #define IP1SR8_19_16 F_(0, 0) FM(HCTS2_N) FM(TX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
541 #define IP1SR8_23_20 F_(0, 0) FM(HSCK2) FM(RX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
542
543 #define PINMUX_GPSR \
544 GPSR3_29 \
545 GPSR1_28 GPSR3_28 \
546 GPSR1_27 GPSR3_27 \
547 GPSR1_26 GPSR3_26 \
548 GPSR1_25 GPSR3_25 \
549 GPSR1_24 GPSR3_24 GPSR4_24 \
550 GPSR1_23 GPSR3_23 GPSR4_23 \
551 GPSR1_22 GPSR3_22 GPSR4_22 \
552 GPSR1_21 GPSR3_21 GPSR4_21 \
553 GPSR1_20 GPSR3_20 GPSR4_20 GPSR5_20 GPSR6_20 GPSR7_20 \
554 GPSR1_19 GPSR2_19 GPSR3_19 GPSR4_19 GPSR5_19 GPSR6_19 GPSR7_19 \
555 GPSR0_18 GPSR1_18 GPSR2_18 GPSR3_18 GPSR4_18 GPSR5_18 GPSR6_18 GPSR7_18 \
556 GPSR0_17 GPSR1_17 GPSR2_17 GPSR3_17 GPSR4_17 GPSR5_17 GPSR6_17 GPSR7_17 \
557 GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 GPSR4_16 GPSR5_16 GPSR6_16 GPSR7_16 \
558 GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 GPSR7_15 \
559 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 GPSR7_14 \
560 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 GPSR7_13 GPSR8_13 \
561 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 GPSR7_12 GPSR8_12 \
562 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 GPSR7_11 GPSR8_11 \
563 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 GPSR7_10 GPSR8_10 \
564 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 GPSR7_9 GPSR8_9 \
565 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 GPSR7_8 GPSR8_8 \
566 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 GPSR7_7 GPSR8_7 \
567 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 GPSR7_6 GPSR8_6 \
568 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 GPSR7_5 GPSR8_5 \
569 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 GPSR7_4 GPSR8_4 \
570 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 GPSR8_3 \
571 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 GPSR8_2 \
572 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 GPSR8_1 \
573 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0 GPSR8_0
574
575 #define PINMUX_IPSR \
576 \
577 FM(IP0SR0_3_0) IP0SR0_3_0 FM(IP1SR0_3_0) IP1SR0_3_0 FM(IP2SR0_3_0) IP2SR0_3_0 \
578 FM(IP0SR0_7_4) IP0SR0_7_4 FM(IP1SR0_7_4) IP1SR0_7_4 FM(IP2SR0_7_4) IP2SR0_7_4 \
579 FM(IP0SR0_11_8) IP0SR0_11_8 FM(IP1SR0_11_8) IP1SR0_11_8 FM(IP2SR0_11_8) IP2SR0_11_8 \
580 FM(IP0SR0_15_12) IP0SR0_15_12 FM(IP1SR0_15_12) IP1SR0_15_12 \
581 FM(IP0SR0_19_16) IP0SR0_19_16 FM(IP1SR0_19_16) IP1SR0_19_16 \
582 FM(IP0SR0_23_20) IP0SR0_23_20 FM(IP1SR0_23_20) IP1SR0_23_20 \
583 FM(IP0SR0_27_24) IP0SR0_27_24 FM(IP1SR0_27_24) IP1SR0_27_24 \
584 FM(IP0SR0_31_28) IP0SR0_31_28 FM(IP1SR0_31_28) IP1SR0_31_28 \
585 \
586 FM(IP0SR1_3_0) IP0SR1_3_0 FM(IP1SR1_3_0) IP1SR1_3_0 FM(IP2SR1_3_0) IP2SR1_3_0 FM(IP3SR1_3_0) IP3SR1_3_0 \
587 FM(IP0SR1_7_4) IP0SR1_7_4 FM(IP1SR1_7_4) IP1SR1_7_4 FM(IP2SR1_7_4) IP2SR1_7_4 FM(IP3SR1_7_4) IP3SR1_7_4 \
588 FM(IP0SR1_11_8) IP0SR1_11_8 FM(IP1SR1_11_8) IP1SR1_11_8 FM(IP2SR1_11_8) IP2SR1_11_8 FM(IP3SR1_11_8) IP3SR1_11_8 \
589 FM(IP0SR1_15_12) IP0SR1_15_12 FM(IP1SR1_15_12) IP1SR1_15_12 FM(IP2SR1_15_12) IP2SR1_15_12 FM(IP3SR1_15_12) IP3SR1_15_12 \
590 FM(IP0SR1_19_16) IP0SR1_19_16 FM(IP1SR1_19_16) IP1SR1_19_16 FM(IP2SR1_19_16) IP2SR1_19_16 FM(IP3SR1_19_16) IP3SR1_19_16 \
591 FM(IP0SR1_23_20) IP0SR1_23_20 FM(IP1SR1_23_20) IP1SR1_23_20 FM(IP2SR1_23_20) IP2SR1_23_20 \
592 FM(IP0SR1_27_24) IP0SR1_27_24 FM(IP1SR1_27_24) IP1SR1_27_24 FM(IP2SR1_27_24) IP2SR1_27_24 \
593 FM(IP0SR1_31_28) IP0SR1_31_28 FM(IP1SR1_31_28) IP1SR1_31_28 FM(IP2SR1_31_28) IP2SR1_31_28 \
594 \
595 FM(IP0SR2_3_0) IP0SR2_3_0 FM(IP1SR2_3_0) IP1SR2_3_0 FM(IP2SR2_3_0) IP2SR2_3_0 \
596 FM(IP0SR2_7_4) IP0SR2_7_4 FM(IP1SR2_7_4) IP1SR2_7_4 FM(IP2SR2_7_4) IP2SR2_7_4 \
597 FM(IP0SR2_11_8) IP0SR2_11_8 FM(IP1SR2_11_8) IP1SR2_11_8 FM(IP2SR2_11_8) IP2SR2_11_8 \
598 FM(IP0SR2_15_12) IP0SR2_15_12 FM(IP1SR2_15_12) IP1SR2_15_12 FM(IP2SR2_15_12) IP2SR2_15_12 \
599 FM(IP0SR2_19_16) IP0SR2_19_16 FM(IP1SR2_19_16) IP1SR2_19_16 \
600 FM(IP0SR2_23_20) IP0SR2_23_20 FM(IP1SR2_23_20) IP1SR2_23_20 \
601 FM(IP0SR2_27_24) IP0SR2_27_24 FM(IP1SR2_27_24) IP1SR2_27_24 \
602 FM(IP0SR2_31_28) IP0SR2_31_28 FM(IP1SR2_31_28) IP1SR2_31_28 \
603 \
604 FM(IP0SR3_3_0) IP0SR3_3_0 FM(IP1SR3_3_0) IP1SR3_3_0 FM(IP2SR3_3_0) IP2SR3_3_0 FM(IP3SR3_3_0) IP3SR3_3_0 \
605 FM(IP0SR3_7_4) IP0SR3_7_4 FM(IP1SR3_7_4) IP1SR3_7_4 FM(IP2SR3_7_4) IP2SR3_7_4 FM(IP3SR3_7_4) IP3SR3_7_4 \
606 FM(IP0SR3_11_8) IP0SR3_11_8 FM(IP1SR3_11_8) IP1SR3_11_8 FM(IP2SR3_11_8) IP2SR3_11_8 FM(IP3SR3_11_8) IP3SR3_11_8 \
607 FM(IP0SR3_15_12) IP0SR3_15_12 FM(IP1SR3_15_12) IP1SR3_15_12 FM(IP2SR3_15_12) IP2SR3_15_12 FM(IP3SR3_15_12) IP3SR3_15_12 \
608 FM(IP0SR3_19_16) IP0SR3_19_16 FM(IP1SR3_19_16) IP1SR3_19_16 FM(IP2SR3_19_16) IP2SR3_19_16 FM(IP3SR3_19_16) IP3SR3_19_16 \
609 FM(IP0SR3_23_20) IP0SR3_23_20 FM(IP1SR3_23_20) IP1SR3_23_20 FM(IP2SR3_23_20) IP2SR3_23_20 FM(IP3SR3_23_20) IP3SR3_23_20 \
610 FM(IP0SR3_27_24) IP0SR3_27_24 FM(IP1SR3_27_24) IP1SR3_27_24 FM(IP2SR3_27_24) IP2SR3_27_24 \
611 FM(IP0SR3_31_28) IP0SR3_31_28 FM(IP1SR3_31_28) IP1SR3_31_28 FM(IP2SR3_31_28) IP2SR3_31_28 \
612 \
613 FM(IP0SR4_3_0) IP0SR4_3_0 FM(IP1SR4_3_0) IP1SR4_3_0 FM(IP2SR4_3_0) IP2SR4_3_0 FM(IP3SR4_3_0) IP3SR4_3_0 \
614 FM(IP0SR4_7_4) IP0SR4_7_4 FM(IP1SR4_7_4) IP1SR4_7_4 FM(IP2SR4_7_4) IP2SR4_7_4 \
615 FM(IP0SR4_11_8) IP0SR4_11_8 FM(IP1SR4_11_8) IP1SR4_11_8 FM(IP2SR4_11_8) IP2SR4_11_8 \
616 FM(IP0SR4_15_12) IP0SR4_15_12 FM(IP1SR4_15_12) IP1SR4_15_12 FM(IP2SR4_15_12) IP2SR4_15_12 \
617 FM(IP0SR4_19_16) IP0SR4_19_16 FM(IP1SR4_19_16) IP1SR4_19_16 FM(IP2SR4_19_16) IP2SR4_19_16 \
618 FM(IP0SR4_23_20) IP0SR4_23_20 FM(IP1SR4_23_20) IP1SR4_23_20 FM(IP2SR4_23_20) IP2SR4_23_20 \
619 FM(IP0SR4_27_24) IP0SR4_27_24 FM(IP1SR4_27_24) IP1SR4_27_24 FM(IP2SR4_27_24) IP2SR4_27_24 \
620 FM(IP0SR4_31_28) IP0SR4_31_28 FM(IP1SR4_31_28) IP1SR4_31_28 FM(IP2SR4_31_28) IP2SR4_31_28 \
621 \
622 FM(IP0SR5_3_0) IP0SR5_3_0 FM(IP1SR5_3_0) IP1SR5_3_0 FM(IP2SR5_3_0) IP2SR5_3_0 \
623 FM(IP0SR5_7_4) IP0SR5_7_4 FM(IP1SR5_7_4) IP1SR5_7_4 FM(IP2SR5_7_4) IP2SR5_7_4 \
624 FM(IP0SR5_11_8) IP0SR5_11_8 FM(IP1SR5_11_8) IP1SR5_11_8 FM(IP2SR5_11_8) IP2SR5_11_8 \
625 FM(IP0SR5_15_12) IP0SR5_15_12 FM(IP1SR5_15_12) IP1SR5_15_12 FM(IP2SR5_15_12) IP2SR5_15_12 \
626 FM(IP0SR5_19_16) IP0SR5_19_16 FM(IP1SR5_19_16) IP1SR5_19_16 FM(IP2SR5_19_16) IP2SR5_19_16 \
627 FM(IP0SR5_23_20) IP0SR5_23_20 FM(IP1SR5_23_20) IP1SR5_23_20 \
628 FM(IP0SR5_27_24) IP0SR5_27_24 FM(IP1SR5_27_24) IP1SR5_27_24 \
629 FM(IP0SR5_31_28) IP0SR5_31_28 FM(IP1SR5_31_28) IP1SR5_31_28 \
630 \
631 FM(IP0SR6_3_0) IP0SR6_3_0 FM(IP1SR6_3_0) IP1SR6_3_0 FM(IP2SR6_3_0) IP2SR6_3_0 \
632 FM(IP0SR6_7_4) IP0SR6_7_4 FM(IP1SR6_7_4) IP1SR6_7_4 FM(IP2SR6_7_4) IP2SR6_7_4 \
633 FM(IP0SR6_11_8) IP0SR6_11_8 FM(IP1SR6_11_8) IP1SR6_11_8 FM(IP2SR6_11_8) IP2SR6_11_8 \
634 FM(IP0SR6_15_12) IP0SR6_15_12 FM(IP1SR6_15_12) IP1SR6_15_12 FM(IP2SR6_15_12) IP2SR6_15_12 \
635 FM(IP0SR6_19_16) IP0SR6_19_16 FM(IP1SR6_19_16) IP1SR6_19_16 FM(IP2SR6_19_16) IP2SR6_19_16 \
636 FM(IP0SR6_23_20) IP0SR6_23_20 FM(IP1SR6_23_20) IP1SR6_23_20 \
637 FM(IP0SR6_27_24) IP0SR6_27_24 FM(IP1SR6_27_24) IP1SR6_27_24 \
638 FM(IP0SR6_31_28) IP0SR6_31_28 FM(IP1SR6_31_28) IP1SR6_31_28 \
639 \
640 FM(IP0SR7_3_0) IP0SR7_3_0 FM(IP1SR7_3_0) IP1SR7_3_0 FM(IP2SR7_3_0) IP2SR7_3_0 \
641 FM(IP0SR7_7_4) IP0SR7_7_4 FM(IP1SR7_7_4) IP1SR7_7_4 FM(IP2SR7_7_4) IP2SR7_7_4 \
642 FM(IP0SR7_11_8) IP0SR7_11_8 FM(IP1SR7_11_8) IP1SR7_11_8 FM(IP2SR7_11_8) IP2SR7_11_8 \
643 FM(IP0SR7_15_12) IP0SR7_15_12 FM(IP1SR7_15_12) IP1SR7_15_12 FM(IP2SR7_15_12) IP2SR7_15_12 \
644 FM(IP0SR7_19_16) IP0SR7_19_16 FM(IP1SR7_19_16) IP1SR7_19_16 FM(IP2SR7_19_16) IP2SR7_19_16 \
645 FM(IP0SR7_23_20) IP0SR7_23_20 FM(IP1SR7_23_20) IP1SR7_23_20 \
646 FM(IP0SR7_27_24) IP0SR7_27_24 FM(IP1SR7_27_24) IP1SR7_27_24 \
647 FM(IP0SR7_31_28) IP0SR7_31_28 FM(IP1SR7_31_28) IP1SR7_31_28 \
648 \
649 FM(IP0SR8_3_0) IP0SR8_3_0 FM(IP1SR8_3_0) IP1SR8_3_0 \
650 FM(IP0SR8_7_4) IP0SR8_7_4 FM(IP1SR8_7_4) IP1SR8_7_4 \
651 FM(IP0SR8_11_8) IP0SR8_11_8 FM(IP1SR8_11_8) IP1SR8_11_8 \
652 FM(IP0SR8_15_12) IP0SR8_15_12 FM(IP1SR8_15_12) IP1SR8_15_12 \
653 FM(IP0SR8_19_16) IP0SR8_19_16 FM(IP1SR8_19_16) IP1SR8_19_16 \
654 FM(IP0SR8_23_20) IP0SR8_23_20 FM(IP1SR8_23_20) IP1SR8_23_20 \
655 FM(IP0SR8_27_24) IP0SR8_27_24 \
656 FM(IP0SR8_31_28) IP0SR8_31_28
657
658 /* MOD_SEL8 */ /* 0 */ /* 1 */
659 #define MOD_SEL8_11 FM(SEL_SDA5_0) FM(SEL_SDA5_1)
660 #define MOD_SEL8_10 FM(SEL_SCL5_0) FM(SEL_SCL5_1)
661 #define MOD_SEL8_9 FM(SEL_SDA4_0) FM(SEL_SDA4_1)
662 #define MOD_SEL8_8 FM(SEL_SCL4_0) FM(SEL_SCL4_1)
663 #define MOD_SEL8_7 FM(SEL_SDA3_0) FM(SEL_SDA3_1)
664 #define MOD_SEL8_6 FM(SEL_SCL3_0) FM(SEL_SCL3_1)
665 #define MOD_SEL8_5 FM(SEL_SDA2_0) FM(SEL_SDA2_1)
666 #define MOD_SEL8_4 FM(SEL_SCL2_0) FM(SEL_SCL2_1)
667 #define MOD_SEL8_3 FM(SEL_SDA1_0) FM(SEL_SDA1_1)
668 #define MOD_SEL8_2 FM(SEL_SCL1_0) FM(SEL_SCL1_1)
669 #define MOD_SEL8_1 FM(SEL_SDA0_0) FM(SEL_SDA0_1)
670 #define MOD_SEL8_0 FM(SEL_SCL0_0) FM(SEL_SCL0_1)
671
672 #define PINMUX_MOD_SELS \
673 \
674 MOD_SEL8_11 \
675 MOD_SEL8_10 \
676 MOD_SEL8_9 \
677 MOD_SEL8_8 \
678 MOD_SEL8_7 \
679 MOD_SEL8_6 \
680 MOD_SEL8_5 \
681 MOD_SEL8_4 \
682 MOD_SEL8_3 \
683 MOD_SEL8_2 \
684 MOD_SEL8_1 \
685 MOD_SEL8_0
686
687 enum {
688 PINMUX_RESERVED = 0,
689
690 PINMUX_DATA_BEGIN,
691 GP_ALL(DATA),
692 PINMUX_DATA_END,
693
694 #define F_(x, y)
695 #define FM(x) FN_##x,
696 PINMUX_FUNCTION_BEGIN,
697 GP_ALL(FN),
698 PINMUX_GPSR
699 PINMUX_IPSR
700 PINMUX_MOD_SELS
701 PINMUX_FUNCTION_END,
702 #undef F_
703 #undef FM
704
705 #define F_(x, y)
706 #define FM(x) x##_MARK,
707 PINMUX_MARK_BEGIN,
708 PINMUX_GPSR
709 PINMUX_IPSR
710 PINMUX_MOD_SELS
711 PINMUX_MARK_END,
712 #undef F_
713 #undef FM
714 };
715
716 static const u16 pinmux_data[] = {
717 PINMUX_DATA_GP_ALL(),
718
719 /* IP0SR0 */
720 PINMUX_IPSR_GPSR(IP0SR0_3_0, ERROROUTC_N_B),
721 PINMUX_IPSR_GPSR(IP0SR0_3_0, TCLK2_B),
722
723 PINMUX_IPSR_GPSR(IP0SR0_7_4, MSIOF3_SS1),
724
725 PINMUX_IPSR_GPSR(IP0SR0_11_8, MSIOF3_SS2),
726
727 PINMUX_IPSR_GPSR(IP0SR0_15_12, IRQ3_A),
728 PINMUX_IPSR_GPSR(IP0SR0_15_12, MSIOF3_SCK),
729
730 PINMUX_IPSR_GPSR(IP0SR0_19_16, IRQ2_A),
731 PINMUX_IPSR_GPSR(IP0SR0_19_16, MSIOF3_TXD),
732
733 PINMUX_IPSR_GPSR(IP0SR0_23_20, IRQ1_A),
734 PINMUX_IPSR_GPSR(IP0SR0_23_20, MSIOF3_RXD),
735
736 PINMUX_IPSR_GPSR(IP0SR0_27_24, IRQ0_A),
737 PINMUX_IPSR_GPSR(IP0SR0_27_24, MSIOF3_SYNC),
738
739 PINMUX_IPSR_GPSR(IP0SR0_31_28, MSIOF5_SS2),
740
741 /* IP1SR0 */
742 PINMUX_IPSR_GPSR(IP1SR0_3_0, MSIOF5_SS1),
743
744 PINMUX_IPSR_GPSR(IP1SR0_7_4, MSIOF5_SYNC),
745
746 PINMUX_IPSR_GPSR(IP1SR0_11_8, MSIOF5_TXD),
747
748 PINMUX_IPSR_GPSR(IP1SR0_15_12, MSIOF5_SCK),
749
750 PINMUX_IPSR_GPSR(IP1SR0_19_16, MSIOF5_RXD),
751
752 PINMUX_IPSR_GPSR(IP1SR0_23_20, MSIOF2_SS2),
753 PINMUX_IPSR_GPSR(IP1SR0_23_20, TCLK1_A),
754 PINMUX_IPSR_GPSR(IP1SR0_23_20, IRQ2_B),
755
756 PINMUX_IPSR_GPSR(IP1SR0_27_24, MSIOF2_SS1),
757 PINMUX_IPSR_GPSR(IP1SR0_27_24, HTX1_A),
758 PINMUX_IPSR_GPSR(IP1SR0_27_24, TX1_A),
759
760 PINMUX_IPSR_GPSR(IP1SR0_31_28, MSIOF2_SYNC),
761 PINMUX_IPSR_GPSR(IP1SR0_31_28, HRX1_A),
762 PINMUX_IPSR_GPSR(IP1SR0_31_28, RX1_A),
763
764 /* IP2SR0 */
765 PINMUX_IPSR_GPSR(IP2SR0_3_0, MSIOF2_TXD),
766 PINMUX_IPSR_GPSR(IP2SR0_3_0, HCTS1_N_A),
767 PINMUX_IPSR_GPSR(IP2SR0_3_0, CTS1_N_A),
768
769 PINMUX_IPSR_GPSR(IP2SR0_7_4, MSIOF2_SCK),
770 PINMUX_IPSR_GPSR(IP2SR0_7_4, HRTS1_N_A),
771 PINMUX_IPSR_GPSR(IP2SR0_7_4, RTS1_N_A),
772
773 PINMUX_IPSR_GPSR(IP2SR0_11_8, MSIOF2_RXD),
774 PINMUX_IPSR_GPSR(IP2SR0_11_8, HSCK1_A),
775 PINMUX_IPSR_GPSR(IP2SR0_11_8, SCK1_A),
776
777 /* IP0SR1 */
778 PINMUX_IPSR_GPSR(IP0SR1_3_0, MSIOF1_SS2),
779 PINMUX_IPSR_GPSR(IP0SR1_3_0, HTX3_B),
780 PINMUX_IPSR_GPSR(IP0SR1_3_0, TX3_B),
781
782 PINMUX_IPSR_GPSR(IP0SR1_7_4, MSIOF1_SS1),
783 PINMUX_IPSR_GPSR(IP0SR1_7_4, HCTS3_N_B),
784 PINMUX_IPSR_GPSR(IP0SR1_7_4, RX3_B),
785
786 PINMUX_IPSR_GPSR(IP0SR1_11_8, MSIOF1_SYNC),
787 PINMUX_IPSR_GPSR(IP0SR1_11_8, HRTS3_N_B),
788 PINMUX_IPSR_GPSR(IP0SR1_11_8, RTS3_N_B),
789
790 PINMUX_IPSR_GPSR(IP0SR1_15_12, MSIOF1_SCK),
791 PINMUX_IPSR_GPSR(IP0SR1_15_12, HSCK3_B),
792 PINMUX_IPSR_GPSR(IP0SR1_15_12, CTS3_N_B),
793
794 PINMUX_IPSR_GPSR(IP0SR1_19_16, MSIOF1_TXD),
795 PINMUX_IPSR_GPSR(IP0SR1_19_16, HRX3_B),
796 PINMUX_IPSR_GPSR(IP0SR1_19_16, SCK3_B),
797
798 PINMUX_IPSR_GPSR(IP0SR1_23_20, MSIOF1_RXD),
799
800 PINMUX_IPSR_GPSR(IP0SR1_27_24, MSIOF0_SS2),
801 PINMUX_IPSR_GPSR(IP0SR1_27_24, HTX1_B),
802 PINMUX_IPSR_GPSR(IP0SR1_27_24, TX1_B),
803
804 PINMUX_IPSR_GPSR(IP0SR1_31_28, MSIOF0_SS1),
805 PINMUX_IPSR_GPSR(IP0SR1_31_28, HRX1_B),
806 PINMUX_IPSR_GPSR(IP0SR1_31_28, RX1_B),
807
808 /* IP1SR1 */
809 PINMUX_IPSR_GPSR(IP1SR1_3_0, MSIOF0_SYNC),
810 PINMUX_IPSR_GPSR(IP1SR1_3_0, HCTS1_N_B),
811 PINMUX_IPSR_GPSR(IP1SR1_3_0, CTS1_N_B),
812 PINMUX_IPSR_GPSR(IP1SR1_3_0, CANFD5_TX_B),
813
814 PINMUX_IPSR_GPSR(IP1SR1_7_4, MSIOF0_TXD),
815 PINMUX_IPSR_GPSR(IP1SR1_7_4, HRTS1_N_B),
816 PINMUX_IPSR_GPSR(IP1SR1_7_4, RTS1_N_B),
817 PINMUX_IPSR_GPSR(IP1SR1_7_4, CANFD5_RX_B),
818
819 PINMUX_IPSR_GPSR(IP1SR1_11_8, MSIOF0_SCK),
820 PINMUX_IPSR_GPSR(IP1SR1_11_8, HSCK1_B),
821 PINMUX_IPSR_GPSR(IP1SR1_11_8, SCK1_B),
822
823 PINMUX_IPSR_GPSR(IP1SR1_15_12, MSIOF0_RXD),
824
825 PINMUX_IPSR_GPSR(IP1SR1_19_16, HTX0),
826 PINMUX_IPSR_GPSR(IP1SR1_19_16, TX0),
827
828 PINMUX_IPSR_GPSR(IP1SR1_23_20, HCTS0_N),
829 PINMUX_IPSR_GPSR(IP1SR1_23_20, CTS0_N),
830 PINMUX_IPSR_GPSR(IP1SR1_23_20, PWM8),
831
832 PINMUX_IPSR_GPSR(IP1SR1_27_24, HRTS0_N),
833 PINMUX_IPSR_GPSR(IP1SR1_27_24, RTS0_N),
834 PINMUX_IPSR_GPSR(IP1SR1_27_24, PWM9),
835
836 PINMUX_IPSR_GPSR(IP1SR1_31_28, HSCK0),
837 PINMUX_IPSR_GPSR(IP1SR1_31_28, SCK0),
838 PINMUX_IPSR_GPSR(IP1SR1_31_28, PWM0),
839
840 /* IP2SR1 */
841 PINMUX_IPSR_GPSR(IP2SR1_3_0, HRX0),
842 PINMUX_IPSR_GPSR(IP2SR1_3_0, RX0),
843
844 PINMUX_IPSR_GPSR(IP2SR1_7_4, SCIF_CLK),
845 PINMUX_IPSR_GPSR(IP2SR1_7_4, IRQ4_A),
846
847 PINMUX_IPSR_GPSR(IP2SR1_11_8, SSI_SCK),
848 PINMUX_IPSR_GPSR(IP2SR1_11_8, TCLK3_B),
849
850 PINMUX_IPSR_GPSR(IP2SR1_15_12, SSI_WS),
851 PINMUX_IPSR_GPSR(IP2SR1_15_12, TCLK4_B),
852
853 PINMUX_IPSR_GPSR(IP2SR1_19_16, SSI_SD),
854 PINMUX_IPSR_GPSR(IP2SR1_19_16, IRQ0_B),
855
856 PINMUX_IPSR_GPSR(IP2SR1_23_20, AUDIO_CLKOUT),
857 PINMUX_IPSR_GPSR(IP2SR1_23_20, IRQ1_B),
858
859 PINMUX_IPSR_GPSR(IP2SR1_27_24, AUDIO_CLKIN),
860 PINMUX_IPSR_GPSR(IP2SR1_27_24, PWM3_A),
861
862 PINMUX_IPSR_GPSR(IP2SR1_31_28, TCLK2_A),
863 PINMUX_IPSR_GPSR(IP2SR1_31_28, MSIOF4_SS1),
864 PINMUX_IPSR_GPSR(IP2SR1_31_28, IRQ3_B),
865
866 /* IP3SR1 */
867 PINMUX_IPSR_GPSR(IP3SR1_3_0, HRX3_A),
868 PINMUX_IPSR_GPSR(IP3SR1_3_0, SCK3_A),
869 PINMUX_IPSR_GPSR(IP3SR1_3_0, MSIOF4_SS2),
870
871 PINMUX_IPSR_GPSR(IP3SR1_7_4, HSCK3_A),
872 PINMUX_IPSR_GPSR(IP3SR1_7_4, CTS3_N_A),
873 PINMUX_IPSR_GPSR(IP3SR1_7_4, MSIOF4_SCK),
874 PINMUX_IPSR_GPSR(IP3SR1_7_4, TPU0TO0_B),
875
876 PINMUX_IPSR_GPSR(IP3SR1_11_8, HRTS3_N_A),
877 PINMUX_IPSR_GPSR(IP3SR1_11_8, RTS3_N_A),
878 PINMUX_IPSR_GPSR(IP3SR1_11_8, MSIOF4_TXD),
879 PINMUX_IPSR_GPSR(IP3SR1_11_8, TPU0TO1_B),
880
881 PINMUX_IPSR_GPSR(IP3SR1_15_12, HCTS3_N_A),
882 PINMUX_IPSR_GPSR(IP3SR1_15_12, RX3_A),
883 PINMUX_IPSR_GPSR(IP3SR1_15_12, MSIOF4_RXD),
884
885 PINMUX_IPSR_GPSR(IP3SR1_19_16, HTX3_A),
886 PINMUX_IPSR_GPSR(IP3SR1_19_16, TX3_A),
887 PINMUX_IPSR_GPSR(IP3SR1_19_16, MSIOF4_SYNC),
888
889 /* IP0SR2 */
890 PINMUX_IPSR_GPSR(IP0SR2_3_0, FXR_TXDA),
891 PINMUX_IPSR_GPSR(IP0SR2_3_0, CANFD1_TX),
892 PINMUX_IPSR_GPSR(IP0SR2_3_0, TPU0TO2_B),
893
894 PINMUX_IPSR_GPSR(IP0SR2_7_4, FXR_TXENA_N_A),
895 PINMUX_IPSR_GPSR(IP0SR2_7_4, CANFD1_RX),
896 PINMUX_IPSR_GPSR(IP0SR2_7_4, TPU0TO3_B),
897
898 PINMUX_IPSR_GPSR(IP0SR2_11_8, RXDA_EXTFXR),
899 PINMUX_IPSR_GPSR(IP0SR2_11_8, CANFD5_TX_A),
900 PINMUX_IPSR_GPSR(IP0SR2_11_8, IRQ5),
901
902 PINMUX_IPSR_GPSR(IP0SR2_15_12, CLK_EXTFXR),
903 PINMUX_IPSR_GPSR(IP0SR2_15_12, CANFD5_RX_A),
904 PINMUX_IPSR_GPSR(IP0SR2_15_12, IRQ4_B),
905
906 PINMUX_IPSR_GPSR(IP0SR2_19_16, RXDB_EXTFXR),
907
908 PINMUX_IPSR_GPSR(IP0SR2_23_20, FXR_TXENB_N_A),
909
910 PINMUX_IPSR_GPSR(IP0SR2_27_24, FXR_TXDB),
911
912 PINMUX_IPSR_GPSR(IP0SR2_31_28, TPU0TO1_A),
913 PINMUX_IPSR_GPSR(IP0SR2_31_28, CANFD6_TX),
914 PINMUX_IPSR_GPSR(IP0SR2_31_28, TCLK2_C),
915
916 /* IP1SR2 */
917 PINMUX_IPSR_GPSR(IP1SR2_3_0, TPU0TO0_A),
918 PINMUX_IPSR_GPSR(IP1SR2_3_0, CANFD6_RX),
919 PINMUX_IPSR_GPSR(IP1SR2_3_0, TCLK1_B),
920
921 PINMUX_IPSR_GPSR(IP1SR2_7_4, CAN_CLK),
922 PINMUX_IPSR_GPSR(IP1SR2_7_4, FXR_TXENA_N_B),
923
924 PINMUX_IPSR_GPSR(IP1SR2_11_8, CANFD0_TX),
925 PINMUX_IPSR_GPSR(IP1SR2_11_8, FXR_TXENB_N_B),
926
927 PINMUX_IPSR_GPSR(IP1SR2_15_12, CANFD0_RX),
928 PINMUX_IPSR_GPSR(IP1SR2_15_12, STPWT_EXTFXR),
929
930 PINMUX_IPSR_GPSR(IP1SR2_19_16, CANFD2_TX),
931 PINMUX_IPSR_GPSR(IP1SR2_19_16, TPU0TO2_A),
932 PINMUX_IPSR_GPSR(IP1SR2_19_16, TCLK3_C),
933
934 PINMUX_IPSR_GPSR(IP1SR2_23_20, CANFD2_RX),
935 PINMUX_IPSR_GPSR(IP1SR2_23_20, TPU0TO3_A),
936 PINMUX_IPSR_GPSR(IP1SR2_23_20, PWM1_B),
937 PINMUX_IPSR_GPSR(IP1SR2_23_20, TCLK4_C),
938
939 PINMUX_IPSR_GPSR(IP1SR2_27_24, CANFD3_TX),
940 PINMUX_IPSR_GPSR(IP1SR2_27_24, PWM2),
941
942 PINMUX_IPSR_GPSR(IP1SR2_31_28, CANFD3_RX),
943 PINMUX_IPSR_GPSR(IP1SR2_31_28, PWM3_B),
944
945 /* IP2SR2 */
946 PINMUX_IPSR_GPSR(IP2SR2_3_0, CANFD4_TX),
947 PINMUX_IPSR_GPSR(IP2SR2_3_0, PWM4),
948
949 PINMUX_IPSR_GPSR(IP2SR2_7_4, CANFD4_RX),
950 PINMUX_IPSR_GPSR(IP2SR2_7_4, PWM5),
951
952 PINMUX_IPSR_GPSR(IP2SR2_11_8, CANFD7_TX),
953 PINMUX_IPSR_GPSR(IP2SR2_11_8, PWM6),
954
955 PINMUX_IPSR_GPSR(IP2SR2_15_12, CANFD7_RX),
956 PINMUX_IPSR_GPSR(IP2SR2_15_12, PWM7),
957
958 /* IP0SR3 */
959 PINMUX_IPSR_GPSR(IP0SR3_3_0, MMC_SD_D1),
960 PINMUX_IPSR_GPSR(IP0SR3_7_4, MMC_SD_D0),
961 PINMUX_IPSR_GPSR(IP0SR3_11_8, MMC_SD_D2),
962 PINMUX_IPSR_GPSR(IP0SR3_15_12, MMC_SD_CLK),
963 PINMUX_IPSR_GPSR(IP0SR3_19_16, MMC_DS),
964 PINMUX_IPSR_GPSR(IP0SR3_23_20, MMC_SD_D3),
965 PINMUX_IPSR_GPSR(IP0SR3_27_24, MMC_D5),
966 PINMUX_IPSR_GPSR(IP0SR3_31_28, MMC_D4),
967
968 /* IP1SR3 */
969 PINMUX_IPSR_GPSR(IP1SR3_3_0, MMC_D7),
970
971 PINMUX_IPSR_GPSR(IP1SR3_7_4, MMC_D6),
972
973 PINMUX_IPSR_GPSR(IP1SR3_11_8, MMC_SD_CMD),
974
975 PINMUX_IPSR_GPSR(IP1SR3_15_12, SD_CD),
976
977 PINMUX_IPSR_GPSR(IP1SR3_19_16, SD_WP),
978
979 PINMUX_IPSR_GPSR(IP1SR3_23_20, IPC_CLKIN),
980 PINMUX_IPSR_GPSR(IP1SR3_23_20, IPC_CLKEN_IN),
981 PINMUX_IPSR_GPSR(IP1SR3_23_20, PWM1_A),
982 PINMUX_IPSR_GPSR(IP1SR3_23_20, TCLK3_A),
983
984 PINMUX_IPSR_GPSR(IP1SR3_27_24, IPC_CLKOUT),
985 PINMUX_IPSR_GPSR(IP1SR3_27_24, IPC_CLKEN_OUT),
986 PINMUX_IPSR_GPSR(IP1SR3_27_24, ERROROUTC_N_A),
987 PINMUX_IPSR_GPSR(IP1SR3_27_24, TCLK4_A),
988
989 PINMUX_IPSR_GPSR(IP1SR3_31_28, QSPI0_SSL),
990
991 /* IP2SR3 */
992 PINMUX_IPSR_GPSR(IP2SR3_3_0, QSPI0_IO3),
993 PINMUX_IPSR_GPSR(IP2SR3_7_4, QSPI0_IO2),
994 PINMUX_IPSR_GPSR(IP2SR3_11_8, QSPI0_MISO_IO1),
995 PINMUX_IPSR_GPSR(IP2SR3_15_12, QSPI0_MOSI_IO0),
996 PINMUX_IPSR_GPSR(IP2SR3_19_16, QSPI0_SPCLK),
997 PINMUX_IPSR_GPSR(IP2SR3_23_20, QSPI1_MOSI_IO0),
998 PINMUX_IPSR_GPSR(IP2SR3_27_24, QSPI1_SPCLK),
999 PINMUX_IPSR_GPSR(IP2SR3_31_28, QSPI1_MISO_IO1),
1000
1001 /* IP3SR3 */
1002 PINMUX_IPSR_GPSR(IP3SR3_3_0, QSPI1_IO2),
1003 PINMUX_IPSR_GPSR(IP3SR3_7_4, QSPI1_SSL),
1004 PINMUX_IPSR_GPSR(IP3SR3_11_8, QSPI1_IO3),
1005 PINMUX_IPSR_GPSR(IP3SR3_15_12, RPC_RESET_N),
1006 PINMUX_IPSR_GPSR(IP3SR3_19_16, RPC_WP_N),
1007 PINMUX_IPSR_GPSR(IP3SR3_23_20, RPC_INT_N),
1008
1009 /* IP0SR4 */
1010 PINMUX_IPSR_GPSR(IP0SR4_3_0, TSN0_MDIO),
1011 PINMUX_IPSR_GPSR(IP0SR4_7_4, TSN0_MDC),
1012 PINMUX_IPSR_GPSR(IP0SR4_11_8, TSN0_AVTP_PPS1),
1013 PINMUX_IPSR_GPSR(IP0SR4_15_12, TSN0_PHY_INT),
1014 PINMUX_IPSR_GPSR(IP0SR4_19_16, TSN0_LINK),
1015 PINMUX_IPSR_GPSR(IP0SR4_23_20, TSN0_AVTP_MATCH),
1016 PINMUX_IPSR_GPSR(IP0SR4_27_24, TSN0_AVTP_CAPTURE),
1017 PINMUX_IPSR_GPSR(IP0SR4_31_28, TSN0_RX_CTL),
1018
1019 /* IP1SR4 */
1020 PINMUX_IPSR_GPSR(IP1SR4_3_0, TSN0_AVTP_PPS0),
1021 PINMUX_IPSR_GPSR(IP1SR4_7_4, TSN0_TX_CTL),
1022 PINMUX_IPSR_GPSR(IP1SR4_11_8, TSN0_RD0),
1023 PINMUX_IPSR_GPSR(IP1SR4_15_12, TSN0_RXC),
1024 PINMUX_IPSR_GPSR(IP1SR4_19_16, TSN0_TXC),
1025 PINMUX_IPSR_GPSR(IP1SR4_23_20, TSN0_RD1),
1026 PINMUX_IPSR_GPSR(IP1SR4_27_24, TSN0_TD1),
1027 PINMUX_IPSR_GPSR(IP1SR4_31_28, TSN0_TD0),
1028
1029 /* IP2SR4 */
1030 PINMUX_IPSR_GPSR(IP2SR4_3_0, TSN0_RD3),
1031 PINMUX_IPSR_GPSR(IP2SR4_7_4, TSN0_RD2),
1032 PINMUX_IPSR_GPSR(IP2SR4_11_8, TSN0_TD3),
1033 PINMUX_IPSR_GPSR(IP2SR4_15_12, TSN0_TD2),
1034 PINMUX_IPSR_GPSR(IP2SR4_19_16, TSN0_TXCREFCLK),
1035 PINMUX_IPSR_GPSR(IP2SR4_23_20, PCIE0_CLKREQ_N),
1036 PINMUX_IPSR_GPSR(IP2SR4_27_24, PCIE1_CLKREQ_N),
1037 PINMUX_IPSR_GPSR(IP2SR4_31_28, AVS0),
1038
1039 /* IP3SR4 */
1040 PINMUX_IPSR_GPSR(IP3SR4_3_0, AVS1),
1041
1042 /* IP0SR5 */
1043 PINMUX_IPSR_GPSR(IP0SR5_3_0, AVB2_AVTP_PPS),
1044 PINMUX_IPSR_GPSR(IP0SR5_7_4, AVB2_AVTP_CAPTURE),
1045 PINMUX_IPSR_GPSR(IP0SR5_11_8, AVB2_AVTP_MATCH),
1046 PINMUX_IPSR_GPSR(IP0SR5_15_12, AVB2_LINK),
1047 PINMUX_IPSR_GPSR(IP0SR5_19_16, AVB2_PHY_INT),
1048 PINMUX_IPSR_GPSR(IP0SR5_23_20, AVB2_MAGIC),
1049 PINMUX_IPSR_GPSR(IP0SR5_27_24, AVB2_MDC),
1050 PINMUX_IPSR_GPSR(IP0SR5_31_28, AVB2_TXCREFCLK),
1051
1052 /* IP1SR5 */
1053 PINMUX_IPSR_GPSR(IP1SR5_3_0, AVB2_TD3),
1054 PINMUX_IPSR_GPSR(IP1SR5_7_4, AVB2_RD3),
1055 PINMUX_IPSR_GPSR(IP1SR5_11_8, AVB2_MDIO),
1056 PINMUX_IPSR_GPSR(IP1SR5_15_12, AVB2_TD2),
1057 PINMUX_IPSR_GPSR(IP1SR5_19_16, AVB2_TD1),
1058 PINMUX_IPSR_GPSR(IP1SR5_23_20, AVB2_RD2),
1059 PINMUX_IPSR_GPSR(IP1SR5_27_24, AVB2_RD1),
1060 PINMUX_IPSR_GPSR(IP1SR5_31_28, AVB2_TD0),
1061
1062 /* IP2SR5 */
1063 PINMUX_IPSR_GPSR(IP2SR5_3_0, AVB2_TXC),
1064 PINMUX_IPSR_GPSR(IP2SR5_7_4, AVB2_RD0),
1065 PINMUX_IPSR_GPSR(IP2SR5_11_8, AVB2_RXC),
1066 PINMUX_IPSR_GPSR(IP2SR5_15_12, AVB2_TX_CTL),
1067 PINMUX_IPSR_GPSR(IP2SR5_19_16, AVB2_RX_CTL),
1068
1069 /* IP0SR6 */
1070 PINMUX_IPSR_GPSR(IP0SR6_3_0, AVB1_MDIO),
1071
1072 PINMUX_IPSR_GPSR(IP0SR6_7_4, AVB1_MAGIC),
1073
1074 PINMUX_IPSR_GPSR(IP0SR6_11_8, AVB1_MDC),
1075
1076 PINMUX_IPSR_GPSR(IP0SR6_15_12, AVB1_PHY_INT),
1077
1078 PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_LINK),
1079 PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_MII_TX_ER),
1080
1081 PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_AVTP_MATCH),
1082 PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_MII_RX_ER),
1083
1084 PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_TXC),
1085 PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_MII_TXC),
1086
1087 PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_TX_CTL),
1088 PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_MII_TX_EN),
1089
1090 /* IP1SR6 */
1091 PINMUX_IPSR_GPSR(IP1SR6_3_0, AVB1_RXC),
1092 PINMUX_IPSR_GPSR(IP1SR6_3_0, AVB1_MII_RXC),
1093
1094 PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_RX_CTL),
1095 PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_MII_RX_DV),
1096
1097 PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_AVTP_PPS),
1098 PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_MII_COL),
1099
1100 PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_AVTP_CAPTURE),
1101 PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_MII_CRS),
1102
1103 PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_TD1),
1104 PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_MII_TD1),
1105
1106 PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_TD0),
1107 PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_MII_TD0),
1108
1109 PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_RD1),
1110 PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_MII_RD1),
1111
1112 PINMUX_IPSR_GPSR(IP1SR6_31_28, AVB1_RD0),
1113 PINMUX_IPSR_GPSR(IP1SR6_31_28, AVB1_MII_RD0),
1114
1115 /* IP2SR6 */
1116 PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_TD2),
1117 PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_MII_TD2),
1118
1119 PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_RD2),
1120 PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_MII_RD2),
1121
1122 PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_TD3),
1123 PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_MII_TD3),
1124
1125 PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_RD3),
1126 PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_MII_RD3),
1127
1128 PINMUX_IPSR_GPSR(IP2SR6_19_16, AVB1_TXCREFCLK),
1129
1130 /* IP0SR7 */
1131 PINMUX_IPSR_GPSR(IP0SR7_3_0, AVB0_AVTP_PPS),
1132 PINMUX_IPSR_GPSR(IP0SR7_3_0, AVB0_MII_COL),
1133
1134 PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_AVTP_CAPTURE),
1135 PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_MII_CRS),
1136
1137 PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_AVTP_MATCH),
1138 PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_MII_RX_ER),
1139 PINMUX_IPSR_GPSR(IP0SR7_11_8, CC5_OSCOUT),
1140
1141 PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_TD3),
1142 PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_MII_TD3),
1143
1144 PINMUX_IPSR_GPSR(IP0SR7_19_16, AVB0_LINK),
1145 PINMUX_IPSR_GPSR(IP0SR7_19_16, AVB0_MII_TX_ER),
1146
1147 PINMUX_IPSR_GPSR(IP0SR7_23_20, AVB0_PHY_INT),
1148
1149 PINMUX_IPSR_GPSR(IP0SR7_27_24, AVB0_TD2),
1150 PINMUX_IPSR_GPSR(IP0SR7_27_24, AVB0_MII_TD2),
1151
1152 PINMUX_IPSR_GPSR(IP0SR7_31_28, AVB0_TD1),
1153 PINMUX_IPSR_GPSR(IP0SR7_31_28, AVB0_MII_TD1),
1154
1155 /* IP1SR7 */
1156 PINMUX_IPSR_GPSR(IP1SR7_3_0, AVB0_RD3),
1157 PINMUX_IPSR_GPSR(IP1SR7_3_0, AVB0_MII_RD3),
1158
1159 PINMUX_IPSR_GPSR(IP1SR7_7_4, AVB0_TXCREFCLK),
1160
1161 PINMUX_IPSR_GPSR(IP1SR7_11_8, AVB0_MAGIC),
1162
1163 PINMUX_IPSR_GPSR(IP1SR7_15_12, AVB0_TD0),
1164 PINMUX_IPSR_GPSR(IP1SR7_15_12, AVB0_MII_TD0),
1165
1166 PINMUX_IPSR_GPSR(IP1SR7_19_16, AVB0_RD2),
1167 PINMUX_IPSR_GPSR(IP1SR7_19_16, AVB0_MII_RD2),
1168
1169 PINMUX_IPSR_GPSR(IP1SR7_23_20, AVB0_MDC),
1170
1171 PINMUX_IPSR_GPSR(IP1SR7_27_24, AVB0_MDIO),
1172
1173 PINMUX_IPSR_GPSR(IP1SR7_31_28, AVB0_TXC),
1174 PINMUX_IPSR_GPSR(IP1SR7_31_28, AVB0_MII_TXC),
1175
1176 /* IP2SR7 */
1177 PINMUX_IPSR_GPSR(IP2SR7_3_0, AVB0_TX_CTL),
1178 PINMUX_IPSR_GPSR(IP2SR7_3_0, AVB0_MII_TX_EN),
1179
1180 PINMUX_IPSR_GPSR(IP2SR7_7_4, AVB0_RD1),
1181 PINMUX_IPSR_GPSR(IP2SR7_7_4, AVB0_MII_RD1),
1182
1183 PINMUX_IPSR_GPSR(IP2SR7_11_8, AVB0_RD0),
1184 PINMUX_IPSR_GPSR(IP2SR7_11_8, AVB0_MII_RD0),
1185
1186 PINMUX_IPSR_GPSR(IP2SR7_15_12, AVB0_RXC),
1187 PINMUX_IPSR_GPSR(IP2SR7_15_12, AVB0_MII_RXC),
1188
1189 PINMUX_IPSR_GPSR(IP2SR7_19_16, AVB0_RX_CTL),
1190 PINMUX_IPSR_GPSR(IP2SR7_19_16, AVB0_MII_RX_DV),
1191
1192 /* IP0SR8 */
1193 PINMUX_IPSR_MSEL(IP0SR8_3_0, SCL0, SEL_SCL0_0),
1194 PINMUX_IPSR_MSEL(IP0SR8_7_4, SDA0, SEL_SDA0_0),
1195 PINMUX_IPSR_MSEL(IP0SR8_11_8, SCL1, SEL_SCL1_0),
1196 PINMUX_IPSR_MSEL(IP0SR8_15_12, SDA1, SEL_SDA1_0),
1197 PINMUX_IPSR_MSEL(IP0SR8_19_16, SCL2, SEL_SCL2_0),
1198 PINMUX_IPSR_MSEL(IP0SR8_23_20, SDA2, SEL_SDA2_0),
1199 PINMUX_IPSR_MSEL(IP0SR8_27_24, SCL3, SEL_SCL3_0),
1200 PINMUX_IPSR_MSEL(IP0SR8_31_28, SDA3, SEL_SDA3_0),
1201
1202 /* IP1SR8 */
1203 PINMUX_IPSR_MSEL(IP1SR8_3_0, SCL4, SEL_SCL4_0),
1204 PINMUX_IPSR_MSEL(IP1SR8_3_0, HRX2, SEL_SCL4_0),
1205 PINMUX_IPSR_MSEL(IP1SR8_3_0, SCK4, SEL_SCL4_0),
1206
1207 PINMUX_IPSR_MSEL(IP1SR8_7_4, SDA4, SEL_SDA4_0),
1208 PINMUX_IPSR_MSEL(IP1SR8_7_4, HTX2, SEL_SDA4_0),
1209 PINMUX_IPSR_MSEL(IP1SR8_7_4, CTS4_N, SEL_SDA4_0),
1210
1211 PINMUX_IPSR_MSEL(IP1SR8_11_8, SCL5, SEL_SCL5_0),
1212 PINMUX_IPSR_MSEL(IP1SR8_11_8, HRTS2_N, SEL_SCL5_0),
1213 PINMUX_IPSR_MSEL(IP1SR8_11_8, RTS4_N, SEL_SCL5_0),
1214
1215 PINMUX_IPSR_MSEL(IP1SR8_15_12, SDA5, SEL_SDA5_0),
1216 PINMUX_IPSR_MSEL(IP1SR8_15_12, SCIF_CLK2, SEL_SDA5_0),
1217
1218 PINMUX_IPSR_GPSR(IP1SR8_19_16, HCTS2_N),
1219 PINMUX_IPSR_GPSR(IP1SR8_19_16, TX4),
1220
1221 PINMUX_IPSR_GPSR(IP1SR8_23_20, HSCK2),
1222 PINMUX_IPSR_GPSR(IP1SR8_23_20, RX4),
1223 };
1224
1225 /*
1226 * Pins not associated with a GPIO port.
1227 */
1228 enum {
1229 GP_ASSIGN_LAST(),
1230 NOGP_ALL(),
1231 };
1232
1233 static const struct sh_pfc_pin pinmux_pins[] = {
1234 PINMUX_GPIO_GP_ALL(),
1235 PINMUX_NOGP_ALL(),
1236 };
1237
1238 /* - AUDIO CLOCK ----------------------------------------- */
1239 static const unsigned int audio_clkin_pins[] = {
1240 /* CLK IN */
1241 RCAR_GP_PIN(1, 22),
1242 };
1243 static const unsigned int audio_clkin_mux[] = {
1244 AUDIO_CLKIN_MARK,
1245 };
1246 static const unsigned int audio_clkout_pins[] = {
1247 /* CLK OUT */
1248 RCAR_GP_PIN(1, 21),
1249 };
1250 static const unsigned int audio_clkout_mux[] = {
1251 AUDIO_CLKOUT_MARK,
1252 };
1253
1254 /* - AVB0 ------------------------------------------------ */
1255 static const unsigned int avb0_link_pins[] = {
1256 /* AVB0_LINK */
1257 RCAR_GP_PIN(7, 4),
1258 };
1259 static const unsigned int avb0_link_mux[] = {
1260 AVB0_LINK_MARK,
1261 };
1262 static const unsigned int avb0_magic_pins[] = {
1263 /* AVB0_MAGIC */
1264 RCAR_GP_PIN(7, 10),
1265 };
1266 static const unsigned int avb0_magic_mux[] = {
1267 AVB0_MAGIC_MARK,
1268 };
1269 static const unsigned int avb0_phy_int_pins[] = {
1270 /* AVB0_PHY_INT */
1271 RCAR_GP_PIN(7, 5),
1272 };
1273 static const unsigned int avb0_phy_int_mux[] = {
1274 AVB0_PHY_INT_MARK,
1275 };
1276 static const unsigned int avb0_mdio_pins[] = {
1277 /* AVB0_MDC, AVB0_MDIO */
1278 RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14),
1279 };
1280 static const unsigned int avb0_mdio_mux[] = {
1281 AVB0_MDC_MARK, AVB0_MDIO_MARK,
1282 };
1283 static const unsigned int avb0_rgmii_pins[] = {
1284 /*
1285 * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,
1286 * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3,
1287 */
1288 RCAR_GP_PIN(7, 16), RCAR_GP_PIN(7, 15),
1289 RCAR_GP_PIN(7, 11), RCAR_GP_PIN(7, 7),
1290 RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 3),
1291 RCAR_GP_PIN(7, 20), RCAR_GP_PIN(7, 19),
1292 RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),
1293 RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 8),
1294 };
1295 static const unsigned int avb0_rgmii_mux[] = {
1296 AVB0_TX_CTL_MARK, AVB0_TXC_MARK,
1297 AVB0_TD0_MARK, AVB0_TD1_MARK,
1298 AVB0_TD2_MARK, AVB0_TD3_MARK,
1299 AVB0_RX_CTL_MARK, AVB0_RXC_MARK,
1300 AVB0_RD0_MARK, AVB0_RD1_MARK,
1301 AVB0_RD2_MARK, AVB0_RD3_MARK,
1302 };
1303 static const unsigned int avb0_txcrefclk_pins[] = {
1304 /* AVB0_TXCREFCLK */
1305 RCAR_GP_PIN(7, 9),
1306 };
1307 static const unsigned int avb0_txcrefclk_mux[] = {
1308 AVB0_TXCREFCLK_MARK,
1309 };
1310 static const unsigned int avb0_avtp_pps_pins[] = {
1311 /* AVB0_AVTP_PPS */
1312 RCAR_GP_PIN(7, 0),
1313 };
1314 static const unsigned int avb0_avtp_pps_mux[] = {
1315 AVB0_AVTP_PPS_MARK,
1316 };
1317 static const unsigned int avb0_avtp_capture_pins[] = {
1318 /* AVB0_AVTP_CAPTURE */
1319 RCAR_GP_PIN(7, 1),
1320 };
1321 static const unsigned int avb0_avtp_capture_mux[] = {
1322 AVB0_AVTP_CAPTURE_MARK,
1323 };
1324 static const unsigned int avb0_avtp_match_pins[] = {
1325 /* AVB0_AVTP_MATCH */
1326 RCAR_GP_PIN(7, 2),
1327 };
1328 static const unsigned int avb0_avtp_match_mux[] = {
1329 AVB0_AVTP_MATCH_MARK,
1330 };
1331
1332 /* - AVB1 ------------------------------------------------ */
1333 static const unsigned int avb1_link_pins[] = {
1334 /* AVB1_LINK */
1335 RCAR_GP_PIN(6, 4),
1336 };
1337 static const unsigned int avb1_link_mux[] = {
1338 AVB1_LINK_MARK,
1339 };
1340 static const unsigned int avb1_magic_pins[] = {
1341 /* AVB1_MAGIC */
1342 RCAR_GP_PIN(6, 1),
1343 };
1344 static const unsigned int avb1_magic_mux[] = {
1345 AVB1_MAGIC_MARK,
1346 };
1347 static const unsigned int avb1_phy_int_pins[] = {
1348 /* AVB1_PHY_INT */
1349 RCAR_GP_PIN(6, 3),
1350 };
1351 static const unsigned int avb1_phy_int_mux[] = {
1352 AVB1_PHY_INT_MARK,
1353 };
1354 static const unsigned int avb1_mdio_pins[] = {
1355 /* AVB1_MDC, AVB1_MDIO */
1356 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 0),
1357 };
1358 static const unsigned int avb1_mdio_mux[] = {
1359 AVB1_MDC_MARK, AVB1_MDIO_MARK,
1360 };
1361 static const unsigned int avb1_rgmii_pins[] = {
1362 /*
1363 * AVB1_TX_CTL, AVB1_TXC, AVB1_TD0, AVB1_TD1, AVB1_TD2, AVB1_TD3,
1364 * AVB1_RX_CTL, AVB1_RXC, AVB1_RD0, AVB1_RD1, AVB1_RD2, AVB1_RD3,
1365 */
1366 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
1367 RCAR_GP_PIN(6, 13), RCAR_GP_PIN(6, 12),
1368 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 18),
1369 RCAR_GP_PIN(6, 9), RCAR_GP_PIN(6, 8),
1370 RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14),
1371 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 19),
1372 };
1373 static const unsigned int avb1_rgmii_mux[] = {
1374 AVB1_TX_CTL_MARK, AVB1_TXC_MARK,
1375 AVB1_TD0_MARK, AVB1_TD1_MARK,
1376 AVB1_TD2_MARK, AVB1_TD3_MARK,
1377 AVB1_RX_CTL_MARK, AVB1_RXC_MARK,
1378 AVB1_RD0_MARK, AVB1_RD1_MARK,
1379 AVB1_RD2_MARK, AVB1_RD3_MARK,
1380 };
1381 static const unsigned int avb1_txcrefclk_pins[] = {
1382 /* AVB1_TXCREFCLK */
1383 RCAR_GP_PIN(6, 20),
1384 };
1385 static const unsigned int avb1_txcrefclk_mux[] = {
1386 AVB1_TXCREFCLK_MARK,
1387 };
1388 static const unsigned int avb1_avtp_pps_pins[] = {
1389 /* AVB1_AVTP_PPS */
1390 RCAR_GP_PIN(6, 10),
1391 };
1392 static const unsigned int avb1_avtp_pps_mux[] = {
1393 AVB1_AVTP_PPS_MARK,
1394 };
1395 static const unsigned int avb1_avtp_capture_pins[] = {
1396 /* AVB1_AVTP_CAPTURE */
1397 RCAR_GP_PIN(6, 11),
1398 };
1399 static const unsigned int avb1_avtp_capture_mux[] = {
1400 AVB1_AVTP_CAPTURE_MARK,
1401 };
1402 static const unsigned int avb1_avtp_match_pins[] = {
1403 /* AVB1_AVTP_MATCH */
1404 RCAR_GP_PIN(6, 5),
1405 };
1406 static const unsigned int avb1_avtp_match_mux[] = {
1407 AVB1_AVTP_MATCH_MARK,
1408 };
1409
1410 /* - AVB2 ------------------------------------------------ */
1411 static const unsigned int avb2_link_pins[] = {
1412 /* AVB2_LINK */
1413 RCAR_GP_PIN(5, 3),
1414 };
1415 static const unsigned int avb2_link_mux[] = {
1416 AVB2_LINK_MARK,
1417 };
1418 static const unsigned int avb2_magic_pins[] = {
1419 /* AVB2_MAGIC */
1420 RCAR_GP_PIN(5, 5),
1421 };
1422 static const unsigned int avb2_magic_mux[] = {
1423 AVB2_MAGIC_MARK,
1424 };
1425 static const unsigned int avb2_phy_int_pins[] = {
1426 /* AVB2_PHY_INT */
1427 RCAR_GP_PIN(5, 4),
1428 };
1429 static const unsigned int avb2_phy_int_mux[] = {
1430 AVB2_PHY_INT_MARK,
1431 };
1432 static const unsigned int avb2_mdio_pins[] = {
1433 /* AVB2_MDC, AVB2_MDIO */
1434 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 10),
1435 };
1436 static const unsigned int avb2_mdio_mux[] = {
1437 AVB2_MDC_MARK, AVB2_MDIO_MARK,
1438 };
1439 static const unsigned int avb2_rgmii_pins[] = {
1440 /*
1441 * AVB2_TX_CTL, AVB2_TXC, AVB2_TD0, AVB2_TD1, AVB2_TD2, AVB2_TD3,
1442 * AVB2_RX_CTL, AVB2_RXC, AVB2_RD0, AVB2_RD1, AVB2_RD2, AVB2_RD3,
1443 */
1444 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 16),
1445 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 12),
1446 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 8),
1447 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 18),
1448 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 14),
1449 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 9),
1450 };
1451 static const unsigned int avb2_rgmii_mux[] = {
1452 AVB2_TX_CTL_MARK, AVB2_TXC_MARK,
1453 AVB2_TD0_MARK, AVB2_TD1_MARK,
1454 AVB2_TD2_MARK, AVB2_TD3_MARK,
1455 AVB2_RX_CTL_MARK, AVB2_RXC_MARK,
1456 AVB2_RD0_MARK, AVB2_RD1_MARK,
1457 AVB2_RD2_MARK, AVB2_RD3_MARK,
1458 };
1459 static const unsigned int avb2_txcrefclk_pins[] = {
1460 /* AVB2_TXCREFCLK */
1461 RCAR_GP_PIN(5, 7),
1462 };
1463 static const unsigned int avb2_txcrefclk_mux[] = {
1464 AVB2_TXCREFCLK_MARK,
1465 };
1466 static const unsigned int avb2_avtp_pps_pins[] = {
1467 /* AVB2_AVTP_PPS */
1468 RCAR_GP_PIN(5, 0),
1469 };
1470 static const unsigned int avb2_avtp_pps_mux[] = {
1471 AVB2_AVTP_PPS_MARK,
1472 };
1473 static const unsigned int avb2_avtp_capture_pins[] = {
1474 /* AVB2_AVTP_CAPTURE */
1475 RCAR_GP_PIN(5, 1),
1476 };
1477 static const unsigned int avb2_avtp_capture_mux[] = {
1478 AVB2_AVTP_CAPTURE_MARK,
1479 };
1480 static const unsigned int avb2_avtp_match_pins[] = {
1481 /* AVB2_AVTP_MATCH */
1482 RCAR_GP_PIN(5, 2),
1483 };
1484 static const unsigned int avb2_avtp_match_mux[] = {
1485 AVB2_AVTP_MATCH_MARK,
1486 };
1487
1488 /* - CANFD0 ----------------------------------------------------------------- */
1489 static const unsigned int canfd0_data_pins[] = {
1490 /* CANFD0_TX, CANFD0_RX */
1491 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1492 };
1493 static const unsigned int canfd0_data_mux[] = {
1494 CANFD0_TX_MARK, CANFD0_RX_MARK,
1495 };
1496
1497 /* - CANFD1 ----------------------------------------------------------------- */
1498 static const unsigned int canfd1_data_pins[] = {
1499 /* CANFD1_TX, CANFD1_RX */
1500 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1501 };
1502 static const unsigned int canfd1_data_mux[] = {
1503 CANFD1_TX_MARK, CANFD1_RX_MARK,
1504 };
1505
1506 /* - CANFD2 ----------------------------------------------------------------- */
1507 static const unsigned int canfd2_data_pins[] = {
1508 /* CANFD2_TX, CANFD2_RX */
1509 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1510 };
1511 static const unsigned int canfd2_data_mux[] = {
1512 CANFD2_TX_MARK, CANFD2_RX_MARK,
1513 };
1514
1515 /* - CANFD3 ----------------------------------------------------------------- */
1516 static const unsigned int canfd3_data_pins[] = {
1517 /* CANFD3_TX, CANFD3_RX */
1518 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1519 };
1520 static const unsigned int canfd3_data_mux[] = {
1521 CANFD3_TX_MARK, CANFD3_RX_MARK,
1522 };
1523
1524 /* - CANFD4 ----------------------------------------------------------------- */
1525 static const unsigned int canfd4_data_pins[] = {
1526 /* CANFD4_TX, CANFD4_RX */
1527 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
1528 };
1529 static const unsigned int canfd4_data_mux[] = {
1530 CANFD4_TX_MARK, CANFD4_RX_MARK,
1531 };
1532
1533 /* - CANFD5 ----------------------------------------------------------------- */
1534 static const unsigned int canfd5_data_a_pins[] = {
1535 /* CANFD5_TX_A, CANFD5_RX_A */
1536 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
1537 };
1538 static const unsigned int canfd5_data_a_mux[] = {
1539 CANFD5_TX_A_MARK, CANFD5_RX_A_MARK,
1540 };
1541
1542 static const unsigned int canfd5_data_b_pins[] = {
1543 /* CANFD5_TX_B, CANFD5_RX_B */
1544 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
1545 };
1546 static const unsigned int canfd5_data_b_mux[] = {
1547 CANFD5_TX_B_MARK, CANFD5_RX_B_MARK,
1548 };
1549
1550 /* - CANFD6 ----------------------------------------------------------------- */
1551 static const unsigned int canfd6_data_pins[] = {
1552 /* CANFD6_TX, CANFD6_RX */
1553 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
1554 };
1555 static const unsigned int canfd6_data_mux[] = {
1556 CANFD6_TX_MARK, CANFD6_RX_MARK,
1557 };
1558
1559 /* - CANFD7 ----------------------------------------------------------------- */
1560 static const unsigned int canfd7_data_pins[] = {
1561 /* CANFD7_TX, CANFD7_RX */
1562 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
1563 };
1564 static const unsigned int canfd7_data_mux[] = {
1565 CANFD7_TX_MARK, CANFD7_RX_MARK,
1566 };
1567
1568 /* - CANFD Clock ------------------------------------------------------------ */
1569 static const unsigned int can_clk_pins[] = {
1570 /* CAN_CLK */
1571 RCAR_GP_PIN(2, 9),
1572 };
1573 static const unsigned int can_clk_mux[] = {
1574 CAN_CLK_MARK,
1575 };
1576
1577 /* - HSCIF0 ----------------------------------------------------------------- */
1578 static const unsigned int hscif0_data_pins[] = {
1579 /* HRX0, HTX0 */
1580 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12),
1581 };
1582 static const unsigned int hscif0_data_mux[] = {
1583 HRX0_MARK, HTX0_MARK,
1584 };
1585 static const unsigned int hscif0_clk_pins[] = {
1586 /* HSCK0 */
1587 RCAR_GP_PIN(1, 15),
1588 };
1589 static const unsigned int hscif0_clk_mux[] = {
1590 HSCK0_MARK,
1591 };
1592 static const unsigned int hscif0_ctrl_pins[] = {
1593 /* HRTS0_N, HCTS0_N */
1594 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1595 };
1596 static const unsigned int hscif0_ctrl_mux[] = {
1597 HRTS0_N_MARK, HCTS0_N_MARK,
1598 };
1599
1600 /* - HSCIF1 ----------------------------------------------------------------- */
1601 static const unsigned int hscif1_data_a_pins[] = {
1602 /* HRX1_A, HTX1_A */
1603 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
1604 };
1605 static const unsigned int hscif1_data_a_mux[] = {
1606 HRX1_A_MARK, HTX1_A_MARK,
1607 };
1608 static const unsigned int hscif1_clk_a_pins[] = {
1609 /* HSCK1_A */
1610 RCAR_GP_PIN(0, 18),
1611 };
1612 static const unsigned int hscif1_clk_a_mux[] = {
1613 HSCK1_A_MARK,
1614 };
1615 static const unsigned int hscif1_ctrl_a_pins[] = {
1616 /* HRTS1_N_A, HCTS1_N_A */
1617 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
1618 };
1619 static const unsigned int hscif1_ctrl_a_mux[] = {
1620 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
1621 };
1622
1623 static const unsigned int hscif1_data_b_pins[] = {
1624 /* HRX1_B, HTX1_B */
1625 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
1626 };
1627 static const unsigned int hscif1_data_b_mux[] = {
1628 HRX1_B_MARK, HTX1_B_MARK,
1629 };
1630 static const unsigned int hscif1_clk_b_pins[] = {
1631 /* HSCK1_B */
1632 RCAR_GP_PIN(1, 10),
1633 };
1634 static const unsigned int hscif1_clk_b_mux[] = {
1635 HSCK1_B_MARK,
1636 };
1637 static const unsigned int hscif1_ctrl_b_pins[] = {
1638 /* HRTS1_N_B, HCTS1_N_B */
1639 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
1640 };
1641 static const unsigned int hscif1_ctrl_b_mux[] = {
1642 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
1643 };
1644
1645 /* - HSCIF2 ----------------------------------------------------------------- */
1646 static const unsigned int hscif2_data_pins[] = {
1647 /* HRX2, HTX2 */
1648 RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
1649 };
1650 static const unsigned int hscif2_data_mux[] = {
1651 HRX2_MARK, HTX2_MARK,
1652 };
1653 static const unsigned int hscif2_clk_pins[] = {
1654 /* HSCK2 */
1655 RCAR_GP_PIN(8, 13),
1656 };
1657 static const unsigned int hscif2_clk_mux[] = {
1658 HSCK2_MARK,
1659 };
1660 static const unsigned int hscif2_ctrl_pins[] = {
1661 /* HRTS2_N, HCTS2_N */
1662 RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 12),
1663 };
1664 static const unsigned int hscif2_ctrl_mux[] = {
1665 HRTS2_N_MARK, HCTS2_N_MARK,
1666 };
1667
1668 /* - HSCIF3 ----------------------------------------------------------------- */
1669 static const unsigned int hscif3_data_a_pins[] = {
1670 /* HRX3_A, HTX3_A */
1671 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 28),
1672 };
1673 static const unsigned int hscif3_data_a_mux[] = {
1674 HRX3_A_MARK, HTX3_A_MARK,
1675 };
1676 static const unsigned int hscif3_clk_a_pins[] = {
1677 /* HSCK3_A */
1678 RCAR_GP_PIN(1, 25),
1679 };
1680 static const unsigned int hscif3_clk_a_mux[] = {
1681 HSCK3_A_MARK,
1682 };
1683 static const unsigned int hscif3_ctrl_a_pins[] = {
1684 /* HRTS3_N_A, HCTS3_N_A */
1685 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27),
1686 };
1687 static const unsigned int hscif3_ctrl_a_mux[] = {
1688 HRTS3_N_A_MARK, HCTS3_N_A_MARK,
1689 };
1690
1691 static const unsigned int hscif3_data_b_pins[] = {
1692 /* HRX3_B, HTX3_B */
1693 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0),
1694 };
1695 static const unsigned int hscif3_data_b_mux[] = {
1696 HRX3_B_MARK, HTX3_B_MARK,
1697 };
1698 static const unsigned int hscif3_clk_b_pins[] = {
1699 /* HSCK3_B */
1700 RCAR_GP_PIN(1, 3),
1701 };
1702 static const unsigned int hscif3_clk_b_mux[] = {
1703 HSCK3_B_MARK,
1704 };
1705 static const unsigned int hscif3_ctrl_b_pins[] = {
1706 /* HRTS3_N_B, HCTS3_N_B */
1707 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
1708 };
1709 static const unsigned int hscif3_ctrl_b_mux[] = {
1710 HRTS3_N_B_MARK, HCTS3_N_B_MARK,
1711 };
1712
1713 /* - I2C0 ------------------------------------------------------------------- */
1714 static const unsigned int i2c0_pins[] = {
1715 /* SDA0, SCL0 */
1716 RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 0),
1717 };
1718 static const unsigned int i2c0_mux[] = {
1719 SDA0_MARK, SCL0_MARK,
1720 };
1721
1722 /* - I2C1 ------------------------------------------------------------------- */
1723 static const unsigned int i2c1_pins[] = {
1724 /* SDA1, SCL1 */
1725 RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 2),
1726 };
1727 static const unsigned int i2c1_mux[] = {
1728 SDA1_MARK, SCL1_MARK,
1729 };
1730
1731 /* - I2C2 ------------------------------------------------------------------- */
1732 static const unsigned int i2c2_pins[] = {
1733 /* SDA2, SCL2 */
1734 RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 4),
1735 };
1736 static const unsigned int i2c2_mux[] = {
1737 SDA2_MARK, SCL2_MARK,
1738 };
1739
1740 /* - I2C3 ------------------------------------------------------------------- */
1741 static const unsigned int i2c3_pins[] = {
1742 /* SDA3, SCL3 */
1743 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 6),
1744 };
1745 static const unsigned int i2c3_mux[] = {
1746 SDA3_MARK, SCL3_MARK,
1747 };
1748
1749 /* - I2C4 ------------------------------------------------------------------- */
1750 static const unsigned int i2c4_pins[] = {
1751 /* SDA4, SCL4 */
1752 RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 8),
1753 };
1754 static const unsigned int i2c4_mux[] = {
1755 SDA4_MARK, SCL4_MARK,
1756 };
1757
1758 /* - I2C5 ------------------------------------------------------------------- */
1759 static const unsigned int i2c5_pins[] = {
1760 /* SDA5, SCL5 */
1761 RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 10),
1762 };
1763 static const unsigned int i2c5_mux[] = {
1764 SDA5_MARK, SCL5_MARK,
1765 };
1766
1767 /* - MMC -------------------------------------------------------------------- */
1768 static const unsigned int mmc_data_pins[] = {
1769 /* MMC_SD_D[0:3], MMC_D[4:7] */
1770 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
1771 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 5),
1772 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6),
1773 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
1774 };
1775 static const unsigned int mmc_data_mux[] = {
1776 MMC_SD_D0_MARK, MMC_SD_D1_MARK,
1777 MMC_SD_D2_MARK, MMC_SD_D3_MARK,
1778 MMC_D4_MARK, MMC_D5_MARK,
1779 MMC_D6_MARK, MMC_D7_MARK,
1780 };
1781 static const unsigned int mmc_ctrl_pins[] = {
1782 /* MMC_SD_CLK, MMC_SD_CMD */
1783 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 10),
1784 };
1785 static const unsigned int mmc_ctrl_mux[] = {
1786 MMC_SD_CLK_MARK, MMC_SD_CMD_MARK,
1787 };
1788 static const unsigned int mmc_cd_pins[] = {
1789 /* SD_CD */
1790 RCAR_GP_PIN(3, 11),
1791 };
1792 static const unsigned int mmc_cd_mux[] = {
1793 SD_CD_MARK,
1794 };
1795 static const unsigned int mmc_wp_pins[] = {
1796 /* SD_WP */
1797 RCAR_GP_PIN(3, 12),
1798 };
1799 static const unsigned int mmc_wp_mux[] = {
1800 SD_WP_MARK,
1801 };
1802 static const unsigned int mmc_ds_pins[] = {
1803 /* MMC_DS */
1804 RCAR_GP_PIN(3, 4),
1805 };
1806 static const unsigned int mmc_ds_mux[] = {
1807 MMC_DS_MARK,
1808 };
1809
1810 /* - MSIOF0 ----------------------------------------------------------------- */
1811 static const unsigned int msiof0_clk_pins[] = {
1812 /* MSIOF0_SCK */
1813 RCAR_GP_PIN(1, 10),
1814 };
1815 static const unsigned int msiof0_clk_mux[] = {
1816 MSIOF0_SCK_MARK,
1817 };
1818 static const unsigned int msiof0_sync_pins[] = {
1819 /* MSIOF0_SYNC */
1820 RCAR_GP_PIN(1, 8),
1821 };
1822 static const unsigned int msiof0_sync_mux[] = {
1823 MSIOF0_SYNC_MARK,
1824 };
1825 static const unsigned int msiof0_ss1_pins[] = {
1826 /* MSIOF0_SS1 */
1827 RCAR_GP_PIN(1, 7),
1828 };
1829 static const unsigned int msiof0_ss1_mux[] = {
1830 MSIOF0_SS1_MARK,
1831 };
1832 static const unsigned int msiof0_ss2_pins[] = {
1833 /* MSIOF0_SS2 */
1834 RCAR_GP_PIN(1, 6),
1835 };
1836 static const unsigned int msiof0_ss2_mux[] = {
1837 MSIOF0_SS2_MARK,
1838 };
1839 static const unsigned int msiof0_txd_pins[] = {
1840 /* MSIOF0_TXD */
1841 RCAR_GP_PIN(1, 9),
1842 };
1843 static const unsigned int msiof0_txd_mux[] = {
1844 MSIOF0_TXD_MARK,
1845 };
1846 static const unsigned int msiof0_rxd_pins[] = {
1847 /* MSIOF0_RXD */
1848 RCAR_GP_PIN(1, 11),
1849 };
1850 static const unsigned int msiof0_rxd_mux[] = {
1851 MSIOF0_RXD_MARK,
1852 };
1853
1854 /* - MSIOF1 ----------------------------------------------------------------- */
1855 static const unsigned int msiof1_clk_pins[] = {
1856 /* MSIOF1_SCK */
1857 RCAR_GP_PIN(1, 3),
1858 };
1859 static const unsigned int msiof1_clk_mux[] = {
1860 MSIOF1_SCK_MARK,
1861 };
1862 static const unsigned int msiof1_sync_pins[] = {
1863 /* MSIOF1_SYNC */
1864 RCAR_GP_PIN(1, 2),
1865 };
1866 static const unsigned int msiof1_sync_mux[] = {
1867 MSIOF1_SYNC_MARK,
1868 };
1869 static const unsigned int msiof1_ss1_pins[] = {
1870 /* MSIOF1_SS1 */
1871 RCAR_GP_PIN(1, 1),
1872 };
1873 static const unsigned int msiof1_ss1_mux[] = {
1874 MSIOF1_SS1_MARK,
1875 };
1876 static const unsigned int msiof1_ss2_pins[] = {
1877 /* MSIOF1_SS2 */
1878 RCAR_GP_PIN(1, 0),
1879 };
1880 static const unsigned int msiof1_ss2_mux[] = {
1881 MSIOF1_SS2_MARK,
1882 };
1883 static const unsigned int msiof1_txd_pins[] = {
1884 /* MSIOF1_TXD */
1885 RCAR_GP_PIN(1, 4),
1886 };
1887 static const unsigned int msiof1_txd_mux[] = {
1888 MSIOF1_TXD_MARK,
1889 };
1890 static const unsigned int msiof1_rxd_pins[] = {
1891 /* MSIOF1_RXD */
1892 RCAR_GP_PIN(1, 5),
1893 };
1894 static const unsigned int msiof1_rxd_mux[] = {
1895 MSIOF1_RXD_MARK,
1896 };
1897
1898 /* - MSIOF2 ----------------------------------------------------------------- */
1899 static const unsigned int msiof2_clk_pins[] = {
1900 /* MSIOF2_SCK */
1901 RCAR_GP_PIN(0, 17),
1902 };
1903 static const unsigned int msiof2_clk_mux[] = {
1904 MSIOF2_SCK_MARK,
1905 };
1906 static const unsigned int msiof2_sync_pins[] = {
1907 /* MSIOF2_SYNC */
1908 RCAR_GP_PIN(0, 15),
1909 };
1910 static const unsigned int msiof2_sync_mux[] = {
1911 MSIOF2_SYNC_MARK,
1912 };
1913 static const unsigned int msiof2_ss1_pins[] = {
1914 /* MSIOF2_SS1 */
1915 RCAR_GP_PIN(0, 14),
1916 };
1917 static const unsigned int msiof2_ss1_mux[] = {
1918 MSIOF2_SS1_MARK,
1919 };
1920 static const unsigned int msiof2_ss2_pins[] = {
1921 /* MSIOF2_SS2 */
1922 RCAR_GP_PIN(0, 13),
1923 };
1924 static const unsigned int msiof2_ss2_mux[] = {
1925 MSIOF2_SS2_MARK,
1926 };
1927 static const unsigned int msiof2_txd_pins[] = {
1928 /* MSIOF2_TXD */
1929 RCAR_GP_PIN(0, 16),
1930 };
1931 static const unsigned int msiof2_txd_mux[] = {
1932 MSIOF2_TXD_MARK,
1933 };
1934 static const unsigned int msiof2_rxd_pins[] = {
1935 /* MSIOF2_RXD */
1936 RCAR_GP_PIN(0, 18),
1937 };
1938 static const unsigned int msiof2_rxd_mux[] = {
1939 MSIOF2_RXD_MARK,
1940 };
1941
1942 /* - MSIOF3 ----------------------------------------------------------------- */
1943 static const unsigned int msiof3_clk_pins[] = {
1944 /* MSIOF3_SCK */
1945 RCAR_GP_PIN(0, 3),
1946 };
1947 static const unsigned int msiof3_clk_mux[] = {
1948 MSIOF3_SCK_MARK,
1949 };
1950 static const unsigned int msiof3_sync_pins[] = {
1951 /* MSIOF3_SYNC */
1952 RCAR_GP_PIN(0, 6),
1953 };
1954 static const unsigned int msiof3_sync_mux[] = {
1955 MSIOF3_SYNC_MARK,
1956 };
1957 static const unsigned int msiof3_ss1_pins[] = {
1958 /* MSIOF3_SS1 */
1959 RCAR_GP_PIN(0, 1),
1960 };
1961 static const unsigned int msiof3_ss1_mux[] = {
1962 MSIOF3_SS1_MARK,
1963 };
1964 static const unsigned int msiof3_ss2_pins[] = {
1965 /* MSIOF3_SS2 */
1966 RCAR_GP_PIN(0, 2),
1967 };
1968 static const unsigned int msiof3_ss2_mux[] = {
1969 MSIOF3_SS2_MARK,
1970 };
1971 static const unsigned int msiof3_txd_pins[] = {
1972 /* MSIOF3_TXD */
1973 RCAR_GP_PIN(0, 4),
1974 };
1975 static const unsigned int msiof3_txd_mux[] = {
1976 MSIOF3_TXD_MARK,
1977 };
1978 static const unsigned int msiof3_rxd_pins[] = {
1979 /* MSIOF3_RXD */
1980 RCAR_GP_PIN(0, 5),
1981 };
1982 static const unsigned int msiof3_rxd_mux[] = {
1983 MSIOF3_RXD_MARK,
1984 };
1985
1986 /* - MSIOF4 ----------------------------------------------------------------- */
1987 static const unsigned int msiof4_clk_pins[] = {
1988 /* MSIOF4_SCK */
1989 RCAR_GP_PIN(1, 25),
1990 };
1991 static const unsigned int msiof4_clk_mux[] = {
1992 MSIOF4_SCK_MARK,
1993 };
1994 static const unsigned int msiof4_sync_pins[] = {
1995 /* MSIOF4_SYNC */
1996 RCAR_GP_PIN(1, 28),
1997 };
1998 static const unsigned int msiof4_sync_mux[] = {
1999 MSIOF4_SYNC_MARK,
2000 };
2001 static const unsigned int msiof4_ss1_pins[] = {
2002 /* MSIOF4_SS1 */
2003 RCAR_GP_PIN(1, 23),
2004 };
2005 static const unsigned int msiof4_ss1_mux[] = {
2006 MSIOF4_SS1_MARK,
2007 };
2008 static const unsigned int msiof4_ss2_pins[] = {
2009 /* MSIOF4_SS2 */
2010 RCAR_GP_PIN(1, 24),
2011 };
2012 static const unsigned int msiof4_ss2_mux[] = {
2013 MSIOF4_SS2_MARK,
2014 };
2015 static const unsigned int msiof4_txd_pins[] = {
2016 /* MSIOF4_TXD */
2017 RCAR_GP_PIN(1, 26),
2018 };
2019 static const unsigned int msiof4_txd_mux[] = {
2020 MSIOF4_TXD_MARK,
2021 };
2022 static const unsigned int msiof4_rxd_pins[] = {
2023 /* MSIOF4_RXD */
2024 RCAR_GP_PIN(1, 27),
2025 };
2026 static const unsigned int msiof4_rxd_mux[] = {
2027 MSIOF4_RXD_MARK,
2028 };
2029
2030 /* - MSIOF5 ----------------------------------------------------------------- */
2031 static const unsigned int msiof5_clk_pins[] = {
2032 /* MSIOF5_SCK */
2033 RCAR_GP_PIN(0, 11),
2034 };
2035 static const unsigned int msiof5_clk_mux[] = {
2036 MSIOF5_SCK_MARK,
2037 };
2038 static const unsigned int msiof5_sync_pins[] = {
2039 /* MSIOF5_SYNC */
2040 RCAR_GP_PIN(0, 9),
2041 };
2042 static const unsigned int msiof5_sync_mux[] = {
2043 MSIOF5_SYNC_MARK,
2044 };
2045 static const unsigned int msiof5_ss1_pins[] = {
2046 /* MSIOF5_SS1 */
2047 RCAR_GP_PIN(0, 8),
2048 };
2049 static const unsigned int msiof5_ss1_mux[] = {
2050 MSIOF5_SS1_MARK,
2051 };
2052 static const unsigned int msiof5_ss2_pins[] = {
2053 /* MSIOF5_SS2 */
2054 RCAR_GP_PIN(0, 7),
2055 };
2056 static const unsigned int msiof5_ss2_mux[] = {
2057 MSIOF5_SS2_MARK,
2058 };
2059 static const unsigned int msiof5_txd_pins[] = {
2060 /* MSIOF5_TXD */
2061 RCAR_GP_PIN(0, 10),
2062 };
2063 static const unsigned int msiof5_txd_mux[] = {
2064 MSIOF5_TXD_MARK,
2065 };
2066 static const unsigned int msiof5_rxd_pins[] = {
2067 /* MSIOF5_RXD */
2068 RCAR_GP_PIN(0, 12),
2069 };
2070 static const unsigned int msiof5_rxd_mux[] = {
2071 MSIOF5_RXD_MARK,
2072 };
2073
2074 /* - PCIE ------------------------------------------------------------------- */
2075 static const unsigned int pcie0_clkreq_n_pins[] = {
2076 /* PCIE0_CLKREQ_N */
2077 RCAR_GP_PIN(4, 21),
2078 };
2079
2080 static const unsigned int pcie0_clkreq_n_mux[] = {
2081 PCIE0_CLKREQ_N_MARK,
2082 };
2083
2084 static const unsigned int pcie1_clkreq_n_pins[] = {
2085 /* PCIE1_CLKREQ_N */
2086 RCAR_GP_PIN(4, 22),
2087 };
2088
2089 static const unsigned int pcie1_clkreq_n_mux[] = {
2090 PCIE1_CLKREQ_N_MARK,
2091 };
2092
2093 /* - PWM0 ------------------------------------------------------------------- */
2094 static const unsigned int pwm0_pins[] = {
2095 /* PWM0 */
2096 RCAR_GP_PIN(1, 15),
2097 };
2098 static const unsigned int pwm0_mux[] = {
2099 PWM0_MARK,
2100 };
2101
2102 /* - PWM1_A ------------------------------------------------------------------- */
2103 static const unsigned int pwm1_a_pins[] = {
2104 /* PWM1_A */
2105 RCAR_GP_PIN(3, 13),
2106 };
2107 static const unsigned int pwm1_a_mux[] = {
2108 PWM1_A_MARK,
2109 };
2110
2111 /* - PWM1_B ------------------------------------------------------------------- */
2112 static const unsigned int pwm1_b_pins[] = {
2113 /* PWM1_B */
2114 RCAR_GP_PIN(2, 13),
2115 };
2116 static const unsigned int pwm1_b_mux[] = {
2117 PWM1_B_MARK,
2118 };
2119
2120 /* - PWM2 ------------------------------------------------------------------- */
2121 static const unsigned int pwm2_pins[] = {
2122 /* PWM2 */
2123 RCAR_GP_PIN(2, 14),
2124 };
2125 static const unsigned int pwm2_mux[] = {
2126 PWM2_MARK,
2127 };
2128
2129 /* - PWM3_A ------------------------------------------------------------------- */
2130 static const unsigned int pwm3_a_pins[] = {
2131 /* PWM3_A */
2132 RCAR_GP_PIN(1, 22),
2133 };
2134 static const unsigned int pwm3_a_mux[] = {
2135 PWM3_A_MARK,
2136 };
2137
2138 /* - PWM3_B ------------------------------------------------------------------- */
2139 static const unsigned int pwm3_b_pins[] = {
2140 /* PWM3_B */
2141 RCAR_GP_PIN(2, 15),
2142 };
2143 static const unsigned int pwm3_b_mux[] = {
2144 PWM3_B_MARK,
2145 };
2146
2147 /* - PWM4 ------------------------------------------------------------------- */
2148 static const unsigned int pwm4_pins[] = {
2149 /* PWM4 */
2150 RCAR_GP_PIN(2, 16),
2151 };
2152 static const unsigned int pwm4_mux[] = {
2153 PWM4_MARK,
2154 };
2155
2156 /* - PWM5 ------------------------------------------------------------------- */
2157 static const unsigned int pwm5_pins[] = {
2158 /* PWM5 */
2159 RCAR_GP_PIN(2, 17),
2160 };
2161 static const unsigned int pwm5_mux[] = {
2162 PWM5_MARK,
2163 };
2164
2165 /* - PWM6 ------------------------------------------------------------------- */
2166 static const unsigned int pwm6_pins[] = {
2167 /* PWM6 */
2168 RCAR_GP_PIN(2, 18),
2169 };
2170 static const unsigned int pwm6_mux[] = {
2171 PWM6_MARK,
2172 };
2173
2174 /* - PWM7 ------------------------------------------------------------------- */
2175 static const unsigned int pwm7_pins[] = {
2176 /* PWM7 */
2177 RCAR_GP_PIN(2, 19),
2178 };
2179 static const unsigned int pwm7_mux[] = {
2180 PWM7_MARK,
2181 };
2182
2183 /* - PWM8 ------------------------------------------------------------------- */
2184 static const unsigned int pwm8_pins[] = {
2185 /* PWM8 */
2186 RCAR_GP_PIN(1, 13),
2187 };
2188 static const unsigned int pwm8_mux[] = {
2189 PWM8_MARK,
2190 };
2191
2192 /* - PWM9 ------------------------------------------------------------------- */
2193 static const unsigned int pwm9_pins[] = {
2194 /* PWM9 */
2195 RCAR_GP_PIN(1, 14),
2196 };
2197 static const unsigned int pwm9_mux[] = {
2198 PWM9_MARK,
2199 };
2200
2201 /* - QSPI0 ------------------------------------------------------------------ */
2202 static const unsigned int qspi0_ctrl_pins[] = {
2203 /* SPCLK, SSL */
2204 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 15),
2205 };
2206 static const unsigned int qspi0_ctrl_mux[] = {
2207 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
2208 };
2209 static const unsigned int qspi0_data_pins[] = {
2210 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2211 RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
2212 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
2213 };
2214 static const unsigned int qspi0_data_mux[] = {
2215 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
2216 QSPI0_IO2_MARK, QSPI0_IO3_MARK
2217 };
2218
2219 /* - QSPI1 ------------------------------------------------------------------ */
2220 static const unsigned int qspi1_ctrl_pins[] = {
2221 /* SPCLK, SSL */
2222 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 25),
2223 };
2224 static const unsigned int qspi1_ctrl_mux[] = {
2225 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
2226 };
2227 static const unsigned int qspi1_data_pins[] = {
2228 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2229 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 23),
2230 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 26),
2231 };
2232 static const unsigned int qspi1_data_mux[] = {
2233 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
2234 QSPI1_IO2_MARK, QSPI1_IO3_MARK
2235 };
2236
2237 /* - SCIF0 ------------------------------------------------------------------ */
2238 static const unsigned int scif0_data_pins[] = {
2239 /* RX0, TX0 */
2240 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12),
2241 };
2242 static const unsigned int scif0_data_mux[] = {
2243 RX0_MARK, TX0_MARK,
2244 };
2245 static const unsigned int scif0_clk_pins[] = {
2246 /* SCK0 */
2247 RCAR_GP_PIN(1, 15),
2248 };
2249 static const unsigned int scif0_clk_mux[] = {
2250 SCK0_MARK,
2251 };
2252 static const unsigned int scif0_ctrl_pins[] = {
2253 /* RTS0_N, CTS0_N */
2254 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2255 };
2256 static const unsigned int scif0_ctrl_mux[] = {
2257 RTS0_N_MARK, CTS0_N_MARK,
2258 };
2259
2260 /* - SCIF1 ------------------------------------------------------------------ */
2261 static const unsigned int scif1_data_a_pins[] = {
2262 /* RX1_A, TX1_A */
2263 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2264 };
2265 static const unsigned int scif1_data_a_mux[] = {
2266 RX1_A_MARK, TX1_A_MARK,
2267 };
2268 static const unsigned int scif1_clk_a_pins[] = {
2269 /* SCK1_A */
2270 RCAR_GP_PIN(0, 18),
2271 };
2272 static const unsigned int scif1_clk_a_mux[] = {
2273 SCK1_A_MARK,
2274 };
2275 static const unsigned int scif1_ctrl_a_pins[] = {
2276 /* RTS1_N_A, CTS1_N_A */
2277 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
2278 };
2279 static const unsigned int scif1_ctrl_a_mux[] = {
2280 RTS1_N_A_MARK, CTS1_N_A_MARK,
2281 };
2282
2283 static const unsigned int scif1_data_b_pins[] = {
2284 /* RX1_B, TX1_B */
2285 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
2286 };
2287 static const unsigned int scif1_data_b_mux[] = {
2288 RX1_B_MARK, TX1_B_MARK,
2289 };
2290 static const unsigned int scif1_clk_b_pins[] = {
2291 /* SCK1_B */
2292 RCAR_GP_PIN(1, 10),
2293 };
2294 static const unsigned int scif1_clk_b_mux[] = {
2295 SCK1_B_MARK,
2296 };
2297 static const unsigned int scif1_ctrl_b_pins[] = {
2298 /* RTS1_N_B, CTS1_N_B */
2299 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
2300 };
2301 static const unsigned int scif1_ctrl_b_mux[] = {
2302 RTS1_N_B_MARK, CTS1_N_B_MARK,
2303 };
2304
2305 /* - SCIF3 ------------------------------------------------------------------ */
2306 static const unsigned int scif3_data_a_pins[] = {
2307 /* RX3_A, TX3_A */
2308 RCAR_GP_PIN(1, 27), RCAR_GP_PIN(1, 28),
2309 };
2310 static const unsigned int scif3_data_a_mux[] = {
2311 RX3_A_MARK, TX3_A_MARK,
2312 };
2313 static const unsigned int scif3_clk_a_pins[] = {
2314 /* SCK3_A */
2315 RCAR_GP_PIN(1, 24),
2316 };
2317 static const unsigned int scif3_clk_a_mux[] = {
2318 SCK3_A_MARK,
2319 };
2320 static const unsigned int scif3_ctrl_a_pins[] = {
2321 /* RTS3_N_A, CTS3_N_A */
2322 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2323 };
2324 static const unsigned int scif3_ctrl_a_mux[] = {
2325 RTS3_N_A_MARK, CTS3_N_A_MARK,
2326 };
2327
2328 static const unsigned int scif3_data_b_pins[] = {
2329 /* RX3_B, TX3_B */
2330 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2331 };
2332 static const unsigned int scif3_data_b_mux[] = {
2333 RX3_B_MARK, TX3_B_MARK,
2334 };
2335 static const unsigned int scif3_clk_b_pins[] = {
2336 /* SCK3_B */
2337 RCAR_GP_PIN(1, 4),
2338 };
2339 static const unsigned int scif3_clk_b_mux[] = {
2340 SCK3_B_MARK,
2341 };
2342 static const unsigned int scif3_ctrl_b_pins[] = {
2343 /* RTS3_N_B, CTS3_N_B */
2344 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
2345 };
2346 static const unsigned int scif3_ctrl_b_mux[] = {
2347 RTS3_N_B_MARK, CTS3_N_B_MARK,
2348 };
2349
2350 /* - SCIF4 ------------------------------------------------------------------ */
2351 static const unsigned int scif4_data_pins[] = {
2352 /* RX4, TX4 */
2353 RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 12),
2354 };
2355 static const unsigned int scif4_data_mux[] = {
2356 RX4_MARK, TX4_MARK,
2357 };
2358 static const unsigned int scif4_clk_pins[] = {
2359 /* SCK4 */
2360 RCAR_GP_PIN(8, 8),
2361 };
2362 static const unsigned int scif4_clk_mux[] = {
2363 SCK4_MARK,
2364 };
2365 static const unsigned int scif4_ctrl_pins[] = {
2366 /* RTS4_N, CTS4_N */
2367 RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 9),
2368 };
2369 static const unsigned int scif4_ctrl_mux[] = {
2370 RTS4_N_MARK, CTS4_N_MARK,
2371 };
2372
2373 /* - SCIF Clock ------------------------------------------------------------- */
2374 static const unsigned int scif_clk_pins[] = {
2375 /* SCIF_CLK */
2376 RCAR_GP_PIN(1, 17),
2377 };
2378 static const unsigned int scif_clk_mux[] = {
2379 SCIF_CLK_MARK,
2380 };
2381
2382 static const unsigned int scif_clk2_pins[] = {
2383 /* SCIF_CLK2 */
2384 RCAR_GP_PIN(8, 11),
2385 };
2386 static const unsigned int scif_clk2_mux[] = {
2387 SCIF_CLK2_MARK,
2388 };
2389
2390 /* - SSI ------------------------------------------------- */
2391 static const unsigned int ssi_data_pins[] = {
2392 /* SSI_SD */
2393 RCAR_GP_PIN(1, 20),
2394 };
2395 static const unsigned int ssi_data_mux[] = {
2396 SSI_SD_MARK,
2397 };
2398 static const unsigned int ssi_ctrl_pins[] = {
2399 /* SSI_SCK, SSI_WS */
2400 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
2401 };
2402 static const unsigned int ssi_ctrl_mux[] = {
2403 SSI_SCK_MARK, SSI_WS_MARK,
2404 };
2405
2406 /* - TPU -------------------------------------------------------------------- */
2407 static const unsigned int tpu_to0_a_pins[] = {
2408 /* TPU0TO0_A */
2409 RCAR_GP_PIN(2, 8),
2410 };
2411 static const unsigned int tpu_to0_a_mux[] = {
2412 TPU0TO0_A_MARK,
2413 };
2414 static const unsigned int tpu_to1_a_pins[] = {
2415 /* TPU0TO1_A */
2416 RCAR_GP_PIN(2, 7),
2417 };
2418 static const unsigned int tpu_to1_a_mux[] = {
2419 TPU0TO1_A_MARK,
2420 };
2421 static const unsigned int tpu_to2_a_pins[] = {
2422 /* TPU0TO2_A */
2423 RCAR_GP_PIN(2, 12),
2424 };
2425 static const unsigned int tpu_to2_a_mux[] = {
2426 TPU0TO2_A_MARK,
2427 };
2428 static const unsigned int tpu_to3_a_pins[] = {
2429 /* TPU0TO3_A */
2430 RCAR_GP_PIN(2, 13),
2431 };
2432 static const unsigned int tpu_to3_a_mux[] = {
2433 TPU0TO3_A_MARK,
2434 };
2435
2436 static const unsigned int tpu_to0_b_pins[] = {
2437 /* TPU0TO0_B */
2438 RCAR_GP_PIN(1, 25),
2439 };
2440 static const unsigned int tpu_to0_b_mux[] = {
2441 TPU0TO0_B_MARK,
2442 };
2443 static const unsigned int tpu_to1_b_pins[] = {
2444 /* TPU0TO1_B */
2445 RCAR_GP_PIN(1, 26),
2446 };
2447 static const unsigned int tpu_to1_b_mux[] = {
2448 TPU0TO1_B_MARK,
2449 };
2450 static const unsigned int tpu_to2_b_pins[] = {
2451 /* TPU0TO2_B */
2452 RCAR_GP_PIN(2, 0),
2453 };
2454 static const unsigned int tpu_to2_b_mux[] = {
2455 TPU0TO2_B_MARK,
2456 };
2457 static const unsigned int tpu_to3_b_pins[] = {
2458 /* TPU0TO3_B */
2459 RCAR_GP_PIN(2, 1),
2460 };
2461 static const unsigned int tpu_to3_b_mux[] = {
2462 TPU0TO3_B_MARK,
2463 };
2464
2465 /* - TSN0 ------------------------------------------------ */
2466 static const unsigned int tsn0_link_pins[] = {
2467 /* TSN0_LINK */
2468 RCAR_GP_PIN(4, 4),
2469 };
2470 static const unsigned int tsn0_link_mux[] = {
2471 TSN0_LINK_MARK,
2472 };
2473 static const unsigned int tsn0_phy_int_pins[] = {
2474 /* TSN0_PHY_INT */
2475 RCAR_GP_PIN(4, 3),
2476 };
2477 static const unsigned int tsn0_phy_int_mux[] = {
2478 TSN0_PHY_INT_MARK,
2479 };
2480 static const unsigned int tsn0_mdio_pins[] = {
2481 /* TSN0_MDC, TSN0_MDIO */
2482 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
2483 };
2484 static const unsigned int tsn0_mdio_mux[] = {
2485 TSN0_MDC_MARK, TSN0_MDIO_MARK,
2486 };
2487 static const unsigned int tsn0_rgmii_pins[] = {
2488 /*
2489 * TSN0_TX_CTL, TSN0_TXC, TSN0_TD0, TSN0_TD1, TSN0_TD2, TSN0_TD3,
2490 * TSN0_RX_CTL, TSN0_RXC, TSN0_RD0, TSN0_RD1, TSN0_RD2, TSN0_RD3,
2491 */
2492 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 12),
2493 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14),
2494 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
2495 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 11),
2496 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 13),
2497 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
2498 };
2499 static const unsigned int tsn0_rgmii_mux[] = {
2500 TSN0_TX_CTL_MARK, TSN0_TXC_MARK,
2501 TSN0_TD0_MARK, TSN0_TD1_MARK,
2502 TSN0_TD2_MARK, TSN0_TD3_MARK,
2503 TSN0_RX_CTL_MARK, TSN0_RXC_MARK,
2504 TSN0_RD0_MARK, TSN0_RD1_MARK,
2505 TSN0_RD2_MARK, TSN0_RD3_MARK,
2506 };
2507 static const unsigned int tsn0_txcrefclk_pins[] = {
2508 /* TSN0_TXCREFCLK */
2509 RCAR_GP_PIN(4, 20),
2510 };
2511 static const unsigned int tsn0_txcrefclk_mux[] = {
2512 TSN0_TXCREFCLK_MARK,
2513 };
2514 static const unsigned int tsn0_avtp_pps_pins[] = {
2515 /* TSN0_AVTP_PPS0, TSN0_AVTP_PPS1 */
2516 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 2),
2517 };
2518 static const unsigned int tsn0_avtp_pps_mux[] = {
2519 TSN0_AVTP_PPS0_MARK, TSN0_AVTP_PPS1_MARK,
2520 };
2521 static const unsigned int tsn0_avtp_capture_pins[] = {
2522 /* TSN0_AVTP_CAPTURE */
2523 RCAR_GP_PIN(4, 6),
2524 };
2525 static const unsigned int tsn0_avtp_capture_mux[] = {
2526 TSN0_AVTP_CAPTURE_MARK,
2527 };
2528 static const unsigned int tsn0_avtp_match_pins[] = {
2529 /* TSN0_AVTP_MATCH */
2530 RCAR_GP_PIN(4, 5),
2531 };
2532 static const unsigned int tsn0_avtp_match_mux[] = {
2533 TSN0_AVTP_MATCH_MARK,
2534 };
2535
2536 static const struct sh_pfc_pin_group pinmux_groups[] = {
2537 SH_PFC_PIN_GROUP(audio_clkin),
2538 SH_PFC_PIN_GROUP(audio_clkout),
2539
2540 SH_PFC_PIN_GROUP(avb0_link),
2541 SH_PFC_PIN_GROUP(avb0_magic),
2542 SH_PFC_PIN_GROUP(avb0_phy_int),
2543 SH_PFC_PIN_GROUP(avb0_mdio),
2544 SH_PFC_PIN_GROUP(avb0_rgmii),
2545 SH_PFC_PIN_GROUP(avb0_txcrefclk),
2546 SH_PFC_PIN_GROUP(avb0_avtp_pps),
2547 SH_PFC_PIN_GROUP(avb0_avtp_capture),
2548 SH_PFC_PIN_GROUP(avb0_avtp_match),
2549
2550 SH_PFC_PIN_GROUP(avb1_link),
2551 SH_PFC_PIN_GROUP(avb1_magic),
2552 SH_PFC_PIN_GROUP(avb1_phy_int),
2553 SH_PFC_PIN_GROUP(avb1_mdio),
2554 SH_PFC_PIN_GROUP(avb1_rgmii),
2555 SH_PFC_PIN_GROUP(avb1_txcrefclk),
2556 SH_PFC_PIN_GROUP(avb1_avtp_pps),
2557 SH_PFC_PIN_GROUP(avb1_avtp_capture),
2558 SH_PFC_PIN_GROUP(avb1_avtp_match),
2559
2560 SH_PFC_PIN_GROUP(avb2_link),
2561 SH_PFC_PIN_GROUP(avb2_magic),
2562 SH_PFC_PIN_GROUP(avb2_phy_int),
2563 SH_PFC_PIN_GROUP(avb2_mdio),
2564 SH_PFC_PIN_GROUP(avb2_rgmii),
2565 SH_PFC_PIN_GROUP(avb2_txcrefclk),
2566 SH_PFC_PIN_GROUP(avb2_avtp_pps),
2567 SH_PFC_PIN_GROUP(avb2_avtp_capture),
2568 SH_PFC_PIN_GROUP(avb2_avtp_match),
2569
2570 SH_PFC_PIN_GROUP(canfd0_data),
2571 SH_PFC_PIN_GROUP(canfd1_data),
2572 SH_PFC_PIN_GROUP(canfd2_data),
2573 SH_PFC_PIN_GROUP(canfd3_data),
2574 SH_PFC_PIN_GROUP(canfd4_data),
2575 SH_PFC_PIN_GROUP(canfd5_data_a),
2576 SH_PFC_PIN_GROUP(canfd5_data_b),
2577 SH_PFC_PIN_GROUP(canfd6_data),
2578 SH_PFC_PIN_GROUP(canfd7_data),
2579 SH_PFC_PIN_GROUP(can_clk),
2580
2581 SH_PFC_PIN_GROUP(hscif0_data),
2582 SH_PFC_PIN_GROUP(hscif0_clk),
2583 SH_PFC_PIN_GROUP(hscif0_ctrl),
2584 SH_PFC_PIN_GROUP(hscif1_data_a),
2585 SH_PFC_PIN_GROUP(hscif1_clk_a),
2586 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
2587 SH_PFC_PIN_GROUP(hscif1_data_b),
2588 SH_PFC_PIN_GROUP(hscif1_clk_b),
2589 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
2590 SH_PFC_PIN_GROUP(hscif2_data),
2591 SH_PFC_PIN_GROUP(hscif2_clk),
2592 SH_PFC_PIN_GROUP(hscif2_ctrl),
2593 SH_PFC_PIN_GROUP(hscif3_data_a),
2594 SH_PFC_PIN_GROUP(hscif3_clk_a),
2595 SH_PFC_PIN_GROUP(hscif3_ctrl_a),
2596 SH_PFC_PIN_GROUP(hscif3_data_b),
2597 SH_PFC_PIN_GROUP(hscif3_clk_b),
2598 SH_PFC_PIN_GROUP(hscif3_ctrl_b),
2599
2600 SH_PFC_PIN_GROUP(i2c0),
2601 SH_PFC_PIN_GROUP(i2c1),
2602 SH_PFC_PIN_GROUP(i2c2),
2603 SH_PFC_PIN_GROUP(i2c3),
2604 SH_PFC_PIN_GROUP(i2c4),
2605 SH_PFC_PIN_GROUP(i2c5),
2606
2607 BUS_DATA_PIN_GROUP(mmc_data, 1),
2608 BUS_DATA_PIN_GROUP(mmc_data, 4),
2609 BUS_DATA_PIN_GROUP(mmc_data, 8),
2610 SH_PFC_PIN_GROUP(mmc_ctrl),
2611 SH_PFC_PIN_GROUP(mmc_cd),
2612 SH_PFC_PIN_GROUP(mmc_wp),
2613 SH_PFC_PIN_GROUP(mmc_ds),
2614
2615 SH_PFC_PIN_GROUP(msiof0_clk),
2616 SH_PFC_PIN_GROUP(msiof0_sync),
2617 SH_PFC_PIN_GROUP(msiof0_ss1),
2618 SH_PFC_PIN_GROUP(msiof0_ss2),
2619 SH_PFC_PIN_GROUP(msiof0_txd),
2620 SH_PFC_PIN_GROUP(msiof0_rxd),
2621
2622 SH_PFC_PIN_GROUP(msiof1_clk),
2623 SH_PFC_PIN_GROUP(msiof1_sync),
2624 SH_PFC_PIN_GROUP(msiof1_ss1),
2625 SH_PFC_PIN_GROUP(msiof1_ss2),
2626 SH_PFC_PIN_GROUP(msiof1_txd),
2627 SH_PFC_PIN_GROUP(msiof1_rxd),
2628
2629 SH_PFC_PIN_GROUP(msiof2_clk),
2630 SH_PFC_PIN_GROUP(msiof2_sync),
2631 SH_PFC_PIN_GROUP(msiof2_ss1),
2632 SH_PFC_PIN_GROUP(msiof2_ss2),
2633 SH_PFC_PIN_GROUP(msiof2_txd),
2634 SH_PFC_PIN_GROUP(msiof2_rxd),
2635
2636 SH_PFC_PIN_GROUP(msiof3_clk),
2637 SH_PFC_PIN_GROUP(msiof3_sync),
2638 SH_PFC_PIN_GROUP(msiof3_ss1),
2639 SH_PFC_PIN_GROUP(msiof3_ss2),
2640 SH_PFC_PIN_GROUP(msiof3_txd),
2641 SH_PFC_PIN_GROUP(msiof3_rxd),
2642
2643 SH_PFC_PIN_GROUP(msiof4_clk),
2644 SH_PFC_PIN_GROUP(msiof4_sync),
2645 SH_PFC_PIN_GROUP(msiof4_ss1),
2646 SH_PFC_PIN_GROUP(msiof4_ss2),
2647 SH_PFC_PIN_GROUP(msiof4_txd),
2648 SH_PFC_PIN_GROUP(msiof4_rxd),
2649
2650 SH_PFC_PIN_GROUP(msiof5_clk),
2651 SH_PFC_PIN_GROUP(msiof5_sync),
2652 SH_PFC_PIN_GROUP(msiof5_ss1),
2653 SH_PFC_PIN_GROUP(msiof5_ss2),
2654 SH_PFC_PIN_GROUP(msiof5_txd),
2655 SH_PFC_PIN_GROUP(msiof5_rxd),
2656
2657 SH_PFC_PIN_GROUP(pcie0_clkreq_n),
2658 SH_PFC_PIN_GROUP(pcie1_clkreq_n),
2659
2660 SH_PFC_PIN_GROUP(pwm0),
2661 SH_PFC_PIN_GROUP(pwm1_a),
2662 SH_PFC_PIN_GROUP(pwm1_b),
2663 SH_PFC_PIN_GROUP(pwm2),
2664 SH_PFC_PIN_GROUP(pwm3_a),
2665 SH_PFC_PIN_GROUP(pwm3_b),
2666 SH_PFC_PIN_GROUP(pwm4),
2667 SH_PFC_PIN_GROUP(pwm5),
2668 SH_PFC_PIN_GROUP(pwm6),
2669 SH_PFC_PIN_GROUP(pwm7),
2670 SH_PFC_PIN_GROUP(pwm8),
2671 SH_PFC_PIN_GROUP(pwm9),
2672
2673 SH_PFC_PIN_GROUP(qspi0_ctrl),
2674 BUS_DATA_PIN_GROUP(qspi0_data, 2),
2675 BUS_DATA_PIN_GROUP(qspi0_data, 4),
2676 SH_PFC_PIN_GROUP(qspi1_ctrl),
2677 BUS_DATA_PIN_GROUP(qspi1_data, 2),
2678 BUS_DATA_PIN_GROUP(qspi1_data, 4),
2679
2680 SH_PFC_PIN_GROUP(scif0_data),
2681 SH_PFC_PIN_GROUP(scif0_clk),
2682 SH_PFC_PIN_GROUP(scif0_ctrl),
2683 SH_PFC_PIN_GROUP(scif1_data_a),
2684 SH_PFC_PIN_GROUP(scif1_clk_a),
2685 SH_PFC_PIN_GROUP(scif1_ctrl_a),
2686 SH_PFC_PIN_GROUP(scif1_data_b),
2687 SH_PFC_PIN_GROUP(scif1_clk_b),
2688 SH_PFC_PIN_GROUP(scif1_ctrl_b),
2689 SH_PFC_PIN_GROUP(scif3_data_a),
2690 SH_PFC_PIN_GROUP(scif3_clk_a),
2691 SH_PFC_PIN_GROUP(scif3_ctrl_a),
2692 SH_PFC_PIN_GROUP(scif3_data_b),
2693 SH_PFC_PIN_GROUP(scif3_clk_b),
2694 SH_PFC_PIN_GROUP(scif3_ctrl_b),
2695 SH_PFC_PIN_GROUP(scif4_data),
2696 SH_PFC_PIN_GROUP(scif4_clk),
2697 SH_PFC_PIN_GROUP(scif4_ctrl),
2698 SH_PFC_PIN_GROUP(scif_clk),
2699 SH_PFC_PIN_GROUP(scif_clk2),
2700
2701 SH_PFC_PIN_GROUP(ssi_data),
2702 SH_PFC_PIN_GROUP(ssi_ctrl),
2703
2704 SH_PFC_PIN_GROUP(tpu_to0_a),
2705 SH_PFC_PIN_GROUP(tpu_to0_b),
2706 SH_PFC_PIN_GROUP(tpu_to1_a),
2707 SH_PFC_PIN_GROUP(tpu_to1_b),
2708 SH_PFC_PIN_GROUP(tpu_to2_a),
2709 SH_PFC_PIN_GROUP(tpu_to2_b),
2710 SH_PFC_PIN_GROUP(tpu_to3_a),
2711 SH_PFC_PIN_GROUP(tpu_to3_b),
2712
2713 SH_PFC_PIN_GROUP(tsn0_link),
2714 SH_PFC_PIN_GROUP(tsn0_phy_int),
2715 SH_PFC_PIN_GROUP(tsn0_mdio),
2716 SH_PFC_PIN_GROUP(tsn0_rgmii),
2717 SH_PFC_PIN_GROUP(tsn0_txcrefclk),
2718 SH_PFC_PIN_GROUP(tsn0_avtp_pps),
2719 SH_PFC_PIN_GROUP(tsn0_avtp_capture),
2720 SH_PFC_PIN_GROUP(tsn0_avtp_match),
2721 };
2722
2723 static const char * const audio_clk_groups[] = {
2724 "audio_clkin",
2725 "audio_clkout",
2726 };
2727
2728 static const char * const avb0_groups[] = {
2729 "avb0_link",
2730 "avb0_magic",
2731 "avb0_phy_int",
2732 "avb0_mdio",
2733 "avb0_rgmii",
2734 "avb0_txcrefclk",
2735 "avb0_avtp_pps",
2736 "avb0_avtp_capture",
2737 "avb0_avtp_match",
2738 };
2739
2740 static const char * const avb1_groups[] = {
2741 "avb1_link",
2742 "avb1_magic",
2743 "avb1_phy_int",
2744 "avb1_mdio",
2745 "avb1_rgmii",
2746 "avb1_txcrefclk",
2747 "avb1_avtp_pps",
2748 "avb1_avtp_capture",
2749 "avb1_avtp_match",
2750 };
2751
2752 static const char * const avb2_groups[] = {
2753 "avb2_link",
2754 "avb2_magic",
2755 "avb2_phy_int",
2756 "avb2_mdio",
2757 "avb2_rgmii",
2758 "avb2_txcrefclk",
2759 "avb2_avtp_pps",
2760 "avb2_avtp_capture",
2761 "avb2_avtp_match",
2762 };
2763
2764 static const char * const canfd0_groups[] = {
2765 "canfd0_data",
2766 };
2767
2768 static const char * const canfd1_groups[] = {
2769 "canfd1_data",
2770 };
2771
2772 static const char * const canfd2_groups[] = {
2773 "canfd2_data",
2774 };
2775
2776 static const char * const canfd3_groups[] = {
2777 "canfd3_data",
2778 };
2779
2780 static const char * const canfd4_groups[] = {
2781 "canfd4_data",
2782 };
2783
2784 static const char * const canfd5_groups[] = {
2785 "canfd5_data_a",
2786 "canfd5_data_b",
2787 };
2788
2789 static const char * const canfd6_groups[] = {
2790 "canfd6_data",
2791 };
2792
2793 static const char * const canfd7_groups[] = {
2794 "canfd7_data",
2795 };
2796
2797 static const char * const can_clk_groups[] = {
2798 "can_clk",
2799 };
2800
2801 static const char * const hscif0_groups[] = {
2802 "hscif0_data",
2803 "hscif0_clk",
2804 "hscif0_ctrl",
2805 };
2806
2807 static const char * const hscif1_groups[] = {
2808 "hscif1_data_a",
2809 "hscif1_clk_a",
2810 "hscif1_ctrl_a",
2811 "hscif1_data_b",
2812 "hscif1_clk_b",
2813 "hscif1_ctrl_b",
2814 };
2815
2816 static const char * const hscif2_groups[] = {
2817 "hscif2_data",
2818 "hscif2_clk",
2819 "hscif2_ctrl",
2820 };
2821
2822 static const char * const hscif3_groups[] = {
2823 "hscif3_data_a",
2824 "hscif3_clk_a",
2825 "hscif3_ctrl_a",
2826 "hscif3_data_b",
2827 "hscif3_clk_b",
2828 "hscif3_ctrl_b",
2829 };
2830
2831 static const char * const i2c0_groups[] = {
2832 "i2c0",
2833 };
2834
2835 static const char * const i2c1_groups[] = {
2836 "i2c1",
2837 };
2838
2839 static const char * const i2c2_groups[] = {
2840 "i2c2",
2841 };
2842
2843 static const char * const i2c3_groups[] = {
2844 "i2c3",
2845 };
2846
2847 static const char * const i2c4_groups[] = {
2848 "i2c4",
2849 };
2850
2851 static const char * const i2c5_groups[] = {
2852 "i2c5",
2853 };
2854
2855 static const char * const mmc_groups[] = {
2856 "mmc_data1",
2857 "mmc_data4",
2858 "mmc_data8",
2859 "mmc_ctrl",
2860 "mmc_cd",
2861 "mmc_wp",
2862 "mmc_ds",
2863 };
2864
2865 static const char * const msiof0_groups[] = {
2866 "msiof0_clk",
2867 "msiof0_sync",
2868 "msiof0_ss1",
2869 "msiof0_ss2",
2870 "msiof0_txd",
2871 "msiof0_rxd",
2872 };
2873
2874 static const char * const msiof1_groups[] = {
2875 "msiof1_clk",
2876 "msiof1_sync",
2877 "msiof1_ss1",
2878 "msiof1_ss2",
2879 "msiof1_txd",
2880 "msiof1_rxd",
2881 };
2882
2883 static const char * const msiof2_groups[] = {
2884 "msiof2_clk",
2885 "msiof2_sync",
2886 "msiof2_ss1",
2887 "msiof2_ss2",
2888 "msiof2_txd",
2889 "msiof2_rxd",
2890 };
2891
2892 static const char * const msiof3_groups[] = {
2893 "msiof3_clk",
2894 "msiof3_sync",
2895 "msiof3_ss1",
2896 "msiof3_ss2",
2897 "msiof3_txd",
2898 "msiof3_rxd",
2899 };
2900
2901 static const char * const msiof4_groups[] = {
2902 "msiof4_clk",
2903 "msiof4_sync",
2904 "msiof4_ss1",
2905 "msiof4_ss2",
2906 "msiof4_txd",
2907 "msiof4_rxd",
2908 };
2909
2910 static const char * const msiof5_groups[] = {
2911 "msiof5_clk",
2912 "msiof5_sync",
2913 "msiof5_ss1",
2914 "msiof5_ss2",
2915 "msiof5_txd",
2916 "msiof5_rxd",
2917 };
2918
2919 static const char * const pcie_groups[] = {
2920 "pcie0_clkreq_n",
2921 "pcie1_clkreq_n",
2922 };
2923
2924 static const char * const pwm0_groups[] = {
2925 "pwm0",
2926 };
2927
2928 static const char * const pwm1_groups[] = {
2929 "pwm1_a",
2930 "pwm1_b",
2931 };
2932
2933 static const char * const pwm2_groups[] = {
2934 "pwm2",
2935 };
2936
2937 static const char * const pwm3_groups[] = {
2938 "pwm3_a",
2939 "pwm3_b",
2940 };
2941
2942 static const char * const pwm4_groups[] = {
2943 "pwm4",
2944 };
2945
2946 static const char * const pwm5_groups[] = {
2947 "pwm5",
2948 };
2949
2950 static const char * const pwm6_groups[] = {
2951 "pwm6",
2952 };
2953
2954 static const char * const pwm7_groups[] = {
2955 "pwm7",
2956 };
2957
2958 static const char * const pwm8_groups[] = {
2959 "pwm8",
2960 };
2961
2962 static const char * const pwm9_groups[] = {
2963 "pwm9",
2964 };
2965
2966 static const char * const qspi0_groups[] = {
2967 "qspi0_ctrl",
2968 "qspi0_data2",
2969 "qspi0_data4",
2970 };
2971
2972 static const char * const qspi1_groups[] = {
2973 "qspi1_ctrl",
2974 "qspi1_data2",
2975 "qspi1_data4",
2976 };
2977
2978 static const char * const scif0_groups[] = {
2979 "scif0_data",
2980 "scif0_clk",
2981 "scif0_ctrl",
2982 };
2983
2984 static const char * const scif1_groups[] = {
2985 "scif1_data_a",
2986 "scif1_clk_a",
2987 "scif1_ctrl_a",
2988 "scif1_data_b",
2989 "scif1_clk_b",
2990 "scif1_ctrl_b",
2991 };
2992
2993 static const char * const scif3_groups[] = {
2994 "scif3_data_a",
2995 "scif3_clk_a",
2996 "scif3_ctrl_a",
2997 "scif3_data_b",
2998 "scif3_clk_b",
2999 "scif3_ctrl_b",
3000 };
3001
3002 static const char * const scif4_groups[] = {
3003 "scif4_data",
3004 "scif4_clk",
3005 "scif4_ctrl",
3006 };
3007
3008 static const char * const scif_clk_groups[] = {
3009 "scif_clk",
3010 };
3011
3012 static const char * const scif_clk2_groups[] = {
3013 "scif_clk2",
3014 };
3015
3016 static const char * const ssi_groups[] = {
3017 "ssi_data",
3018 "ssi_ctrl",
3019 };
3020
3021 static const char * const tpu_groups[] = {
3022 "tpu_to0_a",
3023 "tpu_to0_b",
3024 "tpu_to1_a",
3025 "tpu_to1_b",
3026 "tpu_to2_a",
3027 "tpu_to2_b",
3028 "tpu_to3_a",
3029 "tpu_to3_b",
3030 };
3031
3032 static const char * const tsn0_groups[] = {
3033 "tsn0_link",
3034 "tsn0_phy_int",
3035 "tsn0_mdio",
3036 "tsn0_rgmii",
3037 "tsn0_txcrefclk",
3038 "tsn0_avtp_pps",
3039 "tsn0_avtp_capture",
3040 "tsn0_avtp_match",
3041 };
3042
3043 static const struct sh_pfc_function pinmux_functions[] = {
3044 SH_PFC_FUNCTION(audio_clk),
3045
3046 SH_PFC_FUNCTION(avb0),
3047 SH_PFC_FUNCTION(avb1),
3048 SH_PFC_FUNCTION(avb2),
3049
3050 SH_PFC_FUNCTION(canfd0),
3051 SH_PFC_FUNCTION(canfd1),
3052 SH_PFC_FUNCTION(canfd2),
3053 SH_PFC_FUNCTION(canfd3),
3054 SH_PFC_FUNCTION(canfd4),
3055 SH_PFC_FUNCTION(canfd5),
3056 SH_PFC_FUNCTION(canfd6),
3057 SH_PFC_FUNCTION(canfd7),
3058 SH_PFC_FUNCTION(can_clk),
3059
3060 SH_PFC_FUNCTION(hscif0),
3061 SH_PFC_FUNCTION(hscif1),
3062 SH_PFC_FUNCTION(hscif2),
3063 SH_PFC_FUNCTION(hscif3),
3064
3065 SH_PFC_FUNCTION(i2c0),
3066 SH_PFC_FUNCTION(i2c1),
3067 SH_PFC_FUNCTION(i2c2),
3068 SH_PFC_FUNCTION(i2c3),
3069 SH_PFC_FUNCTION(i2c4),
3070 SH_PFC_FUNCTION(i2c5),
3071
3072 SH_PFC_FUNCTION(mmc),
3073
3074 SH_PFC_FUNCTION(msiof0),
3075 SH_PFC_FUNCTION(msiof1),
3076 SH_PFC_FUNCTION(msiof2),
3077 SH_PFC_FUNCTION(msiof3),
3078 SH_PFC_FUNCTION(msiof4),
3079 SH_PFC_FUNCTION(msiof5),
3080
3081 SH_PFC_FUNCTION(pcie),
3082
3083 SH_PFC_FUNCTION(pwm0),
3084 SH_PFC_FUNCTION(pwm1),
3085 SH_PFC_FUNCTION(pwm2),
3086 SH_PFC_FUNCTION(pwm3),
3087 SH_PFC_FUNCTION(pwm4),
3088 SH_PFC_FUNCTION(pwm5),
3089 SH_PFC_FUNCTION(pwm6),
3090 SH_PFC_FUNCTION(pwm7),
3091 SH_PFC_FUNCTION(pwm8),
3092 SH_PFC_FUNCTION(pwm9),
3093
3094 SH_PFC_FUNCTION(qspi0),
3095 SH_PFC_FUNCTION(qspi1),
3096
3097 SH_PFC_FUNCTION(scif0),
3098 SH_PFC_FUNCTION(scif1),
3099 SH_PFC_FUNCTION(scif3),
3100 SH_PFC_FUNCTION(scif4),
3101 SH_PFC_FUNCTION(scif_clk),
3102 SH_PFC_FUNCTION(scif_clk2),
3103
3104 SH_PFC_FUNCTION(ssi),
3105
3106 SH_PFC_FUNCTION(tpu),
3107
3108 SH_PFC_FUNCTION(tsn0),
3109 };
3110
3111 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3112 #define F_(x, y) FN_##y
3113 #define FM(x) FN_##x
3114 { PINMUX_CFG_REG_VAR("GPSR0", 0xE6050040, 32,
3115 GROUP(-13, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3116 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3117 GROUP(
3118 /* GP0_31_19 RESERVED */
3119 GP_0_18_FN, GPSR0_18,
3120 GP_0_17_FN, GPSR0_17,
3121 GP_0_16_FN, GPSR0_16,
3122 GP_0_15_FN, GPSR0_15,
3123 GP_0_14_FN, GPSR0_14,
3124 GP_0_13_FN, GPSR0_13,
3125 GP_0_12_FN, GPSR0_12,
3126 GP_0_11_FN, GPSR0_11,
3127 GP_0_10_FN, GPSR0_10,
3128 GP_0_9_FN, GPSR0_9,
3129 GP_0_8_FN, GPSR0_8,
3130 GP_0_7_FN, GPSR0_7,
3131 GP_0_6_FN, GPSR0_6,
3132 GP_0_5_FN, GPSR0_5,
3133 GP_0_4_FN, GPSR0_4,
3134 GP_0_3_FN, GPSR0_3,
3135 GP_0_2_FN, GPSR0_2,
3136 GP_0_1_FN, GPSR0_1,
3137 GP_0_0_FN, GPSR0_0, ))
3138 },
3139 { PINMUX_CFG_REG("GPSR1", 0xE6050840, 32, 1, GROUP(
3140 0, 0,
3141 0, 0,
3142 0, 0,
3143 GP_1_28_FN, GPSR1_28,
3144 GP_1_27_FN, GPSR1_27,
3145 GP_1_26_FN, GPSR1_26,
3146 GP_1_25_FN, GPSR1_25,
3147 GP_1_24_FN, GPSR1_24,
3148 GP_1_23_FN, GPSR1_23,
3149 GP_1_22_FN, GPSR1_22,
3150 GP_1_21_FN, GPSR1_21,
3151 GP_1_20_FN, GPSR1_20,
3152 GP_1_19_FN, GPSR1_19,
3153 GP_1_18_FN, GPSR1_18,
3154 GP_1_17_FN, GPSR1_17,
3155 GP_1_16_FN, GPSR1_16,
3156 GP_1_15_FN, GPSR1_15,
3157 GP_1_14_FN, GPSR1_14,
3158 GP_1_13_FN, GPSR1_13,
3159 GP_1_12_FN, GPSR1_12,
3160 GP_1_11_FN, GPSR1_11,
3161 GP_1_10_FN, GPSR1_10,
3162 GP_1_9_FN, GPSR1_9,
3163 GP_1_8_FN, GPSR1_8,
3164 GP_1_7_FN, GPSR1_7,
3165 GP_1_6_FN, GPSR1_6,
3166 GP_1_5_FN, GPSR1_5,
3167 GP_1_4_FN, GPSR1_4,
3168 GP_1_3_FN, GPSR1_3,
3169 GP_1_2_FN, GPSR1_2,
3170 GP_1_1_FN, GPSR1_1,
3171 GP_1_0_FN, GPSR1_0, ))
3172 },
3173 { PINMUX_CFG_REG_VAR("GPSR2", 0xE6058040, 32,
3174 GROUP(-12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3175 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3176 GROUP(
3177 /* GP2_31_20 RESERVED */
3178 GP_2_19_FN, GPSR2_19,
3179 GP_2_18_FN, GPSR2_18,
3180 GP_2_17_FN, GPSR2_17,
3181 GP_2_16_FN, GPSR2_16,
3182 GP_2_15_FN, GPSR2_15,
3183 GP_2_14_FN, GPSR2_14,
3184 GP_2_13_FN, GPSR2_13,
3185 GP_2_12_FN, GPSR2_12,
3186 GP_2_11_FN, GPSR2_11,
3187 GP_2_10_FN, GPSR2_10,
3188 GP_2_9_FN, GPSR2_9,
3189 GP_2_8_FN, GPSR2_8,
3190 GP_2_7_FN, GPSR2_7,
3191 GP_2_6_FN, GPSR2_6,
3192 GP_2_5_FN, GPSR2_5,
3193 GP_2_4_FN, GPSR2_4,
3194 GP_2_3_FN, GPSR2_3,
3195 GP_2_2_FN, GPSR2_2,
3196 GP_2_1_FN, GPSR2_1,
3197 GP_2_0_FN, GPSR2_0, ))
3198 },
3199 { PINMUX_CFG_REG("GPSR3", 0xE6058840, 32, 1, GROUP(
3200 0, 0,
3201 0, 0,
3202 GP_3_29_FN, GPSR3_29,
3203 GP_3_28_FN, GPSR3_28,
3204 GP_3_27_FN, GPSR3_27,
3205 GP_3_26_FN, GPSR3_26,
3206 GP_3_25_FN, GPSR3_25,
3207 GP_3_24_FN, GPSR3_24,
3208 GP_3_23_FN, GPSR3_23,
3209 GP_3_22_FN, GPSR3_22,
3210 GP_3_21_FN, GPSR3_21,
3211 GP_3_20_FN, GPSR3_20,
3212 GP_3_19_FN, GPSR3_19,
3213 GP_3_18_FN, GPSR3_18,
3214 GP_3_17_FN, GPSR3_17,
3215 GP_3_16_FN, GPSR3_16,
3216 GP_3_15_FN, GPSR3_15,
3217 GP_3_14_FN, GPSR3_14,
3218 GP_3_13_FN, GPSR3_13,
3219 GP_3_12_FN, GPSR3_12,
3220 GP_3_11_FN, GPSR3_11,
3221 GP_3_10_FN, GPSR3_10,
3222 GP_3_9_FN, GPSR3_9,
3223 GP_3_8_FN, GPSR3_8,
3224 GP_3_7_FN, GPSR3_7,
3225 GP_3_6_FN, GPSR3_6,
3226 GP_3_5_FN, GPSR3_5,
3227 GP_3_4_FN, GPSR3_4,
3228 GP_3_3_FN, GPSR3_3,
3229 GP_3_2_FN, GPSR3_2,
3230 GP_3_1_FN, GPSR3_1,
3231 GP_3_0_FN, GPSR3_0, ))
3232 },
3233 { PINMUX_CFG_REG("GPSR4", 0xE6060040, 32, 1, GROUP(
3234 0, 0,
3235 0, 0,
3236 0, 0,
3237 0, 0,
3238 0, 0,
3239 0, 0,
3240 0, 0,
3241 GP_4_24_FN, GPSR4_24,
3242 GP_4_23_FN, GPSR4_23,
3243 GP_4_22_FN, GPSR4_22,
3244 GP_4_21_FN, GPSR4_21,
3245 GP_4_20_FN, GPSR4_20,
3246 GP_4_19_FN, GPSR4_19,
3247 GP_4_18_FN, GPSR4_18,
3248 GP_4_17_FN, GPSR4_17,
3249 GP_4_16_FN, GPSR4_16,
3250 GP_4_15_FN, GPSR4_15,
3251 GP_4_14_FN, GPSR4_14,
3252 GP_4_13_FN, GPSR4_13,
3253 GP_4_12_FN, GPSR4_12,
3254 GP_4_11_FN, GPSR4_11,
3255 GP_4_10_FN, GPSR4_10,
3256 GP_4_9_FN, GPSR4_9,
3257 GP_4_8_FN, GPSR4_8,
3258 GP_4_7_FN, GPSR4_7,
3259 GP_4_6_FN, GPSR4_6,
3260 GP_4_5_FN, GPSR4_5,
3261 GP_4_4_FN, GPSR4_4,
3262 GP_4_3_FN, GPSR4_3,
3263 GP_4_2_FN, GPSR4_2,
3264 GP_4_1_FN, GPSR4_1,
3265 GP_4_0_FN, GPSR4_0, ))
3266 },
3267 { PINMUX_CFG_REG_VAR("GPSR5", 0xE6060840, 32,
3268 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3269 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3270 GROUP(
3271 /* GP5_31_21 RESERVED */
3272 GP_5_20_FN, GPSR5_20,
3273 GP_5_19_FN, GPSR5_19,
3274 GP_5_18_FN, GPSR5_18,
3275 GP_5_17_FN, GPSR5_17,
3276 GP_5_16_FN, GPSR5_16,
3277 GP_5_15_FN, GPSR5_15,
3278 GP_5_14_FN, GPSR5_14,
3279 GP_5_13_FN, GPSR5_13,
3280 GP_5_12_FN, GPSR5_12,
3281 GP_5_11_FN, GPSR5_11,
3282 GP_5_10_FN, GPSR5_10,
3283 GP_5_9_FN, GPSR5_9,
3284 GP_5_8_FN, GPSR5_8,
3285 GP_5_7_FN, GPSR5_7,
3286 GP_5_6_FN, GPSR5_6,
3287 GP_5_5_FN, GPSR5_5,
3288 GP_5_4_FN, GPSR5_4,
3289 GP_5_3_FN, GPSR5_3,
3290 GP_5_2_FN, GPSR5_2,
3291 GP_5_1_FN, GPSR5_1,
3292 GP_5_0_FN, GPSR5_0, ))
3293 },
3294 { PINMUX_CFG_REG_VAR("GPSR6", 0xE6061040, 32,
3295 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3296 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3297 GROUP(
3298 /* GP6_31_21 RESERVED */
3299 GP_6_20_FN, GPSR6_20,
3300 GP_6_19_FN, GPSR6_19,
3301 GP_6_18_FN, GPSR6_18,
3302 GP_6_17_FN, GPSR6_17,
3303 GP_6_16_FN, GPSR6_16,
3304 GP_6_15_FN, GPSR6_15,
3305 GP_6_14_FN, GPSR6_14,
3306 GP_6_13_FN, GPSR6_13,
3307 GP_6_12_FN, GPSR6_12,
3308 GP_6_11_FN, GPSR6_11,
3309 GP_6_10_FN, GPSR6_10,
3310 GP_6_9_FN, GPSR6_9,
3311 GP_6_8_FN, GPSR6_8,
3312 GP_6_7_FN, GPSR6_7,
3313 GP_6_6_FN, GPSR6_6,
3314 GP_6_5_FN, GPSR6_5,
3315 GP_6_4_FN, GPSR6_4,
3316 GP_6_3_FN, GPSR6_3,
3317 GP_6_2_FN, GPSR6_2,
3318 GP_6_1_FN, GPSR6_1,
3319 GP_6_0_FN, GPSR6_0, ))
3320 },
3321 { PINMUX_CFG_REG_VAR("GPSR7", 0xE6061840, 32,
3322 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3323 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3324 GROUP(
3325 /* GP7_31_21 RESERVED */
3326 GP_7_20_FN, GPSR7_20,
3327 GP_7_19_FN, GPSR7_19,
3328 GP_7_18_FN, GPSR7_18,
3329 GP_7_17_FN, GPSR7_17,
3330 GP_7_16_FN, GPSR7_16,
3331 GP_7_15_FN, GPSR7_15,
3332 GP_7_14_FN, GPSR7_14,
3333 GP_7_13_FN, GPSR7_13,
3334 GP_7_12_FN, GPSR7_12,
3335 GP_7_11_FN, GPSR7_11,
3336 GP_7_10_FN, GPSR7_10,
3337 GP_7_9_FN, GPSR7_9,
3338 GP_7_8_FN, GPSR7_8,
3339 GP_7_7_FN, GPSR7_7,
3340 GP_7_6_FN, GPSR7_6,
3341 GP_7_5_FN, GPSR7_5,
3342 GP_7_4_FN, GPSR7_4,
3343 GP_7_3_FN, GPSR7_3,
3344 GP_7_2_FN, GPSR7_2,
3345 GP_7_1_FN, GPSR7_1,
3346 GP_7_0_FN, GPSR7_0, ))
3347 },
3348 { PINMUX_CFG_REG_VAR("GPSR8", 0xE6068040, 32,
3349 GROUP(-18, 1, 1, 1, 1,
3350 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3351 GROUP(
3352 /* GP8_31_14 RESERVED */
3353 GP_8_13_FN, GPSR8_13,
3354 GP_8_12_FN, GPSR8_12,
3355 GP_8_11_FN, GPSR8_11,
3356 GP_8_10_FN, GPSR8_10,
3357 GP_8_9_FN, GPSR8_9,
3358 GP_8_8_FN, GPSR8_8,
3359 GP_8_7_FN, GPSR8_7,
3360 GP_8_6_FN, GPSR8_6,
3361 GP_8_5_FN, GPSR8_5,
3362 GP_8_4_FN, GPSR8_4,
3363 GP_8_3_FN, GPSR8_3,
3364 GP_8_2_FN, GPSR8_2,
3365 GP_8_1_FN, GPSR8_1,
3366 GP_8_0_FN, GPSR8_0, ))
3367 },
3368 #undef F_
3369 #undef FM
3370
3371 #define F_(x, y) x,
3372 #define FM(x) FN_##x,
3373 { PINMUX_CFG_REG("IP0SR0", 0xE6050060, 32, 4, GROUP(
3374 IP0SR0_31_28
3375 IP0SR0_27_24
3376 IP0SR0_23_20
3377 IP0SR0_19_16
3378 IP0SR0_15_12
3379 IP0SR0_11_8
3380 IP0SR0_7_4
3381 IP0SR0_3_0))
3382 },
3383 { PINMUX_CFG_REG("IP1SR0", 0xE6050064, 32, 4, GROUP(
3384 IP1SR0_31_28
3385 IP1SR0_27_24
3386 IP1SR0_23_20
3387 IP1SR0_19_16
3388 IP1SR0_15_12
3389 IP1SR0_11_8
3390 IP1SR0_7_4
3391 IP1SR0_3_0))
3392 },
3393 { PINMUX_CFG_REG_VAR("IP2SR0", 0xE6050068, 32,
3394 GROUP(-20, 4, 4, 4),
3395 GROUP(
3396 /* IP2SR0_31_12 RESERVED */
3397 IP2SR0_11_8
3398 IP2SR0_7_4
3399 IP2SR0_3_0))
3400 },
3401 { PINMUX_CFG_REG("IP0SR1", 0xE6050860, 32, 4, GROUP(
3402 IP0SR1_31_28
3403 IP0SR1_27_24
3404 IP0SR1_23_20
3405 IP0SR1_19_16
3406 IP0SR1_15_12
3407 IP0SR1_11_8
3408 IP0SR1_7_4
3409 IP0SR1_3_0))
3410 },
3411 { PINMUX_CFG_REG("IP1SR1", 0xE6050864, 32, 4, GROUP(
3412 IP1SR1_31_28
3413 IP1SR1_27_24
3414 IP1SR1_23_20
3415 IP1SR1_19_16
3416 IP1SR1_15_12
3417 IP1SR1_11_8
3418 IP1SR1_7_4
3419 IP1SR1_3_0))
3420 },
3421 { PINMUX_CFG_REG("IP2SR1", 0xE6050868, 32, 4, GROUP(
3422 IP2SR1_31_28
3423 IP2SR1_27_24
3424 IP2SR1_23_20
3425 IP2SR1_19_16
3426 IP2SR1_15_12
3427 IP2SR1_11_8
3428 IP2SR1_7_4
3429 IP2SR1_3_0))
3430 },
3431 { PINMUX_CFG_REG_VAR("IP3SR1", 0xE605086C, 32,
3432 GROUP(-12, 4, 4, 4, 4, 4),
3433 GROUP(
3434 /* IP3SR1_31_20 RESERVED */
3435 IP3SR1_19_16
3436 IP3SR1_15_12
3437 IP3SR1_11_8
3438 IP3SR1_7_4
3439 IP3SR1_3_0))
3440 },
3441 { PINMUX_CFG_REG("IP0SR2", 0xE6058060, 32, 4, GROUP(
3442 IP0SR2_31_28
3443 IP0SR2_27_24
3444 IP0SR2_23_20
3445 IP0SR2_19_16
3446 IP0SR2_15_12
3447 IP0SR2_11_8
3448 IP0SR2_7_4
3449 IP0SR2_3_0))
3450 },
3451 { PINMUX_CFG_REG("IP1SR2", 0xE6058064, 32, 4, GROUP(
3452 IP1SR2_31_28
3453 IP1SR2_27_24
3454 IP1SR2_23_20
3455 IP1SR2_19_16
3456 IP1SR2_15_12
3457 IP1SR2_11_8
3458 IP1SR2_7_4
3459 IP1SR2_3_0))
3460 },
3461 { PINMUX_CFG_REG_VAR("IP2SR2", 0xE6058068, 32,
3462 GROUP(-16, 4, 4, 4, 4),
3463 GROUP(
3464 /* IP2SR2_31_16 RESERVED */
3465 IP2SR2_15_12
3466 IP2SR2_11_8
3467 IP2SR2_7_4
3468 IP2SR2_3_0))
3469 },
3470 { PINMUX_CFG_REG("IP0SR3", 0xE6058860, 32, 4, GROUP(
3471 IP0SR3_31_28
3472 IP0SR3_27_24
3473 IP0SR3_23_20
3474 IP0SR3_19_16
3475 IP0SR3_15_12
3476 IP0SR3_11_8
3477 IP0SR3_7_4
3478 IP0SR3_3_0))
3479 },
3480 { PINMUX_CFG_REG("IP1SR3", 0xE6058864, 32, 4, GROUP(
3481 IP1SR3_31_28
3482 IP1SR3_27_24
3483 IP1SR3_23_20
3484 IP1SR3_19_16
3485 IP1SR3_15_12
3486 IP1SR3_11_8
3487 IP1SR3_7_4
3488 IP1SR3_3_0))
3489 },
3490 { PINMUX_CFG_REG("IP2SR3", 0xE6058868, 32, 4, GROUP(
3491 IP2SR3_31_28
3492 IP2SR3_27_24
3493 IP2SR3_23_20
3494 IP2SR3_19_16
3495 IP2SR3_15_12
3496 IP2SR3_11_8
3497 IP2SR3_7_4
3498 IP2SR3_3_0))
3499 },
3500 { PINMUX_CFG_REG_VAR("IP3SR3", 0xE605886C, 32,
3501 GROUP(-8, 4, 4, 4, 4, 4, 4),
3502 GROUP(
3503 /* IP3SR3_31_24 RESERVED */
3504 IP3SR3_23_20
3505 IP3SR3_19_16
3506 IP3SR3_15_12
3507 IP3SR3_11_8
3508 IP3SR3_7_4
3509 IP3SR3_3_0))
3510 },
3511 { PINMUX_CFG_REG_VAR("IP0SR4", 0xE6060060, 32,
3512 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3513 GROUP(
3514 IP0SR4_31_28
3515 IP0SR4_27_24
3516 IP0SR4_23_20
3517 IP0SR4_19_16
3518 IP0SR4_15_12
3519 IP0SR4_11_8
3520 IP0SR4_7_4
3521 IP0SR4_3_0))
3522 },
3523 { PINMUX_CFG_REG_VAR("IP1SR4", 0xE6060064, 32,
3524 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3525 GROUP(
3526 IP1SR4_31_28
3527 IP1SR4_27_24
3528 IP1SR4_23_20
3529 IP1SR4_19_16
3530 IP1SR4_15_12
3531 IP1SR4_11_8
3532 IP1SR4_7_4
3533 IP1SR4_3_0))
3534 },
3535 { PINMUX_CFG_REG_VAR("IP2SR4", 0xE6060068, 32,
3536 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3537 GROUP(
3538 IP2SR4_31_28
3539 IP2SR4_27_24
3540 IP2SR4_23_20
3541 IP2SR4_19_16
3542 IP2SR4_15_12
3543 IP2SR4_11_8
3544 IP2SR4_7_4
3545 IP2SR4_3_0))
3546 },
3547 { PINMUX_CFG_REG_VAR("IP3SR4", 0xE606006C, 32,
3548 GROUP(-28, 4),
3549 GROUP(
3550 /* IP3SR4_31_4 RESERVED */
3551 IP3SR4_3_0))
3552 },
3553 { PINMUX_CFG_REG_VAR("IP0SR5", 0xE6060860, 32,
3554 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3555 GROUP(
3556 IP0SR5_31_28
3557 IP0SR5_27_24
3558 IP0SR5_23_20
3559 IP0SR5_19_16
3560 IP0SR5_15_12
3561 IP0SR5_11_8
3562 IP0SR5_7_4
3563 IP0SR5_3_0))
3564 },
3565 { PINMUX_CFG_REG_VAR("IP1SR5", 0xE6060864, 32,
3566 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3567 GROUP(
3568 IP1SR5_31_28
3569 IP1SR5_27_24
3570 IP1SR5_23_20
3571 IP1SR5_19_16
3572 IP1SR5_15_12
3573 IP1SR5_11_8
3574 IP1SR5_7_4
3575 IP1SR5_3_0))
3576 },
3577 { PINMUX_CFG_REG_VAR("IP2SR5", 0xE6060868, 32,
3578 GROUP(-12, 4, 4, 4, 4, 4),
3579 GROUP(
3580 /* IP2SR5_31_20 RESERVED */
3581 IP2SR5_19_16
3582 IP2SR5_15_12
3583 IP2SR5_11_8
3584 IP2SR5_7_4
3585 IP2SR5_3_0))
3586 },
3587 { PINMUX_CFG_REG("IP0SR6", 0xE6061060, 32, 4, GROUP(
3588 IP0SR6_31_28
3589 IP0SR6_27_24
3590 IP0SR6_23_20
3591 IP0SR6_19_16
3592 IP0SR6_15_12
3593 IP0SR6_11_8
3594 IP0SR6_7_4
3595 IP0SR6_3_0))
3596 },
3597 { PINMUX_CFG_REG("IP1SR6", 0xE6061064, 32, 4, GROUP(
3598 IP1SR6_31_28
3599 IP1SR6_27_24
3600 IP1SR6_23_20
3601 IP1SR6_19_16
3602 IP1SR6_15_12
3603 IP1SR6_11_8
3604 IP1SR6_7_4
3605 IP1SR6_3_0))
3606 },
3607 { PINMUX_CFG_REG_VAR("IP2SR6", 0xE6061068, 32,
3608 GROUP(-12, 4, 4, 4, 4, 4),
3609 GROUP(
3610 /* IP2SR6_31_20 RESERVED */
3611 IP2SR6_19_16
3612 IP2SR6_15_12
3613 IP2SR6_11_8
3614 IP2SR6_7_4
3615 IP2SR6_3_0))
3616 },
3617 { PINMUX_CFG_REG("IP0SR7", 0xE6061860, 32, 4, GROUP(
3618 IP0SR7_31_28
3619 IP0SR7_27_24
3620 IP0SR7_23_20
3621 IP0SR7_19_16
3622 IP0SR7_15_12
3623 IP0SR7_11_8
3624 IP0SR7_7_4
3625 IP0SR7_3_0))
3626 },
3627 { PINMUX_CFG_REG("IP1SR7", 0xE6061864, 32, 4, GROUP(
3628 IP1SR7_31_28
3629 IP1SR7_27_24
3630 IP1SR7_23_20
3631 IP1SR7_19_16
3632 IP1SR7_15_12
3633 IP1SR7_11_8
3634 IP1SR7_7_4
3635 IP1SR7_3_0))
3636 },
3637 { PINMUX_CFG_REG_VAR("IP2SR7", 0xE6061868, 32,
3638 GROUP(-12, 4, 4, 4, 4, 4),
3639 GROUP(
3640 /* IP2SR7_31_20 RESERVED */
3641 IP2SR7_19_16
3642 IP2SR7_15_12
3643 IP2SR7_11_8
3644 IP2SR7_7_4
3645 IP2SR7_3_0))
3646 },
3647 { PINMUX_CFG_REG("IP0SR8", 0xE6068060, 32, 4, GROUP(
3648 IP0SR8_31_28
3649 IP0SR8_27_24
3650 IP0SR8_23_20
3651 IP0SR8_19_16
3652 IP0SR8_15_12
3653 IP0SR8_11_8
3654 IP0SR8_7_4
3655 IP0SR8_3_0))
3656 },
3657 { PINMUX_CFG_REG_VAR("IP1SR8", 0xE6068064, 32,
3658 GROUP(-8, 4, 4, 4, 4, 4, 4),
3659 GROUP(
3660 /* IP1SR8_31_24 RESERVED */
3661 IP1SR8_23_20
3662 IP1SR8_19_16
3663 IP1SR8_15_12
3664 IP1SR8_11_8
3665 IP1SR8_7_4
3666 IP1SR8_3_0))
3667 },
3668 #undef F_
3669 #undef FM
3670
3671 #define F_(x, y) x,
3672 #define FM(x) FN_##x,
3673 { PINMUX_CFG_REG_VAR("MOD_SEL8", 0xE6068100, 32,
3674 GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3675 GROUP(
3676 /* RESERVED 31-12 */
3677 MOD_SEL8_11
3678 MOD_SEL8_10
3679 MOD_SEL8_9
3680 MOD_SEL8_8
3681 MOD_SEL8_7
3682 MOD_SEL8_6
3683 MOD_SEL8_5
3684 MOD_SEL8_4
3685 MOD_SEL8_3
3686 MOD_SEL8_2
3687 MOD_SEL8_1
3688 MOD_SEL8_0))
3689 },
3690 { /* sentinel */ }
3691 };
3692
3693 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
3694 { PINMUX_DRIVE_REG("DRV0CTRL0", 0xE6050080) {
3695 { RCAR_GP_PIN(0, 7), 28, 3 }, /* MSIOF5_SS2 */
3696 { RCAR_GP_PIN(0, 6), 24, 3 }, /* IRQ0 */
3697 { RCAR_GP_PIN(0, 5), 20, 3 }, /* IRQ1 */
3698 { RCAR_GP_PIN(0, 4), 16, 3 }, /* IRQ2 */
3699 { RCAR_GP_PIN(0, 3), 12, 3 }, /* IRQ3 */
3700 { RCAR_GP_PIN(0, 2), 8, 3 }, /* GP0_02 */
3701 { RCAR_GP_PIN(0, 1), 4, 3 }, /* GP0_01 */
3702 { RCAR_GP_PIN(0, 0), 0, 3 }, /* GP0_00 */
3703 } },
3704 { PINMUX_DRIVE_REG("DRV1CTRL0", 0xE6050084) {
3705 { RCAR_GP_PIN(0, 15), 28, 3 }, /* MSIOF2_SYNC */
3706 { RCAR_GP_PIN(0, 14), 24, 3 }, /* MSIOF2_SS1 */
3707 { RCAR_GP_PIN(0, 13), 20, 3 }, /* MSIOF2_SS2 */
3708 { RCAR_GP_PIN(0, 12), 16, 3 }, /* MSIOF5_RXD */
3709 { RCAR_GP_PIN(0, 11), 12, 3 }, /* MSIOF5_SCK */
3710 { RCAR_GP_PIN(0, 10), 8, 3 }, /* MSIOF5_TXD */
3711 { RCAR_GP_PIN(0, 9), 4, 3 }, /* MSIOF5_SYNC */
3712 { RCAR_GP_PIN(0, 8), 0, 3 }, /* MSIOF5_SS1 */
3713 } },
3714 { PINMUX_DRIVE_REG("DRV2CTRL0", 0xE6050088) {
3715 { RCAR_GP_PIN(0, 18), 8, 3 }, /* MSIOF2_RXD */
3716 { RCAR_GP_PIN(0, 17), 4, 3 }, /* MSIOF2_SCK */
3717 { RCAR_GP_PIN(0, 16), 0, 3 }, /* MSIOF2_TXD */
3718 } },
3719 { PINMUX_DRIVE_REG("DRV0CTRL1", 0xE6050880) {
3720 { RCAR_GP_PIN(1, 7), 28, 3 }, /* MSIOF0_SS1 */
3721 { RCAR_GP_PIN(1, 6), 24, 3 }, /* MSIOF0_SS2 */
3722 { RCAR_GP_PIN(1, 5), 20, 3 }, /* MSIOF1_RXD */
3723 { RCAR_GP_PIN(1, 4), 16, 3 }, /* MSIOF1_TXD */
3724 { RCAR_GP_PIN(1, 3), 12, 3 }, /* MSIOF1_SCK */
3725 { RCAR_GP_PIN(1, 2), 8, 3 }, /* MSIOF1_SYNC */
3726 { RCAR_GP_PIN(1, 1), 4, 3 }, /* MSIOF1_SS1 */
3727 { RCAR_GP_PIN(1, 0), 0, 3 }, /* MSIOF1_SS2 */
3728 } },
3729 { PINMUX_DRIVE_REG("DRV1CTRL1", 0xE6050884) {
3730 { RCAR_GP_PIN(1, 15), 28, 3 }, /* HSCK0 */
3731 { RCAR_GP_PIN(1, 14), 24, 3 }, /* HRTS0_N */
3732 { RCAR_GP_PIN(1, 13), 20, 3 }, /* HCTS0_N */
3733 { RCAR_GP_PIN(1, 12), 16, 3 }, /* HTX0 */
3734 { RCAR_GP_PIN(1, 11), 12, 3 }, /* MSIOF0_RXD */
3735 { RCAR_GP_PIN(1, 10), 8, 3 }, /* MSIOF0_SCK */
3736 { RCAR_GP_PIN(1, 9), 4, 3 }, /* MSIOF0_TXD */
3737 { RCAR_GP_PIN(1, 8), 0, 3 }, /* MSIOF0_SYNC */
3738 } },
3739 { PINMUX_DRIVE_REG("DRV2CTRL1", 0xE6050888) {
3740 { RCAR_GP_PIN(1, 23), 28, 3 }, /* GP1_23 */
3741 { RCAR_GP_PIN(1, 22), 24, 3 }, /* AUDIO_CLKIN */
3742 { RCAR_GP_PIN(1, 21), 20, 3 }, /* AUDIO_CLKOUT */
3743 { RCAR_GP_PIN(1, 20), 16, 3 }, /* SSI_SD */
3744 { RCAR_GP_PIN(1, 19), 12, 3 }, /* SSI_WS */
3745 { RCAR_GP_PIN(1, 18), 8, 3 }, /* SSI_SCK */
3746 { RCAR_GP_PIN(1, 17), 4, 3 }, /* SCIF_CLK */
3747 { RCAR_GP_PIN(1, 16), 0, 3 }, /* HRX0 */
3748 } },
3749 { PINMUX_DRIVE_REG("DRV3CTRL1", 0xE605088C) {
3750 { RCAR_GP_PIN(1, 28), 16, 3 }, /* HTX3 */
3751 { RCAR_GP_PIN(1, 27), 12, 3 }, /* HCTS3_N */
3752 { RCAR_GP_PIN(1, 26), 8, 3 }, /* HRTS3_N */
3753 { RCAR_GP_PIN(1, 25), 4, 3 }, /* HSCK3 */
3754 { RCAR_GP_PIN(1, 24), 0, 3 }, /* HRX3 */
3755 } },
3756 { PINMUX_DRIVE_REG("DRV0CTRL2", 0xE6058080) {
3757 { RCAR_GP_PIN(2, 7), 28, 3 }, /* TPU0TO1 */
3758 { RCAR_GP_PIN(2, 6), 24, 3 }, /* FXR_TXDB */
3759 { RCAR_GP_PIN(2, 5), 20, 3 }, /* FXR_TXENB_N */
3760 { RCAR_GP_PIN(2, 4), 16, 3 }, /* RXDB_EXTFXR */
3761 { RCAR_GP_PIN(2, 3), 12, 3 }, /* CLK_EXTFXR */
3762 { RCAR_GP_PIN(2, 2), 8, 3 }, /* RXDA_EXTFXR */
3763 { RCAR_GP_PIN(2, 1), 4, 3 }, /* FXR_TXENA_N */
3764 { RCAR_GP_PIN(2, 0), 0, 3 }, /* FXR_TXDA */
3765 } },
3766 { PINMUX_DRIVE_REG("DRV1CTRL2", 0xE6058084) {
3767 { RCAR_GP_PIN(2, 15), 28, 3 }, /* CANFD3_RX */
3768 { RCAR_GP_PIN(2, 14), 24, 3 }, /* CANFD3_TX */
3769 { RCAR_GP_PIN(2, 13), 20, 3 }, /* CANFD2_RX */
3770 { RCAR_GP_PIN(2, 12), 16, 3 }, /* CANFD2_TX */
3771 { RCAR_GP_PIN(2, 11), 12, 3 }, /* CANFD0_RX */
3772 { RCAR_GP_PIN(2, 10), 8, 3 }, /* CANFD0_TX */
3773 { RCAR_GP_PIN(2, 9), 4, 3 }, /* CAN_CLK */
3774 { RCAR_GP_PIN(2, 8), 0, 3 }, /* TPU0TO0 */
3775 } },
3776 { PINMUX_DRIVE_REG("DRV2CTRL2", 0xE6058088) {
3777 { RCAR_GP_PIN(2, 19), 12, 3 }, /* CANFD7_RX */
3778 { RCAR_GP_PIN(2, 18), 8, 3 }, /* CANFD7_TX */
3779 { RCAR_GP_PIN(2, 17), 4, 3 }, /* CANFD4_RX */
3780 { RCAR_GP_PIN(2, 16), 0, 3 }, /* CANFD4_TX */
3781 } },
3782 { PINMUX_DRIVE_REG("DRV0CTRL3", 0xE6058880) {
3783 { RCAR_GP_PIN(3, 7), 28, 3 }, /* MMC_D4 */
3784 { RCAR_GP_PIN(3, 6), 24, 3 }, /* MMC_D5 */
3785 { RCAR_GP_PIN(3, 5), 20, 3 }, /* MMC_SD_D3 */
3786 { RCAR_GP_PIN(3, 4), 16, 3 }, /* MMC_DS */
3787 { RCAR_GP_PIN(3, 3), 12, 3 }, /* MMC_SD_CLK */
3788 { RCAR_GP_PIN(3, 2), 8, 3 }, /* MMC_SD_D2 */
3789 { RCAR_GP_PIN(3, 1), 4, 3 }, /* MMC_SD_D0 */
3790 { RCAR_GP_PIN(3, 0), 0, 3 }, /* MMC_SD_D1 */
3791 } },
3792 { PINMUX_DRIVE_REG("DRV1CTRL3", 0xE6058884) {
3793 { RCAR_GP_PIN(3, 15), 28, 2 }, /* QSPI0_SSL */
3794 { RCAR_GP_PIN(3, 14), 24, 2 }, /* IPC_CLKOUT */
3795 { RCAR_GP_PIN(3, 13), 20, 2 }, /* IPC_CLKIN */
3796 { RCAR_GP_PIN(3, 12), 16, 3 }, /* SD_WP */
3797 { RCAR_GP_PIN(3, 11), 12, 3 }, /* SD_CD */
3798 { RCAR_GP_PIN(3, 10), 8, 3 }, /* MMC_SD_CMD */
3799 { RCAR_GP_PIN(3, 9), 4, 3 }, /* MMC_D6*/
3800 { RCAR_GP_PIN(3, 8), 0, 3 }, /* MMC_D7 */
3801 } },
3802 { PINMUX_DRIVE_REG("DRV2CTRL3", 0xE6058888) {
3803 { RCAR_GP_PIN(3, 23), 28, 2 }, /* QSPI1_MISO_IO1 */
3804 { RCAR_GP_PIN(3, 22), 24, 2 }, /* QSPI1_SPCLK */
3805 { RCAR_GP_PIN(3, 21), 20, 2 }, /* QSPI1_MOSI_IO0 */
3806 { RCAR_GP_PIN(3, 20), 16, 2 }, /* QSPI0_SPCLK */
3807 { RCAR_GP_PIN(3, 19), 12, 2 }, /* QSPI0_MOSI_IO0 */
3808 { RCAR_GP_PIN(3, 18), 8, 2 }, /* QSPI0_MISO_IO1 */
3809 { RCAR_GP_PIN(3, 17), 4, 2 }, /* QSPI0_IO2 */
3810 { RCAR_GP_PIN(3, 16), 0, 2 }, /* QSPI0_IO3 */
3811 } },
3812 { PINMUX_DRIVE_REG("DRV3CTRL3", 0xE605888C) {
3813 { RCAR_GP_PIN(3, 29), 20, 2 }, /* RPC_INT_N */
3814 { RCAR_GP_PIN(3, 28), 16, 2 }, /* RPC_WP_N */
3815 { RCAR_GP_PIN(3, 27), 12, 2 }, /* RPC_RESET_N */
3816 { RCAR_GP_PIN(3, 26), 8, 2 }, /* QSPI1_IO3 */
3817 { RCAR_GP_PIN(3, 25), 4, 2 }, /* QSPI1_SSL */
3818 { RCAR_GP_PIN(3, 24), 0, 2 }, /* QSPI1_IO2 */
3819 } },
3820 { PINMUX_DRIVE_REG("DRV0CTRL4", 0xE6060080) {
3821 { RCAR_GP_PIN(4, 7), 28, 3 }, /* TSN0_RX_CTL */
3822 { RCAR_GP_PIN(4, 6), 24, 3 }, /* TSN0_AVTP_CAPTURE */
3823 { RCAR_GP_PIN(4, 5), 20, 3 }, /* TSN0_AVTP_MATCH */
3824 { RCAR_GP_PIN(4, 4), 16, 3 }, /* TSN0_LINK */
3825 { RCAR_GP_PIN(4, 3), 12, 3 }, /* TSN0_PHY_INT */
3826 { RCAR_GP_PIN(4, 2), 8, 3 }, /* TSN0_AVTP_PPS1 */
3827 { RCAR_GP_PIN(4, 1), 4, 3 }, /* TSN0_MDC */
3828 { RCAR_GP_PIN(4, 0), 0, 3 }, /* TSN0_MDIO */
3829 } },
3830 { PINMUX_DRIVE_REG("DRV1CTRL4", 0xE6060084) {
3831 { RCAR_GP_PIN(4, 15), 28, 3 }, /* TSN0_TD0 */
3832 { RCAR_GP_PIN(4, 14), 24, 3 }, /* TSN0_TD1 */
3833 { RCAR_GP_PIN(4, 13), 20, 3 }, /* TSN0_RD1 */
3834 { RCAR_GP_PIN(4, 12), 16, 3 }, /* TSN0_TXC */
3835 { RCAR_GP_PIN(4, 11), 12, 3 }, /* TSN0_RXC */
3836 { RCAR_GP_PIN(4, 10), 8, 3 }, /* TSN0_RD0 */
3837 { RCAR_GP_PIN(4, 9), 4, 3 }, /* TSN0_TX_CTL */
3838 { RCAR_GP_PIN(4, 8), 0, 3 }, /* TSN0_AVTP_PPS0 */
3839 } },
3840 { PINMUX_DRIVE_REG("DRV2CTRL4", 0xE6060088) {
3841 { RCAR_GP_PIN(4, 23), 28, 3 }, /* AVS0 */
3842 { RCAR_GP_PIN(4, 22), 24, 3 }, /* PCIE1_CLKREQ_N */
3843 { RCAR_GP_PIN(4, 21), 20, 3 }, /* PCIE0_CLKREQ_N */
3844 { RCAR_GP_PIN(4, 20), 16, 3 }, /* TSN0_TXCREFCLK */
3845 { RCAR_GP_PIN(4, 19), 12, 3 }, /* TSN0_TD2 */
3846 { RCAR_GP_PIN(4, 18), 8, 3 }, /* TSN0_TD3 */
3847 { RCAR_GP_PIN(4, 17), 4, 3 }, /* TSN0_RD2 */
3848 { RCAR_GP_PIN(4, 16), 0, 3 }, /* TSN0_RD3 */
3849 } },
3850 { PINMUX_DRIVE_REG("DRV3CTRL4", 0xE606008C) {
3851 { RCAR_GP_PIN(4, 24), 0, 3 }, /* AVS1 */
3852 } },
3853 { PINMUX_DRIVE_REG("DRV0CTRL5", 0xE6060880) {
3854 { RCAR_GP_PIN(5, 7), 28, 3 }, /* AVB2_TXCREFCLK */
3855 { RCAR_GP_PIN(5, 6), 24, 3 }, /* AVB2_MDC */
3856 { RCAR_GP_PIN(5, 5), 20, 3 }, /* AVB2_MAGIC */
3857 { RCAR_GP_PIN(5, 4), 16, 3 }, /* AVB2_PHY_INT */
3858 { RCAR_GP_PIN(5, 3), 12, 3 }, /* AVB2_LINK */
3859 { RCAR_GP_PIN(5, 2), 8, 3 }, /* AVB2_AVTP_MATCH */
3860 { RCAR_GP_PIN(5, 1), 4, 3 }, /* AVB2_AVTP_CAPTURE */
3861 { RCAR_GP_PIN(5, 0), 0, 3 }, /* AVB2_AVTP_PPS */
3862 } },
3863 { PINMUX_DRIVE_REG("DRV1CTRL5", 0xE6060884) {
3864 { RCAR_GP_PIN(5, 15), 28, 3 }, /* AVB2_TD0 */
3865 { RCAR_GP_PIN(5, 14), 24, 3 }, /* AVB2_RD1 */
3866 { RCAR_GP_PIN(5, 13), 20, 3 }, /* AVB2_RD2 */
3867 { RCAR_GP_PIN(5, 12), 16, 3 }, /* AVB2_TD1 */
3868 { RCAR_GP_PIN(5, 11), 12, 3 }, /* AVB2_TD2 */
3869 { RCAR_GP_PIN(5, 10), 8, 3 }, /* AVB2_MDIO */
3870 { RCAR_GP_PIN(5, 9), 4, 3 }, /* AVB2_RD3 */
3871 { RCAR_GP_PIN(5, 8), 0, 3 }, /* AVB2_TD3 */
3872 } },
3873 { PINMUX_DRIVE_REG("DRV2CTRL5", 0xE6060888) {
3874 { RCAR_GP_PIN(5, 20), 16, 3 }, /* AVB2_RX_CTL */
3875 { RCAR_GP_PIN(5, 19), 12, 3 }, /* AVB2_TX_CTL */
3876 { RCAR_GP_PIN(5, 18), 8, 3 }, /* AVB2_RXC */
3877 { RCAR_GP_PIN(5, 17), 4, 3 }, /* AVB2_RD0 */
3878 { RCAR_GP_PIN(5, 16), 0, 3 }, /* AVB2_TXC */
3879 } },
3880 { PINMUX_DRIVE_REG("DRV0CTRL6", 0xE6061080) {
3881 { RCAR_GP_PIN(6, 7), 28, 3 }, /* AVB1_TX_CTL */
3882 { RCAR_GP_PIN(6, 6), 24, 3 }, /* AVB1_TXC */
3883 { RCAR_GP_PIN(6, 5), 20, 3 }, /* AVB1_AVTP_MATCH */
3884 { RCAR_GP_PIN(6, 4), 16, 3 }, /* AVB1_LINK */
3885 { RCAR_GP_PIN(6, 3), 12, 3 }, /* AVB1_PHY_INT */
3886 { RCAR_GP_PIN(6, 2), 8, 3 }, /* AVB1_MDC */
3887 { RCAR_GP_PIN(6, 1), 4, 3 }, /* AVB1_MAGIC */
3888 { RCAR_GP_PIN(6, 0), 0, 3 }, /* AVB1_MDIO */
3889 } },
3890 { PINMUX_DRIVE_REG("DRV1CTRL6", 0xE6061084) {
3891 { RCAR_GP_PIN(6, 15), 28, 3 }, /* AVB1_RD0 */
3892 { RCAR_GP_PIN(6, 14), 24, 3 }, /* AVB1_RD1 */
3893 { RCAR_GP_PIN(6, 13), 20, 3 }, /* AVB1_TD0 */
3894 { RCAR_GP_PIN(6, 12), 16, 3 }, /* AVB1_TD1 */
3895 { RCAR_GP_PIN(6, 11), 12, 3 }, /* AVB1_AVTP_CAPTURE */
3896 { RCAR_GP_PIN(6, 10), 8, 3 }, /* AVB1_AVTP_PPS */
3897 { RCAR_GP_PIN(6, 9), 4, 3 }, /* AVB1_RX_CTL */
3898 { RCAR_GP_PIN(6, 8), 0, 3 }, /* AVB1_RXC */
3899 } },
3900 { PINMUX_DRIVE_REG("DRV2CTRL6", 0xE6061088) {
3901 { RCAR_GP_PIN(6, 20), 16, 3 }, /* AVB1_TXCREFCLK */
3902 { RCAR_GP_PIN(6, 19), 12, 3 }, /* AVB1_RD3 */
3903 { RCAR_GP_PIN(6, 18), 8, 3 }, /* AVB1_TD3 */
3904 { RCAR_GP_PIN(6, 17), 4, 3 }, /* AVB1_RD2 */
3905 { RCAR_GP_PIN(6, 16), 0, 3 }, /* AVB1_TD2 */
3906 } },
3907 { PINMUX_DRIVE_REG("DRV0CTRL7", 0xE6061880) {
3908 { RCAR_GP_PIN(7, 7), 28, 3 }, /* AVB0_TD1 */
3909 { RCAR_GP_PIN(7, 6), 24, 3 }, /* AVB0_TD2 */
3910 { RCAR_GP_PIN(7, 5), 20, 3 }, /* AVB0_PHY_INT */
3911 { RCAR_GP_PIN(7, 4), 16, 3 }, /* AVB0_LINK */
3912 { RCAR_GP_PIN(7, 3), 12, 3 }, /* AVB0_TD3 */
3913 { RCAR_GP_PIN(7, 2), 8, 3 }, /* AVB0_AVTP_MATCH */
3914 { RCAR_GP_PIN(7, 1), 4, 3 }, /* AVB0_AVTP_CAPTURE */
3915 { RCAR_GP_PIN(7, 0), 0, 3 }, /* AVB0_AVTP_PPS */
3916 } },
3917 { PINMUX_DRIVE_REG("DRV1CTRL7", 0xE6061884) {
3918 { RCAR_GP_PIN(7, 15), 28, 3 }, /* AVB0_TXC */
3919 { RCAR_GP_PIN(7, 14), 24, 3 }, /* AVB0_MDIO */
3920 { RCAR_GP_PIN(7, 13), 20, 3 }, /* AVB0_MDC */
3921 { RCAR_GP_PIN(7, 12), 16, 3 }, /* AVB0_RD2 */
3922 { RCAR_GP_PIN(7, 11), 12, 3 }, /* AVB0_TD0 */
3923 { RCAR_GP_PIN(7, 10), 8, 3 }, /* AVB0_MAGIC */
3924 { RCAR_GP_PIN(7, 9), 4, 3 }, /* AVB0_TXCREFCLK */
3925 { RCAR_GP_PIN(7, 8), 0, 3 }, /* AVB0_RD3 */
3926 } },
3927 { PINMUX_DRIVE_REG("DRV2CTRL7", 0xE6061888) {
3928 { RCAR_GP_PIN(7, 20), 16, 3 }, /* AVB0_RX_CTL */
3929 { RCAR_GP_PIN(7, 19), 12, 3 }, /* AVB0_RXC */
3930 { RCAR_GP_PIN(7, 18), 8, 3 }, /* AVB0_RD0 */
3931 { RCAR_GP_PIN(7, 17), 4, 3 }, /* AVB0_RD1 */
3932 { RCAR_GP_PIN(7, 16), 0, 3 }, /* AVB0_TX_CTL */
3933 } },
3934 { PINMUX_DRIVE_REG("DRV0CTRL8", 0xE6068080) {
3935 { RCAR_GP_PIN(8, 7), 28, 3 }, /* SDA3 */
3936 { RCAR_GP_PIN(8, 6), 24, 3 }, /* SCL3 */
3937 { RCAR_GP_PIN(8, 5), 20, 3 }, /* SDA2 */
3938 { RCAR_GP_PIN(8, 4), 16, 3 }, /* SCL2 */
3939 { RCAR_GP_PIN(8, 3), 12, 3 }, /* SDA1 */
3940 { RCAR_GP_PIN(8, 2), 8, 3 }, /* SCL1 */
3941 { RCAR_GP_PIN(8, 1), 4, 3 }, /* SDA0 */
3942 { RCAR_GP_PIN(8, 0), 0, 3 }, /* SCL0 */
3943 } },
3944 { PINMUX_DRIVE_REG("DRV1CTRL8", 0xE6068084) {
3945 { RCAR_GP_PIN(8, 13), 20, 3 }, /* GP8_13 */
3946 { RCAR_GP_PIN(8, 12), 16, 3 }, /* GP8_12 */
3947 { RCAR_GP_PIN(8, 11), 12, 3 }, /* SDA5 */
3948 { RCAR_GP_PIN(8, 10), 8, 3 }, /* SCL5 */
3949 { RCAR_GP_PIN(8, 9), 4, 3 }, /* SDA4 */
3950 { RCAR_GP_PIN(8, 8), 0, 3 }, /* SCL4 */
3951 } },
3952 { /* sentinel */ }
3953 };
3954
3955 enum ioctrl_regs {
3956 POC0,
3957 POC1,
3958 POC3,
3959 POC4,
3960 POC5,
3961 POC6,
3962 POC7,
3963 POC8,
3964 };
3965
3966 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
3967 [POC0] = { 0xE60500A0, },
3968 [POC1] = { 0xE60508A0, },
3969 [POC3] = { 0xE60588A0, },
3970 [POC4] = { 0xE60600A0, },
3971 [POC5] = { 0xE60608A0, },
3972 [POC6] = { 0xE60610A0, },
3973 [POC7] = { 0xE60618A0, },
3974 [POC8] = { 0xE60680A0, },
3975 { /* sentinel */ }
3976 };
3977
r8a779g0_pin_to_pocctrl(unsigned int pin,u32 * pocctrl)3978 static int r8a779g0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
3979 {
3980 int bit = pin & 0x1f;
3981
3982 switch (pin) {
3983 case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 18):
3984 *pocctrl = pinmux_ioctrl_regs[POC0].reg;
3985 return bit;
3986
3987 case RCAR_GP_PIN(1, 0) ... RCAR_GP_PIN(1, 22):
3988 *pocctrl = pinmux_ioctrl_regs[POC1].reg;
3989 return bit;
3990
3991 case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 12):
3992 *pocctrl = pinmux_ioctrl_regs[POC3].reg;
3993 return bit;
3994
3995 case PIN_VDDQ_TSN0:
3996 *pocctrl = pinmux_ioctrl_regs[POC4].reg;
3997 return 0;
3998
3999 case PIN_VDDQ_AVB2:
4000 *pocctrl = pinmux_ioctrl_regs[POC5].reg;
4001 return 0;
4002
4003 case PIN_VDDQ_AVB1:
4004 *pocctrl = pinmux_ioctrl_regs[POC6].reg;
4005 return 0;
4006
4007 case PIN_VDDQ_AVB0:
4008 *pocctrl = pinmux_ioctrl_regs[POC7].reg;
4009 return 0;
4010
4011 case RCAR_GP_PIN(8, 0) ... RCAR_GP_PIN(8, 13):
4012 *pocctrl = pinmux_ioctrl_regs[POC8].reg;
4013 return bit;
4014
4015 default:
4016 return -EINVAL;
4017 }
4018 }
4019
4020 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
4021 { PINMUX_BIAS_REG("PUEN0", 0xE60500C0, "PUD0", 0xE60500E0) {
4022 [ 0] = RCAR_GP_PIN(0, 0), /* GP0_00 */
4023 [ 1] = RCAR_GP_PIN(0, 1), /* GP0_01 */
4024 [ 2] = RCAR_GP_PIN(0, 2), /* GP0_02 */
4025 [ 3] = RCAR_GP_PIN(0, 3), /* IRQ3 */
4026 [ 4] = RCAR_GP_PIN(0, 4), /* IRQ2 */
4027 [ 5] = RCAR_GP_PIN(0, 5), /* IRQ1 */
4028 [ 6] = RCAR_GP_PIN(0, 6), /* IRQ0 */
4029 [ 7] = RCAR_GP_PIN(0, 7), /* MSIOF5_SS2 */
4030 [ 8] = RCAR_GP_PIN(0, 8), /* MSIOF5_SS1 */
4031 [ 9] = RCAR_GP_PIN(0, 9), /* MSIOF5_SYNC */
4032 [10] = RCAR_GP_PIN(0, 10), /* MSIOF5_TXD */
4033 [11] = RCAR_GP_PIN(0, 11), /* MSIOF5_SCK */
4034 [12] = RCAR_GP_PIN(0, 12), /* MSIOF5_RXD */
4035 [13] = RCAR_GP_PIN(0, 13), /* MSIOF2_SS2 */
4036 [14] = RCAR_GP_PIN(0, 14), /* MSIOF2_SS1 */
4037 [15] = RCAR_GP_PIN(0, 15), /* MSIOF2_SYNC */
4038 [16] = RCAR_GP_PIN(0, 16), /* MSIOF2_TXD */
4039 [17] = RCAR_GP_PIN(0, 17), /* MSIOF2_SCK */
4040 [18] = RCAR_GP_PIN(0, 18), /* MSIOF2_RXD */
4041 [19] = SH_PFC_PIN_NONE,
4042 [20] = SH_PFC_PIN_NONE,
4043 [21] = SH_PFC_PIN_NONE,
4044 [22] = SH_PFC_PIN_NONE,
4045 [23] = SH_PFC_PIN_NONE,
4046 [24] = SH_PFC_PIN_NONE,
4047 [25] = SH_PFC_PIN_NONE,
4048 [26] = SH_PFC_PIN_NONE,
4049 [27] = SH_PFC_PIN_NONE,
4050 [28] = SH_PFC_PIN_NONE,
4051 [29] = SH_PFC_PIN_NONE,
4052 [30] = SH_PFC_PIN_NONE,
4053 [31] = SH_PFC_PIN_NONE,
4054 } },
4055 { PINMUX_BIAS_REG("PUEN1", 0xE60508C0, "PUD1", 0xE60508E0) {
4056 [ 0] = RCAR_GP_PIN(1, 0), /* MSIOF1_SS2 */
4057 [ 1] = RCAR_GP_PIN(1, 1), /* MSIOF1_SS1 */
4058 [ 2] = RCAR_GP_PIN(1, 2), /* MSIOF1_SYNC */
4059 [ 3] = RCAR_GP_PIN(1, 3), /* MSIOF1_SCK */
4060 [ 4] = RCAR_GP_PIN(1, 4), /* MSIOF1_TXD */
4061 [ 5] = RCAR_GP_PIN(1, 5), /* MSIOF1_RXD */
4062 [ 6] = RCAR_GP_PIN(1, 6), /* MSIOF0_SS2 */
4063 [ 7] = RCAR_GP_PIN(1, 7), /* MSIOF0_SS1 */
4064 [ 8] = RCAR_GP_PIN(1, 8), /* MSIOF0_SYNC */
4065 [ 9] = RCAR_GP_PIN(1, 9), /* MSIOF0_TXD */
4066 [10] = RCAR_GP_PIN(1, 10), /* MSIOF0_SCK */
4067 [11] = RCAR_GP_PIN(1, 11), /* MSIOF0_RXD */
4068 [12] = RCAR_GP_PIN(1, 12), /* HTX0 */
4069 [13] = RCAR_GP_PIN(1, 13), /* HCTS0_N */
4070 [14] = RCAR_GP_PIN(1, 14), /* HRTS0_N */
4071 [15] = RCAR_GP_PIN(1, 15), /* HSCK0 */
4072 [16] = RCAR_GP_PIN(1, 16), /* HRX0 */
4073 [17] = RCAR_GP_PIN(1, 17), /* SCIF_CLK */
4074 [18] = RCAR_GP_PIN(1, 18), /* SSI_SCK */
4075 [19] = RCAR_GP_PIN(1, 19), /* SSI_WS */
4076 [20] = RCAR_GP_PIN(1, 20), /* SSI_SD */
4077 [21] = RCAR_GP_PIN(1, 21), /* AUDIO_CLKOUT */
4078 [22] = RCAR_GP_PIN(1, 22), /* AUDIO_CLKIN */
4079 [23] = RCAR_GP_PIN(1, 23), /* GP1_23 */
4080 [24] = RCAR_GP_PIN(1, 24), /* HRX3 */
4081 [25] = RCAR_GP_PIN(1, 25), /* HSCK3 */
4082 [26] = RCAR_GP_PIN(1, 26), /* HRTS3_N */
4083 [27] = RCAR_GP_PIN(1, 27), /* HCTS3_N */
4084 [28] = RCAR_GP_PIN(1, 28), /* HTX3 */
4085 [29] = SH_PFC_PIN_NONE,
4086 [30] = SH_PFC_PIN_NONE,
4087 [31] = SH_PFC_PIN_NONE,
4088 } },
4089 { PINMUX_BIAS_REG("PUEN2", 0xE60580C0, "PUD2", 0xE60580E0) {
4090 [ 0] = RCAR_GP_PIN(2, 0), /* FXR_TXDA */
4091 [ 1] = RCAR_GP_PIN(2, 1), /* FXR_TXENA_N */
4092 [ 2] = RCAR_GP_PIN(2, 2), /* RXDA_EXTFXR */
4093 [ 3] = RCAR_GP_PIN(2, 3), /* CLK_EXTFXR */
4094 [ 4] = RCAR_GP_PIN(2, 4), /* RXDB_EXTFXR */
4095 [ 5] = RCAR_GP_PIN(2, 5), /* FXR_TXENB_N */
4096 [ 6] = RCAR_GP_PIN(2, 6), /* FXR_TXDB */
4097 [ 7] = RCAR_GP_PIN(2, 7), /* TPU0TO1 */
4098 [ 8] = RCAR_GP_PIN(2, 8), /* TPU0TO0 */
4099 [ 9] = RCAR_GP_PIN(2, 9), /* CAN_CLK */
4100 [10] = RCAR_GP_PIN(2, 10), /* CANFD0_TX */
4101 [11] = RCAR_GP_PIN(2, 11), /* CANFD0_RX */
4102 [12] = RCAR_GP_PIN(2, 12), /* CANFD2_TX */
4103 [13] = RCAR_GP_PIN(2, 13), /* CANFD2_RX */
4104 [14] = RCAR_GP_PIN(2, 14), /* CANFD3_TX */
4105 [15] = RCAR_GP_PIN(2, 15), /* CANFD3_RX */
4106 [16] = RCAR_GP_PIN(2, 16), /* CANFD4_TX */
4107 [17] = RCAR_GP_PIN(2, 17), /* CANFD4_RX */
4108 [18] = RCAR_GP_PIN(2, 18), /* CANFD7_TX */
4109 [19] = RCAR_GP_PIN(2, 19), /* CANFD7_RX */
4110 [20] = SH_PFC_PIN_NONE,
4111 [21] = SH_PFC_PIN_NONE,
4112 [22] = SH_PFC_PIN_NONE,
4113 [23] = SH_PFC_PIN_NONE,
4114 [24] = SH_PFC_PIN_NONE,
4115 [25] = SH_PFC_PIN_NONE,
4116 [26] = SH_PFC_PIN_NONE,
4117 [27] = SH_PFC_PIN_NONE,
4118 [28] = SH_PFC_PIN_NONE,
4119 [29] = SH_PFC_PIN_NONE,
4120 [30] = SH_PFC_PIN_NONE,
4121 [31] = SH_PFC_PIN_NONE,
4122 } },
4123 { PINMUX_BIAS_REG("PUEN3", 0xE60588C0, "PUD3", 0xE60588E0) {
4124 [ 0] = RCAR_GP_PIN(3, 0), /* MMC_SD_D1 */
4125 [ 1] = RCAR_GP_PIN(3, 1), /* MMC_SD_D0 */
4126 [ 2] = RCAR_GP_PIN(3, 2), /* MMC_SD_D2 */
4127 [ 3] = RCAR_GP_PIN(3, 3), /* MMC_SD_CLK */
4128 [ 4] = RCAR_GP_PIN(3, 4), /* MMC_DS */
4129 [ 5] = RCAR_GP_PIN(3, 5), /* MMC_SD_D3 */
4130 [ 6] = RCAR_GP_PIN(3, 6), /* MMC_D5 */
4131 [ 7] = RCAR_GP_PIN(3, 7), /* MMC_D4 */
4132 [ 8] = RCAR_GP_PIN(3, 8), /* MMC_D7 */
4133 [ 9] = RCAR_GP_PIN(3, 9), /* MMC_D6 */
4134 [10] = RCAR_GP_PIN(3, 10), /* MMC_SD_CMD */
4135 [11] = RCAR_GP_PIN(3, 11), /* SD_CD */
4136 [12] = RCAR_GP_PIN(3, 12), /* SD_WP */
4137 [13] = RCAR_GP_PIN(3, 13), /* IPC_CLKIN */
4138 [14] = RCAR_GP_PIN(3, 14), /* IPC_CLKOUT */
4139 [15] = RCAR_GP_PIN(3, 15), /* QSPI0_SSL */
4140 [16] = RCAR_GP_PIN(3, 16), /* QSPI0_IO3 */
4141 [17] = RCAR_GP_PIN(3, 17), /* QSPI0_IO2 */
4142 [18] = RCAR_GP_PIN(3, 18), /* QSPI0_MISO_IO1 */
4143 [19] = RCAR_GP_PIN(3, 19), /* QSPI0_MOSI_IO0 */
4144 [20] = RCAR_GP_PIN(3, 20), /* QSPI0_SPCLK */
4145 [21] = RCAR_GP_PIN(3, 21), /* QSPI1_MOSI_IO0 */
4146 [22] = RCAR_GP_PIN(3, 22), /* QSPI1_SPCLK */
4147 [23] = RCAR_GP_PIN(3, 23), /* QSPI1_MISO_IO1 */
4148 [24] = RCAR_GP_PIN(3, 24), /* QSPI1_IO2 */
4149 [25] = RCAR_GP_PIN(3, 25), /* QSPI1_SSL */
4150 [26] = RCAR_GP_PIN(3, 26), /* QSPI1_IO3 */
4151 [27] = RCAR_GP_PIN(3, 27), /* RPC_RESET_N */
4152 [28] = RCAR_GP_PIN(3, 28), /* RPC_WP_N */
4153 [29] = RCAR_GP_PIN(3, 29), /* RPC_INT_N */
4154 [30] = SH_PFC_PIN_NONE,
4155 [31] = SH_PFC_PIN_NONE,
4156 } },
4157 { PINMUX_BIAS_REG("PUEN4", 0xE60600C0, "PUD4", 0xE60600E0) {
4158 [ 0] = RCAR_GP_PIN(4, 0), /* TSN0_MDIO */
4159 [ 1] = RCAR_GP_PIN(4, 1), /* TSN0_MDC */
4160 [ 2] = RCAR_GP_PIN(4, 2), /* TSN0_AVTP_PPS1 */
4161 [ 3] = RCAR_GP_PIN(4, 3), /* TSN0_PHY_INT */
4162 [ 4] = RCAR_GP_PIN(4, 4), /* TSN0_LINK */
4163 [ 5] = RCAR_GP_PIN(4, 5), /* TSN0_AVTP_MATCH */
4164 [ 6] = RCAR_GP_PIN(4, 6), /* TSN0_AVTP_CAPTURE */
4165 [ 7] = RCAR_GP_PIN(4, 7), /* TSN0_RX_CTL */
4166 [ 8] = RCAR_GP_PIN(4, 8), /* TSN0_AVTP_PPS0 */
4167 [ 9] = RCAR_GP_PIN(4, 9), /* TSN0_TX_CTL */
4168 [10] = RCAR_GP_PIN(4, 10), /* TSN0_RD0 */
4169 [11] = RCAR_GP_PIN(4, 11), /* TSN0_RXC */
4170 [12] = RCAR_GP_PIN(4, 12), /* TSN0_TXC */
4171 [13] = RCAR_GP_PIN(4, 13), /* TSN0_RD1 */
4172 [14] = RCAR_GP_PIN(4, 14), /* TSN0_TD1 */
4173 [15] = RCAR_GP_PIN(4, 15), /* TSN0_TD0 */
4174 [16] = RCAR_GP_PIN(4, 16), /* TSN0_RD3 */
4175 [17] = RCAR_GP_PIN(4, 17), /* TSN0_RD2 */
4176 [18] = RCAR_GP_PIN(4, 18), /* TSN0_TD3 */
4177 [19] = RCAR_GP_PIN(4, 19), /* TSN0_TD2 */
4178 [20] = RCAR_GP_PIN(4, 20), /* TSN0_TXCREFCLK */
4179 [21] = RCAR_GP_PIN(4, 21), /* PCIE0_CLKREQ_N */
4180 [22] = RCAR_GP_PIN(4, 22), /* PCIE1_CLKREQ_N */
4181 [23] = RCAR_GP_PIN(4, 23), /* AVS0 */
4182 [24] = RCAR_GP_PIN(4, 24), /* AVS1 */
4183 [25] = SH_PFC_PIN_NONE,
4184 [26] = SH_PFC_PIN_NONE,
4185 [27] = SH_PFC_PIN_NONE,
4186 [28] = SH_PFC_PIN_NONE,
4187 [29] = SH_PFC_PIN_NONE,
4188 [30] = SH_PFC_PIN_NONE,
4189 [31] = SH_PFC_PIN_NONE,
4190 } },
4191 { PINMUX_BIAS_REG("PUEN5", 0xE60608C0, "PUD5", 0xE60608E0) {
4192 [ 0] = RCAR_GP_PIN(5, 0), /* AVB2_AVTP_PPS */
4193 [ 1] = RCAR_GP_PIN(5, 1), /* AVB0_AVTP_CAPTURE */
4194 [ 2] = RCAR_GP_PIN(5, 2), /* AVB2_AVTP_MATCH */
4195 [ 3] = RCAR_GP_PIN(5, 3), /* AVB2_LINK */
4196 [ 4] = RCAR_GP_PIN(5, 4), /* AVB2_PHY_INT */
4197 [ 5] = RCAR_GP_PIN(5, 5), /* AVB2_MAGIC */
4198 [ 6] = RCAR_GP_PIN(5, 6), /* AVB2_MDC */
4199 [ 7] = RCAR_GP_PIN(5, 7), /* AVB2_TXCREFCLK */
4200 [ 8] = RCAR_GP_PIN(5, 8), /* AVB2_TD3 */
4201 [ 9] = RCAR_GP_PIN(5, 9), /* AVB2_RD3 */
4202 [10] = RCAR_GP_PIN(5, 10), /* AVB2_MDIO */
4203 [11] = RCAR_GP_PIN(5, 11), /* AVB2_TD2 */
4204 [12] = RCAR_GP_PIN(5, 12), /* AVB2_TD1 */
4205 [13] = RCAR_GP_PIN(5, 13), /* AVB2_RD2 */
4206 [14] = RCAR_GP_PIN(5, 14), /* AVB2_RD1 */
4207 [15] = RCAR_GP_PIN(5, 15), /* AVB2_TD0 */
4208 [16] = RCAR_GP_PIN(5, 16), /* AVB2_TXC */
4209 [17] = RCAR_GP_PIN(5, 17), /* AVB2_RD0 */
4210 [18] = RCAR_GP_PIN(5, 18), /* AVB2_RXC */
4211 [19] = RCAR_GP_PIN(5, 19), /* AVB2_TX_CTL */
4212 [20] = RCAR_GP_PIN(5, 20), /* AVB2_RX_CTL */
4213 [21] = SH_PFC_PIN_NONE,
4214 [22] = SH_PFC_PIN_NONE,
4215 [23] = SH_PFC_PIN_NONE,
4216 [24] = SH_PFC_PIN_NONE,
4217 [25] = SH_PFC_PIN_NONE,
4218 [26] = SH_PFC_PIN_NONE,
4219 [27] = SH_PFC_PIN_NONE,
4220 [28] = SH_PFC_PIN_NONE,
4221 [29] = SH_PFC_PIN_NONE,
4222 [30] = SH_PFC_PIN_NONE,
4223 [31] = SH_PFC_PIN_NONE,
4224 } },
4225 { PINMUX_BIAS_REG("PUEN6", 0xE60610C0, "PUD6", 0xE60610E0) {
4226 [ 0] = RCAR_GP_PIN(6, 0), /* AVB1_MDIO */
4227 [ 1] = RCAR_GP_PIN(6, 1), /* AVB1_MAGIC */
4228 [ 2] = RCAR_GP_PIN(6, 2), /* AVB1_MDC */
4229 [ 3] = RCAR_GP_PIN(6, 3), /* AVB1_PHY_INT */
4230 [ 4] = RCAR_GP_PIN(6, 4), /* AVB1_LINK */
4231 [ 5] = RCAR_GP_PIN(6, 5), /* AVB1_AVTP_MATCH */
4232 [ 6] = RCAR_GP_PIN(6, 6), /* AVB1_TXC */
4233 [ 7] = RCAR_GP_PIN(6, 7), /* AVB1_TX_CTL */
4234 [ 8] = RCAR_GP_PIN(6, 8), /* AVB1_RXC */
4235 [ 9] = RCAR_GP_PIN(6, 9), /* AVB1_RX_CTL */
4236 [10] = RCAR_GP_PIN(6, 10), /* AVB1_AVTP_PPS */
4237 [11] = RCAR_GP_PIN(6, 11), /* AVB1_AVTP_CAPTURE */
4238 [12] = RCAR_GP_PIN(6, 12), /* AVB1_TD1 */
4239 [13] = RCAR_GP_PIN(6, 13), /* AVB1_TD0 */
4240 [14] = RCAR_GP_PIN(6, 14), /* AVB1_RD1*/
4241 [15] = RCAR_GP_PIN(6, 15), /* AVB1_RD0 */
4242 [16] = RCAR_GP_PIN(6, 16), /* AVB1_TD2 */
4243 [17] = RCAR_GP_PIN(6, 17), /* AVB1_RD2 */
4244 [18] = RCAR_GP_PIN(6, 18), /* AVB1_TD3 */
4245 [19] = RCAR_GP_PIN(6, 19), /* AVB1_RD3 */
4246 [20] = RCAR_GP_PIN(6, 20), /* AVB1_TXCREFCLK */
4247 [21] = SH_PFC_PIN_NONE,
4248 [22] = SH_PFC_PIN_NONE,
4249 [23] = SH_PFC_PIN_NONE,
4250 [24] = SH_PFC_PIN_NONE,
4251 [25] = SH_PFC_PIN_NONE,
4252 [26] = SH_PFC_PIN_NONE,
4253 [27] = SH_PFC_PIN_NONE,
4254 [28] = SH_PFC_PIN_NONE,
4255 [29] = SH_PFC_PIN_NONE,
4256 [30] = SH_PFC_PIN_NONE,
4257 [31] = SH_PFC_PIN_NONE,
4258 } },
4259 { PINMUX_BIAS_REG("PUEN7", 0xE60618C0, "PUD7", 0xE60618E0) {
4260 [ 0] = RCAR_GP_PIN(7, 0), /* AVB0_AVTP_PPS */
4261 [ 1] = RCAR_GP_PIN(7, 1), /* AVB0_AVTP_CAPTURE */
4262 [ 2] = RCAR_GP_PIN(7, 2), /* AVB0_AVTP_MATCH */
4263 [ 3] = RCAR_GP_PIN(7, 3), /* AVB0_TD3 */
4264 [ 4] = RCAR_GP_PIN(7, 4), /* AVB0_LINK */
4265 [ 5] = RCAR_GP_PIN(7, 5), /* AVB0_PHY_INT */
4266 [ 6] = RCAR_GP_PIN(7, 6), /* AVB0_TD2 */
4267 [ 7] = RCAR_GP_PIN(7, 7), /* AVB0_TD1 */
4268 [ 8] = RCAR_GP_PIN(7, 8), /* AVB0_RD3 */
4269 [ 9] = RCAR_GP_PIN(7, 9), /* AVB0_TXCREFCLK */
4270 [10] = RCAR_GP_PIN(7, 10), /* AVB0_MAGIC */
4271 [11] = RCAR_GP_PIN(7, 11), /* AVB0_TD0 */
4272 [12] = RCAR_GP_PIN(7, 12), /* AVB0_RD2 */
4273 [13] = RCAR_GP_PIN(7, 13), /* AVB0_MDC */
4274 [14] = RCAR_GP_PIN(7, 14), /* AVB0_MDIO */
4275 [15] = RCAR_GP_PIN(7, 15), /* AVB0_TXC */
4276 [16] = RCAR_GP_PIN(7, 16), /* AVB0_TX_CTL */
4277 [17] = RCAR_GP_PIN(7, 17), /* AVB0_RD1 */
4278 [18] = RCAR_GP_PIN(7, 18), /* AVB0_RD0 */
4279 [19] = RCAR_GP_PIN(7, 19), /* AVB0_RXC */
4280 [20] = RCAR_GP_PIN(7, 20), /* AVB0_RX_CTL */
4281 [21] = SH_PFC_PIN_NONE,
4282 [22] = SH_PFC_PIN_NONE,
4283 [23] = SH_PFC_PIN_NONE,
4284 [24] = SH_PFC_PIN_NONE,
4285 [25] = SH_PFC_PIN_NONE,
4286 [26] = SH_PFC_PIN_NONE,
4287 [27] = SH_PFC_PIN_NONE,
4288 [28] = SH_PFC_PIN_NONE,
4289 [29] = SH_PFC_PIN_NONE,
4290 [30] = SH_PFC_PIN_NONE,
4291 [31] = SH_PFC_PIN_NONE,
4292 } },
4293 { PINMUX_BIAS_REG("PUEN8", 0xE60680C0, "PUD8", 0xE60680E0) {
4294 [ 0] = RCAR_GP_PIN(8, 0), /* SCL0 */
4295 [ 1] = RCAR_GP_PIN(8, 1), /* SDA0 */
4296 [ 2] = RCAR_GP_PIN(8, 2), /* SCL1 */
4297 [ 3] = RCAR_GP_PIN(8, 3), /* SDA1 */
4298 [ 4] = RCAR_GP_PIN(8, 4), /* SCL2 */
4299 [ 5] = RCAR_GP_PIN(8, 5), /* SDA2 */
4300 [ 6] = RCAR_GP_PIN(8, 6), /* SCL3 */
4301 [ 7] = RCAR_GP_PIN(8, 7), /* SDA3 */
4302 [ 8] = RCAR_GP_PIN(8, 8), /* SCL4 */
4303 [ 9] = RCAR_GP_PIN(8, 9), /* SDA4 */
4304 [10] = RCAR_GP_PIN(8, 10), /* SCL5 */
4305 [11] = RCAR_GP_PIN(8, 11), /* SDA5 */
4306 [12] = RCAR_GP_PIN(8, 12), /* GP8_12 */
4307 [13] = RCAR_GP_PIN(8, 13), /* GP8_13 */
4308 [14] = SH_PFC_PIN_NONE,
4309 [15] = SH_PFC_PIN_NONE,
4310 [16] = SH_PFC_PIN_NONE,
4311 [17] = SH_PFC_PIN_NONE,
4312 [18] = SH_PFC_PIN_NONE,
4313 [19] = SH_PFC_PIN_NONE,
4314 [20] = SH_PFC_PIN_NONE,
4315 [21] = SH_PFC_PIN_NONE,
4316 [22] = SH_PFC_PIN_NONE,
4317 [23] = SH_PFC_PIN_NONE,
4318 [24] = SH_PFC_PIN_NONE,
4319 [25] = SH_PFC_PIN_NONE,
4320 [26] = SH_PFC_PIN_NONE,
4321 [27] = SH_PFC_PIN_NONE,
4322 [28] = SH_PFC_PIN_NONE,
4323 [29] = SH_PFC_PIN_NONE,
4324 [30] = SH_PFC_PIN_NONE,
4325 [31] = SH_PFC_PIN_NONE,
4326 } },
4327 { /* sentinel */ }
4328 };
4329
4330 static const struct sh_pfc_soc_operations r8a779g0_pin_ops = {
4331 .pin_to_pocctrl = r8a779g0_pin_to_pocctrl,
4332 .get_bias = rcar_pinmux_get_bias,
4333 .set_bias = rcar_pinmux_set_bias,
4334 };
4335
4336 const struct sh_pfc_soc_info r8a779g0_pinmux_info = {
4337 .name = "r8a779g0_pfc",
4338 .ops = &r8a779g0_pin_ops,
4339 .unlock_reg = 0x1ff, /* PMMRn mask */
4340
4341 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
4342
4343 .pins = pinmux_pins,
4344 .nr_pins = ARRAY_SIZE(pinmux_pins),
4345 .groups = pinmux_groups,
4346 .nr_groups = ARRAY_SIZE(pinmux_groups),
4347 .functions = pinmux_functions,
4348 .nr_functions = ARRAY_SIZE(pinmux_functions),
4349
4350 .cfg_regs = pinmux_config_regs,
4351 .drive_regs = pinmux_drive_regs,
4352 .bias_regs = pinmux_bias_regs,
4353 .ioctrl_regs = pinmux_ioctrl_regs,
4354
4355 .pinmux_data = pinmux_data,
4356 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
4357 };
4358