1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * R8A779A0 processor support - PFC hardware block.
4  *
5  * Copyright (C) 2021 Renesas Electronics Corp.
6  *
7  * This file is based on the drivers/pinctrl/renesas/pfc-r8a779a0.c
8  */
9 
10 #include <linux/errno.h>
11 #include <linux/io.h>
12 #include <linux/kernel.h>
13 
14 #include "sh_pfc.h"
15 
16 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
17 
18 #define CPU_ALL_GP(fn, sfx)								\
19 	PORT_GP_CFG_19(0,	fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
20 	PORT_GP_CFG_23(1,	fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
21 	PORT_GP_CFG_1(1, 23,	fn, sfx, CFG_FLAGS),					\
22 	PORT_GP_CFG_1(1, 24,	fn, sfx, CFG_FLAGS),					\
23 	PORT_GP_CFG_1(1, 25,	fn, sfx, CFG_FLAGS),					\
24 	PORT_GP_CFG_1(1, 26,	fn, sfx, CFG_FLAGS),					\
25 	PORT_GP_CFG_1(1, 27,	fn, sfx, CFG_FLAGS),					\
26 	PORT_GP_CFG_1(1, 28,	fn, sfx, CFG_FLAGS),					\
27 	PORT_GP_CFG_20(2,	fn, sfx, CFG_FLAGS),					\
28 	PORT_GP_CFG_13(3,	fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
29 	PORT_GP_CFG_1(3, 13,	fn, sfx, CFG_FLAGS),					\
30 	PORT_GP_CFG_1(3, 14,	fn, sfx, CFG_FLAGS),					\
31 	PORT_GP_CFG_1(3, 15,	fn, sfx, CFG_FLAGS),					\
32 	PORT_GP_CFG_1(3, 16,	fn, sfx, CFG_FLAGS),					\
33 	PORT_GP_CFG_1(3, 17,	fn, sfx, CFG_FLAGS),					\
34 	PORT_GP_CFG_1(3, 18,	fn, sfx, CFG_FLAGS),					\
35 	PORT_GP_CFG_1(3, 19,	fn, sfx, CFG_FLAGS),					\
36 	PORT_GP_CFG_1(3, 20,	fn, sfx, CFG_FLAGS),					\
37 	PORT_GP_CFG_1(3, 21,	fn, sfx, CFG_FLAGS),					\
38 	PORT_GP_CFG_1(3, 22,	fn, sfx, CFG_FLAGS),					\
39 	PORT_GP_CFG_1(3, 23,	fn, sfx, CFG_FLAGS),					\
40 	PORT_GP_CFG_1(3, 24,	fn, sfx, CFG_FLAGS),					\
41 	PORT_GP_CFG_1(3, 25,	fn, sfx, CFG_FLAGS),					\
42 	PORT_GP_CFG_1(3, 26,	fn, sfx, CFG_FLAGS),					\
43 	PORT_GP_CFG_1(3, 27,	fn, sfx, CFG_FLAGS),					\
44 	PORT_GP_CFG_1(3, 28,	fn, sfx, CFG_FLAGS),					\
45 	PORT_GP_CFG_1(3, 29,	fn, sfx, CFG_FLAGS),					\
46 	PORT_GP_CFG_25(4,	fn, sfx, CFG_FLAGS),					\
47 	PORT_GP_CFG_21(5,	fn, sfx, CFG_FLAGS),					\
48 	PORT_GP_CFG_21(6,	fn, sfx, CFG_FLAGS),					\
49 	PORT_GP_CFG_21(7,	fn, sfx, CFG_FLAGS),					\
50 	PORT_GP_CFG_14(8,	fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33)
51 
52 #define CPU_ALL_NOGP(fn)								\
53 	PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25),	\
54 	PIN_NOGP_CFG(VDDQ_AVB1, "VDDQ_AVB1", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25),	\
55 	PIN_NOGP_CFG(VDDQ_AVB2, "VDDQ_AVB2", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25),	\
56 	PIN_NOGP_CFG(VDDQ_TSN0, "VDDQ_TSN0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25)
57 
58 /* GPSR0 */
59 #define GPSR0_18	F_(MSIOF2_RXD,		IP2SR0_11_8)
60 #define GPSR0_17	F_(MSIOF2_SCK,		IP2SR0_7_4)
61 #define GPSR0_16	F_(MSIOF2_TXD,		IP2SR0_3_0)
62 #define GPSR0_15	F_(MSIOF2_SYNC,		IP1SR0_31_28)
63 #define GPSR0_14	F_(MSIOF2_SS1,		IP1SR0_27_24)
64 #define GPSR0_13	F_(MSIOF2_SS2,		IP1SR0_23_20)
65 #define GPSR0_12	F_(MSIOF5_RXD,		IP1SR0_19_16)
66 #define GPSR0_11	F_(MSIOF5_SCK,		IP1SR0_15_12)
67 #define GPSR0_10	F_(MSIOF5_TXD,		IP1SR0_11_8)
68 #define GPSR0_9		F_(MSIOF5_SYNC,		IP1SR0_7_4)
69 #define GPSR0_8		F_(MSIOF5_SS1,		IP1SR0_3_0)
70 #define GPSR0_7		F_(MSIOF5_SS2,		IP0SR0_31_28)
71 #define GPSR0_6		F_(IRQ0,		IP0SR0_27_24)
72 #define GPSR0_5		F_(IRQ1,		IP0SR0_23_20)
73 #define GPSR0_4		F_(IRQ2,		IP0SR0_19_16)
74 #define GPSR0_3		F_(IRQ3,		IP0SR0_15_12)
75 #define GPSR0_2		F_(GP0_02,		IP0SR0_11_8)
76 #define GPSR0_1		F_(GP0_01,		IP0SR0_7_4)
77 #define GPSR0_0		F_(GP0_00,		IP0SR0_3_0)
78 
79 /* GPSR1 */
80 #define GPSR1_28	F_(HTX3,		IP3SR1_19_16)
81 #define GPSR1_27	F_(HCTS3_N,		IP3SR1_15_12)
82 #define GPSR1_26	F_(HRTS3_N,		IP3SR1_11_8)
83 #define GPSR1_25	F_(HSCK3,		IP3SR1_7_4)
84 #define GPSR1_24	F_(HRX3,		IP3SR1_3_0)
85 #define GPSR1_23	F_(GP1_23,		IP2SR1_31_28)
86 #define GPSR1_22	F_(AUDIO_CLKIN,		IP2SR1_27_24)
87 #define GPSR1_21	F_(AUDIO_CLKOUT,	IP2SR1_23_20)
88 #define GPSR1_20	F_(SSI_SD,		IP2SR1_19_16)
89 #define GPSR1_19	F_(SSI_WS,		IP2SR1_15_12)
90 #define GPSR1_18	F_(SSI_SCK,		IP2SR1_11_8)
91 #define GPSR1_17	F_(SCIF_CLK,		IP2SR1_7_4)
92 #define GPSR1_16	F_(HRX0,		IP2SR1_3_0)
93 #define GPSR1_15	F_(HSCK0,		IP1SR1_31_28)
94 #define GPSR1_14	F_(HRTS0_N,		IP1SR1_27_24)
95 #define GPSR1_13	F_(HCTS0_N,		IP1SR1_23_20)
96 #define GPSR1_12	F_(HTX0,		IP1SR1_19_16)
97 #define GPSR1_11	F_(MSIOF0_RXD,		IP1SR1_15_12)
98 #define GPSR1_10	F_(MSIOF0_SCK,		IP1SR1_11_8)
99 #define GPSR1_9		F_(MSIOF0_TXD,		IP1SR1_7_4)
100 #define GPSR1_8		F_(MSIOF0_SYNC,		IP1SR1_3_0)
101 #define GPSR1_7		F_(MSIOF0_SS1,		IP0SR1_31_28)
102 #define GPSR1_6		F_(MSIOF0_SS2,		IP0SR1_27_24)
103 #define GPSR1_5		F_(MSIOF1_RXD,		IP0SR1_23_20)
104 #define GPSR1_4		F_(MSIOF1_TXD,		IP0SR1_19_16)
105 #define GPSR1_3		F_(MSIOF1_SCK,		IP0SR1_15_12)
106 #define GPSR1_2		F_(MSIOF1_SYNC,		IP0SR1_11_8)
107 #define GPSR1_1		F_(MSIOF1_SS1,		IP0SR1_7_4)
108 #define GPSR1_0		F_(MSIOF1_SS2,		IP0SR1_3_0)
109 
110 /* GPSR2 */
111 #define GPSR2_19	F_(CANFD7_RX,		IP2SR2_15_12)
112 #define GPSR2_18	F_(CANFD7_TX,		IP2SR2_11_8)
113 #define GPSR2_17	F_(CANFD4_RX,		IP2SR2_7_4)
114 #define GPSR2_16	F_(CANFD4_TX,		IP2SR2_3_0)
115 #define GPSR2_15	F_(CANFD3_RX,		IP1SR2_31_28)
116 #define GPSR2_14	F_(CANFD3_TX,		IP1SR2_27_24)
117 #define GPSR2_13	F_(CANFD2_RX,		IP1SR2_23_20)
118 #define GPSR2_12	F_(CANFD2_TX,		IP1SR2_19_16)
119 #define GPSR2_11	F_(CANFD0_RX,		IP1SR2_15_12)
120 #define GPSR2_10	F_(CANFD0_TX,		IP1SR2_11_8)
121 #define GPSR2_9		F_(CAN_CLK,		IP1SR2_7_4)
122 #define GPSR2_8		F_(TPU0TO0,		IP1SR2_3_0)
123 #define GPSR2_7		F_(TPU0TO1,		IP0SR2_31_28)
124 #define GPSR2_6		F_(FXR_TXDB,		IP0SR2_27_24)
125 #define GPSR2_5		F_(FXR_TXENB_N,		IP0SR2_23_20)
126 #define GPSR2_4		F_(RXDB_EXTFXR,		IP0SR2_19_16)
127 #define GPSR2_3		F_(CLK_EXTFXR,		IP0SR2_15_12)
128 #define GPSR2_2		F_(RXDA_EXTFXR,		IP0SR2_11_8)
129 #define GPSR2_1		F_(FXR_TXENA_N,		IP0SR2_7_4)
130 #define GPSR2_0		F_(FXR_TXDA,		IP0SR2_3_0)
131 
132 /* GPSR3 */
133 #define GPSR3_29	F_(RPC_INT_N,		IP3SR3_23_20)
134 #define GPSR3_28	F_(RPC_WP_N,		IP3SR3_19_16)
135 #define GPSR3_27	F_(RPC_RESET_N,		IP3SR3_15_12)
136 #define GPSR3_26	F_(QSPI1_IO3,		IP3SR3_11_8)
137 #define GPSR3_25	F_(QSPI1_SSL,		IP3SR3_7_4)
138 #define GPSR3_24	F_(QSPI1_IO2,		IP3SR3_3_0)
139 #define GPSR3_23	F_(QSPI1_MISO_IO1,	IP2SR3_31_28)
140 #define GPSR3_22	F_(QSPI1_SPCLK,		IP2SR3_27_24)
141 #define GPSR3_21	F_(QSPI1_MOSI_IO0,	IP2SR3_23_20)
142 #define GPSR3_20	F_(QSPI0_SPCLK,		IP2SR3_19_16)
143 #define GPSR3_19	F_(QSPI0_MOSI_IO0,	IP2SR3_15_12)
144 #define GPSR3_18	F_(QSPI0_MISO_IO1,	IP2SR3_11_8)
145 #define GPSR3_17	F_(QSPI0_IO2,		IP2SR3_7_4)
146 #define GPSR3_16	F_(QSPI0_IO3,		IP2SR3_3_0)
147 #define GPSR3_15	F_(QSPI0_SSL,		IP1SR3_31_28)
148 #define GPSR3_14	F_(IPC_CLKOUT,		IP1SR3_27_24)
149 #define GPSR3_13	F_(IPC_CLKIN,		IP1SR3_23_20)
150 #define GPSR3_12	F_(SD_WP,		IP1SR3_19_16)
151 #define GPSR3_11	F_(SD_CD,		IP1SR3_15_12)
152 #define GPSR3_10	F_(MMC_SD_CMD,		IP1SR3_11_8)
153 #define GPSR3_9		F_(MMC_D6,		IP1SR3_7_4)
154 #define GPSR3_8		F_(MMC_D7,		IP1SR3_3_0)
155 #define GPSR3_7		F_(MMC_D4,		IP0SR3_31_28)
156 #define GPSR3_6		F_(MMC_D5,		IP0SR3_27_24)
157 #define GPSR3_5		F_(MMC_SD_D3,		IP0SR3_23_20)
158 #define GPSR3_4		F_(MMC_DS,		IP0SR3_19_16)
159 #define GPSR3_3		F_(MMC_SD_CLK,		IP0SR3_15_12)
160 #define GPSR3_2		F_(MMC_SD_D2,		IP0SR3_11_8)
161 #define GPSR3_1		F_(MMC_SD_D0,		IP0SR3_7_4)
162 #define GPSR3_0		F_(MMC_SD_D1,		IP0SR3_3_0)
163 
164 /* GPSR4 */
165 #define GPSR4_24	F_(AVS1,		IP3SR4_3_0)
166 #define GPSR4_23	F_(AVS0,		IP2SR4_31_28)
167 #define GPSR4_22	F_(PCIE1_CLKREQ_N,	IP2SR4_27_24)
168 #define GPSR4_21	F_(PCIE0_CLKREQ_N,	IP2SR4_23_20)
169 #define GPSR4_20	F_(TSN0_TXCREFCLK,	IP2SR4_19_16)
170 #define GPSR4_19	F_(TSN0_TD2,		IP2SR4_15_12)
171 #define GPSR4_18	F_(TSN0_TD3,		IP2SR4_11_8)
172 #define GPSR4_17	F_(TSN0_RD2,		IP2SR4_7_4)
173 #define GPSR4_16	F_(TSN0_RD3,		IP2SR4_3_0)
174 #define GPSR4_15	F_(TSN0_TD0,		IP1SR4_31_28)
175 #define GPSR4_14	F_(TSN0_TD1,		IP1SR4_27_24)
176 #define GPSR4_13	F_(TSN0_RD1,		IP1SR4_23_20)
177 #define GPSR4_12	F_(TSN0_TXC,		IP1SR4_19_16)
178 #define GPSR4_11	F_(TSN0_RXC,		IP1SR4_15_12)
179 #define GPSR4_10	F_(TSN0_RD0,		IP1SR4_11_8)
180 #define GPSR4_9		F_(TSN0_TX_CTL,		IP1SR4_7_4)
181 #define GPSR4_8		F_(TSN0_AVTP_PPS0,	IP1SR4_3_0)
182 #define GPSR4_7		F_(TSN0_RX_CTL,		IP0SR4_31_28)
183 #define GPSR4_6		F_(TSN0_AVTP_CAPTURE,	IP0SR4_27_24)
184 #define GPSR4_5		F_(TSN0_AVTP_MATCH,	IP0SR4_23_20)
185 #define GPSR4_4		F_(TSN0_LINK,		IP0SR4_19_16)
186 #define GPSR4_3		F_(TSN0_PHY_INT,	IP0SR4_15_12)
187 #define GPSR4_2		F_(TSN0_AVTP_PPS1,	IP0SR4_11_8)
188 #define GPSR4_1		F_(TSN0_MDC,		IP0SR4_7_4)
189 #define GPSR4_0		F_(TSN0_MDIO,		IP0SR4_3_0)
190 
191 /* GPSR 5 */
192 #define GPSR5_20	F_(AVB2_RX_CTL,		IP2SR5_19_16)
193 #define GPSR5_19	F_(AVB2_TX_CTL,		IP2SR5_15_12)
194 #define GPSR5_18	F_(AVB2_RXC,		IP2SR5_11_8)
195 #define GPSR5_17	F_(AVB2_RD0,		IP2SR5_7_4)
196 #define GPSR5_16	F_(AVB2_TXC,		IP2SR5_3_0)
197 #define GPSR5_15	F_(AVB2_TD0,		IP1SR5_31_28)
198 #define GPSR5_14	F_(AVB2_RD1,		IP1SR5_27_24)
199 #define GPSR5_13	F_(AVB2_RD2,		IP1SR5_23_20)
200 #define GPSR5_12	F_(AVB2_TD1,		IP1SR5_19_16)
201 #define GPSR5_11	F_(AVB2_TD2,		IP1SR5_15_12)
202 #define GPSR5_10	F_(AVB2_MDIO,		IP1SR5_11_8)
203 #define GPSR5_9		F_(AVB2_RD3,		IP1SR5_7_4)
204 #define GPSR5_8		F_(AVB2_TD3,		IP1SR5_3_0)
205 #define GPSR5_7		F_(AVB2_TXCREFCLK,	IP0SR5_31_28)
206 #define GPSR5_6		F_(AVB2_MDC,		IP0SR5_27_24)
207 #define GPSR5_5		F_(AVB2_MAGIC,		IP0SR5_23_20)
208 #define GPSR5_4		F_(AVB2_PHY_INT,	IP0SR5_19_16)
209 #define GPSR5_3		F_(AVB2_LINK,		IP0SR5_15_12)
210 #define GPSR5_2		F_(AVB2_AVTP_MATCH,	IP0SR5_11_8)
211 #define GPSR5_1		F_(AVB2_AVTP_CAPTURE,	IP0SR5_7_4)
212 #define GPSR5_0		F_(AVB2_AVTP_PPS,	IP0SR5_3_0)
213 
214 /* GPSR 6 */
215 #define GPSR6_20	F_(AVB1_TXCREFCLK,	IP2SR6_19_16)
216 #define GPSR6_19	F_(AVB1_RD3,		IP2SR6_15_12)
217 #define GPSR6_18	F_(AVB1_TD3,		IP2SR6_11_8)
218 #define GPSR6_17	F_(AVB1_RD2,		IP2SR6_7_4)
219 #define GPSR6_16	F_(AVB1_TD2,		IP2SR6_3_0)
220 #define GPSR6_15	F_(AVB1_RD0,		IP1SR6_31_28)
221 #define GPSR6_14	F_(AVB1_RD1,		IP1SR6_27_24)
222 #define GPSR6_13	F_(AVB1_TD0,		IP1SR6_23_20)
223 #define GPSR6_12	F_(AVB1_TD1,		IP1SR6_19_16)
224 #define GPSR6_11	F_(AVB1_AVTP_CAPTURE,	IP1SR6_15_12)
225 #define GPSR6_10	F_(AVB1_AVTP_PPS,	IP1SR6_11_8)
226 #define GPSR6_9		F_(AVB1_RX_CTL,		IP1SR6_7_4)
227 #define GPSR6_8		F_(AVB1_RXC,		IP1SR6_3_0)
228 #define GPSR6_7		F_(AVB1_TX_CTL,		IP0SR6_31_28)
229 #define GPSR6_6		F_(AVB1_TXC,		IP0SR6_27_24)
230 #define GPSR6_5		F_(AVB1_AVTP_MATCH,	IP0SR6_23_20)
231 #define GPSR6_4		F_(AVB1_LINK,		IP0SR6_19_16)
232 #define GPSR6_3		F_(AVB1_PHY_INT,	IP0SR6_15_12)
233 #define GPSR6_2		F_(AVB1_MDC,		IP0SR6_11_8)
234 #define GPSR6_1		F_(AVB1_MAGIC,		IP0SR6_7_4)
235 #define GPSR6_0		F_(AVB1_MDIO,		IP0SR6_3_0)
236 
237 /* GPSR7 */
238 #define GPSR7_20	F_(AVB0_RX_CTL,		IP2SR7_19_16)
239 #define GPSR7_19	F_(AVB0_RXC,		IP2SR7_15_12)
240 #define GPSR7_18	F_(AVB0_RD0,		IP2SR7_11_8)
241 #define GPSR7_17	F_(AVB0_RD1,		IP2SR7_7_4)
242 #define GPSR7_16	F_(AVB0_TX_CTL,		IP2SR7_3_0)
243 #define GPSR7_15	F_(AVB0_TXC,		IP1SR7_31_28)
244 #define GPSR7_14	F_(AVB0_MDIO,		IP1SR7_27_24)
245 #define GPSR7_13	F_(AVB0_MDC,		IP1SR7_23_20)
246 #define GPSR7_12	F_(AVB0_RD2,		IP1SR7_19_16)
247 #define GPSR7_11	F_(AVB0_TD0,		IP1SR7_15_12)
248 #define GPSR7_10	F_(AVB0_MAGIC,		IP1SR7_11_8)
249 #define GPSR7_9		F_(AVB0_TXCREFCLK,	IP1SR7_7_4)
250 #define GPSR7_8		F_(AVB0_RD3,		IP1SR7_3_0)
251 #define GPSR7_7		F_(AVB0_TD1,		IP0SR7_31_28)
252 #define GPSR7_6		F_(AVB0_TD2,		IP0SR7_27_24)
253 #define GPSR7_5		F_(AVB0_PHY_INT,	IP0SR7_23_20)
254 #define GPSR7_4		F_(AVB0_LINK,		IP0SR7_19_16)
255 #define GPSR7_3		F_(AVB0_TD3,		IP0SR7_15_12)
256 #define GPSR7_2		F_(AVB0_AVTP_MATCH,	IP0SR7_11_8)
257 #define GPSR7_1		F_(AVB0_AVTP_CAPTURE,	IP0SR7_7_4)
258 #define GPSR7_0		F_(AVB0_AVTP_PPS,	IP0SR7_3_0)
259 
260 /* GPSR8 */
261 #define GPSR8_13	F_(GP8_13,		IP1SR8_23_20)
262 #define GPSR8_12	F_(GP8_12,		IP1SR8_19_16)
263 #define GPSR8_11	F_(SDA5,		IP1SR8_15_12)
264 #define GPSR8_10	F_(SCL5,		IP1SR8_11_8)
265 #define GPSR8_9		F_(SDA4,		IP1SR8_7_4)
266 #define GPSR8_8		F_(SCL4,		IP1SR8_3_0)
267 #define GPSR8_7		F_(SDA3,		IP0SR8_31_28)
268 #define GPSR8_6		F_(SCL3,		IP0SR8_27_24)
269 #define GPSR8_5		F_(SDA2,		IP0SR8_23_20)
270 #define GPSR8_4		F_(SCL2,		IP0SR8_19_16)
271 #define GPSR8_3		F_(SDA1,		IP0SR8_15_12)
272 #define GPSR8_2		F_(SCL1,		IP0SR8_11_8)
273 #define GPSR8_1		F_(SDA0,		IP0SR8_7_4)
274 #define GPSR8_0		F_(SCL0,		IP0SR8_3_0)
275 
276 /* SR0 */
277 /* IP0SR0 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
278 #define IP0SR0_3_0	F_(0, 0)		FM(ERROROUTC_N_B)	FM(TCLK2_A)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP0SR0_7_4	F_(0, 0)		FM(MSIOF3_SS1)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP0SR0_11_8	F_(0, 0)		FM(MSIOF3_SS2)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP0SR0_15_12	FM(IRQ3)		FM(MSIOF3_SCK)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP0SR0_19_16	FM(IRQ2)		FM(MSIOF3_TXD)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP0SR0_23_20	FM(IRQ1)		FM(MSIOF3_RXD)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP0SR0_27_24	FM(IRQ0)		FM(MSIOF3_SYNC)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP0SR0_31_28	FM(MSIOF5_SS2)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 
287 /* IP1SR0 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
288 #define IP1SR0_3_0	FM(MSIOF5_SS1)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP1SR0_7_4	FM(MSIOF5_SYNC)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP1SR0_11_8	FM(MSIOF5_TXD)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP1SR0_15_12	FM(MSIOF5_SCK)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP1SR0_19_16	FM(MSIOF5_RXD)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP1SR0_23_20	FM(MSIOF2_SS2)		FM(TCLK1)		FM(IRQ2_A)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP1SR0_27_24	FM(MSIOF2_SS1)		FM(HTX1)		FM(TX1)			F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP1SR0_31_28	FM(MSIOF2_SYNC)		FM(HRX1)		FM(RX1)			F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 
297 /* IP2SR0 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
298 #define IP2SR0_3_0	FM(MSIOF2_TXD)		FM(HCTS1_N)		FM(CTS1_N)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP2SR0_7_4	FM(MSIOF2_SCK)		FM(HRTS1_N)		FM(RTS1_N)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP2SR0_11_8	FM(MSIOF2_RXD)		FM(HSCK1)		FM(SCK1)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 
302 /* SR1 */
303 /* IP0SR1 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
304 #define IP0SR1_3_0	FM(MSIOF1_SS2)		FM(HTX3_A)		FM(TX3)			F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP0SR1_7_4	FM(MSIOF1_SS1)		FM(HCTS3_N_A)		FM(RX3)			F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP0SR1_11_8	FM(MSIOF1_SYNC)		FM(HRTS3_N_A)		FM(RTS3_N)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP0SR1_15_12	FM(MSIOF1_SCK)		FM(HSCK3_A)		FM(CTS3_N)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP0SR1_19_16	FM(MSIOF1_TXD)		FM(HRX3_A)		FM(SCK3)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP0SR1_23_20	FM(MSIOF1_RXD)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP0SR1_27_24	FM(MSIOF0_SS2)		FM(HTX1_X)		FM(TX1_X)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP0SR1_31_28	FM(MSIOF0_SS1)		FM(HRX1_X)		FM(RX1_X)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 
313 /* IP1SR1 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
314 #define IP1SR1_3_0	FM(MSIOF0_SYNC)		FM(HCTS1_N_X)		FM(CTS1_N_X)		FM(CANFD5_TX_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP1SR1_7_4	FM(MSIOF0_TXD)		FM(HRTS1_N_X)		FM(RTS1_N_X)		FM(CANFD5_RX_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316 #define IP1SR1_11_8	FM(MSIOF0_SCK)		FM(HSCK1_X)		FM(SCK1_X)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317 #define IP1SR1_15_12	FM(MSIOF0_RXD)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318 #define IP1SR1_19_16	FM(HTX0)		FM(TX0)			F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319 #define IP1SR1_23_20	FM(HCTS0_N)		FM(CTS0_N)		FM(PWM8_A)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP1SR1_27_24	FM(HRTS0_N)		FM(RTS0_N)		FM(PWM9_A)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP1SR1_31_28	FM(HSCK0)		FM(SCK0)		FM(PWM0_A)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 
323 /* IP2SR1 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
324 #define IP2SR1_3_0	FM(HRX0)		FM(RX0)			F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP2SR1_7_4	FM(SCIF_CLK)		FM(IRQ4_A)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP2SR1_11_8	FM(SSI_SCK)		FM(TCLK3)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP2SR1_15_12	FM(SSI_WS)		FM(TCLK4)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP2SR1_19_16	FM(SSI_SD)		FM(IRQ0_A)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP2SR1_23_20	FM(AUDIO_CLKOUT)	FM(IRQ1_A)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP2SR1_27_24	FM(AUDIO_CLKIN)		FM(PWM3_A)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP2SR1_31_28	F_(0, 0)		FM(TCLK2)		FM(MSIOF4_SS1)		FM(IRQ3_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 
333 /* IP3SR1 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
334 #define IP3SR1_3_0	FM(HRX3)		FM(SCK3_A)		FM(MSIOF4_SS2)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 #define IP3SR1_7_4	FM(HSCK3)		FM(CTS3_N_A)		FM(MSIOF4_SCK)		FM(TPU0TO0_A)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336 #define IP3SR1_11_8	FM(HRTS3_N)		FM(RTS3_N_A)		FM(MSIOF4_TXD)		FM(TPU0TO1_A)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337 #define IP3SR1_15_12	FM(HCTS3_N)		FM(RX3_A)		FM(MSIOF4_RXD)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 #define IP3SR1_19_16	FM(HTX3)		FM(TX3_A)		FM(MSIOF4_SYNC)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339 
340 /* SR2 */
341 /* IP0SR2 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
342 #define IP0SR2_3_0	FM(FXR_TXDA)		FM(CANFD1_TX)		FM(TPU0TO2_A)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 #define IP0SR2_7_4	FM(FXR_TXENA_N)		FM(CANFD1_RX)		FM(TPU0TO3_A)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 #define IP0SR2_11_8	FM(RXDA_EXTFXR)		FM(CANFD5_TX)		FM(IRQ5)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 #define IP0SR2_15_12	FM(CLK_EXTFXR)		FM(CANFD5_RX)		FM(IRQ4_B)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP0SR2_19_16	FM(RXDB_EXTFXR)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP0SR2_23_20	FM(FXR_TXENB_N)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 #define IP0SR2_27_24	FM(FXR_TXDB)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349 #define IP0SR2_31_28	FM(TPU0TO1)		FM(CANFD6_TX)		F_(0, 0)		FM(TCLK2_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350 
351 /* IP1SR2 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
352 #define IP1SR2_3_0	FM(TPU0TO0)		FM(CANFD6_RX)		F_(0, 0)		FM(TCLK1_A)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353 #define IP1SR2_7_4	FM(CAN_CLK)		FM(FXR_TXENA_N_X)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354 #define IP1SR2_11_8	FM(CANFD0_TX)		FM(FXR_TXENB_N_X)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355 #define IP1SR2_15_12	FM(CANFD0_RX)		FM(STPWT_EXTFXR)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356 #define IP1SR2_19_16	FM(CANFD2_TX)		FM(TPU0TO2)		F_(0, 0)		FM(TCLK3_A)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357 #define IP1SR2_23_20	FM(CANFD2_RX)		FM(TPU0TO3)		FM(PWM1_B)		FM(TCLK4_A)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358 #define IP1SR2_27_24	FM(CANFD3_TX)		F_(0, 0)		FM(PWM2_B)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359 #define IP1SR2_31_28	FM(CANFD3_RX)		F_(0, 0)		FM(PWM3_B)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360 
361 /* IP2SR2 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
362 #define IP2SR2_3_0	FM(CANFD4_TX)		F_(0, 0)		FM(PWM4)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363 #define IP2SR2_7_4	FM(CANFD4_RX)		F_(0, 0)		FM(PWM5)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364 #define IP2SR2_11_8	FM(CANFD7_TX)		F_(0, 0)		FM(PWM6)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
365 #define IP2SR2_15_12	FM(CANFD7_RX)		F_(0, 0)		FM(PWM7)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
366 
367 /* SR3 */
368 /* IP0SR3 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
369 #define IP0SR3_3_0	FM(MMC_SD_D1)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370 #define IP0SR3_7_4	FM(MMC_SD_D0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
371 #define IP0SR3_11_8	FM(MMC_SD_D2)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
372 #define IP0SR3_15_12	FM(MMC_SD_CLK)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
373 #define IP0SR3_19_16	FM(MMC_DS)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
374 #define IP0SR3_23_20	FM(MMC_SD_D3)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
375 #define IP0SR3_27_24	FM(MMC_D5)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
376 #define IP0SR3_31_28	FM(MMC_D4)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
377 
378 /* IP1SR3 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
379 #define IP1SR3_3_0	FM(MMC_D7)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
380 #define IP1SR3_7_4	FM(MMC_D6)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
381 #define IP1SR3_11_8	FM(MMC_SD_CMD)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
382 #define IP1SR3_15_12	FM(SD_CD)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
383 #define IP1SR3_19_16	FM(SD_WP)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
384 #define IP1SR3_23_20	FM(IPC_CLKIN)		FM(IPC_CLKEN_IN)	FM(PWM1_A)		FM(TCLK3_X)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
385 #define IP1SR3_27_24	FM(IPC_CLKOUT)		FM(IPC_CLKEN_OUT)	FM(ERROROUTC_N_A)	FM(TCLK4_X)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
386 #define IP1SR3_31_28	FM(QSPI0_SSL)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
387 
388 /* IP2SR3 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
389 #define IP2SR3_3_0	FM(QSPI0_IO3)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
390 #define IP2SR3_7_4	FM(QSPI0_IO2)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
391 #define IP2SR3_11_8	FM(QSPI0_MISO_IO1)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
392 #define IP2SR3_15_12	FM(QSPI0_MOSI_IO0)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
393 #define IP2SR3_19_16	FM(QSPI0_SPCLK)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
394 #define IP2SR3_23_20	FM(QSPI1_MOSI_IO0)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
395 #define IP2SR3_27_24	FM(QSPI1_SPCLK)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
396 #define IP2SR3_31_28	FM(QSPI1_MISO_IO1)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
397 
398 /* IP3SR3 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
399 #define IP3SR3_3_0	FM(QSPI1_IO2)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
400 #define IP3SR3_7_4	FM(QSPI1_SSL)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
401 #define IP3SR3_11_8	FM(QSPI1_IO3)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
402 #define IP3SR3_15_12	FM(RPC_RESET_N)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
403 #define IP3SR3_19_16	FM(RPC_WP_N)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
404 #define IP3SR3_23_20	FM(RPC_INT_N)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
405 
406 /* SR4 */
407 /* IP0SR4 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
408 #define IP0SR4_3_0	FM(TSN0_MDIO)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
409 #define IP0SR4_7_4	FM(TSN0_MDC)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
410 #define IP0SR4_11_8	FM(TSN0_AVTP_PPS1)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
411 #define IP0SR4_15_12	FM(TSN0_PHY_INT)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
412 #define IP0SR4_19_16	FM(TSN0_LINK)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
413 #define IP0SR4_23_20	FM(TSN0_AVTP_MATCH)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
414 #define IP0SR4_27_24	FM(TSN0_AVTP_CAPTURE)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
415 #define IP0SR4_31_28	FM(TSN0_RX_CTL)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
416 
417 /* IP1SR4 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
418 #define IP1SR4_3_0	FM(TSN0_AVTP_PPS0)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
419 #define IP1SR4_7_4	FM(TSN0_TX_CTL)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
420 #define IP1SR4_11_8	FM(TSN0_RD0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
421 #define IP1SR4_15_12	FM(TSN0_RXC)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
422 #define IP1SR4_19_16	FM(TSN0_TXC)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
423 #define IP1SR4_23_20	FM(TSN0_RD1)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
424 #define IP1SR4_27_24	FM(TSN0_TD1)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
425 #define IP1SR4_31_28	FM(TSN0_TD0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
426 
427 /* IP2SR4 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
428 #define IP2SR4_3_0	FM(TSN0_RD3)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
429 #define IP2SR4_7_4	FM(TSN0_RD2)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
430 #define IP2SR4_11_8	FM(TSN0_TD3)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
431 #define IP2SR4_15_12	FM(TSN0_TD2)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
432 #define IP2SR4_19_16	FM(TSN0_TXCREFCLK)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
433 #define IP2SR4_23_20	FM(PCIE0_CLKREQ_N)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
434 #define IP2SR4_27_24	FM(PCIE1_CLKREQ_N)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
435 #define IP2SR4_31_28	FM(AVS0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
436 
437 /* IP3SR4 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
438 #define IP3SR4_3_0	FM(AVS1)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
439 
440 /* SR5 */
441 /* IP0SR5 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
442 #define IP0SR5_3_0	FM(AVB2_AVTP_PPS)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
443 #define IP0SR5_7_4	FM(AVB2_AVTP_CAPTURE)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
444 #define IP0SR5_11_8	FM(AVB2_AVTP_MATCH)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
445 #define IP0SR5_15_12	FM(AVB2_LINK)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
446 #define IP0SR5_19_16	FM(AVB2_PHY_INT)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
447 #define IP0SR5_23_20	FM(AVB2_MAGIC)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
448 #define IP0SR5_27_24	FM(AVB2_MDC)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
449 #define IP0SR5_31_28	FM(AVB2_TXCREFCLK)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
450 
451 /* IP1SR5 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
452 #define IP1SR5_3_0	FM(AVB2_TD3)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
453 #define IP1SR5_7_4	FM(AVB2_RD3)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
454 #define IP1SR5_11_8	FM(AVB2_MDIO)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
455 #define IP1SR5_15_12	FM(AVB2_TD2)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
456 #define IP1SR5_19_16	FM(AVB2_TD1)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
457 #define IP1SR5_23_20	FM(AVB2_RD2)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
458 #define IP1SR5_27_24	FM(AVB2_RD1)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
459 #define IP1SR5_31_28	FM(AVB2_TD0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
460 
461 /* IP2SR5 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
462 #define IP2SR5_3_0	FM(AVB2_TXC)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
463 #define IP2SR5_7_4	FM(AVB2_RD0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
464 #define IP2SR5_11_8	FM(AVB2_RXC)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
465 #define IP2SR5_15_12	FM(AVB2_TX_CTL)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
466 #define IP2SR5_19_16	FM(AVB2_RX_CTL)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
467 
468 /* SR6 */
469 /* IP0SR6 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
470 #define IP0SR6_3_0	FM(AVB1_MDIO)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
471 #define IP0SR6_7_4	FM(AVB1_MAGIC)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
472 #define IP0SR6_11_8	FM(AVB1_MDC)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
473 #define IP0SR6_15_12	FM(AVB1_PHY_INT)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
474 #define IP0SR6_19_16	FM(AVB1_LINK)		FM(AVB1_MII_TX_ER)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
475 #define IP0SR6_23_20	FM(AVB1_AVTP_MATCH)	FM(AVB1_MII_RX_ER)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
476 #define IP0SR6_27_24	FM(AVB1_TXC)		FM(AVB1_MII_TXC)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
477 #define IP0SR6_31_28	FM(AVB1_TX_CTL)		FM(AVB1_MII_TX_EN)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
478 
479 /* IP1SR6 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
480 #define IP1SR6_3_0	FM(AVB1_RXC)		FM(AVB1_MII_RXC)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
481 #define IP1SR6_7_4	FM(AVB1_RX_CTL)		FM(AVB1_MII_RX_DV)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
482 #define IP1SR6_11_8	FM(AVB1_AVTP_PPS)	FM(AVB1_MII_COL)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
483 #define IP1SR6_15_12	FM(AVB1_AVTP_CAPTURE)	FM(AVB1_MII_CRS)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
484 #define IP1SR6_19_16	FM(AVB1_TD1)		FM(AVB1_MII_TD1)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
485 #define IP1SR6_23_20	FM(AVB1_TD0)		FM(AVB1_MII_TD0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
486 #define IP1SR6_27_24	FM(AVB1_RD1)		FM(AVB1_MII_RD1)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
487 #define IP1SR6_31_28	FM(AVB1_RD0)		FM(AVB1_MII_RD0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
488 
489 /* IP2SR6 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
490 #define IP2SR6_3_0	FM(AVB1_TD2)		FM(AVB1_MII_TD2)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
491 #define IP2SR6_7_4	FM(AVB1_RD2)		FM(AVB1_MII_RD2)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
492 #define IP2SR6_11_8	FM(AVB1_TD3)		FM(AVB1_MII_TD3)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
493 #define IP2SR6_15_12	FM(AVB1_RD3)		FM(AVB1_MII_RD3)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
494 #define IP2SR6_19_16	FM(AVB1_TXCREFCLK)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
495 
496 /* SR7 */
497 /* IP0SR7 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
498 #define IP0SR7_3_0	FM(AVB0_AVTP_PPS)	FM(AVB0_MII_COL)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
499 #define IP0SR7_7_4	FM(AVB0_AVTP_CAPTURE)	FM(AVB0_MII_CRS)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
500 #define IP0SR7_11_8	FM(AVB0_AVTP_MATCH)	FM(AVB0_MII_RX_ER)	FM(CC5_OSCOUT)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
501 #define IP0SR7_15_12	FM(AVB0_TD3)		FM(AVB0_MII_TD3)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
502 #define IP0SR7_19_16	FM(AVB0_LINK)		FM(AVB0_MII_TX_ER)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
503 #define IP0SR7_23_20	FM(AVB0_PHY_INT)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
504 #define IP0SR7_27_24	FM(AVB0_TD2)		FM(AVB0_MII_TD2)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
505 #define IP0SR7_31_28	FM(AVB0_TD1)		FM(AVB0_MII_TD1)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
506 
507 /* IP1SR7 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
508 #define IP1SR7_3_0	FM(AVB0_RD3)		FM(AVB0_MII_RD3)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
509 #define IP1SR7_7_4	FM(AVB0_TXCREFCLK)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
510 #define IP1SR7_11_8	FM(AVB0_MAGIC)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
511 #define IP1SR7_15_12	FM(AVB0_TD0)		FM(AVB0_MII_TD0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
512 #define IP1SR7_19_16	FM(AVB0_RD2)		FM(AVB0_MII_RD2)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
513 #define IP1SR7_23_20	FM(AVB0_MDC)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
514 #define IP1SR7_27_24	FM(AVB0_MDIO)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
515 #define IP1SR7_31_28	FM(AVB0_TXC)		FM(AVB0_MII_TXC)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
516 
517 /* IP2SR7 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
518 #define IP2SR7_3_0	FM(AVB0_TX_CTL)		FM(AVB0_MII_TX_EN)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
519 #define IP2SR7_7_4	FM(AVB0_RD1)		FM(AVB0_MII_RD1)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
520 #define IP2SR7_11_8	FM(AVB0_RD0)		FM(AVB0_MII_RD0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
521 #define IP2SR7_15_12	FM(AVB0_RXC)		FM(AVB0_MII_RXC)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
522 #define IP2SR7_19_16	FM(AVB0_RX_CTL)		FM(AVB0_MII_RX_DV)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
523 
524 /* SR8 */
525 /* IP0SR8 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
526 #define IP0SR8_3_0	FM(SCL0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
527 #define IP0SR8_7_4	FM(SDA0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
528 #define IP0SR8_11_8	FM(SCL1)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
529 #define IP0SR8_15_12	FM(SDA1)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
530 #define IP0SR8_19_16	FM(SCL2)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
531 #define IP0SR8_23_20	FM(SDA2)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
532 #define IP0SR8_27_24	FM(SCL3)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
533 #define IP0SR8_31_28	FM(SDA3)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
534 
535 /* IP1SR8 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
536 #define IP1SR8_3_0	FM(SCL4)		FM(HRX2)		FM(SCK4)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
537 #define IP1SR8_7_4	FM(SDA4)		FM(HTX2)		FM(CTS4_N)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
538 #define IP1SR8_11_8	FM(SCL5)		FM(HRTS2_N)		FM(RTS4_N)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
539 #define IP1SR8_15_12	FM(SDA5)		FM(SCIF_CLK2)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
540 #define IP1SR8_19_16	F_(0, 0)		FM(HCTS2_N)		FM(TX4)			F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
541 #define IP1SR8_23_20	F_(0, 0)		FM(HSCK2)		FM(RX4)			F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
542 
543 #define PINMUX_GPSR	\
544 						GPSR3_29											\
545 		GPSR1_28			GPSR3_28											\
546 		GPSR1_27			GPSR3_27											\
547 		GPSR1_26			GPSR3_26											\
548 		GPSR1_25			GPSR3_25											\
549 		GPSR1_24			GPSR3_24	GPSR4_24									\
550 		GPSR1_23			GPSR3_23	GPSR4_23									\
551 		GPSR1_22			GPSR3_22	GPSR4_22									\
552 		GPSR1_21			GPSR3_21	GPSR4_21									\
553 		GPSR1_20			GPSR3_20	GPSR4_20	GPSR5_20	GPSR6_20	GPSR7_20			\
554 		GPSR1_19	GPSR2_19	GPSR3_19	GPSR4_19	GPSR5_19	GPSR6_19	GPSR7_19			\
555 GPSR0_18	GPSR1_18	GPSR2_18	GPSR3_18	GPSR4_18	GPSR5_18	GPSR6_18	GPSR7_18			\
556 GPSR0_17	GPSR1_17	GPSR2_17	GPSR3_17	GPSR4_17	GPSR5_17	GPSR6_17	GPSR7_17			\
557 GPSR0_16	GPSR1_16	GPSR2_16	GPSR3_16	GPSR4_16	GPSR5_16	GPSR6_16	GPSR7_16			\
558 GPSR0_15	GPSR1_15	GPSR2_15	GPSR3_15	GPSR4_15	GPSR5_15	GPSR6_15	GPSR7_15			\
559 GPSR0_14	GPSR1_14	GPSR2_14	GPSR3_14	GPSR4_14	GPSR5_14	GPSR6_14	GPSR7_14			\
560 GPSR0_13	GPSR1_13	GPSR2_13	GPSR3_13	GPSR4_13	GPSR5_13	GPSR6_13	GPSR7_13	GPSR8_13	\
561 GPSR0_12	GPSR1_12	GPSR2_12	GPSR3_12	GPSR4_12	GPSR5_12	GPSR6_12	GPSR7_12	GPSR8_12	\
562 GPSR0_11	GPSR1_11	GPSR2_11	GPSR3_11	GPSR4_11	GPSR5_11	GPSR6_11	GPSR7_11	GPSR8_11	\
563 GPSR0_10	GPSR1_10	GPSR2_10	GPSR3_10	GPSR4_10	GPSR5_10	GPSR6_10	GPSR7_10	GPSR8_10	\
564 GPSR0_9		GPSR1_9		GPSR2_9		GPSR3_9		GPSR4_9		GPSR5_9		GPSR6_9		GPSR7_9		GPSR8_9		\
565 GPSR0_8		GPSR1_8		GPSR2_8		GPSR3_8		GPSR4_8		GPSR5_8		GPSR6_8		GPSR7_8		GPSR8_8		\
566 GPSR0_7		GPSR1_7		GPSR2_7		GPSR3_7		GPSR4_7		GPSR5_7		GPSR6_7		GPSR7_7		GPSR8_7		\
567 GPSR0_6		GPSR1_6		GPSR2_6		GPSR3_6		GPSR4_6		GPSR5_6		GPSR6_6		GPSR7_6		GPSR8_6		\
568 GPSR0_5		GPSR1_5		GPSR2_5		GPSR3_5		GPSR4_5		GPSR5_5		GPSR6_5		GPSR7_5		GPSR8_5		\
569 GPSR0_4		GPSR1_4		GPSR2_4		GPSR3_4		GPSR4_4		GPSR5_4		GPSR6_4		GPSR7_4		GPSR8_4		\
570 GPSR0_3		GPSR1_3		GPSR2_3		GPSR3_3		GPSR4_3		GPSR5_3		GPSR6_3		GPSR7_3		GPSR8_3		\
571 GPSR0_2		GPSR1_2		GPSR2_2		GPSR3_2		GPSR4_2		GPSR5_2		GPSR6_2		GPSR7_2		GPSR8_2		\
572 GPSR0_1		GPSR1_1		GPSR2_1		GPSR3_1		GPSR4_1		GPSR5_1		GPSR6_1		GPSR7_1		GPSR8_1		\
573 GPSR0_0		GPSR1_0		GPSR2_0		GPSR3_0		GPSR4_0		GPSR5_0		GPSR6_0		GPSR7_0		GPSR8_0
574 
575 #define PINMUX_IPSR	\
576 \
577 FM(IP0SR0_3_0)		IP0SR0_3_0	FM(IP1SR0_3_0)		IP1SR0_3_0	FM(IP2SR0_3_0)		IP2SR0_3_0	\
578 FM(IP0SR0_7_4)		IP0SR0_7_4	FM(IP1SR0_7_4)		IP1SR0_7_4	FM(IP2SR0_7_4)		IP2SR0_7_4	\
579 FM(IP0SR0_11_8)		IP0SR0_11_8	FM(IP1SR0_11_8)		IP1SR0_11_8	FM(IP2SR0_11_8)		IP2SR0_11_8	\
580 FM(IP0SR0_15_12)	IP0SR0_15_12	FM(IP1SR0_15_12)	IP1SR0_15_12	\
581 FM(IP0SR0_19_16)	IP0SR0_19_16	FM(IP1SR0_19_16)	IP1SR0_19_16	\
582 FM(IP0SR0_23_20)	IP0SR0_23_20	FM(IP1SR0_23_20)	IP1SR0_23_20	\
583 FM(IP0SR0_27_24)	IP0SR0_27_24	FM(IP1SR0_27_24)	IP1SR0_27_24	\
584 FM(IP0SR0_31_28)	IP0SR0_31_28	FM(IP1SR0_31_28)	IP1SR0_31_28	\
585 \
586 FM(IP0SR1_3_0)		IP0SR1_3_0	FM(IP1SR1_3_0)		IP1SR1_3_0	FM(IP2SR1_3_0)		IP2SR1_3_0	FM(IP3SR1_3_0)		IP3SR1_3_0	\
587 FM(IP0SR1_7_4)		IP0SR1_7_4	FM(IP1SR1_7_4)		IP1SR1_7_4	FM(IP2SR1_7_4)		IP2SR1_7_4	FM(IP3SR1_7_4)		IP3SR1_7_4	\
588 FM(IP0SR1_11_8)		IP0SR1_11_8	FM(IP1SR1_11_8)		IP1SR1_11_8	FM(IP2SR1_11_8)		IP2SR1_11_8	FM(IP3SR1_11_8)		IP3SR1_11_8	\
589 FM(IP0SR1_15_12)	IP0SR1_15_12	FM(IP1SR1_15_12)	IP1SR1_15_12	FM(IP2SR1_15_12)	IP2SR1_15_12	FM(IP3SR1_15_12)	IP3SR1_15_12	\
590 FM(IP0SR1_19_16)	IP0SR1_19_16	FM(IP1SR1_19_16)	IP1SR1_19_16	FM(IP2SR1_19_16)	IP2SR1_19_16	FM(IP3SR1_19_16)	IP3SR1_19_16	\
591 FM(IP0SR1_23_20)	IP0SR1_23_20	FM(IP1SR1_23_20)	IP1SR1_23_20	FM(IP2SR1_23_20)	IP2SR1_23_20	\
592 FM(IP0SR1_27_24)	IP0SR1_27_24	FM(IP1SR1_27_24)	IP1SR1_27_24	FM(IP2SR1_27_24)	IP2SR1_27_24	\
593 FM(IP0SR1_31_28)	IP0SR1_31_28	FM(IP1SR1_31_28)	IP1SR1_31_28	FM(IP2SR1_31_28)	IP2SR1_31_28	\
594 \
595 FM(IP0SR2_3_0)		IP0SR2_3_0	FM(IP1SR2_3_0)		IP1SR2_3_0	FM(IP2SR2_3_0)		IP2SR2_3_0	\
596 FM(IP0SR2_7_4)		IP0SR2_7_4	FM(IP1SR2_7_4)		IP1SR2_7_4	FM(IP2SR2_7_4)		IP2SR2_7_4	\
597 FM(IP0SR2_11_8)		IP0SR2_11_8	FM(IP1SR2_11_8)		IP1SR2_11_8	FM(IP2SR2_11_8)		IP2SR2_11_8	\
598 FM(IP0SR2_15_12)	IP0SR2_15_12	FM(IP1SR2_15_12)	IP1SR2_15_12	FM(IP2SR2_15_12)	IP2SR2_15_12	\
599 FM(IP0SR2_19_16)	IP0SR2_19_16	FM(IP1SR2_19_16)	IP1SR2_19_16	\
600 FM(IP0SR2_23_20)	IP0SR2_23_20	FM(IP1SR2_23_20)	IP1SR2_23_20	\
601 FM(IP0SR2_27_24)	IP0SR2_27_24	FM(IP1SR2_27_24)	IP1SR2_27_24	\
602 FM(IP0SR2_31_28)	IP0SR2_31_28	FM(IP1SR2_31_28)	IP1SR2_31_28	\
603 \
604 FM(IP0SR3_3_0)		IP0SR3_3_0	FM(IP1SR3_3_0)		IP1SR3_3_0	FM(IP2SR3_3_0)		IP2SR3_3_0	FM(IP3SR3_3_0)		IP3SR3_3_0	\
605 FM(IP0SR3_7_4)		IP0SR3_7_4	FM(IP1SR3_7_4)		IP1SR3_7_4	FM(IP2SR3_7_4)		IP2SR3_7_4	FM(IP3SR3_7_4)		IP3SR3_7_4	\
606 FM(IP0SR3_11_8)		IP0SR3_11_8	FM(IP1SR3_11_8)		IP1SR3_11_8	FM(IP2SR3_11_8)		IP2SR3_11_8	FM(IP3SR3_11_8)		IP3SR3_11_8	\
607 FM(IP0SR3_15_12)	IP0SR3_15_12	FM(IP1SR3_15_12)	IP1SR3_15_12	FM(IP2SR3_15_12)	IP2SR3_15_12	FM(IP3SR3_15_12)	IP3SR3_15_12	\
608 FM(IP0SR3_19_16)	IP0SR3_19_16	FM(IP1SR3_19_16)	IP1SR3_19_16	FM(IP2SR3_19_16)	IP2SR3_19_16	FM(IP3SR3_19_16)	IP3SR3_19_16	\
609 FM(IP0SR3_23_20)	IP0SR3_23_20	FM(IP1SR3_23_20)	IP1SR3_23_20	FM(IP2SR3_23_20)	IP2SR3_23_20	FM(IP3SR3_23_20)	IP3SR3_23_20	\
610 FM(IP0SR3_27_24)	IP0SR3_27_24	FM(IP1SR3_27_24)	IP1SR3_27_24	FM(IP2SR3_27_24)	IP2SR3_27_24						\
611 FM(IP0SR3_31_28)	IP0SR3_31_28	FM(IP1SR3_31_28)	IP1SR3_31_28	FM(IP2SR3_31_28)	IP2SR3_31_28						\
612 \
613 FM(IP0SR4_3_0)		IP0SR4_3_0	FM(IP1SR4_3_0)		IP1SR4_3_0	FM(IP2SR4_3_0)		IP2SR4_3_0	FM(IP3SR4_3_0)		IP3SR4_3_0	\
614 FM(IP0SR4_7_4)		IP0SR4_7_4	FM(IP1SR4_7_4)		IP1SR4_7_4	FM(IP2SR4_7_4)		IP2SR4_7_4	\
615 FM(IP0SR4_11_8)		IP0SR4_11_8	FM(IP1SR4_11_8)		IP1SR4_11_8	FM(IP2SR4_11_8)		IP2SR4_11_8	\
616 FM(IP0SR4_15_12)	IP0SR4_15_12	FM(IP1SR4_15_12)	IP1SR4_15_12	FM(IP2SR4_15_12)	IP2SR4_15_12	\
617 FM(IP0SR4_19_16)	IP0SR4_19_16	FM(IP1SR4_19_16)	IP1SR4_19_16	FM(IP2SR4_19_16)	IP2SR4_19_16	\
618 FM(IP0SR4_23_20)	IP0SR4_23_20	FM(IP1SR4_23_20)	IP1SR4_23_20	FM(IP2SR4_23_20)	IP2SR4_23_20	\
619 FM(IP0SR4_27_24)	IP0SR4_27_24	FM(IP1SR4_27_24)	IP1SR4_27_24	FM(IP2SR4_27_24)	IP2SR4_27_24	\
620 FM(IP0SR4_31_28)	IP0SR4_31_28	FM(IP1SR4_31_28)	IP1SR4_31_28	FM(IP2SR4_31_28)	IP2SR4_31_28	\
621 \
622 FM(IP0SR5_3_0)		IP0SR5_3_0	FM(IP1SR5_3_0)		IP1SR5_3_0	FM(IP2SR5_3_0)		IP2SR5_3_0	\
623 FM(IP0SR5_7_4)		IP0SR5_7_4	FM(IP1SR5_7_4)		IP1SR5_7_4	FM(IP2SR5_7_4)		IP2SR5_7_4	\
624 FM(IP0SR5_11_8)		IP0SR5_11_8	FM(IP1SR5_11_8)		IP1SR5_11_8	FM(IP2SR5_11_8)		IP2SR5_11_8	\
625 FM(IP0SR5_15_12)	IP0SR5_15_12	FM(IP1SR5_15_12)	IP1SR5_15_12	FM(IP2SR5_15_12)	IP2SR5_15_12	\
626 FM(IP0SR5_19_16)	IP0SR5_19_16	FM(IP1SR5_19_16)	IP1SR5_19_16	FM(IP2SR5_19_16)	IP2SR5_19_16	\
627 FM(IP0SR5_23_20)	IP0SR5_23_20	FM(IP1SR5_23_20)	IP1SR5_23_20	\
628 FM(IP0SR5_27_24)	IP0SR5_27_24	FM(IP1SR5_27_24)	IP1SR5_27_24	\
629 FM(IP0SR5_31_28)	IP0SR5_31_28	FM(IP1SR5_31_28)	IP1SR5_31_28	\
630 \
631 FM(IP0SR6_3_0)		IP0SR6_3_0	FM(IP1SR6_3_0)		IP1SR6_3_0	FM(IP2SR6_3_0)		IP2SR6_3_0	\
632 FM(IP0SR6_7_4)		IP0SR6_7_4	FM(IP1SR6_7_4)		IP1SR6_7_4	FM(IP2SR6_7_4)		IP2SR6_7_4	\
633 FM(IP0SR6_11_8)		IP0SR6_11_8	FM(IP1SR6_11_8)		IP1SR6_11_8	FM(IP2SR6_11_8)		IP2SR6_11_8	\
634 FM(IP0SR6_15_12)	IP0SR6_15_12	FM(IP1SR6_15_12)	IP1SR6_15_12	FM(IP2SR6_15_12)	IP2SR6_15_12	\
635 FM(IP0SR6_19_16)	IP0SR6_19_16	FM(IP1SR6_19_16)	IP1SR6_19_16	FM(IP2SR6_19_16)	IP2SR6_19_16	\
636 FM(IP0SR6_23_20)	IP0SR6_23_20	FM(IP1SR6_23_20)	IP1SR6_23_20	\
637 FM(IP0SR6_27_24)	IP0SR6_27_24	FM(IP1SR6_27_24)	IP1SR6_27_24	\
638 FM(IP0SR6_31_28)	IP0SR6_31_28	FM(IP1SR6_31_28)	IP1SR6_31_28	\
639 \
640 FM(IP0SR7_3_0)		IP0SR7_3_0	FM(IP1SR7_3_0)		IP1SR7_3_0	FM(IP2SR7_3_0)		IP2SR7_3_0	\
641 FM(IP0SR7_7_4)		IP0SR7_7_4	FM(IP1SR7_7_4)		IP1SR7_7_4	FM(IP2SR7_7_4)		IP2SR7_7_4	\
642 FM(IP0SR7_11_8)		IP0SR7_11_8	FM(IP1SR7_11_8)		IP1SR7_11_8	FM(IP2SR7_11_8)		IP2SR7_11_8	\
643 FM(IP0SR7_15_12)	IP0SR7_15_12	FM(IP1SR7_15_12)	IP1SR7_15_12	FM(IP2SR7_15_12)	IP2SR7_15_12	\
644 FM(IP0SR7_19_16)	IP0SR7_19_16	FM(IP1SR7_19_16)	IP1SR7_19_16	FM(IP2SR7_19_16)	IP2SR7_19_16	\
645 FM(IP0SR7_23_20)	IP0SR7_23_20	FM(IP1SR7_23_20)	IP1SR7_23_20	\
646 FM(IP0SR7_27_24)	IP0SR7_27_24	FM(IP1SR7_27_24)	IP1SR7_27_24	\
647 FM(IP0SR7_31_28)	IP0SR7_31_28	FM(IP1SR7_31_28)	IP1SR7_31_28	\
648 \
649 FM(IP0SR8_3_0)		IP0SR8_3_0	FM(IP1SR8_3_0)		IP1SR8_3_0	\
650 FM(IP0SR8_7_4)		IP0SR8_7_4	FM(IP1SR8_7_4)		IP1SR8_7_4	\
651 FM(IP0SR8_11_8)		IP0SR8_11_8	FM(IP1SR8_11_8)		IP1SR8_11_8	\
652 FM(IP0SR8_15_12)	IP0SR8_15_12	FM(IP1SR8_15_12)	IP1SR8_15_12	\
653 FM(IP0SR8_19_16)	IP0SR8_19_16	FM(IP1SR8_19_16)	IP1SR8_19_16	\
654 FM(IP0SR8_23_20)	IP0SR8_23_20	FM(IP1SR8_23_20)	IP1SR8_23_20	\
655 FM(IP0SR8_27_24)	IP0SR8_27_24	\
656 FM(IP0SR8_31_28)	IP0SR8_31_28
657 
658 /* MOD_SEL8 */			/* 0 */				/* 1 */
659 #define MOD_SEL8_11		FM(SEL_SDA5_0)			FM(SEL_SDA5_1)
660 #define MOD_SEL8_10		FM(SEL_SCL5_0)			FM(SEL_SCL5_1)
661 #define MOD_SEL8_9		FM(SEL_SDA4_0)			FM(SEL_SDA4_1)
662 #define MOD_SEL8_8		FM(SEL_SCL4_0)			FM(SEL_SCL4_1)
663 #define MOD_SEL8_7		FM(SEL_SDA3_0)			FM(SEL_SDA3_1)
664 #define MOD_SEL8_6		FM(SEL_SCL3_0)			FM(SEL_SCL3_1)
665 #define MOD_SEL8_5		FM(SEL_SDA2_0)			FM(SEL_SDA2_1)
666 #define MOD_SEL8_4		FM(SEL_SCL2_0)			FM(SEL_SCL2_1)
667 #define MOD_SEL8_3		FM(SEL_SDA1_0)			FM(SEL_SDA1_1)
668 #define MOD_SEL8_2		FM(SEL_SCL1_0)			FM(SEL_SCL1_1)
669 #define MOD_SEL8_1		FM(SEL_SDA0_0)			FM(SEL_SDA0_1)
670 #define MOD_SEL8_0		FM(SEL_SCL0_0)			FM(SEL_SCL0_1)
671 
672 #define PINMUX_MOD_SELS \
673 \
674 MOD_SEL8_11	\
675 MOD_SEL8_10	\
676 MOD_SEL8_9	\
677 MOD_SEL8_8	\
678 MOD_SEL8_7	\
679 MOD_SEL8_6	\
680 MOD_SEL8_5	\
681 MOD_SEL8_4	\
682 MOD_SEL8_3	\
683 MOD_SEL8_2	\
684 MOD_SEL8_1	\
685 MOD_SEL8_0
686 
687 enum {
688 	PINMUX_RESERVED = 0,
689 
690 	PINMUX_DATA_BEGIN,
691 	GP_ALL(DATA),
692 	PINMUX_DATA_END,
693 
694 #define F_(x, y)
695 #define FM(x)   FN_##x,
696 	PINMUX_FUNCTION_BEGIN,
697 	GP_ALL(FN),
698 	PINMUX_GPSR
699 	PINMUX_IPSR
700 	PINMUX_MOD_SELS
701 	PINMUX_FUNCTION_END,
702 #undef F_
703 #undef FM
704 
705 #define F_(x, y)
706 #define FM(x)	x##_MARK,
707 	PINMUX_MARK_BEGIN,
708 	PINMUX_GPSR
709 	PINMUX_IPSR
710 	PINMUX_MOD_SELS
711 	PINMUX_MARK_END,
712 #undef F_
713 #undef FM
714 };
715 
716 static const u16 pinmux_data[] = {
717 	PINMUX_DATA_GP_ALL(),
718 
719 	/* IP0SR0 */
720 	PINMUX_IPSR_GPSR(IP0SR0_3_0,	ERROROUTC_N_B),
721 	PINMUX_IPSR_GPSR(IP0SR0_3_0,	TCLK2_A),
722 
723 	PINMUX_IPSR_GPSR(IP0SR0_7_4,	MSIOF3_SS1),
724 
725 	PINMUX_IPSR_GPSR(IP0SR0_11_8,	MSIOF3_SS2),
726 
727 	PINMUX_IPSR_GPSR(IP0SR0_15_12,	IRQ3),
728 	PINMUX_IPSR_GPSR(IP0SR0_15_12,	MSIOF3_SCK),
729 
730 	PINMUX_IPSR_GPSR(IP0SR0_19_16,	IRQ2),
731 	PINMUX_IPSR_GPSR(IP0SR0_19_16,	MSIOF3_TXD),
732 
733 	PINMUX_IPSR_GPSR(IP0SR0_23_20,	IRQ1),
734 	PINMUX_IPSR_GPSR(IP0SR0_23_20,	MSIOF3_RXD),
735 
736 	PINMUX_IPSR_GPSR(IP0SR0_27_24,	IRQ0),
737 	PINMUX_IPSR_GPSR(IP0SR0_27_24,	MSIOF3_SYNC),
738 
739 	PINMUX_IPSR_GPSR(IP0SR0_31_28,	MSIOF5_SS2),
740 
741 	/* IP1SR0 */
742 	PINMUX_IPSR_GPSR(IP1SR0_3_0,	MSIOF5_SS1),
743 
744 	PINMUX_IPSR_GPSR(IP1SR0_7_4,	MSIOF5_SYNC),
745 
746 	PINMUX_IPSR_GPSR(IP1SR0_11_8,	MSIOF5_TXD),
747 
748 	PINMUX_IPSR_GPSR(IP1SR0_15_12,	MSIOF5_SCK),
749 
750 	PINMUX_IPSR_GPSR(IP1SR0_19_16,	MSIOF5_RXD),
751 
752 	PINMUX_IPSR_GPSR(IP1SR0_23_20,	MSIOF2_SS2),
753 	PINMUX_IPSR_GPSR(IP1SR0_23_20,	TCLK1),
754 	PINMUX_IPSR_GPSR(IP1SR0_23_20,	IRQ2_A),
755 
756 	PINMUX_IPSR_GPSR(IP1SR0_27_24,	MSIOF2_SS1),
757 	PINMUX_IPSR_GPSR(IP1SR0_27_24,	HTX1),
758 	PINMUX_IPSR_GPSR(IP1SR0_27_24,	TX1),
759 
760 	PINMUX_IPSR_GPSR(IP1SR0_31_28,	MSIOF2_SYNC),
761 	PINMUX_IPSR_GPSR(IP1SR0_31_28,	HRX1),
762 	PINMUX_IPSR_GPSR(IP1SR0_31_28,	RX1),
763 
764 	/* IP2SR0 */
765 	PINMUX_IPSR_GPSR(IP2SR0_3_0,	MSIOF2_TXD),
766 	PINMUX_IPSR_GPSR(IP2SR0_3_0,	HCTS1_N),
767 	PINMUX_IPSR_GPSR(IP2SR0_3_0,	CTS1_N),
768 
769 	PINMUX_IPSR_GPSR(IP2SR0_7_4,	MSIOF2_SCK),
770 	PINMUX_IPSR_GPSR(IP2SR0_7_4,	HRTS1_N),
771 	PINMUX_IPSR_GPSR(IP2SR0_7_4,	RTS1_N),
772 
773 	PINMUX_IPSR_GPSR(IP2SR0_11_8,	MSIOF2_RXD),
774 	PINMUX_IPSR_GPSR(IP2SR0_11_8,	HSCK1),
775 	PINMUX_IPSR_GPSR(IP2SR0_11_8,	SCK1),
776 
777 	/* IP0SR1 */
778 	PINMUX_IPSR_GPSR(IP0SR1_3_0,	MSIOF1_SS2),
779 	PINMUX_IPSR_GPSR(IP0SR1_3_0,	HTX3_A),
780 	PINMUX_IPSR_GPSR(IP0SR1_3_0,	TX3),
781 
782 	PINMUX_IPSR_GPSR(IP0SR1_7_4,	MSIOF1_SS1),
783 	PINMUX_IPSR_GPSR(IP0SR1_7_4,	HCTS3_N_A),
784 	PINMUX_IPSR_GPSR(IP0SR1_7_4,	RX3),
785 
786 	PINMUX_IPSR_GPSR(IP0SR1_11_8,	MSIOF1_SYNC),
787 	PINMUX_IPSR_GPSR(IP0SR1_11_8,	HRTS3_N_A),
788 	PINMUX_IPSR_GPSR(IP0SR1_11_8,	RTS3_N),
789 
790 	PINMUX_IPSR_GPSR(IP0SR1_15_12,	MSIOF1_SCK),
791 	PINMUX_IPSR_GPSR(IP0SR1_15_12,	HSCK3_A),
792 	PINMUX_IPSR_GPSR(IP0SR1_15_12,	CTS3_N),
793 
794 	PINMUX_IPSR_GPSR(IP0SR1_19_16,	MSIOF1_TXD),
795 	PINMUX_IPSR_GPSR(IP0SR1_19_16,	HRX3_A),
796 	PINMUX_IPSR_GPSR(IP0SR1_19_16,	SCK3),
797 
798 	PINMUX_IPSR_GPSR(IP0SR1_23_20,	MSIOF1_RXD),
799 
800 	PINMUX_IPSR_GPSR(IP0SR1_27_24,	MSIOF0_SS2),
801 	PINMUX_IPSR_GPSR(IP0SR1_27_24,	HTX1_X),
802 	PINMUX_IPSR_GPSR(IP0SR1_27_24,	TX1_X),
803 
804 	PINMUX_IPSR_GPSR(IP0SR1_31_28,	MSIOF0_SS1),
805 	PINMUX_IPSR_GPSR(IP0SR1_31_28,	HRX1_X),
806 	PINMUX_IPSR_GPSR(IP0SR1_31_28,	RX1_X),
807 
808 	/* IP1SR1 */
809 	PINMUX_IPSR_GPSR(IP1SR1_3_0,	MSIOF0_SYNC),
810 	PINMUX_IPSR_GPSR(IP1SR1_3_0,	HCTS1_N_X),
811 	PINMUX_IPSR_GPSR(IP1SR1_3_0,	CTS1_N_X),
812 	PINMUX_IPSR_GPSR(IP1SR1_3_0,	CANFD5_TX_B),
813 
814 	PINMUX_IPSR_GPSR(IP1SR1_7_4,	MSIOF0_TXD),
815 	PINMUX_IPSR_GPSR(IP1SR1_7_4,	HRTS1_N_X),
816 	PINMUX_IPSR_GPSR(IP1SR1_7_4,	RTS1_N_X),
817 	PINMUX_IPSR_GPSR(IP1SR1_7_4,	CANFD5_RX_B),
818 
819 	PINMUX_IPSR_GPSR(IP1SR1_11_8,	MSIOF0_SCK),
820 	PINMUX_IPSR_GPSR(IP1SR1_11_8,	HSCK1_X),
821 	PINMUX_IPSR_GPSR(IP1SR1_11_8,	SCK1_X),
822 
823 	PINMUX_IPSR_GPSR(IP1SR1_15_12,	MSIOF0_RXD),
824 
825 	PINMUX_IPSR_GPSR(IP1SR1_19_16,	HTX0),
826 	PINMUX_IPSR_GPSR(IP1SR1_19_16,	TX0),
827 
828 	PINMUX_IPSR_GPSR(IP1SR1_23_20,	HCTS0_N),
829 	PINMUX_IPSR_GPSR(IP1SR1_23_20,	CTS0_N),
830 	PINMUX_IPSR_GPSR(IP1SR1_23_20,	PWM8_A),
831 
832 	PINMUX_IPSR_GPSR(IP1SR1_27_24,	HRTS0_N),
833 	PINMUX_IPSR_GPSR(IP1SR1_27_24,	RTS0_N),
834 	PINMUX_IPSR_GPSR(IP1SR1_27_24,	PWM9_A),
835 
836 	PINMUX_IPSR_GPSR(IP1SR1_31_28,	HSCK0),
837 	PINMUX_IPSR_GPSR(IP1SR1_31_28,	SCK0),
838 	PINMUX_IPSR_GPSR(IP1SR1_31_28,	PWM0_A),
839 
840 	/* IP2SR1 */
841 	PINMUX_IPSR_GPSR(IP2SR1_3_0,	HRX0),
842 	PINMUX_IPSR_GPSR(IP2SR1_3_0,	RX0),
843 
844 	PINMUX_IPSR_GPSR(IP2SR1_7_4,	SCIF_CLK),
845 	PINMUX_IPSR_GPSR(IP2SR1_7_4,	IRQ4_A),
846 
847 	PINMUX_IPSR_GPSR(IP2SR1_11_8,	SSI_SCK),
848 	PINMUX_IPSR_GPSR(IP2SR1_11_8,	TCLK3),
849 
850 	PINMUX_IPSR_GPSR(IP2SR1_15_12,	SSI_WS),
851 	PINMUX_IPSR_GPSR(IP2SR1_15_12,	TCLK4),
852 
853 	PINMUX_IPSR_GPSR(IP2SR1_19_16,	SSI_SD),
854 	PINMUX_IPSR_GPSR(IP2SR1_19_16,	IRQ0_A),
855 
856 	PINMUX_IPSR_GPSR(IP2SR1_23_20,	AUDIO_CLKOUT),
857 	PINMUX_IPSR_GPSR(IP2SR1_23_20,	IRQ1_A),
858 
859 	PINMUX_IPSR_GPSR(IP2SR1_27_24,	AUDIO_CLKIN),
860 	PINMUX_IPSR_GPSR(IP2SR1_27_24,	PWM3_A),
861 
862 	PINMUX_IPSR_GPSR(IP2SR1_31_28,	TCLK2),
863 	PINMUX_IPSR_GPSR(IP2SR1_31_28,	MSIOF4_SS1),
864 	PINMUX_IPSR_GPSR(IP2SR1_31_28,	IRQ3_B),
865 
866 	/* IP3SR1 */
867 	PINMUX_IPSR_GPSR(IP3SR1_3_0,	HRX3),
868 	PINMUX_IPSR_GPSR(IP3SR1_3_0,	SCK3_A),
869 	PINMUX_IPSR_GPSR(IP3SR1_3_0,	MSIOF4_SS2),
870 
871 	PINMUX_IPSR_GPSR(IP3SR1_7_4,	HSCK3),
872 	PINMUX_IPSR_GPSR(IP3SR1_7_4,	CTS3_N_A),
873 	PINMUX_IPSR_GPSR(IP3SR1_7_4,	MSIOF4_SCK),
874 	PINMUX_IPSR_GPSR(IP3SR1_7_4,	TPU0TO0_A),
875 
876 	PINMUX_IPSR_GPSR(IP3SR1_11_8,	HRTS3_N),
877 	PINMUX_IPSR_GPSR(IP3SR1_11_8,	RTS3_N_A),
878 	PINMUX_IPSR_GPSR(IP3SR1_11_8,	MSIOF4_TXD),
879 	PINMUX_IPSR_GPSR(IP3SR1_11_8,	TPU0TO1_A),
880 
881 	PINMUX_IPSR_GPSR(IP3SR1_15_12,	HCTS3_N),
882 	PINMUX_IPSR_GPSR(IP3SR1_15_12,	RX3_A),
883 	PINMUX_IPSR_GPSR(IP3SR1_15_12,	MSIOF4_RXD),
884 
885 	PINMUX_IPSR_GPSR(IP3SR1_19_16,	HTX3),
886 	PINMUX_IPSR_GPSR(IP3SR1_19_16,	TX3_A),
887 	PINMUX_IPSR_GPSR(IP3SR1_19_16,	MSIOF4_SYNC),
888 
889 	/* IP0SR2 */
890 	PINMUX_IPSR_GPSR(IP0SR2_3_0,	FXR_TXDA),
891 	PINMUX_IPSR_GPSR(IP0SR2_3_0,	CANFD1_TX),
892 	PINMUX_IPSR_GPSR(IP0SR2_3_0,	TPU0TO2_A),
893 
894 	PINMUX_IPSR_GPSR(IP0SR2_7_4,	FXR_TXENA_N),
895 	PINMUX_IPSR_GPSR(IP0SR2_7_4,	CANFD1_RX),
896 	PINMUX_IPSR_GPSR(IP0SR2_7_4,	TPU0TO3_A),
897 
898 	PINMUX_IPSR_GPSR(IP0SR2_11_8,	RXDA_EXTFXR),
899 	PINMUX_IPSR_GPSR(IP0SR2_11_8,	CANFD5_TX),
900 	PINMUX_IPSR_GPSR(IP0SR2_11_8,	IRQ5),
901 
902 	PINMUX_IPSR_GPSR(IP0SR2_15_12,	CLK_EXTFXR),
903 	PINMUX_IPSR_GPSR(IP0SR2_15_12,	CANFD5_RX),
904 	PINMUX_IPSR_GPSR(IP0SR2_15_12,	IRQ4_B),
905 
906 	PINMUX_IPSR_GPSR(IP0SR2_19_16,	RXDB_EXTFXR),
907 
908 	PINMUX_IPSR_GPSR(IP0SR2_23_20,	FXR_TXENB_N),
909 
910 	PINMUX_IPSR_GPSR(IP0SR2_27_24,	FXR_TXDB),
911 
912 	PINMUX_IPSR_GPSR(IP0SR2_31_28,	TPU0TO1),
913 	PINMUX_IPSR_GPSR(IP0SR2_31_28,	CANFD6_TX),
914 	PINMUX_IPSR_GPSR(IP0SR2_31_28,	TCLK2_B),
915 
916 	/* IP1SR2 */
917 	PINMUX_IPSR_GPSR(IP1SR2_3_0,	TPU0TO0),
918 	PINMUX_IPSR_GPSR(IP1SR2_3_0,	CANFD6_RX),
919 	PINMUX_IPSR_GPSR(IP1SR2_3_0,	TCLK1_A),
920 
921 	PINMUX_IPSR_GPSR(IP1SR2_7_4,	CAN_CLK),
922 	PINMUX_IPSR_GPSR(IP1SR2_7_4,	FXR_TXENA_N_X),
923 
924 	PINMUX_IPSR_GPSR(IP1SR2_11_8,	CANFD0_TX),
925 	PINMUX_IPSR_GPSR(IP1SR2_11_8,	FXR_TXENB_N_X),
926 
927 	PINMUX_IPSR_GPSR(IP1SR2_15_12,	CANFD0_RX),
928 	PINMUX_IPSR_GPSR(IP1SR2_15_12,	STPWT_EXTFXR),
929 
930 	PINMUX_IPSR_GPSR(IP1SR2_19_16,	CANFD2_TX),
931 	PINMUX_IPSR_GPSR(IP1SR2_19_16,	TPU0TO2),
932 	PINMUX_IPSR_GPSR(IP1SR2_19_16,	TCLK3_A),
933 
934 	PINMUX_IPSR_GPSR(IP1SR2_23_20,	CANFD2_RX),
935 	PINMUX_IPSR_GPSR(IP1SR2_23_20,	TPU0TO3),
936 	PINMUX_IPSR_GPSR(IP1SR2_23_20,	PWM1_B),
937 	PINMUX_IPSR_GPSR(IP1SR2_23_20,	TCLK4_A),
938 
939 	PINMUX_IPSR_GPSR(IP1SR2_27_24,	CANFD3_TX),
940 	PINMUX_IPSR_GPSR(IP1SR2_27_24,	PWM2_B),
941 
942 	PINMUX_IPSR_GPSR(IP1SR2_31_28,	CANFD3_RX),
943 	PINMUX_IPSR_GPSR(IP1SR2_31_28,	PWM3_B),
944 
945 	/* IP2SR2 */
946 	PINMUX_IPSR_GPSR(IP2SR2_3_0,	CANFD4_TX),
947 	PINMUX_IPSR_GPSR(IP2SR2_3_0,	PWM4),
948 
949 	PINMUX_IPSR_GPSR(IP2SR2_7_4,	CANFD4_RX),
950 	PINMUX_IPSR_GPSR(IP2SR2_7_4,	PWM5),
951 
952 	PINMUX_IPSR_GPSR(IP2SR2_11_8,	CANFD7_TX),
953 	PINMUX_IPSR_GPSR(IP2SR2_11_8,	PWM6),
954 
955 	PINMUX_IPSR_GPSR(IP2SR2_15_12,	CANFD7_RX),
956 	PINMUX_IPSR_GPSR(IP2SR2_15_12,	PWM7),
957 
958 	/* IP0SR3 */
959 	PINMUX_IPSR_GPSR(IP0SR3_3_0,	MMC_SD_D1),
960 	PINMUX_IPSR_GPSR(IP0SR3_7_4,	MMC_SD_D0),
961 	PINMUX_IPSR_GPSR(IP0SR3_11_8,	MMC_SD_D2),
962 	PINMUX_IPSR_GPSR(IP0SR3_15_12,	MMC_SD_CLK),
963 	PINMUX_IPSR_GPSR(IP0SR3_19_16,	MMC_DS),
964 	PINMUX_IPSR_GPSR(IP0SR3_23_20,	MMC_SD_D3),
965 	PINMUX_IPSR_GPSR(IP0SR3_27_24,	MMC_D5),
966 	PINMUX_IPSR_GPSR(IP0SR3_31_28,	MMC_D4),
967 
968 	/* IP1SR3 */
969 	PINMUX_IPSR_GPSR(IP1SR3_3_0,	MMC_D7),
970 
971 	PINMUX_IPSR_GPSR(IP1SR3_7_4,	MMC_D6),
972 
973 	PINMUX_IPSR_GPSR(IP1SR3_11_8,	MMC_SD_CMD),
974 
975 	PINMUX_IPSR_GPSR(IP1SR3_15_12,	SD_CD),
976 
977 	PINMUX_IPSR_GPSR(IP1SR3_19_16,	SD_WP),
978 
979 	PINMUX_IPSR_GPSR(IP1SR3_23_20,	IPC_CLKIN),
980 	PINMUX_IPSR_GPSR(IP1SR3_23_20,	IPC_CLKEN_IN),
981 	PINMUX_IPSR_GPSR(IP1SR3_23_20,	PWM1_A),
982 	PINMUX_IPSR_GPSR(IP1SR3_23_20,	TCLK3_X),
983 
984 	PINMUX_IPSR_GPSR(IP1SR3_27_24,	IPC_CLKOUT),
985 	PINMUX_IPSR_GPSR(IP1SR3_27_24,	IPC_CLKEN_OUT),
986 	PINMUX_IPSR_GPSR(IP1SR3_27_24,	ERROROUTC_N_A),
987 	PINMUX_IPSR_GPSR(IP1SR3_27_24,	TCLK4_X),
988 
989 	PINMUX_IPSR_GPSR(IP1SR3_31_28,	QSPI0_SSL),
990 
991 	/* IP2SR3 */
992 	PINMUX_IPSR_GPSR(IP2SR3_3_0,	QSPI0_IO3),
993 	PINMUX_IPSR_GPSR(IP2SR3_7_4,	QSPI0_IO2),
994 	PINMUX_IPSR_GPSR(IP2SR3_11_8,	QSPI0_MISO_IO1),
995 	PINMUX_IPSR_GPSR(IP2SR3_15_12,	QSPI0_MOSI_IO0),
996 	PINMUX_IPSR_GPSR(IP2SR3_19_16,	QSPI0_SPCLK),
997 	PINMUX_IPSR_GPSR(IP2SR3_23_20,	QSPI1_MOSI_IO0),
998 	PINMUX_IPSR_GPSR(IP2SR3_27_24,	QSPI1_SPCLK),
999 	PINMUX_IPSR_GPSR(IP2SR3_31_28,	QSPI1_MISO_IO1),
1000 
1001 	/* IP3SR3 */
1002 	PINMUX_IPSR_GPSR(IP3SR3_3_0,	QSPI1_IO2),
1003 	PINMUX_IPSR_GPSR(IP3SR3_7_4,	QSPI1_SSL),
1004 	PINMUX_IPSR_GPSR(IP3SR3_11_8,	QSPI1_IO3),
1005 	PINMUX_IPSR_GPSR(IP3SR3_15_12,	RPC_RESET_N),
1006 	PINMUX_IPSR_GPSR(IP3SR3_19_16,	RPC_WP_N),
1007 	PINMUX_IPSR_GPSR(IP3SR3_23_20,	RPC_INT_N),
1008 
1009 	/* IP0SR4 */
1010 	PINMUX_IPSR_GPSR(IP0SR4_3_0,	TSN0_MDIO),
1011 	PINMUX_IPSR_GPSR(IP0SR4_7_4,	TSN0_MDC),
1012 	PINMUX_IPSR_GPSR(IP0SR4_11_8,	TSN0_AVTP_PPS1),
1013 	PINMUX_IPSR_GPSR(IP0SR4_15_12,	TSN0_PHY_INT),
1014 	PINMUX_IPSR_GPSR(IP0SR4_19_16,	TSN0_LINK),
1015 	PINMUX_IPSR_GPSR(IP0SR4_23_20,	TSN0_AVTP_MATCH),
1016 	PINMUX_IPSR_GPSR(IP0SR4_27_24,	TSN0_AVTP_CAPTURE),
1017 	PINMUX_IPSR_GPSR(IP0SR4_31_28,	TSN0_RX_CTL),
1018 
1019 	/* IP1SR4 */
1020 	PINMUX_IPSR_GPSR(IP1SR4_3_0,	TSN0_AVTP_PPS0),
1021 	PINMUX_IPSR_GPSR(IP1SR4_7_4,	TSN0_TX_CTL),
1022 	PINMUX_IPSR_GPSR(IP1SR4_11_8,	TSN0_RD0),
1023 	PINMUX_IPSR_GPSR(IP1SR4_15_12,	TSN0_RXC),
1024 	PINMUX_IPSR_GPSR(IP1SR4_19_16,	TSN0_TXC),
1025 	PINMUX_IPSR_GPSR(IP1SR4_23_20,	TSN0_RD1),
1026 	PINMUX_IPSR_GPSR(IP1SR4_27_24,	TSN0_TD1),
1027 	PINMUX_IPSR_GPSR(IP1SR4_31_28,	TSN0_TD0),
1028 
1029 	/* IP2SR4 */
1030 	PINMUX_IPSR_GPSR(IP2SR4_3_0,	TSN0_RD3),
1031 	PINMUX_IPSR_GPSR(IP2SR4_7_4,	TSN0_RD2),
1032 	PINMUX_IPSR_GPSR(IP2SR4_11_8,	TSN0_TD3),
1033 	PINMUX_IPSR_GPSR(IP2SR4_15_12,	TSN0_TD2),
1034 	PINMUX_IPSR_GPSR(IP2SR4_19_16,	TSN0_TXCREFCLK),
1035 	PINMUX_IPSR_GPSR(IP2SR4_23_20,	PCIE0_CLKREQ_N),
1036 	PINMUX_IPSR_GPSR(IP2SR4_27_24,	PCIE1_CLKREQ_N),
1037 	PINMUX_IPSR_GPSR(IP2SR4_31_28,	AVS0),
1038 
1039 	/* IP3SR4 */
1040 	PINMUX_IPSR_GPSR(IP3SR4_3_0,	AVS1),
1041 
1042 	/* IP0SR5 */
1043 	PINMUX_IPSR_GPSR(IP0SR5_3_0,	AVB2_AVTP_PPS),
1044 	PINMUX_IPSR_GPSR(IP0SR5_7_4,	AVB2_AVTP_CAPTURE),
1045 	PINMUX_IPSR_GPSR(IP0SR5_11_8,	AVB2_AVTP_MATCH),
1046 	PINMUX_IPSR_GPSR(IP0SR5_15_12,	AVB2_LINK),
1047 	PINMUX_IPSR_GPSR(IP0SR5_19_16,	AVB2_PHY_INT),
1048 	PINMUX_IPSR_GPSR(IP0SR5_23_20,	AVB2_MAGIC),
1049 	PINMUX_IPSR_GPSR(IP0SR5_27_24,	AVB2_MDC),
1050 	PINMUX_IPSR_GPSR(IP0SR5_31_28,	AVB2_TXCREFCLK),
1051 
1052 	/* IP1SR5 */
1053 	PINMUX_IPSR_GPSR(IP1SR5_3_0,	AVB2_TD3),
1054 	PINMUX_IPSR_GPSR(IP1SR5_7_4,	AVB2_RD3),
1055 	PINMUX_IPSR_GPSR(IP1SR5_11_8,	AVB2_MDIO),
1056 	PINMUX_IPSR_GPSR(IP1SR5_15_12,	AVB2_TD2),
1057 	PINMUX_IPSR_GPSR(IP1SR5_19_16,	AVB2_TD1),
1058 	PINMUX_IPSR_GPSR(IP1SR5_23_20,	AVB2_RD2),
1059 	PINMUX_IPSR_GPSR(IP1SR5_27_24,	AVB2_RD1),
1060 	PINMUX_IPSR_GPSR(IP1SR5_31_28,	AVB2_TD0),
1061 
1062 	/* IP2SR5 */
1063 	PINMUX_IPSR_GPSR(IP2SR5_3_0,	AVB2_TXC),
1064 	PINMUX_IPSR_GPSR(IP2SR5_7_4,	AVB2_RD0),
1065 	PINMUX_IPSR_GPSR(IP2SR5_11_8,	AVB2_RXC),
1066 	PINMUX_IPSR_GPSR(IP2SR5_15_12,	AVB2_TX_CTL),
1067 	PINMUX_IPSR_GPSR(IP2SR5_19_16,	AVB2_RX_CTL),
1068 
1069 	/* IP0SR6 */
1070 	PINMUX_IPSR_GPSR(IP0SR6_3_0,	AVB1_MDIO),
1071 
1072 	PINMUX_IPSR_GPSR(IP0SR6_7_4,	AVB1_MAGIC),
1073 
1074 	PINMUX_IPSR_GPSR(IP0SR6_11_8,	AVB1_MDC),
1075 
1076 	PINMUX_IPSR_GPSR(IP0SR6_15_12,	AVB1_PHY_INT),
1077 
1078 	PINMUX_IPSR_GPSR(IP0SR6_19_16,	AVB1_LINK),
1079 	PINMUX_IPSR_GPSR(IP0SR6_19_16,	AVB1_MII_TX_ER),
1080 
1081 	PINMUX_IPSR_GPSR(IP0SR6_23_20,	AVB1_AVTP_MATCH),
1082 	PINMUX_IPSR_GPSR(IP0SR6_23_20,	AVB1_MII_RX_ER),
1083 
1084 	PINMUX_IPSR_GPSR(IP0SR6_27_24,	AVB1_TXC),
1085 	PINMUX_IPSR_GPSR(IP0SR6_27_24,	AVB1_MII_TXC),
1086 
1087 	PINMUX_IPSR_GPSR(IP0SR6_31_28,	AVB1_TX_CTL),
1088 	PINMUX_IPSR_GPSR(IP0SR6_31_28,	AVB1_MII_TX_EN),
1089 
1090 	/* IP1SR6 */
1091 	PINMUX_IPSR_GPSR(IP1SR6_3_0,	AVB1_RXC),
1092 	PINMUX_IPSR_GPSR(IP1SR6_3_0,	AVB1_MII_RXC),
1093 
1094 	PINMUX_IPSR_GPSR(IP1SR6_7_4,	AVB1_RX_CTL),
1095 	PINMUX_IPSR_GPSR(IP1SR6_7_4,	AVB1_MII_RX_DV),
1096 
1097 	PINMUX_IPSR_GPSR(IP1SR6_11_8,	AVB1_AVTP_PPS),
1098 	PINMUX_IPSR_GPSR(IP1SR6_11_8,	AVB1_MII_COL),
1099 
1100 	PINMUX_IPSR_GPSR(IP1SR6_15_12,	AVB1_AVTP_CAPTURE),
1101 	PINMUX_IPSR_GPSR(IP1SR6_15_12,	AVB1_MII_CRS),
1102 
1103 	PINMUX_IPSR_GPSR(IP1SR6_19_16,	AVB1_TD1),
1104 	PINMUX_IPSR_GPSR(IP1SR6_19_16,	AVB1_MII_TD1),
1105 
1106 	PINMUX_IPSR_GPSR(IP1SR6_23_20,	AVB1_TD0),
1107 	PINMUX_IPSR_GPSR(IP1SR6_23_20,	AVB1_MII_TD0),
1108 
1109 	PINMUX_IPSR_GPSR(IP1SR6_27_24,	AVB1_RD1),
1110 	PINMUX_IPSR_GPSR(IP1SR6_27_24,	AVB1_MII_RD1),
1111 
1112 	PINMUX_IPSR_GPSR(IP1SR6_31_28,	AVB1_RD0),
1113 	PINMUX_IPSR_GPSR(IP1SR6_31_28,	AVB1_MII_RD0),
1114 
1115 	/* IP2SR6 */
1116 	PINMUX_IPSR_GPSR(IP2SR6_3_0,	AVB1_TD2),
1117 	PINMUX_IPSR_GPSR(IP2SR6_3_0,	AVB1_MII_TD2),
1118 
1119 	PINMUX_IPSR_GPSR(IP2SR6_7_4,	AVB1_RD2),
1120 	PINMUX_IPSR_GPSR(IP2SR6_7_4,	AVB1_MII_RD2),
1121 
1122 	PINMUX_IPSR_GPSR(IP2SR6_11_8,	AVB1_TD3),
1123 	PINMUX_IPSR_GPSR(IP2SR6_11_8,	AVB1_MII_TD3),
1124 
1125 	PINMUX_IPSR_GPSR(IP2SR6_15_12,	AVB1_RD3),
1126 	PINMUX_IPSR_GPSR(IP2SR6_15_12,	AVB1_MII_RD3),
1127 
1128 	PINMUX_IPSR_GPSR(IP2SR6_19_16,	AVB1_TXCREFCLK),
1129 
1130 	/* IP0SR7 */
1131 	PINMUX_IPSR_GPSR(IP0SR7_3_0,	AVB0_AVTP_PPS),
1132 	PINMUX_IPSR_GPSR(IP0SR7_3_0,	AVB0_MII_COL),
1133 
1134 	PINMUX_IPSR_GPSR(IP0SR7_7_4,	AVB0_AVTP_CAPTURE),
1135 	PINMUX_IPSR_GPSR(IP0SR7_7_4,	AVB0_MII_CRS),
1136 
1137 	PINMUX_IPSR_GPSR(IP0SR7_11_8,	AVB0_AVTP_MATCH),
1138 	PINMUX_IPSR_GPSR(IP0SR7_11_8,	AVB0_MII_RX_ER),
1139 	PINMUX_IPSR_GPSR(IP0SR7_11_8,	CC5_OSCOUT),
1140 
1141 	PINMUX_IPSR_GPSR(IP0SR7_15_12,	AVB0_TD3),
1142 	PINMUX_IPSR_GPSR(IP0SR7_15_12,	AVB0_MII_TD3),
1143 
1144 	PINMUX_IPSR_GPSR(IP0SR7_19_16,	AVB0_LINK),
1145 	PINMUX_IPSR_GPSR(IP0SR7_19_16,	AVB0_MII_TX_ER),
1146 
1147 	PINMUX_IPSR_GPSR(IP0SR7_23_20,	AVB0_PHY_INT),
1148 
1149 	PINMUX_IPSR_GPSR(IP0SR7_27_24,	AVB0_TD2),
1150 	PINMUX_IPSR_GPSR(IP0SR7_27_24,	AVB0_MII_TD2),
1151 
1152 	PINMUX_IPSR_GPSR(IP0SR7_31_28,	AVB0_TD1),
1153 	PINMUX_IPSR_GPSR(IP0SR7_31_28,	AVB0_MII_TD1),
1154 
1155 	/* IP1SR7 */
1156 	PINMUX_IPSR_GPSR(IP1SR7_3_0,	AVB0_RD3),
1157 	PINMUX_IPSR_GPSR(IP1SR7_3_0,	AVB0_MII_RD3),
1158 
1159 	PINMUX_IPSR_GPSR(IP1SR7_7_4,	AVB0_TXCREFCLK),
1160 
1161 	PINMUX_IPSR_GPSR(IP1SR7_11_8,	AVB0_MAGIC),
1162 
1163 	PINMUX_IPSR_GPSR(IP1SR7_15_12,	AVB0_TD0),
1164 	PINMUX_IPSR_GPSR(IP1SR7_15_12,	AVB0_MII_TD0),
1165 
1166 	PINMUX_IPSR_GPSR(IP1SR7_19_16,	AVB0_RD2),
1167 	PINMUX_IPSR_GPSR(IP1SR7_19_16,	AVB0_MII_RD2),
1168 
1169 	PINMUX_IPSR_GPSR(IP1SR7_23_20,	AVB0_MDC),
1170 
1171 	PINMUX_IPSR_GPSR(IP1SR7_27_24,	AVB0_MDIO),
1172 
1173 	PINMUX_IPSR_GPSR(IP1SR7_31_28,	AVB0_TXC),
1174 	PINMUX_IPSR_GPSR(IP1SR7_31_28,	AVB0_MII_TXC),
1175 
1176 	/* IP2SR7 */
1177 	PINMUX_IPSR_GPSR(IP2SR7_3_0,	AVB0_TX_CTL),
1178 	PINMUX_IPSR_GPSR(IP2SR7_3_0,	AVB0_MII_TX_EN),
1179 
1180 	PINMUX_IPSR_GPSR(IP2SR7_7_4,	AVB0_RD1),
1181 	PINMUX_IPSR_GPSR(IP2SR7_7_4,	AVB0_MII_RD1),
1182 
1183 	PINMUX_IPSR_GPSR(IP2SR7_11_8,	AVB0_RD0),
1184 	PINMUX_IPSR_GPSR(IP2SR7_11_8,	AVB0_MII_RD0),
1185 
1186 	PINMUX_IPSR_GPSR(IP2SR7_15_12,	AVB0_RXC),
1187 	PINMUX_IPSR_GPSR(IP2SR7_15_12,	AVB0_MII_RXC),
1188 
1189 	PINMUX_IPSR_GPSR(IP2SR7_19_16,	AVB0_RX_CTL),
1190 	PINMUX_IPSR_GPSR(IP2SR7_19_16,	AVB0_MII_RX_DV),
1191 
1192 	/* IP0SR8 */
1193 	PINMUX_IPSR_MSEL(IP0SR8_3_0,	SCL0,			SEL_SCL0_0),
1194 	PINMUX_IPSR_MSEL(IP0SR8_7_4,	SDA0,			SEL_SDA0_0),
1195 	PINMUX_IPSR_MSEL(IP0SR8_11_8,	SCL1,			SEL_SCL1_0),
1196 	PINMUX_IPSR_MSEL(IP0SR8_15_12,	SDA1,			SEL_SDA1_0),
1197 	PINMUX_IPSR_MSEL(IP0SR8_19_16,	SCL2,			SEL_SCL2_0),
1198 	PINMUX_IPSR_MSEL(IP0SR8_23_20,	SDA2,			SEL_SDA2_0),
1199 	PINMUX_IPSR_MSEL(IP0SR8_27_24,	SCL3,			SEL_SCL3_0),
1200 	PINMUX_IPSR_MSEL(IP0SR8_31_28,	SDA3,			SEL_SDA3_0),
1201 
1202 	/* IP1SR8 */
1203 	PINMUX_IPSR_MSEL(IP1SR8_3_0,	SCL4,			SEL_SCL4_0),
1204 	PINMUX_IPSR_MSEL(IP1SR8_3_0,	HRX2,			SEL_SCL4_0),
1205 	PINMUX_IPSR_MSEL(IP1SR8_3_0,	SCK4,			SEL_SCL4_0),
1206 
1207 	PINMUX_IPSR_MSEL(IP1SR8_7_4,	SDA4,			SEL_SDA4_0),
1208 	PINMUX_IPSR_MSEL(IP1SR8_7_4,	HTX2,			SEL_SDA4_0),
1209 	PINMUX_IPSR_MSEL(IP1SR8_7_4,	CTS4_N,			SEL_SDA4_0),
1210 
1211 	PINMUX_IPSR_MSEL(IP1SR8_11_8,	SCL5,			SEL_SCL5_0),
1212 	PINMUX_IPSR_MSEL(IP1SR8_11_8,	HRTS2_N,		SEL_SCL5_0),
1213 	PINMUX_IPSR_MSEL(IP1SR8_11_8,	RTS4_N,			SEL_SCL5_0),
1214 
1215 	PINMUX_IPSR_MSEL(IP1SR8_15_12,	SDA5,			SEL_SDA5_0),
1216 	PINMUX_IPSR_MSEL(IP1SR8_15_12,	SCIF_CLK2,		SEL_SDA5_0),
1217 
1218 	PINMUX_IPSR_GPSR(IP1SR8_19_16,	HCTS2_N),
1219 	PINMUX_IPSR_GPSR(IP1SR8_19_16,	TX4),
1220 
1221 	PINMUX_IPSR_GPSR(IP1SR8_23_20,	HSCK2),
1222 	PINMUX_IPSR_GPSR(IP1SR8_23_20,	RX4),
1223 };
1224 
1225 /*
1226  * Pins not associated with a GPIO port.
1227  */
1228 enum {
1229 	GP_ASSIGN_LAST(),
1230 	NOGP_ALL(),
1231 };
1232 
1233 static const struct sh_pfc_pin pinmux_pins[] = {
1234 	PINMUX_GPIO_GP_ALL(),
1235 	PINMUX_NOGP_ALL(),
1236 };
1237 
1238 /* - AUDIO CLOCK ----------------------------------------- */
1239 static const unsigned int audio_clkin_pins[] = {
1240 	/* CLK IN */
1241 	RCAR_GP_PIN(1, 22),
1242 };
1243 static const unsigned int audio_clkin_mux[] = {
1244 	AUDIO_CLKIN_MARK,
1245 };
1246 static const unsigned int audio_clkout_pins[] = {
1247 	/* CLK OUT */
1248 	RCAR_GP_PIN(1, 21),
1249 };
1250 static const unsigned int audio_clkout_mux[] = {
1251 	AUDIO_CLKOUT_MARK,
1252 };
1253 
1254 /* - AVB0 ------------------------------------------------ */
1255 static const unsigned int avb0_link_pins[] = {
1256 	/* AVB0_LINK */
1257 	RCAR_GP_PIN(7, 4),
1258 };
1259 static const unsigned int avb0_link_mux[] = {
1260 	AVB0_LINK_MARK,
1261 };
1262 static const unsigned int avb0_magic_pins[] = {
1263 	/* AVB0_MAGIC */
1264 	RCAR_GP_PIN(7, 10),
1265 };
1266 static const unsigned int avb0_magic_mux[] = {
1267 	AVB0_MAGIC_MARK,
1268 };
1269 static const unsigned int avb0_phy_int_pins[] = {
1270 	/* AVB0_PHY_INT */
1271 	RCAR_GP_PIN(7, 5),
1272 };
1273 static const unsigned int avb0_phy_int_mux[] = {
1274 	AVB0_PHY_INT_MARK,
1275 };
1276 static const unsigned int avb0_mdio_pins[] = {
1277 	/* AVB0_MDC, AVB0_MDIO */
1278 	RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14),
1279 };
1280 static const unsigned int avb0_mdio_mux[] = {
1281 	AVB0_MDC_MARK, AVB0_MDIO_MARK,
1282 };
1283 static const unsigned int avb0_rgmii_pins[] = {
1284 	/*
1285 	 * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,
1286 	 * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3,
1287 	 */
1288 	RCAR_GP_PIN(7, 16), RCAR_GP_PIN(7, 15),
1289 	RCAR_GP_PIN(7, 11), RCAR_GP_PIN(7,  7),
1290 	RCAR_GP_PIN(7,  6), RCAR_GP_PIN(7,  3),
1291 	RCAR_GP_PIN(7, 20), RCAR_GP_PIN(7, 19),
1292 	RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),
1293 	RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7,  8),
1294 };
1295 static const unsigned int avb0_rgmii_mux[] = {
1296 	AVB0_TX_CTL_MARK,	AVB0_TXC_MARK,
1297 	AVB0_TD0_MARK,		AVB0_TD1_MARK,
1298 	AVB0_TD2_MARK,		AVB0_TD3_MARK,
1299 	AVB0_RX_CTL_MARK,	AVB0_RXC_MARK,
1300 	AVB0_RD0_MARK,		AVB0_RD1_MARK,
1301 	AVB0_RD2_MARK,		AVB0_RD3_MARK,
1302 };
1303 static const unsigned int avb0_txcrefclk_pins[] = {
1304 	/* AVB0_TXCREFCLK */
1305 	RCAR_GP_PIN(7, 9),
1306 };
1307 static const unsigned int avb0_txcrefclk_mux[] = {
1308 	AVB0_TXCREFCLK_MARK,
1309 };
1310 static const unsigned int avb0_avtp_pps_pins[] = {
1311 	/* AVB0_AVTP_PPS */
1312 	RCAR_GP_PIN(7, 0),
1313 };
1314 static const unsigned int avb0_avtp_pps_mux[] = {
1315 	AVB0_AVTP_PPS_MARK,
1316 };
1317 static const unsigned int avb0_avtp_capture_pins[] = {
1318 	/* AVB0_AVTP_CAPTURE */
1319 	RCAR_GP_PIN(7, 1),
1320 };
1321 static const unsigned int avb0_avtp_capture_mux[] = {
1322 	AVB0_AVTP_CAPTURE_MARK,
1323 };
1324 static const unsigned int avb0_avtp_match_pins[] = {
1325 	/* AVB0_AVTP_MATCH */
1326 	RCAR_GP_PIN(7, 2),
1327 };
1328 static const unsigned int avb0_avtp_match_mux[] = {
1329 	AVB0_AVTP_MATCH_MARK,
1330 };
1331 
1332 /* - AVB1 ------------------------------------------------ */
1333 static const unsigned int avb1_link_pins[] = {
1334 	/* AVB1_LINK */
1335 	RCAR_GP_PIN(6, 4),
1336 };
1337 static const unsigned int avb1_link_mux[] = {
1338 	AVB1_LINK_MARK,
1339 };
1340 static const unsigned int avb1_magic_pins[] = {
1341 	/* AVB1_MAGIC */
1342 	RCAR_GP_PIN(6, 1),
1343 };
1344 static const unsigned int avb1_magic_mux[] = {
1345 	AVB1_MAGIC_MARK,
1346 };
1347 static const unsigned int avb1_phy_int_pins[] = {
1348 	/* AVB1_PHY_INT */
1349 	RCAR_GP_PIN(6, 3),
1350 };
1351 static const unsigned int avb1_phy_int_mux[] = {
1352 	AVB1_PHY_INT_MARK,
1353 };
1354 static const unsigned int avb1_mdio_pins[] = {
1355 	/* AVB1_MDC, AVB1_MDIO */
1356 	RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 0),
1357 };
1358 static const unsigned int avb1_mdio_mux[] = {
1359 	AVB1_MDC_MARK, AVB1_MDIO_MARK,
1360 };
1361 static const unsigned int avb1_rgmii_pins[] = {
1362 	/*
1363 	 * AVB1_TX_CTL, AVB1_TXC, AVB1_TD0, AVB1_TD1, AVB1_TD2, AVB1_TD3,
1364 	 * AVB1_RX_CTL, AVB1_RXC, AVB1_RD0, AVB1_RD1, AVB1_RD2, AVB1_RD3,
1365 	 */
1366 	RCAR_GP_PIN(6,  7), RCAR_GP_PIN(6,  6),
1367 	RCAR_GP_PIN(6, 13), RCAR_GP_PIN(6, 12),
1368 	RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 18),
1369 	RCAR_GP_PIN(6,  9), RCAR_GP_PIN(6,  8),
1370 	RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14),
1371 	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 19),
1372 };
1373 static const unsigned int avb1_rgmii_mux[] = {
1374 	AVB1_TX_CTL_MARK,	AVB1_TXC_MARK,
1375 	AVB1_TD0_MARK,		AVB1_TD1_MARK,
1376 	AVB1_TD2_MARK,		AVB1_TD3_MARK,
1377 	AVB1_RX_CTL_MARK,	AVB1_RXC_MARK,
1378 	AVB1_RD0_MARK,		AVB1_RD1_MARK,
1379 	AVB1_RD2_MARK,		AVB1_RD3_MARK,
1380 };
1381 static const unsigned int avb1_txcrefclk_pins[] = {
1382 	/* AVB1_TXCREFCLK */
1383 	RCAR_GP_PIN(6, 20),
1384 };
1385 static const unsigned int avb1_txcrefclk_mux[] = {
1386 	AVB1_TXCREFCLK_MARK,
1387 };
1388 static const unsigned int avb1_avtp_pps_pins[] = {
1389 	/* AVB1_AVTP_PPS */
1390 	RCAR_GP_PIN(6, 10),
1391 };
1392 static const unsigned int avb1_avtp_pps_mux[] = {
1393 	AVB1_AVTP_PPS_MARK,
1394 };
1395 static const unsigned int avb1_avtp_capture_pins[] = {
1396 	/* AVB1_AVTP_CAPTURE */
1397 	RCAR_GP_PIN(6, 11),
1398 };
1399 static const unsigned int avb1_avtp_capture_mux[] = {
1400 	AVB1_AVTP_CAPTURE_MARK,
1401 };
1402 static const unsigned int avb1_avtp_match_pins[] = {
1403 	/* AVB1_AVTP_MATCH */
1404 	RCAR_GP_PIN(6, 5),
1405 };
1406 static const unsigned int avb1_avtp_match_mux[] = {
1407 	AVB1_AVTP_MATCH_MARK,
1408 };
1409 
1410 /* - AVB2 ------------------------------------------------ */
1411 static const unsigned int avb2_link_pins[] = {
1412 	/* AVB2_LINK */
1413 	RCAR_GP_PIN(5, 3),
1414 };
1415 static const unsigned int avb2_link_mux[] = {
1416 	AVB2_LINK_MARK,
1417 };
1418 static const unsigned int avb2_magic_pins[] = {
1419 	/* AVB2_MAGIC */
1420 	RCAR_GP_PIN(5, 5),
1421 };
1422 static const unsigned int avb2_magic_mux[] = {
1423 	AVB2_MAGIC_MARK,
1424 };
1425 static const unsigned int avb2_phy_int_pins[] = {
1426 	/* AVB2_PHY_INT */
1427 	RCAR_GP_PIN(5, 4),
1428 };
1429 static const unsigned int avb2_phy_int_mux[] = {
1430 	AVB2_PHY_INT_MARK,
1431 };
1432 static const unsigned int avb2_mdio_pins[] = {
1433 	/* AVB2_MDC, AVB2_MDIO */
1434 	RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 10),
1435 };
1436 static const unsigned int avb2_mdio_mux[] = {
1437 	AVB2_MDC_MARK, AVB2_MDIO_MARK,
1438 };
1439 static const unsigned int avb2_rgmii_pins[] = {
1440 	/*
1441 	 * AVB2_TX_CTL, AVB2_TXC, AVB2_TD0, AVB2_TD1, AVB2_TD2, AVB2_TD3,
1442 	 * AVB2_RX_CTL, AVB2_RXC, AVB2_RD0, AVB2_RD1, AVB2_RD2, AVB2_RD3,
1443 	 */
1444 	RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 16),
1445 	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 12),
1446 	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5,  8),
1447 	RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 18),
1448 	RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 14),
1449 	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5,  9),
1450 };
1451 static const unsigned int avb2_rgmii_mux[] = {
1452 	AVB2_TX_CTL_MARK,	AVB2_TXC_MARK,
1453 	AVB2_TD0_MARK,		AVB2_TD1_MARK,
1454 	AVB2_TD2_MARK,		AVB2_TD3_MARK,
1455 	AVB2_RX_CTL_MARK,	AVB2_RXC_MARK,
1456 	AVB2_RD0_MARK,		AVB2_RD1_MARK,
1457 	AVB2_RD2_MARK,		AVB2_RD3_MARK,
1458 };
1459 static const unsigned int avb2_txcrefclk_pins[] = {
1460 	/* AVB2_TXCREFCLK */
1461 	RCAR_GP_PIN(5, 7),
1462 };
1463 static const unsigned int avb2_txcrefclk_mux[] = {
1464 	AVB2_TXCREFCLK_MARK,
1465 };
1466 static const unsigned int avb2_avtp_pps_pins[] = {
1467 	/* AVB2_AVTP_PPS */
1468 	RCAR_GP_PIN(5, 0),
1469 };
1470 static const unsigned int avb2_avtp_pps_mux[] = {
1471 	AVB2_AVTP_PPS_MARK,
1472 };
1473 static const unsigned int avb2_avtp_capture_pins[] = {
1474 	/* AVB2_AVTP_CAPTURE */
1475 	RCAR_GP_PIN(5, 1),
1476 };
1477 static const unsigned int avb2_avtp_capture_mux[] = {
1478 	AVB2_AVTP_CAPTURE_MARK,
1479 };
1480 static const unsigned int avb2_avtp_match_pins[] = {
1481 	/* AVB2_AVTP_MATCH */
1482 	RCAR_GP_PIN(5, 2),
1483 };
1484 static const unsigned int avb2_avtp_match_mux[] = {
1485 	AVB2_AVTP_MATCH_MARK,
1486 };
1487 
1488 /* - CANFD0 ----------------------------------------------------------------- */
1489 static const unsigned int canfd0_data_pins[] = {
1490 	/* CANFD0_TX, CANFD0_RX */
1491 	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1492 };
1493 static const unsigned int canfd0_data_mux[] = {
1494 	CANFD0_TX_MARK, CANFD0_RX_MARK,
1495 };
1496 
1497 /* - CANFD1 ----------------------------------------------------------------- */
1498 static const unsigned int canfd1_data_pins[] = {
1499 	/* CANFD1_TX, CANFD1_RX */
1500 	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1501 };
1502 static const unsigned int canfd1_data_mux[] = {
1503 	CANFD1_TX_MARK, CANFD1_RX_MARK,
1504 };
1505 
1506 /* - CANFD2 ----------------------------------------------------------------- */
1507 static const unsigned int canfd2_data_pins[] = {
1508 	/* CANFD2_TX, CANFD2_RX */
1509 	RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1510 };
1511 static const unsigned int canfd2_data_mux[] = {
1512 	CANFD2_TX_MARK, CANFD2_RX_MARK,
1513 };
1514 
1515 /* - CANFD3 ----------------------------------------------------------------- */
1516 static const unsigned int canfd3_data_pins[] = {
1517 	/* CANFD3_TX, CANFD3_RX */
1518 	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1519 };
1520 static const unsigned int canfd3_data_mux[] = {
1521 	CANFD3_TX_MARK, CANFD3_RX_MARK,
1522 };
1523 
1524 /* - CANFD4 ----------------------------------------------------------------- */
1525 static const unsigned int canfd4_data_pins[] = {
1526 	/* CANFD4_TX, CANFD4_RX */
1527 	RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
1528 };
1529 static const unsigned int canfd4_data_mux[] = {
1530 	CANFD4_TX_MARK, CANFD4_RX_MARK,
1531 };
1532 
1533 /* - CANFD5 ----------------------------------------------------------------- */
1534 static const unsigned int canfd5_data_pins[] = {
1535 	/* CANFD5_TX, CANFD5_RX */
1536 	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
1537 };
1538 static const unsigned int canfd5_data_mux[] = {
1539 	CANFD5_TX_MARK, CANFD5_RX_MARK,
1540 };
1541 
1542 /* - CANFD5_B ----------------------------------------------------------------- */
1543 static const unsigned int canfd5_data_b_pins[] = {
1544 	/* CANFD5_TX_B, CANFD5_RX_B */
1545 	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
1546 };
1547 static const unsigned int canfd5_data_b_mux[] = {
1548 	CANFD5_TX_B_MARK, CANFD5_RX_B_MARK,
1549 };
1550 
1551 /* - CANFD6 ----------------------------------------------------------------- */
1552 static const unsigned int canfd6_data_pins[] = {
1553 	/* CANFD6_TX, CANFD6_RX */
1554 	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
1555 };
1556 static const unsigned int canfd6_data_mux[] = {
1557 	CANFD6_TX_MARK, CANFD6_RX_MARK,
1558 };
1559 
1560 /* - CANFD7 ----------------------------------------------------------------- */
1561 static const unsigned int canfd7_data_pins[] = {
1562 	/* CANFD7_TX, CANFD7_RX */
1563 	RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
1564 };
1565 static const unsigned int canfd7_data_mux[] = {
1566 	CANFD7_TX_MARK, CANFD7_RX_MARK,
1567 };
1568 
1569 /* - CANFD Clock ------------------------------------------------------------ */
1570 static const unsigned int can_clk_pins[] = {
1571 	/* CAN_CLK */
1572 	RCAR_GP_PIN(2, 9),
1573 };
1574 static const unsigned int can_clk_mux[] = {
1575 	CAN_CLK_MARK,
1576 };
1577 
1578 /* - HSCIF0 ----------------------------------------------------------------- */
1579 static const unsigned int hscif0_data_pins[] = {
1580 	/* HRX0, HTX0 */
1581 	RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12),
1582 };
1583 static const unsigned int hscif0_data_mux[] = {
1584 	HRX0_MARK, HTX0_MARK,
1585 };
1586 static const unsigned int hscif0_clk_pins[] = {
1587 	/* HSCK0 */
1588 	RCAR_GP_PIN(1, 15),
1589 };
1590 static const unsigned int hscif0_clk_mux[] = {
1591 	HSCK0_MARK,
1592 };
1593 static const unsigned int hscif0_ctrl_pins[] = {
1594 	/* HRTS0_N, HCTS0_N */
1595 	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1596 };
1597 static const unsigned int hscif0_ctrl_mux[] = {
1598 	HRTS0_N_MARK, HCTS0_N_MARK,
1599 };
1600 
1601 /* - HSCIF1 ----------------------------------------------------------------- */
1602 static const unsigned int hscif1_data_pins[] = {
1603 	/* HRX1, HTX1 */
1604 	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
1605 };
1606 static const unsigned int hscif1_data_mux[] = {
1607 	HRX1_MARK, HTX1_MARK,
1608 };
1609 static const unsigned int hscif1_clk_pins[] = {
1610 	/* HSCK1 */
1611 	RCAR_GP_PIN(0, 18),
1612 };
1613 static const unsigned int hscif1_clk_mux[] = {
1614 	HSCK1_MARK,
1615 };
1616 static const unsigned int hscif1_ctrl_pins[] = {
1617 	/* HRTS1_N, HCTS1_N */
1618 	RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
1619 };
1620 static const unsigned int hscif1_ctrl_mux[] = {
1621 	HRTS1_N_MARK, HCTS1_N_MARK,
1622 };
1623 
1624 /* - HSCIF1_X---------------------------------------------------------------- */
1625 static const unsigned int hscif1_data_x_pins[] = {
1626 	/* HRX1_X, HTX1_X */
1627 	RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
1628 };
1629 static const unsigned int hscif1_data_x_mux[] = {
1630 	HRX1_X_MARK, HTX1_X_MARK,
1631 };
1632 static const unsigned int hscif1_clk_x_pins[] = {
1633 	/* HSCK1_X */
1634 	RCAR_GP_PIN(1, 10),
1635 };
1636 static const unsigned int hscif1_clk_x_mux[] = {
1637 	HSCK1_X_MARK,
1638 };
1639 static const unsigned int hscif1_ctrl_x_pins[] = {
1640 	/* HRTS1_N_X, HCTS1_N_X */
1641 	RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
1642 };
1643 static const unsigned int hscif1_ctrl_x_mux[] = {
1644 	HRTS1_N_X_MARK, HCTS1_N_X_MARK,
1645 };
1646 
1647 /* - HSCIF2 ----------------------------------------------------------------- */
1648 static const unsigned int hscif2_data_pins[] = {
1649 	/* HRX2, HTX2 */
1650 	RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
1651 };
1652 static const unsigned int hscif2_data_mux[] = {
1653 	HRX2_MARK, HTX2_MARK,
1654 };
1655 static const unsigned int hscif2_clk_pins[] = {
1656 	/* HSCK2 */
1657 	RCAR_GP_PIN(8, 13),
1658 };
1659 static const unsigned int hscif2_clk_mux[] = {
1660 	HSCK2_MARK,
1661 };
1662 static const unsigned int hscif2_ctrl_pins[] = {
1663 	/* HRTS2_N, HCTS2_N */
1664 	RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 12),
1665 };
1666 static const unsigned int hscif2_ctrl_mux[] = {
1667 	HRTS2_N_MARK, HCTS2_N_MARK,
1668 };
1669 
1670 /* - HSCIF3 ----------------------------------------------------------------- */
1671 static const unsigned int hscif3_data_pins[] = {
1672 	/* HRX3, HTX3 */
1673 	RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 28),
1674 };
1675 static const unsigned int hscif3_data_mux[] = {
1676 	HRX3_MARK, HTX3_MARK,
1677 };
1678 static const unsigned int hscif3_clk_pins[] = {
1679 	/* HSCK3 */
1680 	RCAR_GP_PIN(1, 25),
1681 };
1682 static const unsigned int hscif3_clk_mux[] = {
1683 	HSCK3_MARK,
1684 };
1685 static const unsigned int hscif3_ctrl_pins[] = {
1686 	/* HRTS3_N, HCTS3_N */
1687 	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27),
1688 };
1689 static const unsigned int hscif3_ctrl_mux[] = {
1690 	HRTS3_N_MARK, HCTS3_N_MARK,
1691 };
1692 
1693 /* - HSCIF3_A ----------------------------------------------------------------- */
1694 static const unsigned int hscif3_data_a_pins[] = {
1695 	/* HRX3_A, HTX3_A */
1696 	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0),
1697 };
1698 static const unsigned int hscif3_data_a_mux[] = {
1699 	HRX3_A_MARK, HTX3_A_MARK,
1700 };
1701 static const unsigned int hscif3_clk_a_pins[] = {
1702 	/* HSCK3_A */
1703 	RCAR_GP_PIN(1, 3),
1704 };
1705 static const unsigned int hscif3_clk_a_mux[] = {
1706 	HSCK3_A_MARK,
1707 };
1708 static const unsigned int hscif3_ctrl_a_pins[] = {
1709 	/* HRTS3_N_A, HCTS3_N_A */
1710 	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
1711 };
1712 static const unsigned int hscif3_ctrl_a_mux[] = {
1713 	HRTS3_N_A_MARK, HCTS3_N_A_MARK,
1714 };
1715 
1716 /* - I2C0 ------------------------------------------------------------------- */
1717 static const unsigned int i2c0_pins[] = {
1718 	/* SDA0, SCL0 */
1719 	RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 0),
1720 };
1721 static const unsigned int i2c0_mux[] = {
1722 	SDA0_MARK, SCL0_MARK,
1723 };
1724 
1725 /* - I2C1 ------------------------------------------------------------------- */
1726 static const unsigned int i2c1_pins[] = {
1727 	/* SDA1, SCL1 */
1728 	RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 2),
1729 };
1730 static const unsigned int i2c1_mux[] = {
1731 	SDA1_MARK, SCL1_MARK,
1732 };
1733 
1734 /* - I2C2 ------------------------------------------------------------------- */
1735 static const unsigned int i2c2_pins[] = {
1736 	/* SDA2, SCL2 */
1737 	RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 4),
1738 };
1739 static const unsigned int i2c2_mux[] = {
1740 	SDA2_MARK, SCL2_MARK,
1741 };
1742 
1743 /* - I2C3 ------------------------------------------------------------------- */
1744 static const unsigned int i2c3_pins[] = {
1745 	/* SDA3, SCL3 */
1746 	RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 6),
1747 };
1748 static const unsigned int i2c3_mux[] = {
1749 	SDA3_MARK, SCL3_MARK,
1750 };
1751 
1752 /* - I2C4 ------------------------------------------------------------------- */
1753 static const unsigned int i2c4_pins[] = {
1754 	/* SDA4, SCL4 */
1755 	RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 8),
1756 };
1757 static const unsigned int i2c4_mux[] = {
1758 	SDA4_MARK, SCL4_MARK,
1759 };
1760 
1761 /* - I2C5 ------------------------------------------------------------------- */
1762 static const unsigned int i2c5_pins[] = {
1763 	/* SDA5, SCL5 */
1764 	RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 10),
1765 };
1766 static const unsigned int i2c5_mux[] = {
1767 	SDA5_MARK, SCL5_MARK,
1768 };
1769 
1770 /* - MMC -------------------------------------------------------------------- */
1771 static const unsigned int mmc_data_pins[] = {
1772 	/* MMC_SD_D[0:3], MMC_D[4:7] */
1773 	RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
1774 	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 5),
1775 	RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6),
1776 	RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
1777 };
1778 static const unsigned int mmc_data_mux[] = {
1779 	MMC_SD_D0_MARK, MMC_SD_D1_MARK,
1780 	MMC_SD_D2_MARK, MMC_SD_D3_MARK,
1781 	MMC_D4_MARK, MMC_D5_MARK,
1782 	MMC_D6_MARK, MMC_D7_MARK,
1783 };
1784 static const unsigned int mmc_ctrl_pins[] = {
1785 	/* MMC_SD_CLK, MMC_SD_CMD */
1786 	RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 10),
1787 };
1788 static const unsigned int mmc_ctrl_mux[] = {
1789 	MMC_SD_CLK_MARK, MMC_SD_CMD_MARK,
1790 };
1791 static const unsigned int mmc_cd_pins[] = {
1792 	/* SD_CD */
1793 	RCAR_GP_PIN(3, 11),
1794 };
1795 static const unsigned int mmc_cd_mux[] = {
1796 	SD_CD_MARK,
1797 };
1798 static const unsigned int mmc_wp_pins[] = {
1799 	/* SD_WP */
1800 	RCAR_GP_PIN(3, 12),
1801 };
1802 static const unsigned int mmc_wp_mux[] = {
1803 	SD_WP_MARK,
1804 };
1805 static const unsigned int mmc_ds_pins[] = {
1806 	/* MMC_DS */
1807 	RCAR_GP_PIN(3, 4),
1808 };
1809 static const unsigned int mmc_ds_mux[] = {
1810 	MMC_DS_MARK,
1811 };
1812 
1813 /* - MSIOF0 ----------------------------------------------------------------- */
1814 static const unsigned int msiof0_clk_pins[] = {
1815 	/* MSIOF0_SCK */
1816 	RCAR_GP_PIN(1, 10),
1817 };
1818 static const unsigned int msiof0_clk_mux[] = {
1819 	MSIOF0_SCK_MARK,
1820 };
1821 static const unsigned int msiof0_sync_pins[] = {
1822 	/* MSIOF0_SYNC */
1823 	RCAR_GP_PIN(1, 8),
1824 };
1825 static const unsigned int msiof0_sync_mux[] = {
1826 	MSIOF0_SYNC_MARK,
1827 };
1828 static const unsigned int msiof0_ss1_pins[] = {
1829 	/* MSIOF0_SS1 */
1830 	RCAR_GP_PIN(1, 7),
1831 };
1832 static const unsigned int msiof0_ss1_mux[] = {
1833 	MSIOF0_SS1_MARK,
1834 };
1835 static const unsigned int msiof0_ss2_pins[] = {
1836 	/* MSIOF0_SS2 */
1837 	RCAR_GP_PIN(1, 6),
1838 };
1839 static const unsigned int msiof0_ss2_mux[] = {
1840 	MSIOF0_SS2_MARK,
1841 };
1842 static const unsigned int msiof0_txd_pins[] = {
1843 	/* MSIOF0_TXD */
1844 	RCAR_GP_PIN(1, 9),
1845 };
1846 static const unsigned int msiof0_txd_mux[] = {
1847 	MSIOF0_TXD_MARK,
1848 };
1849 static const unsigned int msiof0_rxd_pins[] = {
1850 	/* MSIOF0_RXD */
1851 	RCAR_GP_PIN(1, 11),
1852 };
1853 static const unsigned int msiof0_rxd_mux[] = {
1854 	MSIOF0_RXD_MARK,
1855 };
1856 
1857 /* - MSIOF1 ----------------------------------------------------------------- */
1858 static const unsigned int msiof1_clk_pins[] = {
1859 	/* MSIOF1_SCK */
1860 	RCAR_GP_PIN(1, 3),
1861 };
1862 static const unsigned int msiof1_clk_mux[] = {
1863 	MSIOF1_SCK_MARK,
1864 };
1865 static const unsigned int msiof1_sync_pins[] = {
1866 	/* MSIOF1_SYNC */
1867 	RCAR_GP_PIN(1, 2),
1868 };
1869 static const unsigned int msiof1_sync_mux[] = {
1870 	MSIOF1_SYNC_MARK,
1871 };
1872 static const unsigned int msiof1_ss1_pins[] = {
1873 	/* MSIOF1_SS1 */
1874 	RCAR_GP_PIN(1, 1),
1875 };
1876 static const unsigned int msiof1_ss1_mux[] = {
1877 	MSIOF1_SS1_MARK,
1878 };
1879 static const unsigned int msiof1_ss2_pins[] = {
1880 	/* MSIOF1_SS2 */
1881 	RCAR_GP_PIN(1, 0),
1882 };
1883 static const unsigned int msiof1_ss2_mux[] = {
1884 	MSIOF1_SS2_MARK,
1885 };
1886 static const unsigned int msiof1_txd_pins[] = {
1887 	/* MSIOF1_TXD */
1888 	RCAR_GP_PIN(1, 4),
1889 };
1890 static const unsigned int msiof1_txd_mux[] = {
1891 	MSIOF1_TXD_MARK,
1892 };
1893 static const unsigned int msiof1_rxd_pins[] = {
1894 	/* MSIOF1_RXD */
1895 	RCAR_GP_PIN(1, 5),
1896 };
1897 static const unsigned int msiof1_rxd_mux[] = {
1898 	MSIOF1_RXD_MARK,
1899 };
1900 
1901 /* - MSIOF2 ----------------------------------------------------------------- */
1902 static const unsigned int msiof2_clk_pins[] = {
1903 	/* MSIOF2_SCK */
1904 	RCAR_GP_PIN(0, 17),
1905 };
1906 static const unsigned int msiof2_clk_mux[] = {
1907 	MSIOF2_SCK_MARK,
1908 };
1909 static const unsigned int msiof2_sync_pins[] = {
1910 	/* MSIOF2_SYNC */
1911 	RCAR_GP_PIN(0, 15),
1912 };
1913 static const unsigned int msiof2_sync_mux[] = {
1914 	MSIOF2_SYNC_MARK,
1915 };
1916 static const unsigned int msiof2_ss1_pins[] = {
1917 	/* MSIOF2_SS1 */
1918 	RCAR_GP_PIN(0, 14),
1919 };
1920 static const unsigned int msiof2_ss1_mux[] = {
1921 	MSIOF2_SS1_MARK,
1922 };
1923 static const unsigned int msiof2_ss2_pins[] = {
1924 	/* MSIOF2_SS2 */
1925 	RCAR_GP_PIN(0, 13),
1926 };
1927 static const unsigned int msiof2_ss2_mux[] = {
1928 	MSIOF2_SS2_MARK,
1929 };
1930 static const unsigned int msiof2_txd_pins[] = {
1931 	/* MSIOF2_TXD */
1932 	RCAR_GP_PIN(0, 16),
1933 };
1934 static const unsigned int msiof2_txd_mux[] = {
1935 	MSIOF2_TXD_MARK,
1936 };
1937 static const unsigned int msiof2_rxd_pins[] = {
1938 	/* MSIOF2_RXD */
1939 	RCAR_GP_PIN(0, 18),
1940 };
1941 static const unsigned int msiof2_rxd_mux[] = {
1942 	MSIOF2_RXD_MARK,
1943 };
1944 
1945 /* - MSIOF3 ----------------------------------------------------------------- */
1946 static const unsigned int msiof3_clk_pins[] = {
1947 	/* MSIOF3_SCK */
1948 	RCAR_GP_PIN(0, 3),
1949 };
1950 static const unsigned int msiof3_clk_mux[] = {
1951 	MSIOF3_SCK_MARK,
1952 };
1953 static const unsigned int msiof3_sync_pins[] = {
1954 	/* MSIOF3_SYNC */
1955 	RCAR_GP_PIN(0, 6),
1956 };
1957 static const unsigned int msiof3_sync_mux[] = {
1958 	MSIOF3_SYNC_MARK,
1959 };
1960 static const unsigned int msiof3_ss1_pins[] = {
1961 	/* MSIOF3_SS1 */
1962 	RCAR_GP_PIN(0, 1),
1963 };
1964 static const unsigned int msiof3_ss1_mux[] = {
1965 	MSIOF3_SS1_MARK,
1966 };
1967 static const unsigned int msiof3_ss2_pins[] = {
1968 	/* MSIOF3_SS2 */
1969 	RCAR_GP_PIN(0, 2),
1970 };
1971 static const unsigned int msiof3_ss2_mux[] = {
1972 	MSIOF3_SS2_MARK,
1973 };
1974 static const unsigned int msiof3_txd_pins[] = {
1975 	/* MSIOF3_TXD */
1976 	RCAR_GP_PIN(0, 4),
1977 };
1978 static const unsigned int msiof3_txd_mux[] = {
1979 	MSIOF3_TXD_MARK,
1980 };
1981 static const unsigned int msiof3_rxd_pins[] = {
1982 	/* MSIOF3_RXD */
1983 	RCAR_GP_PIN(0, 5),
1984 };
1985 static const unsigned int msiof3_rxd_mux[] = {
1986 	MSIOF3_RXD_MARK,
1987 };
1988 
1989 /* - MSIOF4 ----------------------------------------------------------------- */
1990 static const unsigned int msiof4_clk_pins[] = {
1991 	/* MSIOF4_SCK */
1992 	RCAR_GP_PIN(1, 25),
1993 };
1994 static const unsigned int msiof4_clk_mux[] = {
1995 	MSIOF4_SCK_MARK,
1996 };
1997 static const unsigned int msiof4_sync_pins[] = {
1998 	/* MSIOF4_SYNC */
1999 	RCAR_GP_PIN(1, 28),
2000 };
2001 static const unsigned int msiof4_sync_mux[] = {
2002 	MSIOF4_SYNC_MARK,
2003 };
2004 static const unsigned int msiof4_ss1_pins[] = {
2005 	/* MSIOF4_SS1 */
2006 	RCAR_GP_PIN(1, 23),
2007 };
2008 static const unsigned int msiof4_ss1_mux[] = {
2009 	MSIOF4_SS1_MARK,
2010 };
2011 static const unsigned int msiof4_ss2_pins[] = {
2012 	/* MSIOF4_SS2 */
2013 	RCAR_GP_PIN(1, 24),
2014 };
2015 static const unsigned int msiof4_ss2_mux[] = {
2016 	MSIOF4_SS2_MARK,
2017 };
2018 static const unsigned int msiof4_txd_pins[] = {
2019 	/* MSIOF4_TXD */
2020 	RCAR_GP_PIN(1, 26),
2021 };
2022 static const unsigned int msiof4_txd_mux[] = {
2023 	MSIOF4_TXD_MARK,
2024 };
2025 static const unsigned int msiof4_rxd_pins[] = {
2026 	/* MSIOF4_RXD */
2027 	RCAR_GP_PIN(1, 27),
2028 };
2029 static const unsigned int msiof4_rxd_mux[] = {
2030 	MSIOF4_RXD_MARK,
2031 };
2032 
2033 /* - MSIOF5 ----------------------------------------------------------------- */
2034 static const unsigned int msiof5_clk_pins[] = {
2035 	/* MSIOF5_SCK */
2036 	RCAR_GP_PIN(0, 11),
2037 };
2038 static const unsigned int msiof5_clk_mux[] = {
2039 	MSIOF5_SCK_MARK,
2040 };
2041 static const unsigned int msiof5_sync_pins[] = {
2042 	/* MSIOF5_SYNC */
2043 	RCAR_GP_PIN(0, 9),
2044 };
2045 static const unsigned int msiof5_sync_mux[] = {
2046 	MSIOF5_SYNC_MARK,
2047 };
2048 static const unsigned int msiof5_ss1_pins[] = {
2049 	/* MSIOF5_SS1 */
2050 	RCAR_GP_PIN(0, 8),
2051 };
2052 static const unsigned int msiof5_ss1_mux[] = {
2053 	MSIOF5_SS1_MARK,
2054 };
2055 static const unsigned int msiof5_ss2_pins[] = {
2056 	/* MSIOF5_SS2 */
2057 	RCAR_GP_PIN(0, 7),
2058 };
2059 static const unsigned int msiof5_ss2_mux[] = {
2060 	MSIOF5_SS2_MARK,
2061 };
2062 static const unsigned int msiof5_txd_pins[] = {
2063 	/* MSIOF5_TXD */
2064 	RCAR_GP_PIN(0, 10),
2065 };
2066 static const unsigned int msiof5_txd_mux[] = {
2067 	MSIOF5_TXD_MARK,
2068 };
2069 static const unsigned int msiof5_rxd_pins[] = {
2070 	/* MSIOF5_RXD */
2071 	RCAR_GP_PIN(0, 12),
2072 };
2073 static const unsigned int msiof5_rxd_mux[] = {
2074 	MSIOF5_RXD_MARK,
2075 };
2076 
2077 /* - PCIE ------------------------------------------------------------------- */
2078 static const unsigned int pcie0_clkreq_n_pins[] = {
2079 	/* PCIE0_CLKREQ_N */
2080 	RCAR_GP_PIN(4, 21),
2081 };
2082 
2083 static const unsigned int pcie0_clkreq_n_mux[] = {
2084 	PCIE0_CLKREQ_N_MARK,
2085 };
2086 
2087 static const unsigned int pcie1_clkreq_n_pins[] = {
2088 	/* PCIE1_CLKREQ_N */
2089 	RCAR_GP_PIN(4, 22),
2090 };
2091 
2092 static const unsigned int pcie1_clkreq_n_mux[] = {
2093 	PCIE1_CLKREQ_N_MARK,
2094 };
2095 
2096 /* - PWM0_A ------------------------------------------------------------------- */
2097 static const unsigned int pwm0_a_pins[] = {
2098 	/* PWM0_A */
2099 	RCAR_GP_PIN(1, 15),
2100 };
2101 static const unsigned int pwm0_a_mux[] = {
2102 	PWM0_A_MARK,
2103 };
2104 
2105 /* - PWM1_A ------------------------------------------------------------------- */
2106 static const unsigned int pwm1_a_pins[] = {
2107 	/* PWM1_A */
2108 	RCAR_GP_PIN(3, 13),
2109 };
2110 static const unsigned int pwm1_a_mux[] = {
2111 	PWM1_A_MARK,
2112 };
2113 
2114 /* - PWM1_B ------------------------------------------------------------------- */
2115 static const unsigned int pwm1_b_pins[] = {
2116 	/* PWM1_B */
2117 	RCAR_GP_PIN(2, 13),
2118 };
2119 static const unsigned int pwm1_b_mux[] = {
2120 	PWM1_B_MARK,
2121 };
2122 
2123 /* - PWM2_B ------------------------------------------------------------------- */
2124 static const unsigned int pwm2_b_pins[] = {
2125 	/* PWM2_B */
2126 	RCAR_GP_PIN(2, 14),
2127 };
2128 static const unsigned int pwm2_b_mux[] = {
2129 	PWM2_B_MARK,
2130 };
2131 
2132 /* - PWM3_A ------------------------------------------------------------------- */
2133 static const unsigned int pwm3_a_pins[] = {
2134 	/* PWM3_A */
2135 	RCAR_GP_PIN(1, 22),
2136 };
2137 static const unsigned int pwm3_a_mux[] = {
2138 	PWM3_A_MARK,
2139 };
2140 
2141 /* - PWM3_B ------------------------------------------------------------------- */
2142 static const unsigned int pwm3_b_pins[] = {
2143 	/* PWM3_B */
2144 	RCAR_GP_PIN(2, 15),
2145 };
2146 static const unsigned int pwm3_b_mux[] = {
2147 	PWM3_B_MARK,
2148 };
2149 
2150 /* - PWM4 ------------------------------------------------------------------- */
2151 static const unsigned int pwm4_pins[] = {
2152 	/* PWM4 */
2153 	RCAR_GP_PIN(2, 16),
2154 };
2155 static const unsigned int pwm4_mux[] = {
2156 	PWM4_MARK,
2157 };
2158 
2159 /* - PWM5 ------------------------------------------------------------------- */
2160 static const unsigned int pwm5_pins[] = {
2161 	/* PWM5 */
2162 	RCAR_GP_PIN(2, 17),
2163 };
2164 static const unsigned int pwm5_mux[] = {
2165 	PWM5_MARK,
2166 };
2167 
2168 /* - PWM6 ------------------------------------------------------------------- */
2169 static const unsigned int pwm6_pins[] = {
2170 	/* PWM6 */
2171 	RCAR_GP_PIN(2, 18),
2172 };
2173 static const unsigned int pwm6_mux[] = {
2174 	PWM6_MARK,
2175 };
2176 
2177 /* - PWM7 ------------------------------------------------------------------- */
2178 static const unsigned int pwm7_pins[] = {
2179 	/* PWM7 */
2180 	RCAR_GP_PIN(2, 19),
2181 };
2182 static const unsigned int pwm7_mux[] = {
2183 	PWM7_MARK,
2184 };
2185 
2186 /* - PWM8_A ------------------------------------------------------------------- */
2187 static const unsigned int pwm8_a_pins[] = {
2188 	/* PWM8_A */
2189 	RCAR_GP_PIN(1, 13),
2190 };
2191 static const unsigned int pwm8_a_mux[] = {
2192 	PWM8_A_MARK,
2193 };
2194 
2195 /* - PWM9_A ------------------------------------------------------------------- */
2196 static const unsigned int pwm9_a_pins[] = {
2197 	/* PWM9_A */
2198 	RCAR_GP_PIN(1, 14),
2199 };
2200 static const unsigned int pwm9_a_mux[] = {
2201 	PWM9_A_MARK,
2202 };
2203 
2204 /* - QSPI0 ------------------------------------------------------------------ */
2205 static const unsigned int qspi0_ctrl_pins[] = {
2206 	/* SPCLK, SSL */
2207 	RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 15),
2208 };
2209 static const unsigned int qspi0_ctrl_mux[] = {
2210 	QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
2211 };
2212 static const unsigned int qspi0_data_pins[] = {
2213 	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
2214 	RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
2215 	RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
2216 };
2217 static const unsigned int qspi0_data_mux[] = {
2218 	QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
2219 	QSPI0_IO2_MARK, QSPI0_IO3_MARK
2220 };
2221 
2222 /* - QSPI1 ------------------------------------------------------------------ */
2223 static const unsigned int qspi1_ctrl_pins[] = {
2224 	/* SPCLK, SSL */
2225 	RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 25),
2226 };
2227 static const unsigned int qspi1_ctrl_mux[] = {
2228 	QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
2229 };
2230 static const unsigned int qspi1_data_pins[] = {
2231 	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
2232 	RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 23),
2233 	RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 26),
2234 };
2235 static const unsigned int qspi1_data_mux[] = {
2236 	QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
2237 	QSPI1_IO2_MARK, QSPI1_IO3_MARK
2238 };
2239 
2240 /* - SCIF0 ------------------------------------------------------------------ */
2241 static const unsigned int scif0_data_pins[] = {
2242 	/* RX0, TX0 */
2243 	RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12),
2244 };
2245 static const unsigned int scif0_data_mux[] = {
2246 	RX0_MARK, TX0_MARK,
2247 };
2248 static const unsigned int scif0_clk_pins[] = {
2249 	/* SCK0 */
2250 	RCAR_GP_PIN(1, 15),
2251 };
2252 static const unsigned int scif0_clk_mux[] = {
2253 	SCK0_MARK,
2254 };
2255 static const unsigned int scif0_ctrl_pins[] = {
2256 	/* RTS0_N, CTS0_N */
2257 	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2258 };
2259 static const unsigned int scif0_ctrl_mux[] = {
2260 	RTS0_N_MARK, CTS0_N_MARK,
2261 };
2262 
2263 /* - SCIF1 ------------------------------------------------------------------ */
2264 static const unsigned int scif1_data_pins[] = {
2265 	/* RX1, TX1 */
2266 	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2267 };
2268 static const unsigned int scif1_data_mux[] = {
2269 	RX1_MARK, TX1_MARK,
2270 };
2271 static const unsigned int scif1_clk_pins[] = {
2272 	/* SCK1 */
2273 	RCAR_GP_PIN(0, 18),
2274 };
2275 static const unsigned int scif1_clk_mux[] = {
2276 	SCK1_MARK,
2277 };
2278 static const unsigned int scif1_ctrl_pins[] = {
2279 	/* RTS1_N, CTS1_N */
2280 	RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
2281 };
2282 static const unsigned int scif1_ctrl_mux[] = {
2283 	RTS1_N_MARK, CTS1_N_MARK,
2284 };
2285 
2286 /* - SCIF1_X ------------------------------------------------------------------ */
2287 static const unsigned int scif1_data_x_pins[] = {
2288 	/* RX1_X, TX1_X */
2289 	RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
2290 };
2291 static const unsigned int scif1_data_x_mux[] = {
2292 	RX1_X_MARK, TX1_X_MARK,
2293 };
2294 static const unsigned int scif1_clk_x_pins[] = {
2295 	/* SCK1_X */
2296 	RCAR_GP_PIN(1, 10),
2297 };
2298 static const unsigned int scif1_clk_x_mux[] = {
2299 	SCK1_X_MARK,
2300 };
2301 static const unsigned int scif1_ctrl_x_pins[] = {
2302 	/* RTS1_N_X, CTS1_N_X */
2303 	RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
2304 };
2305 static const unsigned int scif1_ctrl_x_mux[] = {
2306 	RTS1_N_X_MARK, CTS1_N_X_MARK,
2307 };
2308 
2309 /* - SCIF3 ------------------------------------------------------------------ */
2310 static const unsigned int scif3_data_pins[] = {
2311 	/* RX3, TX3 */
2312 	RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2313 };
2314 static const unsigned int scif3_data_mux[] = {
2315 	RX3_MARK, TX3_MARK,
2316 };
2317 static const unsigned int scif3_clk_pins[] = {
2318 	/* SCK3 */
2319 	RCAR_GP_PIN(1, 4),
2320 };
2321 static const unsigned int scif3_clk_mux[] = {
2322 	SCK3_MARK,
2323 };
2324 static const unsigned int scif3_ctrl_pins[] = {
2325 	/* RTS3_N, CTS3_N */
2326 	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
2327 };
2328 static const unsigned int scif3_ctrl_mux[] = {
2329 	RTS3_N_MARK, CTS3_N_MARK,
2330 };
2331 
2332 /* - SCIF3_A ------------------------------------------------------------------ */
2333 static const unsigned int scif3_data_a_pins[] = {
2334 	/* RX3_A, TX3_A */
2335 	RCAR_GP_PIN(1, 27), RCAR_GP_PIN(1, 28),
2336 };
2337 static const unsigned int scif3_data_a_mux[] = {
2338 	RX3_A_MARK, TX3_A_MARK,
2339 };
2340 static const unsigned int scif3_clk_a_pins[] = {
2341 	/* SCK3_A */
2342 	RCAR_GP_PIN(1, 24),
2343 };
2344 static const unsigned int scif3_clk_a_mux[] = {
2345 	SCK3_A_MARK,
2346 };
2347 static const unsigned int scif3_ctrl_a_pins[] = {
2348 	/* RTS3_N_A, CTS3_N_A */
2349 	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2350 };
2351 static const unsigned int scif3_ctrl_a_mux[] = {
2352 	RTS3_N_A_MARK, CTS3_N_A_MARK,
2353 };
2354 
2355 /* - SCIF4 ------------------------------------------------------------------ */
2356 static const unsigned int scif4_data_pins[] = {
2357 	/* RX4, TX4 */
2358 	RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 12),
2359 };
2360 static const unsigned int scif4_data_mux[] = {
2361 	RX4_MARK, TX4_MARK,
2362 };
2363 static const unsigned int scif4_clk_pins[] = {
2364 	/* SCK4 */
2365 	RCAR_GP_PIN(8, 8),
2366 };
2367 static const unsigned int scif4_clk_mux[] = {
2368 	SCK4_MARK,
2369 };
2370 static const unsigned int scif4_ctrl_pins[] = {
2371 	/* RTS4_N, CTS4_N */
2372 	RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 9),
2373 };
2374 static const unsigned int scif4_ctrl_mux[] = {
2375 	RTS4_N_MARK, CTS4_N_MARK,
2376 };
2377 
2378 /* - SCIF Clock ------------------------------------------------------------- */
2379 static const unsigned int scif_clk_pins[] = {
2380 	/* SCIF_CLK */
2381 	RCAR_GP_PIN(1, 17),
2382 };
2383 static const unsigned int scif_clk_mux[] = {
2384 	SCIF_CLK_MARK,
2385 };
2386 
2387 static const unsigned int scif_clk2_pins[] = {
2388 	/* SCIF_CLK2 */
2389 	RCAR_GP_PIN(8, 11),
2390 };
2391 static const unsigned int scif_clk2_mux[] = {
2392 	SCIF_CLK2_MARK,
2393 };
2394 
2395 /* - SSI ------------------------------------------------- */
2396 static const unsigned int ssi_data_pins[] = {
2397 	/* SSI_SD */
2398 	RCAR_GP_PIN(1, 20),
2399 };
2400 static const unsigned int ssi_data_mux[] = {
2401 	SSI_SD_MARK,
2402 };
2403 static const unsigned int ssi_ctrl_pins[] = {
2404 	/* SSI_SCK,  SSI_WS */
2405 	RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
2406 };
2407 static const unsigned int ssi_ctrl_mux[] = {
2408 	SSI_SCK_MARK, SSI_WS_MARK,
2409 };
2410 
2411 /* - TPU ------------------------------------------------------------------- */
2412 static const unsigned int tpu_to0_pins[] = {
2413 	/* TPU0TO0 */
2414 	RCAR_GP_PIN(2, 8),
2415 };
2416 static const unsigned int tpu_to0_mux[] = {
2417 	TPU0TO0_MARK,
2418 };
2419 static const unsigned int tpu_to1_pins[] = {
2420 	/* TPU0TO1 */
2421 	RCAR_GP_PIN(2, 7),
2422 };
2423 static const unsigned int tpu_to1_mux[] = {
2424 	TPU0TO1_MARK,
2425 };
2426 static const unsigned int tpu_to2_pins[] = {
2427 	/* TPU0TO2 */
2428 	RCAR_GP_PIN(2, 12),
2429 };
2430 static const unsigned int tpu_to2_mux[] = {
2431 	TPU0TO2_MARK,
2432 };
2433 static const unsigned int tpu_to3_pins[] = {
2434 	/* TPU0TO3 */
2435 	RCAR_GP_PIN(2, 13),
2436 };
2437 static const unsigned int tpu_to3_mux[] = {
2438 	TPU0TO3_MARK,
2439 };
2440 
2441 /* - TPU_A ------------------------------------------------------------------- */
2442 static const unsigned int tpu_to0_a_pins[] = {
2443 	/* TPU0TO0_A */
2444 	RCAR_GP_PIN(1, 25),
2445 };
2446 static const unsigned int tpu_to0_a_mux[] = {
2447 	TPU0TO0_A_MARK,
2448 };
2449 static const unsigned int tpu_to1_a_pins[] = {
2450 	/* TPU0TO1_A */
2451 	RCAR_GP_PIN(1, 26),
2452 };
2453 static const unsigned int tpu_to1_a_mux[] = {
2454 	TPU0TO1_A_MARK,
2455 };
2456 static const unsigned int tpu_to2_a_pins[] = {
2457 	/* TPU0TO2_A */
2458 	RCAR_GP_PIN(2, 0),
2459 };
2460 static const unsigned int tpu_to2_a_mux[] = {
2461 	TPU0TO2_A_MARK,
2462 };
2463 static const unsigned int tpu_to3_a_pins[] = {
2464 	/* TPU0TO3_A */
2465 	RCAR_GP_PIN(2, 1),
2466 };
2467 static const unsigned int tpu_to3_a_mux[] = {
2468 	TPU0TO3_A_MARK,
2469 };
2470 
2471 /* - TSN0 ------------------------------------------------ */
2472 static const unsigned int tsn0_link_pins[] = {
2473 	/* TSN0_LINK */
2474 	RCAR_GP_PIN(4, 4),
2475 };
2476 static const unsigned int tsn0_link_mux[] = {
2477 	TSN0_LINK_MARK,
2478 };
2479 static const unsigned int tsn0_phy_int_pins[] = {
2480 	/* TSN0_PHY_INT */
2481 	RCAR_GP_PIN(4, 3),
2482 };
2483 static const unsigned int tsn0_phy_int_mux[] = {
2484 	TSN0_PHY_INT_MARK,
2485 };
2486 static const unsigned int tsn0_mdio_pins[] = {
2487 	/* TSN0_MDC, TSN0_MDIO */
2488 	RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
2489 };
2490 static const unsigned int tsn0_mdio_mux[] = {
2491 	TSN0_MDC_MARK, TSN0_MDIO_MARK,
2492 };
2493 static const unsigned int tsn0_rgmii_pins[] = {
2494 	/*
2495 	 * TSN0_TX_CTL, TSN0_TXC, TSN0_TD0, TSN0_TD1, TSN0_TD2, TSN0_TD3,
2496 	 * TSN0_RX_CTL, TSN0_RXC, TSN0_RD0, TSN0_RD1, TSN0_RD2, TSN0_RD3,
2497 	 */
2498 	RCAR_GP_PIN(4,  9), RCAR_GP_PIN(4, 12),
2499 	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14),
2500 	RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
2501 	RCAR_GP_PIN(4,  7), RCAR_GP_PIN(4, 11),
2502 	RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 13),
2503 	RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
2504 };
2505 static const unsigned int tsn0_rgmii_mux[] = {
2506 	TSN0_TX_CTL_MARK,	TSN0_TXC_MARK,
2507 	TSN0_TD0_MARK,		TSN0_TD1_MARK,
2508 	TSN0_TD2_MARK,		TSN0_TD3_MARK,
2509 	TSN0_RX_CTL_MARK,	TSN0_RXC_MARK,
2510 	TSN0_RD0_MARK,		TSN0_RD1_MARK,
2511 	TSN0_RD2_MARK,		TSN0_RD3_MARK,
2512 };
2513 static const unsigned int tsn0_txcrefclk_pins[] = {
2514 	/* TSN0_TXCREFCLK */
2515 	RCAR_GP_PIN(4, 20),
2516 };
2517 static const unsigned int tsn0_txcrefclk_mux[] = {
2518 	TSN0_TXCREFCLK_MARK,
2519 };
2520 static const unsigned int tsn0_avtp_pps_pins[] = {
2521 	/* TSN0_AVTP_PPS0, TSN0_AVTP_PPS1 */
2522 	RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 2),
2523 };
2524 static const unsigned int tsn0_avtp_pps_mux[] = {
2525 	TSN0_AVTP_PPS0_MARK, TSN0_AVTP_PPS1_MARK,
2526 };
2527 static const unsigned int tsn0_avtp_capture_pins[] = {
2528 	/* TSN0_AVTP_CAPTURE */
2529 	RCAR_GP_PIN(4, 6),
2530 };
2531 static const unsigned int tsn0_avtp_capture_mux[] = {
2532 	TSN0_AVTP_CAPTURE_MARK,
2533 };
2534 static const unsigned int tsn0_avtp_match_pins[] = {
2535 	/* TSN0_AVTP_MATCH */
2536 	RCAR_GP_PIN(4, 5),
2537 };
2538 static const unsigned int tsn0_avtp_match_mux[] = {
2539 	TSN0_AVTP_MATCH_MARK,
2540 };
2541 
2542 static const struct sh_pfc_pin_group pinmux_groups[] = {
2543 	SH_PFC_PIN_GROUP(audio_clkin),
2544 	SH_PFC_PIN_GROUP(audio_clkout),
2545 
2546 	SH_PFC_PIN_GROUP(avb0_link),
2547 	SH_PFC_PIN_GROUP(avb0_magic),
2548 	SH_PFC_PIN_GROUP(avb0_phy_int),
2549 	SH_PFC_PIN_GROUP(avb0_mdio),
2550 	SH_PFC_PIN_GROUP(avb0_rgmii),
2551 	SH_PFC_PIN_GROUP(avb0_txcrefclk),
2552 	SH_PFC_PIN_GROUP(avb0_avtp_pps),
2553 	SH_PFC_PIN_GROUP(avb0_avtp_capture),
2554 	SH_PFC_PIN_GROUP(avb0_avtp_match),
2555 
2556 	SH_PFC_PIN_GROUP(avb1_link),
2557 	SH_PFC_PIN_GROUP(avb1_magic),
2558 	SH_PFC_PIN_GROUP(avb1_phy_int),
2559 	SH_PFC_PIN_GROUP(avb1_mdio),
2560 	SH_PFC_PIN_GROUP(avb1_rgmii),
2561 	SH_PFC_PIN_GROUP(avb1_txcrefclk),
2562 	SH_PFC_PIN_GROUP(avb1_avtp_pps),
2563 	SH_PFC_PIN_GROUP(avb1_avtp_capture),
2564 	SH_PFC_PIN_GROUP(avb1_avtp_match),
2565 
2566 	SH_PFC_PIN_GROUP(avb2_link),
2567 	SH_PFC_PIN_GROUP(avb2_magic),
2568 	SH_PFC_PIN_GROUP(avb2_phy_int),
2569 	SH_PFC_PIN_GROUP(avb2_mdio),
2570 	SH_PFC_PIN_GROUP(avb2_rgmii),
2571 	SH_PFC_PIN_GROUP(avb2_txcrefclk),
2572 	SH_PFC_PIN_GROUP(avb2_avtp_pps),
2573 	SH_PFC_PIN_GROUP(avb2_avtp_capture),
2574 	SH_PFC_PIN_GROUP(avb2_avtp_match),
2575 
2576 	SH_PFC_PIN_GROUP(canfd0_data),
2577 	SH_PFC_PIN_GROUP(canfd1_data),
2578 	SH_PFC_PIN_GROUP(canfd2_data),
2579 	SH_PFC_PIN_GROUP(canfd3_data),
2580 	SH_PFC_PIN_GROUP(canfd4_data),
2581 	SH_PFC_PIN_GROUP(canfd5_data),		/* suffix might be updated */
2582 	SH_PFC_PIN_GROUP(canfd5_data_b),	/* suffix might be updated */
2583 	SH_PFC_PIN_GROUP(canfd6_data),
2584 	SH_PFC_PIN_GROUP(canfd7_data),
2585 	SH_PFC_PIN_GROUP(can_clk),
2586 
2587 	SH_PFC_PIN_GROUP(hscif0_data),
2588 	SH_PFC_PIN_GROUP(hscif0_clk),
2589 	SH_PFC_PIN_GROUP(hscif0_ctrl),
2590 	SH_PFC_PIN_GROUP(hscif1_data),		/* suffix might be updated */
2591 	SH_PFC_PIN_GROUP(hscif1_clk),		/* suffix might be updated */
2592 	SH_PFC_PIN_GROUP(hscif1_ctrl),		/* suffix might be updated */
2593 	SH_PFC_PIN_GROUP(hscif1_data_x),	/* suffix might be updated */
2594 	SH_PFC_PIN_GROUP(hscif1_clk_x),		/* suffix might be updated */
2595 	SH_PFC_PIN_GROUP(hscif1_ctrl_x),	/* suffix might be updated */
2596 	SH_PFC_PIN_GROUP(hscif2_data),
2597 	SH_PFC_PIN_GROUP(hscif2_clk),
2598 	SH_PFC_PIN_GROUP(hscif2_ctrl),
2599 	SH_PFC_PIN_GROUP(hscif3_data),		/* suffix might be updated */
2600 	SH_PFC_PIN_GROUP(hscif3_clk),		/* suffix might be updated */
2601 	SH_PFC_PIN_GROUP(hscif3_ctrl),		/* suffix might be updated */
2602 	SH_PFC_PIN_GROUP(hscif3_data_a),	/* suffix might be updated */
2603 	SH_PFC_PIN_GROUP(hscif3_clk_a),		/* suffix might be updated */
2604 	SH_PFC_PIN_GROUP(hscif3_ctrl_a),	/* suffix might be updated */
2605 
2606 	SH_PFC_PIN_GROUP(i2c0),
2607 	SH_PFC_PIN_GROUP(i2c1),
2608 	SH_PFC_PIN_GROUP(i2c2),
2609 	SH_PFC_PIN_GROUP(i2c3),
2610 	SH_PFC_PIN_GROUP(i2c4),
2611 	SH_PFC_PIN_GROUP(i2c5),
2612 
2613 	BUS_DATA_PIN_GROUP(mmc_data, 1),
2614 	BUS_DATA_PIN_GROUP(mmc_data, 4),
2615 	BUS_DATA_PIN_GROUP(mmc_data, 8),
2616 	SH_PFC_PIN_GROUP(mmc_ctrl),
2617 	SH_PFC_PIN_GROUP(mmc_cd),
2618 	SH_PFC_PIN_GROUP(mmc_wp),
2619 	SH_PFC_PIN_GROUP(mmc_ds),
2620 
2621 	SH_PFC_PIN_GROUP(msiof0_clk),
2622 	SH_PFC_PIN_GROUP(msiof0_sync),
2623 	SH_PFC_PIN_GROUP(msiof0_ss1),
2624 	SH_PFC_PIN_GROUP(msiof0_ss2),
2625 	SH_PFC_PIN_GROUP(msiof0_txd),
2626 	SH_PFC_PIN_GROUP(msiof0_rxd),
2627 
2628 	SH_PFC_PIN_GROUP(msiof1_clk),
2629 	SH_PFC_PIN_GROUP(msiof1_sync),
2630 	SH_PFC_PIN_GROUP(msiof1_ss1),
2631 	SH_PFC_PIN_GROUP(msiof1_ss2),
2632 	SH_PFC_PIN_GROUP(msiof1_txd),
2633 	SH_PFC_PIN_GROUP(msiof1_rxd),
2634 
2635 	SH_PFC_PIN_GROUP(msiof2_clk),
2636 	SH_PFC_PIN_GROUP(msiof2_sync),
2637 	SH_PFC_PIN_GROUP(msiof2_ss1),
2638 	SH_PFC_PIN_GROUP(msiof2_ss2),
2639 	SH_PFC_PIN_GROUP(msiof2_txd),
2640 	SH_PFC_PIN_GROUP(msiof2_rxd),
2641 
2642 	SH_PFC_PIN_GROUP(msiof3_clk),
2643 	SH_PFC_PIN_GROUP(msiof3_sync),
2644 	SH_PFC_PIN_GROUP(msiof3_ss1),
2645 	SH_PFC_PIN_GROUP(msiof3_ss2),
2646 	SH_PFC_PIN_GROUP(msiof3_txd),
2647 	SH_PFC_PIN_GROUP(msiof3_rxd),
2648 
2649 	SH_PFC_PIN_GROUP(msiof4_clk),
2650 	SH_PFC_PIN_GROUP(msiof4_sync),
2651 	SH_PFC_PIN_GROUP(msiof4_ss1),
2652 	SH_PFC_PIN_GROUP(msiof4_ss2),
2653 	SH_PFC_PIN_GROUP(msiof4_txd),
2654 	SH_PFC_PIN_GROUP(msiof4_rxd),
2655 
2656 	SH_PFC_PIN_GROUP(msiof5_clk),
2657 	SH_PFC_PIN_GROUP(msiof5_sync),
2658 	SH_PFC_PIN_GROUP(msiof5_ss1),
2659 	SH_PFC_PIN_GROUP(msiof5_ss2),
2660 	SH_PFC_PIN_GROUP(msiof5_txd),
2661 	SH_PFC_PIN_GROUP(msiof5_rxd),
2662 
2663 	SH_PFC_PIN_GROUP(pcie0_clkreq_n),
2664 	SH_PFC_PIN_GROUP(pcie1_clkreq_n),
2665 
2666 	SH_PFC_PIN_GROUP(pwm0_a),		/* suffix might be updated */
2667 	SH_PFC_PIN_GROUP(pwm1_a),
2668 	SH_PFC_PIN_GROUP(pwm1_b),
2669 	SH_PFC_PIN_GROUP(pwm2_b),		/* suffix might be updated */
2670 	SH_PFC_PIN_GROUP(pwm3_a),
2671 	SH_PFC_PIN_GROUP(pwm3_b),
2672 	SH_PFC_PIN_GROUP(pwm4),
2673 	SH_PFC_PIN_GROUP(pwm5),
2674 	SH_PFC_PIN_GROUP(pwm6),
2675 	SH_PFC_PIN_GROUP(pwm7),
2676 	SH_PFC_PIN_GROUP(pwm8_a),		/* suffix might be updated */
2677 	SH_PFC_PIN_GROUP(pwm9_a),		/* suffix might be updated */
2678 
2679 	SH_PFC_PIN_GROUP(qspi0_ctrl),
2680 	BUS_DATA_PIN_GROUP(qspi0_data, 2),
2681 	BUS_DATA_PIN_GROUP(qspi0_data, 4),
2682 	SH_PFC_PIN_GROUP(qspi1_ctrl),
2683 	BUS_DATA_PIN_GROUP(qspi1_data, 2),
2684 	BUS_DATA_PIN_GROUP(qspi1_data, 4),
2685 
2686 	SH_PFC_PIN_GROUP(scif0_data),
2687 	SH_PFC_PIN_GROUP(scif0_clk),
2688 	SH_PFC_PIN_GROUP(scif0_ctrl),
2689 	SH_PFC_PIN_GROUP(scif1_data),		/* suffix might be updated */
2690 	SH_PFC_PIN_GROUP(scif1_clk),		/* suffix might be updated */
2691 	SH_PFC_PIN_GROUP(scif1_ctrl),		/* suffix might be updated */
2692 	SH_PFC_PIN_GROUP(scif1_data_x),		/* suffix might be updated */
2693 	SH_PFC_PIN_GROUP(scif1_clk_x),		/* suffix might be updated */
2694 	SH_PFC_PIN_GROUP(scif1_ctrl_x),		/* suffix might be updated */
2695 	SH_PFC_PIN_GROUP(scif3_data),		/* suffix might be updated */
2696 	SH_PFC_PIN_GROUP(scif3_clk),		/* suffix might be updated */
2697 	SH_PFC_PIN_GROUP(scif3_ctrl),		/* suffix might be updated */
2698 	SH_PFC_PIN_GROUP(scif3_data_a),		/* suffix might be updated */
2699 	SH_PFC_PIN_GROUP(scif3_clk_a),		/* suffix might be updated */
2700 	SH_PFC_PIN_GROUP(scif3_ctrl_a),		/* suffix might be updated */
2701 	SH_PFC_PIN_GROUP(scif4_data),
2702 	SH_PFC_PIN_GROUP(scif4_clk),
2703 	SH_PFC_PIN_GROUP(scif4_ctrl),
2704 	SH_PFC_PIN_GROUP(scif_clk),
2705 	SH_PFC_PIN_GROUP(scif_clk2),
2706 
2707 	SH_PFC_PIN_GROUP(ssi_data),
2708 	SH_PFC_PIN_GROUP(ssi_ctrl),
2709 
2710 	SH_PFC_PIN_GROUP(tpu_to0),		/* suffix might be updated */
2711 	SH_PFC_PIN_GROUP(tpu_to0_a),		/* suffix might be updated */
2712 	SH_PFC_PIN_GROUP(tpu_to1),		/* suffix might be updated */
2713 	SH_PFC_PIN_GROUP(tpu_to1_a),		/* suffix might be updated */
2714 	SH_PFC_PIN_GROUP(tpu_to2),		/* suffix might be updated */
2715 	SH_PFC_PIN_GROUP(tpu_to2_a),		/* suffix might be updated */
2716 	SH_PFC_PIN_GROUP(tpu_to3),		/* suffix might be updated */
2717 	SH_PFC_PIN_GROUP(tpu_to3_a),		/* suffix might be updated */
2718 
2719 	SH_PFC_PIN_GROUP(tsn0_link),
2720 	SH_PFC_PIN_GROUP(tsn0_phy_int),
2721 	SH_PFC_PIN_GROUP(tsn0_mdio),
2722 	SH_PFC_PIN_GROUP(tsn0_rgmii),
2723 	SH_PFC_PIN_GROUP(tsn0_txcrefclk),
2724 	SH_PFC_PIN_GROUP(tsn0_avtp_pps),
2725 	SH_PFC_PIN_GROUP(tsn0_avtp_capture),
2726 	SH_PFC_PIN_GROUP(tsn0_avtp_match),
2727 };
2728 
2729 static const char * const audio_clk_groups[] = {
2730 	"audio_clkin",
2731 	"audio_clkout",
2732 };
2733 
2734 static const char * const avb0_groups[] = {
2735 	"avb0_link",
2736 	"avb0_magic",
2737 	"avb0_phy_int",
2738 	"avb0_mdio",
2739 	"avb0_rgmii",
2740 	"avb0_txcrefclk",
2741 	"avb0_avtp_pps",
2742 	"avb0_avtp_capture",
2743 	"avb0_avtp_match",
2744 };
2745 
2746 static const char * const avb1_groups[] = {
2747 	"avb1_link",
2748 	"avb1_magic",
2749 	"avb1_phy_int",
2750 	"avb1_mdio",
2751 	"avb1_rgmii",
2752 	"avb1_txcrefclk",
2753 	"avb1_avtp_pps",
2754 	"avb1_avtp_capture",
2755 	"avb1_avtp_match",
2756 };
2757 
2758 static const char * const avb2_groups[] = {
2759 	"avb2_link",
2760 	"avb2_magic",
2761 	"avb2_phy_int",
2762 	"avb2_mdio",
2763 	"avb2_rgmii",
2764 	"avb2_txcrefclk",
2765 	"avb2_avtp_pps",
2766 	"avb2_avtp_capture",
2767 	"avb2_avtp_match",
2768 };
2769 
2770 static const char * const canfd0_groups[] = {
2771 	"canfd0_data",
2772 };
2773 
2774 static const char * const canfd1_groups[] = {
2775 	"canfd1_data",
2776 };
2777 
2778 static const char * const canfd2_groups[] = {
2779 	"canfd2_data",
2780 };
2781 
2782 static const char * const canfd3_groups[] = {
2783 	"canfd3_data",
2784 };
2785 
2786 static const char * const canfd4_groups[] = {
2787 	"canfd4_data",
2788 };
2789 
2790 static const char * const canfd5_groups[] = {
2791 	/* suffix might be updated */
2792 	"canfd5_data",
2793 	"canfd5_data_b",
2794 };
2795 
2796 static const char * const canfd6_groups[] = {
2797 	"canfd6_data",
2798 };
2799 
2800 static const char * const canfd7_groups[] = {
2801 	"canfd7_data",
2802 };
2803 
2804 static const char * const can_clk_groups[] = {
2805 	"can_clk",
2806 };
2807 
2808 static const char * const hscif0_groups[] = {
2809 	"hscif0_data",
2810 	"hscif0_clk",
2811 	"hscif0_ctrl",
2812 };
2813 
2814 static const char * const hscif1_groups[] = {
2815 	/* suffix might be updated */
2816 	"hscif1_data",
2817 	"hscif1_clk",
2818 	"hscif1_ctrl",
2819 	"hscif1_data_x",
2820 	"hscif1_clk_x",
2821 	"hscif1_ctrl_x",
2822 };
2823 
2824 static const char * const hscif2_groups[] = {
2825 	"hscif2_data",
2826 	"hscif2_clk",
2827 	"hscif2_ctrl",
2828 };
2829 
2830 static const char * const hscif3_groups[] = {
2831 	/* suffix might be updated */
2832 	"hscif3_data",
2833 	"hscif3_clk",
2834 	"hscif3_ctrl",
2835 	"hscif3_data_a",
2836 	"hscif3_clk_a",
2837 	"hscif3_ctrl_a",
2838 };
2839 
2840 static const char * const i2c0_groups[] = {
2841 	"i2c0",
2842 };
2843 
2844 static const char * const i2c1_groups[] = {
2845 	"i2c1",
2846 };
2847 
2848 static const char * const i2c2_groups[] = {
2849 	"i2c2",
2850 };
2851 
2852 static const char * const i2c3_groups[] = {
2853 	"i2c3",
2854 };
2855 
2856 static const char * const i2c4_groups[] = {
2857 	"i2c4",
2858 };
2859 
2860 static const char * const i2c5_groups[] = {
2861 	"i2c5",
2862 };
2863 
2864 static const char * const mmc_groups[] = {
2865 	"mmc_data1",
2866 	"mmc_data4",
2867 	"mmc_data8",
2868 	"mmc_ctrl",
2869 	"mmc_cd",
2870 	"mmc_wp",
2871 	"mmc_ds",
2872 };
2873 
2874 static const char * const msiof0_groups[] = {
2875 	"msiof0_clk",
2876 	"msiof0_sync",
2877 	"msiof0_ss1",
2878 	"msiof0_ss2",
2879 	"msiof0_txd",
2880 	"msiof0_rxd",
2881 };
2882 
2883 static const char * const msiof1_groups[] = {
2884 	"msiof1_clk",
2885 	"msiof1_sync",
2886 	"msiof1_ss1",
2887 	"msiof1_ss2",
2888 	"msiof1_txd",
2889 	"msiof1_rxd",
2890 };
2891 
2892 static const char * const msiof2_groups[] = {
2893 	"msiof2_clk",
2894 	"msiof2_sync",
2895 	"msiof2_ss1",
2896 	"msiof2_ss2",
2897 	"msiof2_txd",
2898 	"msiof2_rxd",
2899 };
2900 
2901 static const char * const msiof3_groups[] = {
2902 	"msiof3_clk",
2903 	"msiof3_sync",
2904 	"msiof3_ss1",
2905 	"msiof3_ss2",
2906 	"msiof3_txd",
2907 	"msiof3_rxd",
2908 };
2909 
2910 static const char * const msiof4_groups[] = {
2911 	"msiof4_clk",
2912 	"msiof4_sync",
2913 	"msiof4_ss1",
2914 	"msiof4_ss2",
2915 	"msiof4_txd",
2916 	"msiof4_rxd",
2917 };
2918 
2919 static const char * const msiof5_groups[] = {
2920 	"msiof5_clk",
2921 	"msiof5_sync",
2922 	"msiof5_ss1",
2923 	"msiof5_ss2",
2924 	"msiof5_txd",
2925 	"msiof5_rxd",
2926 };
2927 
2928 static const char * const pcie_groups[] = {
2929 	"pcie0_clkreq_n",
2930 	"pcie1_clkreq_n",
2931 };
2932 
2933 static const char * const pwm0_groups[] = {
2934 	/* suffix might be updated */
2935 	"pwm0_a",
2936 };
2937 
2938 static const char * const pwm1_groups[] = {
2939 	"pwm1_a",
2940 	"pwm1_b",
2941 };
2942 
2943 static const char * const pwm2_groups[] = {
2944 	/* suffix might be updated */
2945 	"pwm2_b",
2946 };
2947 
2948 static const char * const pwm3_groups[] = {
2949 	"pwm3_a",
2950 	"pwm3_b",
2951 };
2952 
2953 static const char * const pwm4_groups[] = {
2954 	"pwm4",
2955 };
2956 
2957 static const char * const pwm5_groups[] = {
2958 	"pwm5",
2959 };
2960 
2961 static const char * const pwm6_groups[] = {
2962 	"pwm6",
2963 };
2964 
2965 static const char * const pwm7_groups[] = {
2966 	"pwm7",
2967 };
2968 
2969 static const char * const pwm8_groups[] = {
2970 	/* suffix might be updated */
2971 	"pwm8_a",
2972 };
2973 
2974 static const char * const pwm9_groups[] = {
2975 	/* suffix might be updated */
2976 	"pwm9_a",
2977 };
2978 
2979 static const char * const qspi0_groups[] = {
2980 	"qspi0_ctrl",
2981 	"qspi0_data2",
2982 	"qspi0_data4",
2983 };
2984 
2985 static const char * const qspi1_groups[] = {
2986 	"qspi1_ctrl",
2987 	"qspi1_data2",
2988 	"qspi1_data4",
2989 };
2990 
2991 static const char * const scif0_groups[] = {
2992 	"scif0_data",
2993 	"scif0_clk",
2994 	"scif0_ctrl",
2995 };
2996 
2997 static const char * const scif1_groups[] = {
2998 	/* suffix might be updated */
2999 	"scif1_data",
3000 	"scif1_clk",
3001 	"scif1_ctrl",
3002 	"scif1_data_x",
3003 	"scif1_clk_x",
3004 	"scif1_ctrl_x",
3005 };
3006 
3007 static const char * const scif3_groups[] = {
3008 	/* suffix might be updated */
3009 	"scif3_data",
3010 	"scif3_clk",
3011 	"scif3_ctrl",
3012 	"scif3_data_a",
3013 	"scif3_clk_a",
3014 	"scif3_ctrl_a",
3015 };
3016 
3017 static const char * const scif4_groups[] = {
3018 	"scif4_data",
3019 	"scif4_clk",
3020 	"scif4_ctrl",
3021 };
3022 
3023 static const char * const scif_clk_groups[] = {
3024 	"scif_clk",
3025 };
3026 
3027 static const char * const scif_clk2_groups[] = {
3028 	"scif_clk2",
3029 };
3030 
3031 static const char * const ssi_groups[] = {
3032 	"ssi_data",
3033 	"ssi_ctrl",
3034 };
3035 
3036 static const char * const tpu_groups[] = {
3037 	/* suffix might be updated */
3038 	"tpu_to0",
3039 	"tpu_to0_a",
3040 	"tpu_to1",
3041 	"tpu_to1_a",
3042 	"tpu_to2",
3043 	"tpu_to2_a",
3044 	"tpu_to3",
3045 	"tpu_to3_a",
3046 };
3047 
3048 static const char * const tsn0_groups[] = {
3049 	"tsn0_link",
3050 	"tsn0_phy_int",
3051 	"tsn0_mdio",
3052 	"tsn0_rgmii",
3053 	"tsn0_txcrefclk",
3054 	"tsn0_avtp_pps",
3055 	"tsn0_avtp_capture",
3056 	"tsn0_avtp_match",
3057 };
3058 
3059 static const struct sh_pfc_function pinmux_functions[] = {
3060 	SH_PFC_FUNCTION(audio_clk),
3061 
3062 	SH_PFC_FUNCTION(avb0),
3063 	SH_PFC_FUNCTION(avb1),
3064 	SH_PFC_FUNCTION(avb2),
3065 
3066 	SH_PFC_FUNCTION(canfd0),
3067 	SH_PFC_FUNCTION(canfd1),
3068 	SH_PFC_FUNCTION(canfd2),
3069 	SH_PFC_FUNCTION(canfd3),
3070 	SH_PFC_FUNCTION(canfd4),
3071 	SH_PFC_FUNCTION(canfd5),
3072 	SH_PFC_FUNCTION(canfd6),
3073 	SH_PFC_FUNCTION(canfd7),
3074 	SH_PFC_FUNCTION(can_clk),
3075 
3076 	SH_PFC_FUNCTION(hscif0),
3077 	SH_PFC_FUNCTION(hscif1),
3078 	SH_PFC_FUNCTION(hscif2),
3079 	SH_PFC_FUNCTION(hscif3),
3080 
3081 	SH_PFC_FUNCTION(i2c0),
3082 	SH_PFC_FUNCTION(i2c1),
3083 	SH_PFC_FUNCTION(i2c2),
3084 	SH_PFC_FUNCTION(i2c3),
3085 	SH_PFC_FUNCTION(i2c4),
3086 	SH_PFC_FUNCTION(i2c5),
3087 
3088 	SH_PFC_FUNCTION(mmc),
3089 
3090 	SH_PFC_FUNCTION(msiof0),
3091 	SH_PFC_FUNCTION(msiof1),
3092 	SH_PFC_FUNCTION(msiof2),
3093 	SH_PFC_FUNCTION(msiof3),
3094 	SH_PFC_FUNCTION(msiof4),
3095 	SH_PFC_FUNCTION(msiof5),
3096 
3097 	SH_PFC_FUNCTION(pcie),
3098 
3099 	SH_PFC_FUNCTION(pwm0),
3100 	SH_PFC_FUNCTION(pwm1),
3101 	SH_PFC_FUNCTION(pwm2),
3102 	SH_PFC_FUNCTION(pwm3),
3103 	SH_PFC_FUNCTION(pwm4),
3104 	SH_PFC_FUNCTION(pwm5),
3105 	SH_PFC_FUNCTION(pwm6),
3106 	SH_PFC_FUNCTION(pwm7),
3107 	SH_PFC_FUNCTION(pwm8),
3108 	SH_PFC_FUNCTION(pwm9),
3109 
3110 	SH_PFC_FUNCTION(qspi0),
3111 	SH_PFC_FUNCTION(qspi1),
3112 
3113 	SH_PFC_FUNCTION(scif0),
3114 	SH_PFC_FUNCTION(scif1),
3115 	SH_PFC_FUNCTION(scif3),
3116 	SH_PFC_FUNCTION(scif4),
3117 	SH_PFC_FUNCTION(scif_clk),
3118 	SH_PFC_FUNCTION(scif_clk2),
3119 
3120 	SH_PFC_FUNCTION(ssi),
3121 
3122 	SH_PFC_FUNCTION(tpu),
3123 
3124 	SH_PFC_FUNCTION(tsn0),
3125 };
3126 
3127 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3128 #define F_(x, y)	FN_##y
3129 #define FM(x)		FN_##x
3130 	{ PINMUX_CFG_REG_VAR("GPSR0", 0xE6050040, 32,
3131 			     GROUP(-13, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3132 				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3133 			     GROUP(
3134 		/* GP0_31_19 RESERVED */
3135 		GP_0_18_FN,	GPSR0_18,
3136 		GP_0_17_FN,	GPSR0_17,
3137 		GP_0_16_FN,	GPSR0_16,
3138 		GP_0_15_FN,	GPSR0_15,
3139 		GP_0_14_FN,	GPSR0_14,
3140 		GP_0_13_FN,	GPSR0_13,
3141 		GP_0_12_FN,	GPSR0_12,
3142 		GP_0_11_FN,	GPSR0_11,
3143 		GP_0_10_FN,	GPSR0_10,
3144 		GP_0_9_FN,	GPSR0_9,
3145 		GP_0_8_FN,	GPSR0_8,
3146 		GP_0_7_FN,	GPSR0_7,
3147 		GP_0_6_FN,	GPSR0_6,
3148 		GP_0_5_FN,	GPSR0_5,
3149 		GP_0_4_FN,	GPSR0_4,
3150 		GP_0_3_FN,	GPSR0_3,
3151 		GP_0_2_FN,	GPSR0_2,
3152 		GP_0_1_FN,	GPSR0_1,
3153 		GP_0_0_FN,	GPSR0_0, ))
3154 	},
3155 	{ PINMUX_CFG_REG("GPSR1", 0xE6050840, 32, 1, GROUP(
3156 		0, 0,
3157 		0, 0,
3158 		0, 0,
3159 		GP_1_28_FN,	GPSR1_28,
3160 		GP_1_27_FN,	GPSR1_27,
3161 		GP_1_26_FN,	GPSR1_26,
3162 		GP_1_25_FN,	GPSR1_25,
3163 		GP_1_24_FN,	GPSR1_24,
3164 		GP_1_23_FN,	GPSR1_23,
3165 		GP_1_22_FN,	GPSR1_22,
3166 		GP_1_21_FN,	GPSR1_21,
3167 		GP_1_20_FN,	GPSR1_20,
3168 		GP_1_19_FN,	GPSR1_19,
3169 		GP_1_18_FN,	GPSR1_18,
3170 		GP_1_17_FN,	GPSR1_17,
3171 		GP_1_16_FN,	GPSR1_16,
3172 		GP_1_15_FN,	GPSR1_15,
3173 		GP_1_14_FN,	GPSR1_14,
3174 		GP_1_13_FN,	GPSR1_13,
3175 		GP_1_12_FN,	GPSR1_12,
3176 		GP_1_11_FN,	GPSR1_11,
3177 		GP_1_10_FN,	GPSR1_10,
3178 		GP_1_9_FN,	GPSR1_9,
3179 		GP_1_8_FN,	GPSR1_8,
3180 		GP_1_7_FN,	GPSR1_7,
3181 		GP_1_6_FN,	GPSR1_6,
3182 		GP_1_5_FN,	GPSR1_5,
3183 		GP_1_4_FN,	GPSR1_4,
3184 		GP_1_3_FN,	GPSR1_3,
3185 		GP_1_2_FN,	GPSR1_2,
3186 		GP_1_1_FN,	GPSR1_1,
3187 		GP_1_0_FN,	GPSR1_0, ))
3188 	},
3189 	{ PINMUX_CFG_REG_VAR("GPSR2", 0xE6058040, 32,
3190 			     GROUP(-12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3191 				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3192 			     GROUP(
3193 		/* GP2_31_20 RESERVED */
3194 		GP_2_19_FN,	GPSR2_19,
3195 		GP_2_18_FN,	GPSR2_18,
3196 		GP_2_17_FN,	GPSR2_17,
3197 		GP_2_16_FN,	GPSR2_16,
3198 		GP_2_15_FN,	GPSR2_15,
3199 		GP_2_14_FN,	GPSR2_14,
3200 		GP_2_13_FN,	GPSR2_13,
3201 		GP_2_12_FN,	GPSR2_12,
3202 		GP_2_11_FN,	GPSR2_11,
3203 		GP_2_10_FN,	GPSR2_10,
3204 		GP_2_9_FN,	GPSR2_9,
3205 		GP_2_8_FN,	GPSR2_8,
3206 		GP_2_7_FN,	GPSR2_7,
3207 		GP_2_6_FN,	GPSR2_6,
3208 		GP_2_5_FN,	GPSR2_5,
3209 		GP_2_4_FN,	GPSR2_4,
3210 		GP_2_3_FN,	GPSR2_3,
3211 		GP_2_2_FN,	GPSR2_2,
3212 		GP_2_1_FN,	GPSR2_1,
3213 		GP_2_0_FN,	GPSR2_0, ))
3214 	},
3215 	{ PINMUX_CFG_REG("GPSR3", 0xE6058840, 32, 1, GROUP(
3216 		0, 0,
3217 		0, 0,
3218 		GP_3_29_FN,	GPSR3_29,
3219 		GP_3_28_FN,	GPSR3_28,
3220 		GP_3_27_FN,	GPSR3_27,
3221 		GP_3_26_FN,	GPSR3_26,
3222 		GP_3_25_FN,	GPSR3_25,
3223 		GP_3_24_FN,	GPSR3_24,
3224 		GP_3_23_FN,	GPSR3_23,
3225 		GP_3_22_FN,	GPSR3_22,
3226 		GP_3_21_FN,	GPSR3_21,
3227 		GP_3_20_FN,	GPSR3_20,
3228 		GP_3_19_FN,	GPSR3_19,
3229 		GP_3_18_FN,	GPSR3_18,
3230 		GP_3_17_FN,	GPSR3_17,
3231 		GP_3_16_FN,	GPSR3_16,
3232 		GP_3_15_FN,	GPSR3_15,
3233 		GP_3_14_FN,	GPSR3_14,
3234 		GP_3_13_FN,	GPSR3_13,
3235 		GP_3_12_FN,	GPSR3_12,
3236 		GP_3_11_FN,	GPSR3_11,
3237 		GP_3_10_FN,	GPSR3_10,
3238 		GP_3_9_FN,	GPSR3_9,
3239 		GP_3_8_FN,	GPSR3_8,
3240 		GP_3_7_FN,	GPSR3_7,
3241 		GP_3_6_FN,	GPSR3_6,
3242 		GP_3_5_FN,	GPSR3_5,
3243 		GP_3_4_FN,	GPSR3_4,
3244 		GP_3_3_FN,	GPSR3_3,
3245 		GP_3_2_FN,	GPSR3_2,
3246 		GP_3_1_FN,	GPSR3_1,
3247 		GP_3_0_FN,	GPSR3_0, ))
3248 	},
3249 	{ PINMUX_CFG_REG("GPSR4", 0xE6060040, 32, 1, GROUP(
3250 		0, 0,
3251 		0, 0,
3252 		0, 0,
3253 		0, 0,
3254 		0, 0,
3255 		0, 0,
3256 		0, 0,
3257 		GP_4_24_FN,	GPSR4_24,
3258 		GP_4_23_FN,	GPSR4_23,
3259 		GP_4_22_FN,	GPSR4_22,
3260 		GP_4_21_FN,	GPSR4_21,
3261 		GP_4_20_FN,	GPSR4_20,
3262 		GP_4_19_FN,	GPSR4_19,
3263 		GP_4_18_FN,	GPSR4_18,
3264 		GP_4_17_FN,	GPSR4_17,
3265 		GP_4_16_FN,	GPSR4_16,
3266 		GP_4_15_FN,	GPSR4_15,
3267 		GP_4_14_FN,	GPSR4_14,
3268 		GP_4_13_FN,	GPSR4_13,
3269 		GP_4_12_FN,	GPSR4_12,
3270 		GP_4_11_FN,	GPSR4_11,
3271 		GP_4_10_FN,	GPSR4_10,
3272 		GP_4_9_FN,	GPSR4_9,
3273 		GP_4_8_FN,	GPSR4_8,
3274 		GP_4_7_FN,	GPSR4_7,
3275 		GP_4_6_FN,	GPSR4_6,
3276 		GP_4_5_FN,	GPSR4_5,
3277 		GP_4_4_FN,	GPSR4_4,
3278 		GP_4_3_FN,	GPSR4_3,
3279 		GP_4_2_FN,	GPSR4_2,
3280 		GP_4_1_FN,	GPSR4_1,
3281 		GP_4_0_FN,	GPSR4_0, ))
3282 	},
3283 	{ PINMUX_CFG_REG_VAR("GPSR5", 0xE6060840, 32,
3284 			     GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3285 				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3286 			     GROUP(
3287 		/* GP5_31_21 RESERVED */
3288 		GP_5_20_FN,	GPSR5_20,
3289 		GP_5_19_FN,	GPSR5_19,
3290 		GP_5_18_FN,	GPSR5_18,
3291 		GP_5_17_FN,	GPSR5_17,
3292 		GP_5_16_FN,	GPSR5_16,
3293 		GP_5_15_FN,	GPSR5_15,
3294 		GP_5_14_FN,	GPSR5_14,
3295 		GP_5_13_FN,	GPSR5_13,
3296 		GP_5_12_FN,	GPSR5_12,
3297 		GP_5_11_FN,	GPSR5_11,
3298 		GP_5_10_FN,	GPSR5_10,
3299 		GP_5_9_FN,	GPSR5_9,
3300 		GP_5_8_FN,	GPSR5_8,
3301 		GP_5_7_FN,	GPSR5_7,
3302 		GP_5_6_FN,	GPSR5_6,
3303 		GP_5_5_FN,	GPSR5_5,
3304 		GP_5_4_FN,	GPSR5_4,
3305 		GP_5_3_FN,	GPSR5_3,
3306 		GP_5_2_FN,	GPSR5_2,
3307 		GP_5_1_FN,	GPSR5_1,
3308 		GP_5_0_FN,	GPSR5_0, ))
3309 	},
3310 	{ PINMUX_CFG_REG_VAR("GPSR6", 0xE6061040, 32,
3311 			     GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3312 				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3313 			     GROUP(
3314 		/* GP6_31_21 RESERVED */
3315 		GP_6_20_FN,	GPSR6_20,
3316 		GP_6_19_FN,	GPSR6_19,
3317 		GP_6_18_FN,	GPSR6_18,
3318 		GP_6_17_FN,	GPSR6_17,
3319 		GP_6_16_FN,	GPSR6_16,
3320 		GP_6_15_FN,	GPSR6_15,
3321 		GP_6_14_FN,	GPSR6_14,
3322 		GP_6_13_FN,	GPSR6_13,
3323 		GP_6_12_FN,	GPSR6_12,
3324 		GP_6_11_FN,	GPSR6_11,
3325 		GP_6_10_FN,	GPSR6_10,
3326 		GP_6_9_FN,	GPSR6_9,
3327 		GP_6_8_FN,	GPSR6_8,
3328 		GP_6_7_FN,	GPSR6_7,
3329 		GP_6_6_FN,	GPSR6_6,
3330 		GP_6_5_FN,	GPSR6_5,
3331 		GP_6_4_FN,	GPSR6_4,
3332 		GP_6_3_FN,	GPSR6_3,
3333 		GP_6_2_FN,	GPSR6_2,
3334 		GP_6_1_FN,	GPSR6_1,
3335 		GP_6_0_FN,	GPSR6_0, ))
3336 	},
3337 	{ PINMUX_CFG_REG_VAR("GPSR7", 0xE6061840, 32,
3338 			     GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3339 				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3340 			     GROUP(
3341 		/* GP7_31_21 RESERVED */
3342 		GP_7_20_FN,	GPSR7_20,
3343 		GP_7_19_FN,	GPSR7_19,
3344 		GP_7_18_FN,	GPSR7_18,
3345 		GP_7_17_FN,	GPSR7_17,
3346 		GP_7_16_FN,	GPSR7_16,
3347 		GP_7_15_FN,	GPSR7_15,
3348 		GP_7_14_FN,	GPSR7_14,
3349 		GP_7_13_FN,	GPSR7_13,
3350 		GP_7_12_FN,	GPSR7_12,
3351 		GP_7_11_FN,	GPSR7_11,
3352 		GP_7_10_FN,	GPSR7_10,
3353 		GP_7_9_FN,	GPSR7_9,
3354 		GP_7_8_FN,	GPSR7_8,
3355 		GP_7_7_FN,	GPSR7_7,
3356 		GP_7_6_FN,	GPSR7_6,
3357 		GP_7_5_FN,	GPSR7_5,
3358 		GP_7_4_FN,	GPSR7_4,
3359 		GP_7_3_FN,	GPSR7_3,
3360 		GP_7_2_FN,	GPSR7_2,
3361 		GP_7_1_FN,	GPSR7_1,
3362 		GP_7_0_FN,	GPSR7_0, ))
3363 	},
3364 	{ PINMUX_CFG_REG_VAR("GPSR8", 0xE6068040, 32,
3365 			     GROUP(-18, 1, 1, 1, 1,
3366 				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3367 			     GROUP(
3368 		/* GP8_31_14 RESERVED */
3369 		GP_8_13_FN,	GPSR8_13,
3370 		GP_8_12_FN,	GPSR8_12,
3371 		GP_8_11_FN,	GPSR8_11,
3372 		GP_8_10_FN,	GPSR8_10,
3373 		GP_8_9_FN,	GPSR8_9,
3374 		GP_8_8_FN,	GPSR8_8,
3375 		GP_8_7_FN,	GPSR8_7,
3376 		GP_8_6_FN,	GPSR8_6,
3377 		GP_8_5_FN,	GPSR8_5,
3378 		GP_8_4_FN,	GPSR8_4,
3379 		GP_8_3_FN,	GPSR8_3,
3380 		GP_8_2_FN,	GPSR8_2,
3381 		GP_8_1_FN,	GPSR8_1,
3382 		GP_8_0_FN,	GPSR8_0, ))
3383 	},
3384 #undef F_
3385 #undef FM
3386 
3387 #define F_(x, y)	x,
3388 #define FM(x)		FN_##x,
3389 	{ PINMUX_CFG_REG("IP0SR0", 0xE6050060, 32, 4, GROUP(
3390 		IP0SR0_31_28
3391 		IP0SR0_27_24
3392 		IP0SR0_23_20
3393 		IP0SR0_19_16
3394 		IP0SR0_15_12
3395 		IP0SR0_11_8
3396 		IP0SR0_7_4
3397 		IP0SR0_3_0))
3398 	},
3399 	{ PINMUX_CFG_REG("IP1SR0", 0xE6050064, 32, 4, GROUP(
3400 		IP1SR0_31_28
3401 		IP1SR0_27_24
3402 		IP1SR0_23_20
3403 		IP1SR0_19_16
3404 		IP1SR0_15_12
3405 		IP1SR0_11_8
3406 		IP1SR0_7_4
3407 		IP1SR0_3_0))
3408 	},
3409 	{ PINMUX_CFG_REG_VAR("IP2SR0", 0xE6050068, 32,
3410 			     GROUP(-20, 4, 4, 4),
3411 			     GROUP(
3412 		/* IP2SR0_31_12 RESERVED */
3413 		IP2SR0_11_8
3414 		IP2SR0_7_4
3415 		IP2SR0_3_0))
3416 	},
3417 	{ PINMUX_CFG_REG("IP0SR1", 0xE6050860, 32, 4, GROUP(
3418 		IP0SR1_31_28
3419 		IP0SR1_27_24
3420 		IP0SR1_23_20
3421 		IP0SR1_19_16
3422 		IP0SR1_15_12
3423 		IP0SR1_11_8
3424 		IP0SR1_7_4
3425 		IP0SR1_3_0))
3426 	},
3427 	{ PINMUX_CFG_REG("IP1SR1", 0xE6050864, 32, 4, GROUP(
3428 		IP1SR1_31_28
3429 		IP1SR1_27_24
3430 		IP1SR1_23_20
3431 		IP1SR1_19_16
3432 		IP1SR1_15_12
3433 		IP1SR1_11_8
3434 		IP1SR1_7_4
3435 		IP1SR1_3_0))
3436 	},
3437 	{ PINMUX_CFG_REG("IP2SR1", 0xE6050868, 32, 4, GROUP(
3438 		IP2SR1_31_28
3439 		IP2SR1_27_24
3440 		IP2SR1_23_20
3441 		IP2SR1_19_16
3442 		IP2SR1_15_12
3443 		IP2SR1_11_8
3444 		IP2SR1_7_4
3445 		IP2SR1_3_0))
3446 	},
3447 	{ PINMUX_CFG_REG_VAR("IP3SR1", 0xE605086C, 32,
3448 			     GROUP(-12, 4, 4, 4, 4, 4),
3449 			     GROUP(
3450 		/* IP3SR1_31_20 RESERVED */
3451 		IP3SR1_19_16
3452 		IP3SR1_15_12
3453 		IP3SR1_11_8
3454 		IP3SR1_7_4
3455 		IP3SR1_3_0))
3456 	},
3457 	{ PINMUX_CFG_REG("IP0SR2", 0xE6058060, 32, 4, GROUP(
3458 		IP0SR2_31_28
3459 		IP0SR2_27_24
3460 		IP0SR2_23_20
3461 		IP0SR2_19_16
3462 		IP0SR2_15_12
3463 		IP0SR2_11_8
3464 		IP0SR2_7_4
3465 		IP0SR2_3_0))
3466 	},
3467 	{ PINMUX_CFG_REG("IP1SR2", 0xE6058064, 32, 4, GROUP(
3468 		IP1SR2_31_28
3469 		IP1SR2_27_24
3470 		IP1SR2_23_20
3471 		IP1SR2_19_16
3472 		IP1SR2_15_12
3473 		IP1SR2_11_8
3474 		IP1SR2_7_4
3475 		IP1SR2_3_0))
3476 	},
3477 	{ PINMUX_CFG_REG_VAR("IP2SR2", 0xE6058068, 32,
3478 			     GROUP(-16, 4, 4, 4, 4),
3479 			     GROUP(
3480 		/* IP2SR2_31_16 RESERVED */
3481 		IP2SR2_15_12
3482 		IP2SR2_11_8
3483 		IP2SR2_7_4
3484 		IP2SR2_3_0))
3485 	},
3486 	{ PINMUX_CFG_REG("IP0SR3", 0xE6058860, 32, 4, GROUP(
3487 		IP0SR3_31_28
3488 		IP0SR3_27_24
3489 		IP0SR3_23_20
3490 		IP0SR3_19_16
3491 		IP0SR3_15_12
3492 		IP0SR3_11_8
3493 		IP0SR3_7_4
3494 		IP0SR3_3_0))
3495 	},
3496 	{ PINMUX_CFG_REG("IP1SR3", 0xE6058864, 32, 4, GROUP(
3497 		IP1SR3_31_28
3498 		IP1SR3_27_24
3499 		IP1SR3_23_20
3500 		IP1SR3_19_16
3501 		IP1SR3_15_12
3502 		IP1SR3_11_8
3503 		IP1SR3_7_4
3504 		IP1SR3_3_0))
3505 	},
3506 	{ PINMUX_CFG_REG("IP2SR3", 0xE6058868, 32, 4, GROUP(
3507 		IP2SR3_31_28
3508 		IP2SR3_27_24
3509 		IP2SR3_23_20
3510 		IP2SR3_19_16
3511 		IP2SR3_15_12
3512 		IP2SR3_11_8
3513 		IP2SR3_7_4
3514 		IP2SR3_3_0))
3515 	},
3516 	{ PINMUX_CFG_REG_VAR("IP3SR3", 0xE605886C, 32,
3517 			     GROUP(-8, 4, 4, 4, 4, 4, 4),
3518 			     GROUP(
3519 		/* IP3SR3_31_24 RESERVED */
3520 		IP3SR3_23_20
3521 		IP3SR3_19_16
3522 		IP3SR3_15_12
3523 		IP3SR3_11_8
3524 		IP3SR3_7_4
3525 		IP3SR3_3_0))
3526 	},
3527 	{ PINMUX_CFG_REG_VAR("IP0SR4", 0xE6060060, 32,
3528 			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3529 			     GROUP(
3530 		IP0SR4_31_28
3531 		IP0SR4_27_24
3532 		IP0SR4_23_20
3533 		IP0SR4_19_16
3534 		IP0SR4_15_12
3535 		IP0SR4_11_8
3536 		IP0SR4_7_4
3537 		IP0SR4_3_0))
3538 	},
3539 	{ PINMUX_CFG_REG_VAR("IP1SR4", 0xE6060064, 32,
3540 			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3541 			     GROUP(
3542 		IP1SR4_31_28
3543 		IP1SR4_27_24
3544 		IP1SR4_23_20
3545 		IP1SR4_19_16
3546 		IP1SR4_15_12
3547 		IP1SR4_11_8
3548 		IP1SR4_7_4
3549 		IP1SR4_3_0))
3550 	},
3551 	{ PINMUX_CFG_REG_VAR("IP2SR4", 0xE6060068, 32,
3552 			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3553 			     GROUP(
3554 		IP2SR4_31_28
3555 		IP2SR4_27_24
3556 		IP2SR4_23_20
3557 		IP2SR4_19_16
3558 		IP2SR4_15_12
3559 		IP2SR4_11_8
3560 		IP2SR4_7_4
3561 		IP2SR4_3_0))
3562 	},
3563 	{ PINMUX_CFG_REG_VAR("IP3SR4", 0xE606006C, 32,
3564 			     GROUP(-28, 4),
3565 			     GROUP(
3566 		/* IP3SR4_31_4 RESERVED */
3567 		IP3SR4_3_0))
3568 	},
3569 	{ PINMUX_CFG_REG_VAR("IP0SR5", 0xE6060860, 32,
3570 			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3571 			     GROUP(
3572 		IP0SR5_31_28
3573 		IP0SR5_27_24
3574 		IP0SR5_23_20
3575 		IP0SR5_19_16
3576 		IP0SR5_15_12
3577 		IP0SR5_11_8
3578 		IP0SR5_7_4
3579 		IP0SR5_3_0))
3580 	},
3581 	{ PINMUX_CFG_REG_VAR("IP1SR5", 0xE6060864, 32,
3582 			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3583 			     GROUP(
3584 		IP1SR5_31_28
3585 		IP1SR5_27_24
3586 		IP1SR5_23_20
3587 		IP1SR5_19_16
3588 		IP1SR5_15_12
3589 		IP1SR5_11_8
3590 		IP1SR5_7_4
3591 		IP1SR5_3_0))
3592 	},
3593 	{ PINMUX_CFG_REG_VAR("IP2SR5", 0xE6060868, 32,
3594 			     GROUP(-12, 4, 4, 4, 4, 4),
3595 			     GROUP(
3596 		/* IP2SR5_31_20 RESERVED */
3597 		IP2SR5_19_16
3598 		IP2SR5_15_12
3599 		IP2SR5_11_8
3600 		IP2SR5_7_4
3601 		IP2SR5_3_0))
3602 	},
3603 	{ PINMUX_CFG_REG("IP0SR6", 0xE6061060, 32, 4, GROUP(
3604 		IP0SR6_31_28
3605 		IP0SR6_27_24
3606 		IP0SR6_23_20
3607 		IP0SR6_19_16
3608 		IP0SR6_15_12
3609 		IP0SR6_11_8
3610 		IP0SR6_7_4
3611 		IP0SR6_3_0))
3612 	},
3613 	{ PINMUX_CFG_REG("IP1SR6", 0xE6061064, 32, 4, GROUP(
3614 		IP1SR6_31_28
3615 		IP1SR6_27_24
3616 		IP1SR6_23_20
3617 		IP1SR6_19_16
3618 		IP1SR6_15_12
3619 		IP1SR6_11_8
3620 		IP1SR6_7_4
3621 		IP1SR6_3_0))
3622 	},
3623 	{ PINMUX_CFG_REG_VAR("IP2SR6", 0xE6061068, 32,
3624 			     GROUP(-12, 4, 4, 4, 4, 4),
3625 			     GROUP(
3626 		/* IP2SR6_31_20 RESERVED */
3627 		IP2SR6_19_16
3628 		IP2SR6_15_12
3629 		IP2SR6_11_8
3630 		IP2SR6_7_4
3631 		IP2SR6_3_0))
3632 	},
3633 	{ PINMUX_CFG_REG("IP0SR7", 0xE6061860, 32, 4, GROUP(
3634 		IP0SR7_31_28
3635 		IP0SR7_27_24
3636 		IP0SR7_23_20
3637 		IP0SR7_19_16
3638 		IP0SR7_15_12
3639 		IP0SR7_11_8
3640 		IP0SR7_7_4
3641 		IP0SR7_3_0))
3642 	},
3643 	{ PINMUX_CFG_REG("IP1SR7", 0xE6061864, 32, 4, GROUP(
3644 		IP1SR7_31_28
3645 		IP1SR7_27_24
3646 		IP1SR7_23_20
3647 		IP1SR7_19_16
3648 		IP1SR7_15_12
3649 		IP1SR7_11_8
3650 		IP1SR7_7_4
3651 		IP1SR7_3_0))
3652 	},
3653 	{ PINMUX_CFG_REG_VAR("IP2SR7", 0xE6061868, 32,
3654 			     GROUP(-12, 4, 4, 4, 4, 4),
3655 			     GROUP(
3656 		/* IP2SR7_31_20 RESERVED */
3657 		IP2SR7_19_16
3658 		IP2SR7_15_12
3659 		IP2SR7_11_8
3660 		IP2SR7_7_4
3661 		IP2SR7_3_0))
3662 	},
3663 	{ PINMUX_CFG_REG("IP0SR8", 0xE6068060, 32, 4, GROUP(
3664 		IP0SR8_31_28
3665 		IP0SR8_27_24
3666 		IP0SR8_23_20
3667 		IP0SR8_19_16
3668 		IP0SR8_15_12
3669 		IP0SR8_11_8
3670 		IP0SR8_7_4
3671 		IP0SR8_3_0))
3672 	},
3673 	{ PINMUX_CFG_REG_VAR("IP1SR8", 0xE6068064, 32,
3674 			     GROUP(-8, 4, 4, 4, 4, 4, 4),
3675 			     GROUP(
3676 		/* IP1SR8_31_24 RESERVED */
3677 		IP1SR8_23_20
3678 		IP1SR8_19_16
3679 		IP1SR8_15_12
3680 		IP1SR8_11_8
3681 		IP1SR8_7_4
3682 		IP1SR8_3_0))
3683 	},
3684 #undef F_
3685 #undef FM
3686 
3687 #define F_(x, y)	x,
3688 #define FM(x)		FN_##x,
3689 	{ PINMUX_CFG_REG_VAR("MOD_SEL8", 0xE6068100, 32,
3690 			     GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3691 			     GROUP(
3692 		/* RESERVED 31-12 */
3693 		MOD_SEL8_11
3694 		MOD_SEL8_10
3695 		MOD_SEL8_9
3696 		MOD_SEL8_8
3697 		MOD_SEL8_7
3698 		MOD_SEL8_6
3699 		MOD_SEL8_5
3700 		MOD_SEL8_4
3701 		MOD_SEL8_3
3702 		MOD_SEL8_2
3703 		MOD_SEL8_1
3704 		MOD_SEL8_0))
3705 	},
3706 	{ /* sentinel */ }
3707 };
3708 
3709 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
3710 	{ PINMUX_DRIVE_REG("DRV0CTRL0", 0xE6050080) {
3711 		{ RCAR_GP_PIN(0,  7), 28, 3 },	/* MSIOF5_SS2 */
3712 		{ RCAR_GP_PIN(0,  6), 24, 3 },	/* IRQ0 */
3713 		{ RCAR_GP_PIN(0,  5), 20, 3 },	/* IRQ1 */
3714 		{ RCAR_GP_PIN(0,  4), 16, 3 },	/* IRQ2 */
3715 		{ RCAR_GP_PIN(0,  3), 12, 3 },	/* IRQ3 */
3716 		{ RCAR_GP_PIN(0,  2),  8, 3 },	/* GP0_02 */
3717 		{ RCAR_GP_PIN(0,  1),  4, 3 },	/* GP0_01 */
3718 		{ RCAR_GP_PIN(0,  0),  0, 3 },	/* GP0_00 */
3719 	} },
3720 	{ PINMUX_DRIVE_REG("DRV1CTRL0", 0xE6050084) {
3721 		{ RCAR_GP_PIN(0, 15), 28, 3 },	/* MSIOF2_SYNC */
3722 		{ RCAR_GP_PIN(0, 14), 24, 3 },	/* MSIOF2_SS1 */
3723 		{ RCAR_GP_PIN(0, 13), 20, 3 },	/* MSIOF2_SS2 */
3724 		{ RCAR_GP_PIN(0, 12), 16, 3 },	/* MSIOF5_RXD */
3725 		{ RCAR_GP_PIN(0, 11), 12, 3 },	/* MSIOF5_SCK */
3726 		{ RCAR_GP_PIN(0, 10),  8, 3 },	/* MSIOF5_TXD */
3727 		{ RCAR_GP_PIN(0,  9),  4, 3 },	/* MSIOF5_SYNC */
3728 		{ RCAR_GP_PIN(0,  8),  0, 3 },	/* MSIOF5_SS1 */
3729 	} },
3730 	{ PINMUX_DRIVE_REG("DRV2CTRL0", 0xE6050088) {
3731 		{ RCAR_GP_PIN(0, 18),  8, 3 },	/* MSIOF2_RXD */
3732 		{ RCAR_GP_PIN(0, 17),  4, 3 },	/* MSIOF2_SCK */
3733 		{ RCAR_GP_PIN(0, 16),  0, 3 },	/* MSIOF2_TXD */
3734 	} },
3735 	{ PINMUX_DRIVE_REG("DRV0CTRL1", 0xE6050880) {
3736 		{ RCAR_GP_PIN(1,  7), 28, 3 },	/* MSIOF0_SS1 */
3737 		{ RCAR_GP_PIN(1,  6), 24, 3 },	/* MSIOF0_SS2 */
3738 		{ RCAR_GP_PIN(1,  5), 20, 3 },	/* MSIOF1_RXD */
3739 		{ RCAR_GP_PIN(1,  4), 16, 3 },	/* MSIOF1_TXD */
3740 		{ RCAR_GP_PIN(1,  3), 12, 3 },	/* MSIOF1_SCK */
3741 		{ RCAR_GP_PIN(1,  2),  8, 3 },	/* MSIOF1_SYNC */
3742 		{ RCAR_GP_PIN(1,  1),  4, 3 },	/* MSIOF1_SS1 */
3743 		{ RCAR_GP_PIN(1,  0),  0, 3 },	/* MSIOF1_SS2 */
3744 	} },
3745 	{ PINMUX_DRIVE_REG("DRV1CTRL1", 0xE6050884) {
3746 		{ RCAR_GP_PIN(1, 15), 28, 3 },	/* HSCK0 */
3747 		{ RCAR_GP_PIN(1, 14), 24, 3 },	/* HRTS0_N */
3748 		{ RCAR_GP_PIN(1, 13), 20, 3 },	/* HCTS0_N */
3749 		{ RCAR_GP_PIN(1, 12), 16, 3 },	/* HTX0 */
3750 		{ RCAR_GP_PIN(1, 11), 12, 3 },	/* MSIOF0_RXD */
3751 		{ RCAR_GP_PIN(1, 10),  8, 3 },	/* MSIOF0_SCK */
3752 		{ RCAR_GP_PIN(1,  9),  4, 3 },	/* MSIOF0_TXD */
3753 		{ RCAR_GP_PIN(1,  8),  0, 3 },	/* MSIOF0_SYNC */
3754 	} },
3755 	{ PINMUX_DRIVE_REG("DRV2CTRL1", 0xE6050888) {
3756 		{ RCAR_GP_PIN(1, 23), 28, 3 },	/* GP1_23 */
3757 		{ RCAR_GP_PIN(1, 22), 24, 3 },	/* AUDIO_CLKIN */
3758 		{ RCAR_GP_PIN(1, 21), 20, 3 },	/* AUDIO_CLKOUT */
3759 		{ RCAR_GP_PIN(1, 20), 16, 3 },	/* SSI_SD */
3760 		{ RCAR_GP_PIN(1, 19), 12, 3 },	/* SSI_WS */
3761 		{ RCAR_GP_PIN(1, 18),  8, 3 },	/* SSI_SCK */
3762 		{ RCAR_GP_PIN(1, 17),  4, 3 },	/* SCIF_CLK */
3763 		{ RCAR_GP_PIN(1, 16),  0, 3 },	/* HRX0 */
3764 	} },
3765 	{ PINMUX_DRIVE_REG("DRV3CTRL1", 0xE605088C) {
3766 		{ RCAR_GP_PIN(1, 28), 16, 3 },	/* HTX3 */
3767 		{ RCAR_GP_PIN(1, 27), 12, 3 },	/* HCTS3_N */
3768 		{ RCAR_GP_PIN(1, 26),  8, 3 },	/* HRTS3_N */
3769 		{ RCAR_GP_PIN(1, 25),  4, 3 },	/* HSCK3 */
3770 		{ RCAR_GP_PIN(1, 24),  0, 3 },	/* HRX3 */
3771 	} },
3772 	{ PINMUX_DRIVE_REG("DRV0CTRL2", 0xE6058080) {
3773 		{ RCAR_GP_PIN(2,  7), 28, 3 },	/* TPU0TO1 */
3774 		{ RCAR_GP_PIN(2,  6), 24, 3 },	/* FXR_TXDB */
3775 		{ RCAR_GP_PIN(2,  5), 20, 3 },	/* FXR_TXENB_N */
3776 		{ RCAR_GP_PIN(2,  4), 16, 3 },	/* RXDB_EXTFXR */
3777 		{ RCAR_GP_PIN(2,  3), 12, 3 },	/* CLK_EXTFXR */
3778 		{ RCAR_GP_PIN(2,  2),  8, 3 },	/* RXDA_EXTFXR */
3779 		{ RCAR_GP_PIN(2,  1),  4, 3 },	/* FXR_TXENA_N */
3780 		{ RCAR_GP_PIN(2,  0),  0, 3 },	/* FXR_TXDA */
3781 	} },
3782 	{ PINMUX_DRIVE_REG("DRV1CTRL2", 0xE6058084) {
3783 		{ RCAR_GP_PIN(2, 15), 28, 3 },	/* CANFD3_RX */
3784 		{ RCAR_GP_PIN(2, 14), 24, 3 },	/* CANFD3_TX */
3785 		{ RCAR_GP_PIN(2, 13), 20, 3 },	/* CANFD2_RX */
3786 		{ RCAR_GP_PIN(2, 12), 16, 3 },	/* CANFD2_TX */
3787 		{ RCAR_GP_PIN(2, 11), 12, 3 },	/* CANFD0_RX */
3788 		{ RCAR_GP_PIN(2, 10),  8, 3 },	/* CANFD0_TX */
3789 		{ RCAR_GP_PIN(2,  9),  4, 3 },	/* CAN_CLK */
3790 		{ RCAR_GP_PIN(2,  8),  0, 3 },	/* TPU0TO0 */
3791 	} },
3792 	{ PINMUX_DRIVE_REG("DRV2CTRL2", 0xE6058088) {
3793 		{ RCAR_GP_PIN(2, 19), 12, 3 },	/* CANFD7_RX */
3794 		{ RCAR_GP_PIN(2, 18),  8, 3 },	/* CANFD7_TX */
3795 		{ RCAR_GP_PIN(2, 17),  4, 3 },	/* CANFD4_RX */
3796 		{ RCAR_GP_PIN(2, 16),  0, 3 },	/* CANFD4_TX */
3797 	} },
3798 	{ PINMUX_DRIVE_REG("DRV0CTRL3", 0xE6058880) {
3799 		{ RCAR_GP_PIN(3,  7), 28, 3 },	/* MMC_D4 */
3800 		{ RCAR_GP_PIN(3,  6), 24, 3 },	/* MMC_D5 */
3801 		{ RCAR_GP_PIN(3,  5), 20, 3 },	/* MMC_SD_D3 */
3802 		{ RCAR_GP_PIN(3,  4), 16, 3 },	/* MMC_DS */
3803 		{ RCAR_GP_PIN(3,  3), 12, 3 },	/* MMC_SD_CLK */
3804 		{ RCAR_GP_PIN(3,  2),  8, 3 },	/* MMC_SD_D2 */
3805 		{ RCAR_GP_PIN(3,  1),  4, 3 },	/* MMC_SD_D0 */
3806 		{ RCAR_GP_PIN(3,  0),  0, 3 },	/* MMC_SD_D1 */
3807 	} },
3808 	{ PINMUX_DRIVE_REG("DRV1CTRL3", 0xE6058884) {
3809 		{ RCAR_GP_PIN(3, 15), 28, 2 },	/* QSPI0_SSL */
3810 		{ RCAR_GP_PIN(3, 14), 24, 2 },	/* IPC_CLKOUT */
3811 		{ RCAR_GP_PIN(3, 13), 20, 2 },	/* IPC_CLKIN */
3812 		{ RCAR_GP_PIN(3, 12), 16, 3 },	/* SD_WP */
3813 		{ RCAR_GP_PIN(3, 11), 12, 3 },	/* SD_CD */
3814 		{ RCAR_GP_PIN(3, 10),  8, 3 },	/* MMC_SD_CMD */
3815 		{ RCAR_GP_PIN(3,  9),  4, 3 },	/* MMC_D6*/
3816 		{ RCAR_GP_PIN(3,  8),  0, 3 },	/* MMC_D7 */
3817 	} },
3818 	{ PINMUX_DRIVE_REG("DRV2CTRL3", 0xE6058888) {
3819 		{ RCAR_GP_PIN(3, 23), 28, 2 },	/* QSPI1_MISO_IO1 */
3820 		{ RCAR_GP_PIN(3, 22), 24, 2 },	/* QSPI1_SPCLK */
3821 		{ RCAR_GP_PIN(3, 21), 20, 2 },	/* QSPI1_MOSI_IO0 */
3822 		{ RCAR_GP_PIN(3, 20), 16, 2 },	/* QSPI0_SPCLK */
3823 		{ RCAR_GP_PIN(3, 19), 12, 2 },	/* QSPI0_MOSI_IO0 */
3824 		{ RCAR_GP_PIN(3, 18),  8, 2 },	/* QSPI0_MISO_IO1 */
3825 		{ RCAR_GP_PIN(3, 17),  4, 2 },	/* QSPI0_IO2 */
3826 		{ RCAR_GP_PIN(3, 16),  0, 2 },	/* QSPI0_IO3 */
3827 	} },
3828 	{ PINMUX_DRIVE_REG("DRV3CTRL3", 0xE605888C) {
3829 		{ RCAR_GP_PIN(3, 29), 20, 2 },	/* RPC_INT_N */
3830 		{ RCAR_GP_PIN(3, 28), 16, 2 },	/* RPC_WP_N */
3831 		{ RCAR_GP_PIN(3, 27), 12, 2 },	/* RPC_RESET_N */
3832 		{ RCAR_GP_PIN(3, 26),  8, 2 },	/* QSPI1_IO3 */
3833 		{ RCAR_GP_PIN(3, 25),  4, 2 },	/* QSPI1_SSL */
3834 		{ RCAR_GP_PIN(3, 24),  0, 2 },	/* QSPI1_IO2 */
3835 	} },
3836 	{ PINMUX_DRIVE_REG("DRV0CTRL4", 0xE6060080) {
3837 		{ RCAR_GP_PIN(4,  7), 28, 3 },	/* TSN0_RX_CTL */
3838 		{ RCAR_GP_PIN(4,  6), 24, 3 },	/* TSN0_AVTP_CAPTURE */
3839 		{ RCAR_GP_PIN(4,  5), 20, 3 },	/* TSN0_AVTP_MATCH */
3840 		{ RCAR_GP_PIN(4,  4), 16, 3 },	/* TSN0_LINK */
3841 		{ RCAR_GP_PIN(4,  3), 12, 3 },	/* TSN0_PHY_INT */
3842 		{ RCAR_GP_PIN(4,  2),  8, 3 },	/* TSN0_AVTP_PPS1 */
3843 		{ RCAR_GP_PIN(4,  1),  4, 3 },	/* TSN0_MDC */
3844 		{ RCAR_GP_PIN(4,  0),  0, 3 },	/* TSN0_MDIO */
3845 	} },
3846 	{ PINMUX_DRIVE_REG("DRV1CTRL4", 0xE6060084) {
3847 		{ RCAR_GP_PIN(4, 15), 28, 3 },	/* TSN0_TD0 */
3848 		{ RCAR_GP_PIN(4, 14), 24, 3 },	/* TSN0_TD1 */
3849 		{ RCAR_GP_PIN(4, 13), 20, 3 },	/* TSN0_RD1 */
3850 		{ RCAR_GP_PIN(4, 12), 16, 3 },	/* TSN0_TXC */
3851 		{ RCAR_GP_PIN(4, 11), 12, 3 },	/* TSN0_RXC */
3852 		{ RCAR_GP_PIN(4, 10),  8, 3 },	/* TSN0_RD0 */
3853 		{ RCAR_GP_PIN(4,  9),  4, 3 },	/* TSN0_TX_CTL */
3854 		{ RCAR_GP_PIN(4,  8),  0, 3 },	/* TSN0_AVTP_PPS0 */
3855 	} },
3856 	{ PINMUX_DRIVE_REG("DRV2CTRL4", 0xE6060088) {
3857 		{ RCAR_GP_PIN(4, 23), 28, 3 },	/* AVS0 */
3858 		{ RCAR_GP_PIN(4, 22), 24, 3 },	/* PCIE1_CLKREQ_N */
3859 		{ RCAR_GP_PIN(4, 21), 20, 3 },	/* PCIE0_CLKREQ_N */
3860 		{ RCAR_GP_PIN(4, 20), 16, 3 },	/* TSN0_TXCREFCLK */
3861 		{ RCAR_GP_PIN(4, 19), 12, 3 },	/* TSN0_TD2 */
3862 		{ RCAR_GP_PIN(4, 18),  8, 3 },	/* TSN0_TD3 */
3863 		{ RCAR_GP_PIN(4, 17),  4, 3 },	/* TSN0_RD2 */
3864 		{ RCAR_GP_PIN(4, 16),  0, 3 },	/* TSN0_RD3 */
3865 	} },
3866 	{ PINMUX_DRIVE_REG("DRV3CTRL4", 0xE606008C) {
3867 		{ RCAR_GP_PIN(4, 24),  0, 3 },	/* AVS1 */
3868 	} },
3869 	{ PINMUX_DRIVE_REG("DRV0CTRL5", 0xE6060880) {
3870 		{ RCAR_GP_PIN(5,  7), 28, 3 },	/* AVB2_TXCREFCLK */
3871 		{ RCAR_GP_PIN(5,  6), 24, 3 },	/* AVB2_MDC */
3872 		{ RCAR_GP_PIN(5,  5), 20, 3 },	/* AVB2_MAGIC */
3873 		{ RCAR_GP_PIN(5,  4), 16, 3 },	/* AVB2_PHY_INT */
3874 		{ RCAR_GP_PIN(5,  3), 12, 3 },	/* AVB2_LINK */
3875 		{ RCAR_GP_PIN(5,  2),  8, 3 },	/* AVB2_AVTP_MATCH */
3876 		{ RCAR_GP_PIN(5,  1),  4, 3 },	/* AVB2_AVTP_CAPTURE */
3877 		{ RCAR_GP_PIN(5,  0),  0, 3 },	/* AVB2_AVTP_PPS */
3878 	} },
3879 	{ PINMUX_DRIVE_REG("DRV1CTRL5", 0xE6060884) {
3880 		{ RCAR_GP_PIN(5, 15), 28, 3 },	/* AVB2_TD0 */
3881 		{ RCAR_GP_PIN(5, 14), 24, 3 },	/* AVB2_RD1 */
3882 		{ RCAR_GP_PIN(5, 13), 20, 3 },	/* AVB2_RD2 */
3883 		{ RCAR_GP_PIN(5, 12), 16, 3 },	/* AVB2_TD1 */
3884 		{ RCAR_GP_PIN(5, 11), 12, 3 },	/* AVB2_TD2 */
3885 		{ RCAR_GP_PIN(5, 10),  8, 3 },	/* AVB2_MDIO */
3886 		{ RCAR_GP_PIN(5,  9),  4, 3 },	/* AVB2_RD3 */
3887 		{ RCAR_GP_PIN(5,  8),  0, 3 },	/* AVB2_TD3 */
3888 	} },
3889 	{ PINMUX_DRIVE_REG("DRV2CTRL5", 0xE6060888) {
3890 		{ RCAR_GP_PIN(5, 20), 16, 3 },	/* AVB2_RX_CTL */
3891 		{ RCAR_GP_PIN(5, 19), 12, 3 },	/* AVB2_TX_CTL */
3892 		{ RCAR_GP_PIN(5, 18),  8, 3 },	/* AVB2_RXC */
3893 		{ RCAR_GP_PIN(5, 17),  4, 3 },	/* AVB2_RD0 */
3894 		{ RCAR_GP_PIN(5, 16),  0, 3 },	/* AVB2_TXC */
3895 	} },
3896 	{ PINMUX_DRIVE_REG("DRV0CTRL6", 0xE6061080) {
3897 		{ RCAR_GP_PIN(6,  7), 28, 3 },	/* AVB1_TX_CTL */
3898 		{ RCAR_GP_PIN(6,  6), 24, 3 },	/* AVB1_TXC */
3899 		{ RCAR_GP_PIN(6,  5), 20, 3 },	/* AVB1_AVTP_MATCH */
3900 		{ RCAR_GP_PIN(6,  4), 16, 3 },	/* AVB1_LINK */
3901 		{ RCAR_GP_PIN(6,  3), 12, 3 },	/* AVB1_PHY_INT */
3902 		{ RCAR_GP_PIN(6,  2),  8, 3 },	/* AVB1_MDC */
3903 		{ RCAR_GP_PIN(6,  1),  4, 3 },	/* AVB1_MAGIC */
3904 		{ RCAR_GP_PIN(6,  0),  0, 3 },	/* AVB1_MDIO */
3905 	} },
3906 	{ PINMUX_DRIVE_REG("DRV1CTRL6", 0xE6061084) {
3907 		{ RCAR_GP_PIN(6, 15), 28, 3 },	/* AVB1_RD0 */
3908 		{ RCAR_GP_PIN(6, 14), 24, 3 },	/* AVB1_RD1 */
3909 		{ RCAR_GP_PIN(6, 13), 20, 3 },	/* AVB1_TD0 */
3910 		{ RCAR_GP_PIN(6, 12), 16, 3 },	/* AVB1_TD1 */
3911 		{ RCAR_GP_PIN(6, 11), 12, 3 },	/* AVB1_AVTP_CAPTURE */
3912 		{ RCAR_GP_PIN(6, 10),  8, 3 },	/* AVB1_AVTP_PPS */
3913 		{ RCAR_GP_PIN(6,  9),  4, 3 },	/* AVB1_RX_CTL */
3914 		{ RCAR_GP_PIN(6,  8),  0, 3 },	/* AVB1_RXC */
3915 	} },
3916 	{ PINMUX_DRIVE_REG("DRV2CTRL6", 0xE6061088) {
3917 		{ RCAR_GP_PIN(6, 20), 16, 3 },	/* AVB1_TXCREFCLK */
3918 		{ RCAR_GP_PIN(6, 19), 12, 3 },	/* AVB1_RD3 */
3919 		{ RCAR_GP_PIN(6, 18),  8, 3 },	/* AVB1_TD3 */
3920 		{ RCAR_GP_PIN(6, 17),  4, 3 },	/* AVB1_RD2 */
3921 		{ RCAR_GP_PIN(6, 16),  0, 3 },	/* AVB1_TD2 */
3922 	} },
3923 	{ PINMUX_DRIVE_REG("DRV0CTRL7", 0xE6061880) {
3924 		{ RCAR_GP_PIN(7,  7), 28, 3 },	/* AVB0_TD1 */
3925 		{ RCAR_GP_PIN(7,  6), 24, 3 },	/* AVB0_TD2 */
3926 		{ RCAR_GP_PIN(7,  5), 20, 3 },	/* AVB0_PHY_INT */
3927 		{ RCAR_GP_PIN(7,  4), 16, 3 },	/* AVB0_LINK */
3928 		{ RCAR_GP_PIN(7,  3), 12, 3 },	/* AVB0_TD3 */
3929 		{ RCAR_GP_PIN(7,  2),  8, 3 },	/* AVB0_AVTP_MATCH */
3930 		{ RCAR_GP_PIN(7,  1),  4, 3 },	/* AVB0_AVTP_CAPTURE */
3931 		{ RCAR_GP_PIN(7,  0),  0, 3 },	/* AVB0_AVTP_PPS */
3932 	} },
3933 	{ PINMUX_DRIVE_REG("DRV1CTRL7", 0xE6061884) {
3934 		{ RCAR_GP_PIN(7, 15), 28, 3 },	/* AVB0_TXC */
3935 		{ RCAR_GP_PIN(7, 14), 24, 3 },	/* AVB0_MDIO */
3936 		{ RCAR_GP_PIN(7, 13), 20, 3 },	/* AVB0_MDC */
3937 		{ RCAR_GP_PIN(7, 12), 16, 3 },	/* AVB0_RD2 */
3938 		{ RCAR_GP_PIN(7, 11), 12, 3 },	/* AVB0_TD0 */
3939 		{ RCAR_GP_PIN(7, 10),  8, 3 },	/* AVB0_MAGIC */
3940 		{ RCAR_GP_PIN(7,  9),  4, 3 },	/* AVB0_TXCREFCLK */
3941 		{ RCAR_GP_PIN(7,  8),  0, 3 },	/* AVB0_RD3 */
3942 	} },
3943 	{ PINMUX_DRIVE_REG("DRV2CTRL7", 0xE6061888) {
3944 		{ RCAR_GP_PIN(7, 20), 16, 3 },	/* AVB0_RX_CTL */
3945 		{ RCAR_GP_PIN(7, 19), 12, 3 },	/* AVB0_RXC */
3946 		{ RCAR_GP_PIN(7, 18),  8, 3 },	/* AVB0_RD0 */
3947 		{ RCAR_GP_PIN(7, 17),  4, 3 },	/* AVB0_RD1 */
3948 		{ RCAR_GP_PIN(7, 16),  0, 3 },	/* AVB0_TX_CTL */
3949 	} },
3950 	{ PINMUX_DRIVE_REG("DRV0CTRL8", 0xE6068080) {
3951 		{ RCAR_GP_PIN(8,  7), 28, 3 },	/* SDA3 */
3952 		{ RCAR_GP_PIN(8,  6), 24, 3 },	/* SCL3 */
3953 		{ RCAR_GP_PIN(8,  5), 20, 3 },	/* SDA2 */
3954 		{ RCAR_GP_PIN(8,  4), 16, 3 },	/* SCL2 */
3955 		{ RCAR_GP_PIN(8,  3), 12, 3 },	/* SDA1 */
3956 		{ RCAR_GP_PIN(8,  2),  8, 3 },	/* SCL1 */
3957 		{ RCAR_GP_PIN(8,  1),  4, 3 },	/* SDA0 */
3958 		{ RCAR_GP_PIN(8,  0),  0, 3 },	/* SCL0 */
3959 	} },
3960 	{ PINMUX_DRIVE_REG("DRV1CTRL8", 0xE6068084) {
3961 		{ RCAR_GP_PIN(8, 13), 20, 3 },	/* GP8_13 */
3962 		{ RCAR_GP_PIN(8, 12), 16, 3 },	/* GP8_12 */
3963 		{ RCAR_GP_PIN(8, 11), 12, 3 },	/* SDA5 */
3964 		{ RCAR_GP_PIN(8, 10),  8, 3 },	/* SCL5 */
3965 		{ RCAR_GP_PIN(8,  9),  4, 3 },	/* SDA4 */
3966 		{ RCAR_GP_PIN(8,  8),  0, 3 },	/* SCL4 */
3967 	} },
3968 	{ /* sentinel */ }
3969 };
3970 
3971 enum ioctrl_regs {
3972 	POC0,
3973 	POC1,
3974 	POC3,
3975 	POC4,
3976 	POC5,
3977 	POC6,
3978 	POC7,
3979 	POC8,
3980 };
3981 
3982 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
3983 	[POC0]		= { 0xE60500A0, },
3984 	[POC1]		= { 0xE60508A0, },
3985 	[POC3]		= { 0xE60588A0, },
3986 	[POC4]		= { 0xE60600A0, },
3987 	[POC5]		= { 0xE60608A0, },
3988 	[POC6]		= { 0xE60610A0, },
3989 	[POC7]		= { 0xE60618A0, },
3990 	[POC8]		= { 0xE60680A0, },
3991 	{ /* sentinel */ }
3992 };
3993 
3994 static int r8a779g0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
3995 {
3996 	int bit = pin & 0x1f;
3997 
3998 	switch (pin) {
3999 	case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 18):
4000 		*pocctrl = pinmux_ioctrl_regs[POC0].reg;
4001 		return bit;
4002 
4003 	case RCAR_GP_PIN(1, 0) ... RCAR_GP_PIN(1, 22):
4004 		*pocctrl = pinmux_ioctrl_regs[POC1].reg;
4005 		return bit;
4006 
4007 	case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 12):
4008 		*pocctrl = pinmux_ioctrl_regs[POC3].reg;
4009 		return bit;
4010 
4011 	case PIN_VDDQ_TSN0:
4012 		*pocctrl = pinmux_ioctrl_regs[POC4].reg;
4013 		return 0;
4014 
4015 	case PIN_VDDQ_AVB2:
4016 		*pocctrl = pinmux_ioctrl_regs[POC5].reg;
4017 		return 0;
4018 
4019 	case PIN_VDDQ_AVB1:
4020 		*pocctrl = pinmux_ioctrl_regs[POC6].reg;
4021 		return 0;
4022 
4023 	case PIN_VDDQ_AVB0:
4024 		*pocctrl = pinmux_ioctrl_regs[POC7].reg;
4025 		return 0;
4026 
4027 	case RCAR_GP_PIN(8, 0) ... RCAR_GP_PIN(8, 13):
4028 		*pocctrl = pinmux_ioctrl_regs[POC8].reg;
4029 		return bit;
4030 
4031 	default:
4032 		return -EINVAL;
4033 	}
4034 }
4035 
4036 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
4037 	{ PINMUX_BIAS_REG("PUEN0", 0xE60500C0, "PUD0", 0xE60500E0) {
4038 		[ 0] = RCAR_GP_PIN(0,  0),	/* GP0_00 */
4039 		[ 1] = RCAR_GP_PIN(0,  1),	/* GP0_01 */
4040 		[ 2] = RCAR_GP_PIN(0,  2),	/* GP0_02 */
4041 		[ 3] = RCAR_GP_PIN(0,  3),	/* IRQ3 */
4042 		[ 4] = RCAR_GP_PIN(0,  4),	/* IRQ2 */
4043 		[ 5] = RCAR_GP_PIN(0,  5),	/* IRQ1 */
4044 		[ 6] = RCAR_GP_PIN(0,  6),	/* IRQ0 */
4045 		[ 7] = RCAR_GP_PIN(0,  7),	/* MSIOF5_SS2 */
4046 		[ 8] = RCAR_GP_PIN(0,  8),	/* MSIOF5_SS1 */
4047 		[ 9] = RCAR_GP_PIN(0,  9),	/* MSIOF5_SYNC */
4048 		[10] = RCAR_GP_PIN(0, 10),	/* MSIOF5_TXD */
4049 		[11] = RCAR_GP_PIN(0, 11),	/* MSIOF5_SCK */
4050 		[12] = RCAR_GP_PIN(0, 12),	/* MSIOF5_RXD */
4051 		[13] = RCAR_GP_PIN(0, 13),	/* MSIOF2_SS2 */
4052 		[14] = RCAR_GP_PIN(0, 14),	/* MSIOF2_SS1 */
4053 		[15] = RCAR_GP_PIN(0, 15),	/* MSIOF2_SYNC */
4054 		[16] = RCAR_GP_PIN(0, 16),	/* MSIOF2_TXD */
4055 		[17] = RCAR_GP_PIN(0, 17),	/* MSIOF2_SCK */
4056 		[18] = RCAR_GP_PIN(0, 18),	/* MSIOF2_RXD */
4057 		[19] = SH_PFC_PIN_NONE,
4058 		[20] = SH_PFC_PIN_NONE,
4059 		[21] = SH_PFC_PIN_NONE,
4060 		[22] = SH_PFC_PIN_NONE,
4061 		[23] = SH_PFC_PIN_NONE,
4062 		[24] = SH_PFC_PIN_NONE,
4063 		[25] = SH_PFC_PIN_NONE,
4064 		[26] = SH_PFC_PIN_NONE,
4065 		[27] = SH_PFC_PIN_NONE,
4066 		[28] = SH_PFC_PIN_NONE,
4067 		[29] = SH_PFC_PIN_NONE,
4068 		[30] = SH_PFC_PIN_NONE,
4069 		[31] = SH_PFC_PIN_NONE,
4070 	} },
4071 	{ PINMUX_BIAS_REG("PUEN1", 0xE60508C0, "PUD1", 0xE60508E0) {
4072 		[ 0] = RCAR_GP_PIN(1,  0),	/* MSIOF1_SS2 */
4073 		[ 1] = RCAR_GP_PIN(1,  1),	/* MSIOF1_SS1 */
4074 		[ 2] = RCAR_GP_PIN(1,  2),	/* MSIOF1_SYNC */
4075 		[ 3] = RCAR_GP_PIN(1,  3),	/* MSIOF1_SCK */
4076 		[ 4] = RCAR_GP_PIN(1,  4),	/* MSIOF1_TXD */
4077 		[ 5] = RCAR_GP_PIN(1,  5),	/* MSIOF1_RXD */
4078 		[ 6] = RCAR_GP_PIN(1,  6),	/* MSIOF0_SS2 */
4079 		[ 7] = RCAR_GP_PIN(1,  7),	/* MSIOF0_SS1 */
4080 		[ 8] = RCAR_GP_PIN(1,  8),	/* MSIOF0_SYNC */
4081 		[ 9] = RCAR_GP_PIN(1,  9),	/* MSIOF0_TXD */
4082 		[10] = RCAR_GP_PIN(1, 10),	/* MSIOF0_SCK */
4083 		[11] = RCAR_GP_PIN(1, 11),	/* MSIOF0_RXD */
4084 		[12] = RCAR_GP_PIN(1, 12),	/* HTX0 */
4085 		[13] = RCAR_GP_PIN(1, 13),	/* HCTS0_N */
4086 		[14] = RCAR_GP_PIN(1, 14),	/* HRTS0_N */
4087 		[15] = RCAR_GP_PIN(1, 15),	/* HSCK0 */
4088 		[16] = RCAR_GP_PIN(1, 16),	/* HRX0 */
4089 		[17] = RCAR_GP_PIN(1, 17),	/* SCIF_CLK */
4090 		[18] = RCAR_GP_PIN(1, 18),	/* SSI_SCK */
4091 		[19] = RCAR_GP_PIN(1, 19),	/* SSI_WS */
4092 		[20] = RCAR_GP_PIN(1, 20),	/* SSI_SD */
4093 		[21] = RCAR_GP_PIN(1, 21),	/* AUDIO_CLKOUT */
4094 		[22] = RCAR_GP_PIN(1, 22),	/* AUDIO_CLKIN */
4095 		[23] = RCAR_GP_PIN(1, 23),	/* GP1_23 */
4096 		[24] = RCAR_GP_PIN(1, 24),	/* HRX3 */
4097 		[25] = RCAR_GP_PIN(1, 25),	/* HSCK3 */
4098 		[26] = RCAR_GP_PIN(1, 26),	/* HRTS3_N */
4099 		[27] = RCAR_GP_PIN(1, 27),	/* HCTS3_N */
4100 		[28] = RCAR_GP_PIN(1, 28),	/* HTX3 */
4101 		[29] = SH_PFC_PIN_NONE,
4102 		[30] = SH_PFC_PIN_NONE,
4103 		[31] = SH_PFC_PIN_NONE,
4104 	} },
4105 	{ PINMUX_BIAS_REG("PUEN2", 0xE60580C0, "PUD2", 0xE60580E0) {
4106 		[ 0] = RCAR_GP_PIN(2,  0),	/* FXR_TXDA */
4107 		[ 1] = RCAR_GP_PIN(2,  1),	/* FXR_TXENA_N */
4108 		[ 2] = RCAR_GP_PIN(2,  2),	/* RXDA_EXTFXR */
4109 		[ 3] = RCAR_GP_PIN(2,  3),	/* CLK_EXTFXR */
4110 		[ 4] = RCAR_GP_PIN(2,  4),	/* RXDB_EXTFXR */
4111 		[ 5] = RCAR_GP_PIN(2,  5),	/* FXR_TXENB_N */
4112 		[ 6] = RCAR_GP_PIN(2,  6),	/* FXR_TXDB */
4113 		[ 7] = RCAR_GP_PIN(2,  7),	/* TPU0TO1 */
4114 		[ 8] = RCAR_GP_PIN(2,  8),	/* TPU0TO0 */
4115 		[ 9] = RCAR_GP_PIN(2,  9),	/* CAN_CLK */
4116 		[10] = RCAR_GP_PIN(2, 10),	/* CANFD0_TX */
4117 		[11] = RCAR_GP_PIN(2, 11),	/* CANFD0_RX */
4118 		[12] = RCAR_GP_PIN(2, 12),	/* CANFD2_TX */
4119 		[13] = RCAR_GP_PIN(2, 13),	/* CANFD2_RX */
4120 		[14] = RCAR_GP_PIN(2, 14),	/* CANFD3_TX */
4121 		[15] = RCAR_GP_PIN(2, 15),	/* CANFD3_RX */
4122 		[16] = RCAR_GP_PIN(2, 16),	/* CANFD4_TX */
4123 		[17] = RCAR_GP_PIN(2, 17),	/* CANFD4_RX */
4124 		[18] = RCAR_GP_PIN(2, 18),	/* CANFD7_TX */
4125 		[19] = RCAR_GP_PIN(2, 19),	/* CANFD7_RX */
4126 		[20] = SH_PFC_PIN_NONE,
4127 		[21] = SH_PFC_PIN_NONE,
4128 		[22] = SH_PFC_PIN_NONE,
4129 		[23] = SH_PFC_PIN_NONE,
4130 		[24] = SH_PFC_PIN_NONE,
4131 		[25] = SH_PFC_PIN_NONE,
4132 		[26] = SH_PFC_PIN_NONE,
4133 		[27] = SH_PFC_PIN_NONE,
4134 		[28] = SH_PFC_PIN_NONE,
4135 		[29] = SH_PFC_PIN_NONE,
4136 		[30] = SH_PFC_PIN_NONE,
4137 		[31] = SH_PFC_PIN_NONE,
4138 	} },
4139 	{ PINMUX_BIAS_REG("PUEN3", 0xE60588C0, "PUD3", 0xE60588E0) {
4140 		[ 0] = RCAR_GP_PIN(3,  0),	/* MMC_SD_D1 */
4141 		[ 1] = RCAR_GP_PIN(3,  1),	/* MMC_SD_D0 */
4142 		[ 2] = RCAR_GP_PIN(3,  2),	/* MMC_SD_D2 */
4143 		[ 3] = RCAR_GP_PIN(3,  3),	/* MMC_SD_CLK */
4144 		[ 4] = RCAR_GP_PIN(3,  4),	/* MMC_DS */
4145 		[ 5] = RCAR_GP_PIN(3,  5),	/* MMC_SD_D3 */
4146 		[ 6] = RCAR_GP_PIN(3,  6),	/* MMC_D5 */
4147 		[ 7] = RCAR_GP_PIN(3,  7),	/* MMC_D4 */
4148 		[ 8] = RCAR_GP_PIN(3,  8),	/* MMC_D7 */
4149 		[ 9] = RCAR_GP_PIN(3,  9),	/* MMC_D6 */
4150 		[10] = RCAR_GP_PIN(3, 10),	/* MMC_SD_CMD */
4151 		[11] = RCAR_GP_PIN(3, 11),	/* SD_CD */
4152 		[12] = RCAR_GP_PIN(3, 12),	/* SD_WP */
4153 		[13] = RCAR_GP_PIN(3, 13),	/* IPC_CLKIN */
4154 		[14] = RCAR_GP_PIN(3, 14),	/* IPC_CLKOUT */
4155 		[15] = RCAR_GP_PIN(3, 15),	/* QSPI0_SSL */
4156 		[16] = RCAR_GP_PIN(3, 16),	/* QSPI0_IO3 */
4157 		[17] = RCAR_GP_PIN(3, 17),	/* QSPI0_IO2 */
4158 		[18] = RCAR_GP_PIN(3, 18),	/* QSPI0_MISO_IO1 */
4159 		[19] = RCAR_GP_PIN(3, 19),	/* QSPI0_MOSI_IO0 */
4160 		[20] = RCAR_GP_PIN(3, 20),	/* QSPI0_SPCLK */
4161 		[21] = RCAR_GP_PIN(3, 21),	/* QSPI1_MOSI_IO0 */
4162 		[22] = RCAR_GP_PIN(3, 22),	/* QSPI1_SPCLK */
4163 		[23] = RCAR_GP_PIN(3, 23),	/* QSPI1_MISO_IO1 */
4164 		[24] = RCAR_GP_PIN(3, 24),	/* QSPI1_IO2 */
4165 		[25] = RCAR_GP_PIN(3, 25),	/* QSPI1_SSL */
4166 		[26] = RCAR_GP_PIN(3, 26),	/* QSPI1_IO3 */
4167 		[27] = RCAR_GP_PIN(3, 27),	/* RPC_RESET_N */
4168 		[28] = RCAR_GP_PIN(3, 28),	/* RPC_WP_N */
4169 		[29] = RCAR_GP_PIN(3, 29),	/* RPC_INT_N */
4170 		[30] = SH_PFC_PIN_NONE,
4171 		[31] = SH_PFC_PIN_NONE,
4172 	} },
4173 	{ PINMUX_BIAS_REG("PUEN4", 0xE60600C0, "PUD4", 0xE60600E0) {
4174 		[ 0] = RCAR_GP_PIN(4,  0),	/* TSN0_MDIO */
4175 		[ 1] = RCAR_GP_PIN(4,  1),	/* TSN0_MDC */
4176 		[ 2] = RCAR_GP_PIN(4,  2),	/* TSN0_AVTP_PPS1 */
4177 		[ 3] = RCAR_GP_PIN(4,  3),	/* TSN0_PHY_INT */
4178 		[ 4] = RCAR_GP_PIN(4,  4),	/* TSN0_LINK */
4179 		[ 5] = RCAR_GP_PIN(4,  5),	/* TSN0_AVTP_MATCH */
4180 		[ 6] = RCAR_GP_PIN(4,  6),	/* TSN0_AVTP_CAPTURE */
4181 		[ 7] = RCAR_GP_PIN(4,  7),	/* TSN0_RX_CTL */
4182 		[ 8] = RCAR_GP_PIN(4,  8),	/* TSN0_AVTP_PPS0 */
4183 		[ 9] = RCAR_GP_PIN(4,  9),	/* TSN0_TX_CTL */
4184 		[10] = RCAR_GP_PIN(4, 10),	/* TSN0_RD0 */
4185 		[11] = RCAR_GP_PIN(4, 11),	/* TSN0_RXC */
4186 		[12] = RCAR_GP_PIN(4, 12),	/* TSN0_TXC */
4187 		[13] = RCAR_GP_PIN(4, 13),	/* TSN0_RD1 */
4188 		[14] = RCAR_GP_PIN(4, 14),	/* TSN0_TD1 */
4189 		[15] = RCAR_GP_PIN(4, 15),	/* TSN0_TD0 */
4190 		[16] = RCAR_GP_PIN(4, 16),	/* TSN0_RD3 */
4191 		[17] = RCAR_GP_PIN(4, 17),	/* TSN0_RD2 */
4192 		[18] = RCAR_GP_PIN(4, 18),	/* TSN0_TD3 */
4193 		[19] = RCAR_GP_PIN(4, 19),	/* TSN0_TD2 */
4194 		[20] = RCAR_GP_PIN(4, 20),	/* TSN0_TXCREFCLK */
4195 		[21] = RCAR_GP_PIN(4, 21),	/* PCIE0_CLKREQ_N */
4196 		[22] = RCAR_GP_PIN(4, 22),	/* PCIE1_CLKREQ_N */
4197 		[23] = RCAR_GP_PIN(4, 23),	/* AVS0 */
4198 		[24] = RCAR_GP_PIN(4, 24),	/* AVS1 */
4199 		[25] = SH_PFC_PIN_NONE,
4200 		[26] = SH_PFC_PIN_NONE,
4201 		[27] = SH_PFC_PIN_NONE,
4202 		[28] = SH_PFC_PIN_NONE,
4203 		[29] = SH_PFC_PIN_NONE,
4204 		[30] = SH_PFC_PIN_NONE,
4205 		[31] = SH_PFC_PIN_NONE,
4206 	} },
4207 	{ PINMUX_BIAS_REG("PUEN5", 0xE60608C0, "PUD5", 0xE60608E0) {
4208 		[ 0] = RCAR_GP_PIN(5,  0),	/* AVB2_AVTP_PPS */
4209 		[ 1] = RCAR_GP_PIN(5,  1),	/* AVB0_AVTP_CAPTURE */
4210 		[ 2] = RCAR_GP_PIN(5,  2),	/* AVB2_AVTP_MATCH */
4211 		[ 3] = RCAR_GP_PIN(5,  3),	/* AVB2_LINK */
4212 		[ 4] = RCAR_GP_PIN(5,  4),	/* AVB2_PHY_INT */
4213 		[ 5] = RCAR_GP_PIN(5,  5),	/* AVB2_MAGIC */
4214 		[ 6] = RCAR_GP_PIN(5,  6),	/* AVB2_MDC */
4215 		[ 7] = RCAR_GP_PIN(5,  7),	/* AVB2_TXCREFCLK */
4216 		[ 8] = RCAR_GP_PIN(5,  8),	/* AVB2_TD3 */
4217 		[ 9] = RCAR_GP_PIN(5,  9),	/* AVB2_RD3 */
4218 		[10] = RCAR_GP_PIN(5, 10),	/* AVB2_MDIO */
4219 		[11] = RCAR_GP_PIN(5, 11),	/* AVB2_TD2 */
4220 		[12] = RCAR_GP_PIN(5, 12),	/* AVB2_TD1 */
4221 		[13] = RCAR_GP_PIN(5, 13),	/* AVB2_RD2 */
4222 		[14] = RCAR_GP_PIN(5, 14),	/* AVB2_RD1 */
4223 		[15] = RCAR_GP_PIN(5, 15),	/* AVB2_TD0 */
4224 		[16] = RCAR_GP_PIN(5, 16),	/* AVB2_TXC */
4225 		[17] = RCAR_GP_PIN(5, 17),	/* AVB2_RD0 */
4226 		[18] = RCAR_GP_PIN(5, 18),	/* AVB2_RXC */
4227 		[19] = RCAR_GP_PIN(5, 19),	/* AVB2_TX_CTL */
4228 		[20] = RCAR_GP_PIN(5, 20),	/* AVB2_RX_CTL */
4229 		[21] = SH_PFC_PIN_NONE,
4230 		[22] = SH_PFC_PIN_NONE,
4231 		[23] = SH_PFC_PIN_NONE,
4232 		[24] = SH_PFC_PIN_NONE,
4233 		[25] = SH_PFC_PIN_NONE,
4234 		[26] = SH_PFC_PIN_NONE,
4235 		[27] = SH_PFC_PIN_NONE,
4236 		[28] = SH_PFC_PIN_NONE,
4237 		[29] = SH_PFC_PIN_NONE,
4238 		[30] = SH_PFC_PIN_NONE,
4239 		[31] = SH_PFC_PIN_NONE,
4240 	} },
4241 	{ PINMUX_BIAS_REG("PUEN6", 0xE60610C0, "PUD6", 0xE60610E0) {
4242 		[ 0] = RCAR_GP_PIN(6,  0),	/* AVB1_MDIO */
4243 		[ 1] = RCAR_GP_PIN(6,  1),	/* AVB1_MAGIC */
4244 		[ 2] = RCAR_GP_PIN(6,  2),	/* AVB1_MDC */
4245 		[ 3] = RCAR_GP_PIN(6,  3),	/* AVB1_PHY_INT */
4246 		[ 4] = RCAR_GP_PIN(6,  4),	/* AVB1_LINK */
4247 		[ 5] = RCAR_GP_PIN(6,  5),	/* AVB1_AVTP_MATCH */
4248 		[ 6] = RCAR_GP_PIN(6,  6),	/* AVB1_TXC */
4249 		[ 7] = RCAR_GP_PIN(6,  7),	/* AVB1_TX_CTL */
4250 		[ 8] = RCAR_GP_PIN(6,  8),	/* AVB1_RXC */
4251 		[ 9] = RCAR_GP_PIN(6,  9),	/* AVB1_RX_CTL */
4252 		[10] = RCAR_GP_PIN(6, 10),	/* AVB1_AVTP_PPS */
4253 		[11] = RCAR_GP_PIN(6, 11),	/* AVB1_AVTP_CAPTURE */
4254 		[12] = RCAR_GP_PIN(6, 12),	/* AVB1_TD1 */
4255 		[13] = RCAR_GP_PIN(6, 13),	/* AVB1_TD0 */
4256 		[14] = RCAR_GP_PIN(6, 14),	/* AVB1_RD1*/
4257 		[15] = RCAR_GP_PIN(6, 15),	/* AVB1_RD0 */
4258 		[16] = RCAR_GP_PIN(6, 16),	/* AVB1_TD2 */
4259 		[17] = RCAR_GP_PIN(6, 17),	/* AVB1_RD2 */
4260 		[18] = RCAR_GP_PIN(6, 18),	/* AVB1_TD3 */
4261 		[19] = RCAR_GP_PIN(6, 19),	/* AVB1_RD3 */
4262 		[20] = RCAR_GP_PIN(6, 20),	/* AVB1_TXCREFCLK */
4263 		[21] = SH_PFC_PIN_NONE,
4264 		[22] = SH_PFC_PIN_NONE,
4265 		[23] = SH_PFC_PIN_NONE,
4266 		[24] = SH_PFC_PIN_NONE,
4267 		[25] = SH_PFC_PIN_NONE,
4268 		[26] = SH_PFC_PIN_NONE,
4269 		[27] = SH_PFC_PIN_NONE,
4270 		[28] = SH_PFC_PIN_NONE,
4271 		[29] = SH_PFC_PIN_NONE,
4272 		[30] = SH_PFC_PIN_NONE,
4273 		[31] = SH_PFC_PIN_NONE,
4274 	} },
4275 	{ PINMUX_BIAS_REG("PUEN7", 0xE60618C0, "PUD7", 0xE60618E0) {
4276 		[ 0] = RCAR_GP_PIN(7,  0),	/* AVB0_AVTP_PPS */
4277 		[ 1] = RCAR_GP_PIN(7,  1),	/* AVB0_AVTP_CAPTURE */
4278 		[ 2] = RCAR_GP_PIN(7,  2),	/* AVB0_AVTP_MATCH */
4279 		[ 3] = RCAR_GP_PIN(7,  3),	/* AVB0_TD3 */
4280 		[ 4] = RCAR_GP_PIN(7,  4),	/* AVB0_LINK */
4281 		[ 5] = RCAR_GP_PIN(7,  5),	/* AVB0_PHY_INT */
4282 		[ 6] = RCAR_GP_PIN(7,  6),	/* AVB0_TD2 */
4283 		[ 7] = RCAR_GP_PIN(7,  7),	/* AVB0_TD1 */
4284 		[ 8] = RCAR_GP_PIN(7,  8),	/* AVB0_RD3 */
4285 		[ 9] = RCAR_GP_PIN(7,  9),	/* AVB0_TXCREFCLK */
4286 		[10] = RCAR_GP_PIN(7, 10),	/* AVB0_MAGIC */
4287 		[11] = RCAR_GP_PIN(7, 11),	/* AVB0_TD0 */
4288 		[12] = RCAR_GP_PIN(7, 12),	/* AVB0_RD2 */
4289 		[13] = RCAR_GP_PIN(7, 13),	/* AVB0_MDC */
4290 		[14] = RCAR_GP_PIN(7, 14),	/* AVB0_MDIO */
4291 		[15] = RCAR_GP_PIN(7, 15),	/* AVB0_TXC */
4292 		[16] = RCAR_GP_PIN(7, 16),	/* AVB0_TX_CTL */
4293 		[17] = RCAR_GP_PIN(7, 17),	/* AVB0_RD1 */
4294 		[18] = RCAR_GP_PIN(7, 18),	/* AVB0_RD0 */
4295 		[19] = RCAR_GP_PIN(7, 19),	/* AVB0_RXC */
4296 		[20] = RCAR_GP_PIN(7, 20),	/* AVB0_RX_CTL */
4297 		[21] = SH_PFC_PIN_NONE,
4298 		[22] = SH_PFC_PIN_NONE,
4299 		[23] = SH_PFC_PIN_NONE,
4300 		[24] = SH_PFC_PIN_NONE,
4301 		[25] = SH_PFC_PIN_NONE,
4302 		[26] = SH_PFC_PIN_NONE,
4303 		[27] = SH_PFC_PIN_NONE,
4304 		[28] = SH_PFC_PIN_NONE,
4305 		[29] = SH_PFC_PIN_NONE,
4306 		[30] = SH_PFC_PIN_NONE,
4307 		[31] = SH_PFC_PIN_NONE,
4308 	} },
4309 	{ PINMUX_BIAS_REG("PUEN8", 0xE60680C0, "PUD8", 0xE60680E0) {
4310 		[ 0] = RCAR_GP_PIN(8,  0),	/* SCL0 */
4311 		[ 1] = RCAR_GP_PIN(8,  1),	/* SDA0 */
4312 		[ 2] = RCAR_GP_PIN(8,  2),	/* SCL1 */
4313 		[ 3] = RCAR_GP_PIN(8,  3),	/* SDA1 */
4314 		[ 4] = RCAR_GP_PIN(8,  4),	/* SCL2 */
4315 		[ 5] = RCAR_GP_PIN(8,  5),	/* SDA2 */
4316 		[ 6] = RCAR_GP_PIN(8,  6),	/* SCL3 */
4317 		[ 7] = RCAR_GP_PIN(8,  7),	/* SDA3 */
4318 		[ 8] = RCAR_GP_PIN(8,  8),	/* SCL4 */
4319 		[ 9] = RCAR_GP_PIN(8,  9),	/* SDA4 */
4320 		[10] = RCAR_GP_PIN(8, 10),	/* SCL5 */
4321 		[11] = RCAR_GP_PIN(8, 11),	/* SDA5 */
4322 		[12] = RCAR_GP_PIN(8, 12),	/* GP8_12 */
4323 		[13] = RCAR_GP_PIN(8, 13),	/* GP8_13 */
4324 		[14] = SH_PFC_PIN_NONE,
4325 		[15] = SH_PFC_PIN_NONE,
4326 		[16] = SH_PFC_PIN_NONE,
4327 		[17] = SH_PFC_PIN_NONE,
4328 		[18] = SH_PFC_PIN_NONE,
4329 		[19] = SH_PFC_PIN_NONE,
4330 		[20] = SH_PFC_PIN_NONE,
4331 		[21] = SH_PFC_PIN_NONE,
4332 		[22] = SH_PFC_PIN_NONE,
4333 		[23] = SH_PFC_PIN_NONE,
4334 		[24] = SH_PFC_PIN_NONE,
4335 		[25] = SH_PFC_PIN_NONE,
4336 		[26] = SH_PFC_PIN_NONE,
4337 		[27] = SH_PFC_PIN_NONE,
4338 		[28] = SH_PFC_PIN_NONE,
4339 		[29] = SH_PFC_PIN_NONE,
4340 		[30] = SH_PFC_PIN_NONE,
4341 		[31] = SH_PFC_PIN_NONE,
4342 	} },
4343 	{ /* sentinel */ }
4344 };
4345 
4346 static const struct sh_pfc_soc_operations r8a779g0_pin_ops = {
4347 	.pin_to_pocctrl = r8a779g0_pin_to_pocctrl,
4348 	.get_bias = rcar_pinmux_get_bias,
4349 	.set_bias = rcar_pinmux_set_bias,
4350 };
4351 
4352 const struct sh_pfc_soc_info r8a779g0_pinmux_info = {
4353 	.name = "r8a779g0_pfc",
4354 	.ops = &r8a779g0_pin_ops,
4355 	.unlock_reg = 0x1ff,	/* PMMRn mask */
4356 
4357 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
4358 
4359 	.pins = pinmux_pins,
4360 	.nr_pins = ARRAY_SIZE(pinmux_pins),
4361 	.groups = pinmux_groups,
4362 	.nr_groups = ARRAY_SIZE(pinmux_groups),
4363 	.functions = pinmux_functions,
4364 	.nr_functions = ARRAY_SIZE(pinmux_functions),
4365 
4366 	.cfg_regs = pinmux_config_regs,
4367 	.drive_regs = pinmux_drive_regs,
4368 	.bias_regs = pinmux_bias_regs,
4369 	.ioctrl_regs = pinmux_ioctrl_regs,
4370 
4371 	.pinmux_data = pinmux_data,
4372 	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
4373 };
4374