1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * R8A77990 processor support - PFC hardware block. 4 * 5 * Copyright (C) 2018-2019 Renesas Electronics Corp. 6 * 7 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c 8 * 9 * R8A7796 processor support - PFC hardware block. 10 * 11 * Copyright (C) 2016-2017 Renesas Electronics Corp. 12 */ 13 14 #include <linux/errno.h> 15 #include <linux/kernel.h> 16 17 #include "core.h" 18 #include "sh_pfc.h" 19 20 #define CFG_FLAGS (SH_PFC_PIN_CFG_PULL_UP_DOWN) 21 22 #define CPU_ALL_GP(fn, sfx) \ 23 PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \ 24 PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \ 25 PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \ 26 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ 27 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \ 28 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \ 29 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \ 30 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \ 31 PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ 32 PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \ 33 PORT_GP_CFG_9(6, fn, sfx, CFG_FLAGS), \ 34 PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 35 PORT_GP_CFG_1(6, 10, fn, sfx, CFG_FLAGS), \ 36 PORT_GP_CFG_1(6, 11, fn, sfx, CFG_FLAGS), \ 37 PORT_GP_CFG_1(6, 12, fn, sfx, CFG_FLAGS), \ 38 PORT_GP_CFG_1(6, 13, fn, sfx, CFG_FLAGS), \ 39 PORT_GP_CFG_1(6, 14, fn, sfx, CFG_FLAGS), \ 40 PORT_GP_CFG_1(6, 15, fn, sfx, CFG_FLAGS), \ 41 PORT_GP_CFG_1(6, 16, fn, sfx, CFG_FLAGS), \ 42 PORT_GP_CFG_1(6, 17, fn, sfx, CFG_FLAGS) 43 44 #define CPU_ALL_NOGP(fn) \ 45 PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \ 46 PIN_NOGP_CFG(AVB_MDC, "AVB_MDC", fn, CFG_FLAGS), \ 47 PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \ 48 PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \ 49 PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \ 50 PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \ 51 PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \ 52 PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \ 53 PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \ 54 PIN_NOGP_CFG(FSCLKST_N, "FSCLKST_N", fn, CFG_FLAGS), \ 55 PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \ 56 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT_N", fn, CFG_FLAGS), \ 57 PIN_NOGP_CFG(TCK, "TCK", fn, CFG_FLAGS), \ 58 PIN_NOGP_CFG(TDI, "TDI", fn, CFG_FLAGS), \ 59 PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \ 60 PIN_NOGP_CFG(TRST_N, "TRST_N", fn, CFG_FLAGS) 61 62 /* 63 * F_() : just information 64 * FM() : macro for FN_xxx / xxx_MARK 65 */ 66 67 /* GPSR0 */ 68 #define GPSR0_17 F_(SDA4, IP7_27_24) 69 #define GPSR0_16 F_(SCL4, IP7_23_20) 70 #define GPSR0_15 F_(D15, IP7_19_16) 71 #define GPSR0_14 F_(D14, IP7_15_12) 72 #define GPSR0_13 F_(D13, IP7_11_8) 73 #define GPSR0_12 F_(D12, IP7_7_4) 74 #define GPSR0_11 F_(D11, IP7_3_0) 75 #define GPSR0_10 F_(D10, IP6_31_28) 76 #define GPSR0_9 F_(D9, IP6_27_24) 77 #define GPSR0_8 F_(D8, IP6_23_20) 78 #define GPSR0_7 F_(D7, IP6_19_16) 79 #define GPSR0_6 F_(D6, IP6_15_12) 80 #define GPSR0_5 F_(D5, IP6_11_8) 81 #define GPSR0_4 F_(D4, IP6_7_4) 82 #define GPSR0_3 F_(D3, IP6_3_0) 83 #define GPSR0_2 F_(D2, IP5_31_28) 84 #define GPSR0_1 F_(D1, IP5_27_24) 85 #define GPSR0_0 F_(D0, IP5_23_20) 86 87 /* GPSR1 */ 88 #define GPSR1_22 F_(WE0_N, IP5_19_16) 89 #define GPSR1_21 F_(CS0_N, IP5_15_12) 90 #define GPSR1_20 FM(CLKOUT) 91 #define GPSR1_19 F_(A19, IP5_11_8) 92 #define GPSR1_18 F_(A18, IP5_7_4) 93 #define GPSR1_17 F_(A17, IP5_3_0) 94 #define GPSR1_16 F_(A16, IP4_31_28) 95 #define GPSR1_15 F_(A15, IP4_27_24) 96 #define GPSR1_14 F_(A14, IP4_23_20) 97 #define GPSR1_13 F_(A13, IP4_19_16) 98 #define GPSR1_12 F_(A12, IP4_15_12) 99 #define GPSR1_11 F_(A11, IP4_11_8) 100 #define GPSR1_10 F_(A10, IP4_7_4) 101 #define GPSR1_9 F_(A9, IP4_3_0) 102 #define GPSR1_8 F_(A8, IP3_31_28) 103 #define GPSR1_7 F_(A7, IP3_27_24) 104 #define GPSR1_6 F_(A6, IP3_23_20) 105 #define GPSR1_5 F_(A5, IP3_19_16) 106 #define GPSR1_4 F_(A4, IP3_15_12) 107 #define GPSR1_3 F_(A3, IP3_11_8) 108 #define GPSR1_2 F_(A2, IP3_7_4) 109 #define GPSR1_1 F_(A1, IP3_3_0) 110 #define GPSR1_0 F_(A0, IP2_31_28) 111 112 /* GPSR2 */ 113 #define GPSR2_25 F_(EX_WAIT0, IP2_27_24) 114 #define GPSR2_24 F_(RD_WR_N, IP2_23_20) 115 #define GPSR2_23 F_(RD_N, IP2_19_16) 116 #define GPSR2_22 F_(BS_N, IP2_15_12) 117 #define GPSR2_21 FM(AVB_PHY_INT) 118 #define GPSR2_20 F_(AVB_TXCREFCLK, IP2_3_0) 119 #define GPSR2_19 FM(AVB_RD3) 120 #define GPSR2_18 F_(AVB_RD2, IP1_31_28) 121 #define GPSR2_17 F_(AVB_RD1, IP1_27_24) 122 #define GPSR2_16 F_(AVB_RD0, IP1_23_20) 123 #define GPSR2_15 FM(AVB_RXC) 124 #define GPSR2_14 FM(AVB_RX_CTL) 125 #define GPSR2_13 F_(RPC_RESET_N, IP1_19_16) 126 #define GPSR2_12 F_(RPC_INT_N, IP1_15_12) 127 #define GPSR2_11 F_(QSPI1_SSL, IP1_11_8) 128 #define GPSR2_10 F_(QSPI1_IO3, IP1_7_4) 129 #define GPSR2_9 F_(QSPI1_IO2, IP1_3_0) 130 #define GPSR2_8 F_(QSPI1_MISO_IO1, IP0_31_28) 131 #define GPSR2_7 F_(QSPI1_MOSI_IO0, IP0_27_24) 132 #define GPSR2_6 F_(QSPI1_SPCLK, IP0_23_20) 133 #define GPSR2_5 FM(QSPI0_SSL) 134 #define GPSR2_4 F_(QSPI0_IO3, IP0_19_16) 135 #define GPSR2_3 F_(QSPI0_IO2, IP0_15_12) 136 #define GPSR2_2 F_(QSPI0_MISO_IO1, IP0_11_8) 137 #define GPSR2_1 F_(QSPI0_MOSI_IO0, IP0_7_4) 138 #define GPSR2_0 F_(QSPI0_SPCLK, IP0_3_0) 139 140 /* GPSR3 */ 141 #define GPSR3_15 F_(SD1_WP, IP11_7_4) 142 #define GPSR3_14 F_(SD1_CD, IP11_3_0) 143 #define GPSR3_13 F_(SD0_WP, IP10_31_28) 144 #define GPSR3_12 F_(SD0_CD, IP10_27_24) 145 #define GPSR3_11 F_(SD1_DAT3, IP9_11_8) 146 #define GPSR3_10 F_(SD1_DAT2, IP9_7_4) 147 #define GPSR3_9 F_(SD1_DAT1, IP9_3_0) 148 #define GPSR3_8 F_(SD1_DAT0, IP8_31_28) 149 #define GPSR3_7 F_(SD1_CMD, IP8_27_24) 150 #define GPSR3_6 F_(SD1_CLK, IP8_23_20) 151 #define GPSR3_5 F_(SD0_DAT3, IP8_19_16) 152 #define GPSR3_4 F_(SD0_DAT2, IP8_15_12) 153 #define GPSR3_3 F_(SD0_DAT1, IP8_11_8) 154 #define GPSR3_2 F_(SD0_DAT0, IP8_7_4) 155 #define GPSR3_1 F_(SD0_CMD, IP8_3_0) 156 #define GPSR3_0 F_(SD0_CLK, IP7_31_28) 157 158 /* GPSR4 */ 159 #define GPSR4_10 F_(SD3_DS, IP10_23_20) 160 #define GPSR4_9 F_(SD3_DAT7, IP10_19_16) 161 #define GPSR4_8 F_(SD3_DAT6, IP10_15_12) 162 #define GPSR4_7 F_(SD3_DAT5, IP10_11_8) 163 #define GPSR4_6 F_(SD3_DAT4, IP10_7_4) 164 #define GPSR4_5 F_(SD3_DAT3, IP10_3_0) 165 #define GPSR4_4 F_(SD3_DAT2, IP9_31_28) 166 #define GPSR4_3 F_(SD3_DAT1, IP9_27_24) 167 #define GPSR4_2 F_(SD3_DAT0, IP9_23_20) 168 #define GPSR4_1 F_(SD3_CMD, IP9_19_16) 169 #define GPSR4_0 F_(SD3_CLK, IP9_15_12) 170 171 /* GPSR5 */ 172 #define GPSR5_19 F_(MLB_DAT, IP13_23_20) 173 #define GPSR5_18 F_(MLB_SIG, IP13_19_16) 174 #define GPSR5_17 F_(MLB_CLK, IP13_15_12) 175 #define GPSR5_16 F_(SSI_SDATA9, IP13_11_8) 176 #define GPSR5_15 F_(MSIOF0_SS2, IP13_7_4) 177 #define GPSR5_14 F_(MSIOF0_SS1, IP13_3_0) 178 #define GPSR5_13 F_(MSIOF0_SYNC, IP12_31_28) 179 #define GPSR5_12 F_(MSIOF0_TXD, IP12_27_24) 180 #define GPSR5_11 F_(MSIOF0_RXD, IP12_23_20) 181 #define GPSR5_10 F_(MSIOF0_SCK, IP12_19_16) 182 #define GPSR5_9 F_(RX2_A, IP12_15_12) 183 #define GPSR5_8 F_(TX2_A, IP12_11_8) 184 #define GPSR5_7 F_(SCK2_A, IP12_7_4) 185 #define GPSR5_6 F_(TX1, IP12_3_0) 186 #define GPSR5_5 F_(RX1, IP11_31_28) 187 #define GPSR5_4 F_(RTS0_N_A, IP11_23_20) 188 #define GPSR5_3 F_(CTS0_N_A, IP11_19_16) 189 #define GPSR5_2 F_(TX0_A, IP11_15_12) 190 #define GPSR5_1 F_(RX0_A, IP11_11_8) 191 #define GPSR5_0 F_(SCK0_A, IP11_27_24) 192 193 /* GPSR6 */ 194 #define GPSR6_17 F_(USB30_PWEN, IP15_27_24) 195 #define GPSR6_16 F_(SSI_SDATA6, IP15_19_16) 196 #define GPSR6_15 F_(SSI_WS6, IP15_15_12) 197 #define GPSR6_14 F_(SSI_SCK6, IP15_11_8) 198 #define GPSR6_13 F_(SSI_SDATA5, IP15_7_4) 199 #define GPSR6_12 F_(SSI_WS5, IP15_3_0) 200 #define GPSR6_11 F_(SSI_SCK5, IP14_31_28) 201 #define GPSR6_10 F_(SSI_SDATA4, IP14_27_24) 202 #define GPSR6_9 F_(USB30_OVC, IP15_31_28) 203 #define GPSR6_8 F_(AUDIO_CLKA, IP15_23_20) 204 #define GPSR6_7 F_(SSI_SDATA3, IP14_23_20) 205 #define GPSR6_6 F_(SSI_WS349, IP14_19_16) 206 #define GPSR6_5 F_(SSI_SCK349, IP14_15_12) 207 #define GPSR6_4 F_(SSI_SDATA2, IP14_11_8) 208 #define GPSR6_3 F_(SSI_SDATA1, IP14_7_4) 209 #define GPSR6_2 F_(SSI_SDATA0, IP14_3_0) 210 #define GPSR6_1 F_(SSI_WS01239, IP13_31_28) 211 #define GPSR6_0 F_(SSI_SCK01239, IP13_27_24) 212 213 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */ 214 #define IP0_3_0 FM(QSPI0_SPCLK) FM(HSCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 215 #define IP0_7_4 FM(QSPI0_MOSI_IO0) FM(HCTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 216 #define IP0_11_8 FM(QSPI0_MISO_IO1) FM(HRTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 217 #define IP0_15_12 FM(QSPI0_IO2) FM(HTX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 218 #define IP0_19_16 FM(QSPI0_IO3) FM(HRX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 219 #define IP0_23_20 FM(QSPI1_SPCLK) FM(RIF2_CLK_A) FM(HSCK4_B) FM(VI4_DATA0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 220 #define IP0_27_24 FM(QSPI1_MOSI_IO0) FM(RIF2_SYNC_A) FM(HTX4_B) FM(VI4_DATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 221 #define IP0_31_28 FM(QSPI1_MISO_IO1) FM(RIF2_D0_A) FM(HRX4_B) FM(VI4_DATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 222 #define IP1_3_0 FM(QSPI1_IO2) FM(RIF2_D1_A) FM(HTX3_C) FM(VI4_DATA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 223 #define IP1_7_4 FM(QSPI1_IO3) FM(RIF3_CLK_A) FM(HRX3_C) FM(VI4_DATA4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 224 #define IP1_11_8 FM(QSPI1_SSL) FM(RIF3_SYNC_A) FM(HSCK3_C) FM(VI4_DATA5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 225 #define IP1_15_12 FM(RPC_INT_N) FM(RIF3_D0_A) FM(HCTS3_N_C) FM(VI4_DATA6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 226 #define IP1_19_16 FM(RPC_RESET_N) FM(RIF3_D1_A) FM(HRTS3_N_C) FM(VI4_DATA7_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 227 #define IP1_23_20 FM(AVB_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 228 #define IP1_27_24 FM(AVB_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 229 #define IP1_31_28 FM(AVB_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 230 #define IP2_3_0 FM(AVB_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 231 #define IP2_7_4 FM(AVB_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 232 #define IP2_11_8 FM(AVB_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 233 #define IP2_15_12 FM(BS_N) FM(PWM0_A) FM(AVB_MAGIC) FM(VI4_CLK) F_(0, 0) FM(TX3_C) F_(0, 0) FM(VI5_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 234 #define IP2_19_16 FM(RD_N) FM(PWM1_A) FM(AVB_LINK) FM(VI4_FIELD) F_(0, 0) FM(RX3_C) FM(FSCLKST2_N_A) FM(VI5_DATA0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 235 #define IP2_23_20 FM(RD_WR_N) FM(SCL7_A) FM(AVB_AVTP_MATCH) FM(VI4_VSYNC_N) FM(TX5_B) FM(SCK3_C) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 236 #define IP2_27_24 FM(EX_WAIT0) FM(SDA7_A) FM(AVB_AVTP_CAPTURE) FM(VI4_HSYNC_N) FM(RX5_B) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 237 #define IP2_31_28 FM(A0) FM(IRQ0) FM(PWM2_A) FM(MSIOF3_SS1_B) FM(VI5_CLK_A) FM(DU_CDE) FM(HRX3_D) FM(IERX) FM(QSTB_QHE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 238 #define IP3_3_0 FM(A1) FM(IRQ1) FM(PWM3_A) FM(DU_DOTCLKIN1) FM(VI5_DATA0_A) FM(DU_DISP_CDE) FM(SDA6_B) FM(IETX) FM(QCPV_QDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 239 #define IP3_7_4 FM(A2) FM(IRQ2) FM(AVB_AVTP_PPS) FM(VI4_CLKENB) FM(VI5_DATA1_A) FM(DU_DISP) FM(SCL6_B) F_(0, 0) FM(QSTVB_QVE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 240 #define IP3_11_8 FM(A3) FM(CTS4_N_A) FM(PWM4_A) FM(VI4_DATA12) F_(0, 0) FM(DU_DOTCLKOUT0) FM(HTX3_D) FM(IECLK) FM(LCDOUT12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 241 #define IP3_15_12 FM(A4) FM(RTS4_N_A) FM(MSIOF3_SYNC_B) FM(VI4_DATA8) FM(PWM2_B) FM(DU_DG4) FM(RIF2_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 242 #define IP3_19_16 FM(A5) FM(SCK4_A) FM(MSIOF3_SCK_B) FM(VI4_DATA9) FM(PWM3_B) F_(0, 0) FM(RIF2_SYNC_B) F_(0, 0) FM(QPOLA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 243 #define IP3_23_20 FM(A6) FM(RX4_A) FM(MSIOF3_RXD_B) FM(VI4_DATA10) F_(0, 0) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 244 #define IP3_27_24 FM(A7) FM(TX4_A) FM(MSIOF3_TXD_B) FM(VI4_DATA11) F_(0, 0) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 245 #define IP3_31_28 FM(A8) FM(SDA6_A) FM(RX3_B) FM(HRX4_C) FM(VI5_HSYNC_N_A) FM(DU_HSYNC) FM(VI4_DATA0_B) F_(0, 0) FM(QSTH_QHS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 246 247 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */ 248 #define IP4_3_0 FM(A9) FM(TX5_A) FM(IRQ3) FM(VI4_DATA16) FM(VI5_VSYNC_N_A) FM(DU_DG7) F_(0, 0) F_(0, 0) FM(LCDOUT15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 249 #define IP4_7_4 FM(A10) FM(IRQ4) FM(MSIOF2_SYNC_B) FM(VI4_DATA13) FM(VI5_FIELD_A) FM(DU_DG5) FM(FSCLKST2_N_B) F_(0, 0) FM(LCDOUT13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 250 #define IP4_11_8 FM(A11) FM(SCL6_A) FM(TX3_B) FM(HTX4_C) F_(0, 0) FM(DU_VSYNC) FM(VI4_DATA1_B) F_(0, 0) FM(QSTVA_QVS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 251 #define IP4_15_12 FM(A12) FM(RX5_A) FM(MSIOF2_SS2_B) FM(VI4_DATA17) FM(VI5_DATA3_A) FM(DU_DG6) F_(0, 0) F_(0, 0) FM(LCDOUT14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 252 #define IP4_19_16 FM(A13) FM(SCK5_A) FM(MSIOF2_SCK_B) FM(VI4_DATA14) FM(HRX4_D) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(LCDOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 253 #define IP4_23_20 FM(A14) FM(MSIOF1_SS1) FM(MSIOF2_RXD_B) FM(VI4_DATA15) FM(HTX4_D) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(LCDOUT3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 254 #define IP4_27_24 FM(A15) FM(MSIOF1_SS2) FM(MSIOF2_TXD_B) FM(VI4_DATA18) FM(VI5_DATA4_A) FM(DU_DB4) F_(0, 0) F_(0, 0) FM(LCDOUT4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 255 #define IP4_31_28 FM(A16) FM(MSIOF1_SYNC) FM(MSIOF2_SS1_B) FM(VI4_DATA19) FM(VI5_DATA5_A) FM(DU_DB5) F_(0, 0) F_(0, 0) FM(LCDOUT5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 256 #define IP5_3_0 FM(A17) FM(MSIOF1_RXD) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA6_A) FM(DU_DB6) F_(0, 0) F_(0, 0) FM(LCDOUT6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 257 #define IP5_7_4 FM(A18) FM(MSIOF1_TXD) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA7_A) FM(DU_DB0) F_(0, 0) FM(HRX4_E) FM(LCDOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 258 #define IP5_11_8 FM(A19) FM(MSIOF1_SCK) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA2_A) FM(DU_DB1) F_(0, 0) FM(HTX4_E) FM(LCDOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 259 #define IP5_15_12 FM(CS0_N) FM(SCL5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR0) FM(VI4_DATA2_B) F_(0, 0) FM(LCDOUT16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 260 #define IP5_19_16 FM(WE0_N) FM(SDA5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR1) FM(VI4_DATA3_B) F_(0, 0) FM(LCDOUT17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 261 #define IP5_23_20 FM(D0) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR2) FM(CTS4_N_C) F_(0, 0) FM(LCDOUT18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 262 #define IP5_27_24 FM(D1) FM(MSIOF3_SYNC_A) FM(SCK3_A) FM(VI4_DATA23) FM(VI5_CLKENB_A) FM(DU_DB7) FM(RTS4_N_C) F_(0, 0) FM(LCDOUT7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 263 #define IP5_31_28 FM(D2) FM(MSIOF3_RXD_A) FM(RX5_C) F_(0, 0) FM(VI5_DATA14_A) FM(DU_DR3) FM(RX4_C) F_(0, 0) FM(LCDOUT19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 264 #define IP6_3_0 FM(D3) FM(MSIOF3_TXD_A) FM(TX5_C) F_(0, 0) FM(VI5_DATA15_A) FM(DU_DR4) FM(TX4_C) F_(0, 0) FM(LCDOUT20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 265 #define IP6_7_4 FM(D4) FM(CANFD1_TX) FM(HSCK3_B) FM(CAN1_TX) FM(RTS3_N_A) FM(MSIOF3_SS2_A) F_(0, 0) FM(VI5_DATA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 266 #define IP6_11_8 FM(D5) FM(RX3_A) FM(HRX3_B) F_(0, 0) F_(0, 0) FM(DU_DR5) FM(VI4_DATA4_B) F_(0, 0) FM(LCDOUT21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 267 #define IP6_15_12 FM(D6) FM(TX3_A) FM(HTX3_B) F_(0, 0) F_(0, 0) FM(DU_DR6) FM(VI4_DATA5_B) F_(0, 0) FM(LCDOUT22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 268 #define IP6_19_16 FM(D7) FM(CANFD1_RX) FM(IRQ5) FM(CAN1_RX) FM(CTS3_N_A) F_(0, 0) F_(0, 0) FM(VI5_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 269 #define IP6_23_20 FM(D8) FM(MSIOF2_SCK_A) FM(SCK4_B) F_(0, 0) FM(VI5_DATA12_A) FM(DU_DR7) FM(RIF3_CLK_B) FM(HCTS3_N_E) FM(LCDOUT23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 270 #define IP6_27_24 FM(D9) FM(MSIOF2_SYNC_A) F_(0, 0) F_(0, 0) FM(VI5_DATA10_A) FM(DU_DG0) FM(RIF3_SYNC_B) FM(HRX3_E) FM(LCDOUT8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 271 #define IP6_31_28 FM(D10) FM(MSIOF2_RXD_A) F_(0, 0) F_(0, 0) FM(VI5_DATA13_A) FM(DU_DG1) FM(RIF3_D0_B) FM(HTX3_E) FM(LCDOUT9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 272 #define IP7_3_0 FM(D11) FM(MSIOF2_TXD_A) F_(0, 0) F_(0, 0) FM(VI5_DATA11_A) FM(DU_DG2) FM(RIF3_D1_B) FM(HRTS3_N_E) FM(LCDOUT10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 273 #define IP7_7_4 FM(D12) FM(CANFD0_TX) FM(TX4_B) FM(CAN0_TX) FM(VI5_DATA8_A) F_(0, 0) F_(0, 0) FM(VI5_DATA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 274 #define IP7_11_8 FM(D13) FM(CANFD0_RX) FM(RX4_B) FM(CAN0_RX) FM(VI5_DATA9_A) FM(SCL7_B) F_(0, 0) FM(VI5_DATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 275 #define IP7_15_12 FM(D14) FM(CAN_CLK) FM(HRX3_A) FM(MSIOF2_SS2_A) F_(0, 0) FM(SDA7_B) F_(0, 0) FM(VI5_DATA5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 276 #define IP7_19_16 FM(D15) FM(MSIOF2_SS1_A) FM(HTX3_A) FM(MSIOF3_SS1_A) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) FM(LCDOUT11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 277 #define IP7_23_20 FM(SCL4) FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DOTCLKIN0) FM(VI4_DATA6_B) FM(VI5_DATA6_B) FM(QCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 278 #define IP7_27_24 FM(SDA4) FM(WE1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI4_DATA7_B) FM(VI5_DATA7_B) FM(QPOLB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 279 #define IP7_31_28 FM(SD0_CLK) FM(NFDATA8) FM(SCL1_C) FM(HSCK1_B) FM(SDA2_E) FM(FMCLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 280 281 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */ 282 #define IP8_3_0 FM(SD0_CMD) FM(NFDATA9) F_(0, 0) FM(HRX1_B) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 283 #define IP8_7_4 FM(SD0_DAT0) FM(NFDATA10) F_(0, 0) FM(HTX1_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 284 #define IP8_11_8 FM(SD0_DAT1) FM(NFDATA11) FM(SDA2_C) FM(HCTS1_N_B) F_(0, 0) FM(FMIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 285 #define IP8_15_12 FM(SD0_DAT2) FM(NFDATA12) FM(SCL2_C) FM(HRTS1_N_B) F_(0, 0) FM(BPFCLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 286 #define IP8_19_16 FM(SD0_DAT3) FM(NFDATA13) FM(SDA1_C) FM(SCL2_E) FM(SPEEDIN_C) FM(REMOCON_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 287 #define IP8_23_20 FM(SD1_CLK) FM(NFDATA14_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 288 #define IP8_27_24 FM(SD1_CMD) FM(NFDATA15_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 289 #define IP8_31_28 FM(SD1_DAT0) FM(NFWP_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 290 #define IP9_3_0 FM(SD1_DAT1) FM(NFCE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 291 #define IP9_7_4 FM(SD1_DAT2) FM(NFALE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 292 #define IP9_11_8 FM(SD1_DAT3) FM(NFRB_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 293 #define IP9_15_12 FM(SD3_CLK) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 294 #define IP9_19_16 FM(SD3_CMD) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 295 #define IP9_23_20 FM(SD3_DAT0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 296 #define IP9_27_24 FM(SD3_DAT1) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 297 #define IP9_31_28 FM(SD3_DAT2) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 298 #define IP10_3_0 FM(SD3_DAT3) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 299 #define IP10_7_4 FM(SD3_DAT4) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 300 #define IP10_11_8 FM(SD3_DAT5) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 301 #define IP10_15_12 FM(SD3_DAT6) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 302 #define IP10_19_16 FM(SD3_DAT7) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 303 #define IP10_23_20 FM(SD3_DS) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 304 #define IP10_27_24 FM(SD0_CD) FM(NFALE_A) FM(SD3_CD) FM(RIF0_CLK_B) FM(SCL2_B) FM(TCLK1_A) FM(SSI_SCK2_B) FM(TS_SCK0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 305 #define IP10_31_28 FM(SD0_WP) FM(NFRB_N_A) FM(SD3_WP) FM(RIF0_D0_B) FM(SDA2_B) FM(TCLK2_A) FM(SSI_WS2_B) FM(TS_SDAT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 306 #define IP11_3_0 FM(SD1_CD) FM(NFCE_N_A) FM(SSI_SCK1) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 307 #define IP11_7_4 FM(SD1_WP) FM(NFWP_N_A) FM(SSI_WS1) FM(RIF0_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 308 #define IP11_11_8 FM(RX0_A) FM(HRX1_A) FM(SSI_SCK2_A) FM(RIF1_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 309 #define IP11_15_12 FM(TX0_A) FM(HTX1_A) FM(SSI_WS2_A) FM(RIF1_D0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 310 #define IP11_19_16 FM(CTS0_N_A) FM(NFDATA14_A) FM(AUDIO_CLKOUT_A) FM(RIF1_D1) FM(SCIF_CLK_A) FM(FMCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 311 #define IP11_23_20 FM(RTS0_N_A) FM(NFDATA15_A) FM(AUDIO_CLKOUT1_A) FM(RIF1_CLK) FM(SCL2_A) FM(FMIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 312 #define IP11_27_24 FM(SCK0_A) FM(HSCK1_A) FM(USB3HS0_ID) FM(RTS1_N) FM(SDA2_A) FM(FMCLK_C) F_(0, 0) F_(0, 0) FM(USB0_ID) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 313 #define IP11_31_28 FM(RX1) FM(HRX2_B) FM(SSI_SCK9_B) FM(AUDIO_CLKOUT1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 314 315 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */ 316 #define IP12_3_0 FM(TX1) FM(HTX2_B) FM(SSI_WS9_B) FM(AUDIO_CLKOUT3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 317 #define IP12_7_4 FM(SCK2_A) FM(HSCK0_A) FM(AUDIO_CLKB_A) FM(CTS1_N) FM(RIF0_CLK_A) FM(REMOCON_A) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 318 #define IP12_11_8 FM(TX2_A) FM(HRX0_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) FM(SCL1_A) F_(0, 0) FM(FSO_CFE_0_N_A) FM(TS_SDEN1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 319 #define IP12_15_12 FM(RX2_A) FM(HTX0_A) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(SDA1_A) F_(0, 0) FM(FSO_CFE_1_N_A) FM(TS_SPSYNC1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 320 #define IP12_19_16 FM(MSIOF0_SCK) F_(0, 0) FM(SSI_SCK78) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 321 #define IP12_23_20 FM(MSIOF0_RXD) F_(0, 0) FM(SSI_WS78) F_(0, 0) F_(0, 0) FM(TX2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 322 #define IP12_27_24 FM(MSIOF0_TXD) F_(0, 0) FM(SSI_SDATA7) F_(0, 0) F_(0, 0) FM(RX2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 323 #define IP12_31_28 FM(MSIOF0_SYNC) FM(AUDIO_CLKOUT_B) FM(SSI_SDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 324 #define IP13_3_0 FM(MSIOF0_SS1) FM(HRX2_A) FM(SSI_SCK4) FM(HCTS0_N_A) FM(BPFCLK_C) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 325 #define IP13_7_4 FM(MSIOF0_SS2) FM(HTX2_A) FM(SSI_WS4) FM(HRTS0_N_A) FM(FMIN_C) FM(BPFCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 326 #define IP13_11_8 FM(SSI_SDATA9) F_(0, 0) FM(AUDIO_CLKC_A) FM(SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 327 #define IP13_15_12 FM(MLB_CLK) FM(RX0_B) F_(0, 0) FM(RIF0_D0_A) FM(SCL1_B) FM(TCLK1_B) F_(0, 0) F_(0, 0) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 328 #define IP13_19_16 FM(MLB_SIG) FM(SCK0_B) F_(0, 0) FM(RIF0_D1_A) FM(SDA1_B) FM(TCLK2_B) F_(0, 0) F_(0, 0) FM(SIM0_D_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 329 #define IP13_23_20 FM(MLB_DAT) FM(TX0_B) F_(0, 0) FM(RIF0_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 330 #define IP13_27_24 FM(SSI_SCK01239) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 331 #define IP13_31_28 FM(SSI_WS01239) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 332 #define IP14_3_0 FM(SSI_SDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 333 #define IP14_7_4 FM(SSI_SDATA1) FM(AUDIO_CLKC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 334 #define IP14_11_8 FM(SSI_SDATA2) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 335 #define IP14_15_12 FM(SSI_SCK349) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 336 #define IP14_19_16 FM(SSI_WS349) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 337 #define IP14_23_20 FM(SSI_SDATA3) FM(AUDIO_CLKOUT1_C) FM(AUDIO_CLKB_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 338 #define IP14_27_24 FM(SSI_SDATA4) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 339 #define IP14_31_28 FM(SSI_SCK5) FM(HRX0_B) F_(0, 0) FM(USB0_PWEN_B) FM(SCL2_D) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 340 #define IP15_3_0 FM(SSI_WS5) FM(HTX0_B) F_(0, 0) FM(USB0_OVC_B) FM(SDA2_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 341 #define IP15_7_4 FM(SSI_SDATA5) FM(HSCK0_B) FM(AUDIO_CLKB_C) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 342 #define IP15_11_8 FM(SSI_SCK6) FM(HSCK2_A) FM(AUDIO_CLKC_C) FM(TPU0TO1) F_(0, 0) F_(0, 0) FM(FSO_CFE_0_N_B) F_(0, 0) FM(SIM0_RST_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 343 #define IP15_15_12 FM(SSI_WS6) FM(HCTS2_N_A) FM(AUDIO_CLKOUT2_C) FM(TPU0TO2) FM(SDA1_D) F_(0, 0) FM(FSO_CFE_1_N_B) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 344 #define IP15_19_16 FM(SSI_SDATA6) FM(HRTS2_N_A) FM(AUDIO_CLKOUT3_C) FM(TPU0TO3) FM(SCL1_D) F_(0, 0) FM(FSO_TOE_N_B) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 345 #define IP15_23_20 FM(AUDIO_CLKA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 346 #define IP15_27_24 FM(USB30_PWEN) FM(USB0_PWEN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 347 #define IP15_31_28 FM(USB30_OVC) FM(USB0_OVC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 348 349 #define PINMUX_GPSR \ 350 \ 351 \ 352 \ 353 \ 354 \ 355 \ 356 \ 357 GPSR2_25 \ 358 GPSR2_24 \ 359 GPSR2_23 \ 360 GPSR1_22 GPSR2_22 \ 361 GPSR1_21 GPSR2_21 \ 362 GPSR1_20 GPSR2_20 \ 363 GPSR1_19 GPSR2_19 GPSR5_19 \ 364 GPSR1_18 GPSR2_18 GPSR5_18 \ 365 GPSR0_17 GPSR1_17 GPSR2_17 GPSR5_17 GPSR6_17 \ 366 GPSR0_16 GPSR1_16 GPSR2_16 GPSR5_16 GPSR6_16 \ 367 GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR5_15 GPSR6_15 \ 368 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR5_14 GPSR6_14 \ 369 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR5_13 GPSR6_13 \ 370 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR5_12 GPSR6_12 \ 371 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR5_11 GPSR6_11 \ 372 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \ 373 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \ 374 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \ 375 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \ 376 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \ 377 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \ 378 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \ 379 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 \ 380 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 \ 381 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 \ 382 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 383 384 #define PINMUX_IPSR \ 385 \ 386 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \ 387 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \ 388 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \ 389 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \ 390 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \ 391 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \ 392 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ 393 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \ 394 \ 395 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ 396 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ 397 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ 398 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \ 399 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ 400 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ 401 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ 402 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ 403 \ 404 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \ 405 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \ 406 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \ 407 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \ 408 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \ 409 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \ 410 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \ 411 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \ 412 \ 413 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \ 414 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \ 415 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \ 416 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \ 417 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \ 418 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \ 419 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \ 420 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 421 422 /* The bit numbering in MOD_SEL fields is reversed */ 423 #define REV4(f0, f1, f2, f3) f0 f2 f1 f3 424 #define REV8(f0, f1, f2, f3, f4, f5, f6, f7) f0 f4 f2 f6 f1 f5 f3 f7 425 426 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 427 #define MOD_SEL0_30_29 REV4(FM(SEL_ADGB_0), FM(SEL_ADGB_1), FM(SEL_ADGB_2), F_(0, 0)) 428 #define MOD_SEL0_28 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) 429 #define MOD_SEL0_27_26 REV4(FM(SEL_FM_0), FM(SEL_FM_1), FM(SEL_FM_2), F_(0, 0)) 430 #define MOD_SEL0_25 FM(SEL_FSO_0) FM(SEL_FSO_1) 431 #define MOD_SEL0_24 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1) 432 #define MOD_SEL0_23 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1) 433 #define MOD_SEL0_22 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) 434 #define MOD_SEL0_21_20 REV4(FM(SEL_I2C1_0), FM(SEL_I2C1_1), FM(SEL_I2C1_2), FM(SEL_I2C1_3)) 435 #define MOD_SEL0_19_18_17 REV8(FM(SEL_I2C2_0), FM(SEL_I2C2_1), FM(SEL_I2C2_2), FM(SEL_I2C2_3), FM(SEL_I2C2_4), F_(0, 0), F_(0, 0), F_(0, 0)) 436 #define MOD_SEL0_16 FM(SEL_NDF_0) FM(SEL_NDF_1) 437 #define MOD_SEL0_15 FM(SEL_PWM0_0) FM(SEL_PWM0_1) 438 #define MOD_SEL0_14 FM(SEL_PWM1_0) FM(SEL_PWM1_1) 439 #define MOD_SEL0_13_12 REV4(FM(SEL_PWM2_0), FM(SEL_PWM2_1), FM(SEL_PWM2_2), F_(0, 0)) 440 #define MOD_SEL0_11_10 REV4(FM(SEL_PWM3_0), FM(SEL_PWM3_1), FM(SEL_PWM3_2), F_(0, 0)) 441 #define MOD_SEL0_9 FM(SEL_PWM4_0) FM(SEL_PWM4_1) 442 #define MOD_SEL0_8 FM(SEL_PWM5_0) FM(SEL_PWM5_1) 443 #define MOD_SEL0_7 FM(SEL_PWM6_0) FM(SEL_PWM6_1) 444 #define MOD_SEL0_6_5 REV4(FM(SEL_REMOCON_0), FM(SEL_REMOCON_1), FM(SEL_REMOCON_2), F_(0, 0)) 445 #define MOD_SEL0_4 FM(SEL_SCIF_0) FM(SEL_SCIF_1) 446 #define MOD_SEL0_3 FM(SEL_SCIF0_0) FM(SEL_SCIF0_1) 447 #define MOD_SEL0_2 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1) 448 #define MOD_SEL0_1_0 REV4(FM(SEL_SPEED_PULSE_IF_0), FM(SEL_SPEED_PULSE_IF_1), FM(SEL_SPEED_PULSE_IF_2), F_(0, 0)) 449 450 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 451 #define MOD_SEL1_31 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) 452 #define MOD_SEL1_30 FM(SEL_SSI2_0) FM(SEL_SSI2_1) 453 #define MOD_SEL1_29 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1) 454 #define MOD_SEL1_28 FM(SEL_USB_20_CH0_0) FM(SEL_USB_20_CH0_1) 455 #define MOD_SEL1_26 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1) 456 #define MOD_SEL1_25 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1) 457 #define MOD_SEL1_24_23_22 REV8(FM(SEL_HSCIF3_0), FM(SEL_HSCIF3_1), FM(SEL_HSCIF3_2), FM(SEL_HSCIF3_3), FM(SEL_HSCIF3_4), F_(0, 0), F_(0, 0), F_(0, 0)) 458 #define MOD_SEL1_21_20_19 REV8(FM(SEL_HSCIF4_0), FM(SEL_HSCIF4_1), FM(SEL_HSCIF4_2), FM(SEL_HSCIF4_3), FM(SEL_HSCIF4_4), F_(0, 0), F_(0, 0), F_(0, 0)) 459 #define MOD_SEL1_18 FM(SEL_I2C6_0) FM(SEL_I2C6_1) 460 #define MOD_SEL1_17 FM(SEL_I2C7_0) FM(SEL_I2C7_1) 461 #define MOD_SEL1_16 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) 462 #define MOD_SEL1_15 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) 463 #define MOD_SEL1_14_13 REV4(FM(SEL_SCIF3_0), FM(SEL_SCIF3_1), FM(SEL_SCIF3_2), F_(0, 0)) 464 #define MOD_SEL1_12_11 REV4(FM(SEL_SCIF4_0), FM(SEL_SCIF4_1), FM(SEL_SCIF4_2), F_(0, 0)) 465 #define MOD_SEL1_10_9 REV4(FM(SEL_SCIF5_0), FM(SEL_SCIF5_1), FM(SEL_SCIF5_2), F_(0, 0)) 466 #define MOD_SEL1_8 FM(SEL_VIN4_0) FM(SEL_VIN4_1) 467 #define MOD_SEL1_7 FM(SEL_VIN5_0) FM(SEL_VIN5_1) 468 #define MOD_SEL1_6_5 REV4(FM(SEL_ADGC_0), FM(SEL_ADGC_1), FM(SEL_ADGC_2), F_(0, 0)) 469 #define MOD_SEL1_4 FM(SEL_SSI9_0) FM(SEL_SSI9_1) 470 471 #define PINMUX_MOD_SELS \ 472 \ 473 MOD_SEL1_31 \ 474 MOD_SEL0_30_29 MOD_SEL1_30 \ 475 MOD_SEL1_29 \ 476 MOD_SEL0_28 MOD_SEL1_28 \ 477 MOD_SEL0_27_26 \ 478 MOD_SEL1_26 \ 479 MOD_SEL0_25 MOD_SEL1_25 \ 480 MOD_SEL0_24 MOD_SEL1_24_23_22 \ 481 MOD_SEL0_23 \ 482 MOD_SEL0_22 \ 483 MOD_SEL0_21_20 MOD_SEL1_21_20_19 \ 484 MOD_SEL0_19_18_17 MOD_SEL1_18 \ 485 MOD_SEL1_17 \ 486 MOD_SEL0_16 MOD_SEL1_16 \ 487 MOD_SEL0_15 MOD_SEL1_15 \ 488 MOD_SEL0_14 MOD_SEL1_14_13 \ 489 MOD_SEL0_13_12 \ 490 MOD_SEL1_12_11 \ 491 MOD_SEL0_11_10 \ 492 MOD_SEL1_10_9 \ 493 MOD_SEL0_9 \ 494 MOD_SEL0_8 MOD_SEL1_8 \ 495 MOD_SEL0_7 MOD_SEL1_7 \ 496 MOD_SEL0_6_5 MOD_SEL1_6_5 \ 497 MOD_SEL0_4 MOD_SEL1_4 \ 498 MOD_SEL0_3 \ 499 MOD_SEL0_2 \ 500 MOD_SEL0_1_0 501 502 /* 503 * These pins are not able to be muxed but have other properties 504 * that can be set, such as pull-up/pull-down enable. 505 */ 506 #define PINMUX_STATIC \ 507 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) \ 508 FM(AVB_TD3) \ 509 FM(PRESETOUT_N) FM(FSCLKST_N) FM(TRST_N) FM(TCK) FM(TMS) FM(TDI) \ 510 FM(ASEBRK) \ 511 FM(MLB_REF) 512 513 enum { 514 PINMUX_RESERVED = 0, 515 516 PINMUX_DATA_BEGIN, 517 GP_ALL(DATA), 518 PINMUX_DATA_END, 519 520 #define F_(x, y) 521 #define FM(x) FN_##x, 522 PINMUX_FUNCTION_BEGIN, 523 GP_ALL(FN), 524 PINMUX_GPSR 525 PINMUX_IPSR 526 PINMUX_MOD_SELS 527 PINMUX_FUNCTION_END, 528 #undef F_ 529 #undef FM 530 531 #define F_(x, y) 532 #define FM(x) x##_MARK, 533 PINMUX_MARK_BEGIN, 534 PINMUX_GPSR 535 PINMUX_IPSR 536 PINMUX_MOD_SELS 537 PINMUX_STATIC 538 PINMUX_MARK_END, 539 #undef F_ 540 #undef FM 541 }; 542 543 static const u16 pinmux_data[] = { 544 PINMUX_DATA_GP_ALL(), 545 546 PINMUX_SINGLE(CLKOUT), 547 PINMUX_SINGLE(AVB_PHY_INT), 548 PINMUX_SINGLE(AVB_RD3), 549 PINMUX_SINGLE(AVB_RXC), 550 PINMUX_SINGLE(AVB_RX_CTL), 551 PINMUX_SINGLE(QSPI0_SSL), 552 553 /* IPSR0 */ 554 PINMUX_IPSR_GPSR(IP0_3_0, QSPI0_SPCLK), 555 PINMUX_IPSR_MSEL(IP0_3_0, HSCK4_A, SEL_HSCIF4_0), 556 557 PINMUX_IPSR_GPSR(IP0_7_4, QSPI0_MOSI_IO0), 558 PINMUX_IPSR_MSEL(IP0_7_4, HCTS4_N_A, SEL_HSCIF4_0), 559 560 PINMUX_IPSR_GPSR(IP0_11_8, QSPI0_MISO_IO1), 561 PINMUX_IPSR_MSEL(IP0_11_8, HRTS4_N_A, SEL_HSCIF4_0), 562 563 PINMUX_IPSR_GPSR(IP0_15_12, QSPI0_IO2), 564 PINMUX_IPSR_GPSR(IP0_15_12, HTX4_A), 565 566 PINMUX_IPSR_GPSR(IP0_19_16, QSPI0_IO3), 567 PINMUX_IPSR_MSEL(IP0_19_16, HRX4_A, SEL_HSCIF4_0), 568 569 PINMUX_IPSR_GPSR(IP0_23_20, QSPI1_SPCLK), 570 PINMUX_IPSR_MSEL(IP0_23_20, RIF2_CLK_A, SEL_DRIF2_0), 571 PINMUX_IPSR_MSEL(IP0_23_20, HSCK4_B, SEL_HSCIF4_1), 572 PINMUX_IPSR_MSEL(IP0_23_20, VI4_DATA0_A, SEL_VIN4_0), 573 574 PINMUX_IPSR_GPSR(IP0_27_24, QSPI1_MOSI_IO0), 575 PINMUX_IPSR_MSEL(IP0_27_24, RIF2_SYNC_A, SEL_DRIF2_0), 576 PINMUX_IPSR_GPSR(IP0_27_24, HTX4_B), 577 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA1_A, SEL_VIN4_0), 578 579 PINMUX_IPSR_GPSR(IP0_31_28, QSPI1_MISO_IO1), 580 PINMUX_IPSR_MSEL(IP0_31_28, RIF2_D0_A, SEL_DRIF2_0), 581 PINMUX_IPSR_MSEL(IP0_31_28, HRX4_B, SEL_HSCIF4_1), 582 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA2_A, SEL_VIN4_0), 583 584 /* IPSR1 */ 585 PINMUX_IPSR_GPSR(IP1_3_0, QSPI1_IO2), 586 PINMUX_IPSR_MSEL(IP1_3_0, RIF2_D1_A, SEL_DRIF2_0), 587 PINMUX_IPSR_GPSR(IP1_3_0, HTX3_C), 588 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA3_A, SEL_VIN4_0), 589 590 PINMUX_IPSR_GPSR(IP1_7_4, QSPI1_IO3), 591 PINMUX_IPSR_MSEL(IP1_7_4, RIF3_CLK_A, SEL_DRIF3_0), 592 PINMUX_IPSR_MSEL(IP1_7_4, HRX3_C, SEL_HSCIF3_2), 593 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA4_A, SEL_VIN4_0), 594 595 PINMUX_IPSR_GPSR(IP1_11_8, QSPI1_SSL), 596 PINMUX_IPSR_MSEL(IP1_11_8, RIF3_SYNC_A, SEL_DRIF3_0), 597 PINMUX_IPSR_MSEL(IP1_11_8, HSCK3_C, SEL_HSCIF3_2), 598 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA5_A, SEL_VIN4_0), 599 600 PINMUX_IPSR_GPSR(IP1_15_12, RPC_INT_N), 601 PINMUX_IPSR_MSEL(IP1_15_12, RIF3_D0_A, SEL_DRIF3_0), 602 PINMUX_IPSR_MSEL(IP1_15_12, HCTS3_N_C, SEL_HSCIF3_2), 603 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA6_A, SEL_VIN4_0), 604 605 PINMUX_IPSR_GPSR(IP1_19_16, RPC_RESET_N), 606 PINMUX_IPSR_MSEL(IP1_19_16, RIF3_D1_A, SEL_DRIF3_0), 607 PINMUX_IPSR_MSEL(IP1_19_16, HRTS3_N_C, SEL_HSCIF3_2), 608 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA7_A, SEL_VIN4_0), 609 610 PINMUX_IPSR_GPSR(IP1_23_20, AVB_RD0), 611 612 PINMUX_IPSR_GPSR(IP1_27_24, AVB_RD1), 613 614 PINMUX_IPSR_GPSR(IP1_31_28, AVB_RD2), 615 616 /* IPSR2 */ 617 PINMUX_IPSR_GPSR(IP2_3_0, AVB_TXCREFCLK), 618 619 PINMUX_IPSR_GPSR(IP2_7_4, AVB_MDIO), 620 621 PINMUX_IPSR_GPSR(IP2_11_8, AVB_MDC), 622 623 PINMUX_IPSR_GPSR(IP2_15_12, BS_N), 624 PINMUX_IPSR_MSEL(IP2_15_12, PWM0_A, SEL_PWM0_0), 625 PINMUX_IPSR_GPSR(IP2_15_12, AVB_MAGIC), 626 PINMUX_IPSR_GPSR(IP2_15_12, VI4_CLK), 627 PINMUX_IPSR_GPSR(IP2_15_12, TX3_C), 628 PINMUX_IPSR_MSEL(IP2_15_12, VI5_CLK_B, SEL_VIN5_1), 629 630 PINMUX_IPSR_GPSR(IP2_19_16, RD_N), 631 PINMUX_IPSR_MSEL(IP2_19_16, PWM1_A, SEL_PWM1_0), 632 PINMUX_IPSR_GPSR(IP2_19_16, AVB_LINK), 633 PINMUX_IPSR_GPSR(IP2_19_16, VI4_FIELD), 634 PINMUX_IPSR_MSEL(IP2_19_16, RX3_C, SEL_SCIF3_2), 635 PINMUX_IPSR_GPSR(IP2_19_16, FSCLKST2_N_A), 636 PINMUX_IPSR_MSEL(IP2_19_16, VI5_DATA0_B, SEL_VIN5_1), 637 638 PINMUX_IPSR_GPSR(IP2_23_20, RD_WR_N), 639 PINMUX_IPSR_MSEL(IP2_23_20, SCL7_A, SEL_I2C7_0), 640 PINMUX_IPSR_GPSR(IP2_23_20, AVB_AVTP_MATCH), 641 PINMUX_IPSR_GPSR(IP2_23_20, VI4_VSYNC_N), 642 PINMUX_IPSR_GPSR(IP2_23_20, TX5_B), 643 PINMUX_IPSR_MSEL(IP2_23_20, SCK3_C, SEL_SCIF3_2), 644 PINMUX_IPSR_MSEL(IP2_23_20, PWM5_A, SEL_PWM5_0), 645 646 PINMUX_IPSR_GPSR(IP2_27_24, EX_WAIT0), 647 PINMUX_IPSR_MSEL(IP2_27_24, SDA7_A, SEL_I2C7_0), 648 PINMUX_IPSR_GPSR(IP2_27_24, AVB_AVTP_CAPTURE), 649 PINMUX_IPSR_GPSR(IP2_27_24, VI4_HSYNC_N), 650 PINMUX_IPSR_MSEL(IP2_27_24, RX5_B, SEL_SCIF5_1), 651 PINMUX_IPSR_MSEL(IP2_27_24, PWM6_A, SEL_PWM6_0), 652 653 PINMUX_IPSR_GPSR(IP2_31_28, A0), 654 PINMUX_IPSR_GPSR(IP2_31_28, IRQ0), 655 PINMUX_IPSR_MSEL(IP2_31_28, PWM2_A, SEL_PWM2_0), 656 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF3_SS1_B, SEL_MSIOF3_1), 657 PINMUX_IPSR_MSEL(IP2_31_28, VI5_CLK_A, SEL_VIN5_0), 658 PINMUX_IPSR_GPSR(IP2_31_28, DU_CDE), 659 PINMUX_IPSR_MSEL(IP2_31_28, HRX3_D, SEL_HSCIF3_3), 660 PINMUX_IPSR_GPSR(IP2_31_28, IERX), 661 PINMUX_IPSR_GPSR(IP2_31_28, QSTB_QHE), 662 663 /* IPSR3 */ 664 PINMUX_IPSR_GPSR(IP3_3_0, A1), 665 PINMUX_IPSR_GPSR(IP3_3_0, IRQ1), 666 PINMUX_IPSR_MSEL(IP3_3_0, PWM3_A, SEL_PWM3_0), 667 PINMUX_IPSR_GPSR(IP3_3_0, DU_DOTCLKIN1), 668 PINMUX_IPSR_MSEL(IP3_3_0, VI5_DATA0_A, SEL_VIN5_0), 669 PINMUX_IPSR_GPSR(IP3_3_0, DU_DISP_CDE), 670 PINMUX_IPSR_MSEL(IP3_3_0, SDA6_B, SEL_I2C6_1), 671 PINMUX_IPSR_GPSR(IP3_3_0, IETX), 672 PINMUX_IPSR_GPSR(IP3_3_0, QCPV_QDE), 673 674 PINMUX_IPSR_GPSR(IP3_7_4, A2), 675 PINMUX_IPSR_GPSR(IP3_7_4, IRQ2), 676 PINMUX_IPSR_GPSR(IP3_7_4, AVB_AVTP_PPS), 677 PINMUX_IPSR_GPSR(IP3_7_4, VI4_CLKENB), 678 PINMUX_IPSR_MSEL(IP3_7_4, VI5_DATA1_A, SEL_VIN5_0), 679 PINMUX_IPSR_GPSR(IP3_7_4, DU_DISP), 680 PINMUX_IPSR_MSEL(IP3_7_4, SCL6_B, SEL_I2C6_1), 681 PINMUX_IPSR_GPSR(IP3_7_4, QSTVB_QVE), 682 683 PINMUX_IPSR_GPSR(IP3_11_8, A3), 684 PINMUX_IPSR_MSEL(IP3_11_8, CTS4_N_A, SEL_SCIF4_0), 685 PINMUX_IPSR_MSEL(IP3_11_8, PWM4_A, SEL_PWM4_0), 686 PINMUX_IPSR_GPSR(IP3_11_8, VI4_DATA12), 687 PINMUX_IPSR_GPSR(IP3_11_8, DU_DOTCLKOUT0), 688 PINMUX_IPSR_GPSR(IP3_11_8, HTX3_D), 689 PINMUX_IPSR_GPSR(IP3_11_8, IECLK), 690 PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT12), 691 692 PINMUX_IPSR_GPSR(IP3_15_12, A4), 693 PINMUX_IPSR_MSEL(IP3_15_12, RTS4_N_A, SEL_SCIF4_0), 694 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SYNC_B, SEL_MSIOF3_1), 695 PINMUX_IPSR_GPSR(IP3_15_12, VI4_DATA8), 696 PINMUX_IPSR_MSEL(IP3_15_12, PWM2_B, SEL_PWM2_1), 697 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4), 698 PINMUX_IPSR_MSEL(IP3_15_12, RIF2_CLK_B, SEL_DRIF2_1), 699 700 PINMUX_IPSR_GPSR(IP3_19_16, A5), 701 PINMUX_IPSR_MSEL(IP3_19_16, SCK4_A, SEL_SCIF4_0), 702 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SCK_B, SEL_MSIOF3_1), 703 PINMUX_IPSR_GPSR(IP3_19_16, VI4_DATA9), 704 PINMUX_IPSR_MSEL(IP3_19_16, PWM3_B, SEL_PWM3_1), 705 PINMUX_IPSR_MSEL(IP3_19_16, RIF2_SYNC_B, SEL_DRIF2_1), 706 PINMUX_IPSR_GPSR(IP3_19_16, QPOLA), 707 708 PINMUX_IPSR_GPSR(IP3_23_20, A6), 709 PINMUX_IPSR_MSEL(IP3_23_20, RX4_A, SEL_SCIF4_0), 710 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_B, SEL_MSIOF3_1), 711 PINMUX_IPSR_GPSR(IP3_23_20, VI4_DATA10), 712 PINMUX_IPSR_MSEL(IP3_23_20, RIF2_D0_B, SEL_DRIF2_1), 713 714 PINMUX_IPSR_GPSR(IP3_27_24, A7), 715 PINMUX_IPSR_GPSR(IP3_27_24, TX4_A), 716 PINMUX_IPSR_GPSR(IP3_27_24, MSIOF3_TXD_B), 717 PINMUX_IPSR_GPSR(IP3_27_24, VI4_DATA11), 718 PINMUX_IPSR_MSEL(IP3_27_24, RIF2_D1_B, SEL_DRIF2_1), 719 720 PINMUX_IPSR_GPSR(IP3_31_28, A8), 721 PINMUX_IPSR_MSEL(IP3_31_28, SDA6_A, SEL_I2C6_0), 722 PINMUX_IPSR_MSEL(IP3_31_28, RX3_B, SEL_SCIF3_1), 723 PINMUX_IPSR_MSEL(IP3_31_28, HRX4_C, SEL_HSCIF4_2), 724 PINMUX_IPSR_MSEL(IP3_31_28, VI5_HSYNC_N_A, SEL_VIN5_0), 725 PINMUX_IPSR_GPSR(IP3_31_28, DU_HSYNC), 726 PINMUX_IPSR_MSEL(IP3_31_28, VI4_DATA0_B, SEL_VIN4_1), 727 PINMUX_IPSR_GPSR(IP3_31_28, QSTH_QHS), 728 729 /* IPSR4 */ 730 PINMUX_IPSR_GPSR(IP4_3_0, A9), 731 PINMUX_IPSR_GPSR(IP4_3_0, TX5_A), 732 PINMUX_IPSR_GPSR(IP4_3_0, IRQ3), 733 PINMUX_IPSR_GPSR(IP4_3_0, VI4_DATA16), 734 PINMUX_IPSR_MSEL(IP4_3_0, VI5_VSYNC_N_A, SEL_VIN5_0), 735 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG7), 736 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT15), 737 738 PINMUX_IPSR_GPSR(IP4_7_4, A10), 739 PINMUX_IPSR_GPSR(IP4_7_4, IRQ4), 740 PINMUX_IPSR_MSEL(IP4_7_4, MSIOF2_SYNC_B, SEL_MSIOF2_1), 741 PINMUX_IPSR_GPSR(IP4_7_4, VI4_DATA13), 742 PINMUX_IPSR_MSEL(IP4_7_4, VI5_FIELD_A, SEL_VIN5_0), 743 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG5), 744 PINMUX_IPSR_GPSR(IP4_7_4, FSCLKST2_N_B), 745 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT13), 746 747 PINMUX_IPSR_GPSR(IP4_11_8, A11), 748 PINMUX_IPSR_MSEL(IP4_11_8, SCL6_A, SEL_I2C6_0), 749 PINMUX_IPSR_GPSR(IP4_11_8, TX3_B), 750 PINMUX_IPSR_GPSR(IP4_11_8, HTX4_C), 751 PINMUX_IPSR_GPSR(IP4_11_8, DU_VSYNC), 752 PINMUX_IPSR_MSEL(IP4_11_8, VI4_DATA1_B, SEL_VIN4_1), 753 PINMUX_IPSR_GPSR(IP4_11_8, QSTVA_QVS), 754 755 PINMUX_IPSR_GPSR(IP4_15_12, A12), 756 PINMUX_IPSR_MSEL(IP4_15_12, RX5_A, SEL_SCIF5_0), 757 PINMUX_IPSR_GPSR(IP4_15_12, MSIOF2_SS2_B), 758 PINMUX_IPSR_GPSR(IP4_15_12, VI4_DATA17), 759 PINMUX_IPSR_MSEL(IP4_15_12, VI5_DATA3_A, SEL_VIN5_0), 760 PINMUX_IPSR_GPSR(IP4_15_12, DU_DG6), 761 PINMUX_IPSR_GPSR(IP4_15_12, LCDOUT14), 762 763 PINMUX_IPSR_GPSR(IP4_19_16, A13), 764 PINMUX_IPSR_MSEL(IP4_19_16, SCK5_A, SEL_SCIF5_0), 765 PINMUX_IPSR_MSEL(IP4_19_16, MSIOF2_SCK_B, SEL_MSIOF2_1), 766 PINMUX_IPSR_GPSR(IP4_19_16, VI4_DATA14), 767 PINMUX_IPSR_MSEL(IP4_19_16, HRX4_D, SEL_HSCIF4_3), 768 PINMUX_IPSR_GPSR(IP4_19_16, DU_DB2), 769 PINMUX_IPSR_GPSR(IP4_19_16, LCDOUT2), 770 771 PINMUX_IPSR_GPSR(IP4_23_20, A14), 772 PINMUX_IPSR_GPSR(IP4_23_20, MSIOF1_SS1), 773 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF2_RXD_B, SEL_MSIOF2_1), 774 PINMUX_IPSR_GPSR(IP4_23_20, VI4_DATA15), 775 PINMUX_IPSR_GPSR(IP4_23_20, HTX4_D), 776 PINMUX_IPSR_GPSR(IP4_23_20, DU_DB3), 777 PINMUX_IPSR_GPSR(IP4_23_20, LCDOUT3), 778 779 PINMUX_IPSR_GPSR(IP4_27_24, A15), 780 PINMUX_IPSR_GPSR(IP4_27_24, MSIOF1_SS2), 781 PINMUX_IPSR_GPSR(IP4_27_24, MSIOF2_TXD_B), 782 PINMUX_IPSR_GPSR(IP4_27_24, VI4_DATA18), 783 PINMUX_IPSR_MSEL(IP4_27_24, VI5_DATA4_A, SEL_VIN5_0), 784 PINMUX_IPSR_GPSR(IP4_27_24, DU_DB4), 785 PINMUX_IPSR_GPSR(IP4_27_24, LCDOUT4), 786 787 PINMUX_IPSR_GPSR(IP4_31_28, A16), 788 PINMUX_IPSR_GPSR(IP4_31_28, MSIOF1_SYNC), 789 PINMUX_IPSR_GPSR(IP4_31_28, MSIOF2_SS1_B), 790 PINMUX_IPSR_GPSR(IP4_31_28, VI4_DATA19), 791 PINMUX_IPSR_MSEL(IP4_31_28, VI5_DATA5_A, SEL_VIN5_0), 792 PINMUX_IPSR_GPSR(IP4_31_28, DU_DB5), 793 PINMUX_IPSR_GPSR(IP4_31_28, LCDOUT5), 794 795 /* IPSR5 */ 796 PINMUX_IPSR_GPSR(IP5_3_0, A17), 797 PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD), 798 PINMUX_IPSR_GPSR(IP5_3_0, VI4_DATA20), 799 PINMUX_IPSR_MSEL(IP5_3_0, VI5_DATA6_A, SEL_VIN5_0), 800 PINMUX_IPSR_GPSR(IP5_3_0, DU_DB6), 801 PINMUX_IPSR_GPSR(IP5_3_0, LCDOUT6), 802 803 PINMUX_IPSR_GPSR(IP5_7_4, A18), 804 PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD), 805 PINMUX_IPSR_GPSR(IP5_7_4, VI4_DATA21), 806 PINMUX_IPSR_MSEL(IP5_7_4, VI5_DATA7_A, SEL_VIN5_0), 807 PINMUX_IPSR_GPSR(IP5_7_4, DU_DB0), 808 PINMUX_IPSR_MSEL(IP5_7_4, HRX4_E, SEL_HSCIF4_4), 809 PINMUX_IPSR_GPSR(IP5_7_4, LCDOUT0), 810 811 PINMUX_IPSR_GPSR(IP5_11_8, A19), 812 PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK), 813 PINMUX_IPSR_GPSR(IP5_11_8, VI4_DATA22), 814 PINMUX_IPSR_MSEL(IP5_11_8, VI5_DATA2_A, SEL_VIN5_0), 815 PINMUX_IPSR_GPSR(IP5_11_8, DU_DB1), 816 PINMUX_IPSR_GPSR(IP5_11_8, HTX4_E), 817 PINMUX_IPSR_GPSR(IP5_11_8, LCDOUT1), 818 819 PINMUX_IPSR_GPSR(IP5_15_12, CS0_N), 820 PINMUX_IPSR_GPSR(IP5_15_12, SCL5), 821 PINMUX_IPSR_GPSR(IP5_15_12, DU_DR0), 822 PINMUX_IPSR_MSEL(IP5_15_12, VI4_DATA2_B, SEL_VIN4_1), 823 PINMUX_IPSR_GPSR(IP5_15_12, LCDOUT16), 824 825 PINMUX_IPSR_GPSR(IP5_19_16, WE0_N), 826 PINMUX_IPSR_GPSR(IP5_19_16, SDA5), 827 PINMUX_IPSR_GPSR(IP5_19_16, DU_DR1), 828 PINMUX_IPSR_MSEL(IP5_19_16, VI4_DATA3_B, SEL_VIN4_1), 829 PINMUX_IPSR_GPSR(IP5_19_16, LCDOUT17), 830 831 PINMUX_IPSR_GPSR(IP5_23_20, D0), 832 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_SCK_A, SEL_MSIOF3_0), 833 PINMUX_IPSR_GPSR(IP5_23_20, DU_DR2), 834 PINMUX_IPSR_MSEL(IP5_23_20, CTS4_N_C, SEL_SCIF4_2), 835 PINMUX_IPSR_GPSR(IP5_23_20, LCDOUT18), 836 837 PINMUX_IPSR_GPSR(IP5_27_24, D1), 838 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_SYNC_A, SEL_MSIOF3_0), 839 PINMUX_IPSR_MSEL(IP5_27_24, SCK3_A, SEL_SCIF3_0), 840 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA23), 841 PINMUX_IPSR_MSEL(IP5_27_24, VI5_CLKENB_A, SEL_VIN5_0), 842 PINMUX_IPSR_GPSR(IP5_27_24, DU_DB7), 843 PINMUX_IPSR_MSEL(IP5_27_24, RTS4_N_C, SEL_SCIF4_2), 844 PINMUX_IPSR_GPSR(IP5_27_24, LCDOUT7), 845 846 PINMUX_IPSR_GPSR(IP5_31_28, D2), 847 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF3_RXD_A, SEL_MSIOF3_0), 848 PINMUX_IPSR_MSEL(IP5_31_28, RX5_C, SEL_SCIF5_2), 849 PINMUX_IPSR_MSEL(IP5_31_28, VI5_DATA14_A, SEL_VIN5_0), 850 PINMUX_IPSR_GPSR(IP5_31_28, DU_DR3), 851 PINMUX_IPSR_MSEL(IP5_31_28, RX4_C, SEL_SCIF4_2), 852 PINMUX_IPSR_GPSR(IP5_31_28, LCDOUT19), 853 854 /* IPSR6 */ 855 PINMUX_IPSR_GPSR(IP6_3_0, D3), 856 PINMUX_IPSR_GPSR(IP6_3_0, MSIOF3_TXD_A), 857 PINMUX_IPSR_GPSR(IP6_3_0, TX5_C), 858 PINMUX_IPSR_MSEL(IP6_3_0, VI5_DATA15_A, SEL_VIN5_0), 859 PINMUX_IPSR_GPSR(IP6_3_0, DU_DR4), 860 PINMUX_IPSR_GPSR(IP6_3_0, TX4_C), 861 PINMUX_IPSR_GPSR(IP6_3_0, LCDOUT20), 862 863 PINMUX_IPSR_GPSR(IP6_7_4, D4), 864 PINMUX_IPSR_GPSR(IP6_7_4, CANFD1_TX), 865 PINMUX_IPSR_MSEL(IP6_7_4, HSCK3_B, SEL_HSCIF3_1), 866 PINMUX_IPSR_GPSR(IP6_7_4, CAN1_TX), 867 PINMUX_IPSR_MSEL(IP6_7_4, RTS3_N_A, SEL_SCIF3_0), 868 PINMUX_IPSR_GPSR(IP6_7_4, MSIOF3_SS2_A), 869 PINMUX_IPSR_MSEL(IP6_7_4, VI5_DATA1_B, SEL_VIN5_1), 870 871 PINMUX_IPSR_GPSR(IP6_11_8, D5), 872 PINMUX_IPSR_MSEL(IP6_11_8, RX3_A, SEL_SCIF3_0), 873 PINMUX_IPSR_MSEL(IP6_11_8, HRX3_B, SEL_HSCIF3_1), 874 PINMUX_IPSR_GPSR(IP6_11_8, DU_DR5), 875 PINMUX_IPSR_MSEL(IP6_11_8, VI4_DATA4_B, SEL_VIN4_1), 876 PINMUX_IPSR_GPSR(IP6_11_8, LCDOUT21), 877 878 PINMUX_IPSR_GPSR(IP6_15_12, D6), 879 PINMUX_IPSR_GPSR(IP6_15_12, TX3_A), 880 PINMUX_IPSR_GPSR(IP6_15_12, HTX3_B), 881 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR6), 882 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA5_B, SEL_VIN4_1), 883 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT22), 884 885 PINMUX_IPSR_GPSR(IP6_19_16, D7), 886 PINMUX_IPSR_GPSR(IP6_19_16, CANFD1_RX), 887 PINMUX_IPSR_GPSR(IP6_19_16, IRQ5), 888 PINMUX_IPSR_GPSR(IP6_19_16, CAN1_RX), 889 PINMUX_IPSR_MSEL(IP6_19_16, CTS3_N_A, SEL_SCIF3_0), 890 PINMUX_IPSR_MSEL(IP6_19_16, VI5_DATA2_B, SEL_VIN5_1), 891 892 PINMUX_IPSR_GPSR(IP6_23_20, D8), 893 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_SCK_A, SEL_MSIOF2_0), 894 PINMUX_IPSR_MSEL(IP6_23_20, SCK4_B, SEL_SCIF4_1), 895 PINMUX_IPSR_MSEL(IP6_23_20, VI5_DATA12_A, SEL_VIN5_0), 896 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR7), 897 PINMUX_IPSR_MSEL(IP6_23_20, RIF3_CLK_B, SEL_DRIF3_1), 898 PINMUX_IPSR_MSEL(IP6_23_20, HCTS3_N_E, SEL_HSCIF3_4), 899 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT23), 900 901 PINMUX_IPSR_GPSR(IP6_27_24, D9), 902 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_SYNC_A, SEL_MSIOF2_0), 903 PINMUX_IPSR_MSEL(IP6_27_24, VI5_DATA10_A, SEL_VIN5_0), 904 PINMUX_IPSR_GPSR(IP6_27_24, DU_DG0), 905 PINMUX_IPSR_MSEL(IP6_27_24, RIF3_SYNC_B, SEL_DRIF3_1), 906 PINMUX_IPSR_MSEL(IP6_27_24, HRX3_E, SEL_HSCIF3_4), 907 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT8), 908 909 PINMUX_IPSR_GPSR(IP6_31_28, D10), 910 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_RXD_A, SEL_MSIOF2_0), 911 PINMUX_IPSR_MSEL(IP6_31_28, VI5_DATA13_A, SEL_VIN5_0), 912 PINMUX_IPSR_GPSR(IP6_31_28, DU_DG1), 913 PINMUX_IPSR_MSEL(IP6_31_28, RIF3_D0_B, SEL_DRIF3_1), 914 PINMUX_IPSR_GPSR(IP6_31_28, HTX3_E), 915 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT9), 916 917 /* IPSR7 */ 918 PINMUX_IPSR_GPSR(IP7_3_0, D11), 919 PINMUX_IPSR_GPSR(IP7_3_0, MSIOF2_TXD_A), 920 PINMUX_IPSR_MSEL(IP7_3_0, VI5_DATA11_A, SEL_VIN5_0), 921 PINMUX_IPSR_GPSR(IP7_3_0, DU_DG2), 922 PINMUX_IPSR_MSEL(IP7_3_0, RIF3_D1_B, SEL_DRIF3_1), 923 PINMUX_IPSR_MSEL(IP7_3_0, HRTS3_N_E, SEL_HSCIF3_4), 924 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT10), 925 926 PINMUX_IPSR_GPSR(IP7_7_4, D12), 927 PINMUX_IPSR_GPSR(IP7_7_4, CANFD0_TX), 928 PINMUX_IPSR_GPSR(IP7_7_4, TX4_B), 929 PINMUX_IPSR_GPSR(IP7_7_4, CAN0_TX), 930 PINMUX_IPSR_MSEL(IP7_7_4, VI5_DATA8_A, SEL_VIN5_0), 931 PINMUX_IPSR_MSEL(IP7_7_4, VI5_DATA3_B, SEL_VIN5_1), 932 933 PINMUX_IPSR_GPSR(IP7_11_8, D13), 934 PINMUX_IPSR_GPSR(IP7_11_8, CANFD0_RX), 935 PINMUX_IPSR_MSEL(IP7_11_8, RX4_B, SEL_SCIF4_1), 936 PINMUX_IPSR_GPSR(IP7_11_8, CAN0_RX), 937 PINMUX_IPSR_MSEL(IP7_11_8, VI5_DATA9_A, SEL_VIN5_0), 938 PINMUX_IPSR_MSEL(IP7_11_8, SCL7_B, SEL_I2C7_1), 939 PINMUX_IPSR_MSEL(IP7_11_8, VI5_DATA4_B, SEL_VIN5_1), 940 941 PINMUX_IPSR_GPSR(IP7_15_12, D14), 942 PINMUX_IPSR_GPSR(IP7_15_12, CAN_CLK), 943 PINMUX_IPSR_MSEL(IP7_15_12, HRX3_A, SEL_HSCIF3_0), 944 PINMUX_IPSR_GPSR(IP7_15_12, MSIOF2_SS2_A), 945 PINMUX_IPSR_MSEL(IP7_15_12, SDA7_B, SEL_I2C7_1), 946 PINMUX_IPSR_MSEL(IP7_15_12, VI5_DATA5_B, SEL_VIN5_1), 947 948 PINMUX_IPSR_GPSR(IP7_19_16, D15), 949 PINMUX_IPSR_GPSR(IP7_19_16, MSIOF2_SS1_A), 950 PINMUX_IPSR_GPSR(IP7_19_16, HTX3_A), 951 PINMUX_IPSR_GPSR(IP7_19_16, MSIOF3_SS1_A), 952 PINMUX_IPSR_GPSR(IP7_19_16, DU_DG3), 953 PINMUX_IPSR_GPSR(IP7_19_16, LCDOUT11), 954 955 PINMUX_IPSR_GPSR(IP7_23_20, SCL4), 956 PINMUX_IPSR_GPSR(IP7_23_20, CS1_N_A26), 957 PINMUX_IPSR_GPSR(IP7_23_20, DU_DOTCLKIN0), 958 PINMUX_IPSR_MSEL(IP7_23_20, VI4_DATA6_B, SEL_VIN4_1), 959 PINMUX_IPSR_MSEL(IP7_23_20, VI5_DATA6_B, SEL_VIN5_1), 960 PINMUX_IPSR_GPSR(IP7_23_20, QCLK), 961 962 PINMUX_IPSR_GPSR(IP7_27_24, SDA4), 963 PINMUX_IPSR_GPSR(IP7_27_24, WE1_N), 964 PINMUX_IPSR_MSEL(IP7_27_24, VI4_DATA7_B, SEL_VIN4_1), 965 PINMUX_IPSR_MSEL(IP7_27_24, VI5_DATA7_B, SEL_VIN5_1), 966 PINMUX_IPSR_GPSR(IP7_27_24, QPOLB), 967 968 PINMUX_IPSR_GPSR(IP7_31_28, SD0_CLK), 969 PINMUX_IPSR_GPSR(IP7_31_28, NFDATA8), 970 PINMUX_IPSR_MSEL(IP7_31_28, SCL1_C, SEL_I2C1_2), 971 PINMUX_IPSR_MSEL(IP7_31_28, HSCK1_B, SEL_HSCIF1_1), 972 PINMUX_IPSR_MSEL(IP7_31_28, SDA2_E, SEL_I2C2_4), 973 PINMUX_IPSR_MSEL(IP7_31_28, FMCLK_B, SEL_FM_1), 974 975 /* IPSR8 */ 976 PINMUX_IPSR_GPSR(IP8_3_0, SD0_CMD), 977 PINMUX_IPSR_GPSR(IP8_3_0, NFDATA9), 978 PINMUX_IPSR_MSEL(IP8_3_0, HRX1_B, SEL_HSCIF1_1), 979 PINMUX_IPSR_MSEL(IP8_3_0, SPEEDIN_B, SEL_SPEED_PULSE_IF_1), 980 981 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT0), 982 PINMUX_IPSR_GPSR(IP8_7_4, NFDATA10), 983 PINMUX_IPSR_GPSR(IP8_7_4, HTX1_B), 984 PINMUX_IPSR_MSEL(IP8_7_4, REMOCON_B, SEL_REMOCON_1), 985 986 PINMUX_IPSR_GPSR(IP8_11_8, SD0_DAT1), 987 PINMUX_IPSR_GPSR(IP8_11_8, NFDATA11), 988 PINMUX_IPSR_MSEL(IP8_11_8, SDA2_C, SEL_I2C2_2), 989 PINMUX_IPSR_MSEL(IP8_11_8, HCTS1_N_B, SEL_HSCIF1_1), 990 PINMUX_IPSR_MSEL(IP8_11_8, FMIN_B, SEL_FM_1), 991 992 PINMUX_IPSR_GPSR(IP8_15_12, SD0_DAT2), 993 PINMUX_IPSR_GPSR(IP8_15_12, NFDATA12), 994 PINMUX_IPSR_MSEL(IP8_15_12, SCL2_C, SEL_I2C2_2), 995 PINMUX_IPSR_MSEL(IP8_15_12, HRTS1_N_B, SEL_HSCIF1_1), 996 PINMUX_IPSR_GPSR(IP8_15_12, BPFCLK_B), 997 998 PINMUX_IPSR_GPSR(IP8_19_16, SD0_DAT3), 999 PINMUX_IPSR_GPSR(IP8_19_16, NFDATA13), 1000 PINMUX_IPSR_MSEL(IP8_19_16, SDA1_C, SEL_I2C1_2), 1001 PINMUX_IPSR_MSEL(IP8_19_16, SCL2_E, SEL_I2C2_4), 1002 PINMUX_IPSR_MSEL(IP8_19_16, SPEEDIN_C, SEL_SPEED_PULSE_IF_2), 1003 PINMUX_IPSR_MSEL(IP8_19_16, REMOCON_C, SEL_REMOCON_2), 1004 1005 PINMUX_IPSR_GPSR(IP8_23_20, SD1_CLK), 1006 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1), 1007 1008 PINMUX_IPSR_GPSR(IP8_27_24, SD1_CMD), 1009 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1), 1010 1011 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT0), 1012 PINMUX_IPSR_MSEL(IP8_31_28, NFWP_N_B, SEL_NDF_1), 1013 1014 /* IPSR9 */ 1015 PINMUX_IPSR_GPSR(IP9_3_0, SD1_DAT1), 1016 PINMUX_IPSR_MSEL(IP9_3_0, NFCE_N_B, SEL_NDF_1), 1017 1018 PINMUX_IPSR_GPSR(IP9_7_4, SD1_DAT2), 1019 PINMUX_IPSR_MSEL(IP9_7_4, NFALE_B, SEL_NDF_1), 1020 1021 PINMUX_IPSR_GPSR(IP9_11_8, SD1_DAT3), 1022 PINMUX_IPSR_MSEL(IP9_11_8, NFRB_N_B, SEL_NDF_1), 1023 1024 PINMUX_IPSR_GPSR(IP9_15_12, SD3_CLK), 1025 PINMUX_IPSR_GPSR(IP9_15_12, NFWE_N), 1026 1027 PINMUX_IPSR_GPSR(IP9_19_16, SD3_CMD), 1028 PINMUX_IPSR_GPSR(IP9_19_16, NFRE_N), 1029 1030 PINMUX_IPSR_GPSR(IP9_23_20, SD3_DAT0), 1031 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA0), 1032 1033 PINMUX_IPSR_GPSR(IP9_27_24, SD3_DAT1), 1034 PINMUX_IPSR_GPSR(IP9_27_24, NFDATA1), 1035 1036 PINMUX_IPSR_GPSR(IP9_31_28, SD3_DAT2), 1037 PINMUX_IPSR_GPSR(IP9_31_28, NFDATA2), 1038 1039 /* IPSR10 */ 1040 PINMUX_IPSR_GPSR(IP10_3_0, SD3_DAT3), 1041 PINMUX_IPSR_GPSR(IP10_3_0, NFDATA3), 1042 1043 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT4), 1044 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA4), 1045 1046 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT5), 1047 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA5), 1048 1049 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT6), 1050 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA6), 1051 1052 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT7), 1053 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA7), 1054 1055 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DS), 1056 PINMUX_IPSR_GPSR(IP10_23_20, NFCLE), 1057 1058 PINMUX_IPSR_GPSR(IP10_27_24, SD0_CD), 1059 PINMUX_IPSR_MSEL(IP10_27_24, NFALE_A, SEL_NDF_0), 1060 PINMUX_IPSR_GPSR(IP10_27_24, SD3_CD), 1061 PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1), 1062 PINMUX_IPSR_MSEL(IP10_27_24, SCL2_B, SEL_I2C2_1), 1063 PINMUX_IPSR_MSEL(IP10_27_24, TCLK1_A, SEL_TIMER_TMU_0), 1064 PINMUX_IPSR_MSEL(IP10_27_24, SSI_SCK2_B, SEL_SSI2_1), 1065 PINMUX_IPSR_GPSR(IP10_27_24, TS_SCK0), 1066 1067 PINMUX_IPSR_GPSR(IP10_31_28, SD0_WP), 1068 PINMUX_IPSR_MSEL(IP10_31_28, NFRB_N_A, SEL_NDF_0), 1069 PINMUX_IPSR_GPSR(IP10_31_28, SD3_WP), 1070 PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1), 1071 PINMUX_IPSR_MSEL(IP10_31_28, SDA2_B, SEL_I2C2_1), 1072 PINMUX_IPSR_MSEL(IP10_31_28, TCLK2_A, SEL_TIMER_TMU_0), 1073 PINMUX_IPSR_MSEL(IP10_31_28, SSI_WS2_B, SEL_SSI2_1), 1074 PINMUX_IPSR_GPSR(IP10_31_28, TS_SDAT0), 1075 1076 /* IPSR11 */ 1077 PINMUX_IPSR_GPSR(IP11_3_0, SD1_CD), 1078 PINMUX_IPSR_MSEL(IP11_3_0, NFCE_N_A, SEL_NDF_0), 1079 PINMUX_IPSR_GPSR(IP11_3_0, SSI_SCK1), 1080 PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1), 1081 PINMUX_IPSR_GPSR(IP11_3_0, TS_SDEN0), 1082 1083 PINMUX_IPSR_GPSR(IP11_7_4, SD1_WP), 1084 PINMUX_IPSR_MSEL(IP11_7_4, NFWP_N_A, SEL_NDF_0), 1085 PINMUX_IPSR_GPSR(IP11_7_4, SSI_WS1), 1086 PINMUX_IPSR_MSEL(IP11_7_4, RIF0_SYNC_B, SEL_DRIF0_1), 1087 PINMUX_IPSR_GPSR(IP11_7_4, TS_SPSYNC0), 1088 1089 PINMUX_IPSR_MSEL(IP11_11_8, RX0_A, SEL_SCIF0_0), 1090 PINMUX_IPSR_MSEL(IP11_11_8, HRX1_A, SEL_HSCIF1_0), 1091 PINMUX_IPSR_MSEL(IP11_11_8, SSI_SCK2_A, SEL_SSI2_0), 1092 PINMUX_IPSR_GPSR(IP11_11_8, RIF1_SYNC), 1093 PINMUX_IPSR_GPSR(IP11_11_8, TS_SCK1), 1094 1095 PINMUX_IPSR_MSEL(IP11_15_12, TX0_A, SEL_SCIF0_0), 1096 PINMUX_IPSR_GPSR(IP11_15_12, HTX1_A), 1097 PINMUX_IPSR_MSEL(IP11_15_12, SSI_WS2_A, SEL_SSI2_0), 1098 PINMUX_IPSR_GPSR(IP11_15_12, RIF1_D0), 1099 PINMUX_IPSR_GPSR(IP11_15_12, TS_SDAT1), 1100 1101 PINMUX_IPSR_MSEL(IP11_19_16, CTS0_N_A, SEL_SCIF0_0), 1102 PINMUX_IPSR_MSEL(IP11_19_16, NFDATA14_A, SEL_NDF_0), 1103 PINMUX_IPSR_GPSR(IP11_19_16, AUDIO_CLKOUT_A), 1104 PINMUX_IPSR_GPSR(IP11_19_16, RIF1_D1), 1105 PINMUX_IPSR_MSEL(IP11_19_16, SCIF_CLK_A, SEL_SCIF_0), 1106 PINMUX_IPSR_MSEL(IP11_19_16, FMCLK_A, SEL_FM_0), 1107 1108 PINMUX_IPSR_MSEL(IP11_23_20, RTS0_N_A, SEL_SCIF0_0), 1109 PINMUX_IPSR_MSEL(IP11_23_20, NFDATA15_A, SEL_NDF_0), 1110 PINMUX_IPSR_GPSR(IP11_23_20, AUDIO_CLKOUT1_A), 1111 PINMUX_IPSR_GPSR(IP11_23_20, RIF1_CLK), 1112 PINMUX_IPSR_MSEL(IP11_23_20, SCL2_A, SEL_I2C2_0), 1113 PINMUX_IPSR_MSEL(IP11_23_20, FMIN_A, SEL_FM_0), 1114 1115 PINMUX_IPSR_MSEL(IP11_27_24, SCK0_A, SEL_SCIF0_0), 1116 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_A, SEL_HSCIF1_0), 1117 PINMUX_IPSR_GPSR(IP11_27_24, USB3HS0_ID), 1118 PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N), 1119 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0), 1120 PINMUX_IPSR_MSEL(IP11_27_24, FMCLK_C, SEL_FM_2), 1121 PINMUX_IPSR_GPSR(IP11_27_24, USB0_ID), 1122 1123 PINMUX_IPSR_GPSR(IP11_31_28, RX1), 1124 PINMUX_IPSR_MSEL(IP11_31_28, HRX2_B, SEL_HSCIF2_1), 1125 PINMUX_IPSR_MSEL(IP11_31_28, SSI_SCK9_B, SEL_SSI9_1), 1126 PINMUX_IPSR_GPSR(IP11_31_28, AUDIO_CLKOUT1_B), 1127 1128 /* IPSR12 */ 1129 PINMUX_IPSR_GPSR(IP12_3_0, TX1), 1130 PINMUX_IPSR_GPSR(IP12_3_0, HTX2_B), 1131 PINMUX_IPSR_MSEL(IP12_3_0, SSI_WS9_B, SEL_SSI9_1), 1132 PINMUX_IPSR_GPSR(IP12_3_0, AUDIO_CLKOUT3_B), 1133 1134 PINMUX_IPSR_MSEL(IP12_7_4, SCK2_A, SEL_SCIF2_0), 1135 PINMUX_IPSR_MSEL(IP12_7_4, HSCK0_A, SEL_HSCIF0_0), 1136 PINMUX_IPSR_MSEL(IP12_7_4, AUDIO_CLKB_A, SEL_ADGB_0), 1137 PINMUX_IPSR_GPSR(IP12_7_4, CTS1_N), 1138 PINMUX_IPSR_MSEL(IP12_7_4, RIF0_CLK_A, SEL_DRIF0_0), 1139 PINMUX_IPSR_MSEL(IP12_7_4, REMOCON_A, SEL_REMOCON_0), 1140 PINMUX_IPSR_MSEL(IP12_7_4, SCIF_CLK_B, SEL_SCIF_1), 1141 1142 PINMUX_IPSR_MSEL(IP12_11_8, TX2_A, SEL_SCIF2_0), 1143 PINMUX_IPSR_MSEL(IP12_11_8, HRX0_A, SEL_HSCIF0_0), 1144 PINMUX_IPSR_GPSR(IP12_11_8, AUDIO_CLKOUT2_A), 1145 PINMUX_IPSR_MSEL(IP12_11_8, SCL1_A, SEL_I2C1_0), 1146 PINMUX_IPSR_MSEL(IP12_11_8, FSO_CFE_0_N_A, SEL_FSO_0), 1147 PINMUX_IPSR_GPSR(IP12_11_8, TS_SDEN1), 1148 1149 PINMUX_IPSR_MSEL(IP12_15_12, RX2_A, SEL_SCIF2_0), 1150 PINMUX_IPSR_GPSR(IP12_15_12, HTX0_A), 1151 PINMUX_IPSR_GPSR(IP12_15_12, AUDIO_CLKOUT3_A), 1152 PINMUX_IPSR_MSEL(IP12_15_12, SDA1_A, SEL_I2C1_0), 1153 PINMUX_IPSR_MSEL(IP12_15_12, FSO_CFE_1_N_A, SEL_FSO_0), 1154 PINMUX_IPSR_GPSR(IP12_15_12, TS_SPSYNC1), 1155 1156 PINMUX_IPSR_GPSR(IP12_19_16, MSIOF0_SCK), 1157 PINMUX_IPSR_GPSR(IP12_19_16, SSI_SCK78), 1158 1159 PINMUX_IPSR_GPSR(IP12_23_20, MSIOF0_RXD), 1160 PINMUX_IPSR_GPSR(IP12_23_20, SSI_WS78), 1161 PINMUX_IPSR_MSEL(IP12_23_20, TX2_B, SEL_SCIF2_1), 1162 1163 PINMUX_IPSR_GPSR(IP12_27_24, MSIOF0_TXD), 1164 PINMUX_IPSR_GPSR(IP12_27_24, SSI_SDATA7), 1165 PINMUX_IPSR_MSEL(IP12_27_24, RX2_B, SEL_SCIF2_1), 1166 1167 PINMUX_IPSR_GPSR(IP12_31_28, MSIOF0_SYNC), 1168 PINMUX_IPSR_GPSR(IP12_31_28, AUDIO_CLKOUT_B), 1169 PINMUX_IPSR_GPSR(IP12_31_28, SSI_SDATA8), 1170 1171 /* IPSR13 */ 1172 PINMUX_IPSR_GPSR(IP13_3_0, MSIOF0_SS1), 1173 PINMUX_IPSR_MSEL(IP13_3_0, HRX2_A, SEL_HSCIF2_0), 1174 PINMUX_IPSR_GPSR(IP13_3_0, SSI_SCK4), 1175 PINMUX_IPSR_MSEL(IP13_3_0, HCTS0_N_A, SEL_HSCIF0_0), 1176 PINMUX_IPSR_GPSR(IP13_3_0, BPFCLK_C), 1177 PINMUX_IPSR_MSEL(IP13_3_0, SPEEDIN_A, SEL_SPEED_PULSE_IF_0), 1178 1179 PINMUX_IPSR_GPSR(IP13_7_4, MSIOF0_SS2), 1180 PINMUX_IPSR_GPSR(IP13_7_4, HTX2_A), 1181 PINMUX_IPSR_GPSR(IP13_7_4, SSI_WS4), 1182 PINMUX_IPSR_MSEL(IP13_7_4, HRTS0_N_A, SEL_HSCIF0_0), 1183 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_C, SEL_FM_2), 1184 PINMUX_IPSR_GPSR(IP13_7_4, BPFCLK_A), 1185 1186 PINMUX_IPSR_GPSR(IP13_11_8, SSI_SDATA9), 1187 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKC_A, SEL_ADGC_0), 1188 PINMUX_IPSR_GPSR(IP13_11_8, SCK1), 1189 1190 PINMUX_IPSR_GPSR(IP13_15_12, MLB_CLK), 1191 PINMUX_IPSR_MSEL(IP13_15_12, RX0_B, SEL_SCIF0_1), 1192 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_A, SEL_DRIF0_0), 1193 PINMUX_IPSR_MSEL(IP13_15_12, SCL1_B, SEL_I2C1_1), 1194 PINMUX_IPSR_MSEL(IP13_15_12, TCLK1_B, SEL_TIMER_TMU_1), 1195 PINMUX_IPSR_GPSR(IP13_15_12, SIM0_RST_A), 1196 1197 PINMUX_IPSR_GPSR(IP13_19_16, MLB_SIG), 1198 PINMUX_IPSR_MSEL(IP13_19_16, SCK0_B, SEL_SCIF0_1), 1199 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_A, SEL_DRIF0_0), 1200 PINMUX_IPSR_MSEL(IP13_19_16, SDA1_B, SEL_I2C1_1), 1201 PINMUX_IPSR_MSEL(IP13_19_16, TCLK2_B, SEL_TIMER_TMU_1), 1202 PINMUX_IPSR_MSEL(IP13_19_16, SIM0_D_A, SEL_SIMCARD_0), 1203 1204 PINMUX_IPSR_GPSR(IP13_23_20, MLB_DAT), 1205 PINMUX_IPSR_MSEL(IP13_23_20, TX0_B, SEL_SCIF0_1), 1206 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_A, SEL_DRIF0_0), 1207 PINMUX_IPSR_GPSR(IP13_23_20, SIM0_CLK_A), 1208 1209 PINMUX_IPSR_GPSR(IP13_27_24, SSI_SCK01239), 1210 1211 PINMUX_IPSR_GPSR(IP13_31_28, SSI_WS01239), 1212 1213 /* IPSR14 */ 1214 PINMUX_IPSR_GPSR(IP14_3_0, SSI_SDATA0), 1215 1216 PINMUX_IPSR_GPSR(IP14_7_4, SSI_SDATA1), 1217 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_B, SEL_ADGC_1), 1218 PINMUX_IPSR_MSEL(IP14_7_4, PWM0_B, SEL_PWM0_1), 1219 1220 PINMUX_IPSR_GPSR(IP14_11_8, SSI_SDATA2), 1221 PINMUX_IPSR_GPSR(IP14_11_8, AUDIO_CLKOUT2_B), 1222 PINMUX_IPSR_MSEL(IP14_11_8, SSI_SCK9_A, SEL_SSI9_0), 1223 PINMUX_IPSR_MSEL(IP14_11_8, PWM1_B, SEL_PWM1_1), 1224 1225 PINMUX_IPSR_GPSR(IP14_15_12, SSI_SCK349), 1226 PINMUX_IPSR_MSEL(IP14_15_12, PWM2_C, SEL_PWM2_2), 1227 1228 PINMUX_IPSR_GPSR(IP14_19_16, SSI_WS349), 1229 PINMUX_IPSR_MSEL(IP14_19_16, PWM3_C, SEL_PWM3_2), 1230 1231 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SDATA3), 1232 PINMUX_IPSR_GPSR(IP14_23_20, AUDIO_CLKOUT1_C), 1233 PINMUX_IPSR_MSEL(IP14_23_20, AUDIO_CLKB_B, SEL_ADGB_1), 1234 PINMUX_IPSR_MSEL(IP14_23_20, PWM4_B, SEL_PWM4_1), 1235 1236 PINMUX_IPSR_GPSR(IP14_27_24, SSI_SDATA4), 1237 PINMUX_IPSR_MSEL(IP14_27_24, SSI_WS9_A, SEL_SSI9_0), 1238 PINMUX_IPSR_MSEL(IP14_27_24, PWM5_B, SEL_PWM5_1), 1239 1240 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SCK5), 1241 PINMUX_IPSR_MSEL(IP14_31_28, HRX0_B, SEL_HSCIF0_1), 1242 PINMUX_IPSR_GPSR(IP14_31_28, USB0_PWEN_B), 1243 PINMUX_IPSR_MSEL(IP14_31_28, SCL2_D, SEL_I2C2_3), 1244 PINMUX_IPSR_MSEL(IP14_31_28, PWM6_B, SEL_PWM6_1), 1245 1246 /* IPSR15 */ 1247 PINMUX_IPSR_GPSR(IP15_3_0, SSI_WS5), 1248 PINMUX_IPSR_GPSR(IP15_3_0, HTX0_B), 1249 PINMUX_IPSR_MSEL(IP15_3_0, USB0_OVC_B, SEL_USB_20_CH0_1), 1250 PINMUX_IPSR_MSEL(IP15_3_0, SDA2_D, SEL_I2C2_3), 1251 1252 PINMUX_IPSR_GPSR(IP15_7_4, SSI_SDATA5), 1253 PINMUX_IPSR_MSEL(IP15_7_4, HSCK0_B, SEL_HSCIF0_1), 1254 PINMUX_IPSR_MSEL(IP15_7_4, AUDIO_CLKB_C, SEL_ADGB_2), 1255 PINMUX_IPSR_GPSR(IP15_7_4, TPU0TO0), 1256 1257 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK6), 1258 PINMUX_IPSR_MSEL(IP15_11_8, HSCK2_A, SEL_HSCIF2_0), 1259 PINMUX_IPSR_MSEL(IP15_11_8, AUDIO_CLKC_C, SEL_ADGC_2), 1260 PINMUX_IPSR_GPSR(IP15_11_8, TPU0TO1), 1261 PINMUX_IPSR_MSEL(IP15_11_8, FSO_CFE_0_N_B, SEL_FSO_1), 1262 PINMUX_IPSR_GPSR(IP15_11_8, SIM0_RST_B), 1263 1264 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS6), 1265 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0), 1266 PINMUX_IPSR_GPSR(IP15_15_12, AUDIO_CLKOUT2_C), 1267 PINMUX_IPSR_GPSR(IP15_15_12, TPU0TO2), 1268 PINMUX_IPSR_MSEL(IP15_15_12, SDA1_D, SEL_I2C1_3), 1269 PINMUX_IPSR_MSEL(IP15_15_12, FSO_CFE_1_N_B, SEL_FSO_1), 1270 PINMUX_IPSR_MSEL(IP15_15_12, SIM0_D_B, SEL_SIMCARD_1), 1271 1272 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA6), 1273 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0), 1274 PINMUX_IPSR_GPSR(IP15_19_16, AUDIO_CLKOUT3_C), 1275 PINMUX_IPSR_GPSR(IP15_19_16, TPU0TO3), 1276 PINMUX_IPSR_MSEL(IP15_19_16, SCL1_D, SEL_I2C1_3), 1277 PINMUX_IPSR_MSEL(IP15_19_16, FSO_TOE_N_B, SEL_FSO_1), 1278 PINMUX_IPSR_GPSR(IP15_19_16, SIM0_CLK_B), 1279 1280 PINMUX_IPSR_GPSR(IP15_23_20, AUDIO_CLKA), 1281 1282 PINMUX_IPSR_GPSR(IP15_27_24, USB30_PWEN), 1283 PINMUX_IPSR_GPSR(IP15_27_24, USB0_PWEN_A), 1284 1285 PINMUX_IPSR_GPSR(IP15_31_28, USB30_OVC), 1286 PINMUX_IPSR_MSEL(IP15_31_28, USB0_OVC_A, SEL_USB_20_CH0_0), 1287 1288 /* 1289 * Static pins can not be muxed between different functions but 1290 * still need mark entries in the pinmux list. Add each static 1291 * pin to the list without an associated function. The sh-pfc 1292 * core will do the right thing and skip trying to mux the pin 1293 * while still applying configuration to it. 1294 */ 1295 #define FM(x) PINMUX_DATA(x##_MARK, 0), 1296 PINMUX_STATIC 1297 #undef FM 1298 }; 1299 1300 /* 1301 * Pins not associated with a GPIO port. 1302 */ 1303 enum { 1304 GP_ASSIGN_LAST(), 1305 NOGP_ALL(), 1306 }; 1307 1308 static const struct sh_pfc_pin pinmux_pins[] = { 1309 PINMUX_GPIO_GP_ALL(), 1310 PINMUX_NOGP_ALL(), 1311 }; 1312 1313 /* - AUDIO CLOCK ------------------------------------------------------------ */ 1314 static const unsigned int audio_clk_a_pins[] = { 1315 /* CLK A */ 1316 RCAR_GP_PIN(6, 8), 1317 }; 1318 1319 static const unsigned int audio_clk_a_mux[] = { 1320 AUDIO_CLKA_MARK, 1321 }; 1322 1323 static const unsigned int audio_clk_b_a_pins[] = { 1324 /* CLK B_A */ 1325 RCAR_GP_PIN(5, 7), 1326 }; 1327 1328 static const unsigned int audio_clk_b_a_mux[] = { 1329 AUDIO_CLKB_A_MARK, 1330 }; 1331 1332 static const unsigned int audio_clk_b_b_pins[] = { 1333 /* CLK B_B */ 1334 RCAR_GP_PIN(6, 7), 1335 }; 1336 1337 static const unsigned int audio_clk_b_b_mux[] = { 1338 AUDIO_CLKB_B_MARK, 1339 }; 1340 1341 static const unsigned int audio_clk_b_c_pins[] = { 1342 /* CLK B_C */ 1343 RCAR_GP_PIN(6, 13), 1344 }; 1345 1346 static const unsigned int audio_clk_b_c_mux[] = { 1347 AUDIO_CLKB_C_MARK, 1348 }; 1349 1350 static const unsigned int audio_clk_c_a_pins[] = { 1351 /* CLK C_A */ 1352 RCAR_GP_PIN(5, 16), 1353 }; 1354 1355 static const unsigned int audio_clk_c_a_mux[] = { 1356 AUDIO_CLKC_A_MARK, 1357 }; 1358 1359 static const unsigned int audio_clk_c_b_pins[] = { 1360 /* CLK C_B */ 1361 RCAR_GP_PIN(6, 3), 1362 }; 1363 1364 static const unsigned int audio_clk_c_b_mux[] = { 1365 AUDIO_CLKC_B_MARK, 1366 }; 1367 1368 static const unsigned int audio_clk_c_c_pins[] = { 1369 /* CLK C_C */ 1370 RCAR_GP_PIN(6, 14), 1371 }; 1372 1373 static const unsigned int audio_clk_c_c_mux[] = { 1374 AUDIO_CLKC_C_MARK, 1375 }; 1376 1377 static const unsigned int audio_clkout_a_pins[] = { 1378 /* CLKOUT_A */ 1379 RCAR_GP_PIN(5, 3), 1380 }; 1381 1382 static const unsigned int audio_clkout_a_mux[] = { 1383 AUDIO_CLKOUT_A_MARK, 1384 }; 1385 1386 static const unsigned int audio_clkout_b_pins[] = { 1387 /* CLKOUT_B */ 1388 RCAR_GP_PIN(5, 13), 1389 }; 1390 1391 static const unsigned int audio_clkout_b_mux[] = { 1392 AUDIO_CLKOUT_B_MARK, 1393 }; 1394 1395 static const unsigned int audio_clkout1_a_pins[] = { 1396 /* CLKOUT1_A */ 1397 RCAR_GP_PIN(5, 4), 1398 }; 1399 1400 static const unsigned int audio_clkout1_a_mux[] = { 1401 AUDIO_CLKOUT1_A_MARK, 1402 }; 1403 1404 static const unsigned int audio_clkout1_b_pins[] = { 1405 /* CLKOUT1_B */ 1406 RCAR_GP_PIN(5, 5), 1407 }; 1408 1409 static const unsigned int audio_clkout1_b_mux[] = { 1410 AUDIO_CLKOUT1_B_MARK, 1411 }; 1412 1413 static const unsigned int audio_clkout1_c_pins[] = { 1414 /* CLKOUT1_C */ 1415 RCAR_GP_PIN(6, 7), 1416 }; 1417 1418 static const unsigned int audio_clkout1_c_mux[] = { 1419 AUDIO_CLKOUT1_C_MARK, 1420 }; 1421 1422 static const unsigned int audio_clkout2_a_pins[] = { 1423 /* CLKOUT2_A */ 1424 RCAR_GP_PIN(5, 8), 1425 }; 1426 1427 static const unsigned int audio_clkout2_a_mux[] = { 1428 AUDIO_CLKOUT2_A_MARK, 1429 }; 1430 1431 static const unsigned int audio_clkout2_b_pins[] = { 1432 /* CLKOUT2_B */ 1433 RCAR_GP_PIN(6, 4), 1434 }; 1435 1436 static const unsigned int audio_clkout2_b_mux[] = { 1437 AUDIO_CLKOUT2_B_MARK, 1438 }; 1439 1440 static const unsigned int audio_clkout2_c_pins[] = { 1441 /* CLKOUT2_C */ 1442 RCAR_GP_PIN(6, 15), 1443 }; 1444 1445 static const unsigned int audio_clkout2_c_mux[] = { 1446 AUDIO_CLKOUT2_C_MARK, 1447 }; 1448 1449 static const unsigned int audio_clkout3_a_pins[] = { 1450 /* CLKOUT3_A */ 1451 RCAR_GP_PIN(5, 9), 1452 }; 1453 1454 static const unsigned int audio_clkout3_a_mux[] = { 1455 AUDIO_CLKOUT3_A_MARK, 1456 }; 1457 1458 static const unsigned int audio_clkout3_b_pins[] = { 1459 /* CLKOUT3_B */ 1460 RCAR_GP_PIN(5, 6), 1461 }; 1462 1463 static const unsigned int audio_clkout3_b_mux[] = { 1464 AUDIO_CLKOUT3_B_MARK, 1465 }; 1466 1467 static const unsigned int audio_clkout3_c_pins[] = { 1468 /* CLKOUT3_C */ 1469 RCAR_GP_PIN(6, 16), 1470 }; 1471 1472 static const unsigned int audio_clkout3_c_mux[] = { 1473 AUDIO_CLKOUT3_C_MARK, 1474 }; 1475 1476 /* - EtherAVB --------------------------------------------------------------- */ 1477 static const unsigned int avb_link_pins[] = { 1478 /* AVB_LINK */ 1479 RCAR_GP_PIN(2, 23), 1480 }; 1481 1482 static const unsigned int avb_link_mux[] = { 1483 AVB_LINK_MARK, 1484 }; 1485 1486 static const unsigned int avb_magic_pins[] = { 1487 /* AVB_MAGIC */ 1488 RCAR_GP_PIN(2, 22), 1489 }; 1490 1491 static const unsigned int avb_magic_mux[] = { 1492 AVB_MAGIC_MARK, 1493 }; 1494 1495 static const unsigned int avb_phy_int_pins[] = { 1496 /* AVB_PHY_INT */ 1497 RCAR_GP_PIN(2, 21), 1498 }; 1499 1500 static const unsigned int avb_phy_int_mux[] = { 1501 AVB_PHY_INT_MARK, 1502 }; 1503 1504 static const unsigned int avb_mii_pins[] = { 1505 /* 1506 * AVB_RX_CTL, AVB_RXC, AVB_RD0, 1507 * AVB_RD1, AVB_RD2, AVB_RD3, 1508 * AVB_TXCREFCLK 1509 */ 1510 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), 1511 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19), 1512 RCAR_GP_PIN(2, 20), 1513 }; 1514 1515 static const unsigned int avb_mii_mux[] = { 1516 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK, 1517 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK, 1518 AVB_TXCREFCLK_MARK, 1519 }; 1520 1521 static const unsigned int avb_avtp_pps_pins[] = { 1522 /* AVB_AVTP_PPS */ 1523 RCAR_GP_PIN(1, 2), 1524 }; 1525 1526 static const unsigned int avb_avtp_pps_mux[] = { 1527 AVB_AVTP_PPS_MARK, 1528 }; 1529 1530 static const unsigned int avb_avtp_match_pins[] = { 1531 /* AVB_AVTP_MATCH */ 1532 RCAR_GP_PIN(2, 24), 1533 }; 1534 1535 static const unsigned int avb_avtp_match_mux[] = { 1536 AVB_AVTP_MATCH_MARK, 1537 }; 1538 1539 static const unsigned int avb_avtp_capture_pins[] = { 1540 /* AVB_AVTP_CAPTURE */ 1541 RCAR_GP_PIN(2, 25), 1542 }; 1543 1544 static const unsigned int avb_avtp_capture_mux[] = { 1545 AVB_AVTP_CAPTURE_MARK, 1546 }; 1547 1548 /* - CAN ------------------------------------------------------------------ */ 1549 static const unsigned int can0_data_pins[] = { 1550 /* TX, RX */ 1551 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 1552 }; 1553 1554 static const unsigned int can0_data_mux[] = { 1555 CAN0_TX_MARK, CAN0_RX_MARK, 1556 }; 1557 1558 static const unsigned int can1_data_pins[] = { 1559 /* TX, RX */ 1560 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7), 1561 }; 1562 1563 static const unsigned int can1_data_mux[] = { 1564 CAN1_TX_MARK, CAN1_RX_MARK, 1565 }; 1566 1567 /* - CAN Clock -------------------------------------------------------------- */ 1568 static const unsigned int can_clk_pins[] = { 1569 /* CLK */ 1570 RCAR_GP_PIN(0, 14), 1571 }; 1572 1573 static const unsigned int can_clk_mux[] = { 1574 CAN_CLK_MARK, 1575 }; 1576 1577 /* - CAN FD --------------------------------------------------------------- */ 1578 static const unsigned int canfd0_data_pins[] = { 1579 /* TX, RX */ 1580 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 1581 }; 1582 1583 static const unsigned int canfd0_data_mux[] = { 1584 CANFD0_TX_MARK, CANFD0_RX_MARK, 1585 }; 1586 1587 static const unsigned int canfd1_data_pins[] = { 1588 /* TX, RX */ 1589 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7), 1590 }; 1591 1592 static const unsigned int canfd1_data_mux[] = { 1593 CANFD1_TX_MARK, CANFD1_RX_MARK, 1594 }; 1595 1596 #ifdef CONFIG_PINCTRL_PFC_R8A77990 1597 /* - DRIF0 --------------------------------------------------------------- */ 1598 static const unsigned int drif0_ctrl_a_pins[] = { 1599 /* CLK, SYNC */ 1600 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 19), 1601 }; 1602 1603 static const unsigned int drif0_ctrl_a_mux[] = { 1604 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK, 1605 }; 1606 1607 static const unsigned int drif0_data0_a_pins[] = { 1608 /* D0 */ 1609 RCAR_GP_PIN(5, 17), 1610 }; 1611 1612 static const unsigned int drif0_data0_a_mux[] = { 1613 RIF0_D0_A_MARK, 1614 }; 1615 1616 static const unsigned int drif0_data1_a_pins[] = { 1617 /* D1 */ 1618 RCAR_GP_PIN(5, 18), 1619 }; 1620 1621 static const unsigned int drif0_data1_a_mux[] = { 1622 RIF0_D1_A_MARK, 1623 }; 1624 1625 static const unsigned int drif0_ctrl_b_pins[] = { 1626 /* CLK, SYNC */ 1627 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15), 1628 }; 1629 1630 static const unsigned int drif0_ctrl_b_mux[] = { 1631 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK, 1632 }; 1633 1634 static const unsigned int drif0_data0_b_pins[] = { 1635 /* D0 */ 1636 RCAR_GP_PIN(3, 13), 1637 }; 1638 1639 static const unsigned int drif0_data0_b_mux[] = { 1640 RIF0_D0_B_MARK, 1641 }; 1642 1643 static const unsigned int drif0_data1_b_pins[] = { 1644 /* D1 */ 1645 RCAR_GP_PIN(3, 14), 1646 }; 1647 1648 static const unsigned int drif0_data1_b_mux[] = { 1649 RIF0_D1_B_MARK, 1650 }; 1651 1652 /* - DRIF1 --------------------------------------------------------------- */ 1653 static const unsigned int drif1_ctrl_pins[] = { 1654 /* CLK, SYNC */ 1655 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 1), 1656 }; 1657 1658 static const unsigned int drif1_ctrl_mux[] = { 1659 RIF1_CLK_MARK, RIF1_SYNC_MARK, 1660 }; 1661 1662 static const unsigned int drif1_data0_pins[] = { 1663 /* D0 */ 1664 RCAR_GP_PIN(5, 2), 1665 }; 1666 1667 static const unsigned int drif1_data0_mux[] = { 1668 RIF1_D0_MARK, 1669 }; 1670 1671 static const unsigned int drif1_data1_pins[] = { 1672 /* D1 */ 1673 RCAR_GP_PIN(5, 3), 1674 }; 1675 1676 static const unsigned int drif1_data1_mux[] = { 1677 RIF1_D1_MARK, 1678 }; 1679 1680 /* - DRIF2 --------------------------------------------------------------- */ 1681 static const unsigned int drif2_ctrl_a_pins[] = { 1682 /* CLK, SYNC */ 1683 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 1684 }; 1685 1686 static const unsigned int drif2_ctrl_a_mux[] = { 1687 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK, 1688 }; 1689 1690 static const unsigned int drif2_data0_a_pins[] = { 1691 /* D0 */ 1692 RCAR_GP_PIN(2, 8), 1693 }; 1694 1695 static const unsigned int drif2_data0_a_mux[] = { 1696 RIF2_D0_A_MARK, 1697 }; 1698 1699 static const unsigned int drif2_data1_a_pins[] = { 1700 /* D1 */ 1701 RCAR_GP_PIN(2, 9), 1702 }; 1703 1704 static const unsigned int drif2_data1_a_mux[] = { 1705 RIF2_D1_A_MARK, 1706 }; 1707 1708 static const unsigned int drif2_ctrl_b_pins[] = { 1709 /* CLK, SYNC */ 1710 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 1711 }; 1712 1713 static const unsigned int drif2_ctrl_b_mux[] = { 1714 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK, 1715 }; 1716 1717 static const unsigned int drif2_data0_b_pins[] = { 1718 /* D0 */ 1719 RCAR_GP_PIN(1, 6), 1720 }; 1721 1722 static const unsigned int drif2_data0_b_mux[] = { 1723 RIF2_D0_B_MARK, 1724 }; 1725 1726 static const unsigned int drif2_data1_b_pins[] = { 1727 /* D1 */ 1728 RCAR_GP_PIN(1, 7), 1729 }; 1730 1731 static const unsigned int drif2_data1_b_mux[] = { 1732 RIF2_D1_B_MARK, 1733 }; 1734 1735 /* - DRIF3 --------------------------------------------------------------- */ 1736 static const unsigned int drif3_ctrl_a_pins[] = { 1737 /* CLK, SYNC */ 1738 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), 1739 }; 1740 1741 static const unsigned int drif3_ctrl_a_mux[] = { 1742 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK, 1743 }; 1744 1745 static const unsigned int drif3_data0_a_pins[] = { 1746 /* D0 */ 1747 RCAR_GP_PIN(2, 12), 1748 }; 1749 1750 static const unsigned int drif3_data0_a_mux[] = { 1751 RIF3_D0_A_MARK, 1752 }; 1753 1754 static const unsigned int drif3_data1_a_pins[] = { 1755 /* D1 */ 1756 RCAR_GP_PIN(2, 13), 1757 }; 1758 1759 static const unsigned int drif3_data1_a_mux[] = { 1760 RIF3_D1_A_MARK, 1761 }; 1762 1763 static const unsigned int drif3_ctrl_b_pins[] = { 1764 /* CLK, SYNC */ 1765 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), 1766 }; 1767 1768 static const unsigned int drif3_ctrl_b_mux[] = { 1769 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK, 1770 }; 1771 1772 static const unsigned int drif3_data0_b_pins[] = { 1773 /* D0 */ 1774 RCAR_GP_PIN(0, 10), 1775 }; 1776 1777 static const unsigned int drif3_data0_b_mux[] = { 1778 RIF3_D0_B_MARK, 1779 }; 1780 1781 static const unsigned int drif3_data1_b_pins[] = { 1782 /* D1 */ 1783 RCAR_GP_PIN(0, 11), 1784 }; 1785 1786 static const unsigned int drif3_data1_b_mux[] = { 1787 RIF3_D1_B_MARK, 1788 }; 1789 #endif /* CONFIG_PINCTRL_PFC_R8A77990 */ 1790 1791 /* - DU --------------------------------------------------------------------- */ 1792 static const unsigned int du_rgb666_pins[] = { 1793 /* R[7:2], G[7:2], B[7:2] */ 1794 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5), 1795 RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 0), 1796 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 10), 1797 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11), 1798 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), 1799 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 1800 }; 1801 static const unsigned int du_rgb666_mux[] = { 1802 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, 1803 DU_DR3_MARK, DU_DR2_MARK, 1804 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, 1805 DU_DG3_MARK, DU_DG2_MARK, 1806 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, 1807 DU_DB3_MARK, DU_DB2_MARK, 1808 }; 1809 static const unsigned int du_rgb888_pins[] = { 1810 /* R[7:0], G[7:0], B[7:0] */ 1811 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5), 1812 RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 0), 1813 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), 1814 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 10), 1815 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11), 1816 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9), 1817 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), 1818 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 1819 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), 1820 }; 1821 static const unsigned int du_rgb888_mux[] = { 1822 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, 1823 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK, 1824 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, 1825 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK, 1826 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, 1827 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK, 1828 }; 1829 static const unsigned int du_clk_in_0_pins[] = { 1830 /* CLKIN0 */ 1831 RCAR_GP_PIN(0, 16), 1832 }; 1833 static const unsigned int du_clk_in_0_mux[] = { 1834 DU_DOTCLKIN0_MARK 1835 }; 1836 static const unsigned int du_clk_in_1_pins[] = { 1837 /* CLKIN1 */ 1838 RCAR_GP_PIN(1, 1), 1839 }; 1840 static const unsigned int du_clk_in_1_mux[] = { 1841 DU_DOTCLKIN1_MARK 1842 }; 1843 static const unsigned int du_clk_out_0_pins[] = { 1844 /* CLKOUT */ 1845 RCAR_GP_PIN(1, 3), 1846 }; 1847 static const unsigned int du_clk_out_0_mux[] = { 1848 DU_DOTCLKOUT0_MARK 1849 }; 1850 static const unsigned int du_sync_pins[] = { 1851 /* VSYNC, HSYNC */ 1852 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 8), 1853 }; 1854 static const unsigned int du_sync_mux[] = { 1855 DU_VSYNC_MARK, DU_HSYNC_MARK 1856 }; 1857 static const unsigned int du_disp_cde_pins[] = { 1858 /* DISP_CDE */ 1859 RCAR_GP_PIN(1, 1), 1860 }; 1861 static const unsigned int du_disp_cde_mux[] = { 1862 DU_DISP_CDE_MARK, 1863 }; 1864 static const unsigned int du_cde_pins[] = { 1865 /* CDE */ 1866 RCAR_GP_PIN(1, 0), 1867 }; 1868 static const unsigned int du_cde_mux[] = { 1869 DU_CDE_MARK, 1870 }; 1871 static const unsigned int du_disp_pins[] = { 1872 /* DISP */ 1873 RCAR_GP_PIN(1, 2), 1874 }; 1875 static const unsigned int du_disp_mux[] = { 1876 DU_DISP_MARK, 1877 }; 1878 1879 /* - HSCIF0 --------------------------------------------------*/ 1880 static const unsigned int hscif0_data_a_pins[] = { 1881 /* RX, TX */ 1882 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), 1883 }; 1884 1885 static const unsigned int hscif0_data_a_mux[] = { 1886 HRX0_A_MARK, HTX0_A_MARK, 1887 }; 1888 1889 static const unsigned int hscif0_clk_a_pins[] = { 1890 /* SCK */ 1891 RCAR_GP_PIN(5, 7), 1892 }; 1893 1894 static const unsigned int hscif0_clk_a_mux[] = { 1895 HSCK0_A_MARK, 1896 }; 1897 1898 static const unsigned int hscif0_ctrl_a_pins[] = { 1899 /* RTS, CTS */ 1900 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), 1901 }; 1902 1903 static const unsigned int hscif0_ctrl_a_mux[] = { 1904 HRTS0_N_A_MARK, HCTS0_N_A_MARK, 1905 }; 1906 1907 static const unsigned int hscif0_data_b_pins[] = { 1908 /* RX, TX */ 1909 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), 1910 }; 1911 1912 static const unsigned int hscif0_data_b_mux[] = { 1913 HRX0_B_MARK, HTX0_B_MARK, 1914 }; 1915 1916 static const unsigned int hscif0_clk_b_pins[] = { 1917 /* SCK */ 1918 RCAR_GP_PIN(6, 13), 1919 }; 1920 1921 static const unsigned int hscif0_clk_b_mux[] = { 1922 HSCK0_B_MARK, 1923 }; 1924 1925 /* - HSCIF1 ------------------------------------------------- */ 1926 static const unsigned int hscif1_data_a_pins[] = { 1927 /* RX, TX */ 1928 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 1929 }; 1930 1931 static const unsigned int hscif1_data_a_mux[] = { 1932 HRX1_A_MARK, HTX1_A_MARK, 1933 }; 1934 1935 static const unsigned int hscif1_clk_a_pins[] = { 1936 /* SCK */ 1937 RCAR_GP_PIN(5, 0), 1938 }; 1939 1940 static const unsigned int hscif1_clk_a_mux[] = { 1941 HSCK1_A_MARK, 1942 }; 1943 1944 static const unsigned int hscif1_data_b_pins[] = { 1945 /* RX, TX */ 1946 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), 1947 }; 1948 1949 static const unsigned int hscif1_data_b_mux[] = { 1950 HRX1_B_MARK, HTX1_B_MARK, 1951 }; 1952 1953 static const unsigned int hscif1_clk_b_pins[] = { 1954 /* SCK */ 1955 RCAR_GP_PIN(3, 0), 1956 }; 1957 1958 static const unsigned int hscif1_clk_b_mux[] = { 1959 HSCK1_B_MARK, 1960 }; 1961 1962 static const unsigned int hscif1_ctrl_b_pins[] = { 1963 /* RTS, CTS */ 1964 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), 1965 }; 1966 1967 static const unsigned int hscif1_ctrl_b_mux[] = { 1968 HRTS1_N_B_MARK, HCTS1_N_B_MARK, 1969 }; 1970 1971 /* - HSCIF2 ------------------------------------------------- */ 1972 static const unsigned int hscif2_data_a_pins[] = { 1973 /* RX, TX */ 1974 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), 1975 }; 1976 1977 static const unsigned int hscif2_data_a_mux[] = { 1978 HRX2_A_MARK, HTX2_A_MARK, 1979 }; 1980 1981 static const unsigned int hscif2_clk_a_pins[] = { 1982 /* SCK */ 1983 RCAR_GP_PIN(6, 14), 1984 }; 1985 1986 static const unsigned int hscif2_clk_a_mux[] = { 1987 HSCK2_A_MARK, 1988 }; 1989 1990 static const unsigned int hscif2_ctrl_a_pins[] = { 1991 /* RTS, CTS */ 1992 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15), 1993 }; 1994 1995 static const unsigned int hscif2_ctrl_a_mux[] = { 1996 HRTS2_N_A_MARK, HCTS2_N_A_MARK, 1997 }; 1998 1999 static const unsigned int hscif2_data_b_pins[] = { 2000 /* RX, TX */ 2001 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 2002 }; 2003 2004 static const unsigned int hscif2_data_b_mux[] = { 2005 HRX2_B_MARK, HTX2_B_MARK, 2006 }; 2007 2008 /* - HSCIF3 ------------------------------------------------*/ 2009 static const unsigned int hscif3_data_a_pins[] = { 2010 /* RX, TX */ 2011 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 2012 }; 2013 2014 static const unsigned int hscif3_data_a_mux[] = { 2015 HRX3_A_MARK, HTX3_A_MARK, 2016 }; 2017 2018 static const unsigned int hscif3_data_b_pins[] = { 2019 /* RX, TX */ 2020 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), 2021 }; 2022 2023 static const unsigned int hscif3_data_b_mux[] = { 2024 HRX3_B_MARK, HTX3_B_MARK, 2025 }; 2026 2027 static const unsigned int hscif3_clk_b_pins[] = { 2028 /* SCK */ 2029 RCAR_GP_PIN(0, 4), 2030 }; 2031 2032 static const unsigned int hscif3_clk_b_mux[] = { 2033 HSCK3_B_MARK, 2034 }; 2035 2036 static const unsigned int hscif3_data_c_pins[] = { 2037 /* RX, TX */ 2038 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 9), 2039 }; 2040 2041 static const unsigned int hscif3_data_c_mux[] = { 2042 HRX3_C_MARK, HTX3_C_MARK, 2043 }; 2044 2045 static const unsigned int hscif3_clk_c_pins[] = { 2046 /* SCK */ 2047 RCAR_GP_PIN(2, 11), 2048 }; 2049 2050 static const unsigned int hscif3_clk_c_mux[] = { 2051 HSCK3_C_MARK, 2052 }; 2053 2054 static const unsigned int hscif3_ctrl_c_pins[] = { 2055 /* RTS, CTS */ 2056 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 12), 2057 }; 2058 2059 static const unsigned int hscif3_ctrl_c_mux[] = { 2060 HRTS3_N_C_MARK, HCTS3_N_C_MARK, 2061 }; 2062 2063 static const unsigned int hscif3_data_d_pins[] = { 2064 /* RX, TX */ 2065 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 3), 2066 }; 2067 2068 static const unsigned int hscif3_data_d_mux[] = { 2069 HRX3_D_MARK, HTX3_D_MARK, 2070 }; 2071 2072 static const unsigned int hscif3_data_e_pins[] = { 2073 /* RX, TX */ 2074 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), 2075 }; 2076 2077 static const unsigned int hscif3_data_e_mux[] = { 2078 HRX3_E_MARK, HTX3_E_MARK, 2079 }; 2080 2081 static const unsigned int hscif3_ctrl_e_pins[] = { 2082 /* RTS, CTS */ 2083 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 8), 2084 }; 2085 2086 static const unsigned int hscif3_ctrl_e_mux[] = { 2087 HRTS3_N_E_MARK, HCTS3_N_E_MARK, 2088 }; 2089 2090 /* - HSCIF4 -------------------------------------------------- */ 2091 static const unsigned int hscif4_data_a_pins[] = { 2092 /* RX, TX */ 2093 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), 2094 }; 2095 2096 static const unsigned int hscif4_data_a_mux[] = { 2097 HRX4_A_MARK, HTX4_A_MARK, 2098 }; 2099 2100 static const unsigned int hscif4_clk_a_pins[] = { 2101 /* SCK */ 2102 RCAR_GP_PIN(2, 0), 2103 }; 2104 2105 static const unsigned int hscif4_clk_a_mux[] = { 2106 HSCK4_A_MARK, 2107 }; 2108 2109 static const unsigned int hscif4_ctrl_a_pins[] = { 2110 /* RTS, CTS */ 2111 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1), 2112 }; 2113 2114 static const unsigned int hscif4_ctrl_a_mux[] = { 2115 HRTS4_N_A_MARK, HCTS4_N_A_MARK, 2116 }; 2117 2118 static const unsigned int hscif4_data_b_pins[] = { 2119 /* RX, TX */ 2120 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7), 2121 }; 2122 2123 static const unsigned int hscif4_data_b_mux[] = { 2124 HRX4_B_MARK, HTX4_B_MARK, 2125 }; 2126 2127 static const unsigned int hscif4_clk_b_pins[] = { 2128 /* SCK */ 2129 RCAR_GP_PIN(2, 6), 2130 }; 2131 2132 static const unsigned int hscif4_clk_b_mux[] = { 2133 HSCK4_B_MARK, 2134 }; 2135 2136 static const unsigned int hscif4_data_c_pins[] = { 2137 /* RX, TX */ 2138 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 2139 }; 2140 2141 static const unsigned int hscif4_data_c_mux[] = { 2142 HRX4_C_MARK, HTX4_C_MARK, 2143 }; 2144 2145 static const unsigned int hscif4_data_d_pins[] = { 2146 /* RX, TX */ 2147 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), 2148 }; 2149 2150 static const unsigned int hscif4_data_d_mux[] = { 2151 HRX4_D_MARK, HTX4_D_MARK, 2152 }; 2153 2154 static const unsigned int hscif4_data_e_pins[] = { 2155 /* RX, TX */ 2156 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), 2157 }; 2158 2159 static const unsigned int hscif4_data_e_mux[] = { 2160 HRX4_E_MARK, HTX4_E_MARK, 2161 }; 2162 2163 /* - I2C -------------------------------------------------------------------- */ 2164 static const unsigned int i2c1_a_pins[] = { 2165 /* SCL, SDA */ 2166 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), 2167 }; 2168 2169 static const unsigned int i2c1_a_mux[] = { 2170 SCL1_A_MARK, SDA1_A_MARK, 2171 }; 2172 2173 static const unsigned int i2c1_b_pins[] = { 2174 /* SCL, SDA */ 2175 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18), 2176 }; 2177 2178 static const unsigned int i2c1_b_mux[] = { 2179 SCL1_B_MARK, SDA1_B_MARK, 2180 }; 2181 2182 static const unsigned int i2c1_c_pins[] = { 2183 /* SCL, SDA */ 2184 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 5), 2185 }; 2186 2187 static const unsigned int i2c1_c_mux[] = { 2188 SCL1_C_MARK, SDA1_C_MARK, 2189 }; 2190 2191 static const unsigned int i2c1_d_pins[] = { 2192 /* SCL, SDA */ 2193 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15), 2194 }; 2195 2196 static const unsigned int i2c1_d_mux[] = { 2197 SCL1_D_MARK, SDA1_D_MARK, 2198 }; 2199 2200 static const unsigned int i2c2_a_pins[] = { 2201 /* SCL, SDA */ 2202 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 0), 2203 }; 2204 2205 static const unsigned int i2c2_a_mux[] = { 2206 SCL2_A_MARK, SDA2_A_MARK, 2207 }; 2208 2209 static const unsigned int i2c2_b_pins[] = { 2210 /* SCL, SDA */ 2211 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), 2212 }; 2213 2214 static const unsigned int i2c2_b_mux[] = { 2215 SCL2_B_MARK, SDA2_B_MARK, 2216 }; 2217 2218 static const unsigned int i2c2_c_pins[] = { 2219 /* SCL, SDA */ 2220 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), 2221 }; 2222 2223 static const unsigned int i2c2_c_mux[] = { 2224 SCL2_C_MARK, SDA2_C_MARK, 2225 }; 2226 2227 static const unsigned int i2c2_d_pins[] = { 2228 /* SCL, SDA */ 2229 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), 2230 }; 2231 2232 static const unsigned int i2c2_d_mux[] = { 2233 SCL2_D_MARK, SDA2_D_MARK, 2234 }; 2235 2236 static const unsigned int i2c2_e_pins[] = { 2237 /* SCL, SDA */ 2238 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 0), 2239 }; 2240 2241 static const unsigned int i2c2_e_mux[] = { 2242 SCL2_E_MARK, SDA2_E_MARK, 2243 }; 2244 2245 static const unsigned int i2c4_pins[] = { 2246 /* SCL, SDA */ 2247 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17), 2248 }; 2249 2250 static const unsigned int i2c4_mux[] = { 2251 SCL4_MARK, SDA4_MARK, 2252 }; 2253 2254 static const unsigned int i2c5_pins[] = { 2255 /* SCL, SDA */ 2256 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), 2257 }; 2258 2259 static const unsigned int i2c5_mux[] = { 2260 SCL5_MARK, SDA5_MARK, 2261 }; 2262 2263 static const unsigned int i2c6_a_pins[] = { 2264 /* SCL, SDA */ 2265 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 8), 2266 }; 2267 2268 static const unsigned int i2c6_a_mux[] = { 2269 SCL6_A_MARK, SDA6_A_MARK, 2270 }; 2271 2272 static const unsigned int i2c6_b_pins[] = { 2273 /* SCL, SDA */ 2274 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1), 2275 }; 2276 2277 static const unsigned int i2c6_b_mux[] = { 2278 SCL6_B_MARK, SDA6_B_MARK, 2279 }; 2280 2281 static const unsigned int i2c7_a_pins[] = { 2282 /* SCL, SDA */ 2283 RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 25), 2284 }; 2285 2286 static const unsigned int i2c7_a_mux[] = { 2287 SCL7_A_MARK, SDA7_A_MARK, 2288 }; 2289 2290 static const unsigned int i2c7_b_pins[] = { 2291 /* SCL, SDA */ 2292 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14), 2293 }; 2294 2295 static const unsigned int i2c7_b_mux[] = { 2296 SCL7_B_MARK, SDA7_B_MARK, 2297 }; 2298 2299 /* - INTC-EX ---------------------------------------------------------------- */ 2300 static const unsigned int intc_ex_irq0_pins[] = { 2301 /* IRQ0 */ 2302 RCAR_GP_PIN(1, 0), 2303 }; 2304 static const unsigned int intc_ex_irq0_mux[] = { 2305 IRQ0_MARK, 2306 }; 2307 static const unsigned int intc_ex_irq1_pins[] = { 2308 /* IRQ1 */ 2309 RCAR_GP_PIN(1, 1), 2310 }; 2311 static const unsigned int intc_ex_irq1_mux[] = { 2312 IRQ1_MARK, 2313 }; 2314 static const unsigned int intc_ex_irq2_pins[] = { 2315 /* IRQ2 */ 2316 RCAR_GP_PIN(1, 2), 2317 }; 2318 static const unsigned int intc_ex_irq2_mux[] = { 2319 IRQ2_MARK, 2320 }; 2321 static const unsigned int intc_ex_irq3_pins[] = { 2322 /* IRQ3 */ 2323 RCAR_GP_PIN(1, 9), 2324 }; 2325 static const unsigned int intc_ex_irq3_mux[] = { 2326 IRQ3_MARK, 2327 }; 2328 static const unsigned int intc_ex_irq4_pins[] = { 2329 /* IRQ4 */ 2330 RCAR_GP_PIN(1, 10), 2331 }; 2332 static const unsigned int intc_ex_irq4_mux[] = { 2333 IRQ4_MARK, 2334 }; 2335 static const unsigned int intc_ex_irq5_pins[] = { 2336 /* IRQ5 */ 2337 RCAR_GP_PIN(0, 7), 2338 }; 2339 static const unsigned int intc_ex_irq5_mux[] = { 2340 IRQ5_MARK, 2341 }; 2342 2343 /* - MSIOF0 ----------------------------------------------------------------- */ 2344 static const unsigned int msiof0_clk_pins[] = { 2345 /* SCK */ 2346 RCAR_GP_PIN(5, 10), 2347 }; 2348 2349 static const unsigned int msiof0_clk_mux[] = { 2350 MSIOF0_SCK_MARK, 2351 }; 2352 2353 static const unsigned int msiof0_sync_pins[] = { 2354 /* SYNC */ 2355 RCAR_GP_PIN(5, 13), 2356 }; 2357 2358 static const unsigned int msiof0_sync_mux[] = { 2359 MSIOF0_SYNC_MARK, 2360 }; 2361 2362 static const unsigned int msiof0_ss1_pins[] = { 2363 /* SS1 */ 2364 RCAR_GP_PIN(5, 14), 2365 }; 2366 2367 static const unsigned int msiof0_ss1_mux[] = { 2368 MSIOF0_SS1_MARK, 2369 }; 2370 2371 static const unsigned int msiof0_ss2_pins[] = { 2372 /* SS2 */ 2373 RCAR_GP_PIN(5, 15), 2374 }; 2375 2376 static const unsigned int msiof0_ss2_mux[] = { 2377 MSIOF0_SS2_MARK, 2378 }; 2379 2380 static const unsigned int msiof0_txd_pins[] = { 2381 /* TXD */ 2382 RCAR_GP_PIN(5, 12), 2383 }; 2384 2385 static const unsigned int msiof0_txd_mux[] = { 2386 MSIOF0_TXD_MARK, 2387 }; 2388 2389 static const unsigned int msiof0_rxd_pins[] = { 2390 /* RXD */ 2391 RCAR_GP_PIN(5, 11), 2392 }; 2393 2394 static const unsigned int msiof0_rxd_mux[] = { 2395 MSIOF0_RXD_MARK, 2396 }; 2397 2398 /* - MSIOF1 ----------------------------------------------------------------- */ 2399 static const unsigned int msiof1_clk_pins[] = { 2400 /* SCK */ 2401 RCAR_GP_PIN(1, 19), 2402 }; 2403 2404 static const unsigned int msiof1_clk_mux[] = { 2405 MSIOF1_SCK_MARK, 2406 }; 2407 2408 static const unsigned int msiof1_sync_pins[] = { 2409 /* SYNC */ 2410 RCAR_GP_PIN(1, 16), 2411 }; 2412 2413 static const unsigned int msiof1_sync_mux[] = { 2414 MSIOF1_SYNC_MARK, 2415 }; 2416 2417 static const unsigned int msiof1_ss1_pins[] = { 2418 /* SS1 */ 2419 RCAR_GP_PIN(1, 14), 2420 }; 2421 2422 static const unsigned int msiof1_ss1_mux[] = { 2423 MSIOF1_SS1_MARK, 2424 }; 2425 2426 static const unsigned int msiof1_ss2_pins[] = { 2427 /* SS2 */ 2428 RCAR_GP_PIN(1, 15), 2429 }; 2430 2431 static const unsigned int msiof1_ss2_mux[] = { 2432 MSIOF1_SS2_MARK, 2433 }; 2434 2435 static const unsigned int msiof1_txd_pins[] = { 2436 /* TXD */ 2437 RCAR_GP_PIN(1, 18), 2438 }; 2439 2440 static const unsigned int msiof1_txd_mux[] = { 2441 MSIOF1_TXD_MARK, 2442 }; 2443 2444 static const unsigned int msiof1_rxd_pins[] = { 2445 /* RXD */ 2446 RCAR_GP_PIN(1, 17), 2447 }; 2448 2449 static const unsigned int msiof1_rxd_mux[] = { 2450 MSIOF1_RXD_MARK, 2451 }; 2452 2453 /* - MSIOF2 ----------------------------------------------------------------- */ 2454 static const unsigned int msiof2_clk_a_pins[] = { 2455 /* SCK */ 2456 RCAR_GP_PIN(0, 8), 2457 }; 2458 2459 static const unsigned int msiof2_clk_a_mux[] = { 2460 MSIOF2_SCK_A_MARK, 2461 }; 2462 2463 static const unsigned int msiof2_sync_a_pins[] = { 2464 /* SYNC */ 2465 RCAR_GP_PIN(0, 9), 2466 }; 2467 2468 static const unsigned int msiof2_sync_a_mux[] = { 2469 MSIOF2_SYNC_A_MARK, 2470 }; 2471 2472 static const unsigned int msiof2_ss1_a_pins[] = { 2473 /* SS1 */ 2474 RCAR_GP_PIN(0, 15), 2475 }; 2476 2477 static const unsigned int msiof2_ss1_a_mux[] = { 2478 MSIOF2_SS1_A_MARK, 2479 }; 2480 2481 static const unsigned int msiof2_ss2_a_pins[] = { 2482 /* SS2 */ 2483 RCAR_GP_PIN(0, 14), 2484 }; 2485 2486 static const unsigned int msiof2_ss2_a_mux[] = { 2487 MSIOF2_SS2_A_MARK, 2488 }; 2489 2490 static const unsigned int msiof2_txd_a_pins[] = { 2491 /* TXD */ 2492 RCAR_GP_PIN(0, 11), 2493 }; 2494 2495 static const unsigned int msiof2_txd_a_mux[] = { 2496 MSIOF2_TXD_A_MARK, 2497 }; 2498 2499 static const unsigned int msiof2_rxd_a_pins[] = { 2500 /* RXD */ 2501 RCAR_GP_PIN(0, 10), 2502 }; 2503 2504 static const unsigned int msiof2_rxd_a_mux[] = { 2505 MSIOF2_RXD_A_MARK, 2506 }; 2507 2508 static const unsigned int msiof2_clk_b_pins[] = { 2509 /* SCK */ 2510 RCAR_GP_PIN(1, 13), 2511 }; 2512 2513 static const unsigned int msiof2_clk_b_mux[] = { 2514 MSIOF2_SCK_B_MARK, 2515 }; 2516 2517 static const unsigned int msiof2_sync_b_pins[] = { 2518 /* SYNC */ 2519 RCAR_GP_PIN(1, 10), 2520 }; 2521 2522 static const unsigned int msiof2_sync_b_mux[] = { 2523 MSIOF2_SYNC_B_MARK, 2524 }; 2525 2526 static const unsigned int msiof2_ss1_b_pins[] = { 2527 /* SS1 */ 2528 RCAR_GP_PIN(1, 16), 2529 }; 2530 2531 static const unsigned int msiof2_ss1_b_mux[] = { 2532 MSIOF2_SS1_B_MARK, 2533 }; 2534 2535 static const unsigned int msiof2_ss2_b_pins[] = { 2536 /* SS2 */ 2537 RCAR_GP_PIN(1, 12), 2538 }; 2539 2540 static const unsigned int msiof2_ss2_b_mux[] = { 2541 MSIOF2_SS2_B_MARK, 2542 }; 2543 2544 static const unsigned int msiof2_txd_b_pins[] = { 2545 /* TXD */ 2546 RCAR_GP_PIN(1, 15), 2547 }; 2548 2549 static const unsigned int msiof2_txd_b_mux[] = { 2550 MSIOF2_TXD_B_MARK, 2551 }; 2552 2553 static const unsigned int msiof2_rxd_b_pins[] = { 2554 /* RXD */ 2555 RCAR_GP_PIN(1, 14), 2556 }; 2557 2558 static const unsigned int msiof2_rxd_b_mux[] = { 2559 MSIOF2_RXD_B_MARK, 2560 }; 2561 2562 /* - MSIOF3 ----------------------------------------------------------------- */ 2563 static const unsigned int msiof3_clk_a_pins[] = { 2564 /* SCK */ 2565 RCAR_GP_PIN(0, 0), 2566 }; 2567 2568 static const unsigned int msiof3_clk_a_mux[] = { 2569 MSIOF3_SCK_A_MARK, 2570 }; 2571 2572 static const unsigned int msiof3_sync_a_pins[] = { 2573 /* SYNC */ 2574 RCAR_GP_PIN(0, 1), 2575 }; 2576 2577 static const unsigned int msiof3_sync_a_mux[] = { 2578 MSIOF3_SYNC_A_MARK, 2579 }; 2580 2581 static const unsigned int msiof3_ss1_a_pins[] = { 2582 /* SS1 */ 2583 RCAR_GP_PIN(0, 15), 2584 }; 2585 2586 static const unsigned int msiof3_ss1_a_mux[] = { 2587 MSIOF3_SS1_A_MARK, 2588 }; 2589 2590 static const unsigned int msiof3_ss2_a_pins[] = { 2591 /* SS2 */ 2592 RCAR_GP_PIN(0, 4), 2593 }; 2594 2595 static const unsigned int msiof3_ss2_a_mux[] = { 2596 MSIOF3_SS2_A_MARK, 2597 }; 2598 2599 static const unsigned int msiof3_txd_a_pins[] = { 2600 /* TXD */ 2601 RCAR_GP_PIN(0, 3), 2602 }; 2603 2604 static const unsigned int msiof3_txd_a_mux[] = { 2605 MSIOF3_TXD_A_MARK, 2606 }; 2607 2608 static const unsigned int msiof3_rxd_a_pins[] = { 2609 /* RXD */ 2610 RCAR_GP_PIN(0, 2), 2611 }; 2612 2613 static const unsigned int msiof3_rxd_a_mux[] = { 2614 MSIOF3_RXD_A_MARK, 2615 }; 2616 2617 static const unsigned int msiof3_clk_b_pins[] = { 2618 /* SCK */ 2619 RCAR_GP_PIN(1, 5), 2620 }; 2621 2622 static const unsigned int msiof3_clk_b_mux[] = { 2623 MSIOF3_SCK_B_MARK, 2624 }; 2625 2626 static const unsigned int msiof3_sync_b_pins[] = { 2627 /* SYNC */ 2628 RCAR_GP_PIN(1, 4), 2629 }; 2630 2631 static const unsigned int msiof3_sync_b_mux[] = { 2632 MSIOF3_SYNC_B_MARK, 2633 }; 2634 2635 static const unsigned int msiof3_ss1_b_pins[] = { 2636 /* SS1 */ 2637 RCAR_GP_PIN(1, 0), 2638 }; 2639 2640 static const unsigned int msiof3_ss1_b_mux[] = { 2641 MSIOF3_SS1_B_MARK, 2642 }; 2643 2644 static const unsigned int msiof3_txd_b_pins[] = { 2645 /* TXD */ 2646 RCAR_GP_PIN(1, 7), 2647 }; 2648 2649 static const unsigned int msiof3_txd_b_mux[] = { 2650 MSIOF3_TXD_B_MARK, 2651 }; 2652 2653 static const unsigned int msiof3_rxd_b_pins[] = { 2654 /* RXD */ 2655 RCAR_GP_PIN(1, 6), 2656 }; 2657 2658 static const unsigned int msiof3_rxd_b_mux[] = { 2659 MSIOF3_RXD_B_MARK, 2660 }; 2661 2662 /* - PWM0 --------------------------------------------------------------------*/ 2663 static const unsigned int pwm0_a_pins[] = { 2664 /* PWM */ 2665 RCAR_GP_PIN(2, 22), 2666 }; 2667 2668 static const unsigned int pwm0_a_mux[] = { 2669 PWM0_A_MARK, 2670 }; 2671 2672 static const unsigned int pwm0_b_pins[] = { 2673 /* PWM */ 2674 RCAR_GP_PIN(6, 3), 2675 }; 2676 2677 static const unsigned int pwm0_b_mux[] = { 2678 PWM0_B_MARK, 2679 }; 2680 2681 /* - PWM1 --------------------------------------------------------------------*/ 2682 static const unsigned int pwm1_a_pins[] = { 2683 /* PWM */ 2684 RCAR_GP_PIN(2, 23), 2685 }; 2686 2687 static const unsigned int pwm1_a_mux[] = { 2688 PWM1_A_MARK, 2689 }; 2690 2691 static const unsigned int pwm1_b_pins[] = { 2692 /* PWM */ 2693 RCAR_GP_PIN(6, 4), 2694 }; 2695 2696 static const unsigned int pwm1_b_mux[] = { 2697 PWM1_B_MARK, 2698 }; 2699 2700 /* - PWM2 --------------------------------------------------------------------*/ 2701 static const unsigned int pwm2_a_pins[] = { 2702 /* PWM */ 2703 RCAR_GP_PIN(1, 0), 2704 }; 2705 2706 static const unsigned int pwm2_a_mux[] = { 2707 PWM2_A_MARK, 2708 }; 2709 2710 static const unsigned int pwm2_b_pins[] = { 2711 /* PWM */ 2712 RCAR_GP_PIN(1, 4), 2713 }; 2714 2715 static const unsigned int pwm2_b_mux[] = { 2716 PWM2_B_MARK, 2717 }; 2718 2719 static const unsigned int pwm2_c_pins[] = { 2720 /* PWM */ 2721 RCAR_GP_PIN(6, 5), 2722 }; 2723 2724 static const unsigned int pwm2_c_mux[] = { 2725 PWM2_C_MARK, 2726 }; 2727 2728 /* - PWM3 --------------------------------------------------------------------*/ 2729 static const unsigned int pwm3_a_pins[] = { 2730 /* PWM */ 2731 RCAR_GP_PIN(1, 1), 2732 }; 2733 2734 static const unsigned int pwm3_a_mux[] = { 2735 PWM3_A_MARK, 2736 }; 2737 2738 static const unsigned int pwm3_b_pins[] = { 2739 /* PWM */ 2740 RCAR_GP_PIN(1, 5), 2741 }; 2742 2743 static const unsigned int pwm3_b_mux[] = { 2744 PWM3_B_MARK, 2745 }; 2746 2747 static const unsigned int pwm3_c_pins[] = { 2748 /* PWM */ 2749 RCAR_GP_PIN(6, 6), 2750 }; 2751 2752 static const unsigned int pwm3_c_mux[] = { 2753 PWM3_C_MARK, 2754 }; 2755 2756 /* - PWM4 --------------------------------------------------------------------*/ 2757 static const unsigned int pwm4_a_pins[] = { 2758 /* PWM */ 2759 RCAR_GP_PIN(1, 3), 2760 }; 2761 2762 static const unsigned int pwm4_a_mux[] = { 2763 PWM4_A_MARK, 2764 }; 2765 2766 static const unsigned int pwm4_b_pins[] = { 2767 /* PWM */ 2768 RCAR_GP_PIN(6, 7), 2769 }; 2770 2771 static const unsigned int pwm4_b_mux[] = { 2772 PWM4_B_MARK, 2773 }; 2774 2775 /* - PWM5 --------------------------------------------------------------------*/ 2776 static const unsigned int pwm5_a_pins[] = { 2777 /* PWM */ 2778 RCAR_GP_PIN(2, 24), 2779 }; 2780 2781 static const unsigned int pwm5_a_mux[] = { 2782 PWM5_A_MARK, 2783 }; 2784 2785 static const unsigned int pwm5_b_pins[] = { 2786 /* PWM */ 2787 RCAR_GP_PIN(6, 10), 2788 }; 2789 2790 static const unsigned int pwm5_b_mux[] = { 2791 PWM5_B_MARK, 2792 }; 2793 2794 /* - PWM6 --------------------------------------------------------------------*/ 2795 static const unsigned int pwm6_a_pins[] = { 2796 /* PWM */ 2797 RCAR_GP_PIN(2, 25), 2798 }; 2799 2800 static const unsigned int pwm6_a_mux[] = { 2801 PWM6_A_MARK, 2802 }; 2803 2804 static const unsigned int pwm6_b_pins[] = { 2805 /* PWM */ 2806 RCAR_GP_PIN(6, 11), 2807 }; 2808 2809 static const unsigned int pwm6_b_mux[] = { 2810 PWM6_B_MARK, 2811 }; 2812 2813 /* - QSPI0 ------------------------------------------------------------------ */ 2814 static const unsigned int qspi0_ctrl_pins[] = { 2815 /* QSPI0_SPCLK, QSPI0_SSL */ 2816 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 5), 2817 }; 2818 static const unsigned int qspi0_ctrl_mux[] = { 2819 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, 2820 }; 2821 static const unsigned int qspi0_data2_pins[] = { 2822 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ 2823 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), 2824 }; 2825 static const unsigned int qspi0_data2_mux[] = { 2826 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, 2827 }; 2828 static const unsigned int qspi0_data4_pins[] = { 2829 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ 2830 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), 2831 /* QSPI0_IO2, QSPI0_IO3 */ 2832 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), 2833 }; 2834 static const unsigned int qspi0_data4_mux[] = { 2835 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, 2836 QSPI0_IO2_MARK, QSPI0_IO3_MARK, 2837 }; 2838 /* - QSPI1 ------------------------------------------------------------------ */ 2839 static const unsigned int qspi1_ctrl_pins[] = { 2840 /* QSPI1_SPCLK, QSPI1_SSL */ 2841 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 11), 2842 }; 2843 static const unsigned int qspi1_ctrl_mux[] = { 2844 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, 2845 }; 2846 static const unsigned int qspi1_data2_pins[] = { 2847 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ 2848 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 2849 }; 2850 static const unsigned int qspi1_data2_mux[] = { 2851 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, 2852 }; 2853 static const unsigned int qspi1_data4_pins[] = { 2854 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ 2855 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 2856 /* QSPI1_IO2, QSPI1_IO3 */ 2857 RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), 2858 }; 2859 static const unsigned int qspi1_data4_mux[] = { 2860 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, 2861 QSPI1_IO2_MARK, QSPI1_IO3_MARK, 2862 }; 2863 2864 /* - SCIF0 ------------------------------------------------------------------ */ 2865 static const unsigned int scif0_data_a_pins[] = { 2866 /* RX, TX */ 2867 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 2868 }; 2869 2870 static const unsigned int scif0_data_a_mux[] = { 2871 RX0_A_MARK, TX0_A_MARK, 2872 }; 2873 2874 static const unsigned int scif0_clk_a_pins[] = { 2875 /* SCK */ 2876 RCAR_GP_PIN(5, 0), 2877 }; 2878 2879 static const unsigned int scif0_clk_a_mux[] = { 2880 SCK0_A_MARK, 2881 }; 2882 2883 static const unsigned int scif0_ctrl_a_pins[] = { 2884 /* RTS, CTS */ 2885 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), 2886 }; 2887 2888 static const unsigned int scif0_ctrl_a_mux[] = { 2889 RTS0_N_A_MARK, CTS0_N_A_MARK, 2890 }; 2891 2892 static const unsigned int scif0_data_b_pins[] = { 2893 /* RX, TX */ 2894 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19), 2895 }; 2896 2897 static const unsigned int scif0_data_b_mux[] = { 2898 RX0_B_MARK, TX0_B_MARK, 2899 }; 2900 2901 static const unsigned int scif0_clk_b_pins[] = { 2902 /* SCK */ 2903 RCAR_GP_PIN(5, 18), 2904 }; 2905 2906 static const unsigned int scif0_clk_b_mux[] = { 2907 SCK0_B_MARK, 2908 }; 2909 2910 /* - SCIF1 ------------------------------------------------------------------ */ 2911 static const unsigned int scif1_data_pins[] = { 2912 /* RX, TX */ 2913 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 2914 }; 2915 2916 static const unsigned int scif1_data_mux[] = { 2917 RX1_MARK, TX1_MARK, 2918 }; 2919 2920 static const unsigned int scif1_clk_pins[] = { 2921 /* SCK */ 2922 RCAR_GP_PIN(5, 16), 2923 }; 2924 2925 static const unsigned int scif1_clk_mux[] = { 2926 SCK1_MARK, 2927 }; 2928 2929 static const unsigned int scif1_ctrl_pins[] = { 2930 /* RTS, CTS */ 2931 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 7), 2932 }; 2933 2934 static const unsigned int scif1_ctrl_mux[] = { 2935 RTS1_N_MARK, CTS1_N_MARK, 2936 }; 2937 2938 /* - SCIF2 ------------------------------------------------------------------ */ 2939 static const unsigned int scif2_data_a_pins[] = { 2940 /* RX, TX */ 2941 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8), 2942 }; 2943 2944 static const unsigned int scif2_data_a_mux[] = { 2945 RX2_A_MARK, TX2_A_MARK, 2946 }; 2947 2948 static const unsigned int scif2_clk_a_pins[] = { 2949 /* SCK */ 2950 RCAR_GP_PIN(5, 7), 2951 }; 2952 2953 static const unsigned int scif2_clk_a_mux[] = { 2954 SCK2_A_MARK, 2955 }; 2956 2957 static const unsigned int scif2_data_b_pins[] = { 2958 /* RX, TX */ 2959 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11), 2960 }; 2961 2962 static const unsigned int scif2_data_b_mux[] = { 2963 RX2_B_MARK, TX2_B_MARK, 2964 }; 2965 2966 /* - SCIF3 ------------------------------------------------------------------ */ 2967 static const unsigned int scif3_data_a_pins[] = { 2968 /* RX, TX */ 2969 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), 2970 }; 2971 2972 static const unsigned int scif3_data_a_mux[] = { 2973 RX3_A_MARK, TX3_A_MARK, 2974 }; 2975 2976 static const unsigned int scif3_clk_a_pins[] = { 2977 /* SCK */ 2978 RCAR_GP_PIN(0, 1), 2979 }; 2980 2981 static const unsigned int scif3_clk_a_mux[] = { 2982 SCK3_A_MARK, 2983 }; 2984 2985 static const unsigned int scif3_ctrl_a_pins[] = { 2986 /* RTS, CTS */ 2987 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7), 2988 }; 2989 2990 static const unsigned int scif3_ctrl_a_mux[] = { 2991 RTS3_N_A_MARK, CTS3_N_A_MARK, 2992 }; 2993 2994 static const unsigned int scif3_data_b_pins[] = { 2995 /* RX, TX */ 2996 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 2997 }; 2998 2999 static const unsigned int scif3_data_b_mux[] = { 3000 RX3_B_MARK, TX3_B_MARK, 3001 }; 3002 3003 static const unsigned int scif3_data_c_pins[] = { 3004 /* RX, TX */ 3005 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), 3006 }; 3007 3008 static const unsigned int scif3_data_c_mux[] = { 3009 RX3_C_MARK, TX3_C_MARK, 3010 }; 3011 3012 static const unsigned int scif3_clk_c_pins[] = { 3013 /* SCK */ 3014 RCAR_GP_PIN(2, 24), 3015 }; 3016 3017 static const unsigned int scif3_clk_c_mux[] = { 3018 SCK3_C_MARK, 3019 }; 3020 3021 /* - SCIF4 ------------------------------------------------------------------ */ 3022 static const unsigned int scif4_data_a_pins[] = { 3023 /* RX, TX */ 3024 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3025 }; 3026 3027 static const unsigned int scif4_data_a_mux[] = { 3028 RX4_A_MARK, TX4_A_MARK, 3029 }; 3030 3031 static const unsigned int scif4_clk_a_pins[] = { 3032 /* SCK */ 3033 RCAR_GP_PIN(1, 5), 3034 }; 3035 3036 static const unsigned int scif4_clk_a_mux[] = { 3037 SCK4_A_MARK, 3038 }; 3039 3040 static const unsigned int scif4_ctrl_a_pins[] = { 3041 /* RTS, CTS */ 3042 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), 3043 }; 3044 3045 static const unsigned int scif4_ctrl_a_mux[] = { 3046 RTS4_N_A_MARK, CTS4_N_A_MARK, 3047 }; 3048 3049 static const unsigned int scif4_data_b_pins[] = { 3050 /* RX, TX */ 3051 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12), 3052 }; 3053 3054 static const unsigned int scif4_data_b_mux[] = { 3055 RX4_B_MARK, TX4_B_MARK, 3056 }; 3057 3058 static const unsigned int scif4_clk_b_pins[] = { 3059 /* SCK */ 3060 RCAR_GP_PIN(0, 8), 3061 }; 3062 3063 static const unsigned int scif4_clk_b_mux[] = { 3064 SCK4_B_MARK, 3065 }; 3066 3067 static const unsigned int scif4_data_c_pins[] = { 3068 /* RX, TX */ 3069 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 3070 }; 3071 3072 static const unsigned int scif4_data_c_mux[] = { 3073 RX4_C_MARK, TX4_C_MARK, 3074 }; 3075 3076 static const unsigned int scif4_ctrl_c_pins[] = { 3077 /* RTS, CTS */ 3078 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0), 3079 }; 3080 3081 static const unsigned int scif4_ctrl_c_mux[] = { 3082 RTS4_N_C_MARK, CTS4_N_C_MARK, 3083 }; 3084 3085 /* - SCIF5 ------------------------------------------------------------------ */ 3086 static const unsigned int scif5_data_a_pins[] = { 3087 /* RX, TX */ 3088 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 9), 3089 }; 3090 3091 static const unsigned int scif5_data_a_mux[] = { 3092 RX5_A_MARK, TX5_A_MARK, 3093 }; 3094 3095 static const unsigned int scif5_clk_a_pins[] = { 3096 /* SCK */ 3097 RCAR_GP_PIN(1, 13), 3098 }; 3099 3100 static const unsigned int scif5_clk_a_mux[] = { 3101 SCK5_A_MARK, 3102 }; 3103 3104 static const unsigned int scif5_data_b_pins[] = { 3105 /* RX, TX */ 3106 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24), 3107 }; 3108 3109 static const unsigned int scif5_data_b_mux[] = { 3110 RX5_B_MARK, TX5_B_MARK, 3111 }; 3112 3113 static const unsigned int scif5_data_c_pins[] = { 3114 /* RX, TX */ 3115 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 3116 }; 3117 3118 static const unsigned int scif5_data_c_mux[] = { 3119 RX5_C_MARK, TX5_C_MARK, 3120 }; 3121 3122 /* - SCIF Clock ------------------------------------------------------------- */ 3123 static const unsigned int scif_clk_a_pins[] = { 3124 /* SCIF_CLK */ 3125 RCAR_GP_PIN(5, 3), 3126 }; 3127 3128 static const unsigned int scif_clk_a_mux[] = { 3129 SCIF_CLK_A_MARK, 3130 }; 3131 3132 static const unsigned int scif_clk_b_pins[] = { 3133 /* SCIF_CLK */ 3134 RCAR_GP_PIN(5, 7), 3135 }; 3136 3137 static const unsigned int scif_clk_b_mux[] = { 3138 SCIF_CLK_B_MARK, 3139 }; 3140 3141 /* - SDHI0 ------------------------------------------------------------------ */ 3142 static const unsigned int sdhi0_data1_pins[] = { 3143 /* D0 */ 3144 RCAR_GP_PIN(3, 2), 3145 }; 3146 3147 static const unsigned int sdhi0_data1_mux[] = { 3148 SD0_DAT0_MARK, 3149 }; 3150 3151 static const unsigned int sdhi0_data4_pins[] = { 3152 /* D[0:3] */ 3153 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), 3154 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), 3155 }; 3156 3157 static const unsigned int sdhi0_data4_mux[] = { 3158 SD0_DAT0_MARK, SD0_DAT1_MARK, 3159 SD0_DAT2_MARK, SD0_DAT3_MARK, 3160 }; 3161 3162 static const unsigned int sdhi0_ctrl_pins[] = { 3163 /* CLK, CMD */ 3164 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), 3165 }; 3166 3167 static const unsigned int sdhi0_ctrl_mux[] = { 3168 SD0_CLK_MARK, SD0_CMD_MARK, 3169 }; 3170 3171 static const unsigned int sdhi0_cd_pins[] = { 3172 /* CD */ 3173 RCAR_GP_PIN(3, 12), 3174 }; 3175 3176 static const unsigned int sdhi0_cd_mux[] = { 3177 SD0_CD_MARK, 3178 }; 3179 3180 static const unsigned int sdhi0_wp_pins[] = { 3181 /* WP */ 3182 RCAR_GP_PIN(3, 13), 3183 }; 3184 3185 static const unsigned int sdhi0_wp_mux[] = { 3186 SD0_WP_MARK, 3187 }; 3188 3189 /* - SDHI1 ------------------------------------------------------------------ */ 3190 static const unsigned int sdhi1_data1_pins[] = { 3191 /* D0 */ 3192 RCAR_GP_PIN(3, 8), 3193 }; 3194 3195 static const unsigned int sdhi1_data1_mux[] = { 3196 SD1_DAT0_MARK, 3197 }; 3198 3199 static const unsigned int sdhi1_data4_pins[] = { 3200 /* D[0:3] */ 3201 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 3202 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 3203 }; 3204 3205 static const unsigned int sdhi1_data4_mux[] = { 3206 SD1_DAT0_MARK, SD1_DAT1_MARK, 3207 SD1_DAT2_MARK, SD1_DAT3_MARK, 3208 }; 3209 3210 static const unsigned int sdhi1_ctrl_pins[] = { 3211 /* CLK, CMD */ 3212 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 3213 }; 3214 3215 static const unsigned int sdhi1_ctrl_mux[] = { 3216 SD1_CLK_MARK, SD1_CMD_MARK, 3217 }; 3218 3219 static const unsigned int sdhi1_cd_pins[] = { 3220 /* CD */ 3221 RCAR_GP_PIN(3, 14), 3222 }; 3223 3224 static const unsigned int sdhi1_cd_mux[] = { 3225 SD1_CD_MARK, 3226 }; 3227 3228 static const unsigned int sdhi1_wp_pins[] = { 3229 /* WP */ 3230 RCAR_GP_PIN(3, 15), 3231 }; 3232 3233 static const unsigned int sdhi1_wp_mux[] = { 3234 SD1_WP_MARK, 3235 }; 3236 3237 /* - SDHI3 ------------------------------------------------------------------ */ 3238 static const unsigned int sdhi3_data1_pins[] = { 3239 /* D0 */ 3240 RCAR_GP_PIN(4, 2), 3241 }; 3242 3243 static const unsigned int sdhi3_data1_mux[] = { 3244 SD3_DAT0_MARK, 3245 }; 3246 3247 static const unsigned int sdhi3_data4_pins[] = { 3248 /* D[0:3] */ 3249 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), 3250 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), 3251 }; 3252 3253 static const unsigned int sdhi3_data4_mux[] = { 3254 SD3_DAT0_MARK, SD3_DAT1_MARK, 3255 SD3_DAT2_MARK, SD3_DAT3_MARK, 3256 }; 3257 3258 static const unsigned int sdhi3_data8_pins[] = { 3259 /* D[0:7] */ 3260 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), 3261 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), 3262 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7), 3263 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), 3264 }; 3265 3266 static const unsigned int sdhi3_data8_mux[] = { 3267 SD3_DAT0_MARK, SD3_DAT1_MARK, 3268 SD3_DAT2_MARK, SD3_DAT3_MARK, 3269 SD3_DAT4_MARK, SD3_DAT5_MARK, 3270 SD3_DAT6_MARK, SD3_DAT7_MARK, 3271 }; 3272 3273 static const unsigned int sdhi3_ctrl_pins[] = { 3274 /* CLK, CMD */ 3275 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), 3276 }; 3277 3278 static const unsigned int sdhi3_ctrl_mux[] = { 3279 SD3_CLK_MARK, SD3_CMD_MARK, 3280 }; 3281 3282 static const unsigned int sdhi3_cd_pins[] = { 3283 /* CD */ 3284 RCAR_GP_PIN(3, 12), 3285 }; 3286 3287 static const unsigned int sdhi3_cd_mux[] = { 3288 SD3_CD_MARK, 3289 }; 3290 3291 static const unsigned int sdhi3_wp_pins[] = { 3292 /* WP */ 3293 RCAR_GP_PIN(3, 13), 3294 }; 3295 3296 static const unsigned int sdhi3_wp_mux[] = { 3297 SD3_WP_MARK, 3298 }; 3299 3300 static const unsigned int sdhi3_ds_pins[] = { 3301 /* DS */ 3302 RCAR_GP_PIN(4, 10), 3303 }; 3304 3305 static const unsigned int sdhi3_ds_mux[] = { 3306 SD3_DS_MARK, 3307 }; 3308 3309 /* - SSI -------------------------------------------------------------------- */ 3310 static const unsigned int ssi0_data_pins[] = { 3311 /* SDATA */ 3312 RCAR_GP_PIN(6, 2), 3313 }; 3314 3315 static const unsigned int ssi0_data_mux[] = { 3316 SSI_SDATA0_MARK, 3317 }; 3318 3319 static const unsigned int ssi01239_ctrl_pins[] = { 3320 /* SCK, WS */ 3321 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), 3322 }; 3323 3324 static const unsigned int ssi01239_ctrl_mux[] = { 3325 SSI_SCK01239_MARK, SSI_WS01239_MARK, 3326 }; 3327 3328 static const unsigned int ssi1_data_pins[] = { 3329 /* SDATA */ 3330 RCAR_GP_PIN(6, 3), 3331 }; 3332 3333 static const unsigned int ssi1_data_mux[] = { 3334 SSI_SDATA1_MARK, 3335 }; 3336 3337 static const unsigned int ssi1_ctrl_pins[] = { 3338 /* SCK, WS */ 3339 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), 3340 }; 3341 3342 static const unsigned int ssi1_ctrl_mux[] = { 3343 SSI_SCK1_MARK, SSI_WS1_MARK, 3344 }; 3345 3346 static const unsigned int ssi2_data_pins[] = { 3347 /* SDATA */ 3348 RCAR_GP_PIN(6, 4), 3349 }; 3350 3351 static const unsigned int ssi2_data_mux[] = { 3352 SSI_SDATA2_MARK, 3353 }; 3354 3355 static const unsigned int ssi2_ctrl_a_pins[] = { 3356 /* SCK, WS */ 3357 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 3358 }; 3359 3360 static const unsigned int ssi2_ctrl_a_mux[] = { 3361 SSI_SCK2_A_MARK, SSI_WS2_A_MARK, 3362 }; 3363 3364 static const unsigned int ssi2_ctrl_b_pins[] = { 3365 /* SCK, WS */ 3366 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), 3367 }; 3368 3369 static const unsigned int ssi2_ctrl_b_mux[] = { 3370 SSI_SCK2_B_MARK, SSI_WS2_B_MARK, 3371 }; 3372 3373 static const unsigned int ssi3_data_pins[] = { 3374 /* SDATA */ 3375 RCAR_GP_PIN(6, 7), 3376 }; 3377 3378 static const unsigned int ssi3_data_mux[] = { 3379 SSI_SDATA3_MARK, 3380 }; 3381 3382 static const unsigned int ssi349_ctrl_pins[] = { 3383 /* SCK, WS */ 3384 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6), 3385 }; 3386 3387 static const unsigned int ssi349_ctrl_mux[] = { 3388 SSI_SCK349_MARK, SSI_WS349_MARK, 3389 }; 3390 3391 static const unsigned int ssi4_data_pins[] = { 3392 /* SDATA */ 3393 RCAR_GP_PIN(6, 10), 3394 }; 3395 3396 static const unsigned int ssi4_data_mux[] = { 3397 SSI_SDATA4_MARK, 3398 }; 3399 3400 static const unsigned int ssi4_ctrl_pins[] = { 3401 /* SCK, WS */ 3402 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), 3403 }; 3404 3405 static const unsigned int ssi4_ctrl_mux[] = { 3406 SSI_SCK4_MARK, SSI_WS4_MARK, 3407 }; 3408 3409 static const unsigned int ssi5_data_pins[] = { 3410 /* SDATA */ 3411 RCAR_GP_PIN(6, 13), 3412 }; 3413 3414 static const unsigned int ssi5_data_mux[] = { 3415 SSI_SDATA5_MARK, 3416 }; 3417 3418 static const unsigned int ssi5_ctrl_pins[] = { 3419 /* SCK, WS */ 3420 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), 3421 }; 3422 3423 static const unsigned int ssi5_ctrl_mux[] = { 3424 SSI_SCK5_MARK, SSI_WS5_MARK, 3425 }; 3426 3427 static const unsigned int ssi6_data_pins[] = { 3428 /* SDATA */ 3429 RCAR_GP_PIN(6, 16), 3430 }; 3431 3432 static const unsigned int ssi6_data_mux[] = { 3433 SSI_SDATA6_MARK, 3434 }; 3435 3436 static const unsigned int ssi6_ctrl_pins[] = { 3437 /* SCK, WS */ 3438 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), 3439 }; 3440 3441 static const unsigned int ssi6_ctrl_mux[] = { 3442 SSI_SCK6_MARK, SSI_WS6_MARK, 3443 }; 3444 3445 static const unsigned int ssi7_data_pins[] = { 3446 /* SDATA */ 3447 RCAR_GP_PIN(5, 12), 3448 }; 3449 3450 static const unsigned int ssi7_data_mux[] = { 3451 SSI_SDATA7_MARK, 3452 }; 3453 3454 static const unsigned int ssi78_ctrl_pins[] = { 3455 /* SCK, WS */ 3456 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11), 3457 }; 3458 3459 static const unsigned int ssi78_ctrl_mux[] = { 3460 SSI_SCK78_MARK, SSI_WS78_MARK, 3461 }; 3462 3463 static const unsigned int ssi8_data_pins[] = { 3464 /* SDATA */ 3465 RCAR_GP_PIN(5, 13), 3466 }; 3467 3468 static const unsigned int ssi8_data_mux[] = { 3469 SSI_SDATA8_MARK, 3470 }; 3471 3472 static const unsigned int ssi9_data_pins[] = { 3473 /* SDATA */ 3474 RCAR_GP_PIN(5, 16), 3475 }; 3476 3477 static const unsigned int ssi9_data_mux[] = { 3478 SSI_SDATA9_MARK, 3479 }; 3480 3481 static const unsigned int ssi9_ctrl_a_pins[] = { 3482 /* SCK, WS */ 3483 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 10), 3484 }; 3485 3486 static const unsigned int ssi9_ctrl_a_mux[] = { 3487 SSI_SCK9_A_MARK, SSI_WS9_A_MARK, 3488 }; 3489 3490 static const unsigned int ssi9_ctrl_b_pins[] = { 3491 /* SCK, WS */ 3492 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 3493 }; 3494 3495 static const unsigned int ssi9_ctrl_b_mux[] = { 3496 SSI_SCK9_B_MARK, SSI_WS9_B_MARK, 3497 }; 3498 3499 /* - TMU -------------------------------------------------------------------- */ 3500 static const unsigned int tmu_tclk1_a_pins[] = { 3501 /* TCLK */ 3502 RCAR_GP_PIN(3, 12), 3503 }; 3504 3505 static const unsigned int tmu_tclk1_a_mux[] = { 3506 TCLK1_A_MARK, 3507 }; 3508 3509 static const unsigned int tmu_tclk1_b_pins[] = { 3510 /* TCLK */ 3511 RCAR_GP_PIN(5, 17), 3512 }; 3513 3514 static const unsigned int tmu_tclk1_b_mux[] = { 3515 TCLK1_B_MARK, 3516 }; 3517 3518 static const unsigned int tmu_tclk2_a_pins[] = { 3519 /* TCLK */ 3520 RCAR_GP_PIN(3, 13), 3521 }; 3522 3523 static const unsigned int tmu_tclk2_a_mux[] = { 3524 TCLK2_A_MARK, 3525 }; 3526 3527 static const unsigned int tmu_tclk2_b_pins[] = { 3528 /* TCLK */ 3529 RCAR_GP_PIN(5, 18), 3530 }; 3531 3532 static const unsigned int tmu_tclk2_b_mux[] = { 3533 TCLK2_B_MARK, 3534 }; 3535 3536 /* - USB0 ------------------------------------------------------------------- */ 3537 static const unsigned int usb0_a_pins[] = { 3538 /* PWEN, OVC */ 3539 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 9), 3540 }; 3541 3542 static const unsigned int usb0_a_mux[] = { 3543 USB0_PWEN_A_MARK, USB0_OVC_A_MARK, 3544 }; 3545 3546 static const unsigned int usb0_b_pins[] = { 3547 /* PWEN, OVC */ 3548 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), 3549 }; 3550 3551 static const unsigned int usb0_b_mux[] = { 3552 USB0_PWEN_B_MARK, USB0_OVC_B_MARK, 3553 }; 3554 3555 static const unsigned int usb0_id_pins[] = { 3556 /* ID */ 3557 RCAR_GP_PIN(5, 0) 3558 }; 3559 3560 static const unsigned int usb0_id_mux[] = { 3561 USB0_ID_MARK, 3562 }; 3563 3564 /* - USB30 ------------------------------------------------------------------ */ 3565 static const unsigned int usb30_pins[] = { 3566 /* PWEN, OVC */ 3567 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 9), 3568 }; 3569 3570 static const unsigned int usb30_mux[] = { 3571 USB30_PWEN_MARK, USB30_OVC_MARK, 3572 }; 3573 3574 static const unsigned int usb30_id_pins[] = { 3575 /* ID */ 3576 RCAR_GP_PIN(5, 0), 3577 }; 3578 3579 static const unsigned int usb30_id_mux[] = { 3580 USB3HS0_ID_MARK, 3581 }; 3582 3583 /* - VIN4 ------------------------------------------------------------------- */ 3584 static const unsigned int vin4_data18_a_pins[] = { 3585 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 3586 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), 3587 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), 3588 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3589 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), 3590 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), 3591 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), 3592 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), 3593 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1), 3594 }; 3595 3596 static const unsigned int vin4_data18_a_mux[] = { 3597 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, 3598 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, 3599 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, 3600 VI4_DATA10_MARK, VI4_DATA11_MARK, 3601 VI4_DATA12_MARK, VI4_DATA13_MARK, 3602 VI4_DATA14_MARK, VI4_DATA15_MARK, 3603 VI4_DATA18_MARK, VI4_DATA19_MARK, 3604 VI4_DATA20_MARK, VI4_DATA21_MARK, 3605 VI4_DATA22_MARK, VI4_DATA23_MARK, 3606 }; 3607 3608 static const union vin_data vin4_data_a_pins = { 3609 .data24 = { 3610 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 3611 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 3612 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), 3613 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), 3614 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 3615 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3616 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), 3617 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), 3618 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), 3619 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), 3620 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), 3621 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1), 3622 }, 3623 }; 3624 3625 static const union vin_data vin4_data_a_mux = { 3626 .data24 = { 3627 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, 3628 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, 3629 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, 3630 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, 3631 VI4_DATA8_MARK, VI4_DATA9_MARK, 3632 VI4_DATA10_MARK, VI4_DATA11_MARK, 3633 VI4_DATA12_MARK, VI4_DATA13_MARK, 3634 VI4_DATA14_MARK, VI4_DATA15_MARK, 3635 VI4_DATA16_MARK, VI4_DATA17_MARK, 3636 VI4_DATA18_MARK, VI4_DATA19_MARK, 3637 VI4_DATA20_MARK, VI4_DATA21_MARK, 3638 VI4_DATA22_MARK, VI4_DATA23_MARK, 3639 }, 3640 }; 3641 3642 static const unsigned int vin4_data18_b_pins[] = { 3643 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), 3644 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), 3645 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17), 3646 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3647 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), 3648 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), 3649 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), 3650 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), 3651 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1), 3652 }; 3653 3654 static const unsigned int vin4_data18_b_mux[] = { 3655 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, 3656 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, 3657 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, 3658 VI4_DATA10_MARK, VI4_DATA11_MARK, 3659 VI4_DATA12_MARK, VI4_DATA13_MARK, 3660 VI4_DATA14_MARK, VI4_DATA15_MARK, 3661 VI4_DATA18_MARK, VI4_DATA19_MARK, 3662 VI4_DATA20_MARK, VI4_DATA21_MARK, 3663 VI4_DATA22_MARK, VI4_DATA23_MARK, 3664 }; 3665 3666 static const union vin_data vin4_data_b_pins = { 3667 .data24 = { 3668 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 3669 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), 3670 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), 3671 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17), 3672 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 3673 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3674 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), 3675 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), 3676 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), 3677 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), 3678 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), 3679 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1), 3680 }, 3681 }; 3682 3683 static const union vin_data vin4_data_b_mux = { 3684 .data24 = { 3685 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, 3686 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, 3687 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, 3688 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, 3689 VI4_DATA8_MARK, VI4_DATA9_MARK, 3690 VI4_DATA10_MARK, VI4_DATA11_MARK, 3691 VI4_DATA12_MARK, VI4_DATA13_MARK, 3692 VI4_DATA14_MARK, VI4_DATA15_MARK, 3693 VI4_DATA16_MARK, VI4_DATA17_MARK, 3694 VI4_DATA18_MARK, VI4_DATA19_MARK, 3695 VI4_DATA20_MARK, VI4_DATA21_MARK, 3696 VI4_DATA22_MARK, VI4_DATA23_MARK, 3697 }, 3698 }; 3699 3700 static const unsigned int vin4_sync_pins[] = { 3701 /* HSYNC, VSYNC */ 3702 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24), 3703 }; 3704 3705 static const unsigned int vin4_sync_mux[] = { 3706 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK, 3707 }; 3708 3709 static const unsigned int vin4_field_pins[] = { 3710 RCAR_GP_PIN(2, 23), 3711 }; 3712 3713 static const unsigned int vin4_field_mux[] = { 3714 VI4_FIELD_MARK, 3715 }; 3716 3717 static const unsigned int vin4_clkenb_pins[] = { 3718 RCAR_GP_PIN(1, 2), 3719 }; 3720 3721 static const unsigned int vin4_clkenb_mux[] = { 3722 VI4_CLKENB_MARK, 3723 }; 3724 3725 static const unsigned int vin4_clk_pins[] = { 3726 RCAR_GP_PIN(2, 22), 3727 }; 3728 3729 static const unsigned int vin4_clk_mux[] = { 3730 VI4_CLK_MARK, 3731 }; 3732 3733 /* - VIN5 ------------------------------------------------------------------- */ 3734 static const union vin_data16 vin5_data_a_pins = { 3735 .data16 = { 3736 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2), 3737 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 12), 3738 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), 3739 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), 3740 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 3741 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 11), 3742 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 10), 3743 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 3744 }, 3745 }; 3746 3747 static const union vin_data16 vin5_data_a_mux = { 3748 .data16 = { 3749 VI5_DATA0_A_MARK, VI5_DATA1_A_MARK, 3750 VI5_DATA2_A_MARK, VI5_DATA3_A_MARK, 3751 VI5_DATA4_A_MARK, VI5_DATA5_A_MARK, 3752 VI5_DATA6_A_MARK, VI5_DATA7_A_MARK, 3753 VI5_DATA8_A_MARK, VI5_DATA9_A_MARK, 3754 VI5_DATA10_A_MARK, VI5_DATA11_A_MARK, 3755 VI5_DATA12_A_MARK, VI5_DATA13_A_MARK, 3756 VI5_DATA14_A_MARK, VI5_DATA15_A_MARK, 3757 }, 3758 }; 3759 3760 static const unsigned int vin5_data8_b_pins[] = { 3761 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(0, 4), 3762 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 12), 3763 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14), 3764 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17), 3765 }; 3766 3767 static const unsigned int vin5_data8_b_mux[] = { 3768 VI5_DATA0_B_MARK, VI5_DATA1_B_MARK, 3769 VI5_DATA2_B_MARK, VI5_DATA3_B_MARK, 3770 VI5_DATA4_B_MARK, VI5_DATA5_B_MARK, 3771 VI5_DATA6_B_MARK, VI5_DATA7_B_MARK, 3772 }; 3773 3774 static const unsigned int vin5_sync_a_pins[] = { 3775 /* HSYNC_N, VSYNC_N */ 3776 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9), 3777 }; 3778 3779 static const unsigned int vin5_sync_a_mux[] = { 3780 VI5_HSYNC_N_A_MARK, VI5_VSYNC_N_A_MARK, 3781 }; 3782 3783 static const unsigned int vin5_field_a_pins[] = { 3784 RCAR_GP_PIN(1, 10), 3785 }; 3786 3787 static const unsigned int vin5_field_a_mux[] = { 3788 VI5_FIELD_A_MARK, 3789 }; 3790 3791 static const unsigned int vin5_clkenb_a_pins[] = { 3792 RCAR_GP_PIN(0, 1), 3793 }; 3794 3795 static const unsigned int vin5_clkenb_a_mux[] = { 3796 VI5_CLKENB_A_MARK, 3797 }; 3798 3799 static const unsigned int vin5_clk_a_pins[] = { 3800 RCAR_GP_PIN(1, 0), 3801 }; 3802 3803 static const unsigned int vin5_clk_a_mux[] = { 3804 VI5_CLK_A_MARK, 3805 }; 3806 3807 static const unsigned int vin5_clk_b_pins[] = { 3808 RCAR_GP_PIN(2, 22), 3809 }; 3810 3811 static const unsigned int vin5_clk_b_mux[] = { 3812 VI5_CLK_B_MARK, 3813 }; 3814 3815 static const struct { 3816 struct sh_pfc_pin_group common[253]; 3817 #ifdef CONFIG_PINCTRL_PFC_R8A77990 3818 struct sh_pfc_pin_group automotive[21]; 3819 #endif 3820 } pinmux_groups = { 3821 .common = { 3822 SH_PFC_PIN_GROUP(audio_clk_a), 3823 SH_PFC_PIN_GROUP(audio_clk_b_a), 3824 SH_PFC_PIN_GROUP(audio_clk_b_b), 3825 SH_PFC_PIN_GROUP(audio_clk_b_c), 3826 SH_PFC_PIN_GROUP(audio_clk_c_a), 3827 SH_PFC_PIN_GROUP(audio_clk_c_b), 3828 SH_PFC_PIN_GROUP(audio_clk_c_c), 3829 SH_PFC_PIN_GROUP(audio_clkout_a), 3830 SH_PFC_PIN_GROUP(audio_clkout_b), 3831 SH_PFC_PIN_GROUP(audio_clkout1_a), 3832 SH_PFC_PIN_GROUP(audio_clkout1_b), 3833 SH_PFC_PIN_GROUP(audio_clkout1_c), 3834 SH_PFC_PIN_GROUP(audio_clkout2_a), 3835 SH_PFC_PIN_GROUP(audio_clkout2_b), 3836 SH_PFC_PIN_GROUP(audio_clkout2_c), 3837 SH_PFC_PIN_GROUP(audio_clkout3_a), 3838 SH_PFC_PIN_GROUP(audio_clkout3_b), 3839 SH_PFC_PIN_GROUP(audio_clkout3_c), 3840 SH_PFC_PIN_GROUP(avb_link), 3841 SH_PFC_PIN_GROUP(avb_magic), 3842 SH_PFC_PIN_GROUP(avb_phy_int), 3843 SH_PFC_PIN_GROUP(avb_mii), 3844 SH_PFC_PIN_GROUP(avb_avtp_pps), 3845 SH_PFC_PIN_GROUP(avb_avtp_match), 3846 SH_PFC_PIN_GROUP(avb_avtp_capture), 3847 SH_PFC_PIN_GROUP(can0_data), 3848 SH_PFC_PIN_GROUP(can1_data), 3849 SH_PFC_PIN_GROUP(can_clk), 3850 SH_PFC_PIN_GROUP(canfd0_data), 3851 SH_PFC_PIN_GROUP(canfd1_data), 3852 SH_PFC_PIN_GROUP(du_rgb666), 3853 SH_PFC_PIN_GROUP(du_rgb888), 3854 SH_PFC_PIN_GROUP(du_clk_in_0), 3855 SH_PFC_PIN_GROUP(du_clk_in_1), 3856 SH_PFC_PIN_GROUP(du_clk_out_0), 3857 SH_PFC_PIN_GROUP(du_sync), 3858 SH_PFC_PIN_GROUP(du_disp_cde), 3859 SH_PFC_PIN_GROUP(du_cde), 3860 SH_PFC_PIN_GROUP(du_disp), 3861 SH_PFC_PIN_GROUP(hscif0_data_a), 3862 SH_PFC_PIN_GROUP(hscif0_clk_a), 3863 SH_PFC_PIN_GROUP(hscif0_ctrl_a), 3864 SH_PFC_PIN_GROUP(hscif0_data_b), 3865 SH_PFC_PIN_GROUP(hscif0_clk_b), 3866 SH_PFC_PIN_GROUP(hscif1_data_a), 3867 SH_PFC_PIN_GROUP(hscif1_clk_a), 3868 SH_PFC_PIN_GROUP(hscif1_data_b), 3869 SH_PFC_PIN_GROUP(hscif1_clk_b), 3870 SH_PFC_PIN_GROUP(hscif1_ctrl_b), 3871 SH_PFC_PIN_GROUP(hscif2_data_a), 3872 SH_PFC_PIN_GROUP(hscif2_clk_a), 3873 SH_PFC_PIN_GROUP(hscif2_ctrl_a), 3874 SH_PFC_PIN_GROUP(hscif2_data_b), 3875 SH_PFC_PIN_GROUP(hscif3_data_a), 3876 SH_PFC_PIN_GROUP(hscif3_data_b), 3877 SH_PFC_PIN_GROUP(hscif3_clk_b), 3878 SH_PFC_PIN_GROUP(hscif3_data_c), 3879 SH_PFC_PIN_GROUP(hscif3_clk_c), 3880 SH_PFC_PIN_GROUP(hscif3_ctrl_c), 3881 SH_PFC_PIN_GROUP(hscif3_data_d), 3882 SH_PFC_PIN_GROUP(hscif3_data_e), 3883 SH_PFC_PIN_GROUP(hscif3_ctrl_e), 3884 SH_PFC_PIN_GROUP(hscif4_data_a), 3885 SH_PFC_PIN_GROUP(hscif4_clk_a), 3886 SH_PFC_PIN_GROUP(hscif4_ctrl_a), 3887 SH_PFC_PIN_GROUP(hscif4_data_b), 3888 SH_PFC_PIN_GROUP(hscif4_clk_b), 3889 SH_PFC_PIN_GROUP(hscif4_data_c), 3890 SH_PFC_PIN_GROUP(hscif4_data_d), 3891 SH_PFC_PIN_GROUP(hscif4_data_e), 3892 SH_PFC_PIN_GROUP(i2c1_a), 3893 SH_PFC_PIN_GROUP(i2c1_b), 3894 SH_PFC_PIN_GROUP(i2c1_c), 3895 SH_PFC_PIN_GROUP(i2c1_d), 3896 SH_PFC_PIN_GROUP(i2c2_a), 3897 SH_PFC_PIN_GROUP(i2c2_b), 3898 SH_PFC_PIN_GROUP(i2c2_c), 3899 SH_PFC_PIN_GROUP(i2c2_d), 3900 SH_PFC_PIN_GROUP(i2c2_e), 3901 SH_PFC_PIN_GROUP(i2c4), 3902 SH_PFC_PIN_GROUP(i2c5), 3903 SH_PFC_PIN_GROUP(i2c6_a), 3904 SH_PFC_PIN_GROUP(i2c6_b), 3905 SH_PFC_PIN_GROUP(i2c7_a), 3906 SH_PFC_PIN_GROUP(i2c7_b), 3907 SH_PFC_PIN_GROUP(intc_ex_irq0), 3908 SH_PFC_PIN_GROUP(intc_ex_irq1), 3909 SH_PFC_PIN_GROUP(intc_ex_irq2), 3910 SH_PFC_PIN_GROUP(intc_ex_irq3), 3911 SH_PFC_PIN_GROUP(intc_ex_irq4), 3912 SH_PFC_PIN_GROUP(intc_ex_irq5), 3913 SH_PFC_PIN_GROUP(msiof0_clk), 3914 SH_PFC_PIN_GROUP(msiof0_sync), 3915 SH_PFC_PIN_GROUP(msiof0_ss1), 3916 SH_PFC_PIN_GROUP(msiof0_ss2), 3917 SH_PFC_PIN_GROUP(msiof0_txd), 3918 SH_PFC_PIN_GROUP(msiof0_rxd), 3919 SH_PFC_PIN_GROUP(msiof1_clk), 3920 SH_PFC_PIN_GROUP(msiof1_sync), 3921 SH_PFC_PIN_GROUP(msiof1_ss1), 3922 SH_PFC_PIN_GROUP(msiof1_ss2), 3923 SH_PFC_PIN_GROUP(msiof1_txd), 3924 SH_PFC_PIN_GROUP(msiof1_rxd), 3925 SH_PFC_PIN_GROUP(msiof2_clk_a), 3926 SH_PFC_PIN_GROUP(msiof2_sync_a), 3927 SH_PFC_PIN_GROUP(msiof2_ss1_a), 3928 SH_PFC_PIN_GROUP(msiof2_ss2_a), 3929 SH_PFC_PIN_GROUP(msiof2_txd_a), 3930 SH_PFC_PIN_GROUP(msiof2_rxd_a), 3931 SH_PFC_PIN_GROUP(msiof2_clk_b), 3932 SH_PFC_PIN_GROUP(msiof2_sync_b), 3933 SH_PFC_PIN_GROUP(msiof2_ss1_b), 3934 SH_PFC_PIN_GROUP(msiof2_ss2_b), 3935 SH_PFC_PIN_GROUP(msiof2_txd_b), 3936 SH_PFC_PIN_GROUP(msiof2_rxd_b), 3937 SH_PFC_PIN_GROUP(msiof3_clk_a), 3938 SH_PFC_PIN_GROUP(msiof3_sync_a), 3939 SH_PFC_PIN_GROUP(msiof3_ss1_a), 3940 SH_PFC_PIN_GROUP(msiof3_ss2_a), 3941 SH_PFC_PIN_GROUP(msiof3_txd_a), 3942 SH_PFC_PIN_GROUP(msiof3_rxd_a), 3943 SH_PFC_PIN_GROUP(msiof3_clk_b), 3944 SH_PFC_PIN_GROUP(msiof3_sync_b), 3945 SH_PFC_PIN_GROUP(msiof3_ss1_b), 3946 SH_PFC_PIN_GROUP(msiof3_txd_b), 3947 SH_PFC_PIN_GROUP(msiof3_rxd_b), 3948 SH_PFC_PIN_GROUP(pwm0_a), 3949 SH_PFC_PIN_GROUP(pwm0_b), 3950 SH_PFC_PIN_GROUP(pwm1_a), 3951 SH_PFC_PIN_GROUP(pwm1_b), 3952 SH_PFC_PIN_GROUP(pwm2_a), 3953 SH_PFC_PIN_GROUP(pwm2_b), 3954 SH_PFC_PIN_GROUP(pwm2_c), 3955 SH_PFC_PIN_GROUP(pwm3_a), 3956 SH_PFC_PIN_GROUP(pwm3_b), 3957 SH_PFC_PIN_GROUP(pwm3_c), 3958 SH_PFC_PIN_GROUP(pwm4_a), 3959 SH_PFC_PIN_GROUP(pwm4_b), 3960 SH_PFC_PIN_GROUP(pwm5_a), 3961 SH_PFC_PIN_GROUP(pwm5_b), 3962 SH_PFC_PIN_GROUP(pwm6_a), 3963 SH_PFC_PIN_GROUP(pwm6_b), 3964 SH_PFC_PIN_GROUP(qspi0_ctrl), 3965 SH_PFC_PIN_GROUP(qspi0_data2), 3966 SH_PFC_PIN_GROUP(qspi0_data4), 3967 SH_PFC_PIN_GROUP(qspi1_ctrl), 3968 SH_PFC_PIN_GROUP(qspi1_data2), 3969 SH_PFC_PIN_GROUP(qspi1_data4), 3970 SH_PFC_PIN_GROUP(scif0_data_a), 3971 SH_PFC_PIN_GROUP(scif0_clk_a), 3972 SH_PFC_PIN_GROUP(scif0_ctrl_a), 3973 SH_PFC_PIN_GROUP(scif0_data_b), 3974 SH_PFC_PIN_GROUP(scif0_clk_b), 3975 SH_PFC_PIN_GROUP(scif1_data), 3976 SH_PFC_PIN_GROUP(scif1_clk), 3977 SH_PFC_PIN_GROUP(scif1_ctrl), 3978 SH_PFC_PIN_GROUP(scif2_data_a), 3979 SH_PFC_PIN_GROUP(scif2_clk_a), 3980 SH_PFC_PIN_GROUP(scif2_data_b), 3981 SH_PFC_PIN_GROUP(scif3_data_a), 3982 SH_PFC_PIN_GROUP(scif3_clk_a), 3983 SH_PFC_PIN_GROUP(scif3_ctrl_a), 3984 SH_PFC_PIN_GROUP(scif3_data_b), 3985 SH_PFC_PIN_GROUP(scif3_data_c), 3986 SH_PFC_PIN_GROUP(scif3_clk_c), 3987 SH_PFC_PIN_GROUP(scif4_data_a), 3988 SH_PFC_PIN_GROUP(scif4_clk_a), 3989 SH_PFC_PIN_GROUP(scif4_ctrl_a), 3990 SH_PFC_PIN_GROUP(scif4_data_b), 3991 SH_PFC_PIN_GROUP(scif4_clk_b), 3992 SH_PFC_PIN_GROUP(scif4_data_c), 3993 SH_PFC_PIN_GROUP(scif4_ctrl_c), 3994 SH_PFC_PIN_GROUP(scif5_data_a), 3995 SH_PFC_PIN_GROUP(scif5_clk_a), 3996 SH_PFC_PIN_GROUP(scif5_data_b), 3997 SH_PFC_PIN_GROUP(scif5_data_c), 3998 SH_PFC_PIN_GROUP(scif_clk_a), 3999 SH_PFC_PIN_GROUP(scif_clk_b), 4000 SH_PFC_PIN_GROUP(sdhi0_data1), 4001 SH_PFC_PIN_GROUP(sdhi0_data4), 4002 SH_PFC_PIN_GROUP(sdhi0_ctrl), 4003 SH_PFC_PIN_GROUP(sdhi0_cd), 4004 SH_PFC_PIN_GROUP(sdhi0_wp), 4005 SH_PFC_PIN_GROUP(sdhi1_data1), 4006 SH_PFC_PIN_GROUP(sdhi1_data4), 4007 SH_PFC_PIN_GROUP(sdhi1_ctrl), 4008 SH_PFC_PIN_GROUP(sdhi1_cd), 4009 SH_PFC_PIN_GROUP(sdhi1_wp), 4010 SH_PFC_PIN_GROUP(sdhi3_data1), 4011 SH_PFC_PIN_GROUP(sdhi3_data4), 4012 SH_PFC_PIN_GROUP(sdhi3_data8), 4013 SH_PFC_PIN_GROUP(sdhi3_ctrl), 4014 SH_PFC_PIN_GROUP(sdhi3_cd), 4015 SH_PFC_PIN_GROUP(sdhi3_wp), 4016 SH_PFC_PIN_GROUP(sdhi3_ds), 4017 SH_PFC_PIN_GROUP(ssi0_data), 4018 SH_PFC_PIN_GROUP(ssi01239_ctrl), 4019 SH_PFC_PIN_GROUP(ssi1_data), 4020 SH_PFC_PIN_GROUP(ssi1_ctrl), 4021 SH_PFC_PIN_GROUP(ssi2_data), 4022 SH_PFC_PIN_GROUP(ssi2_ctrl_a), 4023 SH_PFC_PIN_GROUP(ssi2_ctrl_b), 4024 SH_PFC_PIN_GROUP(ssi3_data), 4025 SH_PFC_PIN_GROUP(ssi349_ctrl), 4026 SH_PFC_PIN_GROUP(ssi4_data), 4027 SH_PFC_PIN_GROUP(ssi4_ctrl), 4028 SH_PFC_PIN_GROUP(ssi5_data), 4029 SH_PFC_PIN_GROUP(ssi5_ctrl), 4030 SH_PFC_PIN_GROUP(ssi6_data), 4031 SH_PFC_PIN_GROUP(ssi6_ctrl), 4032 SH_PFC_PIN_GROUP(ssi7_data), 4033 SH_PFC_PIN_GROUP(ssi78_ctrl), 4034 SH_PFC_PIN_GROUP(ssi8_data), 4035 SH_PFC_PIN_GROUP(ssi9_data), 4036 SH_PFC_PIN_GROUP(ssi9_ctrl_a), 4037 SH_PFC_PIN_GROUP(ssi9_ctrl_b), 4038 SH_PFC_PIN_GROUP(tmu_tclk1_a), 4039 SH_PFC_PIN_GROUP(tmu_tclk1_b), 4040 SH_PFC_PIN_GROUP(tmu_tclk2_a), 4041 SH_PFC_PIN_GROUP(tmu_tclk2_b), 4042 SH_PFC_PIN_GROUP(usb0_a), 4043 SH_PFC_PIN_GROUP(usb0_b), 4044 SH_PFC_PIN_GROUP(usb0_id), 4045 SH_PFC_PIN_GROUP(usb30), 4046 SH_PFC_PIN_GROUP(usb30_id), 4047 VIN_DATA_PIN_GROUP(vin4_data, 8, _a), 4048 VIN_DATA_PIN_GROUP(vin4_data, 10, _a), 4049 VIN_DATA_PIN_GROUP(vin4_data, 12, _a), 4050 VIN_DATA_PIN_GROUP(vin4_data, 16, _a), 4051 SH_PFC_PIN_GROUP(vin4_data18_a), 4052 VIN_DATA_PIN_GROUP(vin4_data, 20, _a), 4053 VIN_DATA_PIN_GROUP(vin4_data, 24, _a), 4054 VIN_DATA_PIN_GROUP(vin4_data, 8, _b), 4055 VIN_DATA_PIN_GROUP(vin4_data, 10, _b), 4056 VIN_DATA_PIN_GROUP(vin4_data, 12, _b), 4057 VIN_DATA_PIN_GROUP(vin4_data, 16, _b), 4058 SH_PFC_PIN_GROUP(vin4_data18_b), 4059 VIN_DATA_PIN_GROUP(vin4_data, 20, _b), 4060 VIN_DATA_PIN_GROUP(vin4_data, 24, _b), 4061 SH_PFC_PIN_GROUP(vin4_sync), 4062 SH_PFC_PIN_GROUP(vin4_field), 4063 SH_PFC_PIN_GROUP(vin4_clkenb), 4064 SH_PFC_PIN_GROUP(vin4_clk), 4065 VIN_DATA_PIN_GROUP(vin5_data, 8, _a), 4066 VIN_DATA_PIN_GROUP(vin5_data, 10, _a), 4067 VIN_DATA_PIN_GROUP(vin5_data, 12, _a), 4068 VIN_DATA_PIN_GROUP(vin5_data, 16, _a), 4069 SH_PFC_PIN_GROUP(vin5_data8_b), 4070 SH_PFC_PIN_GROUP(vin5_sync_a), 4071 SH_PFC_PIN_GROUP(vin5_field_a), 4072 SH_PFC_PIN_GROUP(vin5_clkenb_a), 4073 SH_PFC_PIN_GROUP(vin5_clk_a), 4074 SH_PFC_PIN_GROUP(vin5_clk_b), 4075 }, 4076 #ifdef CONFIG_PINCTRL_PFC_R8A77990 4077 .automotive = { 4078 SH_PFC_PIN_GROUP(drif0_ctrl_a), 4079 SH_PFC_PIN_GROUP(drif0_data0_a), 4080 SH_PFC_PIN_GROUP(drif0_data1_a), 4081 SH_PFC_PIN_GROUP(drif0_ctrl_b), 4082 SH_PFC_PIN_GROUP(drif0_data0_b), 4083 SH_PFC_PIN_GROUP(drif0_data1_b), 4084 SH_PFC_PIN_GROUP(drif1_ctrl), 4085 SH_PFC_PIN_GROUP(drif1_data0), 4086 SH_PFC_PIN_GROUP(drif1_data1), 4087 SH_PFC_PIN_GROUP(drif2_ctrl_a), 4088 SH_PFC_PIN_GROUP(drif2_data0_a), 4089 SH_PFC_PIN_GROUP(drif2_data1_a), 4090 SH_PFC_PIN_GROUP(drif2_ctrl_b), 4091 SH_PFC_PIN_GROUP(drif2_data0_b), 4092 SH_PFC_PIN_GROUP(drif2_data1_b), 4093 SH_PFC_PIN_GROUP(drif3_ctrl_a), 4094 SH_PFC_PIN_GROUP(drif3_data0_a), 4095 SH_PFC_PIN_GROUP(drif3_data1_a), 4096 SH_PFC_PIN_GROUP(drif3_ctrl_b), 4097 SH_PFC_PIN_GROUP(drif3_data0_b), 4098 SH_PFC_PIN_GROUP(drif3_data1_b), 4099 } 4100 #endif /* CONFIG_PINCTRL_PFC_R8A77990 */ 4101 }; 4102 4103 static const char * const audio_clk_groups[] = { 4104 "audio_clk_a", 4105 "audio_clk_b_a", 4106 "audio_clk_b_b", 4107 "audio_clk_b_c", 4108 "audio_clk_c_a", 4109 "audio_clk_c_b", 4110 "audio_clk_c_c", 4111 "audio_clkout_a", 4112 "audio_clkout_b", 4113 "audio_clkout1_a", 4114 "audio_clkout1_b", 4115 "audio_clkout1_c", 4116 "audio_clkout2_a", 4117 "audio_clkout2_b", 4118 "audio_clkout2_c", 4119 "audio_clkout3_a", 4120 "audio_clkout3_b", 4121 "audio_clkout3_c", 4122 }; 4123 4124 static const char * const avb_groups[] = { 4125 "avb_link", 4126 "avb_magic", 4127 "avb_phy_int", 4128 "avb_mii", 4129 "avb_avtp_pps", 4130 "avb_avtp_match", 4131 "avb_avtp_capture", 4132 }; 4133 4134 static const char * const can0_groups[] = { 4135 "can0_data", 4136 }; 4137 4138 static const char * const can1_groups[] = { 4139 "can1_data", 4140 }; 4141 4142 static const char * const can_clk_groups[] = { 4143 "can_clk", 4144 }; 4145 4146 static const char * const canfd0_groups[] = { 4147 "canfd0_data", 4148 }; 4149 4150 static const char * const canfd1_groups[] = { 4151 "canfd1_data", 4152 }; 4153 4154 #ifdef CONFIG_PINCTRL_PFC_R8A77990 4155 static const char * const drif0_groups[] = { 4156 "drif0_ctrl_a", 4157 "drif0_data0_a", 4158 "drif0_data1_a", 4159 "drif0_ctrl_b", 4160 "drif0_data0_b", 4161 "drif0_data1_b", 4162 }; 4163 4164 static const char * const drif1_groups[] = { 4165 "drif1_ctrl", 4166 "drif1_data0", 4167 "drif1_data1", 4168 }; 4169 4170 static const char * const drif2_groups[] = { 4171 "drif2_ctrl_a", 4172 "drif2_data0_a", 4173 "drif2_data1_a", 4174 "drif2_ctrl_b", 4175 "drif2_data0_b", 4176 "drif2_data1_b", 4177 }; 4178 4179 static const char * const drif3_groups[] = { 4180 "drif3_ctrl_a", 4181 "drif3_data0_a", 4182 "drif3_data1_a", 4183 "drif3_ctrl_b", 4184 "drif3_data0_b", 4185 "drif3_data1_b", 4186 }; 4187 #endif /* CONFIG_PINCTRL_PFC_R8A77990 */ 4188 4189 static const char * const du_groups[] = { 4190 "du_rgb666", 4191 "du_rgb888", 4192 "du_clk_in_0", 4193 "du_clk_in_1", 4194 "du_clk_out_0", 4195 "du_sync", 4196 "du_disp_cde", 4197 "du_cde", 4198 "du_disp", 4199 }; 4200 4201 static const char * const hscif0_groups[] = { 4202 "hscif0_data_a", 4203 "hscif0_clk_a", 4204 "hscif0_ctrl_a", 4205 "hscif0_data_b", 4206 "hscif0_clk_b", 4207 }; 4208 4209 static const char * const hscif1_groups[] = { 4210 "hscif1_data_a", 4211 "hscif1_clk_a", 4212 "hscif1_data_b", 4213 "hscif1_clk_b", 4214 "hscif1_ctrl_b", 4215 }; 4216 4217 static const char * const hscif2_groups[] = { 4218 "hscif2_data_a", 4219 "hscif2_clk_a", 4220 "hscif2_ctrl_a", 4221 "hscif2_data_b", 4222 }; 4223 4224 static const char * const hscif3_groups[] = { 4225 "hscif3_data_a", 4226 "hscif3_data_b", 4227 "hscif3_clk_b", 4228 "hscif3_data_c", 4229 "hscif3_clk_c", 4230 "hscif3_ctrl_c", 4231 "hscif3_data_d", 4232 "hscif3_data_e", 4233 "hscif3_ctrl_e", 4234 }; 4235 4236 static const char * const hscif4_groups[] = { 4237 "hscif4_data_a", 4238 "hscif4_clk_a", 4239 "hscif4_ctrl_a", 4240 "hscif4_data_b", 4241 "hscif4_clk_b", 4242 "hscif4_data_c", 4243 "hscif4_data_d", 4244 "hscif4_data_e", 4245 }; 4246 4247 static const char * const i2c1_groups[] = { 4248 "i2c1_a", 4249 "i2c1_b", 4250 "i2c1_c", 4251 "i2c1_d", 4252 }; 4253 4254 static const char * const i2c2_groups[] = { 4255 "i2c2_a", 4256 "i2c2_b", 4257 "i2c2_c", 4258 "i2c2_d", 4259 "i2c2_e", 4260 }; 4261 4262 static const char * const i2c4_groups[] = { 4263 "i2c4", 4264 }; 4265 4266 static const char * const i2c5_groups[] = { 4267 "i2c5", 4268 }; 4269 4270 static const char * const i2c6_groups[] = { 4271 "i2c6_a", 4272 "i2c6_b", 4273 }; 4274 4275 static const char * const i2c7_groups[] = { 4276 "i2c7_a", 4277 "i2c7_b", 4278 }; 4279 4280 static const char * const intc_ex_groups[] = { 4281 "intc_ex_irq0", 4282 "intc_ex_irq1", 4283 "intc_ex_irq2", 4284 "intc_ex_irq3", 4285 "intc_ex_irq4", 4286 "intc_ex_irq5", 4287 }; 4288 4289 static const char * const msiof0_groups[] = { 4290 "msiof0_clk", 4291 "msiof0_sync", 4292 "msiof0_ss1", 4293 "msiof0_ss2", 4294 "msiof0_txd", 4295 "msiof0_rxd", 4296 }; 4297 4298 static const char * const msiof1_groups[] = { 4299 "msiof1_clk", 4300 "msiof1_sync", 4301 "msiof1_ss1", 4302 "msiof1_ss2", 4303 "msiof1_txd", 4304 "msiof1_rxd", 4305 }; 4306 4307 static const char * const msiof2_groups[] = { 4308 "msiof2_clk_a", 4309 "msiof2_sync_a", 4310 "msiof2_ss1_a", 4311 "msiof2_ss2_a", 4312 "msiof2_txd_a", 4313 "msiof2_rxd_a", 4314 "msiof2_clk_b", 4315 "msiof2_sync_b", 4316 "msiof2_ss1_b", 4317 "msiof2_ss2_b", 4318 "msiof2_txd_b", 4319 "msiof2_rxd_b", 4320 }; 4321 4322 static const char * const msiof3_groups[] = { 4323 "msiof3_clk_a", 4324 "msiof3_sync_a", 4325 "msiof3_ss1_a", 4326 "msiof3_ss2_a", 4327 "msiof3_txd_a", 4328 "msiof3_rxd_a", 4329 "msiof3_clk_b", 4330 "msiof3_sync_b", 4331 "msiof3_ss1_b", 4332 "msiof3_txd_b", 4333 "msiof3_rxd_b", 4334 }; 4335 4336 static const char * const pwm0_groups[] = { 4337 "pwm0_a", 4338 "pwm0_b", 4339 }; 4340 4341 static const char * const pwm1_groups[] = { 4342 "pwm1_a", 4343 "pwm1_b", 4344 }; 4345 4346 static const char * const pwm2_groups[] = { 4347 "pwm2_a", 4348 "pwm2_b", 4349 "pwm2_c", 4350 }; 4351 4352 static const char * const pwm3_groups[] = { 4353 "pwm3_a", 4354 "pwm3_b", 4355 "pwm3_c", 4356 }; 4357 4358 static const char * const pwm4_groups[] = { 4359 "pwm4_a", 4360 "pwm4_b", 4361 }; 4362 4363 static const char * const pwm5_groups[] = { 4364 "pwm5_a", 4365 "pwm5_b", 4366 }; 4367 4368 static const char * const pwm6_groups[] = { 4369 "pwm6_a", 4370 "pwm6_b", 4371 }; 4372 4373 static const char * const qspi0_groups[] = { 4374 "qspi0_ctrl", 4375 "qspi0_data2", 4376 "qspi0_data4", 4377 }; 4378 4379 static const char * const qspi1_groups[] = { 4380 "qspi1_ctrl", 4381 "qspi1_data2", 4382 "qspi1_data4", 4383 }; 4384 4385 static const char * const scif0_groups[] = { 4386 "scif0_data_a", 4387 "scif0_clk_a", 4388 "scif0_ctrl_a", 4389 "scif0_data_b", 4390 "scif0_clk_b", 4391 }; 4392 4393 static const char * const scif1_groups[] = { 4394 "scif1_data", 4395 "scif1_clk", 4396 "scif1_ctrl", 4397 }; 4398 4399 static const char * const scif2_groups[] = { 4400 "scif2_data_a", 4401 "scif2_clk_a", 4402 "scif2_data_b", 4403 }; 4404 4405 static const char * const scif3_groups[] = { 4406 "scif3_data_a", 4407 "scif3_clk_a", 4408 "scif3_ctrl_a", 4409 "scif3_data_b", 4410 "scif3_data_c", 4411 "scif3_clk_c", 4412 }; 4413 4414 static const char * const scif4_groups[] = { 4415 "scif4_data_a", 4416 "scif4_clk_a", 4417 "scif4_ctrl_a", 4418 "scif4_data_b", 4419 "scif4_clk_b", 4420 "scif4_data_c", 4421 "scif4_ctrl_c", 4422 }; 4423 4424 static const char * const scif5_groups[] = { 4425 "scif5_data_a", 4426 "scif5_clk_a", 4427 "scif5_data_b", 4428 "scif5_data_c", 4429 }; 4430 4431 static const char * const scif_clk_groups[] = { 4432 "scif_clk_a", 4433 "scif_clk_b", 4434 }; 4435 4436 static const char * const sdhi0_groups[] = { 4437 "sdhi0_data1", 4438 "sdhi0_data4", 4439 "sdhi0_ctrl", 4440 "sdhi0_cd", 4441 "sdhi0_wp", 4442 }; 4443 4444 static const char * const sdhi1_groups[] = { 4445 "sdhi1_data1", 4446 "sdhi1_data4", 4447 "sdhi1_ctrl", 4448 "sdhi1_cd", 4449 "sdhi1_wp", 4450 }; 4451 4452 static const char * const sdhi3_groups[] = { 4453 "sdhi3_data1", 4454 "sdhi3_data4", 4455 "sdhi3_data8", 4456 "sdhi3_ctrl", 4457 "sdhi3_cd", 4458 "sdhi3_wp", 4459 "sdhi3_ds", 4460 }; 4461 4462 static const char * const ssi_groups[] = { 4463 "ssi0_data", 4464 "ssi01239_ctrl", 4465 "ssi1_data", 4466 "ssi1_ctrl", 4467 "ssi2_data", 4468 "ssi2_ctrl_a", 4469 "ssi2_ctrl_b", 4470 "ssi3_data", 4471 "ssi349_ctrl", 4472 "ssi4_data", 4473 "ssi4_ctrl", 4474 "ssi5_data", 4475 "ssi5_ctrl", 4476 "ssi6_data", 4477 "ssi6_ctrl", 4478 "ssi7_data", 4479 "ssi78_ctrl", 4480 "ssi8_data", 4481 "ssi9_data", 4482 "ssi9_ctrl_a", 4483 "ssi9_ctrl_b", 4484 }; 4485 4486 static const char * const tmu_groups[] = { 4487 "tmu_tclk1_a", 4488 "tmu_tclk1_b", 4489 "tmu_tclk2_a", 4490 "tmu_tclk2_b", 4491 }; 4492 4493 static const char * const usb0_groups[] = { 4494 "usb0_a", 4495 "usb0_b", 4496 "usb0_id", 4497 }; 4498 4499 static const char * const usb30_groups[] = { 4500 "usb30", 4501 "usb30_id", 4502 }; 4503 4504 static const char * const vin4_groups[] = { 4505 "vin4_data8_a", 4506 "vin4_data10_a", 4507 "vin4_data12_a", 4508 "vin4_data16_a", 4509 "vin4_data18_a", 4510 "vin4_data20_a", 4511 "vin4_data24_a", 4512 "vin4_data8_b", 4513 "vin4_data10_b", 4514 "vin4_data12_b", 4515 "vin4_data16_b", 4516 "vin4_data18_b", 4517 "vin4_data20_b", 4518 "vin4_data24_b", 4519 "vin4_sync", 4520 "vin4_field", 4521 "vin4_clkenb", 4522 "vin4_clk", 4523 }; 4524 4525 static const char * const vin5_groups[] = { 4526 "vin5_data8_a", 4527 "vin5_data10_a", 4528 "vin5_data12_a", 4529 "vin5_data16_a", 4530 "vin5_data8_b", 4531 "vin5_sync_a", 4532 "vin5_field_a", 4533 "vin5_clkenb_a", 4534 "vin5_clk_a", 4535 "vin5_clk_b", 4536 }; 4537 4538 static const struct { 4539 struct sh_pfc_function common[49]; 4540 #ifdef CONFIG_PINCTRL_PFC_R8A77990 4541 struct sh_pfc_function automotive[4]; 4542 #endif 4543 } pinmux_functions = { 4544 .common = { 4545 SH_PFC_FUNCTION(audio_clk), 4546 SH_PFC_FUNCTION(avb), 4547 SH_PFC_FUNCTION(can0), 4548 SH_PFC_FUNCTION(can1), 4549 SH_PFC_FUNCTION(can_clk), 4550 SH_PFC_FUNCTION(canfd0), 4551 SH_PFC_FUNCTION(canfd1), 4552 SH_PFC_FUNCTION(du), 4553 SH_PFC_FUNCTION(hscif0), 4554 SH_PFC_FUNCTION(hscif1), 4555 SH_PFC_FUNCTION(hscif2), 4556 SH_PFC_FUNCTION(hscif3), 4557 SH_PFC_FUNCTION(hscif4), 4558 SH_PFC_FUNCTION(i2c1), 4559 SH_PFC_FUNCTION(i2c2), 4560 SH_PFC_FUNCTION(i2c4), 4561 SH_PFC_FUNCTION(i2c5), 4562 SH_PFC_FUNCTION(i2c6), 4563 SH_PFC_FUNCTION(i2c7), 4564 SH_PFC_FUNCTION(intc_ex), 4565 SH_PFC_FUNCTION(msiof0), 4566 SH_PFC_FUNCTION(msiof1), 4567 SH_PFC_FUNCTION(msiof2), 4568 SH_PFC_FUNCTION(msiof3), 4569 SH_PFC_FUNCTION(pwm0), 4570 SH_PFC_FUNCTION(pwm1), 4571 SH_PFC_FUNCTION(pwm2), 4572 SH_PFC_FUNCTION(pwm3), 4573 SH_PFC_FUNCTION(pwm4), 4574 SH_PFC_FUNCTION(pwm5), 4575 SH_PFC_FUNCTION(pwm6), 4576 SH_PFC_FUNCTION(qspi0), 4577 SH_PFC_FUNCTION(qspi1), 4578 SH_PFC_FUNCTION(scif0), 4579 SH_PFC_FUNCTION(scif1), 4580 SH_PFC_FUNCTION(scif2), 4581 SH_PFC_FUNCTION(scif3), 4582 SH_PFC_FUNCTION(scif4), 4583 SH_PFC_FUNCTION(scif5), 4584 SH_PFC_FUNCTION(scif_clk), 4585 SH_PFC_FUNCTION(sdhi0), 4586 SH_PFC_FUNCTION(sdhi1), 4587 SH_PFC_FUNCTION(sdhi3), 4588 SH_PFC_FUNCTION(ssi), 4589 SH_PFC_FUNCTION(tmu), 4590 SH_PFC_FUNCTION(usb0), 4591 SH_PFC_FUNCTION(usb30), 4592 SH_PFC_FUNCTION(vin4), 4593 SH_PFC_FUNCTION(vin5), 4594 }, 4595 #ifdef CONFIG_PINCTRL_PFC_R8A77990 4596 .automotive = { 4597 SH_PFC_FUNCTION(drif0), 4598 SH_PFC_FUNCTION(drif1), 4599 SH_PFC_FUNCTION(drif2), 4600 SH_PFC_FUNCTION(drif3), 4601 } 4602 #endif /* CONFIG_PINCTRL_PFC_R8A77990 */ 4603 }; 4604 4605 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 4606 #define F_(x, y) FN_##y 4607 #define FM(x) FN_##x 4608 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( 4609 0, 0, 4610 0, 0, 4611 0, 0, 4612 0, 0, 4613 0, 0, 4614 0, 0, 4615 0, 0, 4616 0, 0, 4617 0, 0, 4618 0, 0, 4619 0, 0, 4620 0, 0, 4621 0, 0, 4622 0, 0, 4623 GP_0_17_FN, GPSR0_17, 4624 GP_0_16_FN, GPSR0_16, 4625 GP_0_15_FN, GPSR0_15, 4626 GP_0_14_FN, GPSR0_14, 4627 GP_0_13_FN, GPSR0_13, 4628 GP_0_12_FN, GPSR0_12, 4629 GP_0_11_FN, GPSR0_11, 4630 GP_0_10_FN, GPSR0_10, 4631 GP_0_9_FN, GPSR0_9, 4632 GP_0_8_FN, GPSR0_8, 4633 GP_0_7_FN, GPSR0_7, 4634 GP_0_6_FN, GPSR0_6, 4635 GP_0_5_FN, GPSR0_5, 4636 GP_0_4_FN, GPSR0_4, 4637 GP_0_3_FN, GPSR0_3, 4638 GP_0_2_FN, GPSR0_2, 4639 GP_0_1_FN, GPSR0_1, 4640 GP_0_0_FN, GPSR0_0, )) 4641 }, 4642 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( 4643 0, 0, 4644 0, 0, 4645 0, 0, 4646 0, 0, 4647 0, 0, 4648 0, 0, 4649 0, 0, 4650 0, 0, 4651 0, 0, 4652 GP_1_22_FN, GPSR1_22, 4653 GP_1_21_FN, GPSR1_21, 4654 GP_1_20_FN, GPSR1_20, 4655 GP_1_19_FN, GPSR1_19, 4656 GP_1_18_FN, GPSR1_18, 4657 GP_1_17_FN, GPSR1_17, 4658 GP_1_16_FN, GPSR1_16, 4659 GP_1_15_FN, GPSR1_15, 4660 GP_1_14_FN, GPSR1_14, 4661 GP_1_13_FN, GPSR1_13, 4662 GP_1_12_FN, GPSR1_12, 4663 GP_1_11_FN, GPSR1_11, 4664 GP_1_10_FN, GPSR1_10, 4665 GP_1_9_FN, GPSR1_9, 4666 GP_1_8_FN, GPSR1_8, 4667 GP_1_7_FN, GPSR1_7, 4668 GP_1_6_FN, GPSR1_6, 4669 GP_1_5_FN, GPSR1_5, 4670 GP_1_4_FN, GPSR1_4, 4671 GP_1_3_FN, GPSR1_3, 4672 GP_1_2_FN, GPSR1_2, 4673 GP_1_1_FN, GPSR1_1, 4674 GP_1_0_FN, GPSR1_0, )) 4675 }, 4676 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( 4677 0, 0, 4678 0, 0, 4679 0, 0, 4680 0, 0, 4681 0, 0, 4682 0, 0, 4683 GP_2_25_FN, GPSR2_25, 4684 GP_2_24_FN, GPSR2_24, 4685 GP_2_23_FN, GPSR2_23, 4686 GP_2_22_FN, GPSR2_22, 4687 GP_2_21_FN, GPSR2_21, 4688 GP_2_20_FN, GPSR2_20, 4689 GP_2_19_FN, GPSR2_19, 4690 GP_2_18_FN, GPSR2_18, 4691 GP_2_17_FN, GPSR2_17, 4692 GP_2_16_FN, GPSR2_16, 4693 GP_2_15_FN, GPSR2_15, 4694 GP_2_14_FN, GPSR2_14, 4695 GP_2_13_FN, GPSR2_13, 4696 GP_2_12_FN, GPSR2_12, 4697 GP_2_11_FN, GPSR2_11, 4698 GP_2_10_FN, GPSR2_10, 4699 GP_2_9_FN, GPSR2_9, 4700 GP_2_8_FN, GPSR2_8, 4701 GP_2_7_FN, GPSR2_7, 4702 GP_2_6_FN, GPSR2_6, 4703 GP_2_5_FN, GPSR2_5, 4704 GP_2_4_FN, GPSR2_4, 4705 GP_2_3_FN, GPSR2_3, 4706 GP_2_2_FN, GPSR2_2, 4707 GP_2_1_FN, GPSR2_1, 4708 GP_2_0_FN, GPSR2_0, )) 4709 }, 4710 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( 4711 0, 0, 4712 0, 0, 4713 0, 0, 4714 0, 0, 4715 0, 0, 4716 0, 0, 4717 0, 0, 4718 0, 0, 4719 0, 0, 4720 0, 0, 4721 0, 0, 4722 0, 0, 4723 0, 0, 4724 0, 0, 4725 0, 0, 4726 0, 0, 4727 GP_3_15_FN, GPSR3_15, 4728 GP_3_14_FN, GPSR3_14, 4729 GP_3_13_FN, GPSR3_13, 4730 GP_3_12_FN, GPSR3_12, 4731 GP_3_11_FN, GPSR3_11, 4732 GP_3_10_FN, GPSR3_10, 4733 GP_3_9_FN, GPSR3_9, 4734 GP_3_8_FN, GPSR3_8, 4735 GP_3_7_FN, GPSR3_7, 4736 GP_3_6_FN, GPSR3_6, 4737 GP_3_5_FN, GPSR3_5, 4738 GP_3_4_FN, GPSR3_4, 4739 GP_3_3_FN, GPSR3_3, 4740 GP_3_2_FN, GPSR3_2, 4741 GP_3_1_FN, GPSR3_1, 4742 GP_3_0_FN, GPSR3_0, )) 4743 }, 4744 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( 4745 0, 0, 4746 0, 0, 4747 0, 0, 4748 0, 0, 4749 0, 0, 4750 0, 0, 4751 0, 0, 4752 0, 0, 4753 0, 0, 4754 0, 0, 4755 0, 0, 4756 0, 0, 4757 0, 0, 4758 0, 0, 4759 0, 0, 4760 0, 0, 4761 0, 0, 4762 0, 0, 4763 0, 0, 4764 0, 0, 4765 0, 0, 4766 GP_4_10_FN, GPSR4_10, 4767 GP_4_9_FN, GPSR4_9, 4768 GP_4_8_FN, GPSR4_8, 4769 GP_4_7_FN, GPSR4_7, 4770 GP_4_6_FN, GPSR4_6, 4771 GP_4_5_FN, GPSR4_5, 4772 GP_4_4_FN, GPSR4_4, 4773 GP_4_3_FN, GPSR4_3, 4774 GP_4_2_FN, GPSR4_2, 4775 GP_4_1_FN, GPSR4_1, 4776 GP_4_0_FN, GPSR4_0, )) 4777 }, 4778 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( 4779 0, 0, 4780 0, 0, 4781 0, 0, 4782 0, 0, 4783 0, 0, 4784 0, 0, 4785 0, 0, 4786 0, 0, 4787 0, 0, 4788 0, 0, 4789 0, 0, 4790 0, 0, 4791 GP_5_19_FN, GPSR5_19, 4792 GP_5_18_FN, GPSR5_18, 4793 GP_5_17_FN, GPSR5_17, 4794 GP_5_16_FN, GPSR5_16, 4795 GP_5_15_FN, GPSR5_15, 4796 GP_5_14_FN, GPSR5_14, 4797 GP_5_13_FN, GPSR5_13, 4798 GP_5_12_FN, GPSR5_12, 4799 GP_5_11_FN, GPSR5_11, 4800 GP_5_10_FN, GPSR5_10, 4801 GP_5_9_FN, GPSR5_9, 4802 GP_5_8_FN, GPSR5_8, 4803 GP_5_7_FN, GPSR5_7, 4804 GP_5_6_FN, GPSR5_6, 4805 GP_5_5_FN, GPSR5_5, 4806 GP_5_4_FN, GPSR5_4, 4807 GP_5_3_FN, GPSR5_3, 4808 GP_5_2_FN, GPSR5_2, 4809 GP_5_1_FN, GPSR5_1, 4810 GP_5_0_FN, GPSR5_0, )) 4811 }, 4812 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP( 4813 0, 0, 4814 0, 0, 4815 0, 0, 4816 0, 0, 4817 0, 0, 4818 0, 0, 4819 0, 0, 4820 0, 0, 4821 0, 0, 4822 0, 0, 4823 0, 0, 4824 0, 0, 4825 0, 0, 4826 0, 0, 4827 GP_6_17_FN, GPSR6_17, 4828 GP_6_16_FN, GPSR6_16, 4829 GP_6_15_FN, GPSR6_15, 4830 GP_6_14_FN, GPSR6_14, 4831 GP_6_13_FN, GPSR6_13, 4832 GP_6_12_FN, GPSR6_12, 4833 GP_6_11_FN, GPSR6_11, 4834 GP_6_10_FN, GPSR6_10, 4835 GP_6_9_FN, GPSR6_9, 4836 GP_6_8_FN, GPSR6_8, 4837 GP_6_7_FN, GPSR6_7, 4838 GP_6_6_FN, GPSR6_6, 4839 GP_6_5_FN, GPSR6_5, 4840 GP_6_4_FN, GPSR6_4, 4841 GP_6_3_FN, GPSR6_3, 4842 GP_6_2_FN, GPSR6_2, 4843 GP_6_1_FN, GPSR6_1, 4844 GP_6_0_FN, GPSR6_0, )) 4845 }, 4846 #undef F_ 4847 #undef FM 4848 4849 #define F_(x, y) x, 4850 #define FM(x) FN_##x, 4851 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( 4852 IP0_31_28 4853 IP0_27_24 4854 IP0_23_20 4855 IP0_19_16 4856 IP0_15_12 4857 IP0_11_8 4858 IP0_7_4 4859 IP0_3_0 )) 4860 }, 4861 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( 4862 IP1_31_28 4863 IP1_27_24 4864 IP1_23_20 4865 IP1_19_16 4866 IP1_15_12 4867 IP1_11_8 4868 IP1_7_4 4869 IP1_3_0 )) 4870 }, 4871 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( 4872 IP2_31_28 4873 IP2_27_24 4874 IP2_23_20 4875 IP2_19_16 4876 IP2_15_12 4877 IP2_11_8 4878 IP2_7_4 4879 IP2_3_0 )) 4880 }, 4881 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( 4882 IP3_31_28 4883 IP3_27_24 4884 IP3_23_20 4885 IP3_19_16 4886 IP3_15_12 4887 IP3_11_8 4888 IP3_7_4 4889 IP3_3_0 )) 4890 }, 4891 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( 4892 IP4_31_28 4893 IP4_27_24 4894 IP4_23_20 4895 IP4_19_16 4896 IP4_15_12 4897 IP4_11_8 4898 IP4_7_4 4899 IP4_3_0 )) 4900 }, 4901 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( 4902 IP5_31_28 4903 IP5_27_24 4904 IP5_23_20 4905 IP5_19_16 4906 IP5_15_12 4907 IP5_11_8 4908 IP5_7_4 4909 IP5_3_0 )) 4910 }, 4911 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( 4912 IP6_31_28 4913 IP6_27_24 4914 IP6_23_20 4915 IP6_19_16 4916 IP6_15_12 4917 IP6_11_8 4918 IP6_7_4 4919 IP6_3_0 )) 4920 }, 4921 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( 4922 IP7_31_28 4923 IP7_27_24 4924 IP7_23_20 4925 IP7_19_16 4926 IP7_15_12 4927 IP7_11_8 4928 IP7_7_4 4929 IP7_3_0 )) 4930 }, 4931 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( 4932 IP8_31_28 4933 IP8_27_24 4934 IP8_23_20 4935 IP8_19_16 4936 IP8_15_12 4937 IP8_11_8 4938 IP8_7_4 4939 IP8_3_0 )) 4940 }, 4941 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP( 4942 IP9_31_28 4943 IP9_27_24 4944 IP9_23_20 4945 IP9_19_16 4946 IP9_15_12 4947 IP9_11_8 4948 IP9_7_4 4949 IP9_3_0 )) 4950 }, 4951 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP( 4952 IP10_31_28 4953 IP10_27_24 4954 IP10_23_20 4955 IP10_19_16 4956 IP10_15_12 4957 IP10_11_8 4958 IP10_7_4 4959 IP10_3_0 )) 4960 }, 4961 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP( 4962 IP11_31_28 4963 IP11_27_24 4964 IP11_23_20 4965 IP11_19_16 4966 IP11_15_12 4967 IP11_11_8 4968 IP11_7_4 4969 IP11_3_0 )) 4970 }, 4971 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP( 4972 IP12_31_28 4973 IP12_27_24 4974 IP12_23_20 4975 IP12_19_16 4976 IP12_15_12 4977 IP12_11_8 4978 IP12_7_4 4979 IP12_3_0 )) 4980 }, 4981 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP( 4982 IP13_31_28 4983 IP13_27_24 4984 IP13_23_20 4985 IP13_19_16 4986 IP13_15_12 4987 IP13_11_8 4988 IP13_7_4 4989 IP13_3_0 )) 4990 }, 4991 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP( 4992 IP14_31_28 4993 IP14_27_24 4994 IP14_23_20 4995 IP14_19_16 4996 IP14_15_12 4997 IP14_11_8 4998 IP14_7_4 4999 IP14_3_0 )) 5000 }, 5001 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP( 5002 IP15_31_28 5003 IP15_27_24 5004 IP15_23_20 5005 IP15_19_16 5006 IP15_15_12 5007 IP15_11_8 5008 IP15_7_4 5009 IP15_3_0 )) 5010 }, 5011 #undef F_ 5012 #undef FM 5013 5014 #define F_(x, y) x, 5015 #define FM(x) FN_##x, 5016 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, 5017 GROUP(1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1, 1, 5018 1, 2, 2, 1, 1, 1, 2, 1, 1, 1, 2), 5019 GROUP( 5020 /* RESERVED 31 */ 5021 0, 0, 5022 MOD_SEL0_30_29 5023 MOD_SEL0_28 5024 MOD_SEL0_27_26 5025 MOD_SEL0_25 5026 MOD_SEL0_24 5027 MOD_SEL0_23 5028 MOD_SEL0_22 5029 MOD_SEL0_21_20 5030 MOD_SEL0_19_18_17 5031 MOD_SEL0_16 5032 MOD_SEL0_15 5033 MOD_SEL0_14 5034 MOD_SEL0_13_12 5035 MOD_SEL0_11_10 5036 MOD_SEL0_9 5037 MOD_SEL0_8 5038 MOD_SEL0_7 5039 MOD_SEL0_6_5 5040 MOD_SEL0_4 5041 MOD_SEL0_3 5042 MOD_SEL0_2 5043 MOD_SEL0_1_0 )) 5044 }, 5045 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, 5046 GROUP(1, 1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1, 5047 1, 2, 2, 2, 1, 1, 2, 1, 4), 5048 GROUP( 5049 MOD_SEL1_31 5050 MOD_SEL1_30 5051 MOD_SEL1_29 5052 MOD_SEL1_28 5053 /* RESERVED 27 */ 5054 0, 0, 5055 MOD_SEL1_26 5056 MOD_SEL1_25 5057 MOD_SEL1_24_23_22 5058 MOD_SEL1_21_20_19 5059 MOD_SEL1_18 5060 MOD_SEL1_17 5061 MOD_SEL1_16 5062 MOD_SEL1_15 5063 MOD_SEL1_14_13 5064 MOD_SEL1_12_11 5065 MOD_SEL1_10_9 5066 MOD_SEL1_8 5067 MOD_SEL1_7 5068 MOD_SEL1_6_5 5069 MOD_SEL1_4 5070 /* RESERVED 3, 2, 1, 0 */ 5071 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 )) 5072 }, 5073 { }, 5074 }; 5075 5076 enum ioctrl_regs { 5077 POCCTRL0, 5078 TDSELCTRL, 5079 }; 5080 5081 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { 5082 [POCCTRL0] = { 0xe6060380, }, 5083 [TDSELCTRL] = { 0xe60603c0, }, 5084 { /* sentinel */ }, 5085 }; 5086 5087 static int r8a77990_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, 5088 u32 *pocctrl) 5089 { 5090 int bit = -EINVAL; 5091 5092 *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg; 5093 5094 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11)) 5095 bit = pin & 0x1f; 5096 5097 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 10)) 5098 bit = (pin & 0x1f) + 19; 5099 5100 return bit; 5101 } 5102 5103 static const struct pinmux_bias_reg pinmux_bias_regs[] = { 5104 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { 5105 [0] = RCAR_GP_PIN(2, 23), /* RD# */ 5106 [1] = RCAR_GP_PIN(2, 22), /* BS# */ 5107 [2] = RCAR_GP_PIN(2, 21), /* AVB_PHY_INT */ 5108 [3] = PIN_AVB_MDC, /* AVB_MDC */ 5109 [4] = PIN_AVB_MDIO, /* AVB_MDIO */ 5110 [5] = RCAR_GP_PIN(2, 20), /* AVB_TXCREFCLK */ 5111 [6] = PIN_AVB_TD3, /* AVB_TD3 */ 5112 [7] = PIN_AVB_TD2, /* AVB_TD2 */ 5113 [8] = PIN_AVB_TD1, /* AVB_TD1 */ 5114 [9] = PIN_AVB_TD0, /* AVB_TD0 */ 5115 [10] = PIN_AVB_TXC, /* AVB_TXC */ 5116 [11] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */ 5117 [12] = RCAR_GP_PIN(2, 19), /* AVB_RD3 */ 5118 [13] = RCAR_GP_PIN(2, 18), /* AVB_RD2 */ 5119 [14] = RCAR_GP_PIN(2, 17), /* AVB_RD1 */ 5120 [15] = RCAR_GP_PIN(2, 16), /* AVB_RD0 */ 5121 [16] = RCAR_GP_PIN(2, 15), /* AVB_RXC */ 5122 [17] = RCAR_GP_PIN(2, 14), /* AVB_RX_CTL */ 5123 [18] = RCAR_GP_PIN(2, 13), /* RPC_RESET# */ 5124 [19] = RCAR_GP_PIN(2, 12), /* RPC_INT# */ 5125 [20] = RCAR_GP_PIN(2, 11), /* QSPI1_SSL */ 5126 [21] = RCAR_GP_PIN(2, 10), /* QSPI1_IO3 */ 5127 [22] = RCAR_GP_PIN(2, 9), /* QSPI1_IO2 */ 5128 [23] = RCAR_GP_PIN(2, 8), /* QSPI1_MISO/IO1 */ 5129 [24] = RCAR_GP_PIN(2, 7), /* QSPI1_MOSI/IO0 */ 5130 [25] = RCAR_GP_PIN(2, 6), /* QSPI1_SPCLK */ 5131 [26] = RCAR_GP_PIN(2, 5), /* QSPI0_SSL */ 5132 [27] = RCAR_GP_PIN(2, 4), /* QSPI0_IO3 */ 5133 [28] = RCAR_GP_PIN(2, 3), /* QSPI0_IO2 */ 5134 [29] = RCAR_GP_PIN(2, 2), /* QSPI0_MISO/IO1 */ 5135 [30] = RCAR_GP_PIN(2, 1), /* QSPI0_MOSI/IO0 */ 5136 [31] = RCAR_GP_PIN(2, 0), /* QSPI0_SPCLK */ 5137 } }, 5138 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) { 5139 [0] = RCAR_GP_PIN(0, 4), /* D4 */ 5140 [1] = RCAR_GP_PIN(0, 3), /* D3 */ 5141 [2] = RCAR_GP_PIN(0, 2), /* D2 */ 5142 [3] = RCAR_GP_PIN(0, 1), /* D1 */ 5143 [4] = RCAR_GP_PIN(0, 0), /* D0 */ 5144 [5] = RCAR_GP_PIN(1, 22), /* WE0# */ 5145 [6] = RCAR_GP_PIN(1, 21), /* CS0# */ 5146 [7] = RCAR_GP_PIN(1, 20), /* CLKOUT */ 5147 [8] = RCAR_GP_PIN(1, 19), /* A19 */ 5148 [9] = RCAR_GP_PIN(1, 18), /* A18 */ 5149 [10] = RCAR_GP_PIN(1, 17), /* A17 */ 5150 [11] = RCAR_GP_PIN(1, 16), /* A16 */ 5151 [12] = RCAR_GP_PIN(1, 15), /* A15 */ 5152 [13] = RCAR_GP_PIN(1, 14), /* A14 */ 5153 [14] = RCAR_GP_PIN(1, 13), /* A13 */ 5154 [15] = RCAR_GP_PIN(1, 12), /* A12 */ 5155 [16] = RCAR_GP_PIN(1, 11), /* A11 */ 5156 [17] = RCAR_GP_PIN(1, 10), /* A10 */ 5157 [18] = RCAR_GP_PIN(1, 9), /* A9 */ 5158 [19] = RCAR_GP_PIN(1, 8), /* A8 */ 5159 [20] = RCAR_GP_PIN(1, 7), /* A7 */ 5160 [21] = RCAR_GP_PIN(1, 6), /* A6 */ 5161 [22] = RCAR_GP_PIN(1, 5), /* A5 */ 5162 [23] = RCAR_GP_PIN(1, 4), /* A4 */ 5163 [24] = RCAR_GP_PIN(1, 3), /* A3 */ 5164 [25] = RCAR_GP_PIN(1, 2), /* A2 */ 5165 [26] = RCAR_GP_PIN(1, 1), /* A1 */ 5166 [27] = RCAR_GP_PIN(1, 0), /* A0 */ 5167 [28] = SH_PFC_PIN_NONE, 5168 [29] = SH_PFC_PIN_NONE, 5169 [30] = RCAR_GP_PIN(2, 25), /* PUEN_EX_WAIT0 */ 5170 [31] = RCAR_GP_PIN(2, 24), /* PUEN_RD/WR# */ 5171 } }, 5172 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { 5173 [0] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ 5174 [1] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ 5175 [2] = PIN_ASEBRK, /* ASEBRK */ 5176 [3] = SH_PFC_PIN_NONE, 5177 [4] = PIN_TDI, /* TDI */ 5178 [5] = PIN_TMS, /* TMS */ 5179 [6] = PIN_TCK, /* TCK */ 5180 [7] = PIN_TRST_N, /* TRST# */ 5181 [8] = SH_PFC_PIN_NONE, 5182 [9] = SH_PFC_PIN_NONE, 5183 [10] = SH_PFC_PIN_NONE, 5184 [11] = SH_PFC_PIN_NONE, 5185 [12] = SH_PFC_PIN_NONE, 5186 [13] = SH_PFC_PIN_NONE, 5187 [14] = SH_PFC_PIN_NONE, 5188 [15] = PIN_FSCLKST_N, /* FSCLKST# */ 5189 [16] = RCAR_GP_PIN(0, 17), /* SDA4 */ 5190 [17] = RCAR_GP_PIN(0, 16), /* SCL4 */ 5191 [18] = SH_PFC_PIN_NONE, 5192 [19] = SH_PFC_PIN_NONE, 5193 [20] = PIN_PRESETOUT_N, /* PRESETOUT# */ 5194 [21] = RCAR_GP_PIN(0, 15), /* D15 */ 5195 [22] = RCAR_GP_PIN(0, 14), /* D14 */ 5196 [23] = RCAR_GP_PIN(0, 13), /* D13 */ 5197 [24] = RCAR_GP_PIN(0, 12), /* D12 */ 5198 [25] = RCAR_GP_PIN(0, 11), /* D11 */ 5199 [26] = RCAR_GP_PIN(0, 10), /* D10 */ 5200 [27] = RCAR_GP_PIN(0, 9), /* D9 */ 5201 [28] = RCAR_GP_PIN(0, 8), /* D8 */ 5202 [29] = RCAR_GP_PIN(0, 7), /* D7 */ 5203 [30] = RCAR_GP_PIN(0, 6), /* D6 */ 5204 [31] = RCAR_GP_PIN(0, 5), /* D5 */ 5205 } }, 5206 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { 5207 [0] = RCAR_GP_PIN(5, 0), /* SCK0_A */ 5208 [1] = RCAR_GP_PIN(5, 4), /* RTS0#_A */ 5209 [2] = RCAR_GP_PIN(5, 3), /* CTS0#_A */ 5210 [3] = RCAR_GP_PIN(5, 2), /* TX0_A */ 5211 [4] = RCAR_GP_PIN(5, 1), /* RX0_A */ 5212 [5] = SH_PFC_PIN_NONE, 5213 [6] = SH_PFC_PIN_NONE, 5214 [7] = RCAR_GP_PIN(3, 15), /* SD1_WP */ 5215 [8] = RCAR_GP_PIN(3, 14), /* SD1_CD */ 5216 [9] = RCAR_GP_PIN(3, 13), /* SD0_WP */ 5217 [10] = RCAR_GP_PIN(3, 12), /* SD0_CD */ 5218 [11] = RCAR_GP_PIN(4, 10), /* SD3_DS */ 5219 [12] = RCAR_GP_PIN(4, 9), /* SD3_DAT7 */ 5220 [13] = RCAR_GP_PIN(4, 8), /* SD3_DAT6 */ 5221 [14] = RCAR_GP_PIN(4, 7), /* SD3_DAT5 */ 5222 [15] = RCAR_GP_PIN(4, 6), /* SD3_DAT4 */ 5223 [16] = RCAR_GP_PIN(4, 5), /* SD3_DAT3 */ 5224 [17] = RCAR_GP_PIN(4, 4), /* SD3_DAT2 */ 5225 [18] = RCAR_GP_PIN(4, 3), /* SD3_DAT1 */ 5226 [19] = RCAR_GP_PIN(4, 2), /* SD3_DAT0 */ 5227 [20] = RCAR_GP_PIN(4, 1), /* SD3_CMD */ 5228 [21] = RCAR_GP_PIN(4, 0), /* SD3_CLK */ 5229 [22] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */ 5230 [23] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */ 5231 [24] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */ 5232 [25] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */ 5233 [26] = RCAR_GP_PIN(3, 7), /* SD1_CMD */ 5234 [27] = RCAR_GP_PIN(3, 6), /* SD1_CLK */ 5235 [28] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */ 5236 [29] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */ 5237 [30] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */ 5238 [31] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ 5239 } }, 5240 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) { 5241 [0] = RCAR_GP_PIN(6, 8), /* AUDIO_CLKA */ 5242 [1] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */ 5243 [2] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */ 5244 [3] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */ 5245 [4] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */ 5246 [5] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */ 5247 [6] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */ 5248 [7] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */ 5249 [8] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */ 5250 [9] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */ 5251 [10] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */ 5252 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2 */ 5253 [12] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1 */ 5254 [13] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */ 5255 [14] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ 5256 [15] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ 5257 [16] = PIN_MLB_REF, /* MLB_REF */ 5258 [17] = RCAR_GP_PIN(5, 19), /* MLB_DAT */ 5259 [18] = RCAR_GP_PIN(5, 18), /* MLB_SIG */ 5260 [19] = RCAR_GP_PIN(5, 17), /* MLB_CLK */ 5261 [20] = RCAR_GP_PIN(5, 16), /* SSI_SDATA9 */ 5262 [21] = RCAR_GP_PIN(5, 15), /* MSIOF0_SS2 */ 5263 [22] = RCAR_GP_PIN(5, 14), /* MSIOF0_SS1 */ 5264 [23] = RCAR_GP_PIN(5, 13), /* MSIOF0_SYNC */ 5265 [24] = RCAR_GP_PIN(5, 12), /* MSIOF0_TXD */ 5266 [25] = RCAR_GP_PIN(5, 11), /* MSIOF0_RXD */ 5267 [26] = RCAR_GP_PIN(5, 10), /* MSIOF0_SCK */ 5268 [27] = RCAR_GP_PIN(5, 9), /* RX2_A */ 5269 [28] = RCAR_GP_PIN(5, 8), /* TX2_A */ 5270 [29] = RCAR_GP_PIN(5, 7), /* SCK2_A */ 5271 [30] = RCAR_GP_PIN(5, 6), /* TX1 */ 5272 [31] = RCAR_GP_PIN(5, 5), /* RX1 */ 5273 } }, 5274 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) { 5275 [0] = SH_PFC_PIN_NONE, 5276 [1] = SH_PFC_PIN_NONE, 5277 [2] = SH_PFC_PIN_NONE, 5278 [3] = SH_PFC_PIN_NONE, 5279 [4] = SH_PFC_PIN_NONE, 5280 [5] = SH_PFC_PIN_NONE, 5281 [6] = SH_PFC_PIN_NONE, 5282 [7] = SH_PFC_PIN_NONE, 5283 [8] = SH_PFC_PIN_NONE, 5284 [9] = SH_PFC_PIN_NONE, 5285 [10] = SH_PFC_PIN_NONE, 5286 [11] = SH_PFC_PIN_NONE, 5287 [12] = SH_PFC_PIN_NONE, 5288 [13] = SH_PFC_PIN_NONE, 5289 [14] = SH_PFC_PIN_NONE, 5290 [15] = SH_PFC_PIN_NONE, 5291 [16] = SH_PFC_PIN_NONE, 5292 [17] = SH_PFC_PIN_NONE, 5293 [18] = SH_PFC_PIN_NONE, 5294 [19] = SH_PFC_PIN_NONE, 5295 [20] = SH_PFC_PIN_NONE, 5296 [21] = SH_PFC_PIN_NONE, 5297 [22] = SH_PFC_PIN_NONE, 5298 [23] = SH_PFC_PIN_NONE, 5299 [24] = SH_PFC_PIN_NONE, 5300 [25] = SH_PFC_PIN_NONE, 5301 [26] = SH_PFC_PIN_NONE, 5302 [27] = SH_PFC_PIN_NONE, 5303 [28] = SH_PFC_PIN_NONE, 5304 [29] = SH_PFC_PIN_NONE, 5305 [30] = RCAR_GP_PIN(6, 9), /* PUEN_USB30_OVC */ 5306 [31] = RCAR_GP_PIN(6, 17), /* PUEN_USB30_PWEN */ 5307 } }, 5308 { /* sentinel */ }, 5309 }; 5310 5311 static const struct sh_pfc_soc_operations r8a77990_pinmux_ops = { 5312 .pin_to_pocctrl = r8a77990_pin_to_pocctrl, 5313 .get_bias = rcar_pinmux_get_bias, 5314 .set_bias = rcar_pinmux_set_bias, 5315 }; 5316 5317 #ifdef CONFIG_PINCTRL_PFC_R8A774C0 5318 const struct sh_pfc_soc_info r8a774c0_pinmux_info = { 5319 .name = "r8a774c0_pfc", 5320 .ops = &r8a77990_pinmux_ops, 5321 .unlock_reg = 0xe6060000, /* PMMR */ 5322 5323 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 5324 5325 .pins = pinmux_pins, 5326 .nr_pins = ARRAY_SIZE(pinmux_pins), 5327 .groups = pinmux_groups.common, 5328 .nr_groups = ARRAY_SIZE(pinmux_groups.common), 5329 .functions = pinmux_functions.common, 5330 .nr_functions = ARRAY_SIZE(pinmux_functions.common), 5331 5332 .cfg_regs = pinmux_config_regs, 5333 .bias_regs = pinmux_bias_regs, 5334 .ioctrl_regs = pinmux_ioctrl_regs, 5335 5336 .pinmux_data = pinmux_data, 5337 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 5338 }; 5339 #endif 5340 5341 #ifdef CONFIG_PINCTRL_PFC_R8A77990 5342 const struct sh_pfc_soc_info r8a77990_pinmux_info = { 5343 .name = "r8a77990_pfc", 5344 .ops = &r8a77990_pinmux_ops, 5345 .unlock_reg = 0xe6060000, /* PMMR */ 5346 5347 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 5348 5349 .pins = pinmux_pins, 5350 .nr_pins = ARRAY_SIZE(pinmux_pins), 5351 .groups = pinmux_groups.common, 5352 .nr_groups = ARRAY_SIZE(pinmux_groups.common) + 5353 ARRAY_SIZE(pinmux_groups.automotive), 5354 .functions = pinmux_functions.common, 5355 .nr_functions = ARRAY_SIZE(pinmux_functions.common) + 5356 ARRAY_SIZE(pinmux_functions.automotive), 5357 5358 .cfg_regs = pinmux_config_regs, 5359 .bias_regs = pinmux_bias_regs, 5360 .ioctrl_regs = pinmux_ioctrl_regs, 5361 5362 .pinmux_data = pinmux_data, 5363 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 5364 }; 5365 #endif 5366