1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * R8A77980 processor support - PFC hardware block. 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 * Copyright (C) 2018 Cogent Embedded, Inc. 7 * 8 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c 9 * 10 * R-Car Gen3 processor support - PFC hardware block. 11 * 12 * Copyright (C) 2015 Renesas Electronics Corporation 13 */ 14 15 #include <linux/errno.h> 16 #include <linux/io.h> 17 #include <linux/kernel.h> 18 19 #include "sh_pfc.h" 20 21 #define CPU_ALL_GP(fn, sfx) \ 22 PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 23 PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 24 PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 25 PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 26 PORT_GP_CFG_25(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 27 PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN) 28 29 #define CPU_ALL_NOGP(fn) \ 30 PIN_NOGP_CFG(DCUTCK_LPDCLK, "DCUTCK_LPDCLK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 31 PIN_NOGP_CFG(DCUTDI_LPDI, "DCUTDI_LPDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 32 PIN_NOGP_CFG(DCUTMS, "DCUTMS", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 33 PIN_NOGP_CFG(DCUTRST_N, "DCUTRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 34 PIN_NOGP_CFG(DU_DOTCLKIN, "DU_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 35 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 36 PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 37 PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 38 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN) 39 40 /* 41 * F_() : just information 42 * FM() : macro for FN_xxx / xxx_MARK 43 */ 44 45 /* GPSR0 */ 46 #define GPSR0_21 F_(DU_EXODDF_DU_ODDF_DISP_CDE, IP2_23_20) 47 #define GPSR0_20 F_(DU_EXVSYNC_DU_VSYNC, IP2_19_16) 48 #define GPSR0_19 F_(DU_EXHSYNC_DU_HSYNC, IP2_15_12) 49 #define GPSR0_18 F_(DU_DOTCLKOUT, IP2_11_8) 50 #define GPSR0_17 F_(DU_DB7, IP2_7_4) 51 #define GPSR0_16 F_(DU_DB6, IP2_3_0) 52 #define GPSR0_15 F_(DU_DB5, IP1_31_28) 53 #define GPSR0_14 F_(DU_DB4, IP1_27_24) 54 #define GPSR0_13 F_(DU_DB3, IP1_23_20) 55 #define GPSR0_12 F_(DU_DB2, IP1_19_16) 56 #define GPSR0_11 F_(DU_DG7, IP1_15_12) 57 #define GPSR0_10 F_(DU_DG6, IP1_11_8) 58 #define GPSR0_9 F_(DU_DG5, IP1_7_4) 59 #define GPSR0_8 F_(DU_DG4, IP1_3_0) 60 #define GPSR0_7 F_(DU_DG3, IP0_31_28) 61 #define GPSR0_6 F_(DU_DG2, IP0_27_24) 62 #define GPSR0_5 F_(DU_DR7, IP0_23_20) 63 #define GPSR0_4 F_(DU_DR6, IP0_19_16) 64 #define GPSR0_3 F_(DU_DR5, IP0_15_12) 65 #define GPSR0_2 F_(DU_DR4, IP0_11_8) 66 #define GPSR0_1 F_(DU_DR3, IP0_7_4) 67 #define GPSR0_0 F_(DU_DR2, IP0_3_0) 68 69 /* GPSR1 */ 70 #define GPSR1_27 F_(DIGRF_CLKOUT, IP8_31_28) 71 #define GPSR1_26 F_(DIGRF_CLKIN, IP8_27_24) 72 #define GPSR1_25 F_(CANFD_CLK_A, IP8_23_20) 73 #define GPSR1_24 F_(CANFD1_RX, IP8_19_16) 74 #define GPSR1_23 F_(CANFD1_TX, IP8_15_12) 75 #define GPSR1_22 F_(CANFD0_RX_A, IP8_11_8) 76 #define GPSR1_21 F_(CANFD0_TX_A, IP8_7_4) 77 #define GPSR1_20 F_(AVB_AVTP_CAPTURE, IP8_3_0) 78 #define GPSR1_19 F_(AVB_AVTP_MATCH, IP7_31_28) 79 #define GPSR1_18 FM(AVB_LINK) 80 #define GPSR1_17 FM(AVB_PHY_INT) 81 #define GPSR1_16 FM(AVB_MAGIC) 82 #define GPSR1_15 FM(AVB_MDC) 83 #define GPSR1_14 FM(AVB_MDIO) 84 #define GPSR1_13 FM(AVB_TXCREFCLK) 85 #define GPSR1_12 FM(AVB_TD3) 86 #define GPSR1_11 FM(AVB_TD2) 87 #define GPSR1_10 FM(AVB_TD1) 88 #define GPSR1_9 FM(AVB_TD0) 89 #define GPSR1_8 FM(AVB_TXC) 90 #define GPSR1_7 FM(AVB_TX_CTL) 91 #define GPSR1_6 FM(AVB_RD3) 92 #define GPSR1_5 FM(AVB_RD2) 93 #define GPSR1_4 FM(AVB_RD1) 94 #define GPSR1_3 FM(AVB_RD0) 95 #define GPSR1_2 FM(AVB_RXC) 96 #define GPSR1_1 FM(AVB_RX_CTL) 97 #define GPSR1_0 F_(IRQ0, IP2_27_24) 98 99 /* GPSR2 */ 100 #define GPSR2_29 F_(FSO_TOE_N, IP10_19_16) 101 #define GPSR2_28 F_(FSO_CFE_1_N, IP10_15_12) 102 #define GPSR2_27 F_(FSO_CFE_0_N, IP10_11_8) 103 #define GPSR2_26 F_(SDA3, IP10_7_4) 104 #define GPSR2_25 F_(SCL3, IP10_3_0) 105 #define GPSR2_24 F_(MSIOF0_SS2, IP9_31_28) 106 #define GPSR2_23 F_(MSIOF0_SS1, IP9_27_24) 107 #define GPSR2_22 F_(MSIOF0_SYNC, IP9_23_20) 108 #define GPSR2_21 F_(MSIOF0_SCK, IP9_19_16) 109 #define GPSR2_20 F_(MSIOF0_TXD, IP9_15_12) 110 #define GPSR2_19 F_(MSIOF0_RXD, IP9_11_8) 111 #define GPSR2_18 F_(IRQ5, IP9_7_4) 112 #define GPSR2_17 F_(IRQ4, IP9_3_0) 113 #define GPSR2_16 F_(VI0_FIELD, IP4_31_28) 114 #define GPSR2_15 F_(VI0_DATA11, IP4_27_24) 115 #define GPSR2_14 F_(VI0_DATA10, IP4_23_20) 116 #define GPSR2_13 F_(VI0_DATA9, IP4_19_16) 117 #define GPSR2_12 F_(VI0_DATA8, IP4_15_12) 118 #define GPSR2_11 F_(VI0_DATA7, IP4_11_8) 119 #define GPSR2_10 F_(VI0_DATA6, IP4_7_4) 120 #define GPSR2_9 F_(VI0_DATA5, IP4_3_0) 121 #define GPSR2_8 F_(VI0_DATA4, IP3_31_28) 122 #define GPSR2_7 F_(VI0_DATA3, IP3_27_24) 123 #define GPSR2_6 F_(VI0_DATA2, IP3_23_20) 124 #define GPSR2_5 F_(VI0_DATA1, IP3_19_16) 125 #define GPSR2_4 F_(VI0_DATA0, IP3_15_12) 126 #define GPSR2_3 F_(VI0_VSYNC_N, IP3_11_8) 127 #define GPSR2_2 F_(VI0_HSYNC_N, IP3_7_4) 128 #define GPSR2_1 F_(VI0_CLKENB, IP3_3_0) 129 #define GPSR2_0 F_(VI0_CLK, IP2_31_28) 130 131 /* GPSR3 */ 132 #define GPSR3_16 F_(VI1_FIELD, IP7_3_0) 133 #define GPSR3_15 F_(VI1_DATA11, IP6_31_28) 134 #define GPSR3_14 F_(VI1_DATA10, IP6_27_24) 135 #define GPSR3_13 F_(VI1_DATA9, IP6_23_20) 136 #define GPSR3_12 F_(VI1_DATA8, IP6_19_16) 137 #define GPSR3_11 F_(VI1_DATA7, IP6_15_12) 138 #define GPSR3_10 F_(VI1_DATA6, IP6_11_8) 139 #define GPSR3_9 F_(VI1_DATA5, IP6_7_4) 140 #define GPSR3_8 F_(VI1_DATA4, IP6_3_0) 141 #define GPSR3_7 F_(VI1_DATA3, IP5_31_28) 142 #define GPSR3_6 F_(VI1_DATA2, IP5_27_24) 143 #define GPSR3_5 F_(VI1_DATA1, IP5_23_20) 144 #define GPSR3_4 F_(VI1_DATA0, IP5_19_16) 145 #define GPSR3_3 F_(VI1_VSYNC_N, IP5_15_12) 146 #define GPSR3_2 F_(VI1_HSYNC_N, IP5_11_8) 147 #define GPSR3_1 F_(VI1_CLKENB, IP5_7_4) 148 #define GPSR3_0 F_(VI1_CLK, IP5_3_0) 149 150 /* GPSR4 */ 151 #define GPSR4_24 FM(GETHER_LINK_A) 152 #define GPSR4_23 FM(GETHER_PHY_INT_A) 153 #define GPSR4_22 FM(GETHER_MAGIC) 154 #define GPSR4_21 FM(GETHER_MDC_A) 155 #define GPSR4_20 FM(GETHER_MDIO_A) 156 #define GPSR4_19 FM(GETHER_TXCREFCLK_MEGA) 157 #define GPSR4_18 FM(GETHER_TXCREFCLK) 158 #define GPSR4_17 FM(GETHER_TD3) 159 #define GPSR4_16 FM(GETHER_TD2) 160 #define GPSR4_15 FM(GETHER_TD1) 161 #define GPSR4_14 FM(GETHER_TD0) 162 #define GPSR4_13 FM(GETHER_TXC) 163 #define GPSR4_12 FM(GETHER_TX_CTL) 164 #define GPSR4_11 FM(GETHER_RD3) 165 #define GPSR4_10 FM(GETHER_RD2) 166 #define GPSR4_9 FM(GETHER_RD1) 167 #define GPSR4_8 FM(GETHER_RD0) 168 #define GPSR4_7 FM(GETHER_RXC) 169 #define GPSR4_6 FM(GETHER_RX_CTL) 170 #define GPSR4_5 F_(SDA2, IP7_27_24) 171 #define GPSR4_4 F_(SCL2, IP7_23_20) 172 #define GPSR4_3 F_(SDA1, IP7_19_16) 173 #define GPSR4_2 F_(SCL1, IP7_15_12) 174 #define GPSR4_1 F_(SDA0, IP7_11_8) 175 #define GPSR4_0 F_(SCL0, IP7_7_4) 176 177 /* GPSR5 */ 178 #define GPSR5_14 FM(RPC_INT_N) 179 #define GPSR5_13 FM(RPC_WP_N) 180 #define GPSR5_12 FM(RPC_RESET_N) 181 #define GPSR5_11 FM(QSPI1_SSL) 182 #define GPSR5_10 FM(QSPI1_IO3) 183 #define GPSR5_9 FM(QSPI1_IO2) 184 #define GPSR5_8 FM(QSPI1_MISO_IO1) 185 #define GPSR5_7 FM(QSPI1_MOSI_IO0) 186 #define GPSR5_6 FM(QSPI1_SPCLK) 187 #define GPSR5_5 FM(QSPI0_SSL) 188 #define GPSR5_4 FM(QSPI0_IO3) 189 #define GPSR5_3 FM(QSPI0_IO2) 190 #define GPSR5_2 FM(QSPI0_MISO_IO1) 191 #define GPSR5_1 FM(QSPI0_MOSI_IO0) 192 #define GPSR5_0 FM(QSPI0_SPCLK) 193 194 195 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ 196 #define IP0_3_0 FM(DU_DR2) FM(SCK4) FM(GETHER_RMII_CRS_DV) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 197 #define IP0_7_4 FM(DU_DR3) FM(RX4) FM(GETHER_RMII_RX_ER) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 198 #define IP0_11_8 FM(DU_DR4) FM(TX4) FM(GETHER_RMII_RXD0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 199 #define IP0_15_12 FM(DU_DR5) FM(CTS4_N) FM(GETHER_RMII_RXD1) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 200 #define IP0_19_16 FM(DU_DR6) FM(RTS4_N) FM(GETHER_RMII_TXD_EN) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 201 #define IP0_23_20 FM(DU_DR7) F_(0, 0) FM(GETHER_RMII_TXD0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 202 #define IP0_27_24 FM(DU_DG2) F_(0, 0) FM(GETHER_RMII_TXD1) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 203 #define IP0_31_28 FM(DU_DG3) FM(CPG_CPCKOUT) FM(GETHER_RMII_REFCLK) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 204 #define IP1_3_0 FM(DU_DG4) FM(SCL5) F_(0, 0) FM(A8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 205 #define IP1_7_4 FM(DU_DG5) FM(SDA5) FM(GETHER_MDC_B) FM(A9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 206 #define IP1_11_8 FM(DU_DG6) FM(SCIF_CLK_A) FM(GETHER_MDIO_B) FM(A10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 207 #define IP1_15_12 FM(DU_DG7) FM(HRX0_A) F_(0, 0) FM(A11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 208 #define IP1_19_16 FM(DU_DB2) FM(HSCK0_A) F_(0, 0) FM(A12) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 209 #define IP1_23_20 FM(DU_DB3) FM(HRTS0_N_A) F_(0, 0) FM(A13) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 210 #define IP1_27_24 FM(DU_DB4) FM(HCTS0_N_A) F_(0, 0) FM(A14) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 211 #define IP1_31_28 FM(DU_DB5) FM(HTX0_A) FM(PWM0_A) FM(A15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 212 #define IP2_3_0 FM(DU_DB6) FM(MSIOF3_RXD) F_(0, 0) FM(A16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 213 #define IP2_7_4 FM(DU_DB7) FM(MSIOF3_TXD) F_(0, 0) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 214 #define IP2_11_8 FM(DU_DOTCLKOUT) FM(MSIOF3_SS1) FM(GETHER_LINK_B) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 215 #define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(MSIOF3_SS2) FM(GETHER_PHY_INT_B) FM(A19) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 216 #define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 217 #define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 218 #define IP2_27_24 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 219 #define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 220 #define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 221 #define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 222 #define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 223 #define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 224 #define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 225 #define IP3_23_20 FM(VI0_DATA2) FM(AVB_AVTP_PPS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 226 #define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 227 #define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 228 #define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 229 #define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 230 #define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 231 #define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 232 #define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 233 #define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 234 #define IP4_27_24 FM(VI0_DATA11) FM(HTX2) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 235 #define IP4_31_28 FM(VI0_FIELD) FM(HRX2) FM(PWM4_A) FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 236 #define IP5_3_0 FM(VI1_CLK) FM(MSIOF1_RXD) F_(0, 0) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 237 #define IP5_7_4 FM(VI1_CLKENB) FM(MSIOF1_TXD) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 238 #define IP5_11_8 FM(VI1_HSYNC_N) FM(MSIOF1_SCK) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 239 #define IP5_15_12 FM(VI1_VSYNC_N) FM(MSIOF1_SYNC) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 240 #define IP5_19_16 FM(VI1_DATA0) FM(MSIOF1_SS1) F_(0, 0) FM(D3) FM(MMC_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 241 #define IP5_23_20 FM(VI1_DATA1) FM(MSIOF1_SS2) F_(0, 0) FM(D4) FM(MMC_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 242 #define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 243 #define IP5_31_28 FM(VI1_DATA3) FM(CANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 244 #define IP6_3_0 FM(VI1_DATA4) FM(CANFD_CLK_B) F_(0, 0) FM(D7) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 245 #define IP6_7_4 FM(VI1_DATA5) F_(0, 0) F_(0, 0) FM(D8) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 246 #define IP6_11_8 FM(VI1_DATA6) F_(0, 0) F_(0, 0) FM(D9) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 247 #define IP6_15_12 FM(VI1_DATA7) F_(0, 0) F_(0, 0) FM(D10) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 248 #define IP6_19_16 FM(VI1_DATA8) F_(0, 0) F_(0, 0) FM(D11) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 249 #define IP6_23_20 FM(VI1_DATA9) FM(TCLK1_A) F_(0, 0) FM(D12) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 250 #define IP6_27_24 FM(VI1_DATA10) FM(TCLK2_A) F_(0, 0) FM(D13) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 251 #define IP6_31_28 FM(VI1_DATA11) FM(SCL4) F_(0, 0) FM(D14) FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 252 #define IP7_3_0 FM(VI1_FIELD) FM(SDA4) F_(0, 0) FM(D15) FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 253 #define IP7_7_4 FM(SCL0) F_(0, 0) F_(0, 0) FM(CLKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 254 #define IP7_11_8 FM(SDA0) F_(0, 0) F_(0, 0) FM(BS_N) FM(SCK0) FM(HSCK0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 255 #define IP7_15_12 FM(SCL1) F_(0, 0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(HCTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 256 #define IP7_19_16 FM(SDA1) F_(0, 0) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N) FM(HRTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 257 #define IP7_23_20 FM(SCL2) F_(0, 0) F_(0, 0) FM(WE1_N) FM(RX0) FM(HRX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 258 #define IP7_27_24 FM(SDA2) F_(0, 0) F_(0, 0) FM(EX_WAIT0) FM(TX0) FM(HTX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 259 #define IP7_31_28 FM(AVB_AVTP_MATCH) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 260 #define IP8_3_0 FM(AVB_AVTP_CAPTURE) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 261 #define IP8_7_4 FM(CANFD0_TX_A) FM(FXR_TXDA) FM(PWM0_B) FM(DU_DISP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 262 #define IP8_11_8 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 263 #define IP8_15_12 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 264 #define IP8_19_16 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 265 #define IP8_23_20 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 266 #define IP8_27_24 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 267 #define IP8_31_28 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 268 #define IP9_3_0 FM(IRQ4) F_(0, 0) F_(0, 0) FM(VI0_DATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 269 #define IP9_7_4 FM(IRQ5) F_(0, 0) F_(0, 0) FM(VI0_DATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 270 #define IP9_11_8 FM(MSIOF0_RXD) FM(DU_DR0) F_(0, 0) FM(VI0_DATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 271 #define IP9_15_12 FM(MSIOF0_TXD) FM(DU_DR1) F_(0, 0) FM(VI0_DATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 272 #define IP9_19_16 FM(MSIOF0_SCK) FM(DU_DG0) F_(0, 0) FM(VI0_DATA16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 273 #define IP9_23_20 FM(MSIOF0_SYNC) FM(DU_DG1) F_(0, 0) FM(VI0_DATA17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 274 #define IP9_27_24 FM(MSIOF0_SS1) FM(DU_DB0) FM(TCLK3) FM(VI0_DATA18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 275 #define IP9_31_28 FM(MSIOF0_SS2) FM(DU_DB1) FM(TCLK4) FM(VI0_DATA19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 276 #define IP10_3_0 FM(SCL3) F_(0, 0) F_(0, 0) FM(VI0_DATA20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 277 #define IP10_7_4 FM(SDA3) F_(0, 0) F_(0, 0) FM(VI0_DATA21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 278 #define IP10_11_8 FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) FM(VI0_DATA22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 279 #define IP10_15_12 FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) FM(VI0_DATA23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 280 #define IP10_19_16 FM(FSO_TOE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 281 282 #define PINMUX_GPSR \ 283 \ 284 GPSR2_29 \ 285 GPSR2_28 \ 286 GPSR1_27 GPSR2_27 \ 287 GPSR1_26 GPSR2_26 \ 288 GPSR1_25 GPSR2_25 \ 289 GPSR1_24 GPSR2_24 GPSR4_24 \ 290 GPSR1_23 GPSR2_23 GPSR4_23 \ 291 GPSR1_22 GPSR2_22 GPSR4_22 \ 292 GPSR0_21 GPSR1_21 GPSR2_21 GPSR4_21 \ 293 GPSR0_20 GPSR1_20 GPSR2_20 GPSR4_20 \ 294 GPSR0_19 GPSR1_19 GPSR2_19 GPSR4_19 \ 295 GPSR0_18 GPSR1_18 GPSR2_18 GPSR4_18 \ 296 GPSR0_17 GPSR1_17 GPSR2_17 GPSR4_17 \ 297 GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 GPSR4_16 \ 298 GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR4_15 \ 299 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 \ 300 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 \ 301 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 \ 302 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 \ 303 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 \ 304 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 \ 305 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 \ 306 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 \ 307 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 \ 308 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 \ 309 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 \ 310 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 \ 311 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 \ 312 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 \ 313 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 314 315 #define PINMUX_IPSR \ 316 \ 317 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \ 318 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \ 319 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \ 320 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \ 321 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \ 322 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \ 323 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ 324 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \ 325 \ 326 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ 327 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ 328 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ 329 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \ 330 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ 331 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ 332 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ 333 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ 334 \ 335 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 \ 336 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 \ 337 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 \ 338 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 \ 339 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 \ 340 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 \ 341 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 \ 342 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 343 344 /* MOD_SEL0 */ /* 0 */ /* 1 */ 345 #define MOD_SEL0_11 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) 346 #define MOD_SEL0_10 FM(SEL_GETHER_0) FM(SEL_GETHER_1) 347 #define MOD_SEL0_9 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1) 348 #define MOD_SEL0_8 FM(SEL_PWM0_0) FM(SEL_PWM0_1) 349 #define MOD_SEL0_7 FM(SEL_PWM1_0) FM(SEL_PWM1_1) 350 #define MOD_SEL0_6 FM(SEL_PWM2_0) FM(SEL_PWM2_1) 351 #define MOD_SEL0_5 FM(SEL_PWM3_0) FM(SEL_PWM3_1) 352 #define MOD_SEL0_4 FM(SEL_PWM4_0) FM(SEL_PWM4_1) 353 #define MOD_SEL0_2 FM(SEL_RSP_0) FM(SEL_RSP_1) 354 #define MOD_SEL0_1 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1) 355 #define MOD_SEL0_0 FM(SEL_TMU_0) FM(SEL_TMU_1) 356 357 #define PINMUX_MOD_SELS \ 358 \ 359 MOD_SEL0_11 \ 360 MOD_SEL0_10 \ 361 MOD_SEL0_9 \ 362 MOD_SEL0_8 \ 363 MOD_SEL0_7 \ 364 MOD_SEL0_6 \ 365 MOD_SEL0_5 \ 366 MOD_SEL0_4 \ 367 MOD_SEL0_2 \ 368 MOD_SEL0_1 \ 369 MOD_SEL0_0 370 371 enum { 372 PINMUX_RESERVED = 0, 373 374 PINMUX_DATA_BEGIN, 375 GP_ALL(DATA), 376 PINMUX_DATA_END, 377 378 #define F_(x, y) 379 #define FM(x) FN_##x, 380 PINMUX_FUNCTION_BEGIN, 381 GP_ALL(FN), 382 PINMUX_GPSR 383 PINMUX_IPSR 384 PINMUX_MOD_SELS 385 PINMUX_FUNCTION_END, 386 #undef F_ 387 #undef FM 388 389 #define F_(x, y) 390 #define FM(x) x##_MARK, 391 PINMUX_MARK_BEGIN, 392 PINMUX_GPSR 393 PINMUX_IPSR 394 PINMUX_MOD_SELS 395 PINMUX_MARK_END, 396 #undef F_ 397 #undef FM 398 }; 399 400 static const u16 pinmux_data[] = { 401 PINMUX_DATA_GP_ALL(), 402 403 PINMUX_SINGLE(AVB_RX_CTL), 404 PINMUX_SINGLE(AVB_RXC), 405 PINMUX_SINGLE(AVB_RD0), 406 PINMUX_SINGLE(AVB_RD1), 407 PINMUX_SINGLE(AVB_RD2), 408 PINMUX_SINGLE(AVB_RD3), 409 PINMUX_SINGLE(AVB_TX_CTL), 410 PINMUX_SINGLE(AVB_TXC), 411 PINMUX_SINGLE(AVB_TD0), 412 PINMUX_SINGLE(AVB_TD1), 413 PINMUX_SINGLE(AVB_TD2), 414 PINMUX_SINGLE(AVB_TD3), 415 PINMUX_SINGLE(AVB_TXCREFCLK), 416 PINMUX_SINGLE(AVB_MDIO), 417 PINMUX_SINGLE(AVB_MDC), 418 PINMUX_SINGLE(AVB_MAGIC), 419 PINMUX_SINGLE(AVB_PHY_INT), 420 PINMUX_SINGLE(AVB_LINK), 421 422 PINMUX_SINGLE(GETHER_RX_CTL), 423 PINMUX_SINGLE(GETHER_RXC), 424 PINMUX_SINGLE(GETHER_RD0), 425 PINMUX_SINGLE(GETHER_RD1), 426 PINMUX_SINGLE(GETHER_RD2), 427 PINMUX_SINGLE(GETHER_RD3), 428 PINMUX_SINGLE(GETHER_TX_CTL), 429 PINMUX_SINGLE(GETHER_TXC), 430 PINMUX_SINGLE(GETHER_TD0), 431 PINMUX_SINGLE(GETHER_TD1), 432 PINMUX_SINGLE(GETHER_TD2), 433 PINMUX_SINGLE(GETHER_TD3), 434 PINMUX_SINGLE(GETHER_TXCREFCLK), 435 PINMUX_SINGLE(GETHER_TXCREFCLK_MEGA), 436 PINMUX_SINGLE(GETHER_MDIO_A), 437 PINMUX_SINGLE(GETHER_MDC_A), 438 PINMUX_SINGLE(GETHER_MAGIC), 439 PINMUX_SINGLE(GETHER_PHY_INT_A), 440 PINMUX_SINGLE(GETHER_LINK_A), 441 442 PINMUX_SINGLE(QSPI0_SPCLK), 443 PINMUX_SINGLE(QSPI0_MOSI_IO0), 444 PINMUX_SINGLE(QSPI0_MISO_IO1), 445 PINMUX_SINGLE(QSPI0_IO2), 446 PINMUX_SINGLE(QSPI0_IO3), 447 PINMUX_SINGLE(QSPI0_SSL), 448 PINMUX_SINGLE(QSPI1_SPCLK), 449 PINMUX_SINGLE(QSPI1_MOSI_IO0), 450 PINMUX_SINGLE(QSPI1_MISO_IO1), 451 PINMUX_SINGLE(QSPI1_IO2), 452 PINMUX_SINGLE(QSPI1_IO3), 453 PINMUX_SINGLE(QSPI1_SSL), 454 PINMUX_SINGLE(RPC_RESET_N), 455 PINMUX_SINGLE(RPC_WP_N), 456 PINMUX_SINGLE(RPC_INT_N), 457 458 /* IPSR0 */ 459 PINMUX_IPSR_GPSR(IP0_3_0, DU_DR2), 460 PINMUX_IPSR_GPSR(IP0_3_0, SCK4), 461 PINMUX_IPSR_GPSR(IP0_3_0, GETHER_RMII_CRS_DV), 462 PINMUX_IPSR_GPSR(IP0_3_0, A0), 463 464 PINMUX_IPSR_GPSR(IP0_7_4, DU_DR3), 465 PINMUX_IPSR_GPSR(IP0_7_4, RX4), 466 PINMUX_IPSR_GPSR(IP0_7_4, GETHER_RMII_RX_ER), 467 PINMUX_IPSR_GPSR(IP0_7_4, A1), 468 469 PINMUX_IPSR_GPSR(IP0_11_8, DU_DR4), 470 PINMUX_IPSR_GPSR(IP0_11_8, TX4), 471 PINMUX_IPSR_GPSR(IP0_11_8, GETHER_RMII_RXD0), 472 PINMUX_IPSR_GPSR(IP0_11_8, A2), 473 474 PINMUX_IPSR_GPSR(IP0_15_12, DU_DR5), 475 PINMUX_IPSR_GPSR(IP0_15_12, CTS4_N), 476 PINMUX_IPSR_GPSR(IP0_15_12, GETHER_RMII_RXD1), 477 PINMUX_IPSR_GPSR(IP0_15_12, A3), 478 479 PINMUX_IPSR_GPSR(IP0_19_16, DU_DR6), 480 PINMUX_IPSR_GPSR(IP0_19_16, RTS4_N), 481 PINMUX_IPSR_GPSR(IP0_19_16, GETHER_RMII_TXD_EN), 482 PINMUX_IPSR_GPSR(IP0_19_16, A4), 483 484 PINMUX_IPSR_GPSR(IP0_23_20, DU_DR7), 485 PINMUX_IPSR_GPSR(IP0_23_20, GETHER_RMII_TXD0), 486 PINMUX_IPSR_GPSR(IP0_23_20, A5), 487 488 PINMUX_IPSR_GPSR(IP0_27_24, DU_DG2), 489 PINMUX_IPSR_GPSR(IP0_27_24, GETHER_RMII_TXD1), 490 PINMUX_IPSR_GPSR(IP0_27_24, A6), 491 492 PINMUX_IPSR_GPSR(IP0_31_28, DU_DG3), 493 PINMUX_IPSR_GPSR(IP0_31_28, CPG_CPCKOUT), 494 PINMUX_IPSR_GPSR(IP0_31_28, GETHER_RMII_REFCLK), 495 PINMUX_IPSR_GPSR(IP0_31_28, A7), 496 PINMUX_IPSR_GPSR(IP0_31_28, PWMFSW0), 497 498 /* IPSR1 */ 499 PINMUX_IPSR_GPSR(IP1_3_0, DU_DG4), 500 PINMUX_IPSR_GPSR(IP1_3_0, SCL5), 501 PINMUX_IPSR_GPSR(IP1_3_0, A8), 502 503 PINMUX_IPSR_GPSR(IP1_7_4, DU_DG5), 504 PINMUX_IPSR_GPSR(IP1_7_4, SDA5), 505 PINMUX_IPSR_MSEL(IP1_7_4, GETHER_MDC_B, SEL_GETHER_1), 506 PINMUX_IPSR_GPSR(IP1_7_4, A9), 507 508 PINMUX_IPSR_GPSR(IP1_11_8, DU_DG6), 509 PINMUX_IPSR_MSEL(IP1_11_8, SCIF_CLK_A, SEL_HSCIF0_0), 510 PINMUX_IPSR_MSEL(IP1_11_8, GETHER_MDIO_B, SEL_GETHER_1), 511 PINMUX_IPSR_GPSR(IP1_11_8, A10), 512 513 PINMUX_IPSR_GPSR(IP1_15_12, DU_DG7), 514 PINMUX_IPSR_MSEL(IP1_15_12, HRX0_A, SEL_HSCIF0_0), 515 PINMUX_IPSR_GPSR(IP1_15_12, A11), 516 517 PINMUX_IPSR_GPSR(IP1_19_16, DU_DB2), 518 PINMUX_IPSR_MSEL(IP1_19_16, HSCK0_A, SEL_HSCIF0_0), 519 PINMUX_IPSR_GPSR(IP1_19_16, A12), 520 PINMUX_IPSR_GPSR(IP1_19_16, IRQ1), 521 522 PINMUX_IPSR_GPSR(IP1_23_20, DU_DB3), 523 PINMUX_IPSR_MSEL(IP1_23_20, HRTS0_N_A, SEL_HSCIF0_0), 524 PINMUX_IPSR_GPSR(IP1_23_20, A13), 525 PINMUX_IPSR_GPSR(IP1_23_20, IRQ2), 526 527 PINMUX_IPSR_GPSR(IP1_27_24, DU_DB4), 528 PINMUX_IPSR_MSEL(IP1_27_24, HCTS0_N_A, SEL_HSCIF0_0), 529 PINMUX_IPSR_GPSR(IP1_27_24, A14), 530 PINMUX_IPSR_GPSR(IP1_27_24, IRQ3), 531 532 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB5), 533 PINMUX_IPSR_MSEL(IP1_31_28, HTX0_A, SEL_HSCIF0_0), 534 PINMUX_IPSR_MSEL(IP1_31_28, PWM0_A, SEL_PWM0_0), 535 PINMUX_IPSR_GPSR(IP1_31_28, A15), 536 537 /* IPSR2 */ 538 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB6), 539 PINMUX_IPSR_GPSR(IP2_3_0, MSIOF3_RXD), 540 PINMUX_IPSR_GPSR(IP2_3_0, A16), 541 542 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB7), 543 PINMUX_IPSR_GPSR(IP2_7_4, MSIOF3_TXD), 544 PINMUX_IPSR_GPSR(IP2_7_4, A17), 545 546 PINMUX_IPSR_GPSR(IP2_11_8, DU_DOTCLKOUT), 547 PINMUX_IPSR_GPSR(IP2_11_8, MSIOF3_SS1), 548 PINMUX_IPSR_MSEL(IP2_11_8, GETHER_LINK_B, SEL_GETHER_1), 549 PINMUX_IPSR_GPSR(IP2_11_8, A18), 550 551 PINMUX_IPSR_GPSR(IP2_15_12, DU_EXHSYNC_DU_HSYNC), 552 PINMUX_IPSR_GPSR(IP2_15_12, MSIOF3_SS2), 553 PINMUX_IPSR_MSEL(IP2_15_12, GETHER_PHY_INT_B, SEL_GETHER_1), 554 PINMUX_IPSR_GPSR(IP2_15_12, A19), 555 PINMUX_IPSR_GPSR(IP2_15_12, FXR_TXENA_N), 556 557 PINMUX_IPSR_GPSR(IP2_19_16, DU_EXVSYNC_DU_VSYNC), 558 PINMUX_IPSR_GPSR(IP2_19_16, MSIOF3_SCK), 559 PINMUX_IPSR_GPSR(IP2_19_16, FXR_TXENB_N), 560 561 PINMUX_IPSR_GPSR(IP2_23_20, DU_EXODDF_DU_ODDF_DISP_CDE), 562 PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC), 563 564 PINMUX_IPSR_GPSR(IP2_27_24, IRQ0), 565 566 PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK), 567 PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK), 568 PINMUX_IPSR_GPSR(IP2_31_28, SCK3), 569 PINMUX_IPSR_GPSR(IP2_31_28, HSCK3), 570 571 /* IPSR3 */ 572 PINMUX_IPSR_GPSR(IP3_3_0, VI0_CLKENB), 573 PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_RXD), 574 PINMUX_IPSR_GPSR(IP3_3_0, RX3), 575 PINMUX_IPSR_GPSR(IP3_3_0, RD_WR_N), 576 PINMUX_IPSR_GPSR(IP3_3_0, HCTS3_N), 577 578 PINMUX_IPSR_GPSR(IP3_7_4, VI0_HSYNC_N), 579 PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD), 580 PINMUX_IPSR_GPSR(IP3_7_4, TX3), 581 PINMUX_IPSR_GPSR(IP3_7_4, HRTS3_N), 582 583 PINMUX_IPSR_GPSR(IP3_11_8, VI0_VSYNC_N), 584 PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_SYNC), 585 PINMUX_IPSR_GPSR(IP3_11_8, CTS3_N), 586 PINMUX_IPSR_GPSR(IP3_11_8, HTX3), 587 588 PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0), 589 PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1), 590 PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N), 591 PINMUX_IPSR_GPSR(IP3_15_12, HRX3), 592 593 PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1), 594 PINMUX_IPSR_GPSR(IP3_19_16, MSIOF2_SS2), 595 PINMUX_IPSR_GPSR(IP3_19_16, SCK1), 596 PINMUX_IPSR_MSEL(IP3_19_16, SPEEDIN_A, SEL_RSP_0), 597 598 PINMUX_IPSR_GPSR(IP3_23_20, VI0_DATA2), 599 PINMUX_IPSR_GPSR(IP3_23_20, AVB_AVTP_PPS), 600 601 PINMUX_IPSR_GPSR(IP3_27_24, VI0_DATA3), 602 PINMUX_IPSR_GPSR(IP3_27_24, HSCK1), 603 604 PINMUX_IPSR_GPSR(IP3_31_28, VI0_DATA4), 605 PINMUX_IPSR_GPSR(IP3_31_28, HRTS1_N), 606 PINMUX_IPSR_MSEL(IP3_31_28, RX1_A, SEL_SCIF1_0), 607 608 /* IPSR4 */ 609 PINMUX_IPSR_GPSR(IP4_3_0, VI0_DATA5), 610 PINMUX_IPSR_GPSR(IP4_3_0, HCTS1_N), 611 PINMUX_IPSR_MSEL(IP4_3_0, TX1_A, SEL_SCIF1_0), 612 613 PINMUX_IPSR_GPSR(IP4_7_4, VI0_DATA6), 614 PINMUX_IPSR_GPSR(IP4_7_4, HTX1), 615 PINMUX_IPSR_GPSR(IP4_7_4, CTS1_N), 616 617 PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7), 618 PINMUX_IPSR_GPSR(IP4_11_8, HRX1), 619 PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N), 620 621 PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8), 622 PINMUX_IPSR_GPSR(IP4_15_12, HSCK2), 623 624 PINMUX_IPSR_GPSR(IP4_19_16, VI0_DATA9), 625 PINMUX_IPSR_GPSR(IP4_19_16, HCTS2_N), 626 PINMUX_IPSR_MSEL(IP4_19_16, PWM1_A, SEL_PWM1_0), 627 628 PINMUX_IPSR_GPSR(IP4_23_20, VI0_DATA10), 629 PINMUX_IPSR_GPSR(IP4_23_20, HRTS2_N), 630 PINMUX_IPSR_MSEL(IP4_23_20, PWM2_A, SEL_PWM2_0), 631 632 PINMUX_IPSR_GPSR(IP4_27_24, VI0_DATA11), 633 PINMUX_IPSR_GPSR(IP4_27_24, HTX2), 634 PINMUX_IPSR_MSEL(IP4_27_24, PWM3_A, SEL_PWM3_0), 635 636 PINMUX_IPSR_GPSR(IP4_31_28, VI0_FIELD), 637 PINMUX_IPSR_GPSR(IP4_31_28, HRX2), 638 PINMUX_IPSR_MSEL(IP4_31_28, PWM4_A, SEL_PWM4_0), 639 PINMUX_IPSR_GPSR(IP4_31_28, CS1_N), 640 641 /* IPSR5 */ 642 PINMUX_IPSR_GPSR(IP5_3_0, VI1_CLK), 643 PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD), 644 PINMUX_IPSR_GPSR(IP5_3_0, CS0_N), 645 646 PINMUX_IPSR_GPSR(IP5_7_4, VI1_CLKENB), 647 PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD), 648 PINMUX_IPSR_GPSR(IP5_7_4, D0), 649 650 PINMUX_IPSR_GPSR(IP5_11_8, VI1_HSYNC_N), 651 PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK), 652 PINMUX_IPSR_GPSR(IP5_11_8, D1), 653 654 PINMUX_IPSR_GPSR(IP5_15_12, VI1_VSYNC_N), 655 PINMUX_IPSR_GPSR(IP5_15_12, MSIOF1_SYNC), 656 PINMUX_IPSR_GPSR(IP5_15_12, D2), 657 658 PINMUX_IPSR_GPSR(IP5_19_16, VI1_DATA0), 659 PINMUX_IPSR_GPSR(IP5_19_16, MSIOF1_SS1), 660 PINMUX_IPSR_GPSR(IP5_19_16, D3), 661 PINMUX_IPSR_GPSR(IP5_19_16, MMC_WP), 662 663 PINMUX_IPSR_GPSR(IP5_23_20, VI1_DATA1), 664 PINMUX_IPSR_GPSR(IP5_23_20, MSIOF1_SS2), 665 PINMUX_IPSR_GPSR(IP5_23_20, D4), 666 PINMUX_IPSR_GPSR(IP5_23_20, MMC_CD), 667 668 PINMUX_IPSR_GPSR(IP5_27_24, VI1_DATA2), 669 PINMUX_IPSR_MSEL(IP5_27_24, CANFD0_TX_B, SEL_CANFD0_1), 670 PINMUX_IPSR_GPSR(IP5_27_24, D5), 671 PINMUX_IPSR_GPSR(IP5_27_24, MMC_DS), 672 673 PINMUX_IPSR_GPSR(IP5_31_28, VI1_DATA3), 674 PINMUX_IPSR_MSEL(IP5_31_28, CANFD0_RX_B, SEL_CANFD0_1), 675 PINMUX_IPSR_GPSR(IP5_31_28, D6), 676 PINMUX_IPSR_GPSR(IP5_31_28, MMC_CMD), 677 678 /* IPSR6 */ 679 PINMUX_IPSR_GPSR(IP6_3_0, VI1_DATA4), 680 PINMUX_IPSR_MSEL(IP6_3_0, CANFD_CLK_B, SEL_CANFD0_1), 681 PINMUX_IPSR_GPSR(IP6_3_0, D7), 682 PINMUX_IPSR_GPSR(IP6_3_0, MMC_D0), 683 684 PINMUX_IPSR_GPSR(IP6_7_4, VI1_DATA5), 685 PINMUX_IPSR_GPSR(IP6_7_4, D8), 686 PINMUX_IPSR_GPSR(IP6_7_4, MMC_D1), 687 688 PINMUX_IPSR_GPSR(IP6_11_8, VI1_DATA6), 689 PINMUX_IPSR_GPSR(IP6_11_8, D9), 690 PINMUX_IPSR_GPSR(IP6_11_8, MMC_D2), 691 692 PINMUX_IPSR_GPSR(IP6_15_12, VI1_DATA7), 693 PINMUX_IPSR_GPSR(IP6_15_12, D10), 694 PINMUX_IPSR_GPSR(IP6_15_12, MMC_D3), 695 696 PINMUX_IPSR_GPSR(IP6_19_16, VI1_DATA8), 697 PINMUX_IPSR_GPSR(IP6_19_16, D11), 698 PINMUX_IPSR_GPSR(IP6_19_16, MMC_CLK), 699 700 PINMUX_IPSR_GPSR(IP6_23_20, VI1_DATA9), 701 PINMUX_IPSR_MSEL(IP6_23_20, TCLK1_A, SEL_TMU_0), 702 PINMUX_IPSR_GPSR(IP6_23_20, D12), 703 PINMUX_IPSR_GPSR(IP6_23_20, MMC_D4), 704 705 PINMUX_IPSR_GPSR(IP6_27_24, VI1_DATA10), 706 PINMUX_IPSR_MSEL(IP6_27_24, TCLK2_A, SEL_TMU_0), 707 PINMUX_IPSR_GPSR(IP6_27_24, D13), 708 PINMUX_IPSR_GPSR(IP6_27_24, MMC_D5), 709 710 PINMUX_IPSR_GPSR(IP6_31_28, VI1_DATA11), 711 PINMUX_IPSR_GPSR(IP6_31_28, SCL4), 712 PINMUX_IPSR_GPSR(IP6_31_28, D14), 713 PINMUX_IPSR_GPSR(IP6_31_28, MMC_D6), 714 715 /* IPSR7 */ 716 PINMUX_IPSR_GPSR(IP7_3_0, VI1_FIELD), 717 PINMUX_IPSR_GPSR(IP7_3_0, SDA4), 718 PINMUX_IPSR_GPSR(IP7_3_0, D15), 719 PINMUX_IPSR_GPSR(IP7_3_0, MMC_D7), 720 721 PINMUX_IPSR_GPSR(IP7_7_4, SCL0), 722 PINMUX_IPSR_GPSR(IP7_7_4, CLKOUT), 723 724 PINMUX_IPSR_GPSR(IP7_11_8, SDA0), 725 PINMUX_IPSR_GPSR(IP7_11_8, BS_N), 726 PINMUX_IPSR_GPSR(IP7_11_8, SCK0), 727 PINMUX_IPSR_MSEL(IP7_11_8, HSCK0_B, SEL_HSCIF0_1), 728 729 PINMUX_IPSR_GPSR(IP7_15_12, SCL1), 730 PINMUX_IPSR_GPSR(IP7_15_12, TPU0TO2), 731 PINMUX_IPSR_GPSR(IP7_15_12, RD_N), 732 PINMUX_IPSR_GPSR(IP7_15_12, CTS0_N), 733 PINMUX_IPSR_GPSR(IP7_15_12, HCTS0_N_B), 734 735 PINMUX_IPSR_GPSR(IP7_19_16, SDA1), 736 PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3), 737 PINMUX_IPSR_GPSR(IP7_19_16, WE0_N), 738 PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N), 739 PINMUX_IPSR_MSEL(IP1_23_20, HRTS0_N_B, SEL_HSCIF0_1), 740 741 PINMUX_IPSR_GPSR(IP7_23_20, SCL2), 742 PINMUX_IPSR_GPSR(IP7_23_20, WE1_N), 743 PINMUX_IPSR_GPSR(IP7_23_20, RX0), 744 PINMUX_IPSR_MSEL(IP7_23_20, HRX0_B, SEL_HSCIF0_1), 745 746 PINMUX_IPSR_GPSR(IP7_27_24, SDA2), 747 PINMUX_IPSR_GPSR(IP7_27_24, EX_WAIT0), 748 PINMUX_IPSR_GPSR(IP7_27_24, TX0), 749 PINMUX_IPSR_MSEL(IP7_27_24, HTX0_B, SEL_HSCIF0_1), 750 751 PINMUX_IPSR_GPSR(IP7_31_28, AVB_AVTP_MATCH), 752 PINMUX_IPSR_GPSR(IP7_31_28, TPU0TO0), 753 754 /* IPSR8 */ 755 PINMUX_IPSR_GPSR(IP8_3_0, AVB_AVTP_CAPTURE), 756 PINMUX_IPSR_GPSR(IP8_3_0, TPU0TO1), 757 758 PINMUX_IPSR_MSEL(IP8_7_4, CANFD0_TX_A, SEL_CANFD0_0), 759 PINMUX_IPSR_GPSR(IP8_7_4, FXR_TXDA), 760 PINMUX_IPSR_MSEL(IP8_7_4, PWM0_B, SEL_PWM0_1), 761 PINMUX_IPSR_GPSR(IP8_7_4, DU_DISP), 762 763 PINMUX_IPSR_MSEL(IP8_11_8, CANFD0_RX_A, SEL_CANFD0_0), 764 PINMUX_IPSR_GPSR(IP8_11_8, RXDA_EXTFXR), 765 PINMUX_IPSR_MSEL(IP8_11_8, PWM1_B, SEL_PWM1_1), 766 PINMUX_IPSR_GPSR(IP8_11_8, DU_CDE), 767 768 PINMUX_IPSR_GPSR(IP8_15_12, CANFD1_TX), 769 PINMUX_IPSR_GPSR(IP8_15_12, FXR_TXDB), 770 PINMUX_IPSR_MSEL(IP8_15_12, PWM2_B, SEL_PWM2_1), 771 PINMUX_IPSR_MSEL(IP8_15_12, TCLK1_B, SEL_TMU_1), 772 PINMUX_IPSR_MSEL(IP8_15_12, TX1_B, SEL_SCIF1_1), 773 774 PINMUX_IPSR_GPSR(IP8_19_16, CANFD1_RX), 775 PINMUX_IPSR_GPSR(IP8_19_16, RXDB_EXTFXR), 776 PINMUX_IPSR_MSEL(IP8_19_16, PWM3_B, SEL_PWM3_1), 777 PINMUX_IPSR_MSEL(IP8_19_16, TCLK2_B, SEL_TMU_1), 778 PINMUX_IPSR_MSEL(IP8_19_16, RX1_B, SEL_SCIF1_1), 779 780 PINMUX_IPSR_MSEL(IP8_23_20, CANFD_CLK_A, SEL_CANFD0_0), 781 PINMUX_IPSR_GPSR(IP8_23_20, CLK_EXTFXR), 782 PINMUX_IPSR_MSEL(IP8_23_20, PWM4_B, SEL_PWM4_1), 783 PINMUX_IPSR_MSEL(IP8_23_20, SPEEDIN_B, SEL_RSP_1), 784 PINMUX_IPSR_MSEL(IP8_23_20, SCIF_CLK_B, SEL_HSCIF0_1), 785 786 PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKIN), 787 PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKEN_IN), 788 789 PINMUX_IPSR_GPSR(IP8_31_28, DIGRF_CLKOUT), 790 PINMUX_IPSR_GPSR(IP8_31_28, DIGRF_CLKEN_OUT), 791 792 /* IPSR9 */ 793 PINMUX_IPSR_GPSR(IP9_3_0, IRQ4), 794 PINMUX_IPSR_GPSR(IP9_3_0, VI0_DATA12), 795 796 PINMUX_IPSR_GPSR(IP9_7_4, IRQ5), 797 PINMUX_IPSR_GPSR(IP9_7_4, VI0_DATA13), 798 799 PINMUX_IPSR_GPSR(IP9_11_8, MSIOF0_RXD), 800 PINMUX_IPSR_GPSR(IP9_11_8, DU_DR0), 801 PINMUX_IPSR_GPSR(IP9_11_8, VI0_DATA14), 802 803 PINMUX_IPSR_GPSR(IP9_15_12, MSIOF0_TXD), 804 PINMUX_IPSR_GPSR(IP9_15_12, DU_DR1), 805 PINMUX_IPSR_GPSR(IP9_15_12, VI0_DATA15), 806 807 PINMUX_IPSR_GPSR(IP9_19_16, MSIOF0_SCK), 808 PINMUX_IPSR_GPSR(IP9_19_16, DU_DG0), 809 PINMUX_IPSR_GPSR(IP9_19_16, VI0_DATA16), 810 811 PINMUX_IPSR_GPSR(IP9_23_20, MSIOF0_SYNC), 812 PINMUX_IPSR_GPSR(IP9_23_20, DU_DG1), 813 PINMUX_IPSR_GPSR(IP9_23_20, VI0_DATA17), 814 815 PINMUX_IPSR_GPSR(IP9_27_24, MSIOF0_SS1), 816 PINMUX_IPSR_GPSR(IP9_27_24, DU_DB0), 817 PINMUX_IPSR_GPSR(IP9_27_24, TCLK3), 818 PINMUX_IPSR_GPSR(IP9_27_24, VI0_DATA18), 819 820 PINMUX_IPSR_GPSR(IP9_31_28, MSIOF0_SS2), 821 PINMUX_IPSR_GPSR(IP9_31_28, DU_DB1), 822 PINMUX_IPSR_GPSR(IP9_31_28, TCLK4), 823 PINMUX_IPSR_GPSR(IP9_31_28, VI0_DATA19), 824 825 /* IPSR10 */ 826 PINMUX_IPSR_GPSR(IP10_3_0, SCL3), 827 PINMUX_IPSR_GPSR(IP10_3_0, VI0_DATA20), 828 829 PINMUX_IPSR_GPSR(IP10_7_4, SDA3), 830 PINMUX_IPSR_GPSR(IP10_7_4, VI0_DATA21), 831 832 PINMUX_IPSR_GPSR(IP10_11_8, FSO_CFE_0_N), 833 PINMUX_IPSR_GPSR(IP10_11_8, VI0_DATA22), 834 835 PINMUX_IPSR_GPSR(IP10_15_12, FSO_CFE_1_N), 836 PINMUX_IPSR_GPSR(IP10_15_12, VI0_DATA23), 837 838 PINMUX_IPSR_GPSR(IP10_19_16, FSO_TOE_N), 839 }; 840 841 /* 842 * Pins not associated with a GPIO port. 843 */ 844 enum { 845 GP_ASSIGN_LAST(), 846 NOGP_ALL(), 847 }; 848 849 static const struct sh_pfc_pin pinmux_pins[] = { 850 PINMUX_GPIO_GP_ALL(), 851 PINMUX_NOGP_ALL(), 852 }; 853 854 /* - AVB -------------------------------------------------------------------- */ 855 static const unsigned int avb_link_pins[] = { 856 /* AVB_LINK */ 857 RCAR_GP_PIN(1, 18), 858 }; 859 static const unsigned int avb_link_mux[] = { 860 AVB_LINK_MARK, 861 }; 862 static const unsigned int avb_magic_pins[] = { 863 /* AVB_MAGIC */ 864 RCAR_GP_PIN(1, 16), 865 }; 866 static const unsigned int avb_magic_mux[] = { 867 AVB_MAGIC_MARK, 868 }; 869 static const unsigned int avb_phy_int_pins[] = { 870 /* AVB_PHY_INT */ 871 RCAR_GP_PIN(1, 17), 872 }; 873 static const unsigned int avb_phy_int_mux[] = { 874 AVB_PHY_INT_MARK, 875 }; 876 static const unsigned int avb_mdio_pins[] = { 877 /* AVB_MDC, AVB_MDIO */ 878 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), 879 }; 880 static const unsigned int avb_mdio_mux[] = { 881 AVB_MDC_MARK, AVB_MDIO_MARK, 882 }; 883 static const unsigned int avb_rgmii_pins[] = { 884 /* 885 * AVB_TX_CTL, AVB_TXC, AVB_TD0, AVB_TD1, AVB_TD2, AVB_TD3, 886 * AVB_RX_CTL, AVB_RXC, AVB_RD0, AVB_RD1, AVB_RD2, AVB_RD3, 887 */ 888 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), 889 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10), 890 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12), 891 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2), 892 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4), 893 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), 894 }; 895 static const unsigned int avb_rgmii_mux[] = { 896 AVB_TX_CTL_MARK, AVB_TXC_MARK, 897 AVB_TD0_MARK, AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK, 898 AVB_RX_CTL_MARK, AVB_RXC_MARK, 899 AVB_RD0_MARK, AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK, 900 }; 901 static const unsigned int avb_txcrefclk_pins[] = { 902 /* AVB_TXCREFCLK */ 903 RCAR_GP_PIN(1, 13), 904 }; 905 static const unsigned int avb_txcrefclk_mux[] = { 906 AVB_TXCREFCLK_MARK, 907 }; 908 static const unsigned int avb_avtp_pps_pins[] = { 909 /* AVB_AVTP_PPS */ 910 RCAR_GP_PIN(2, 6), 911 }; 912 static const unsigned int avb_avtp_pps_mux[] = { 913 AVB_AVTP_PPS_MARK, 914 }; 915 static const unsigned int avb_avtp_capture_pins[] = { 916 /* AVB_AVTP_CAPTURE */ 917 RCAR_GP_PIN(1, 20), 918 }; 919 static const unsigned int avb_avtp_capture_mux[] = { 920 AVB_AVTP_CAPTURE_MARK, 921 }; 922 static const unsigned int avb_avtp_match_pins[] = { 923 /* AVB_AVTP_MATCH */ 924 RCAR_GP_PIN(1, 19), 925 }; 926 static const unsigned int avb_avtp_match_mux[] = { 927 AVB_AVTP_MATCH_MARK, 928 }; 929 930 /* - CANFD0 ----------------------------------------------------------------- */ 931 static const unsigned int canfd0_data_a_pins[] = { 932 /* CANFD0_TX, CANFD0_RX */ 933 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), 934 }; 935 static const unsigned int canfd0_data_a_mux[] = { 936 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK, 937 }; 938 static const unsigned int canfd0_data_b_pins[] = { 939 /* CANFD0_TX, CANFD0_RX */ 940 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 941 }; 942 static const unsigned int canfd0_data_b_mux[] = { 943 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK, 944 }; 945 946 /* - CANFD1 ----------------------------------------------------------------- */ 947 static const unsigned int canfd1_data_pins[] = { 948 /* CANFD1_TX, CANFD1_RX */ 949 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 950 }; 951 static const unsigned int canfd1_data_mux[] = { 952 CANFD1_TX_MARK, CANFD1_RX_MARK, 953 }; 954 955 /* - CANFD Clock ------------------------------------------------------------ */ 956 static const unsigned int canfd_clk_a_pins[] = { 957 /* CANFD_CLK */ 958 RCAR_GP_PIN(1, 25), 959 }; 960 static const unsigned int canfd_clk_a_mux[] = { 961 CANFD_CLK_A_MARK, 962 }; 963 static const unsigned int canfd_clk_b_pins[] = { 964 /* CANFD_CLK */ 965 RCAR_GP_PIN(3, 8), 966 }; 967 static const unsigned int canfd_clk_b_mux[] = { 968 CANFD_CLK_B_MARK, 969 }; 970 971 /* - DU --------------------------------------------------------------------- */ 972 static const unsigned int du_rgb666_pins[] = { 973 /* DU_DR[7:2], DU_DG[7:2], DU_DB[7:2] */ 974 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), 975 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0), 976 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9), 977 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), 978 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15), 979 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12), 980 }; 981 static const unsigned int du_rgb666_mux[] = { 982 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, 983 DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK, 984 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, 985 DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK, 986 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, 987 DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK, 988 }; 989 static const unsigned int du_rgb888_pins[] = { 990 /* DU_DR[7:0], DU_DG[7:0], DU_DB[7:0] */ 991 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), 992 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0), 993 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), 994 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9), 995 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), 996 RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21), 997 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15), 998 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12), 999 RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23), 1000 }; 1001 static const unsigned int du_rgb888_mux[] = { 1002 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, 1003 DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK, 1004 DU_DR1_MARK, DU_DR0_MARK, 1005 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, 1006 DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK, 1007 DU_DG1_MARK, DU_DG0_MARK, 1008 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, 1009 DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK, 1010 DU_DB1_MARK, DU_DB0_MARK, 1011 }; 1012 static const unsigned int du_clk_out_pins[] = { 1013 /* DU_DOTCLKOUT */ 1014 RCAR_GP_PIN(0, 18), 1015 }; 1016 static const unsigned int du_clk_out_mux[] = { 1017 DU_DOTCLKOUT_MARK, 1018 }; 1019 static const unsigned int du_sync_pins[] = { 1020 /* DU_EXVSYNC/DU_VSYNC, DU_EXHSYNC/DU_HSYNC */ 1021 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), 1022 }; 1023 static const unsigned int du_sync_mux[] = { 1024 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK, 1025 }; 1026 static const unsigned int du_oddf_pins[] = { 1027 /* DU_EXODDF/DU_ODDF/DISP/CDE */ 1028 RCAR_GP_PIN(0, 21), 1029 }; 1030 static const unsigned int du_oddf_mux[] = { 1031 DU_EXODDF_DU_ODDF_DISP_CDE_MARK, 1032 }; 1033 static const unsigned int du_cde_pins[] = { 1034 /* DU_CDE */ 1035 RCAR_GP_PIN(1, 22), 1036 }; 1037 static const unsigned int du_cde_mux[] = { 1038 DU_CDE_MARK, 1039 }; 1040 static const unsigned int du_disp_pins[] = { 1041 /* DU_DISP */ 1042 RCAR_GP_PIN(1, 21), 1043 }; 1044 static const unsigned int du_disp_mux[] = { 1045 DU_DISP_MARK, 1046 }; 1047 1048 /* - GETHER ----------------------------------------------------------------- */ 1049 static const unsigned int gether_link_a_pins[] = { 1050 /* GETHER_LINK */ 1051 RCAR_GP_PIN(4, 24), 1052 }; 1053 static const unsigned int gether_link_a_mux[] = { 1054 GETHER_LINK_A_MARK, 1055 }; 1056 static const unsigned int gether_phy_int_a_pins[] = { 1057 /* GETHER_PHY_INT */ 1058 RCAR_GP_PIN(4, 23), 1059 }; 1060 static const unsigned int gether_phy_int_a_mux[] = { 1061 GETHER_PHY_INT_A_MARK, 1062 }; 1063 static const unsigned int gether_mdio_a_pins[] = { 1064 /* GETHER_MDC, GETHER_MDIO */ 1065 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), 1066 }; 1067 static const unsigned int gether_mdio_a_mux[] = { 1068 GETHER_MDC_A_MARK, GETHER_MDIO_A_MARK, 1069 }; 1070 static const unsigned int gether_link_b_pins[] = { 1071 /* GETHER_LINK */ 1072 RCAR_GP_PIN(0, 18), 1073 }; 1074 static const unsigned int gether_link_b_mux[] = { 1075 GETHER_LINK_B_MARK, 1076 }; 1077 static const unsigned int gether_phy_int_b_pins[] = { 1078 /* GETHER_PHY_INT */ 1079 RCAR_GP_PIN(0, 19), 1080 }; 1081 static const unsigned int gether_phy_int_b_mux[] = { 1082 GETHER_PHY_INT_B_MARK, 1083 }; 1084 static const unsigned int gether_mdio_b_mux[] = { 1085 GETHER_MDC_B_MARK, GETHER_MDIO_B_MARK, 1086 }; 1087 static const unsigned int gether_mdio_b_pins[] = { 1088 /* GETHER_MDC, GETHER_MDIO */ 1089 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), 1090 }; 1091 static const unsigned int gether_magic_pins[] = { 1092 /* GETHER_MAGIC */ 1093 RCAR_GP_PIN(4, 22), 1094 }; 1095 static const unsigned int gether_magic_mux[] = { 1096 GETHER_MAGIC_MARK, 1097 }; 1098 static const unsigned int gether_rgmii_pins[] = { 1099 /* 1100 * GETHER_TX_CTL, GETHER_TXC, 1101 * GETHER_TD0, GETHER_TD1, GETHER_TD2, GETHER_TD3, 1102 * GETHER_RX_CTL, GETHER_RXC, 1103 * GETHER_RD0, GETHER_RD1, GETHER_RD2, GETHER_RD3, 1104 */ 1105 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13), 1106 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15), 1107 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17), 1108 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7), 1109 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), 1110 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), 1111 }; 1112 static const unsigned int gether_rgmii_mux[] = { 1113 GETHER_TX_CTL_MARK, GETHER_TXC_MARK, 1114 GETHER_TD0_MARK, GETHER_TD1_MARK, 1115 GETHER_TD2_MARK, GETHER_TD3_MARK, 1116 GETHER_RX_CTL_MARK, GETHER_RXC_MARK, 1117 GETHER_RD0_MARK, AVB_RD1_MARK, 1118 GETHER_RD2_MARK, AVB_RD3_MARK, 1119 }; 1120 static const unsigned int gether_txcrefclk_pins[] = { 1121 /* GETHER_TXCREFCLK */ 1122 RCAR_GP_PIN(4, 18), 1123 }; 1124 static const unsigned int gether_txcrefclk_mux[] = { 1125 GETHER_TXCREFCLK_MARK, 1126 }; 1127 static const unsigned int gether_txcrefclk_mega_pins[] = { 1128 /* GETHER_TXCREFCLK_MEGA */ 1129 RCAR_GP_PIN(4, 19), 1130 }; 1131 static const unsigned int gether_txcrefclk_mega_mux[] = { 1132 GETHER_TXCREFCLK_MEGA_MARK, 1133 }; 1134 static const unsigned int gether_rmii_pins[] = { 1135 /* 1136 * GETHER_RMII_CRS_DV, GETHER_RMII_RX_ER, 1137 * GETHER_RMII_RXD0, GETHER_RMII_RXD1, 1138 * GETHER_RMII_TXD_EN, GETHER_RMII_TXD0, 1139 * GETHER_RMII_TXD1, GETHER_RMII_REFCLK 1140 */ 1141 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 1142 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 1143 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 1144 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 1145 }; 1146 static const unsigned int gether_rmii_mux[] = { 1147 GETHER_RMII_CRS_DV_MARK, GETHER_RMII_RX_ER_MARK, 1148 GETHER_RMII_RXD0_MARK, GETHER_RMII_RXD1_MARK, 1149 GETHER_RMII_TXD_EN_MARK, GETHER_RMII_TXD0_MARK, 1150 GETHER_RMII_TXD1_MARK, GETHER_RMII_REFCLK_MARK, 1151 }; 1152 1153 /* - HSCIF0 ----------------------------------------------------------------- */ 1154 static const unsigned int hscif0_data_a_pins[] = { 1155 /* HRX0, HTX0 */ 1156 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 15), 1157 }; 1158 static const unsigned int hscif0_data_a_mux[] = { 1159 HRX0_A_MARK, HTX0_A_MARK, 1160 }; 1161 static const unsigned int hscif0_clk_a_pins[] = { 1162 /* HSCK0 */ 1163 RCAR_GP_PIN(0, 12), 1164 }; 1165 static const unsigned int hscif0_clk_a_mux[] = { 1166 HSCK0_A_MARK, 1167 }; 1168 static const unsigned int hscif0_ctrl_a_pins[] = { 1169 /* HRTS0#, HCTS0# */ 1170 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14), 1171 }; 1172 static const unsigned int hscif0_ctrl_a_mux[] = { 1173 HRTS0_N_A_MARK, HCTS0_N_A_MARK, 1174 }; 1175 static const unsigned int hscif0_data_b_pins[] = { 1176 /* HRX0, HTX0 */ 1177 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), 1178 }; 1179 static const unsigned int hscif0_data_b_mux[] = { 1180 HRX0_B_MARK, HTX0_B_MARK, 1181 }; 1182 static const unsigned int hscif0_clk_b_pins[] = { 1183 /* HSCK0 */ 1184 RCAR_GP_PIN(4, 1), 1185 }; 1186 static const unsigned int hscif0_clk_b_mux[] = { 1187 HSCK0_B_MARK, 1188 }; 1189 static const unsigned int hscif0_ctrl_b_pins[] = { 1190 /* HRTS0#, HCTS0# */ 1191 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2), 1192 }; 1193 static const unsigned int hscif0_ctrl_b_mux[] = { 1194 HRTS0_N_B_MARK, HCTS0_N_B_MARK, 1195 }; 1196 1197 /* - HSCIF1 ----------------------------------------------------------------- */ 1198 static const unsigned int hscif1_data_pins[] = { 1199 /* HRX1, HTX1 */ 1200 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10), 1201 }; 1202 static const unsigned int hscif1_data_mux[] = { 1203 HRX1_MARK, HTX1_MARK, 1204 }; 1205 static const unsigned int hscif1_clk_pins[] = { 1206 /* HSCK1 */ 1207 RCAR_GP_PIN(2, 7), 1208 }; 1209 static const unsigned int hscif1_clk_mux[] = { 1210 HSCK1_MARK, 1211 }; 1212 static const unsigned int hscif1_ctrl_pins[] = { 1213 /* HRTS1#, HCTS1# */ 1214 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 1215 }; 1216 static const unsigned int hscif1_ctrl_mux[] = { 1217 HRTS1_N_MARK, HCTS1_N_MARK, 1218 }; 1219 1220 /* - HSCIF2 ----------------------------------------------------------------- */ 1221 static const unsigned int hscif2_data_pins[] = { 1222 /* HRX2, HTX2 */ 1223 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15), 1224 }; 1225 static const unsigned int hscif2_data_mux[] = { 1226 HRX2_MARK, HTX2_MARK, 1227 }; 1228 static const unsigned int hscif2_clk_pins[] = { 1229 /* HSCK2 */ 1230 RCAR_GP_PIN(2, 12), 1231 }; 1232 static const unsigned int hscif2_clk_mux[] = { 1233 HSCK2_MARK, 1234 }; 1235 static const unsigned int hscif2_ctrl_pins[] = { 1236 /* HRTS2#, HCTS2# */ 1237 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), 1238 }; 1239 static const unsigned int hscif2_ctrl_mux[] = { 1240 HRTS2_N_MARK, HCTS2_N_MARK, 1241 }; 1242 1243 /* - HSCIF3 ----------------------------------------------------------------- */ 1244 static const unsigned int hscif3_data_pins[] = { 1245 /* HRX3, HTX3 */ 1246 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), 1247 }; 1248 static const unsigned int hscif3_data_mux[] = { 1249 HRX3_MARK, HTX3_MARK, 1250 }; 1251 static const unsigned int hscif3_clk_pins[] = { 1252 /* HSCK3 */ 1253 RCAR_GP_PIN(2, 0), 1254 }; 1255 static const unsigned int hscif3_clk_mux[] = { 1256 HSCK3_MARK, 1257 }; 1258 static const unsigned int hscif3_ctrl_pins[] = { 1259 /* HRTS3#, HCTS3# */ 1260 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1), 1261 }; 1262 static const unsigned int hscif3_ctrl_mux[] = { 1263 HRTS3_N_MARK, HCTS3_N_MARK, 1264 }; 1265 1266 /* - I2C0 ------------------------------------------------------------------- */ 1267 static const unsigned int i2c0_pins[] = { 1268 /* SDA0, SCL0 */ 1269 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0), 1270 }; 1271 static const unsigned int i2c0_mux[] = { 1272 SDA0_MARK, SCL0_MARK, 1273 }; 1274 1275 /* - I2C1 ------------------------------------------------------------------- */ 1276 static const unsigned int i2c1_pins[] = { 1277 /* SDA1, SCL1 */ 1278 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2), 1279 }; 1280 static const unsigned int i2c1_mux[] = { 1281 SDA1_MARK, SCL1_MARK, 1282 }; 1283 1284 /* - I2C2 ------------------------------------------------------------------- */ 1285 static const unsigned int i2c2_pins[] = { 1286 /* SDA2, SCL2 */ 1287 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4), 1288 }; 1289 static const unsigned int i2c2_mux[] = { 1290 SDA2_MARK, SCL2_MARK, 1291 }; 1292 1293 /* - I2C3 ------------------------------------------------------------------- */ 1294 static const unsigned int i2c3_pins[] = { 1295 /* SDA3, SCL3 */ 1296 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 25), 1297 }; 1298 static const unsigned int i2c3_mux[] = { 1299 SDA3_MARK, SCL3_MARK, 1300 }; 1301 1302 /* - I2C4 ------------------------------------------------------------------- */ 1303 static const unsigned int i2c4_pins[] = { 1304 /* SDA4, SCL4 */ 1305 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15), 1306 }; 1307 static const unsigned int i2c4_mux[] = { 1308 SDA4_MARK, SCL4_MARK, 1309 }; 1310 1311 /* - I2C5 ------------------------------------------------------------------- */ 1312 static const unsigned int i2c5_pins[] = { 1313 /* SDA5, SCL5 */ 1314 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8), 1315 }; 1316 static const unsigned int i2c5_mux[] = { 1317 SDA5_MARK, SCL5_MARK, 1318 }; 1319 1320 /* - INTC-EX ---------------------------------------------------------------- */ 1321 static const unsigned int intc_ex_irq0_pins[] = { 1322 /* IRQ0 */ 1323 RCAR_GP_PIN(1, 0), 1324 }; 1325 static const unsigned int intc_ex_irq0_mux[] = { 1326 IRQ0_MARK, 1327 }; 1328 static const unsigned int intc_ex_irq1_pins[] = { 1329 /* IRQ1 */ 1330 RCAR_GP_PIN(0, 12), 1331 }; 1332 static const unsigned int intc_ex_irq1_mux[] = { 1333 IRQ1_MARK, 1334 }; 1335 static const unsigned int intc_ex_irq2_pins[] = { 1336 /* IRQ2 */ 1337 RCAR_GP_PIN(0, 13), 1338 }; 1339 static const unsigned int intc_ex_irq2_mux[] = { 1340 IRQ2_MARK, 1341 }; 1342 static const unsigned int intc_ex_irq3_pins[] = { 1343 /* IRQ3 */ 1344 RCAR_GP_PIN(0, 14), 1345 }; 1346 static const unsigned int intc_ex_irq3_mux[] = { 1347 IRQ3_MARK, 1348 }; 1349 static const unsigned int intc_ex_irq4_pins[] = { 1350 /* IRQ4 */ 1351 RCAR_GP_PIN(2, 17), 1352 }; 1353 static const unsigned int intc_ex_irq4_mux[] = { 1354 IRQ4_MARK, 1355 }; 1356 static const unsigned int intc_ex_irq5_pins[] = { 1357 /* IRQ5 */ 1358 RCAR_GP_PIN(2, 18), 1359 }; 1360 static const unsigned int intc_ex_irq5_mux[] = { 1361 IRQ5_MARK, 1362 }; 1363 1364 /* - MMC -------------------------------------------------------------------- */ 1365 static const unsigned int mmc_data_pins[] = { 1366 /* MMC_D[0:7] */ 1367 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 1368 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 1369 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), 1370 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), 1371 }; 1372 static const unsigned int mmc_data_mux[] = { 1373 MMC_D0_MARK, MMC_D1_MARK, 1374 MMC_D2_MARK, MMC_D3_MARK, 1375 MMC_D4_MARK, MMC_D5_MARK, 1376 MMC_D6_MARK, MMC_D7_MARK, 1377 }; 1378 static const unsigned int mmc_ctrl_pins[] = { 1379 /* MMC_CLK, MMC_CMD */ 1380 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 7), 1381 }; 1382 static const unsigned int mmc_ctrl_mux[] = { 1383 MMC_CLK_MARK, MMC_CMD_MARK, 1384 }; 1385 static const unsigned int mmc_cd_pins[] = { 1386 /* MMC_CD */ 1387 RCAR_GP_PIN(3, 5), 1388 }; 1389 static const unsigned int mmc_cd_mux[] = { 1390 MMC_CD_MARK, 1391 }; 1392 static const unsigned int mmc_wp_pins[] = { 1393 /* MMC_WP */ 1394 RCAR_GP_PIN(3, 4), 1395 }; 1396 static const unsigned int mmc_wp_mux[] = { 1397 MMC_WP_MARK, 1398 }; 1399 static const unsigned int mmc_ds_pins[] = { 1400 /* MMC_DS */ 1401 RCAR_GP_PIN(3, 6), 1402 }; 1403 static const unsigned int mmc_ds_mux[] = { 1404 MMC_DS_MARK, 1405 }; 1406 1407 /* - MSIOF0 ----------------------------------------------------------------- */ 1408 static const unsigned int msiof0_clk_pins[] = { 1409 /* MSIOF0_SCK */ 1410 RCAR_GP_PIN(2, 21), 1411 }; 1412 static const unsigned int msiof0_clk_mux[] = { 1413 MSIOF0_SCK_MARK, 1414 }; 1415 static const unsigned int msiof0_sync_pins[] = { 1416 /* MSIOF0_SYNC */ 1417 RCAR_GP_PIN(2, 22), 1418 }; 1419 static const unsigned int msiof0_sync_mux[] = { 1420 MSIOF0_SYNC_MARK, 1421 }; 1422 static const unsigned int msiof0_ss1_pins[] = { 1423 /* MSIOF0_SS1 */ 1424 RCAR_GP_PIN(2, 23), 1425 }; 1426 static const unsigned int msiof0_ss1_mux[] = { 1427 MSIOF0_SS1_MARK, 1428 }; 1429 static const unsigned int msiof0_ss2_pins[] = { 1430 /* MSIOF0_SS2 */ 1431 RCAR_GP_PIN(2, 24), 1432 }; 1433 static const unsigned int msiof0_ss2_mux[] = { 1434 MSIOF0_SS2_MARK, 1435 }; 1436 static const unsigned int msiof0_txd_pins[] = { 1437 /* MSIOF0_TXD */ 1438 RCAR_GP_PIN(2, 20), 1439 }; 1440 static const unsigned int msiof0_txd_mux[] = { 1441 MSIOF0_TXD_MARK, 1442 }; 1443 static const unsigned int msiof0_rxd_pins[] = { 1444 /* MSIOF0_RXD */ 1445 RCAR_GP_PIN(2, 19), 1446 }; 1447 static const unsigned int msiof0_rxd_mux[] = { 1448 MSIOF0_RXD_MARK, 1449 }; 1450 1451 /* - MSIOF1 ----------------------------------------------------------------- */ 1452 static const unsigned int msiof1_clk_pins[] = { 1453 /* MSIOF1_SCK */ 1454 RCAR_GP_PIN(3, 2), 1455 }; 1456 static const unsigned int msiof1_clk_mux[] = { 1457 MSIOF1_SCK_MARK, 1458 }; 1459 static const unsigned int msiof1_sync_pins[] = { 1460 /* MSIOF1_SYNC */ 1461 RCAR_GP_PIN(3, 3), 1462 }; 1463 static const unsigned int msiof1_sync_mux[] = { 1464 MSIOF1_SYNC_MARK, 1465 }; 1466 static const unsigned int msiof1_ss1_pins[] = { 1467 /* MSIOF1_SS1 */ 1468 RCAR_GP_PIN(3, 4), 1469 }; 1470 static const unsigned int msiof1_ss1_mux[] = { 1471 MSIOF1_SS1_MARK, 1472 }; 1473 static const unsigned int msiof1_ss2_pins[] = { 1474 /* MSIOF1_SS2 */ 1475 RCAR_GP_PIN(3, 5), 1476 }; 1477 static const unsigned int msiof1_ss2_mux[] = { 1478 MSIOF1_SS2_MARK, 1479 }; 1480 static const unsigned int msiof1_txd_pins[] = { 1481 /* MSIOF1_TXD */ 1482 RCAR_GP_PIN(3, 1), 1483 }; 1484 static const unsigned int msiof1_txd_mux[] = { 1485 MSIOF1_TXD_MARK, 1486 }; 1487 static const unsigned int msiof1_rxd_pins[] = { 1488 /* MSIOF1_RXD */ 1489 RCAR_GP_PIN(3, 0), 1490 }; 1491 static const unsigned int msiof1_rxd_mux[] = { 1492 MSIOF1_RXD_MARK, 1493 }; 1494 1495 /* - MSIOF2 ----------------------------------------------------------------- */ 1496 static const unsigned int msiof2_clk_pins[] = { 1497 /* MSIOF2_SCK */ 1498 RCAR_GP_PIN(2, 0), 1499 }; 1500 static const unsigned int msiof2_clk_mux[] = { 1501 MSIOF2_SCK_MARK, 1502 }; 1503 static const unsigned int msiof2_sync_pins[] = { 1504 /* MSIOF2_SYNC */ 1505 RCAR_GP_PIN(2, 3), 1506 }; 1507 static const unsigned int msiof2_sync_mux[] = { 1508 MSIOF2_SYNC_MARK, 1509 }; 1510 static const unsigned int msiof2_ss1_pins[] = { 1511 /* MSIOF2_SS1 */ 1512 RCAR_GP_PIN(2, 4), 1513 }; 1514 static const unsigned int msiof2_ss1_mux[] = { 1515 MSIOF2_SS1_MARK, 1516 }; 1517 static const unsigned int msiof2_ss2_pins[] = { 1518 /* MSIOF2_SS2 */ 1519 RCAR_GP_PIN(2, 5), 1520 }; 1521 static const unsigned int msiof2_ss2_mux[] = { 1522 MSIOF2_SS2_MARK, 1523 }; 1524 static const unsigned int msiof2_txd_pins[] = { 1525 /* MSIOF2_TXD */ 1526 RCAR_GP_PIN(2, 2), 1527 }; 1528 static const unsigned int msiof2_txd_mux[] = { 1529 MSIOF2_TXD_MARK, 1530 }; 1531 static const unsigned int msiof2_rxd_pins[] = { 1532 /* MSIOF2_RXD */ 1533 RCAR_GP_PIN(2, 1), 1534 }; 1535 static const unsigned int msiof2_rxd_mux[] = { 1536 MSIOF2_RXD_MARK, 1537 }; 1538 1539 /* - MSIOF3 ----------------------------------------------------------------- */ 1540 static const unsigned int msiof3_clk_pins[] = { 1541 /* MSIOF3_SCK */ 1542 RCAR_GP_PIN(0, 20), 1543 }; 1544 static const unsigned int msiof3_clk_mux[] = { 1545 MSIOF3_SCK_MARK, 1546 }; 1547 static const unsigned int msiof3_sync_pins[] = { 1548 /* MSIOF3_SYNC */ 1549 RCAR_GP_PIN(0, 21), 1550 }; 1551 static const unsigned int msiof3_sync_mux[] = { 1552 MSIOF3_SYNC_MARK, 1553 }; 1554 static const unsigned int msiof3_ss1_pins[] = { 1555 /* MSIOF3_SS1 */ 1556 RCAR_GP_PIN(0, 18), 1557 }; 1558 static const unsigned int msiof3_ss1_mux[] = { 1559 MSIOF3_SS1_MARK, 1560 }; 1561 static const unsigned int msiof3_ss2_pins[] = { 1562 /* MSIOF3_SS2 */ 1563 RCAR_GP_PIN(0, 19), 1564 }; 1565 static const unsigned int msiof3_ss2_mux[] = { 1566 MSIOF3_SS2_MARK, 1567 }; 1568 static const unsigned int msiof3_txd_pins[] = { 1569 /* MSIOF3_TXD */ 1570 RCAR_GP_PIN(0, 17), 1571 }; 1572 static const unsigned int msiof3_txd_mux[] = { 1573 MSIOF3_TXD_MARK, 1574 }; 1575 static const unsigned int msiof3_rxd_pins[] = { 1576 /* MSIOF3_RXD */ 1577 RCAR_GP_PIN(0, 16), 1578 }; 1579 static const unsigned int msiof3_rxd_mux[] = { 1580 MSIOF3_RXD_MARK, 1581 }; 1582 1583 /* - PWM0 ------------------------------------------------------------------- */ 1584 static const unsigned int pwm0_a_pins[] = { 1585 /* PWM0 */ 1586 RCAR_GP_PIN(0, 15), 1587 }; 1588 static const unsigned int pwm0_a_mux[] = { 1589 PWM0_A_MARK, 1590 }; 1591 static const unsigned int pwm0_b_pins[] = { 1592 /* PWM0 */ 1593 RCAR_GP_PIN(1, 21), 1594 }; 1595 static const unsigned int pwm0_b_mux[] = { 1596 PWM0_B_MARK, 1597 }; 1598 1599 /* - PWM1 ------------------------------------------------------------------- */ 1600 static const unsigned int pwm1_a_pins[] = { 1601 /* PWM1 */ 1602 RCAR_GP_PIN(2, 13), 1603 }; 1604 static const unsigned int pwm1_a_mux[] = { 1605 PWM1_A_MARK, 1606 }; 1607 static const unsigned int pwm1_b_pins[] = { 1608 /* PWM1 */ 1609 RCAR_GP_PIN(1, 22), 1610 }; 1611 static const unsigned int pwm1_b_mux[] = { 1612 PWM1_B_MARK, 1613 }; 1614 1615 /* - PWM2 ------------------------------------------------------------------- */ 1616 static const unsigned int pwm2_a_pins[] = { 1617 /* PWM2 */ 1618 RCAR_GP_PIN(2, 14), 1619 }; 1620 static const unsigned int pwm2_a_mux[] = { 1621 PWM2_A_MARK, 1622 }; 1623 static const unsigned int pwm2_b_pins[] = { 1624 /* PWM2 */ 1625 RCAR_GP_PIN(1, 23), 1626 }; 1627 static const unsigned int pwm2_b_mux[] = { 1628 PWM2_B_MARK, 1629 }; 1630 1631 /* - PWM3 ------------------------------------------------------------------- */ 1632 static const unsigned int pwm3_a_pins[] = { 1633 /* PWM3 */ 1634 RCAR_GP_PIN(2, 15), 1635 }; 1636 static const unsigned int pwm3_a_mux[] = { 1637 PWM3_A_MARK, 1638 }; 1639 static const unsigned int pwm3_b_pins[] = { 1640 /* PWM3 */ 1641 RCAR_GP_PIN(1, 24), 1642 }; 1643 static const unsigned int pwm3_b_mux[] = { 1644 PWM3_B_MARK, 1645 }; 1646 1647 /* - PWM4 ------------------------------------------------------------------- */ 1648 static const unsigned int pwm4_a_pins[] = { 1649 /* PWM4 */ 1650 RCAR_GP_PIN(2, 16), 1651 }; 1652 static const unsigned int pwm4_a_mux[] = { 1653 PWM4_A_MARK, 1654 }; 1655 static const unsigned int pwm4_b_pins[] = { 1656 /* PWM4 */ 1657 RCAR_GP_PIN(1, 25), 1658 }; 1659 static const unsigned int pwm4_b_mux[] = { 1660 PWM4_B_MARK, 1661 }; 1662 1663 /* - QSPI0 ------------------------------------------------------------------ */ 1664 static const unsigned int qspi0_ctrl_pins[] = { 1665 /* SPCLK, SSL */ 1666 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 5), 1667 }; 1668 static const unsigned int qspi0_ctrl_mux[] = { 1669 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, 1670 }; 1671 1672 /* - QSPI1 ------------------------------------------------------------------ */ 1673 static const unsigned int qspi1_ctrl_pins[] = { 1674 /* SPCLK, SSL */ 1675 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 11), 1676 }; 1677 static const unsigned int qspi1_ctrl_mux[] = { 1678 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, 1679 }; 1680 1681 /* - RPC -------------------------------------------------------------------- */ 1682 static const unsigned int rpc_clk_pins[] = { 1683 /* Octal-SPI flash: C/SCLK */ 1684 /* HyperFlash: CK, CK# */ 1685 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6), 1686 }; 1687 static const unsigned int rpc_clk_mux[] = { 1688 QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK, 1689 }; 1690 static const unsigned int rpc_ctrl_pins[] = { 1691 /* Octal-SPI flash: S#/CS, DQS */ 1692 /* HyperFlash: CS#, RDS */ 1693 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11), 1694 }; 1695 static const unsigned int rpc_ctrl_mux[] = { 1696 QSPI0_SSL_MARK, QSPI1_SSL_MARK, 1697 }; 1698 static const unsigned int rpc_data_pins[] = { 1699 /* DQ[0:7] */ 1700 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 1701 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), 1702 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), 1703 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), 1704 }; 1705 static const unsigned int rpc_data_mux[] = { 1706 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, 1707 QSPI0_IO2_MARK, QSPI0_IO3_MARK, 1708 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, 1709 QSPI1_IO2_MARK, QSPI1_IO3_MARK, 1710 }; 1711 static const unsigned int rpc_reset_pins[] = { 1712 /* RPC_RESET# */ 1713 RCAR_GP_PIN(5, 12), 1714 }; 1715 static const unsigned int rpc_reset_mux[] = { 1716 RPC_RESET_N_MARK, 1717 }; 1718 static const unsigned int rpc_int_pins[] = { 1719 /* RPC_INT# */ 1720 RCAR_GP_PIN(5, 14), 1721 }; 1722 static const unsigned int rpc_int_mux[] = { 1723 RPC_INT_N_MARK, 1724 }; 1725 static const unsigned int rpc_wp_pins[] = { 1726 /* RPC_WP# */ 1727 RCAR_GP_PIN(5, 13), 1728 }; 1729 static const unsigned int rpc_wp_mux[] = { 1730 RPC_WP_N_MARK, 1731 }; 1732 1733 /* - SCIF0 ------------------------------------------------------------------ */ 1734 static const unsigned int scif0_data_pins[] = { 1735 /* RX0, TX0 */ 1736 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), 1737 }; 1738 static const unsigned int scif0_data_mux[] = { 1739 RX0_MARK, TX0_MARK, 1740 }; 1741 static const unsigned int scif0_clk_pins[] = { 1742 /* SCK0 */ 1743 RCAR_GP_PIN(4, 1), 1744 }; 1745 static const unsigned int scif0_clk_mux[] = { 1746 SCK0_MARK, 1747 }; 1748 static const unsigned int scif0_ctrl_pins[] = { 1749 /* RTS0#, CTS0# */ 1750 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2), 1751 }; 1752 static const unsigned int scif0_ctrl_mux[] = { 1753 RTS0_N_MARK, CTS0_N_MARK, 1754 }; 1755 1756 /* - SCIF1 ------------------------------------------------------------------ */ 1757 static const unsigned int scif1_data_a_pins[] = { 1758 /* RX1, TX1 */ 1759 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 1760 }; 1761 static const unsigned int scif1_data_a_mux[] = { 1762 RX1_A_MARK, TX1_A_MARK, 1763 }; 1764 static const unsigned int scif1_clk_pins[] = { 1765 /* SCK1 */ 1766 RCAR_GP_PIN(2, 5), 1767 }; 1768 static const unsigned int scif1_clk_mux[] = { 1769 SCK1_MARK, 1770 }; 1771 static const unsigned int scif1_ctrl_pins[] = { 1772 /* RTS1#, CTS1# */ 1773 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10), 1774 }; 1775 static const unsigned int scif1_ctrl_mux[] = { 1776 RTS1_N_MARK, CTS1_N_MARK, 1777 }; 1778 static const unsigned int scif1_data_b_pins[] = { 1779 /* RX1, TX1 */ 1780 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23), 1781 }; 1782 static const unsigned int scif1_data_b_mux[] = { 1783 RX1_B_MARK, TX1_B_MARK, 1784 }; 1785 1786 /* - SCIF3 ------------------------------------------------------------------ */ 1787 static const unsigned int scif3_data_pins[] = { 1788 /* RX3, TX3 */ 1789 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), 1790 }; 1791 static const unsigned int scif3_data_mux[] = { 1792 RX3_MARK, TX3_MARK, 1793 }; 1794 static const unsigned int scif3_clk_pins[] = { 1795 /* SCK3 */ 1796 RCAR_GP_PIN(2, 0), 1797 }; 1798 static const unsigned int scif3_clk_mux[] = { 1799 SCK3_MARK, 1800 }; 1801 static const unsigned int scif3_ctrl_pins[] = { 1802 /* RTS3#, CTS3# */ 1803 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), 1804 }; 1805 static const unsigned int scif3_ctrl_mux[] = { 1806 RTS3_N_MARK, CTS3_N_MARK, 1807 }; 1808 1809 /* - SCIF4 ------------------------------------------------------------------ */ 1810 static const unsigned int scif4_data_pins[] = { 1811 /* RX4, TX4 */ 1812 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2), 1813 }; 1814 static const unsigned int scif4_data_mux[] = { 1815 RX4_MARK, TX4_MARK, 1816 }; 1817 static const unsigned int scif4_clk_pins[] = { 1818 /* SCK4 */ 1819 RCAR_GP_PIN(0, 0), 1820 }; 1821 static const unsigned int scif4_clk_mux[] = { 1822 SCK4_MARK, 1823 }; 1824 static const unsigned int scif4_ctrl_pins[] = { 1825 /* RTS4#, CTS4# */ 1826 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), 1827 }; 1828 static const unsigned int scif4_ctrl_mux[] = { 1829 RTS4_N_MARK, CTS4_N_MARK, 1830 }; 1831 1832 /* - SCIF Clock ------------------------------------------------------------- */ 1833 static const unsigned int scif_clk_a_pins[] = { 1834 /* SCIF_CLK */ 1835 RCAR_GP_PIN(0, 10), 1836 }; 1837 static const unsigned int scif_clk_a_mux[] = { 1838 SCIF_CLK_A_MARK, 1839 }; 1840 static const unsigned int scif_clk_b_pins[] = { 1841 /* SCIF_CLK */ 1842 RCAR_GP_PIN(1, 25), 1843 }; 1844 static const unsigned int scif_clk_b_mux[] = { 1845 SCIF_CLK_B_MARK, 1846 }; 1847 1848 /* - TMU -------------------------------------------------------------------- */ 1849 static const unsigned int tmu_tclk1_a_pins[] = { 1850 /* TCLK1 */ 1851 RCAR_GP_PIN(3, 13), 1852 }; 1853 static const unsigned int tmu_tclk1_a_mux[] = { 1854 TCLK1_A_MARK, 1855 }; 1856 static const unsigned int tmu_tclk1_b_pins[] = { 1857 /* TCLK1 */ 1858 RCAR_GP_PIN(1, 23), 1859 }; 1860 static const unsigned int tmu_tclk1_b_mux[] = { 1861 TCLK1_B_MARK, 1862 }; 1863 static const unsigned int tmu_tclk2_a_pins[] = { 1864 /* TCLK2 */ 1865 RCAR_GP_PIN(3, 14), 1866 }; 1867 static const unsigned int tmu_tclk2_a_mux[] = { 1868 TCLK2_A_MARK, 1869 }; 1870 static const unsigned int tmu_tclk2_b_pins[] = { 1871 /* TCLK2 */ 1872 RCAR_GP_PIN(1, 24), 1873 }; 1874 static const unsigned int tmu_tclk2_b_mux[] = { 1875 TCLK2_B_MARK, 1876 }; 1877 1878 /* - TPU ------------------------------------------------------------------- */ 1879 static const unsigned int tpu_to0_pins[] = { 1880 /* TPU0TO0 */ 1881 RCAR_GP_PIN(1, 19), 1882 }; 1883 static const unsigned int tpu_to0_mux[] = { 1884 TPU0TO0_MARK, 1885 }; 1886 static const unsigned int tpu_to1_pins[] = { 1887 /* TPU0TO1 */ 1888 RCAR_GP_PIN(1, 20), 1889 }; 1890 static const unsigned int tpu_to1_mux[] = { 1891 TPU0TO1_MARK, 1892 }; 1893 static const unsigned int tpu_to2_pins[] = { 1894 /* TPU0TO2 */ 1895 RCAR_GP_PIN(4, 2), 1896 }; 1897 static const unsigned int tpu_to2_mux[] = { 1898 TPU0TO2_MARK, 1899 }; 1900 static const unsigned int tpu_to3_pins[] = { 1901 /* TPU0TO3 */ 1902 RCAR_GP_PIN(4, 3), 1903 }; 1904 static const unsigned int tpu_to3_mux[] = { 1905 TPU0TO3_MARK, 1906 }; 1907 1908 /* - VIN0 ------------------------------------------------------------------- */ 1909 static const unsigned int vin0_data_pins[] = { 1910 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 1911 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 1912 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 1913 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), 1914 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), 1915 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), 1916 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), 1917 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), 1918 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), 1919 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24), 1920 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26), 1921 RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28), 1922 }; 1923 static const unsigned int vin0_data_mux[] = { 1924 VI0_DATA0_MARK, VI0_DATA1_MARK, 1925 VI0_DATA2_MARK, VI0_DATA3_MARK, 1926 VI0_DATA4_MARK, VI0_DATA5_MARK, 1927 VI0_DATA6_MARK, VI0_DATA7_MARK, 1928 VI0_DATA8_MARK, VI0_DATA9_MARK, 1929 VI0_DATA10_MARK, VI0_DATA11_MARK, 1930 VI0_DATA12_MARK, VI0_DATA13_MARK, 1931 VI0_DATA14_MARK, VI0_DATA15_MARK, 1932 VI0_DATA16_MARK, VI0_DATA17_MARK, 1933 VI0_DATA18_MARK, VI0_DATA19_MARK, 1934 VI0_DATA20_MARK, VI0_DATA21_MARK, 1935 VI0_DATA22_MARK, VI0_DATA23_MARK, 1936 }; 1937 static const unsigned int vin0_data18_pins[] = { 1938 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 1939 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 1940 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), 1941 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), 1942 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), 1943 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), 1944 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24), 1945 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26), 1946 RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28), 1947 }; 1948 static const unsigned int vin0_data18_mux[] = { 1949 VI0_DATA2_MARK, VI0_DATA3_MARK, 1950 VI0_DATA4_MARK, VI0_DATA5_MARK, 1951 VI0_DATA6_MARK, VI0_DATA7_MARK, 1952 VI0_DATA10_MARK, VI0_DATA11_MARK, 1953 VI0_DATA12_MARK, VI0_DATA13_MARK, 1954 VI0_DATA14_MARK, VI0_DATA15_MARK, 1955 VI0_DATA18_MARK, VI0_DATA19_MARK, 1956 VI0_DATA20_MARK, VI0_DATA21_MARK, 1957 VI0_DATA22_MARK, VI0_DATA23_MARK, 1958 }; 1959 static const unsigned int vin0_sync_pins[] = { 1960 /* VI0_VSYNC#, VI0_HSYNC# */ 1961 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2), 1962 }; 1963 static const unsigned int vin0_sync_mux[] = { 1964 VI0_VSYNC_N_MARK, VI0_HSYNC_N_MARK, 1965 }; 1966 static const unsigned int vin0_field_pins[] = { 1967 /* VI0_FIELD */ 1968 RCAR_GP_PIN(2, 16), 1969 }; 1970 static const unsigned int vin0_field_mux[] = { 1971 VI0_FIELD_MARK, 1972 }; 1973 static const unsigned int vin0_clkenb_pins[] = { 1974 /* VI0_CLKENB */ 1975 RCAR_GP_PIN(2, 1), 1976 }; 1977 static const unsigned int vin0_clkenb_mux[] = { 1978 VI0_CLKENB_MARK, 1979 }; 1980 static const unsigned int vin0_clk_pins[] = { 1981 /* VI0_CLK */ 1982 RCAR_GP_PIN(2, 0), 1983 }; 1984 static const unsigned int vin0_clk_mux[] = { 1985 VI0_CLK_MARK, 1986 }; 1987 1988 /* - VIN1 ------------------------------------------------------------------- */ 1989 static const unsigned int vin1_data_pins[] = { 1990 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), 1991 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 1992 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 1993 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 1994 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), 1995 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), 1996 }; 1997 static const unsigned int vin1_data_mux[] = { 1998 VI1_DATA0_MARK, VI1_DATA1_MARK, 1999 VI1_DATA2_MARK, VI1_DATA3_MARK, 2000 VI1_DATA4_MARK, VI1_DATA5_MARK, 2001 VI1_DATA6_MARK, VI1_DATA7_MARK, 2002 VI1_DATA8_MARK, VI1_DATA9_MARK, 2003 VI1_DATA10_MARK, VI1_DATA11_MARK, 2004 }; 2005 static const unsigned int vin1_sync_pins[] = { 2006 /* VI1_VSYNC#, VI1_HSYNC# */ 2007 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2), 2008 }; 2009 static const unsigned int vin1_sync_mux[] = { 2010 VI1_VSYNC_N_MARK, VI1_HSYNC_N_MARK, 2011 }; 2012 static const unsigned int vin1_field_pins[] = { 2013 /* VI1_FIELD */ 2014 RCAR_GP_PIN(3, 16), 2015 }; 2016 static const unsigned int vin1_field_mux[] = { 2017 VI1_FIELD_MARK, 2018 }; 2019 static const unsigned int vin1_clkenb_pins[] = { 2020 /* VI1_CLKENB */ 2021 RCAR_GP_PIN(3, 1), 2022 }; 2023 static const unsigned int vin1_clkenb_mux[] = { 2024 VI1_CLKENB_MARK, 2025 }; 2026 static const unsigned int vin1_clk_pins[] = { 2027 /* VI1_CLK */ 2028 RCAR_GP_PIN(3, 0), 2029 }; 2030 static const unsigned int vin1_clk_mux[] = { 2031 VI1_CLK_MARK, 2032 }; 2033 2034 static const struct sh_pfc_pin_group pinmux_groups[] = { 2035 SH_PFC_PIN_GROUP(avb_link), 2036 SH_PFC_PIN_GROUP(avb_magic), 2037 SH_PFC_PIN_GROUP(avb_phy_int), 2038 SH_PFC_PIN_GROUP(avb_mdio), 2039 SH_PFC_PIN_GROUP(avb_rgmii), 2040 SH_PFC_PIN_GROUP(avb_txcrefclk), 2041 SH_PFC_PIN_GROUP(avb_avtp_pps), 2042 SH_PFC_PIN_GROUP(avb_avtp_capture), 2043 SH_PFC_PIN_GROUP(avb_avtp_match), 2044 SH_PFC_PIN_GROUP(canfd0_data_a), 2045 SH_PFC_PIN_GROUP(canfd0_data_b), 2046 SH_PFC_PIN_GROUP(canfd1_data), 2047 SH_PFC_PIN_GROUP(canfd_clk_a), 2048 SH_PFC_PIN_GROUP(canfd_clk_b), 2049 SH_PFC_PIN_GROUP(du_rgb666), 2050 SH_PFC_PIN_GROUP(du_rgb888), 2051 SH_PFC_PIN_GROUP(du_clk_out), 2052 SH_PFC_PIN_GROUP(du_sync), 2053 SH_PFC_PIN_GROUP(du_oddf), 2054 SH_PFC_PIN_GROUP(du_cde), 2055 SH_PFC_PIN_GROUP(du_disp), 2056 SH_PFC_PIN_GROUP(gether_link_a), 2057 SH_PFC_PIN_GROUP(gether_phy_int_a), 2058 SH_PFC_PIN_GROUP(gether_mdio_a), 2059 SH_PFC_PIN_GROUP(gether_link_b), 2060 SH_PFC_PIN_GROUP(gether_phy_int_b), 2061 SH_PFC_PIN_GROUP(gether_mdio_b), 2062 SH_PFC_PIN_GROUP(gether_magic), 2063 SH_PFC_PIN_GROUP(gether_rgmii), 2064 SH_PFC_PIN_GROUP(gether_txcrefclk), 2065 SH_PFC_PIN_GROUP(gether_txcrefclk_mega), 2066 SH_PFC_PIN_GROUP(gether_rmii), 2067 SH_PFC_PIN_GROUP(hscif0_data_a), 2068 SH_PFC_PIN_GROUP(hscif0_clk_a), 2069 SH_PFC_PIN_GROUP(hscif0_ctrl_a), 2070 SH_PFC_PIN_GROUP(hscif0_data_b), 2071 SH_PFC_PIN_GROUP(hscif0_clk_b), 2072 SH_PFC_PIN_GROUP(hscif0_ctrl_b), 2073 SH_PFC_PIN_GROUP(hscif1_data), 2074 SH_PFC_PIN_GROUP(hscif1_clk), 2075 SH_PFC_PIN_GROUP(hscif1_ctrl), 2076 SH_PFC_PIN_GROUP(hscif2_data), 2077 SH_PFC_PIN_GROUP(hscif2_clk), 2078 SH_PFC_PIN_GROUP(hscif2_ctrl), 2079 SH_PFC_PIN_GROUP(hscif3_data), 2080 SH_PFC_PIN_GROUP(hscif3_clk), 2081 SH_PFC_PIN_GROUP(hscif3_ctrl), 2082 SH_PFC_PIN_GROUP(i2c0), 2083 SH_PFC_PIN_GROUP(i2c1), 2084 SH_PFC_PIN_GROUP(i2c2), 2085 SH_PFC_PIN_GROUP(i2c3), 2086 SH_PFC_PIN_GROUP(i2c4), 2087 SH_PFC_PIN_GROUP(i2c5), 2088 SH_PFC_PIN_GROUP(intc_ex_irq0), 2089 SH_PFC_PIN_GROUP(intc_ex_irq1), 2090 SH_PFC_PIN_GROUP(intc_ex_irq2), 2091 SH_PFC_PIN_GROUP(intc_ex_irq3), 2092 SH_PFC_PIN_GROUP(intc_ex_irq4), 2093 SH_PFC_PIN_GROUP(intc_ex_irq5), 2094 BUS_DATA_PIN_GROUP(mmc_data, 1), 2095 BUS_DATA_PIN_GROUP(mmc_data, 4), 2096 BUS_DATA_PIN_GROUP(mmc_data, 8), 2097 SH_PFC_PIN_GROUP(mmc_ctrl), 2098 SH_PFC_PIN_GROUP(mmc_cd), 2099 SH_PFC_PIN_GROUP(mmc_wp), 2100 SH_PFC_PIN_GROUP(mmc_ds), 2101 SH_PFC_PIN_GROUP(msiof0_clk), 2102 SH_PFC_PIN_GROUP(msiof0_sync), 2103 SH_PFC_PIN_GROUP(msiof0_ss1), 2104 SH_PFC_PIN_GROUP(msiof0_ss2), 2105 SH_PFC_PIN_GROUP(msiof0_txd), 2106 SH_PFC_PIN_GROUP(msiof0_rxd), 2107 SH_PFC_PIN_GROUP(msiof1_clk), 2108 SH_PFC_PIN_GROUP(msiof1_sync), 2109 SH_PFC_PIN_GROUP(msiof1_ss1), 2110 SH_PFC_PIN_GROUP(msiof1_ss2), 2111 SH_PFC_PIN_GROUP(msiof1_txd), 2112 SH_PFC_PIN_GROUP(msiof1_rxd), 2113 SH_PFC_PIN_GROUP(msiof2_clk), 2114 SH_PFC_PIN_GROUP(msiof2_sync), 2115 SH_PFC_PIN_GROUP(msiof2_ss1), 2116 SH_PFC_PIN_GROUP(msiof2_ss2), 2117 SH_PFC_PIN_GROUP(msiof2_txd), 2118 SH_PFC_PIN_GROUP(msiof2_rxd), 2119 SH_PFC_PIN_GROUP(msiof3_clk), 2120 SH_PFC_PIN_GROUP(msiof3_sync), 2121 SH_PFC_PIN_GROUP(msiof3_ss1), 2122 SH_PFC_PIN_GROUP(msiof3_ss2), 2123 SH_PFC_PIN_GROUP(msiof3_txd), 2124 SH_PFC_PIN_GROUP(msiof3_rxd), 2125 SH_PFC_PIN_GROUP(pwm0_a), 2126 SH_PFC_PIN_GROUP(pwm0_b), 2127 SH_PFC_PIN_GROUP(pwm1_a), 2128 SH_PFC_PIN_GROUP(pwm1_b), 2129 SH_PFC_PIN_GROUP(pwm2_a), 2130 SH_PFC_PIN_GROUP(pwm2_b), 2131 SH_PFC_PIN_GROUP(pwm3_a), 2132 SH_PFC_PIN_GROUP(pwm3_b), 2133 SH_PFC_PIN_GROUP(pwm4_a), 2134 SH_PFC_PIN_GROUP(pwm4_b), 2135 SH_PFC_PIN_GROUP(qspi0_ctrl), 2136 SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2), 2137 SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4), 2138 SH_PFC_PIN_GROUP(qspi1_ctrl), 2139 SH_PFC_PIN_GROUP_SUBSET(qspi1_data2, rpc_data, 4, 2), 2140 SH_PFC_PIN_GROUP_SUBSET(qspi1_data4, rpc_data, 4, 4), 2141 BUS_DATA_PIN_GROUP(rpc_clk, 1), 2142 BUS_DATA_PIN_GROUP(rpc_clk, 2), 2143 SH_PFC_PIN_GROUP(rpc_ctrl), 2144 SH_PFC_PIN_GROUP(rpc_data), 2145 SH_PFC_PIN_GROUP(rpc_reset), 2146 SH_PFC_PIN_GROUP(rpc_int), 2147 SH_PFC_PIN_GROUP(rpc_wp), 2148 SH_PFC_PIN_GROUP(scif0_data), 2149 SH_PFC_PIN_GROUP(scif0_clk), 2150 SH_PFC_PIN_GROUP(scif0_ctrl), 2151 SH_PFC_PIN_GROUP(scif1_data_a), 2152 SH_PFC_PIN_GROUP(scif1_clk), 2153 SH_PFC_PIN_GROUP(scif1_ctrl), 2154 SH_PFC_PIN_GROUP(scif1_data_b), 2155 SH_PFC_PIN_GROUP(scif3_data), 2156 SH_PFC_PIN_GROUP(scif3_clk), 2157 SH_PFC_PIN_GROUP(scif3_ctrl), 2158 SH_PFC_PIN_GROUP(scif4_data), 2159 SH_PFC_PIN_GROUP(scif4_clk), 2160 SH_PFC_PIN_GROUP(scif4_ctrl), 2161 SH_PFC_PIN_GROUP(scif_clk_a), 2162 SH_PFC_PIN_GROUP(scif_clk_b), 2163 SH_PFC_PIN_GROUP(tmu_tclk1_a), 2164 SH_PFC_PIN_GROUP(tmu_tclk1_b), 2165 SH_PFC_PIN_GROUP(tmu_tclk2_a), 2166 SH_PFC_PIN_GROUP(tmu_tclk2_b), 2167 SH_PFC_PIN_GROUP(tpu_to0), 2168 SH_PFC_PIN_GROUP(tpu_to1), 2169 SH_PFC_PIN_GROUP(tpu_to2), 2170 SH_PFC_PIN_GROUP(tpu_to3), 2171 BUS_DATA_PIN_GROUP(vin0_data, 8), 2172 BUS_DATA_PIN_GROUP(vin0_data, 10), 2173 BUS_DATA_PIN_GROUP(vin0_data, 12), 2174 BUS_DATA_PIN_GROUP(vin0_data, 16), 2175 SH_PFC_PIN_GROUP(vin0_data18), 2176 BUS_DATA_PIN_GROUP(vin0_data, 20), 2177 BUS_DATA_PIN_GROUP(vin0_data, 24), 2178 SH_PFC_PIN_GROUP(vin0_sync), 2179 SH_PFC_PIN_GROUP(vin0_field), 2180 SH_PFC_PIN_GROUP(vin0_clkenb), 2181 SH_PFC_PIN_GROUP(vin0_clk), 2182 BUS_DATA_PIN_GROUP(vin1_data, 8), 2183 BUS_DATA_PIN_GROUP(vin1_data, 10), 2184 BUS_DATA_PIN_GROUP(vin1_data, 12), 2185 SH_PFC_PIN_GROUP(vin1_sync), 2186 SH_PFC_PIN_GROUP(vin1_field), 2187 SH_PFC_PIN_GROUP(vin1_clkenb), 2188 SH_PFC_PIN_GROUP(vin1_clk), 2189 }; 2190 2191 static const char * const avb_groups[] = { 2192 "avb_link", 2193 "avb_magic", 2194 "avb_phy_int", 2195 "avb_mdio", 2196 "avb_rgmii", 2197 "avb_txcrefclk", 2198 "avb_avtp_pps", 2199 "avb_avtp_capture", 2200 "avb_avtp_match", 2201 }; 2202 2203 static const char * const canfd0_groups[] = { 2204 "canfd0_data_a", 2205 "canfd0_data_b", 2206 }; 2207 2208 static const char * const canfd1_groups[] = { 2209 "canfd1_data", 2210 }; 2211 2212 static const char * const canfd_clk_groups[] = { 2213 "canfd_clk_a", 2214 "canfd_clk_b", 2215 }; 2216 2217 static const char * const du_groups[] = { 2218 "du_rgb666", 2219 "du_rgb888", 2220 "du_clk_out", 2221 "du_sync", 2222 "du_oddf", 2223 "du_cde", 2224 "du_disp", 2225 }; 2226 2227 static const char * const gether_groups[] = { 2228 "gether_link_a", 2229 "gether_phy_int_a", 2230 "gether_mdio_a", 2231 "gether_link_b", 2232 "gether_phy_int_b", 2233 "gether_mdio_b", 2234 "gether_magic", 2235 "gether_rgmii", 2236 "gether_txcrefclk", 2237 "gether_txcrefclk_mega", 2238 "gether_rmii", 2239 }; 2240 2241 static const char * const hscif0_groups[] = { 2242 "hscif0_data_a", 2243 "hscif0_clk_a", 2244 "hscif0_ctrl_a", 2245 "hscif0_data_b", 2246 "hscif0_clk_b", 2247 "hscif0_ctrl_b", 2248 }; 2249 2250 static const char * const hscif1_groups[] = { 2251 "hscif1_data", 2252 "hscif1_clk", 2253 "hscif1_ctrl", 2254 }; 2255 2256 static const char * const hscif2_groups[] = { 2257 "hscif2_data", 2258 "hscif2_clk", 2259 "hscif2_ctrl", 2260 }; 2261 2262 static const char * const hscif3_groups[] = { 2263 "hscif3_data", 2264 "hscif3_clk", 2265 "hscif3_ctrl", 2266 }; 2267 2268 static const char * const i2c0_groups[] = { 2269 "i2c0", 2270 }; 2271 2272 static const char * const i2c1_groups[] = { 2273 "i2c1", 2274 }; 2275 2276 static const char * const i2c2_groups[] = { 2277 "i2c2", 2278 }; 2279 2280 static const char * const i2c3_groups[] = { 2281 "i2c3", 2282 }; 2283 2284 static const char * const i2c4_groups[] = { 2285 "i2c4", 2286 }; 2287 2288 static const char * const i2c5_groups[] = { 2289 "i2c5", 2290 }; 2291 2292 static const char * const intc_ex_groups[] = { 2293 "intc_ex_irq0", 2294 "intc_ex_irq1", 2295 "intc_ex_irq2", 2296 "intc_ex_irq3", 2297 "intc_ex_irq4", 2298 "intc_ex_irq5", 2299 }; 2300 2301 static const char * const mmc_groups[] = { 2302 "mmc_data1", 2303 "mmc_data4", 2304 "mmc_data8", 2305 "mmc_ctrl", 2306 "mmc_cd", 2307 "mmc_wp", 2308 "mmc_ds", 2309 }; 2310 2311 static const char * const msiof0_groups[] = { 2312 "msiof0_clk", 2313 "msiof0_sync", 2314 "msiof0_ss1", 2315 "msiof0_ss2", 2316 "msiof0_txd", 2317 "msiof0_rxd", 2318 }; 2319 2320 static const char * const msiof1_groups[] = { 2321 "msiof1_clk", 2322 "msiof1_sync", 2323 "msiof1_ss1", 2324 "msiof1_ss2", 2325 "msiof1_txd", 2326 "msiof1_rxd", 2327 }; 2328 2329 static const char * const msiof2_groups[] = { 2330 "msiof2_clk", 2331 "msiof2_sync", 2332 "msiof2_ss1", 2333 "msiof2_ss2", 2334 "msiof2_txd", 2335 "msiof2_rxd", 2336 }; 2337 2338 static const char * const msiof3_groups[] = { 2339 "msiof3_clk", 2340 "msiof3_sync", 2341 "msiof3_ss1", 2342 "msiof3_ss2", 2343 "msiof3_txd", 2344 "msiof3_rxd", 2345 }; 2346 2347 static const char * const pwm0_groups[] = { 2348 "pwm0_a", 2349 "pwm0_b", 2350 }; 2351 2352 static const char * const pwm1_groups[] = { 2353 "pwm1_a", 2354 "pwm1_b", 2355 }; 2356 2357 static const char * const pwm2_groups[] = { 2358 "pwm2_a", 2359 "pwm2_b", 2360 }; 2361 2362 static const char * const pwm3_groups[] = { 2363 "pwm3_a", 2364 "pwm3_b", 2365 }; 2366 2367 static const char * const pwm4_groups[] = { 2368 "pwm4_a", 2369 "pwm4_b", 2370 }; 2371 2372 static const char * const qspi0_groups[] = { 2373 "qspi0_ctrl", 2374 "qspi0_data2", 2375 "qspi0_data4", 2376 }; 2377 2378 static const char * const qspi1_groups[] = { 2379 "qspi1_ctrl", 2380 "qspi1_data2", 2381 "qspi1_data4", 2382 }; 2383 2384 static const char * const rpc_groups[] = { 2385 "rpc_clk1", 2386 "rpc_clk2", 2387 "rpc_ctrl", 2388 "rpc_data", 2389 "rpc_reset", 2390 "rpc_int", 2391 "rpc_wp", 2392 }; 2393 2394 static const char * const scif0_groups[] = { 2395 "scif0_data", 2396 "scif0_clk", 2397 "scif0_ctrl", 2398 }; 2399 2400 static const char * const scif1_groups[] = { 2401 "scif1_data_a", 2402 "scif1_clk", 2403 "scif1_ctrl", 2404 "scif1_data_b", 2405 }; 2406 2407 static const char * const scif3_groups[] = { 2408 "scif3_data", 2409 "scif3_clk", 2410 "scif3_ctrl", 2411 }; 2412 2413 static const char * const scif4_groups[] = { 2414 "scif4_data", 2415 "scif4_clk", 2416 "scif4_ctrl", 2417 }; 2418 2419 static const char * const scif_clk_groups[] = { 2420 "scif_clk_a", 2421 "scif_clk_b", 2422 }; 2423 2424 static const char * const tmu_groups[] = { 2425 "tmu_tclk1_a", 2426 "tmu_tclk1_b", 2427 "tmu_tclk2_a", 2428 "tmu_tclk2_b", 2429 }; 2430 2431 static const char * const tpu_groups[] = { 2432 "tpu_to0", 2433 "tpu_to1", 2434 "tpu_to2", 2435 "tpu_to3", 2436 }; 2437 2438 static const char * const vin0_groups[] = { 2439 "vin0_data8", 2440 "vin0_data10", 2441 "vin0_data12", 2442 "vin0_data16", 2443 "vin0_data18", 2444 "vin0_data20", 2445 "vin0_data24", 2446 "vin0_sync", 2447 "vin0_field", 2448 "vin0_clkenb", 2449 "vin0_clk", 2450 }; 2451 2452 static const char * const vin1_groups[] = { 2453 "vin1_data8", 2454 "vin1_data10", 2455 "vin1_data12", 2456 "vin1_sync", 2457 "vin1_field", 2458 "vin1_clkenb", 2459 "vin1_clk", 2460 }; 2461 2462 static const struct sh_pfc_function pinmux_functions[] = { 2463 SH_PFC_FUNCTION(avb), 2464 SH_PFC_FUNCTION(canfd0), 2465 SH_PFC_FUNCTION(canfd1), 2466 SH_PFC_FUNCTION(canfd_clk), 2467 SH_PFC_FUNCTION(du), 2468 SH_PFC_FUNCTION(gether), 2469 SH_PFC_FUNCTION(hscif0), 2470 SH_PFC_FUNCTION(hscif1), 2471 SH_PFC_FUNCTION(hscif2), 2472 SH_PFC_FUNCTION(hscif3), 2473 SH_PFC_FUNCTION(i2c0), 2474 SH_PFC_FUNCTION(i2c1), 2475 SH_PFC_FUNCTION(i2c2), 2476 SH_PFC_FUNCTION(i2c3), 2477 SH_PFC_FUNCTION(i2c4), 2478 SH_PFC_FUNCTION(i2c5), 2479 SH_PFC_FUNCTION(intc_ex), 2480 SH_PFC_FUNCTION(mmc), 2481 SH_PFC_FUNCTION(msiof0), 2482 SH_PFC_FUNCTION(msiof1), 2483 SH_PFC_FUNCTION(msiof2), 2484 SH_PFC_FUNCTION(msiof3), 2485 SH_PFC_FUNCTION(pwm0), 2486 SH_PFC_FUNCTION(pwm1), 2487 SH_PFC_FUNCTION(pwm2), 2488 SH_PFC_FUNCTION(pwm3), 2489 SH_PFC_FUNCTION(pwm4), 2490 SH_PFC_FUNCTION(qspi0), 2491 SH_PFC_FUNCTION(qspi1), 2492 SH_PFC_FUNCTION(rpc), 2493 SH_PFC_FUNCTION(scif0), 2494 SH_PFC_FUNCTION(scif1), 2495 SH_PFC_FUNCTION(scif3), 2496 SH_PFC_FUNCTION(scif4), 2497 SH_PFC_FUNCTION(scif_clk), 2498 SH_PFC_FUNCTION(tmu), 2499 SH_PFC_FUNCTION(tpu), 2500 SH_PFC_FUNCTION(vin0), 2501 SH_PFC_FUNCTION(vin1), 2502 }; 2503 2504 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 2505 #define F_(x, y) FN_##y 2506 #define FM(x) FN_##x 2507 { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32, 2508 GROUP(-10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2509 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), 2510 GROUP( 2511 /* GP0_31_22 RESERVED */ 2512 GP_0_21_FN, GPSR0_21, 2513 GP_0_20_FN, GPSR0_20, 2514 GP_0_19_FN, GPSR0_19, 2515 GP_0_18_FN, GPSR0_18, 2516 GP_0_17_FN, GPSR0_17, 2517 GP_0_16_FN, GPSR0_16, 2518 GP_0_15_FN, GPSR0_15, 2519 GP_0_14_FN, GPSR0_14, 2520 GP_0_13_FN, GPSR0_13, 2521 GP_0_12_FN, GPSR0_12, 2522 GP_0_11_FN, GPSR0_11, 2523 GP_0_10_FN, GPSR0_10, 2524 GP_0_9_FN, GPSR0_9, 2525 GP_0_8_FN, GPSR0_8, 2526 GP_0_7_FN, GPSR0_7, 2527 GP_0_6_FN, GPSR0_6, 2528 GP_0_5_FN, GPSR0_5, 2529 GP_0_4_FN, GPSR0_4, 2530 GP_0_3_FN, GPSR0_3, 2531 GP_0_2_FN, GPSR0_2, 2532 GP_0_1_FN, GPSR0_1, 2533 GP_0_0_FN, GPSR0_0, )) 2534 }, 2535 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( 2536 0, 0, 2537 0, 0, 2538 0, 0, 2539 0, 0, 2540 GP_1_27_FN, GPSR1_27, 2541 GP_1_26_FN, GPSR1_26, 2542 GP_1_25_FN, GPSR1_25, 2543 GP_1_24_FN, GPSR1_24, 2544 GP_1_23_FN, GPSR1_23, 2545 GP_1_22_FN, GPSR1_22, 2546 GP_1_21_FN, GPSR1_21, 2547 GP_1_20_FN, GPSR1_20, 2548 GP_1_19_FN, GPSR1_19, 2549 GP_1_18_FN, GPSR1_18, 2550 GP_1_17_FN, GPSR1_17, 2551 GP_1_16_FN, GPSR1_16, 2552 GP_1_15_FN, GPSR1_15, 2553 GP_1_14_FN, GPSR1_14, 2554 GP_1_13_FN, GPSR1_13, 2555 GP_1_12_FN, GPSR1_12, 2556 GP_1_11_FN, GPSR1_11, 2557 GP_1_10_FN, GPSR1_10, 2558 GP_1_9_FN, GPSR1_9, 2559 GP_1_8_FN, GPSR1_8, 2560 GP_1_7_FN, GPSR1_7, 2561 GP_1_6_FN, GPSR1_6, 2562 GP_1_5_FN, GPSR1_5, 2563 GP_1_4_FN, GPSR1_4, 2564 GP_1_3_FN, GPSR1_3, 2565 GP_1_2_FN, GPSR1_2, 2566 GP_1_1_FN, GPSR1_1, 2567 GP_1_0_FN, GPSR1_0, )) 2568 }, 2569 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( 2570 0, 0, 2571 0, 0, 2572 GP_2_29_FN, GPSR2_29, 2573 GP_2_28_FN, GPSR2_28, 2574 GP_2_27_FN, GPSR2_27, 2575 GP_2_26_FN, GPSR2_26, 2576 GP_2_25_FN, GPSR2_25, 2577 GP_2_24_FN, GPSR2_24, 2578 GP_2_23_FN, GPSR2_23, 2579 GP_2_22_FN, GPSR2_22, 2580 GP_2_21_FN, GPSR2_21, 2581 GP_2_20_FN, GPSR2_20, 2582 GP_2_19_FN, GPSR2_19, 2583 GP_2_18_FN, GPSR2_18, 2584 GP_2_17_FN, GPSR2_17, 2585 GP_2_16_FN, GPSR2_16, 2586 GP_2_15_FN, GPSR2_15, 2587 GP_2_14_FN, GPSR2_14, 2588 GP_2_13_FN, GPSR2_13, 2589 GP_2_12_FN, GPSR2_12, 2590 GP_2_11_FN, GPSR2_11, 2591 GP_2_10_FN, GPSR2_10, 2592 GP_2_9_FN, GPSR2_9, 2593 GP_2_8_FN, GPSR2_8, 2594 GP_2_7_FN, GPSR2_7, 2595 GP_2_6_FN, GPSR2_6, 2596 GP_2_5_FN, GPSR2_5, 2597 GP_2_4_FN, GPSR2_4, 2598 GP_2_3_FN, GPSR2_3, 2599 GP_2_2_FN, GPSR2_2, 2600 GP_2_1_FN, GPSR2_1, 2601 GP_2_0_FN, GPSR2_0, )) 2602 }, 2603 { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32, 2604 GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2605 1, 1, 1, 1, 1, 1), 2606 GROUP( 2607 /* GP3_31_17 RESERVED */ 2608 GP_3_16_FN, GPSR3_16, 2609 GP_3_15_FN, GPSR3_15, 2610 GP_3_14_FN, GPSR3_14, 2611 GP_3_13_FN, GPSR3_13, 2612 GP_3_12_FN, GPSR3_12, 2613 GP_3_11_FN, GPSR3_11, 2614 GP_3_10_FN, GPSR3_10, 2615 GP_3_9_FN, GPSR3_9, 2616 GP_3_8_FN, GPSR3_8, 2617 GP_3_7_FN, GPSR3_7, 2618 GP_3_6_FN, GPSR3_6, 2619 GP_3_5_FN, GPSR3_5, 2620 GP_3_4_FN, GPSR3_4, 2621 GP_3_3_FN, GPSR3_3, 2622 GP_3_2_FN, GPSR3_2, 2623 GP_3_1_FN, GPSR3_1, 2624 GP_3_0_FN, GPSR3_0, )) 2625 }, 2626 { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32, 2627 GROUP(-7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2628 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2629 1, 1), 2630 GROUP( 2631 /* GP4_31_25 RESERVED */ 2632 GP_4_24_FN, GPSR4_24, 2633 GP_4_23_FN, GPSR4_23, 2634 GP_4_22_FN, GPSR4_22, 2635 GP_4_21_FN, GPSR4_21, 2636 GP_4_20_FN, GPSR4_20, 2637 GP_4_19_FN, GPSR4_19, 2638 GP_4_18_FN, GPSR4_18, 2639 GP_4_17_FN, GPSR4_17, 2640 GP_4_16_FN, GPSR4_16, 2641 GP_4_15_FN, GPSR4_15, 2642 GP_4_14_FN, GPSR4_14, 2643 GP_4_13_FN, GPSR4_13, 2644 GP_4_12_FN, GPSR4_12, 2645 GP_4_11_FN, GPSR4_11, 2646 GP_4_10_FN, GPSR4_10, 2647 GP_4_9_FN, GPSR4_9, 2648 GP_4_8_FN, GPSR4_8, 2649 GP_4_7_FN, GPSR4_7, 2650 GP_4_6_FN, GPSR4_6, 2651 GP_4_5_FN, GPSR4_5, 2652 GP_4_4_FN, GPSR4_4, 2653 GP_4_3_FN, GPSR4_3, 2654 GP_4_2_FN, GPSR4_2, 2655 GP_4_1_FN, GPSR4_1, 2656 GP_4_0_FN, GPSR4_0, )) 2657 }, 2658 { PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32, 2659 GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2660 1, 1, 1, 1), 2661 GROUP( 2662 /* GP5_31_15 RESERVED */ 2663 GP_5_14_FN, GPSR5_14, 2664 GP_5_13_FN, GPSR5_13, 2665 GP_5_12_FN, GPSR5_12, 2666 GP_5_11_FN, GPSR5_11, 2667 GP_5_10_FN, GPSR5_10, 2668 GP_5_9_FN, GPSR5_9, 2669 GP_5_8_FN, GPSR5_8, 2670 GP_5_7_FN, GPSR5_7, 2671 GP_5_6_FN, GPSR5_6, 2672 GP_5_5_FN, GPSR5_5, 2673 GP_5_4_FN, GPSR5_4, 2674 GP_5_3_FN, GPSR5_3, 2675 GP_5_2_FN, GPSR5_2, 2676 GP_5_1_FN, GPSR5_1, 2677 GP_5_0_FN, GPSR5_0, )) 2678 }, 2679 #undef F_ 2680 #undef FM 2681 2682 #define F_(x, y) x, 2683 #define FM(x) FN_##x, 2684 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( 2685 IP0_31_28 2686 IP0_27_24 2687 IP0_23_20 2688 IP0_19_16 2689 IP0_15_12 2690 IP0_11_8 2691 IP0_7_4 2692 IP0_3_0 )) 2693 }, 2694 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( 2695 IP1_31_28 2696 IP1_27_24 2697 IP1_23_20 2698 IP1_19_16 2699 IP1_15_12 2700 IP1_11_8 2701 IP1_7_4 2702 IP1_3_0 )) 2703 }, 2704 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( 2705 IP2_31_28 2706 IP2_27_24 2707 IP2_23_20 2708 IP2_19_16 2709 IP2_15_12 2710 IP2_11_8 2711 IP2_7_4 2712 IP2_3_0 )) 2713 }, 2714 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( 2715 IP3_31_28 2716 IP3_27_24 2717 IP3_23_20 2718 IP3_19_16 2719 IP3_15_12 2720 IP3_11_8 2721 IP3_7_4 2722 IP3_3_0 )) 2723 }, 2724 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( 2725 IP4_31_28 2726 IP4_27_24 2727 IP4_23_20 2728 IP4_19_16 2729 IP4_15_12 2730 IP4_11_8 2731 IP4_7_4 2732 IP4_3_0 )) 2733 }, 2734 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( 2735 IP5_31_28 2736 IP5_27_24 2737 IP5_23_20 2738 IP5_19_16 2739 IP5_15_12 2740 IP5_11_8 2741 IP5_7_4 2742 IP5_3_0 )) 2743 }, 2744 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( 2745 IP6_31_28 2746 IP6_27_24 2747 IP6_23_20 2748 IP6_19_16 2749 IP6_15_12 2750 IP6_11_8 2751 IP6_7_4 2752 IP6_3_0 )) 2753 }, 2754 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( 2755 IP7_31_28 2756 IP7_27_24 2757 IP7_23_20 2758 IP7_19_16 2759 IP7_15_12 2760 IP7_11_8 2761 IP7_7_4 2762 IP7_3_0 )) 2763 }, 2764 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( 2765 IP8_31_28 2766 IP8_27_24 2767 IP8_23_20 2768 IP8_19_16 2769 IP8_15_12 2770 IP8_11_8 2771 IP8_7_4 2772 IP8_3_0 )) 2773 }, 2774 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP( 2775 IP9_31_28 2776 IP9_27_24 2777 IP9_23_20 2778 IP9_19_16 2779 IP9_15_12 2780 IP9_11_8 2781 IP9_7_4 2782 IP9_3_0 )) 2783 }, 2784 { PINMUX_CFG_REG_VAR("IPSR10", 0xe6060228, 32, 2785 GROUP(-12, 4, 4, 4, 4, 4), 2786 GROUP( 2787 /* IP10_31_20 RESERVED */ 2788 IP10_19_16 2789 IP10_15_12 2790 IP10_11_8 2791 IP10_7_4 2792 IP10_3_0 )) 2793 }, 2794 #undef F_ 2795 #undef FM 2796 2797 #define F_(x, y) x, 2798 #define FM(x) FN_##x, 2799 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, 2800 GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, -1, 1, 1, 1), 2801 GROUP( 2802 /* RESERVED 31-12 */ 2803 MOD_SEL0_11 2804 MOD_SEL0_10 2805 MOD_SEL0_9 2806 MOD_SEL0_8 2807 MOD_SEL0_7 2808 MOD_SEL0_6 2809 MOD_SEL0_5 2810 MOD_SEL0_4 2811 /* RESERVED 3 */ 2812 MOD_SEL0_2 2813 MOD_SEL0_1 2814 MOD_SEL0_0 )) 2815 }, 2816 { }, 2817 }; 2818 2819 enum ioctrl_regs { 2820 POCCTRL0, 2821 POCCTRL1, 2822 POCCTRL2, 2823 POCCTRL3, 2824 TDSELCTRL, 2825 }; 2826 2827 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { 2828 [POCCTRL0] = { 0xe6060380, }, 2829 [POCCTRL1] = { 0xe6060384, }, 2830 [POCCTRL2] = { 0xe6060388, }, 2831 [POCCTRL3] = { 0xe606038c, }, 2832 [TDSELCTRL] = { 0xe60603c0, }, 2833 { /* sentinel */ }, 2834 }; 2835 2836 static int r8a77980_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) 2837 { 2838 int bit = pin & 0x1f; 2839 2840 *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg; 2841 if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21)) 2842 return bit; 2843 else if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9)) 2844 return bit + 22; 2845 2846 *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg; 2847 if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16)) 2848 return bit - 10; 2849 if ((pin >= RCAR_GP_PIN(2, 17) && pin <= RCAR_GP_PIN(2, 24)) || 2850 (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))) 2851 return bit + 7; 2852 2853 *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg; 2854 if (pin >= RCAR_GP_PIN(2, 25) && pin <= RCAR_GP_PIN(2, 29)) 2855 return pin - 25; 2856 2857 return -EINVAL; 2858 } 2859 2860 static const struct pinmux_bias_reg pinmux_bias_regs[] = { 2861 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { 2862 [ 0] = RCAR_GP_PIN(0, 0), /* DU_DR2 */ 2863 [ 1] = RCAR_GP_PIN(0, 1), /* DU_DR3 */ 2864 [ 2] = RCAR_GP_PIN(0, 2), /* DU_DR4 */ 2865 [ 3] = RCAR_GP_PIN(0, 3), /* DU_DR5 */ 2866 [ 4] = RCAR_GP_PIN(0, 4), /* DU_DR6 */ 2867 [ 5] = RCAR_GP_PIN(0, 5), /* DU_DR7 */ 2868 [ 6] = RCAR_GP_PIN(0, 6), /* DU_DG2 */ 2869 [ 7] = RCAR_GP_PIN(0, 7), /* DU_DG3 */ 2870 [ 8] = RCAR_GP_PIN(0, 8), /* DU_DG4 */ 2871 [ 9] = RCAR_GP_PIN(0, 9), /* DU_DG5 */ 2872 [10] = RCAR_GP_PIN(0, 10), /* DU_DG6 */ 2873 [11] = RCAR_GP_PIN(0, 11), /* DU_DG7 */ 2874 [12] = RCAR_GP_PIN(0, 12), /* DU_DB2 */ 2875 [13] = RCAR_GP_PIN(0, 13), /* DU_DB3 */ 2876 [14] = RCAR_GP_PIN(0, 14), /* DU_DB4 */ 2877 [15] = RCAR_GP_PIN(0, 15), /* DU_DB5 */ 2878 [16] = RCAR_GP_PIN(0, 16), /* DU_DB6 */ 2879 [17] = RCAR_GP_PIN(0, 17), /* DU_DB7 */ 2880 [18] = RCAR_GP_PIN(0, 18), /* DU_DOTCLKOUT */ 2881 [19] = RCAR_GP_PIN(0, 19), /* DU_EXHSYNC/DU_HSYNC */ 2882 [20] = RCAR_GP_PIN(0, 20), /* DU_EXVSYNC/DU_VSYNC */ 2883 [21] = RCAR_GP_PIN(0, 21), /* DU_EXODDF/DU_ODDF/DISP/CDE */ 2884 [22] = SH_PFC_PIN_NONE, 2885 [23] = SH_PFC_PIN_NONE, 2886 [24] = PIN_DU_DOTCLKIN, /* DU_DOTCLKIN */ 2887 [25] = SH_PFC_PIN_NONE, 2888 [26] = PIN_PRESETOUT_N, /* PRESETOUT# */ 2889 [27] = SH_PFC_PIN_NONE, 2890 [28] = SH_PFC_PIN_NONE, 2891 [29] = SH_PFC_PIN_NONE, 2892 [30] = PIN_EXTALR, /* EXTALR */ 2893 [31] = PIN_FSCLKST_N, /* FSCLKST# */ 2894 } }, 2895 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) { 2896 [ 0] = PIN_FSCLKST, /* FSCLKST */ 2897 [ 1] = SH_PFC_PIN_NONE, 2898 [ 2] = RCAR_GP_PIN(1, 0), /* IRQ0 */ 2899 [ 3] = PIN_DCUTRST_N, /* DCUTRST# */ 2900 [ 4] = PIN_DCUTCK_LPDCLK, /* DCUTCK_LPDCLK */ 2901 [ 5] = PIN_DCUTMS, /* DCUTMS */ 2902 [ 6] = PIN_DCUTDI_LPDI, /* DCUTDI_LPDI */ 2903 [ 7] = SH_PFC_PIN_NONE, 2904 [ 8] = RCAR_GP_PIN(2, 0), /* VI0_CLK */ 2905 [ 9] = RCAR_GP_PIN(2, 1), /* VI0_CLKENB */ 2906 [10] = RCAR_GP_PIN(2, 2), /* VI0_HSYNC# */ 2907 [11] = RCAR_GP_PIN(2, 3), /* VI0_VSYNC# */ 2908 [12] = RCAR_GP_PIN(2, 4), /* VI0_DATA0 */ 2909 [13] = RCAR_GP_PIN(2, 5), /* VI0_DATA1 */ 2910 [14] = RCAR_GP_PIN(2, 6), /* VI0_DATA2 */ 2911 [15] = RCAR_GP_PIN(2, 7), /* VI0_DATA3 */ 2912 [16] = RCAR_GP_PIN(2, 8), /* VI0_DATA4 */ 2913 [17] = RCAR_GP_PIN(2, 9), /* VI0_DATA5 */ 2914 [18] = RCAR_GP_PIN(2, 10), /* VI0_DATA6 */ 2915 [19] = RCAR_GP_PIN(2, 11), /* VI0_DATA7 */ 2916 [20] = RCAR_GP_PIN(2, 12), /* VI0_DATA8 */ 2917 [21] = RCAR_GP_PIN(2, 13), /* VI0_DATA9 */ 2918 [22] = RCAR_GP_PIN(2, 14), /* VI0_DATA10 */ 2919 [23] = RCAR_GP_PIN(2, 15), /* VI0_DATA11 */ 2920 [24] = RCAR_GP_PIN(2, 16), /* VI0_FIELD */ 2921 [25] = RCAR_GP_PIN(3, 0), /* VI1_CLK */ 2922 [26] = RCAR_GP_PIN(3, 1), /* VI1_CLKENB */ 2923 [27] = RCAR_GP_PIN(3, 2), /* VI1_HSYNC# */ 2924 [28] = RCAR_GP_PIN(3, 3), /* VI1_VSYNC# */ 2925 [29] = RCAR_GP_PIN(3, 4), /* VI1_DATA0 */ 2926 [30] = RCAR_GP_PIN(3, 5), /* VI1_DATA1 */ 2927 [31] = RCAR_GP_PIN(3, 6), /* VI1_DATA2 */ 2928 } }, 2929 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { 2930 [ 0] = RCAR_GP_PIN(3, 7), /* VI1_DATA3 */ 2931 [ 1] = RCAR_GP_PIN(3, 8), /* VI1_DATA4 */ 2932 [ 2] = RCAR_GP_PIN(3, 9), /* VI1_DATA5 */ 2933 [ 3] = RCAR_GP_PIN(3, 10), /* VI1_DATA6 */ 2934 [ 4] = RCAR_GP_PIN(3, 11), /* VI1_DATA7 */ 2935 [ 5] = RCAR_GP_PIN(3, 12), /* VI1_DATA8 */ 2936 [ 6] = RCAR_GP_PIN(3, 13), /* VI1_DATA9 */ 2937 [ 7] = RCAR_GP_PIN(3, 14), /* VI1_DATA10 */ 2938 [ 8] = RCAR_GP_PIN(3, 15), /* VI1_DATA11 */ 2939 [ 9] = RCAR_GP_PIN(3, 16), /* VI1_FIELD */ 2940 [10] = RCAR_GP_PIN(4, 0), /* SCL0 */ 2941 [11] = RCAR_GP_PIN(4, 1), /* SDA0 */ 2942 [12] = RCAR_GP_PIN(4, 2), /* SCL1 */ 2943 [13] = RCAR_GP_PIN(4, 3), /* SDA1 */ 2944 [14] = RCAR_GP_PIN(4, 4), /* SCL2 */ 2945 [15] = RCAR_GP_PIN(4, 5), /* SDA2 */ 2946 [16] = RCAR_GP_PIN(1, 1), /* AVB_RX_CTL */ 2947 [17] = RCAR_GP_PIN(1, 2), /* AVB_RXC */ 2948 [18] = RCAR_GP_PIN(1, 3), /* AVB_RD0 */ 2949 [19] = RCAR_GP_PIN(1, 4), /* AVB_RD1 */ 2950 [20] = RCAR_GP_PIN(1, 5), /* AVB_RD2 */ 2951 [21] = RCAR_GP_PIN(1, 6), /* AVB_RD3 */ 2952 [22] = RCAR_GP_PIN(1, 7), /* AVB_TX_CTL */ 2953 [23] = RCAR_GP_PIN(1, 8), /* AVB_TXC */ 2954 [24] = RCAR_GP_PIN(1, 9), /* AVB_TD0 */ 2955 [25] = RCAR_GP_PIN(1, 10), /* AVB_TD1 */ 2956 [26] = RCAR_GP_PIN(1, 11), /* AVB_TD2 */ 2957 [27] = RCAR_GP_PIN(1, 12), /* AVB_TD3 */ 2958 [28] = RCAR_GP_PIN(1, 13), /* AVB_TXCREFCLK */ 2959 [29] = RCAR_GP_PIN(1, 14), /* AVB_MDIO */ 2960 [30] = RCAR_GP_PIN(1, 15), /* AVB_MDC */ 2961 [31] = RCAR_GP_PIN(1, 16), /* AVB_MAGIC */ 2962 } }, 2963 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { 2964 [ 0] = RCAR_GP_PIN(1, 17), /* AVB_PHY_INT */ 2965 [ 1] = RCAR_GP_PIN(1, 18), /* AVB_LINK */ 2966 [ 2] = RCAR_GP_PIN(1, 19), /* AVB_AVTP_MATCH */ 2967 [ 3] = RCAR_GP_PIN(1, 20), /* AVTP_CAPTURE */ 2968 [ 4] = RCAR_GP_PIN(4, 6), /* GETHER_RX_CTL */ 2969 [ 5] = RCAR_GP_PIN(4, 7), /* GETHER_RXC */ 2970 [ 6] = RCAR_GP_PIN(4, 8), /* GETHER_RD0 */ 2971 [ 7] = RCAR_GP_PIN(4, 9), /* GETHER_RD1 */ 2972 [ 8] = RCAR_GP_PIN(4, 10), /* GETHER_RD2 */ 2973 [ 9] = RCAR_GP_PIN(4, 11), /* GETHER_RD3 */ 2974 [10] = RCAR_GP_PIN(4, 12), /* GETHER_TX_CTL */ 2975 [11] = RCAR_GP_PIN(4, 13), /* GETHER_TXC */ 2976 [12] = RCAR_GP_PIN(4, 14), /* GETHER_TD0 */ 2977 [13] = RCAR_GP_PIN(4, 15), /* GETHER_TD1 */ 2978 [14] = RCAR_GP_PIN(4, 16), /* GETHER_TD2 */ 2979 [15] = RCAR_GP_PIN(4, 17), /* GETHER_TD3 */ 2980 [16] = RCAR_GP_PIN(4, 18), /* GETHER_TXCREFCLK */ 2981 [17] = RCAR_GP_PIN(4, 19), /* GETHER_TXCREFCLK_MEGA */ 2982 [18] = RCAR_GP_PIN(4, 20), /* GETHER_MDIO_A */ 2983 [19] = RCAR_GP_PIN(4, 21), /* GETHER_MDC_A */ 2984 [20] = RCAR_GP_PIN(4, 22), /* GETHER_MAGIC */ 2985 [21] = RCAR_GP_PIN(4, 23), /* GETHER_PHY_INT_A */ 2986 [22] = RCAR_GP_PIN(4, 24), /* GETHER_LINK_A */ 2987 [23] = RCAR_GP_PIN(1, 21), /* CANFD0_TX_A */ 2988 [24] = RCAR_GP_PIN(1, 22), /* CANFD0_RX_A */ 2989 [25] = RCAR_GP_PIN(1, 23), /* CANFD1_TX */ 2990 [26] = RCAR_GP_PIN(1, 24), /* CANFD1_RX */ 2991 [27] = RCAR_GP_PIN(1, 25), /* CAN_CLK_A */ 2992 [28] = RCAR_GP_PIN(5, 0), /* QSPI0_SPCLK */ 2993 [29] = RCAR_GP_PIN(5, 1), /* QSPI0_MOSI_IO0 */ 2994 [30] = RCAR_GP_PIN(5, 2), /* QSPI0_MISO_IO1 */ 2995 [31] = RCAR_GP_PIN(5, 3), /* QSPI0_IO2 */ 2996 } }, 2997 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) { 2998 [ 0] = RCAR_GP_PIN(5, 4), /* QSPI0_IO3 */ 2999 [ 1] = RCAR_GP_PIN(5, 5), /* QSPI0_SSL */ 3000 [ 2] = RCAR_GP_PIN(5, 6), /* QSPI1_SPCLK */ 3001 [ 3] = RCAR_GP_PIN(5, 7), /* QSPI1_MOSI_IO0 */ 3002 [ 4] = RCAR_GP_PIN(5, 8), /* QSPI1_MISO_IO1 */ 3003 [ 5] = RCAR_GP_PIN(5, 9), /* QSPI1_IO2 */ 3004 [ 6] = RCAR_GP_PIN(5, 10), /* QSPI1_IO3 */ 3005 [ 7] = RCAR_GP_PIN(5, 11), /* QSPI1_SSL */ 3006 [ 8] = RCAR_GP_PIN(5, 12), /* RPC_RESET# */ 3007 [ 9] = RCAR_GP_PIN(5, 13), /* RPC_WP# */ 3008 [10] = RCAR_GP_PIN(5, 14), /* RPC_INT# */ 3009 [11] = RCAR_GP_PIN(1, 26), /* DIGRF_CLKIN */ 3010 [12] = RCAR_GP_PIN(1, 27), /* DIGRF_CLKOUT */ 3011 [13] = RCAR_GP_PIN(2, 17), /* IRQ4 */ 3012 [14] = RCAR_GP_PIN(2, 18), /* IRQ5 */ 3013 [15] = RCAR_GP_PIN(2, 25), /* SCL3 */ 3014 [16] = RCAR_GP_PIN(2, 26), /* SDA3 */ 3015 [17] = RCAR_GP_PIN(2, 19), /* MSIOF0_RXD */ 3016 [18] = RCAR_GP_PIN(2, 20), /* MSIOF0_TXD */ 3017 [19] = RCAR_GP_PIN(2, 21), /* MSIOF0_SCK */ 3018 [20] = RCAR_GP_PIN(2, 22), /* MSIOF0_SYNC */ 3019 [21] = RCAR_GP_PIN(2, 23), /* MSIOF0_SS1 */ 3020 [22] = RCAR_GP_PIN(2, 24), /* MSIOF0_SS2 */ 3021 [23] = RCAR_GP_PIN(2, 27), /* FSO_CFE_0# */ 3022 [24] = RCAR_GP_PIN(2, 28), /* FSO_CFE_1# */ 3023 [25] = RCAR_GP_PIN(2, 29), /* FSO_TOE# */ 3024 [26] = SH_PFC_PIN_NONE, 3025 [27] = SH_PFC_PIN_NONE, 3026 [28] = SH_PFC_PIN_NONE, 3027 [29] = SH_PFC_PIN_NONE, 3028 [30] = SH_PFC_PIN_NONE, 3029 [31] = SH_PFC_PIN_NONE, 3030 } }, 3031 { /* sentinel */ } 3032 }; 3033 3034 static const struct sh_pfc_soc_operations r8a77980_pfc_ops = { 3035 .pin_to_pocctrl = r8a77980_pin_to_pocctrl, 3036 .get_bias = rcar_pinmux_get_bias, 3037 .set_bias = rcar_pinmux_set_bias, 3038 }; 3039 3040 const struct sh_pfc_soc_info r8a77980_pinmux_info = { 3041 .name = "r8a77980_pfc", 3042 .ops = &r8a77980_pfc_ops, 3043 .unlock_reg = 0xe6060000, /* PMMR */ 3044 3045 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 3046 3047 .pins = pinmux_pins, 3048 .nr_pins = ARRAY_SIZE(pinmux_pins), 3049 .groups = pinmux_groups, 3050 .nr_groups = ARRAY_SIZE(pinmux_groups), 3051 .functions = pinmux_functions, 3052 .nr_functions = ARRAY_SIZE(pinmux_functions), 3053 3054 .cfg_regs = pinmux_config_regs, 3055 .bias_regs = pinmux_bias_regs, 3056 .ioctrl_regs = pinmux_ioctrl_regs, 3057 3058 .pinmux_data = pinmux_data, 3059 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 3060 }; 3061