1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * R8A77980 processor support - PFC hardware block. 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 * Copyright (C) 2018 Cogent Embedded, Inc. 7 * 8 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c 9 * 10 * R-Car Gen3 processor support - PFC hardware block. 11 * 12 * Copyright (C) 2015 Renesas Electronics Corporation 13 */ 14 15 #include <linux/errno.h> 16 #include <linux/io.h> 17 #include <linux/kernel.h> 18 19 #include "sh_pfc.h" 20 21 #define CPU_ALL_GP(fn, sfx) \ 22 PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 23 PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 24 PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 25 PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 26 PORT_GP_CFG_25(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 27 PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN) 28 29 #define CPU_ALL_NOGP(fn) \ 30 PIN_NOGP_CFG(DCUTCK_LPDCLK, "DCUTCK_LPDCLK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 31 PIN_NOGP_CFG(DCUTDI_LPDI, "DCUTDI_LPDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 32 PIN_NOGP_CFG(DCUTMS, "DCUTMS", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 33 PIN_NOGP_CFG(DCUTRST_N, "DCUTRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 34 PIN_NOGP_CFG(DU_DOTCLKIN, "DU_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 35 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 36 PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 37 PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 38 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN) 39 40 /* 41 * F_() : just information 42 * FM() : macro for FN_xxx / xxx_MARK 43 */ 44 45 /* GPSR0 */ 46 #define GPSR0_21 F_(DU_EXODDF_DU_ODDF_DISP_CDE, IP2_23_20) 47 #define GPSR0_20 F_(DU_EXVSYNC_DU_VSYNC, IP2_19_16) 48 #define GPSR0_19 F_(DU_EXHSYNC_DU_HSYNC, IP2_15_12) 49 #define GPSR0_18 F_(DU_DOTCLKOUT, IP2_11_8) 50 #define GPSR0_17 F_(DU_DB7, IP2_7_4) 51 #define GPSR0_16 F_(DU_DB6, IP2_3_0) 52 #define GPSR0_15 F_(DU_DB5, IP1_31_28) 53 #define GPSR0_14 F_(DU_DB4, IP1_27_24) 54 #define GPSR0_13 F_(DU_DB3, IP1_23_20) 55 #define GPSR0_12 F_(DU_DB2, IP1_19_16) 56 #define GPSR0_11 F_(DU_DG7, IP1_15_12) 57 #define GPSR0_10 F_(DU_DG6, IP1_11_8) 58 #define GPSR0_9 F_(DU_DG5, IP1_7_4) 59 #define GPSR0_8 F_(DU_DG4, IP1_3_0) 60 #define GPSR0_7 F_(DU_DG3, IP0_31_28) 61 #define GPSR0_6 F_(DU_DG2, IP0_27_24) 62 #define GPSR0_5 F_(DU_DR7, IP0_23_20) 63 #define GPSR0_4 F_(DU_DR6, IP0_19_16) 64 #define GPSR0_3 F_(DU_DR5, IP0_15_12) 65 #define GPSR0_2 F_(DU_DR4, IP0_11_8) 66 #define GPSR0_1 F_(DU_DR3, IP0_7_4) 67 #define GPSR0_0 F_(DU_DR2, IP0_3_0) 68 69 /* GPSR1 */ 70 #define GPSR1_27 F_(DIGRF_CLKOUT, IP8_31_28) 71 #define GPSR1_26 F_(DIGRF_CLKIN, IP8_27_24) 72 #define GPSR1_25 F_(CANFD_CLK_A, IP8_23_20) 73 #define GPSR1_24 F_(CANFD1_RX, IP8_19_16) 74 #define GPSR1_23 F_(CANFD1_TX, IP8_15_12) 75 #define GPSR1_22 F_(CANFD0_RX_A, IP8_11_8) 76 #define GPSR1_21 F_(CANFD0_TX_A, IP8_7_4) 77 #define GPSR1_20 F_(AVB_AVTP_CAPTURE, IP8_3_0) 78 #define GPSR1_19 F_(AVB_AVTP_MATCH, IP7_31_28) 79 #define GPSR1_18 FM(AVB_LINK) 80 #define GPSR1_17 FM(AVB_PHY_INT) 81 #define GPSR1_16 FM(AVB_MAGIC) 82 #define GPSR1_15 FM(AVB_MDC) 83 #define GPSR1_14 FM(AVB_MDIO) 84 #define GPSR1_13 FM(AVB_TXCREFCLK) 85 #define GPSR1_12 FM(AVB_TD3) 86 #define GPSR1_11 FM(AVB_TD2) 87 #define GPSR1_10 FM(AVB_TD1) 88 #define GPSR1_9 FM(AVB_TD0) 89 #define GPSR1_8 FM(AVB_TXC) 90 #define GPSR1_7 FM(AVB_TX_CTL) 91 #define GPSR1_6 FM(AVB_RD3) 92 #define GPSR1_5 FM(AVB_RD2) 93 #define GPSR1_4 FM(AVB_RD1) 94 #define GPSR1_3 FM(AVB_RD0) 95 #define GPSR1_2 FM(AVB_RXC) 96 #define GPSR1_1 FM(AVB_RX_CTL) 97 #define GPSR1_0 F_(IRQ0, IP2_27_24) 98 99 /* GPSR2 */ 100 #define GPSR2_29 F_(FSO_TOE_N, IP10_19_16) 101 #define GPSR2_28 F_(FSO_CFE_1_N, IP10_15_12) 102 #define GPSR2_27 F_(FSO_CFE_0_N, IP10_11_8) 103 #define GPSR2_26 F_(SDA3, IP10_7_4) 104 #define GPSR2_25 F_(SCL3, IP10_3_0) 105 #define GPSR2_24 F_(MSIOF0_SS2, IP9_31_28) 106 #define GPSR2_23 F_(MSIOF0_SS1, IP9_27_24) 107 #define GPSR2_22 F_(MSIOF0_SYNC, IP9_23_20) 108 #define GPSR2_21 F_(MSIOF0_SCK, IP9_19_16) 109 #define GPSR2_20 F_(MSIOF0_TXD, IP9_15_12) 110 #define GPSR2_19 F_(MSIOF0_RXD, IP9_11_8) 111 #define GPSR2_18 F_(IRQ5, IP9_7_4) 112 #define GPSR2_17 F_(IRQ4, IP9_3_0) 113 #define GPSR2_16 F_(VI0_FIELD, IP4_31_28) 114 #define GPSR2_15 F_(VI0_DATA11, IP4_27_24) 115 #define GPSR2_14 F_(VI0_DATA10, IP4_23_20) 116 #define GPSR2_13 F_(VI0_DATA9, IP4_19_16) 117 #define GPSR2_12 F_(VI0_DATA8, IP4_15_12) 118 #define GPSR2_11 F_(VI0_DATA7, IP4_11_8) 119 #define GPSR2_10 F_(VI0_DATA6, IP4_7_4) 120 #define GPSR2_9 F_(VI0_DATA5, IP4_3_0) 121 #define GPSR2_8 F_(VI0_DATA4, IP3_31_28) 122 #define GPSR2_7 F_(VI0_DATA3, IP3_27_24) 123 #define GPSR2_6 F_(VI0_DATA2, IP3_23_20) 124 #define GPSR2_5 F_(VI0_DATA1, IP3_19_16) 125 #define GPSR2_4 F_(VI0_DATA0, IP3_15_12) 126 #define GPSR2_3 F_(VI0_VSYNC_N, IP3_11_8) 127 #define GPSR2_2 F_(VI0_HSYNC_N, IP3_7_4) 128 #define GPSR2_1 F_(VI0_CLKENB, IP3_3_0) 129 #define GPSR2_0 F_(VI0_CLK, IP2_31_28) 130 131 /* GPSR3 */ 132 #define GPSR3_16 F_(VI1_FIELD, IP7_3_0) 133 #define GPSR3_15 F_(VI1_DATA11, IP6_31_28) 134 #define GPSR3_14 F_(VI1_DATA10, IP6_27_24) 135 #define GPSR3_13 F_(VI1_DATA9, IP6_23_20) 136 #define GPSR3_12 F_(VI1_DATA8, IP6_19_16) 137 #define GPSR3_11 F_(VI1_DATA7, IP6_15_12) 138 #define GPSR3_10 F_(VI1_DATA6, IP6_11_8) 139 #define GPSR3_9 F_(VI1_DATA5, IP6_7_4) 140 #define GPSR3_8 F_(VI1_DATA4, IP6_3_0) 141 #define GPSR3_7 F_(VI1_DATA3, IP5_31_28) 142 #define GPSR3_6 F_(VI1_DATA2, IP5_27_24) 143 #define GPSR3_5 F_(VI1_DATA1, IP5_23_20) 144 #define GPSR3_4 F_(VI1_DATA0, IP5_19_16) 145 #define GPSR3_3 F_(VI1_VSYNC_N, IP5_15_12) 146 #define GPSR3_2 F_(VI1_HSYNC_N, IP5_11_8) 147 #define GPSR3_1 F_(VI1_CLKENB, IP5_7_4) 148 #define GPSR3_0 F_(VI1_CLK, IP5_3_0) 149 150 /* GPSR4 */ 151 #define GPSR4_24 FM(GETHER_LINK_A) 152 #define GPSR4_23 FM(GETHER_PHY_INT_A) 153 #define GPSR4_22 FM(GETHER_MAGIC) 154 #define GPSR4_21 FM(GETHER_MDC_A) 155 #define GPSR4_20 FM(GETHER_MDIO_A) 156 #define GPSR4_19 FM(GETHER_TXCREFCLK_MEGA) 157 #define GPSR4_18 FM(GETHER_TXCREFCLK) 158 #define GPSR4_17 FM(GETHER_TD3) 159 #define GPSR4_16 FM(GETHER_TD2) 160 #define GPSR4_15 FM(GETHER_TD1) 161 #define GPSR4_14 FM(GETHER_TD0) 162 #define GPSR4_13 FM(GETHER_TXC) 163 #define GPSR4_12 FM(GETHER_TX_CTL) 164 #define GPSR4_11 FM(GETHER_RD3) 165 #define GPSR4_10 FM(GETHER_RD2) 166 #define GPSR4_9 FM(GETHER_RD1) 167 #define GPSR4_8 FM(GETHER_RD0) 168 #define GPSR4_7 FM(GETHER_RXC) 169 #define GPSR4_6 FM(GETHER_RX_CTL) 170 #define GPSR4_5 F_(SDA2, IP7_27_24) 171 #define GPSR4_4 F_(SCL2, IP7_23_20) 172 #define GPSR4_3 F_(SDA1, IP7_19_16) 173 #define GPSR4_2 F_(SCL1, IP7_15_12) 174 #define GPSR4_1 F_(SDA0, IP7_11_8) 175 #define GPSR4_0 F_(SCL0, IP7_7_4) 176 177 /* GPSR5 */ 178 #define GPSR5_14 FM(RPC_INT_N) 179 #define GPSR5_13 FM(RPC_WP_N) 180 #define GPSR5_12 FM(RPC_RESET_N) 181 #define GPSR5_11 FM(QSPI1_SSL) 182 #define GPSR5_10 FM(QSPI1_IO3) 183 #define GPSR5_9 FM(QSPI1_IO2) 184 #define GPSR5_8 FM(QSPI1_MISO_IO1) 185 #define GPSR5_7 FM(QSPI1_MOSI_IO0) 186 #define GPSR5_6 FM(QSPI1_SPCLK) 187 #define GPSR5_5 FM(QSPI0_SSL) 188 #define GPSR5_4 FM(QSPI0_IO3) 189 #define GPSR5_3 FM(QSPI0_IO2) 190 #define GPSR5_2 FM(QSPI0_MISO_IO1) 191 #define GPSR5_1 FM(QSPI0_MOSI_IO0) 192 #define GPSR5_0 FM(QSPI0_SPCLK) 193 194 195 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ 196 #define IP0_3_0 FM(DU_DR2) FM(SCK4) FM(GETHER_RMII_CRS_DV) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 197 #define IP0_7_4 FM(DU_DR3) FM(RX4) FM(GETHER_RMII_RX_ER) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 198 #define IP0_11_8 FM(DU_DR4) FM(TX4) FM(GETHER_RMII_RXD0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 199 #define IP0_15_12 FM(DU_DR5) FM(CTS4_N) FM(GETHER_RMII_RXD1) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 200 #define IP0_19_16 FM(DU_DR6) FM(RTS4_N) FM(GETHER_RMII_TXD_EN) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 201 #define IP0_23_20 FM(DU_DR7) F_(0, 0) FM(GETHER_RMII_TXD0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 202 #define IP0_27_24 FM(DU_DG2) F_(0, 0) FM(GETHER_RMII_TXD1) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 203 #define IP0_31_28 FM(DU_DG3) FM(CPG_CPCKOUT) FM(GETHER_RMII_REFCLK) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 204 #define IP1_3_0 FM(DU_DG4) FM(SCL5) F_(0, 0) FM(A8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 205 #define IP1_7_4 FM(DU_DG5) FM(SDA5) FM(GETHER_MDC_B) FM(A9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 206 #define IP1_11_8 FM(DU_DG6) FM(SCIF_CLK_A) FM(GETHER_MDIO_B) FM(A10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 207 #define IP1_15_12 FM(DU_DG7) FM(HRX0_A) F_(0, 0) FM(A11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 208 #define IP1_19_16 FM(DU_DB2) FM(HSCK0_A) F_(0, 0) FM(A12) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 209 #define IP1_23_20 FM(DU_DB3) FM(HRTS0_N_A) F_(0, 0) FM(A13) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 210 #define IP1_27_24 FM(DU_DB4) FM(HCTS0_N_A) F_(0, 0) FM(A14) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 211 #define IP1_31_28 FM(DU_DB5) FM(HTX0_A) FM(PWM0_A) FM(A15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 212 #define IP2_3_0 FM(DU_DB6) FM(MSIOF3_RXD) F_(0, 0) FM(A16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 213 #define IP2_7_4 FM(DU_DB7) FM(MSIOF3_TXD) F_(0, 0) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 214 #define IP2_11_8 FM(DU_DOTCLKOUT) FM(MSIOF3_SS1) FM(GETHER_LINK_B) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 215 #define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(MSIOF3_SS2) FM(GETHER_PHY_INT_B) FM(A19) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 216 #define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 217 #define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 218 #define IP2_27_24 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 219 #define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 220 #define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 221 #define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 222 #define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 223 #define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 224 #define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 225 #define IP3_23_20 FM(VI0_DATA2) FM(AVB_AVTP_PPS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 226 #define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 227 #define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 228 #define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 229 #define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 230 #define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 231 #define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 232 #define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 233 #define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 234 #define IP4_27_24 FM(VI0_DATA11) FM(HTX2) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 235 #define IP4_31_28 FM(VI0_FIELD) FM(HRX2) FM(PWM4_A) FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 236 #define IP5_3_0 FM(VI1_CLK) FM(MSIOF1_RXD) F_(0, 0) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 237 #define IP5_7_4 FM(VI1_CLKENB) FM(MSIOF1_TXD) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 238 #define IP5_11_8 FM(VI1_HSYNC_N) FM(MSIOF1_SCK) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 239 #define IP5_15_12 FM(VI1_VSYNC_N) FM(MSIOF1_SYNC) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 240 #define IP5_19_16 FM(VI1_DATA0) FM(MSIOF1_SS1) F_(0, 0) FM(D3) FM(MMC_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 241 #define IP5_23_20 FM(VI1_DATA1) FM(MSIOF1_SS2) F_(0, 0) FM(D4) FM(MMC_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 242 #define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 243 #define IP5_31_28 FM(VI1_DATA3) FM(CANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 244 #define IP6_3_0 FM(VI1_DATA4) FM(CANFD_CLK_B) F_(0, 0) FM(D7) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 245 #define IP6_7_4 FM(VI1_DATA5) F_(0, 0) F_(0, 0) FM(D8) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 246 #define IP6_11_8 FM(VI1_DATA6) F_(0, 0) F_(0, 0) FM(D9) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 247 #define IP6_15_12 FM(VI1_DATA7) F_(0, 0) F_(0, 0) FM(D10) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 248 #define IP6_19_16 FM(VI1_DATA8) F_(0, 0) F_(0, 0) FM(D11) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 249 #define IP6_23_20 FM(VI1_DATA9) FM(TCLK1_A) F_(0, 0) FM(D12) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 250 #define IP6_27_24 FM(VI1_DATA10) FM(TCLK2_A) F_(0, 0) FM(D13) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 251 #define IP6_31_28 FM(VI1_DATA11) FM(SCL4) F_(0, 0) FM(D14) FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 252 #define IP7_3_0 FM(VI1_FIELD) FM(SDA4) F_(0, 0) FM(D15) FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 253 #define IP7_7_4 FM(SCL0) F_(0, 0) F_(0, 0) FM(CLKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 254 #define IP7_11_8 FM(SDA0) F_(0, 0) F_(0, 0) FM(BS_N) FM(SCK0) FM(HSCK0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 255 #define IP7_15_12 FM(SCL1) F_(0, 0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(HCTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 256 #define IP7_19_16 FM(SDA1) F_(0, 0) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N) FM(HRTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 257 #define IP7_23_20 FM(SCL2) F_(0, 0) F_(0, 0) FM(WE1_N) FM(RX0) FM(HRX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 258 #define IP7_27_24 FM(SDA2) F_(0, 0) F_(0, 0) FM(EX_WAIT0) FM(TX0) FM(HTX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 259 #define IP7_31_28 FM(AVB_AVTP_MATCH) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 260 #define IP8_3_0 FM(AVB_AVTP_CAPTURE) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 261 #define IP8_7_4 FM(CANFD0_TX_A) FM(FXR_TXDA) FM(PWM0_B) FM(DU_DISP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 262 #define IP8_11_8 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 263 #define IP8_15_12 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 264 #define IP8_19_16 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 265 #define IP8_23_20 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 266 #define IP8_27_24 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 267 #define IP8_31_28 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 268 #define IP9_3_0 FM(IRQ4) F_(0, 0) F_(0, 0) FM(VI0_DATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 269 #define IP9_7_4 FM(IRQ5) F_(0, 0) F_(0, 0) FM(VI0_DATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 270 #define IP9_11_8 FM(MSIOF0_RXD) FM(DU_DR0) F_(0, 0) FM(VI0_DATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 271 #define IP9_15_12 FM(MSIOF0_TXD) FM(DU_DR1) F_(0, 0) FM(VI0_DATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 272 #define IP9_19_16 FM(MSIOF0_SCK) FM(DU_DG0) F_(0, 0) FM(VI0_DATA16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 273 #define IP9_23_20 FM(MSIOF0_SYNC) FM(DU_DG1) F_(0, 0) FM(VI0_DATA17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 274 #define IP9_27_24 FM(MSIOF0_SS1) FM(DU_DB0) FM(TCLK3) FM(VI0_DATA18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 275 #define IP9_31_28 FM(MSIOF0_SS2) FM(DU_DB1) FM(TCLK4) FM(VI0_DATA19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 276 #define IP10_3_0 FM(SCL3) F_(0, 0) F_(0, 0) FM(VI0_DATA20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 277 #define IP10_7_4 FM(SDA3) F_(0, 0) F_(0, 0) FM(VI0_DATA21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 278 #define IP10_11_8 FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) FM(VI0_DATA22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 279 #define IP10_15_12 FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) FM(VI0_DATA23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 280 #define IP10_19_16 FM(FSO_TOE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 281 #define IP10_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 282 #define IP10_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 283 #define IP10_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 284 285 #define PINMUX_GPSR \ 286 \ 287 GPSR2_29 \ 288 GPSR2_28 \ 289 GPSR1_27 GPSR2_27 \ 290 GPSR1_26 GPSR2_26 \ 291 GPSR1_25 GPSR2_25 \ 292 GPSR1_24 GPSR2_24 GPSR4_24 \ 293 GPSR1_23 GPSR2_23 GPSR4_23 \ 294 GPSR1_22 GPSR2_22 GPSR4_22 \ 295 GPSR0_21 GPSR1_21 GPSR2_21 GPSR4_21 \ 296 GPSR0_20 GPSR1_20 GPSR2_20 GPSR4_20 \ 297 GPSR0_19 GPSR1_19 GPSR2_19 GPSR4_19 \ 298 GPSR0_18 GPSR1_18 GPSR2_18 GPSR4_18 \ 299 GPSR0_17 GPSR1_17 GPSR2_17 GPSR4_17 \ 300 GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 GPSR4_16 \ 301 GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR4_15 \ 302 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 \ 303 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 \ 304 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 \ 305 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 \ 306 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 \ 307 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 \ 308 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 \ 309 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 \ 310 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 \ 311 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 \ 312 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 \ 313 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 \ 314 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 \ 315 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 \ 316 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 317 318 #define PINMUX_IPSR \ 319 \ 320 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \ 321 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \ 322 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \ 323 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \ 324 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \ 325 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \ 326 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ 327 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \ 328 \ 329 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ 330 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ 331 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ 332 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \ 333 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ 334 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ 335 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ 336 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ 337 \ 338 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 \ 339 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 \ 340 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 \ 341 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 \ 342 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 \ 343 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 \ 344 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 \ 345 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 346 347 /* MOD_SEL0 */ /* 0 */ /* 1 */ 348 #define MOD_SEL0_11 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) 349 #define MOD_SEL0_10 FM(SEL_GETHER_0) FM(SEL_GETHER_1) 350 #define MOD_SEL0_9 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1) 351 #define MOD_SEL0_8 FM(SEL_PWM0_0) FM(SEL_PWM0_1) 352 #define MOD_SEL0_7 FM(SEL_PWM1_0) FM(SEL_PWM1_1) 353 #define MOD_SEL0_6 FM(SEL_PWM2_0) FM(SEL_PWM2_1) 354 #define MOD_SEL0_5 FM(SEL_PWM3_0) FM(SEL_PWM3_1) 355 #define MOD_SEL0_4 FM(SEL_PWM4_0) FM(SEL_PWM4_1) 356 #define MOD_SEL0_2 FM(SEL_RSP_0) FM(SEL_RSP_1) 357 #define MOD_SEL0_1 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1) 358 #define MOD_SEL0_0 FM(SEL_TMU_0) FM(SEL_TMU_1) 359 360 #define PINMUX_MOD_SELS \ 361 \ 362 MOD_SEL0_11 \ 363 MOD_SEL0_10 \ 364 MOD_SEL0_9 \ 365 MOD_SEL0_8 \ 366 MOD_SEL0_7 \ 367 MOD_SEL0_6 \ 368 MOD_SEL0_5 \ 369 MOD_SEL0_4 \ 370 MOD_SEL0_2 \ 371 MOD_SEL0_1 \ 372 MOD_SEL0_0 373 374 enum { 375 PINMUX_RESERVED = 0, 376 377 PINMUX_DATA_BEGIN, 378 GP_ALL(DATA), 379 PINMUX_DATA_END, 380 381 #define F_(x, y) 382 #define FM(x) FN_##x, 383 PINMUX_FUNCTION_BEGIN, 384 GP_ALL(FN), 385 PINMUX_GPSR 386 PINMUX_IPSR 387 PINMUX_MOD_SELS 388 PINMUX_FUNCTION_END, 389 #undef F_ 390 #undef FM 391 392 #define F_(x, y) 393 #define FM(x) x##_MARK, 394 PINMUX_MARK_BEGIN, 395 PINMUX_GPSR 396 PINMUX_IPSR 397 PINMUX_MOD_SELS 398 PINMUX_MARK_END, 399 #undef F_ 400 #undef FM 401 }; 402 403 static const u16 pinmux_data[] = { 404 PINMUX_DATA_GP_ALL(), 405 406 PINMUX_SINGLE(AVB_RX_CTL), 407 PINMUX_SINGLE(AVB_RXC), 408 PINMUX_SINGLE(AVB_RD0), 409 PINMUX_SINGLE(AVB_RD1), 410 PINMUX_SINGLE(AVB_RD2), 411 PINMUX_SINGLE(AVB_RD3), 412 PINMUX_SINGLE(AVB_TX_CTL), 413 PINMUX_SINGLE(AVB_TXC), 414 PINMUX_SINGLE(AVB_TD0), 415 PINMUX_SINGLE(AVB_TD1), 416 PINMUX_SINGLE(AVB_TD2), 417 PINMUX_SINGLE(AVB_TD3), 418 PINMUX_SINGLE(AVB_TXCREFCLK), 419 PINMUX_SINGLE(AVB_MDIO), 420 PINMUX_SINGLE(AVB_MDC), 421 PINMUX_SINGLE(AVB_MAGIC), 422 PINMUX_SINGLE(AVB_PHY_INT), 423 PINMUX_SINGLE(AVB_LINK), 424 425 PINMUX_SINGLE(GETHER_RX_CTL), 426 PINMUX_SINGLE(GETHER_RXC), 427 PINMUX_SINGLE(GETHER_RD0), 428 PINMUX_SINGLE(GETHER_RD1), 429 PINMUX_SINGLE(GETHER_RD2), 430 PINMUX_SINGLE(GETHER_RD3), 431 PINMUX_SINGLE(GETHER_TX_CTL), 432 PINMUX_SINGLE(GETHER_TXC), 433 PINMUX_SINGLE(GETHER_TD0), 434 PINMUX_SINGLE(GETHER_TD1), 435 PINMUX_SINGLE(GETHER_TD2), 436 PINMUX_SINGLE(GETHER_TD3), 437 PINMUX_SINGLE(GETHER_TXCREFCLK), 438 PINMUX_SINGLE(GETHER_TXCREFCLK_MEGA), 439 PINMUX_SINGLE(GETHER_MDIO_A), 440 PINMUX_SINGLE(GETHER_MDC_A), 441 PINMUX_SINGLE(GETHER_MAGIC), 442 PINMUX_SINGLE(GETHER_PHY_INT_A), 443 PINMUX_SINGLE(GETHER_LINK_A), 444 445 PINMUX_SINGLE(QSPI0_SPCLK), 446 PINMUX_SINGLE(QSPI0_MOSI_IO0), 447 PINMUX_SINGLE(QSPI0_MISO_IO1), 448 PINMUX_SINGLE(QSPI0_IO2), 449 PINMUX_SINGLE(QSPI0_IO3), 450 PINMUX_SINGLE(QSPI0_SSL), 451 PINMUX_SINGLE(QSPI1_SPCLK), 452 PINMUX_SINGLE(QSPI1_MOSI_IO0), 453 PINMUX_SINGLE(QSPI1_MISO_IO1), 454 PINMUX_SINGLE(QSPI1_IO2), 455 PINMUX_SINGLE(QSPI1_IO3), 456 PINMUX_SINGLE(QSPI1_SSL), 457 PINMUX_SINGLE(RPC_RESET_N), 458 PINMUX_SINGLE(RPC_WP_N), 459 PINMUX_SINGLE(RPC_INT_N), 460 461 /* IPSR0 */ 462 PINMUX_IPSR_GPSR(IP0_3_0, DU_DR2), 463 PINMUX_IPSR_GPSR(IP0_3_0, SCK4), 464 PINMUX_IPSR_GPSR(IP0_3_0, GETHER_RMII_CRS_DV), 465 PINMUX_IPSR_GPSR(IP0_3_0, A0), 466 467 PINMUX_IPSR_GPSR(IP0_7_4, DU_DR3), 468 PINMUX_IPSR_GPSR(IP0_7_4, RX4), 469 PINMUX_IPSR_GPSR(IP0_7_4, GETHER_RMII_RX_ER), 470 PINMUX_IPSR_GPSR(IP0_7_4, A1), 471 472 PINMUX_IPSR_GPSR(IP0_11_8, DU_DR4), 473 PINMUX_IPSR_GPSR(IP0_11_8, TX4), 474 PINMUX_IPSR_GPSR(IP0_11_8, GETHER_RMII_RXD0), 475 PINMUX_IPSR_GPSR(IP0_11_8, A2), 476 477 PINMUX_IPSR_GPSR(IP0_15_12, DU_DR5), 478 PINMUX_IPSR_GPSR(IP0_15_12, CTS4_N), 479 PINMUX_IPSR_GPSR(IP0_15_12, GETHER_RMII_RXD1), 480 PINMUX_IPSR_GPSR(IP0_15_12, A3), 481 482 PINMUX_IPSR_GPSR(IP0_19_16, DU_DR6), 483 PINMUX_IPSR_GPSR(IP0_19_16, RTS4_N), 484 PINMUX_IPSR_GPSR(IP0_19_16, GETHER_RMII_TXD_EN), 485 PINMUX_IPSR_GPSR(IP0_19_16, A4), 486 487 PINMUX_IPSR_GPSR(IP0_23_20, DU_DR7), 488 PINMUX_IPSR_GPSR(IP0_23_20, GETHER_RMII_TXD0), 489 PINMUX_IPSR_GPSR(IP0_23_20, A5), 490 491 PINMUX_IPSR_GPSR(IP0_27_24, DU_DG2), 492 PINMUX_IPSR_GPSR(IP0_27_24, GETHER_RMII_TXD1), 493 PINMUX_IPSR_GPSR(IP0_27_24, A6), 494 495 PINMUX_IPSR_GPSR(IP0_31_28, DU_DG3), 496 PINMUX_IPSR_GPSR(IP0_31_28, CPG_CPCKOUT), 497 PINMUX_IPSR_GPSR(IP0_31_28, GETHER_RMII_REFCLK), 498 PINMUX_IPSR_GPSR(IP0_31_28, A7), 499 PINMUX_IPSR_GPSR(IP0_31_28, PWMFSW0), 500 501 /* IPSR1 */ 502 PINMUX_IPSR_GPSR(IP1_3_0, DU_DG4), 503 PINMUX_IPSR_GPSR(IP1_3_0, SCL5), 504 PINMUX_IPSR_GPSR(IP1_3_0, A8), 505 506 PINMUX_IPSR_GPSR(IP1_7_4, DU_DG5), 507 PINMUX_IPSR_GPSR(IP1_7_4, SDA5), 508 PINMUX_IPSR_MSEL(IP1_7_4, GETHER_MDC_B, SEL_GETHER_1), 509 PINMUX_IPSR_GPSR(IP1_7_4, A9), 510 511 PINMUX_IPSR_GPSR(IP1_11_8, DU_DG6), 512 PINMUX_IPSR_MSEL(IP1_11_8, SCIF_CLK_A, SEL_HSCIF0_0), 513 PINMUX_IPSR_MSEL(IP1_11_8, GETHER_MDIO_B, SEL_GETHER_1), 514 PINMUX_IPSR_GPSR(IP1_11_8, A10), 515 516 PINMUX_IPSR_GPSR(IP1_15_12, DU_DG7), 517 PINMUX_IPSR_MSEL(IP1_15_12, HRX0_A, SEL_HSCIF0_0), 518 PINMUX_IPSR_GPSR(IP1_15_12, A11), 519 520 PINMUX_IPSR_GPSR(IP1_19_16, DU_DB2), 521 PINMUX_IPSR_MSEL(IP1_19_16, HSCK0_A, SEL_HSCIF0_0), 522 PINMUX_IPSR_GPSR(IP1_19_16, A12), 523 PINMUX_IPSR_GPSR(IP1_19_16, IRQ1), 524 525 PINMUX_IPSR_GPSR(IP1_23_20, DU_DB3), 526 PINMUX_IPSR_MSEL(IP1_23_20, HRTS0_N_A, SEL_HSCIF0_0), 527 PINMUX_IPSR_GPSR(IP1_23_20, A13), 528 PINMUX_IPSR_GPSR(IP1_23_20, IRQ2), 529 530 PINMUX_IPSR_GPSR(IP1_27_24, DU_DB4), 531 PINMUX_IPSR_MSEL(IP1_27_24, HCTS0_N_A, SEL_HSCIF0_0), 532 PINMUX_IPSR_GPSR(IP1_27_24, A14), 533 PINMUX_IPSR_GPSR(IP1_27_24, IRQ3), 534 535 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB5), 536 PINMUX_IPSR_MSEL(IP1_31_28, HTX0_A, SEL_HSCIF0_0), 537 PINMUX_IPSR_MSEL(IP1_31_28, PWM0_A, SEL_PWM0_0), 538 PINMUX_IPSR_GPSR(IP1_31_28, A15), 539 540 /* IPSR2 */ 541 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB6), 542 PINMUX_IPSR_GPSR(IP2_3_0, MSIOF3_RXD), 543 PINMUX_IPSR_GPSR(IP2_3_0, A16), 544 545 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB7), 546 PINMUX_IPSR_GPSR(IP2_7_4, MSIOF3_TXD), 547 PINMUX_IPSR_GPSR(IP2_7_4, A17), 548 549 PINMUX_IPSR_GPSR(IP2_11_8, DU_DOTCLKOUT), 550 PINMUX_IPSR_GPSR(IP2_11_8, MSIOF3_SS1), 551 PINMUX_IPSR_MSEL(IP2_11_8, GETHER_LINK_B, SEL_GETHER_1), 552 PINMUX_IPSR_GPSR(IP2_11_8, A18), 553 554 PINMUX_IPSR_GPSR(IP2_15_12, DU_EXHSYNC_DU_HSYNC), 555 PINMUX_IPSR_GPSR(IP2_15_12, MSIOF3_SS2), 556 PINMUX_IPSR_MSEL(IP2_15_12, GETHER_PHY_INT_B, SEL_GETHER_1), 557 PINMUX_IPSR_GPSR(IP2_15_12, A19), 558 PINMUX_IPSR_GPSR(IP2_15_12, FXR_TXENA_N), 559 560 PINMUX_IPSR_GPSR(IP2_19_16, DU_EXVSYNC_DU_VSYNC), 561 PINMUX_IPSR_GPSR(IP2_19_16, MSIOF3_SCK), 562 PINMUX_IPSR_GPSR(IP2_19_16, FXR_TXENB_N), 563 564 PINMUX_IPSR_GPSR(IP2_23_20, DU_EXODDF_DU_ODDF_DISP_CDE), 565 PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC), 566 567 PINMUX_IPSR_GPSR(IP2_27_24, IRQ0), 568 569 PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK), 570 PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK), 571 PINMUX_IPSR_GPSR(IP2_31_28, SCK3), 572 PINMUX_IPSR_GPSR(IP2_31_28, HSCK3), 573 574 /* IPSR3 */ 575 PINMUX_IPSR_GPSR(IP3_3_0, VI0_CLKENB), 576 PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_RXD), 577 PINMUX_IPSR_GPSR(IP3_3_0, RX3), 578 PINMUX_IPSR_GPSR(IP3_3_0, RD_WR_N), 579 PINMUX_IPSR_GPSR(IP3_3_0, HCTS3_N), 580 581 PINMUX_IPSR_GPSR(IP3_7_4, VI0_HSYNC_N), 582 PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD), 583 PINMUX_IPSR_GPSR(IP3_7_4, TX3), 584 PINMUX_IPSR_GPSR(IP3_7_4, HRTS3_N), 585 586 PINMUX_IPSR_GPSR(IP3_11_8, VI0_VSYNC_N), 587 PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_SYNC), 588 PINMUX_IPSR_GPSR(IP3_11_8, CTS3_N), 589 PINMUX_IPSR_GPSR(IP3_11_8, HTX3), 590 591 PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0), 592 PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1), 593 PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N), 594 PINMUX_IPSR_GPSR(IP3_15_12, HRX3), 595 596 PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1), 597 PINMUX_IPSR_GPSR(IP3_19_16, MSIOF2_SS2), 598 PINMUX_IPSR_GPSR(IP3_19_16, SCK1), 599 PINMUX_IPSR_MSEL(IP3_19_16, SPEEDIN_A, SEL_RSP_0), 600 601 PINMUX_IPSR_GPSR(IP3_23_20, VI0_DATA2), 602 PINMUX_IPSR_GPSR(IP3_23_20, AVB_AVTP_PPS), 603 604 PINMUX_IPSR_GPSR(IP3_27_24, VI0_DATA3), 605 PINMUX_IPSR_GPSR(IP3_27_24, HSCK1), 606 607 PINMUX_IPSR_GPSR(IP3_31_28, VI0_DATA4), 608 PINMUX_IPSR_GPSR(IP3_31_28, HRTS1_N), 609 PINMUX_IPSR_MSEL(IP3_31_28, RX1_A, SEL_SCIF1_0), 610 611 /* IPSR4 */ 612 PINMUX_IPSR_GPSR(IP4_3_0, VI0_DATA5), 613 PINMUX_IPSR_GPSR(IP4_3_0, HCTS1_N), 614 PINMUX_IPSR_MSEL(IP4_3_0, TX1_A, SEL_SCIF1_0), 615 616 PINMUX_IPSR_GPSR(IP4_7_4, VI0_DATA6), 617 PINMUX_IPSR_GPSR(IP4_7_4, HTX1), 618 PINMUX_IPSR_GPSR(IP4_7_4, CTS1_N), 619 620 PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7), 621 PINMUX_IPSR_GPSR(IP4_11_8, HRX1), 622 PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N), 623 624 PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8), 625 PINMUX_IPSR_GPSR(IP4_15_12, HSCK2), 626 627 PINMUX_IPSR_GPSR(IP4_19_16, VI0_DATA9), 628 PINMUX_IPSR_GPSR(IP4_19_16, HCTS2_N), 629 PINMUX_IPSR_MSEL(IP4_19_16, PWM1_A, SEL_PWM1_0), 630 631 PINMUX_IPSR_GPSR(IP4_23_20, VI0_DATA10), 632 PINMUX_IPSR_GPSR(IP4_23_20, HRTS2_N), 633 PINMUX_IPSR_MSEL(IP4_23_20, PWM2_A, SEL_PWM2_0), 634 635 PINMUX_IPSR_GPSR(IP4_27_24, VI0_DATA11), 636 PINMUX_IPSR_GPSR(IP4_27_24, HTX2), 637 PINMUX_IPSR_MSEL(IP4_27_24, PWM3_A, SEL_PWM3_0), 638 639 PINMUX_IPSR_GPSR(IP4_31_28, VI0_FIELD), 640 PINMUX_IPSR_GPSR(IP4_31_28, HRX2), 641 PINMUX_IPSR_MSEL(IP4_31_28, PWM4_A, SEL_PWM4_0), 642 PINMUX_IPSR_GPSR(IP4_31_28, CS1_N), 643 644 /* IPSR5 */ 645 PINMUX_IPSR_GPSR(IP5_3_0, VI1_CLK), 646 PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD), 647 PINMUX_IPSR_GPSR(IP5_3_0, CS0_N), 648 649 PINMUX_IPSR_GPSR(IP5_7_4, VI1_CLKENB), 650 PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD), 651 PINMUX_IPSR_GPSR(IP5_7_4, D0), 652 653 PINMUX_IPSR_GPSR(IP5_11_8, VI1_HSYNC_N), 654 PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK), 655 PINMUX_IPSR_GPSR(IP5_11_8, D1), 656 657 PINMUX_IPSR_GPSR(IP5_15_12, VI1_VSYNC_N), 658 PINMUX_IPSR_GPSR(IP5_15_12, MSIOF1_SYNC), 659 PINMUX_IPSR_GPSR(IP5_15_12, D2), 660 661 PINMUX_IPSR_GPSR(IP5_19_16, VI1_DATA0), 662 PINMUX_IPSR_GPSR(IP5_19_16, MSIOF1_SS1), 663 PINMUX_IPSR_GPSR(IP5_19_16, D3), 664 PINMUX_IPSR_GPSR(IP5_19_16, MMC_WP), 665 666 PINMUX_IPSR_GPSR(IP5_23_20, VI1_DATA1), 667 PINMUX_IPSR_GPSR(IP5_23_20, MSIOF1_SS2), 668 PINMUX_IPSR_GPSR(IP5_23_20, D4), 669 PINMUX_IPSR_GPSR(IP5_23_20, MMC_CD), 670 671 PINMUX_IPSR_GPSR(IP5_27_24, VI1_DATA2), 672 PINMUX_IPSR_MSEL(IP5_27_24, CANFD0_TX_B, SEL_CANFD0_1), 673 PINMUX_IPSR_GPSR(IP5_27_24, D5), 674 PINMUX_IPSR_GPSR(IP5_27_24, MMC_DS), 675 676 PINMUX_IPSR_GPSR(IP5_31_28, VI1_DATA3), 677 PINMUX_IPSR_MSEL(IP5_31_28, CANFD0_RX_B, SEL_CANFD0_1), 678 PINMUX_IPSR_GPSR(IP5_31_28, D6), 679 PINMUX_IPSR_GPSR(IP5_31_28, MMC_CMD), 680 681 /* IPSR6 */ 682 PINMUX_IPSR_GPSR(IP6_3_0, VI1_DATA4), 683 PINMUX_IPSR_MSEL(IP6_3_0, CANFD_CLK_B, SEL_CANFD0_1), 684 PINMUX_IPSR_GPSR(IP6_3_0, D7), 685 PINMUX_IPSR_GPSR(IP6_3_0, MMC_D0), 686 687 PINMUX_IPSR_GPSR(IP6_7_4, VI1_DATA5), 688 PINMUX_IPSR_GPSR(IP6_7_4, D8), 689 PINMUX_IPSR_GPSR(IP6_7_4, MMC_D1), 690 691 PINMUX_IPSR_GPSR(IP6_11_8, VI1_DATA6), 692 PINMUX_IPSR_GPSR(IP6_11_8, D9), 693 PINMUX_IPSR_GPSR(IP6_11_8, MMC_D2), 694 695 PINMUX_IPSR_GPSR(IP6_15_12, VI1_DATA7), 696 PINMUX_IPSR_GPSR(IP6_15_12, D10), 697 PINMUX_IPSR_GPSR(IP6_15_12, MMC_D3), 698 699 PINMUX_IPSR_GPSR(IP6_19_16, VI1_DATA8), 700 PINMUX_IPSR_GPSR(IP6_19_16, D11), 701 PINMUX_IPSR_GPSR(IP6_19_16, MMC_CLK), 702 703 PINMUX_IPSR_GPSR(IP6_23_20, VI1_DATA9), 704 PINMUX_IPSR_MSEL(IP6_23_20, TCLK1_A, SEL_TMU_0), 705 PINMUX_IPSR_GPSR(IP6_23_20, D12), 706 PINMUX_IPSR_GPSR(IP6_23_20, MMC_D4), 707 708 PINMUX_IPSR_GPSR(IP6_27_24, VI1_DATA10), 709 PINMUX_IPSR_MSEL(IP6_27_24, TCLK2_A, SEL_TMU_0), 710 PINMUX_IPSR_GPSR(IP6_27_24, D13), 711 PINMUX_IPSR_GPSR(IP6_27_24, MMC_D5), 712 713 PINMUX_IPSR_GPSR(IP6_31_28, VI1_DATA11), 714 PINMUX_IPSR_GPSR(IP6_31_28, SCL4), 715 PINMUX_IPSR_GPSR(IP6_31_28, D14), 716 PINMUX_IPSR_GPSR(IP6_31_28, MMC_D6), 717 718 /* IPSR7 */ 719 PINMUX_IPSR_GPSR(IP7_3_0, VI1_FIELD), 720 PINMUX_IPSR_GPSR(IP7_3_0, SDA4), 721 PINMUX_IPSR_GPSR(IP7_3_0, D15), 722 PINMUX_IPSR_GPSR(IP7_3_0, MMC_D7), 723 724 PINMUX_IPSR_GPSR(IP7_7_4, SCL0), 725 PINMUX_IPSR_GPSR(IP7_7_4, CLKOUT), 726 727 PINMUX_IPSR_GPSR(IP7_11_8, SDA0), 728 PINMUX_IPSR_GPSR(IP7_11_8, BS_N), 729 PINMUX_IPSR_GPSR(IP7_11_8, SCK0), 730 PINMUX_IPSR_MSEL(IP7_11_8, HSCK0_B, SEL_HSCIF0_1), 731 732 PINMUX_IPSR_GPSR(IP7_15_12, SCL1), 733 PINMUX_IPSR_GPSR(IP7_15_12, TPU0TO2), 734 PINMUX_IPSR_GPSR(IP7_15_12, RD_N), 735 PINMUX_IPSR_GPSR(IP7_15_12, CTS0_N), 736 PINMUX_IPSR_GPSR(IP7_15_12, HCTS0_N_B), 737 738 PINMUX_IPSR_GPSR(IP7_19_16, SDA1), 739 PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3), 740 PINMUX_IPSR_GPSR(IP7_19_16, WE0_N), 741 PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N), 742 PINMUX_IPSR_MSEL(IP1_23_20, HRTS0_N_B, SEL_HSCIF0_1), 743 744 PINMUX_IPSR_GPSR(IP7_23_20, SCL2), 745 PINMUX_IPSR_GPSR(IP7_23_20, WE1_N), 746 PINMUX_IPSR_GPSR(IP7_23_20, RX0), 747 PINMUX_IPSR_MSEL(IP7_23_20, HRX0_B, SEL_HSCIF0_1), 748 749 PINMUX_IPSR_GPSR(IP7_27_24, SDA2), 750 PINMUX_IPSR_GPSR(IP7_27_24, EX_WAIT0), 751 PINMUX_IPSR_GPSR(IP7_27_24, TX0), 752 PINMUX_IPSR_MSEL(IP7_27_24, HTX0_B, SEL_HSCIF0_1), 753 754 PINMUX_IPSR_GPSR(IP7_31_28, AVB_AVTP_MATCH), 755 PINMUX_IPSR_GPSR(IP7_31_28, TPU0TO0), 756 757 /* IPSR8 */ 758 PINMUX_IPSR_GPSR(IP8_3_0, AVB_AVTP_CAPTURE), 759 PINMUX_IPSR_GPSR(IP8_3_0, TPU0TO1), 760 761 PINMUX_IPSR_MSEL(IP8_7_4, CANFD0_TX_A, SEL_CANFD0_0), 762 PINMUX_IPSR_GPSR(IP8_7_4, FXR_TXDA), 763 PINMUX_IPSR_MSEL(IP8_7_4, PWM0_B, SEL_PWM0_1), 764 PINMUX_IPSR_GPSR(IP8_7_4, DU_DISP), 765 766 PINMUX_IPSR_MSEL(IP8_11_8, CANFD0_RX_A, SEL_CANFD0_0), 767 PINMUX_IPSR_GPSR(IP8_11_8, RXDA_EXTFXR), 768 PINMUX_IPSR_MSEL(IP8_11_8, PWM1_B, SEL_PWM1_1), 769 PINMUX_IPSR_GPSR(IP8_11_8, DU_CDE), 770 771 PINMUX_IPSR_GPSR(IP8_15_12, CANFD1_TX), 772 PINMUX_IPSR_GPSR(IP8_15_12, FXR_TXDB), 773 PINMUX_IPSR_MSEL(IP8_15_12, PWM2_B, SEL_PWM2_1), 774 PINMUX_IPSR_MSEL(IP8_15_12, TCLK1_B, SEL_TMU_1), 775 PINMUX_IPSR_MSEL(IP8_15_12, TX1_B, SEL_SCIF1_1), 776 777 PINMUX_IPSR_GPSR(IP8_19_16, CANFD1_RX), 778 PINMUX_IPSR_GPSR(IP8_19_16, RXDB_EXTFXR), 779 PINMUX_IPSR_MSEL(IP8_19_16, PWM3_B, SEL_PWM3_1), 780 PINMUX_IPSR_MSEL(IP8_19_16, TCLK2_B, SEL_TMU_1), 781 PINMUX_IPSR_MSEL(IP8_19_16, RX1_B, SEL_SCIF1_1), 782 783 PINMUX_IPSR_MSEL(IP8_23_20, CANFD_CLK_A, SEL_CANFD0_0), 784 PINMUX_IPSR_GPSR(IP8_23_20, CLK_EXTFXR), 785 PINMUX_IPSR_MSEL(IP8_23_20, PWM4_B, SEL_PWM4_1), 786 PINMUX_IPSR_MSEL(IP8_23_20, SPEEDIN_B, SEL_RSP_1), 787 PINMUX_IPSR_MSEL(IP8_23_20, SCIF_CLK_B, SEL_HSCIF0_1), 788 789 PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKIN), 790 PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKEN_IN), 791 792 PINMUX_IPSR_GPSR(IP8_31_28, DIGRF_CLKOUT), 793 PINMUX_IPSR_GPSR(IP8_31_28, DIGRF_CLKEN_OUT), 794 795 /* IPSR9 */ 796 PINMUX_IPSR_GPSR(IP9_3_0, IRQ4), 797 PINMUX_IPSR_GPSR(IP9_3_0, VI0_DATA12), 798 799 PINMUX_IPSR_GPSR(IP9_7_4, IRQ5), 800 PINMUX_IPSR_GPSR(IP9_7_4, VI0_DATA13), 801 802 PINMUX_IPSR_GPSR(IP9_11_8, MSIOF0_RXD), 803 PINMUX_IPSR_GPSR(IP9_11_8, DU_DR0), 804 PINMUX_IPSR_GPSR(IP9_11_8, VI0_DATA14), 805 806 PINMUX_IPSR_GPSR(IP9_15_12, MSIOF0_TXD), 807 PINMUX_IPSR_GPSR(IP9_15_12, DU_DR1), 808 PINMUX_IPSR_GPSR(IP9_15_12, VI0_DATA15), 809 810 PINMUX_IPSR_GPSR(IP9_19_16, MSIOF0_SCK), 811 PINMUX_IPSR_GPSR(IP9_19_16, DU_DG0), 812 PINMUX_IPSR_GPSR(IP9_19_16, VI0_DATA16), 813 814 PINMUX_IPSR_GPSR(IP9_23_20, MSIOF0_SYNC), 815 PINMUX_IPSR_GPSR(IP9_23_20, DU_DG1), 816 PINMUX_IPSR_GPSR(IP9_23_20, VI0_DATA17), 817 818 PINMUX_IPSR_GPSR(IP9_27_24, MSIOF0_SS1), 819 PINMUX_IPSR_GPSR(IP9_27_24, DU_DB0), 820 PINMUX_IPSR_GPSR(IP9_27_24, TCLK3), 821 PINMUX_IPSR_GPSR(IP9_27_24, VI0_DATA18), 822 823 PINMUX_IPSR_GPSR(IP9_31_28, MSIOF0_SS2), 824 PINMUX_IPSR_GPSR(IP9_31_28, DU_DB1), 825 PINMUX_IPSR_GPSR(IP9_31_28, TCLK4), 826 PINMUX_IPSR_GPSR(IP9_31_28, VI0_DATA19), 827 828 /* IPSR10 */ 829 PINMUX_IPSR_GPSR(IP10_3_0, SCL3), 830 PINMUX_IPSR_GPSR(IP10_3_0, VI0_DATA20), 831 832 PINMUX_IPSR_GPSR(IP10_7_4, SDA3), 833 PINMUX_IPSR_GPSR(IP10_7_4, VI0_DATA21), 834 835 PINMUX_IPSR_GPSR(IP10_11_8, FSO_CFE_0_N), 836 PINMUX_IPSR_GPSR(IP10_11_8, VI0_DATA22), 837 838 PINMUX_IPSR_GPSR(IP10_15_12, FSO_CFE_1_N), 839 PINMUX_IPSR_GPSR(IP10_15_12, VI0_DATA23), 840 841 PINMUX_IPSR_GPSR(IP10_19_16, FSO_TOE_N), 842 }; 843 844 /* 845 * Pins not associated with a GPIO port. 846 */ 847 enum { 848 GP_ASSIGN_LAST(), 849 NOGP_ALL(), 850 }; 851 852 static const struct sh_pfc_pin pinmux_pins[] = { 853 PINMUX_GPIO_GP_ALL(), 854 PINMUX_NOGP_ALL(), 855 }; 856 857 /* - AVB -------------------------------------------------------------------- */ 858 static const unsigned int avb_link_pins[] = { 859 /* AVB_LINK */ 860 RCAR_GP_PIN(1, 18), 861 }; 862 static const unsigned int avb_link_mux[] = { 863 AVB_LINK_MARK, 864 }; 865 static const unsigned int avb_magic_pins[] = { 866 /* AVB_MAGIC */ 867 RCAR_GP_PIN(1, 16), 868 }; 869 static const unsigned int avb_magic_mux[] = { 870 AVB_MAGIC_MARK, 871 }; 872 static const unsigned int avb_phy_int_pins[] = { 873 /* AVB_PHY_INT */ 874 RCAR_GP_PIN(1, 17), 875 }; 876 static const unsigned int avb_phy_int_mux[] = { 877 AVB_PHY_INT_MARK, 878 }; 879 static const unsigned int avb_mdio_pins[] = { 880 /* AVB_MDC, AVB_MDIO */ 881 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), 882 }; 883 static const unsigned int avb_mdio_mux[] = { 884 AVB_MDC_MARK, AVB_MDIO_MARK, 885 }; 886 static const unsigned int avb_rgmii_pins[] = { 887 /* 888 * AVB_TX_CTL, AVB_TXC, AVB_TD0, AVB_TD1, AVB_TD2, AVB_TD3, 889 * AVB_RX_CTL, AVB_RXC, AVB_RD0, AVB_RD1, AVB_RD2, AVB_RD3, 890 */ 891 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), 892 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10), 893 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12), 894 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2), 895 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4), 896 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), 897 }; 898 static const unsigned int avb_rgmii_mux[] = { 899 AVB_TX_CTL_MARK, AVB_TXC_MARK, 900 AVB_TD0_MARK, AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK, 901 AVB_RX_CTL_MARK, AVB_RXC_MARK, 902 AVB_RD0_MARK, AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK, 903 }; 904 static const unsigned int avb_txcrefclk_pins[] = { 905 /* AVB_TXCREFCLK */ 906 RCAR_GP_PIN(1, 13), 907 }; 908 static const unsigned int avb_txcrefclk_mux[] = { 909 AVB_TXCREFCLK_MARK, 910 }; 911 static const unsigned int avb_avtp_pps_pins[] = { 912 /* AVB_AVTP_PPS */ 913 RCAR_GP_PIN(2, 6), 914 }; 915 static const unsigned int avb_avtp_pps_mux[] = { 916 AVB_AVTP_PPS_MARK, 917 }; 918 static const unsigned int avb_avtp_capture_pins[] = { 919 /* AVB_AVTP_CAPTURE */ 920 RCAR_GP_PIN(1, 20), 921 }; 922 static const unsigned int avb_avtp_capture_mux[] = { 923 AVB_AVTP_CAPTURE_MARK, 924 }; 925 static const unsigned int avb_avtp_match_pins[] = { 926 /* AVB_AVTP_MATCH */ 927 RCAR_GP_PIN(1, 19), 928 }; 929 static const unsigned int avb_avtp_match_mux[] = { 930 AVB_AVTP_MATCH_MARK, 931 }; 932 933 /* - CANFD0 ----------------------------------------------------------------- */ 934 static const unsigned int canfd0_data_a_pins[] = { 935 /* CANFD0_TX, CANFD0_RX */ 936 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), 937 }; 938 static const unsigned int canfd0_data_a_mux[] = { 939 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK, 940 }; 941 static const unsigned int canfd0_data_b_pins[] = { 942 /* CANFD0_TX, CANFD0_RX */ 943 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 944 }; 945 static const unsigned int canfd0_data_b_mux[] = { 946 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK, 947 }; 948 949 /* - CANFD1 ----------------------------------------------------------------- */ 950 static const unsigned int canfd1_data_pins[] = { 951 /* CANFD1_TX, CANFD1_RX */ 952 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 953 }; 954 static const unsigned int canfd1_data_mux[] = { 955 CANFD1_TX_MARK, CANFD1_RX_MARK, 956 }; 957 958 /* - CANFD Clock ------------------------------------------------------------ */ 959 static const unsigned int canfd_clk_a_pins[] = { 960 /* CANFD_CLK */ 961 RCAR_GP_PIN(1, 25), 962 }; 963 static const unsigned int canfd_clk_a_mux[] = { 964 CANFD_CLK_A_MARK, 965 }; 966 static const unsigned int canfd_clk_b_pins[] = { 967 /* CANFD_CLK */ 968 RCAR_GP_PIN(3, 8), 969 }; 970 static const unsigned int canfd_clk_b_mux[] = { 971 CANFD_CLK_B_MARK, 972 }; 973 974 /* - DU --------------------------------------------------------------------- */ 975 static const unsigned int du_rgb666_pins[] = { 976 /* DU_DR[7:2], DU_DG[7:2], DU_DB[7:2] */ 977 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), 978 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0), 979 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9), 980 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), 981 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15), 982 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12), 983 }; 984 static const unsigned int du_rgb666_mux[] = { 985 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, 986 DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK, 987 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, 988 DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK, 989 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, 990 DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK, 991 }; 992 static const unsigned int du_rgb888_pins[] = { 993 /* DU_DR[7:0], DU_DG[7:0], DU_DB[7:0] */ 994 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), 995 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0), 996 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), 997 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9), 998 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), 999 RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21), 1000 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15), 1001 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12), 1002 RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23), 1003 }; 1004 static const unsigned int du_rgb888_mux[] = { 1005 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, 1006 DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK, 1007 DU_DR1_MARK, DU_DR0_MARK, 1008 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, 1009 DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK, 1010 DU_DG1_MARK, DU_DG0_MARK, 1011 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, 1012 DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK, 1013 DU_DB1_MARK, DU_DB0_MARK, 1014 }; 1015 static const unsigned int du_clk_out_pins[] = { 1016 /* DU_DOTCLKOUT */ 1017 RCAR_GP_PIN(0, 18), 1018 }; 1019 static const unsigned int du_clk_out_mux[] = { 1020 DU_DOTCLKOUT_MARK, 1021 }; 1022 static const unsigned int du_sync_pins[] = { 1023 /* DU_EXVSYNC/DU_VSYNC, DU_EXHSYNC/DU_HSYNC */ 1024 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), 1025 }; 1026 static const unsigned int du_sync_mux[] = { 1027 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK, 1028 }; 1029 static const unsigned int du_oddf_pins[] = { 1030 /* DU_EXODDF/DU_ODDF/DISP/CDE */ 1031 RCAR_GP_PIN(0, 21), 1032 }; 1033 static const unsigned int du_oddf_mux[] = { 1034 DU_EXODDF_DU_ODDF_DISP_CDE_MARK, 1035 }; 1036 static const unsigned int du_cde_pins[] = { 1037 /* DU_CDE */ 1038 RCAR_GP_PIN(1, 22), 1039 }; 1040 static const unsigned int du_cde_mux[] = { 1041 DU_CDE_MARK, 1042 }; 1043 static const unsigned int du_disp_pins[] = { 1044 /* DU_DISP */ 1045 RCAR_GP_PIN(1, 21), 1046 }; 1047 static const unsigned int du_disp_mux[] = { 1048 DU_DISP_MARK, 1049 }; 1050 1051 /* - GETHER ----------------------------------------------------------------- */ 1052 static const unsigned int gether_link_a_pins[] = { 1053 /* GETHER_LINK */ 1054 RCAR_GP_PIN(4, 24), 1055 }; 1056 static const unsigned int gether_link_a_mux[] = { 1057 GETHER_LINK_A_MARK, 1058 }; 1059 static const unsigned int gether_phy_int_a_pins[] = { 1060 /* GETHER_PHY_INT */ 1061 RCAR_GP_PIN(4, 23), 1062 }; 1063 static const unsigned int gether_phy_int_a_mux[] = { 1064 GETHER_PHY_INT_A_MARK, 1065 }; 1066 static const unsigned int gether_mdio_a_pins[] = { 1067 /* GETHER_MDC, GETHER_MDIO */ 1068 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), 1069 }; 1070 static const unsigned int gether_mdio_a_mux[] = { 1071 GETHER_MDC_A_MARK, GETHER_MDIO_A_MARK, 1072 }; 1073 static const unsigned int gether_link_b_pins[] = { 1074 /* GETHER_LINK */ 1075 RCAR_GP_PIN(0, 18), 1076 }; 1077 static const unsigned int gether_link_b_mux[] = { 1078 GETHER_LINK_B_MARK, 1079 }; 1080 static const unsigned int gether_phy_int_b_pins[] = { 1081 /* GETHER_PHY_INT */ 1082 RCAR_GP_PIN(0, 19), 1083 }; 1084 static const unsigned int gether_phy_int_b_mux[] = { 1085 GETHER_PHY_INT_B_MARK, 1086 }; 1087 static const unsigned int gether_mdio_b_mux[] = { 1088 GETHER_MDC_B_MARK, GETHER_MDIO_B_MARK, 1089 }; 1090 static const unsigned int gether_mdio_b_pins[] = { 1091 /* GETHER_MDC, GETHER_MDIO */ 1092 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), 1093 }; 1094 static const unsigned int gether_magic_pins[] = { 1095 /* GETHER_MAGIC */ 1096 RCAR_GP_PIN(4, 22), 1097 }; 1098 static const unsigned int gether_magic_mux[] = { 1099 GETHER_MAGIC_MARK, 1100 }; 1101 static const unsigned int gether_rgmii_pins[] = { 1102 /* 1103 * GETHER_TX_CTL, GETHER_TXC, 1104 * GETHER_TD0, GETHER_TD1, GETHER_TD2, GETHER_TD3, 1105 * GETHER_RX_CTL, GETHER_RXC, 1106 * GETHER_RD0, GETHER_RD1, GETHER_RD2, GETHER_RD3, 1107 */ 1108 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13), 1109 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15), 1110 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17), 1111 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7), 1112 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), 1113 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), 1114 }; 1115 static const unsigned int gether_rgmii_mux[] = { 1116 GETHER_TX_CTL_MARK, GETHER_TXC_MARK, 1117 GETHER_TD0_MARK, GETHER_TD1_MARK, 1118 GETHER_TD2_MARK, GETHER_TD3_MARK, 1119 GETHER_RX_CTL_MARK, GETHER_RXC_MARK, 1120 GETHER_RD0_MARK, AVB_RD1_MARK, 1121 GETHER_RD2_MARK, AVB_RD3_MARK, 1122 }; 1123 static const unsigned int gether_txcrefclk_pins[] = { 1124 /* GETHER_TXCREFCLK */ 1125 RCAR_GP_PIN(4, 18), 1126 }; 1127 static const unsigned int gether_txcrefclk_mux[] = { 1128 GETHER_TXCREFCLK_MARK, 1129 }; 1130 static const unsigned int gether_txcrefclk_mega_pins[] = { 1131 /* GETHER_TXCREFCLK_MEGA */ 1132 RCAR_GP_PIN(4, 19), 1133 }; 1134 static const unsigned int gether_txcrefclk_mega_mux[] = { 1135 GETHER_TXCREFCLK_MEGA_MARK, 1136 }; 1137 static const unsigned int gether_rmii_pins[] = { 1138 /* 1139 * GETHER_RMII_CRS_DV, GETHER_RMII_RX_ER, 1140 * GETHER_RMII_RXD0, GETHER_RMII_RXD1, 1141 * GETHER_RMII_TXD_EN, GETHER_RMII_TXD0, 1142 * GETHER_RMII_TXD1, GETHER_RMII_REFCLK 1143 */ 1144 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 1145 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 1146 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 1147 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 1148 }; 1149 static const unsigned int gether_rmii_mux[] = { 1150 GETHER_RMII_CRS_DV_MARK, GETHER_RMII_RX_ER_MARK, 1151 GETHER_RMII_RXD0_MARK, GETHER_RMII_RXD1_MARK, 1152 GETHER_RMII_TXD_EN_MARK, GETHER_RMII_TXD0_MARK, 1153 GETHER_RMII_TXD1_MARK, GETHER_RMII_REFCLK_MARK, 1154 }; 1155 1156 /* - HSCIF0 ----------------------------------------------------------------- */ 1157 static const unsigned int hscif0_data_a_pins[] = { 1158 /* HRX0, HTX0 */ 1159 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 15), 1160 }; 1161 static const unsigned int hscif0_data_a_mux[] = { 1162 HRX0_A_MARK, HTX0_A_MARK, 1163 }; 1164 static const unsigned int hscif0_clk_a_pins[] = { 1165 /* HSCK0 */ 1166 RCAR_GP_PIN(0, 12), 1167 }; 1168 static const unsigned int hscif0_clk_a_mux[] = { 1169 HSCK0_A_MARK, 1170 }; 1171 static const unsigned int hscif0_ctrl_a_pins[] = { 1172 /* HRTS0#, HCTS0# */ 1173 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14), 1174 }; 1175 static const unsigned int hscif0_ctrl_a_mux[] = { 1176 HRTS0_N_A_MARK, HCTS0_N_A_MARK, 1177 }; 1178 static const unsigned int hscif0_data_b_pins[] = { 1179 /* HRX0, HTX0 */ 1180 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), 1181 }; 1182 static const unsigned int hscif0_data_b_mux[] = { 1183 HRX0_B_MARK, HTX0_B_MARK, 1184 }; 1185 static const unsigned int hscif0_clk_b_pins[] = { 1186 /* HSCK0 */ 1187 RCAR_GP_PIN(4, 1), 1188 }; 1189 static const unsigned int hscif0_clk_b_mux[] = { 1190 HSCK0_B_MARK, 1191 }; 1192 static const unsigned int hscif0_ctrl_b_pins[] = { 1193 /* HRTS0#, HCTS0# */ 1194 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2), 1195 }; 1196 static const unsigned int hscif0_ctrl_b_mux[] = { 1197 HRTS0_N_B_MARK, HCTS0_N_B_MARK, 1198 }; 1199 1200 /* - HSCIF1 ----------------------------------------------------------------- */ 1201 static const unsigned int hscif1_data_pins[] = { 1202 /* HRX1, HTX1 */ 1203 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10), 1204 }; 1205 static const unsigned int hscif1_data_mux[] = { 1206 HRX1_MARK, HTX1_MARK, 1207 }; 1208 static const unsigned int hscif1_clk_pins[] = { 1209 /* HSCK1 */ 1210 RCAR_GP_PIN(2, 7), 1211 }; 1212 static const unsigned int hscif1_clk_mux[] = { 1213 HSCK1_MARK, 1214 }; 1215 static const unsigned int hscif1_ctrl_pins[] = { 1216 /* HRTS1#, HCTS1# */ 1217 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 1218 }; 1219 static const unsigned int hscif1_ctrl_mux[] = { 1220 HRTS1_N_MARK, HCTS1_N_MARK, 1221 }; 1222 1223 /* - HSCIF2 ----------------------------------------------------------------- */ 1224 static const unsigned int hscif2_data_pins[] = { 1225 /* HRX2, HTX2 */ 1226 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15), 1227 }; 1228 static const unsigned int hscif2_data_mux[] = { 1229 HRX2_MARK, HTX2_MARK, 1230 }; 1231 static const unsigned int hscif2_clk_pins[] = { 1232 /* HSCK2 */ 1233 RCAR_GP_PIN(2, 12), 1234 }; 1235 static const unsigned int hscif2_clk_mux[] = { 1236 HSCK2_MARK, 1237 }; 1238 static const unsigned int hscif2_ctrl_pins[] = { 1239 /* HRTS2#, HCTS2# */ 1240 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), 1241 }; 1242 static const unsigned int hscif2_ctrl_mux[] = { 1243 HRTS2_N_MARK, HCTS2_N_MARK, 1244 }; 1245 1246 /* - HSCIF3 ----------------------------------------------------------------- */ 1247 static const unsigned int hscif3_data_pins[] = { 1248 /* HRX3, HTX3 */ 1249 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), 1250 }; 1251 static const unsigned int hscif3_data_mux[] = { 1252 HRX3_MARK, HTX3_MARK, 1253 }; 1254 static const unsigned int hscif3_clk_pins[] = { 1255 /* HSCK3 */ 1256 RCAR_GP_PIN(2, 0), 1257 }; 1258 static const unsigned int hscif3_clk_mux[] = { 1259 HSCK3_MARK, 1260 }; 1261 static const unsigned int hscif3_ctrl_pins[] = { 1262 /* HRTS3#, HCTS3# */ 1263 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1), 1264 }; 1265 static const unsigned int hscif3_ctrl_mux[] = { 1266 HRTS3_N_MARK, HCTS3_N_MARK, 1267 }; 1268 1269 /* - I2C0 ------------------------------------------------------------------- */ 1270 static const unsigned int i2c0_pins[] = { 1271 /* SDA0, SCL0 */ 1272 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0), 1273 }; 1274 static const unsigned int i2c0_mux[] = { 1275 SDA0_MARK, SCL0_MARK, 1276 }; 1277 1278 /* - I2C1 ------------------------------------------------------------------- */ 1279 static const unsigned int i2c1_pins[] = { 1280 /* SDA1, SCL1 */ 1281 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2), 1282 }; 1283 static const unsigned int i2c1_mux[] = { 1284 SDA1_MARK, SCL1_MARK, 1285 }; 1286 1287 /* - I2C2 ------------------------------------------------------------------- */ 1288 static const unsigned int i2c2_pins[] = { 1289 /* SDA2, SCL2 */ 1290 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4), 1291 }; 1292 static const unsigned int i2c2_mux[] = { 1293 SDA2_MARK, SCL2_MARK, 1294 }; 1295 1296 /* - I2C3 ------------------------------------------------------------------- */ 1297 static const unsigned int i2c3_pins[] = { 1298 /* SDA3, SCL3 */ 1299 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 25), 1300 }; 1301 static const unsigned int i2c3_mux[] = { 1302 SDA3_MARK, SCL3_MARK, 1303 }; 1304 1305 /* - I2C4 ------------------------------------------------------------------- */ 1306 static const unsigned int i2c4_pins[] = { 1307 /* SDA4, SCL4 */ 1308 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15), 1309 }; 1310 static const unsigned int i2c4_mux[] = { 1311 SDA4_MARK, SCL4_MARK, 1312 }; 1313 1314 /* - I2C5 ------------------------------------------------------------------- */ 1315 static const unsigned int i2c5_pins[] = { 1316 /* SDA5, SCL5 */ 1317 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8), 1318 }; 1319 static const unsigned int i2c5_mux[] = { 1320 SDA5_MARK, SCL5_MARK, 1321 }; 1322 1323 /* - INTC-EX ---------------------------------------------------------------- */ 1324 static const unsigned int intc_ex_irq0_pins[] = { 1325 /* IRQ0 */ 1326 RCAR_GP_PIN(1, 0), 1327 }; 1328 static const unsigned int intc_ex_irq0_mux[] = { 1329 IRQ0_MARK, 1330 }; 1331 static const unsigned int intc_ex_irq1_pins[] = { 1332 /* IRQ1 */ 1333 RCAR_GP_PIN(0, 12), 1334 }; 1335 static const unsigned int intc_ex_irq1_mux[] = { 1336 IRQ1_MARK, 1337 }; 1338 static const unsigned int intc_ex_irq2_pins[] = { 1339 /* IRQ2 */ 1340 RCAR_GP_PIN(0, 13), 1341 }; 1342 static const unsigned int intc_ex_irq2_mux[] = { 1343 IRQ2_MARK, 1344 }; 1345 static const unsigned int intc_ex_irq3_pins[] = { 1346 /* IRQ3 */ 1347 RCAR_GP_PIN(0, 14), 1348 }; 1349 static const unsigned int intc_ex_irq3_mux[] = { 1350 IRQ3_MARK, 1351 }; 1352 static const unsigned int intc_ex_irq4_pins[] = { 1353 /* IRQ4 */ 1354 RCAR_GP_PIN(2, 17), 1355 }; 1356 static const unsigned int intc_ex_irq4_mux[] = { 1357 IRQ4_MARK, 1358 }; 1359 static const unsigned int intc_ex_irq5_pins[] = { 1360 /* IRQ5 */ 1361 RCAR_GP_PIN(2, 18), 1362 }; 1363 static const unsigned int intc_ex_irq5_mux[] = { 1364 IRQ5_MARK, 1365 }; 1366 1367 /* - MMC -------------------------------------------------------------------- */ 1368 static const unsigned int mmc_data1_pins[] = { 1369 /* MMC_D0 */ 1370 RCAR_GP_PIN(3, 8), 1371 }; 1372 static const unsigned int mmc_data1_mux[] = { 1373 MMC_D0_MARK, 1374 }; 1375 static const unsigned int mmc_data4_pins[] = { 1376 /* MMC_D[0:3] */ 1377 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 1378 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 1379 }; 1380 static const unsigned int mmc_data4_mux[] = { 1381 MMC_D0_MARK, MMC_D1_MARK, 1382 MMC_D2_MARK, MMC_D3_MARK, 1383 }; 1384 static const unsigned int mmc_data8_pins[] = { 1385 /* MMC_D[0:7] */ 1386 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 1387 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 1388 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), 1389 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), 1390 }; 1391 static const unsigned int mmc_data8_mux[] = { 1392 MMC_D0_MARK, MMC_D1_MARK, 1393 MMC_D2_MARK, MMC_D3_MARK, 1394 MMC_D4_MARK, MMC_D5_MARK, 1395 MMC_D6_MARK, MMC_D7_MARK, 1396 }; 1397 static const unsigned int mmc_ctrl_pins[] = { 1398 /* MMC_CLK, MMC_CMD */ 1399 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 7), 1400 }; 1401 static const unsigned int mmc_ctrl_mux[] = { 1402 MMC_CLK_MARK, MMC_CMD_MARK, 1403 }; 1404 static const unsigned int mmc_cd_pins[] = { 1405 /* MMC_CD */ 1406 RCAR_GP_PIN(3, 5), 1407 }; 1408 static const unsigned int mmc_cd_mux[] = { 1409 MMC_CD_MARK, 1410 }; 1411 static const unsigned int mmc_wp_pins[] = { 1412 /* MMC_WP */ 1413 RCAR_GP_PIN(3, 4), 1414 }; 1415 static const unsigned int mmc_wp_mux[] = { 1416 MMC_WP_MARK, 1417 }; 1418 static const unsigned int mmc_ds_pins[] = { 1419 /* MMC_DS */ 1420 RCAR_GP_PIN(3, 6), 1421 }; 1422 static const unsigned int mmc_ds_mux[] = { 1423 MMC_DS_MARK, 1424 }; 1425 1426 /* - MSIOF0 ----------------------------------------------------------------- */ 1427 static const unsigned int msiof0_clk_pins[] = { 1428 /* MSIOF0_SCK */ 1429 RCAR_GP_PIN(2, 21), 1430 }; 1431 static const unsigned int msiof0_clk_mux[] = { 1432 MSIOF0_SCK_MARK, 1433 }; 1434 static const unsigned int msiof0_sync_pins[] = { 1435 /* MSIOF0_SYNC */ 1436 RCAR_GP_PIN(2, 22), 1437 }; 1438 static const unsigned int msiof0_sync_mux[] = { 1439 MSIOF0_SYNC_MARK, 1440 }; 1441 static const unsigned int msiof0_ss1_pins[] = { 1442 /* MSIOF0_SS1 */ 1443 RCAR_GP_PIN(2, 23), 1444 }; 1445 static const unsigned int msiof0_ss1_mux[] = { 1446 MSIOF0_SS1_MARK, 1447 }; 1448 static const unsigned int msiof0_ss2_pins[] = { 1449 /* MSIOF0_SS2 */ 1450 RCAR_GP_PIN(2, 24), 1451 }; 1452 static const unsigned int msiof0_ss2_mux[] = { 1453 MSIOF0_SS2_MARK, 1454 }; 1455 static const unsigned int msiof0_txd_pins[] = { 1456 /* MSIOF0_TXD */ 1457 RCAR_GP_PIN(2, 20), 1458 }; 1459 static const unsigned int msiof0_txd_mux[] = { 1460 MSIOF0_TXD_MARK, 1461 }; 1462 static const unsigned int msiof0_rxd_pins[] = { 1463 /* MSIOF0_RXD */ 1464 RCAR_GP_PIN(2, 19), 1465 }; 1466 static const unsigned int msiof0_rxd_mux[] = { 1467 MSIOF0_RXD_MARK, 1468 }; 1469 1470 /* - MSIOF1 ----------------------------------------------------------------- */ 1471 static const unsigned int msiof1_clk_pins[] = { 1472 /* MSIOF1_SCK */ 1473 RCAR_GP_PIN(3, 2), 1474 }; 1475 static const unsigned int msiof1_clk_mux[] = { 1476 MSIOF1_SCK_MARK, 1477 }; 1478 static const unsigned int msiof1_sync_pins[] = { 1479 /* MSIOF1_SYNC */ 1480 RCAR_GP_PIN(3, 3), 1481 }; 1482 static const unsigned int msiof1_sync_mux[] = { 1483 MSIOF1_SYNC_MARK, 1484 }; 1485 static const unsigned int msiof1_ss1_pins[] = { 1486 /* MSIOF1_SS1 */ 1487 RCAR_GP_PIN(3, 4), 1488 }; 1489 static const unsigned int msiof1_ss1_mux[] = { 1490 MSIOF1_SS1_MARK, 1491 }; 1492 static const unsigned int msiof1_ss2_pins[] = { 1493 /* MSIOF1_SS2 */ 1494 RCAR_GP_PIN(3, 5), 1495 }; 1496 static const unsigned int msiof1_ss2_mux[] = { 1497 MSIOF1_SS2_MARK, 1498 }; 1499 static const unsigned int msiof1_txd_pins[] = { 1500 /* MSIOF1_TXD */ 1501 RCAR_GP_PIN(3, 1), 1502 }; 1503 static const unsigned int msiof1_txd_mux[] = { 1504 MSIOF1_TXD_MARK, 1505 }; 1506 static const unsigned int msiof1_rxd_pins[] = { 1507 /* MSIOF1_RXD */ 1508 RCAR_GP_PIN(3, 0), 1509 }; 1510 static const unsigned int msiof1_rxd_mux[] = { 1511 MSIOF1_RXD_MARK, 1512 }; 1513 1514 /* - MSIOF2 ----------------------------------------------------------------- */ 1515 static const unsigned int msiof2_clk_pins[] = { 1516 /* MSIOF2_SCK */ 1517 RCAR_GP_PIN(2, 0), 1518 }; 1519 static const unsigned int msiof2_clk_mux[] = { 1520 MSIOF2_SCK_MARK, 1521 }; 1522 static const unsigned int msiof2_sync_pins[] = { 1523 /* MSIOF2_SYNC */ 1524 RCAR_GP_PIN(2, 3), 1525 }; 1526 static const unsigned int msiof2_sync_mux[] = { 1527 MSIOF2_SYNC_MARK, 1528 }; 1529 static const unsigned int msiof2_ss1_pins[] = { 1530 /* MSIOF2_SS1 */ 1531 RCAR_GP_PIN(2, 4), 1532 }; 1533 static const unsigned int msiof2_ss1_mux[] = { 1534 MSIOF2_SS1_MARK, 1535 }; 1536 static const unsigned int msiof2_ss2_pins[] = { 1537 /* MSIOF2_SS2 */ 1538 RCAR_GP_PIN(2, 5), 1539 }; 1540 static const unsigned int msiof2_ss2_mux[] = { 1541 MSIOF2_SS2_MARK, 1542 }; 1543 static const unsigned int msiof2_txd_pins[] = { 1544 /* MSIOF2_TXD */ 1545 RCAR_GP_PIN(2, 2), 1546 }; 1547 static const unsigned int msiof2_txd_mux[] = { 1548 MSIOF2_TXD_MARK, 1549 }; 1550 static const unsigned int msiof2_rxd_pins[] = { 1551 /* MSIOF2_RXD */ 1552 RCAR_GP_PIN(2, 1), 1553 }; 1554 static const unsigned int msiof2_rxd_mux[] = { 1555 MSIOF2_RXD_MARK, 1556 }; 1557 1558 /* - MSIOF3 ----------------------------------------------------------------- */ 1559 static const unsigned int msiof3_clk_pins[] = { 1560 /* MSIOF3_SCK */ 1561 RCAR_GP_PIN(0, 20), 1562 }; 1563 static const unsigned int msiof3_clk_mux[] = { 1564 MSIOF3_SCK_MARK, 1565 }; 1566 static const unsigned int msiof3_sync_pins[] = { 1567 /* MSIOF3_SYNC */ 1568 RCAR_GP_PIN(0, 21), 1569 }; 1570 static const unsigned int msiof3_sync_mux[] = { 1571 MSIOF3_SYNC_MARK, 1572 }; 1573 static const unsigned int msiof3_ss1_pins[] = { 1574 /* MSIOF3_SS1 */ 1575 RCAR_GP_PIN(0, 18), 1576 }; 1577 static const unsigned int msiof3_ss1_mux[] = { 1578 MSIOF3_SS1_MARK, 1579 }; 1580 static const unsigned int msiof3_ss2_pins[] = { 1581 /* MSIOF3_SS2 */ 1582 RCAR_GP_PIN(0, 19), 1583 }; 1584 static const unsigned int msiof3_ss2_mux[] = { 1585 MSIOF3_SS2_MARK, 1586 }; 1587 static const unsigned int msiof3_txd_pins[] = { 1588 /* MSIOF3_TXD */ 1589 RCAR_GP_PIN(0, 17), 1590 }; 1591 static const unsigned int msiof3_txd_mux[] = { 1592 MSIOF3_TXD_MARK, 1593 }; 1594 static const unsigned int msiof3_rxd_pins[] = { 1595 /* MSIOF3_RXD */ 1596 RCAR_GP_PIN(0, 16), 1597 }; 1598 static const unsigned int msiof3_rxd_mux[] = { 1599 MSIOF3_RXD_MARK, 1600 }; 1601 1602 /* - PWM0 ------------------------------------------------------------------- */ 1603 static const unsigned int pwm0_a_pins[] = { 1604 /* PWM0 */ 1605 RCAR_GP_PIN(0, 15), 1606 }; 1607 static const unsigned int pwm0_a_mux[] = { 1608 PWM0_A_MARK, 1609 }; 1610 static const unsigned int pwm0_b_pins[] = { 1611 /* PWM0 */ 1612 RCAR_GP_PIN(1, 21), 1613 }; 1614 static const unsigned int pwm0_b_mux[] = { 1615 PWM0_B_MARK, 1616 }; 1617 1618 /* - PWM1 ------------------------------------------------------------------- */ 1619 static const unsigned int pwm1_a_pins[] = { 1620 /* PWM1 */ 1621 RCAR_GP_PIN(2, 13), 1622 }; 1623 static const unsigned int pwm1_a_mux[] = { 1624 PWM1_A_MARK, 1625 }; 1626 static const unsigned int pwm1_b_pins[] = { 1627 /* PWM1 */ 1628 RCAR_GP_PIN(1, 22), 1629 }; 1630 static const unsigned int pwm1_b_mux[] = { 1631 PWM1_B_MARK, 1632 }; 1633 1634 /* - PWM2 ------------------------------------------------------------------- */ 1635 static const unsigned int pwm2_a_pins[] = { 1636 /* PWM2 */ 1637 RCAR_GP_PIN(2, 14), 1638 }; 1639 static const unsigned int pwm2_a_mux[] = { 1640 PWM2_A_MARK, 1641 }; 1642 static const unsigned int pwm2_b_pins[] = { 1643 /* PWM2 */ 1644 RCAR_GP_PIN(1, 23), 1645 }; 1646 static const unsigned int pwm2_b_mux[] = { 1647 PWM2_B_MARK, 1648 }; 1649 1650 /* - PWM3 ------------------------------------------------------------------- */ 1651 static const unsigned int pwm3_a_pins[] = { 1652 /* PWM3 */ 1653 RCAR_GP_PIN(2, 15), 1654 }; 1655 static const unsigned int pwm3_a_mux[] = { 1656 PWM3_A_MARK, 1657 }; 1658 static const unsigned int pwm3_b_pins[] = { 1659 /* PWM3 */ 1660 RCAR_GP_PIN(1, 24), 1661 }; 1662 static const unsigned int pwm3_b_mux[] = { 1663 PWM3_B_MARK, 1664 }; 1665 1666 /* - PWM4 ------------------------------------------------------------------- */ 1667 static const unsigned int pwm4_a_pins[] = { 1668 /* PWM4 */ 1669 RCAR_GP_PIN(2, 16), 1670 }; 1671 static const unsigned int pwm4_a_mux[] = { 1672 PWM4_A_MARK, 1673 }; 1674 static const unsigned int pwm4_b_pins[] = { 1675 /* PWM4 */ 1676 RCAR_GP_PIN(1, 25), 1677 }; 1678 static const unsigned int pwm4_b_mux[] = { 1679 PWM4_B_MARK, 1680 }; 1681 1682 /* - QSPI0 ------------------------------------------------------------------ */ 1683 static const unsigned int qspi0_ctrl_pins[] = { 1684 /* SPCLK, SSL */ 1685 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 5), 1686 }; 1687 static const unsigned int qspi0_ctrl_mux[] = { 1688 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, 1689 }; 1690 static const unsigned int qspi0_data2_pins[] = { 1691 /* MOSI_IO0, MISO_IO1 */ 1692 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 1693 }; 1694 static const unsigned int qspi0_data2_mux[] = { 1695 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, 1696 }; 1697 static const unsigned int qspi0_data4_pins[] = { 1698 /* MOSI_IO0, MISO_IO1, IO2, IO3 */ 1699 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 1700 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), 1701 }; 1702 static const unsigned int qspi0_data4_mux[] = { 1703 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, 1704 QSPI0_IO2_MARK, QSPI0_IO3_MARK 1705 }; 1706 1707 /* - QSPI1 ------------------------------------------------------------------ */ 1708 static const unsigned int qspi1_ctrl_pins[] = { 1709 /* SPCLK, SSL */ 1710 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 11), 1711 }; 1712 static const unsigned int qspi1_ctrl_mux[] = { 1713 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, 1714 }; 1715 static const unsigned int qspi1_data2_pins[] = { 1716 /* MOSI_IO0, MISO_IO1 */ 1717 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), 1718 }; 1719 static const unsigned int qspi1_data2_mux[] = { 1720 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, 1721 }; 1722 static const unsigned int qspi1_data4_pins[] = { 1723 /* MOSI_IO0, MISO_IO1, IO2, IO3 */ 1724 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), 1725 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), 1726 }; 1727 static const unsigned int qspi1_data4_mux[] = { 1728 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, 1729 QSPI1_IO2_MARK, QSPI1_IO3_MARK 1730 }; 1731 1732 /* - RPC -------------------------------------------------------------------- */ 1733 static const unsigned int rpc_clk1_pins[] = { 1734 /* Octal-SPI flash: C/SCLK */ 1735 RCAR_GP_PIN(5, 0), 1736 }; 1737 static const unsigned int rpc_clk1_mux[] = { 1738 QSPI0_SPCLK_MARK, 1739 }; 1740 static const unsigned int rpc_clk2_pins[] = { 1741 /* HyperFlash: CK, CK# */ 1742 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6), 1743 }; 1744 static const unsigned int rpc_clk2_mux[] = { 1745 QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK, 1746 }; 1747 static const unsigned int rpc_ctrl_pins[] = { 1748 /* Octal-SPI flash: S#/CS, DQS */ 1749 /* HyperFlash: CS#, RDS */ 1750 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11), 1751 }; 1752 static const unsigned int rpc_ctrl_mux[] = { 1753 QSPI0_SSL_MARK, QSPI1_SSL_MARK, 1754 }; 1755 static const unsigned int rpc_data_pins[] = { 1756 /* DQ[0:7] */ 1757 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 1758 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), 1759 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), 1760 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), 1761 }; 1762 static const unsigned int rpc_data_mux[] = { 1763 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, 1764 QSPI0_IO2_MARK, QSPI0_IO3_MARK, 1765 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, 1766 QSPI1_IO2_MARK, QSPI1_IO3_MARK, 1767 }; 1768 static const unsigned int rpc_reset_pins[] = { 1769 /* RPC_RESET# */ 1770 RCAR_GP_PIN(5, 12), 1771 }; 1772 static const unsigned int rpc_reset_mux[] = { 1773 RPC_RESET_N_MARK, 1774 }; 1775 static const unsigned int rpc_int_pins[] = { 1776 /* RPC_INT# */ 1777 RCAR_GP_PIN(5, 14), 1778 }; 1779 static const unsigned int rpc_int_mux[] = { 1780 RPC_INT_N_MARK, 1781 }; 1782 static const unsigned int rpc_wp_pins[] = { 1783 /* RPC_WP# */ 1784 RCAR_GP_PIN(5, 13), 1785 }; 1786 static const unsigned int rpc_wp_mux[] = { 1787 RPC_WP_N_MARK, 1788 }; 1789 1790 /* - SCIF0 ------------------------------------------------------------------ */ 1791 static const unsigned int scif0_data_pins[] = { 1792 /* RX0, TX0 */ 1793 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), 1794 }; 1795 static const unsigned int scif0_data_mux[] = { 1796 RX0_MARK, TX0_MARK, 1797 }; 1798 static const unsigned int scif0_clk_pins[] = { 1799 /* SCK0 */ 1800 RCAR_GP_PIN(4, 1), 1801 }; 1802 static const unsigned int scif0_clk_mux[] = { 1803 SCK0_MARK, 1804 }; 1805 static const unsigned int scif0_ctrl_pins[] = { 1806 /* RTS0#, CTS0# */ 1807 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2), 1808 }; 1809 static const unsigned int scif0_ctrl_mux[] = { 1810 RTS0_N_MARK, CTS0_N_MARK, 1811 }; 1812 1813 /* - SCIF1 ------------------------------------------------------------------ */ 1814 static const unsigned int scif1_data_a_pins[] = { 1815 /* RX1, TX1 */ 1816 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 1817 }; 1818 static const unsigned int scif1_data_a_mux[] = { 1819 RX1_A_MARK, TX1_A_MARK, 1820 }; 1821 static const unsigned int scif1_clk_pins[] = { 1822 /* SCK1 */ 1823 RCAR_GP_PIN(2, 5), 1824 }; 1825 static const unsigned int scif1_clk_mux[] = { 1826 SCK1_MARK, 1827 }; 1828 static const unsigned int scif1_ctrl_pins[] = { 1829 /* RTS1#, CTS1# */ 1830 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10), 1831 }; 1832 static const unsigned int scif1_ctrl_mux[] = { 1833 RTS1_N_MARK, CTS1_N_MARK, 1834 }; 1835 static const unsigned int scif1_data_b_pins[] = { 1836 /* RX1, TX1 */ 1837 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23), 1838 }; 1839 static const unsigned int scif1_data_b_mux[] = { 1840 RX1_B_MARK, TX1_B_MARK, 1841 }; 1842 1843 /* - SCIF3 ------------------------------------------------------------------ */ 1844 static const unsigned int scif3_data_pins[] = { 1845 /* RX3, TX3 */ 1846 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), 1847 }; 1848 static const unsigned int scif3_data_mux[] = { 1849 RX3_MARK, TX3_MARK, 1850 }; 1851 static const unsigned int scif3_clk_pins[] = { 1852 /* SCK3 */ 1853 RCAR_GP_PIN(2, 0), 1854 }; 1855 static const unsigned int scif3_clk_mux[] = { 1856 SCK3_MARK, 1857 }; 1858 static const unsigned int scif3_ctrl_pins[] = { 1859 /* RTS3#, CTS3# */ 1860 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), 1861 }; 1862 static const unsigned int scif3_ctrl_mux[] = { 1863 RTS3_N_MARK, CTS3_N_MARK, 1864 }; 1865 1866 /* - SCIF4 ------------------------------------------------------------------ */ 1867 static const unsigned int scif4_data_pins[] = { 1868 /* RX4, TX4 */ 1869 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2), 1870 }; 1871 static const unsigned int scif4_data_mux[] = { 1872 RX4_MARK, TX4_MARK, 1873 }; 1874 static const unsigned int scif4_clk_pins[] = { 1875 /* SCK4 */ 1876 RCAR_GP_PIN(0, 0), 1877 }; 1878 static const unsigned int scif4_clk_mux[] = { 1879 SCK4_MARK, 1880 }; 1881 static const unsigned int scif4_ctrl_pins[] = { 1882 /* RTS4#, CTS4# */ 1883 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), 1884 }; 1885 static const unsigned int scif4_ctrl_mux[] = { 1886 RTS4_N_MARK, CTS4_N_MARK, 1887 }; 1888 1889 /* - SCIF Clock ------------------------------------------------------------- */ 1890 static const unsigned int scif_clk_a_pins[] = { 1891 /* SCIF_CLK */ 1892 RCAR_GP_PIN(0, 10), 1893 }; 1894 static const unsigned int scif_clk_a_mux[] = { 1895 SCIF_CLK_A_MARK, 1896 }; 1897 static const unsigned int scif_clk_b_pins[] = { 1898 /* SCIF_CLK */ 1899 RCAR_GP_PIN(1, 25), 1900 }; 1901 static const unsigned int scif_clk_b_mux[] = { 1902 SCIF_CLK_B_MARK, 1903 }; 1904 1905 /* - TMU -------------------------------------------------------------------- */ 1906 static const unsigned int tmu_tclk1_a_pins[] = { 1907 /* TCLK1 */ 1908 RCAR_GP_PIN(3, 13), 1909 }; 1910 static const unsigned int tmu_tclk1_a_mux[] = { 1911 TCLK1_A_MARK, 1912 }; 1913 static const unsigned int tmu_tclk1_b_pins[] = { 1914 /* TCLK1 */ 1915 RCAR_GP_PIN(1, 23), 1916 }; 1917 static const unsigned int tmu_tclk1_b_mux[] = { 1918 TCLK1_B_MARK, 1919 }; 1920 static const unsigned int tmu_tclk2_a_pins[] = { 1921 /* TCLK2 */ 1922 RCAR_GP_PIN(3, 14), 1923 }; 1924 static const unsigned int tmu_tclk2_a_mux[] = { 1925 TCLK2_A_MARK, 1926 }; 1927 static const unsigned int tmu_tclk2_b_pins[] = { 1928 /* TCLK2 */ 1929 RCAR_GP_PIN(1, 24), 1930 }; 1931 static const unsigned int tmu_tclk2_b_mux[] = { 1932 TCLK2_B_MARK, 1933 }; 1934 1935 /* - TPU ------------------------------------------------------------------- */ 1936 static const unsigned int tpu_to0_pins[] = { 1937 /* TPU0TO0 */ 1938 RCAR_GP_PIN(1, 19), 1939 }; 1940 static const unsigned int tpu_to0_mux[] = { 1941 TPU0TO0_MARK, 1942 }; 1943 static const unsigned int tpu_to1_pins[] = { 1944 /* TPU0TO1 */ 1945 RCAR_GP_PIN(1, 20), 1946 }; 1947 static const unsigned int tpu_to1_mux[] = { 1948 TPU0TO1_MARK, 1949 }; 1950 static const unsigned int tpu_to2_pins[] = { 1951 /* TPU0TO2 */ 1952 RCAR_GP_PIN(4, 2), 1953 }; 1954 static const unsigned int tpu_to2_mux[] = { 1955 TPU0TO2_MARK, 1956 }; 1957 static const unsigned int tpu_to3_pins[] = { 1958 /* TPU0TO3 */ 1959 RCAR_GP_PIN(4, 3), 1960 }; 1961 static const unsigned int tpu_to3_mux[] = { 1962 TPU0TO3_MARK, 1963 }; 1964 1965 /* - VIN0 ------------------------------------------------------------------- */ 1966 static const union vin_data vin0_data_pins = { 1967 .data24 = { 1968 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 1969 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 1970 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 1971 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), 1972 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), 1973 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), 1974 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), 1975 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), 1976 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), 1977 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24), 1978 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26), 1979 RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28), 1980 }, 1981 }; 1982 static const union vin_data vin0_data_mux = { 1983 .data24 = { 1984 VI0_DATA0_MARK, VI0_DATA1_MARK, 1985 VI0_DATA2_MARK, VI0_DATA3_MARK, 1986 VI0_DATA4_MARK, VI0_DATA5_MARK, 1987 VI0_DATA6_MARK, VI0_DATA7_MARK, 1988 VI0_DATA8_MARK, VI0_DATA9_MARK, 1989 VI0_DATA10_MARK, VI0_DATA11_MARK, 1990 VI0_DATA12_MARK, VI0_DATA13_MARK, 1991 VI0_DATA14_MARK, VI0_DATA15_MARK, 1992 VI0_DATA16_MARK, VI0_DATA17_MARK, 1993 VI0_DATA18_MARK, VI0_DATA19_MARK, 1994 VI0_DATA20_MARK, VI0_DATA21_MARK, 1995 VI0_DATA22_MARK, VI0_DATA23_MARK, 1996 }, 1997 }; 1998 static const unsigned int vin0_data18_pins[] = { 1999 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 2000 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 2001 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), 2002 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), 2003 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), 2004 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), 2005 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24), 2006 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26), 2007 RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28), 2008 }; 2009 static const unsigned int vin0_data18_mux[] = { 2010 VI0_DATA2_MARK, VI0_DATA3_MARK, 2011 VI0_DATA4_MARK, VI0_DATA5_MARK, 2012 VI0_DATA6_MARK, VI0_DATA7_MARK, 2013 VI0_DATA10_MARK, VI0_DATA11_MARK, 2014 VI0_DATA12_MARK, VI0_DATA13_MARK, 2015 VI0_DATA14_MARK, VI0_DATA15_MARK, 2016 VI0_DATA18_MARK, VI0_DATA19_MARK, 2017 VI0_DATA20_MARK, VI0_DATA21_MARK, 2018 VI0_DATA22_MARK, VI0_DATA23_MARK, 2019 }; 2020 static const unsigned int vin0_sync_pins[] = { 2021 /* VI0_VSYNC#, VI0_HSYNC# */ 2022 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2), 2023 }; 2024 static const unsigned int vin0_sync_mux[] = { 2025 VI0_VSYNC_N_MARK, VI0_HSYNC_N_MARK, 2026 }; 2027 static const unsigned int vin0_field_pins[] = { 2028 /* VI0_FIELD */ 2029 RCAR_GP_PIN(2, 16), 2030 }; 2031 static const unsigned int vin0_field_mux[] = { 2032 VI0_FIELD_MARK, 2033 }; 2034 static const unsigned int vin0_clkenb_pins[] = { 2035 /* VI0_CLKENB */ 2036 RCAR_GP_PIN(2, 1), 2037 }; 2038 static const unsigned int vin0_clkenb_mux[] = { 2039 VI0_CLKENB_MARK, 2040 }; 2041 static const unsigned int vin0_clk_pins[] = { 2042 /* VI0_CLK */ 2043 RCAR_GP_PIN(2, 0), 2044 }; 2045 static const unsigned int vin0_clk_mux[] = { 2046 VI0_CLK_MARK, 2047 }; 2048 2049 /* - VIN1 ------------------------------------------------------------------- */ 2050 static const union vin_data12 vin1_data_pins = { 2051 .data12 = { 2052 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), 2053 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 2054 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 2055 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 2056 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), 2057 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), 2058 }, 2059 }; 2060 static const union vin_data12 vin1_data_mux = { 2061 .data12 = { 2062 VI1_DATA0_MARK, VI1_DATA1_MARK, 2063 VI1_DATA2_MARK, VI1_DATA3_MARK, 2064 VI1_DATA4_MARK, VI1_DATA5_MARK, 2065 VI1_DATA6_MARK, VI1_DATA7_MARK, 2066 VI1_DATA8_MARK, VI1_DATA9_MARK, 2067 VI1_DATA10_MARK, VI1_DATA11_MARK, 2068 }, 2069 }; 2070 static const unsigned int vin1_sync_pins[] = { 2071 /* VI1_VSYNC#, VI1_HSYNC# */ 2072 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2), 2073 }; 2074 static const unsigned int vin1_sync_mux[] = { 2075 VI1_VSYNC_N_MARK, VI1_HSYNC_N_MARK, 2076 }; 2077 static const unsigned int vin1_field_pins[] = { 2078 /* VI1_FIELD */ 2079 RCAR_GP_PIN(3, 16), 2080 }; 2081 static const unsigned int vin1_field_mux[] = { 2082 VI1_FIELD_MARK, 2083 }; 2084 static const unsigned int vin1_clkenb_pins[] = { 2085 /* VI1_CLKENB */ 2086 RCAR_GP_PIN(3, 1), 2087 }; 2088 static const unsigned int vin1_clkenb_mux[] = { 2089 VI1_CLKENB_MARK, 2090 }; 2091 static const unsigned int vin1_clk_pins[] = { 2092 /* VI1_CLK */ 2093 RCAR_GP_PIN(3, 0), 2094 }; 2095 static const unsigned int vin1_clk_mux[] = { 2096 VI1_CLK_MARK, 2097 }; 2098 2099 static const struct sh_pfc_pin_group pinmux_groups[] = { 2100 SH_PFC_PIN_GROUP(avb_link), 2101 SH_PFC_PIN_GROUP(avb_magic), 2102 SH_PFC_PIN_GROUP(avb_phy_int), 2103 SH_PFC_PIN_GROUP(avb_mdio), 2104 SH_PFC_PIN_GROUP(avb_rgmii), 2105 SH_PFC_PIN_GROUP(avb_txcrefclk), 2106 SH_PFC_PIN_GROUP(avb_avtp_pps), 2107 SH_PFC_PIN_GROUP(avb_avtp_capture), 2108 SH_PFC_PIN_GROUP(avb_avtp_match), 2109 SH_PFC_PIN_GROUP(canfd0_data_a), 2110 SH_PFC_PIN_GROUP(canfd0_data_b), 2111 SH_PFC_PIN_GROUP(canfd1_data), 2112 SH_PFC_PIN_GROUP(canfd_clk_a), 2113 SH_PFC_PIN_GROUP(canfd_clk_b), 2114 SH_PFC_PIN_GROUP(du_rgb666), 2115 SH_PFC_PIN_GROUP(du_rgb888), 2116 SH_PFC_PIN_GROUP(du_clk_out), 2117 SH_PFC_PIN_GROUP(du_sync), 2118 SH_PFC_PIN_GROUP(du_oddf), 2119 SH_PFC_PIN_GROUP(du_cde), 2120 SH_PFC_PIN_GROUP(du_disp), 2121 SH_PFC_PIN_GROUP(gether_link_a), 2122 SH_PFC_PIN_GROUP(gether_phy_int_a), 2123 SH_PFC_PIN_GROUP(gether_mdio_a), 2124 SH_PFC_PIN_GROUP(gether_link_b), 2125 SH_PFC_PIN_GROUP(gether_phy_int_b), 2126 SH_PFC_PIN_GROUP(gether_mdio_b), 2127 SH_PFC_PIN_GROUP(gether_magic), 2128 SH_PFC_PIN_GROUP(gether_rgmii), 2129 SH_PFC_PIN_GROUP(gether_txcrefclk), 2130 SH_PFC_PIN_GROUP(gether_txcrefclk_mega), 2131 SH_PFC_PIN_GROUP(gether_rmii), 2132 SH_PFC_PIN_GROUP(hscif0_data_a), 2133 SH_PFC_PIN_GROUP(hscif0_clk_a), 2134 SH_PFC_PIN_GROUP(hscif0_ctrl_a), 2135 SH_PFC_PIN_GROUP(hscif0_data_b), 2136 SH_PFC_PIN_GROUP(hscif0_clk_b), 2137 SH_PFC_PIN_GROUP(hscif0_ctrl_b), 2138 SH_PFC_PIN_GROUP(hscif1_data), 2139 SH_PFC_PIN_GROUP(hscif1_clk), 2140 SH_PFC_PIN_GROUP(hscif1_ctrl), 2141 SH_PFC_PIN_GROUP(hscif2_data), 2142 SH_PFC_PIN_GROUP(hscif2_clk), 2143 SH_PFC_PIN_GROUP(hscif2_ctrl), 2144 SH_PFC_PIN_GROUP(hscif3_data), 2145 SH_PFC_PIN_GROUP(hscif3_clk), 2146 SH_PFC_PIN_GROUP(hscif3_ctrl), 2147 SH_PFC_PIN_GROUP(i2c0), 2148 SH_PFC_PIN_GROUP(i2c1), 2149 SH_PFC_PIN_GROUP(i2c2), 2150 SH_PFC_PIN_GROUP(i2c3), 2151 SH_PFC_PIN_GROUP(i2c4), 2152 SH_PFC_PIN_GROUP(i2c5), 2153 SH_PFC_PIN_GROUP(intc_ex_irq0), 2154 SH_PFC_PIN_GROUP(intc_ex_irq1), 2155 SH_PFC_PIN_GROUP(intc_ex_irq2), 2156 SH_PFC_PIN_GROUP(intc_ex_irq3), 2157 SH_PFC_PIN_GROUP(intc_ex_irq4), 2158 SH_PFC_PIN_GROUP(intc_ex_irq5), 2159 SH_PFC_PIN_GROUP(mmc_data1), 2160 SH_PFC_PIN_GROUP(mmc_data4), 2161 SH_PFC_PIN_GROUP(mmc_data8), 2162 SH_PFC_PIN_GROUP(mmc_ctrl), 2163 SH_PFC_PIN_GROUP(mmc_cd), 2164 SH_PFC_PIN_GROUP(mmc_wp), 2165 SH_PFC_PIN_GROUP(mmc_ds), 2166 SH_PFC_PIN_GROUP(msiof0_clk), 2167 SH_PFC_PIN_GROUP(msiof0_sync), 2168 SH_PFC_PIN_GROUP(msiof0_ss1), 2169 SH_PFC_PIN_GROUP(msiof0_ss2), 2170 SH_PFC_PIN_GROUP(msiof0_txd), 2171 SH_PFC_PIN_GROUP(msiof0_rxd), 2172 SH_PFC_PIN_GROUP(msiof1_clk), 2173 SH_PFC_PIN_GROUP(msiof1_sync), 2174 SH_PFC_PIN_GROUP(msiof1_ss1), 2175 SH_PFC_PIN_GROUP(msiof1_ss2), 2176 SH_PFC_PIN_GROUP(msiof1_txd), 2177 SH_PFC_PIN_GROUP(msiof1_rxd), 2178 SH_PFC_PIN_GROUP(msiof2_clk), 2179 SH_PFC_PIN_GROUP(msiof2_sync), 2180 SH_PFC_PIN_GROUP(msiof2_ss1), 2181 SH_PFC_PIN_GROUP(msiof2_ss2), 2182 SH_PFC_PIN_GROUP(msiof2_txd), 2183 SH_PFC_PIN_GROUP(msiof2_rxd), 2184 SH_PFC_PIN_GROUP(msiof3_clk), 2185 SH_PFC_PIN_GROUP(msiof3_sync), 2186 SH_PFC_PIN_GROUP(msiof3_ss1), 2187 SH_PFC_PIN_GROUP(msiof3_ss2), 2188 SH_PFC_PIN_GROUP(msiof3_txd), 2189 SH_PFC_PIN_GROUP(msiof3_rxd), 2190 SH_PFC_PIN_GROUP(pwm0_a), 2191 SH_PFC_PIN_GROUP(pwm0_b), 2192 SH_PFC_PIN_GROUP(pwm1_a), 2193 SH_PFC_PIN_GROUP(pwm1_b), 2194 SH_PFC_PIN_GROUP(pwm2_a), 2195 SH_PFC_PIN_GROUP(pwm2_b), 2196 SH_PFC_PIN_GROUP(pwm3_a), 2197 SH_PFC_PIN_GROUP(pwm3_b), 2198 SH_PFC_PIN_GROUP(pwm4_a), 2199 SH_PFC_PIN_GROUP(pwm4_b), 2200 SH_PFC_PIN_GROUP(qspi0_ctrl), 2201 SH_PFC_PIN_GROUP(qspi0_data2), 2202 SH_PFC_PIN_GROUP(qspi0_data4), 2203 SH_PFC_PIN_GROUP(qspi1_ctrl), 2204 SH_PFC_PIN_GROUP(qspi1_data2), 2205 SH_PFC_PIN_GROUP(qspi1_data4), 2206 SH_PFC_PIN_GROUP(rpc_clk1), 2207 SH_PFC_PIN_GROUP(rpc_clk2), 2208 SH_PFC_PIN_GROUP(rpc_ctrl), 2209 SH_PFC_PIN_GROUP(rpc_data), 2210 SH_PFC_PIN_GROUP(rpc_reset), 2211 SH_PFC_PIN_GROUP(rpc_int), 2212 SH_PFC_PIN_GROUP(rpc_wp), 2213 SH_PFC_PIN_GROUP(scif0_data), 2214 SH_PFC_PIN_GROUP(scif0_clk), 2215 SH_PFC_PIN_GROUP(scif0_ctrl), 2216 SH_PFC_PIN_GROUP(scif1_data_a), 2217 SH_PFC_PIN_GROUP(scif1_clk), 2218 SH_PFC_PIN_GROUP(scif1_ctrl), 2219 SH_PFC_PIN_GROUP(scif1_data_b), 2220 SH_PFC_PIN_GROUP(scif3_data), 2221 SH_PFC_PIN_GROUP(scif3_clk), 2222 SH_PFC_PIN_GROUP(scif3_ctrl), 2223 SH_PFC_PIN_GROUP(scif4_data), 2224 SH_PFC_PIN_GROUP(scif4_clk), 2225 SH_PFC_PIN_GROUP(scif4_ctrl), 2226 SH_PFC_PIN_GROUP(scif_clk_a), 2227 SH_PFC_PIN_GROUP(scif_clk_b), 2228 SH_PFC_PIN_GROUP(tmu_tclk1_a), 2229 SH_PFC_PIN_GROUP(tmu_tclk1_b), 2230 SH_PFC_PIN_GROUP(tmu_tclk2_a), 2231 SH_PFC_PIN_GROUP(tmu_tclk2_b), 2232 SH_PFC_PIN_GROUP(tpu_to0), 2233 SH_PFC_PIN_GROUP(tpu_to1), 2234 SH_PFC_PIN_GROUP(tpu_to2), 2235 SH_PFC_PIN_GROUP(tpu_to3), 2236 VIN_DATA_PIN_GROUP(vin0_data, 8), 2237 VIN_DATA_PIN_GROUP(vin0_data, 10), 2238 VIN_DATA_PIN_GROUP(vin0_data, 12), 2239 VIN_DATA_PIN_GROUP(vin0_data, 16), 2240 SH_PFC_PIN_GROUP(vin0_data18), 2241 VIN_DATA_PIN_GROUP(vin0_data, 20), 2242 VIN_DATA_PIN_GROUP(vin0_data, 24), 2243 SH_PFC_PIN_GROUP(vin0_sync), 2244 SH_PFC_PIN_GROUP(vin0_field), 2245 SH_PFC_PIN_GROUP(vin0_clkenb), 2246 SH_PFC_PIN_GROUP(vin0_clk), 2247 VIN_DATA_PIN_GROUP(vin1_data, 8), 2248 VIN_DATA_PIN_GROUP(vin1_data, 10), 2249 VIN_DATA_PIN_GROUP(vin1_data, 12), 2250 SH_PFC_PIN_GROUP(vin1_sync), 2251 SH_PFC_PIN_GROUP(vin1_field), 2252 SH_PFC_PIN_GROUP(vin1_clkenb), 2253 SH_PFC_PIN_GROUP(vin1_clk), 2254 }; 2255 2256 static const char * const avb_groups[] = { 2257 "avb_link", 2258 "avb_magic", 2259 "avb_phy_int", 2260 "avb_mdio", 2261 "avb_rgmii", 2262 "avb_txcrefclk", 2263 "avb_avtp_pps", 2264 "avb_avtp_capture", 2265 "avb_avtp_match", 2266 }; 2267 2268 static const char * const canfd0_groups[] = { 2269 "canfd0_data_a", 2270 "canfd0_data_b", 2271 }; 2272 2273 static const char * const canfd1_groups[] = { 2274 "canfd1_data", 2275 }; 2276 2277 static const char * const canfd_clk_groups[] = { 2278 "canfd_clk_a", 2279 "canfd_clk_b", 2280 }; 2281 2282 static const char * const du_groups[] = { 2283 "du_rgb666", 2284 "du_rgb888", 2285 "du_clk_out", 2286 "du_sync", 2287 "du_oddf", 2288 "du_cde", 2289 "du_disp", 2290 }; 2291 2292 static const char * const gether_groups[] = { 2293 "gether_link_a", 2294 "gether_phy_int_a", 2295 "gether_mdio_a", 2296 "gether_link_b", 2297 "gether_phy_int_b", 2298 "gether_mdio_b", 2299 "gether_magic", 2300 "gether_rgmii", 2301 "gether_txcrefclk", 2302 "gether_txcrefclk_mega", 2303 "gether_rmii", 2304 }; 2305 2306 static const char * const hscif0_groups[] = { 2307 "hscif0_data_a", 2308 "hscif0_clk_a", 2309 "hscif0_ctrl_a", 2310 "hscif0_data_b", 2311 "hscif0_clk_b", 2312 "hscif0_ctrl_b", 2313 }; 2314 2315 static const char * const hscif1_groups[] = { 2316 "hscif1_data", 2317 "hscif1_clk", 2318 "hscif1_ctrl", 2319 }; 2320 2321 static const char * const hscif2_groups[] = { 2322 "hscif2_data", 2323 "hscif2_clk", 2324 "hscif2_ctrl", 2325 }; 2326 2327 static const char * const hscif3_groups[] = { 2328 "hscif3_data", 2329 "hscif3_clk", 2330 "hscif3_ctrl", 2331 }; 2332 2333 static const char * const i2c0_groups[] = { 2334 "i2c0", 2335 }; 2336 2337 static const char * const i2c1_groups[] = { 2338 "i2c1", 2339 }; 2340 2341 static const char * const i2c2_groups[] = { 2342 "i2c2", 2343 }; 2344 2345 static const char * const i2c3_groups[] = { 2346 "i2c3", 2347 }; 2348 2349 static const char * const i2c4_groups[] = { 2350 "i2c4", 2351 }; 2352 2353 static const char * const i2c5_groups[] = { 2354 "i2c5", 2355 }; 2356 2357 static const char * const intc_ex_groups[] = { 2358 "intc_ex_irq0", 2359 "intc_ex_irq1", 2360 "intc_ex_irq2", 2361 "intc_ex_irq3", 2362 "intc_ex_irq4", 2363 "intc_ex_irq5", 2364 }; 2365 2366 static const char * const mmc_groups[] = { 2367 "mmc_data1", 2368 "mmc_data4", 2369 "mmc_data8", 2370 "mmc_ctrl", 2371 "mmc_cd", 2372 "mmc_wp", 2373 "mmc_ds", 2374 }; 2375 2376 static const char * const msiof0_groups[] = { 2377 "msiof0_clk", 2378 "msiof0_sync", 2379 "msiof0_ss1", 2380 "msiof0_ss2", 2381 "msiof0_txd", 2382 "msiof0_rxd", 2383 }; 2384 2385 static const char * const msiof1_groups[] = { 2386 "msiof1_clk", 2387 "msiof1_sync", 2388 "msiof1_ss1", 2389 "msiof1_ss2", 2390 "msiof1_txd", 2391 "msiof1_rxd", 2392 }; 2393 2394 static const char * const msiof2_groups[] = { 2395 "msiof2_clk", 2396 "msiof2_sync", 2397 "msiof2_ss1", 2398 "msiof2_ss2", 2399 "msiof2_txd", 2400 "msiof2_rxd", 2401 }; 2402 2403 static const char * const msiof3_groups[] = { 2404 "msiof3_clk", 2405 "msiof3_sync", 2406 "msiof3_ss1", 2407 "msiof3_ss2", 2408 "msiof3_txd", 2409 "msiof3_rxd", 2410 }; 2411 2412 static const char * const pwm0_groups[] = { 2413 "pwm0_a", 2414 "pwm0_b", 2415 }; 2416 2417 static const char * const pwm1_groups[] = { 2418 "pwm1_a", 2419 "pwm1_b", 2420 }; 2421 2422 static const char * const pwm2_groups[] = { 2423 "pwm2_a", 2424 "pwm2_b", 2425 }; 2426 2427 static const char * const pwm3_groups[] = { 2428 "pwm3_a", 2429 "pwm3_b", 2430 }; 2431 2432 static const char * const pwm4_groups[] = { 2433 "pwm4_a", 2434 "pwm4_b", 2435 }; 2436 2437 static const char * const qspi0_groups[] = { 2438 "qspi0_ctrl", 2439 "qspi0_data2", 2440 "qspi0_data4", 2441 }; 2442 2443 static const char * const qspi1_groups[] = { 2444 "qspi1_ctrl", 2445 "qspi1_data2", 2446 "qspi1_data4", 2447 }; 2448 2449 static const char * const rpc_groups[] = { 2450 "rpc_clk1", 2451 "rpc_clk2", 2452 "rpc_ctrl", 2453 "rpc_data", 2454 "rpc_reset", 2455 "rpc_int", 2456 "rpc_wp", 2457 }; 2458 2459 static const char * const scif0_groups[] = { 2460 "scif0_data", 2461 "scif0_clk", 2462 "scif0_ctrl", 2463 }; 2464 2465 static const char * const scif1_groups[] = { 2466 "scif1_data_a", 2467 "scif1_clk", 2468 "scif1_ctrl", 2469 "scif1_data_b", 2470 }; 2471 2472 static const char * const scif3_groups[] = { 2473 "scif3_data", 2474 "scif3_clk", 2475 "scif3_ctrl", 2476 }; 2477 2478 static const char * const scif4_groups[] = { 2479 "scif4_data", 2480 "scif4_clk", 2481 "scif4_ctrl", 2482 }; 2483 2484 static const char * const scif_clk_groups[] = { 2485 "scif_clk_a", 2486 "scif_clk_b", 2487 }; 2488 2489 static const char * const tmu_groups[] = { 2490 "tmu_tclk1_a", 2491 "tmu_tclk1_b", 2492 "tmu_tclk2_a", 2493 "tmu_tclk2_b", 2494 }; 2495 2496 static const char * const tpu_groups[] = { 2497 "tpu_to0", 2498 "tpu_to1", 2499 "tpu_to2", 2500 "tpu_to3", 2501 }; 2502 2503 static const char * const vin0_groups[] = { 2504 "vin0_data8", 2505 "vin0_data10", 2506 "vin0_data12", 2507 "vin0_data16", 2508 "vin0_data18", 2509 "vin0_data20", 2510 "vin0_data24", 2511 "vin0_sync", 2512 "vin0_field", 2513 "vin0_clkenb", 2514 "vin0_clk", 2515 }; 2516 2517 static const char * const vin1_groups[] = { 2518 "vin1_data8", 2519 "vin1_data10", 2520 "vin1_data12", 2521 "vin1_sync", 2522 "vin1_field", 2523 "vin1_clkenb", 2524 "vin1_clk", 2525 }; 2526 2527 static const struct sh_pfc_function pinmux_functions[] = { 2528 SH_PFC_FUNCTION(avb), 2529 SH_PFC_FUNCTION(canfd0), 2530 SH_PFC_FUNCTION(canfd1), 2531 SH_PFC_FUNCTION(canfd_clk), 2532 SH_PFC_FUNCTION(du), 2533 SH_PFC_FUNCTION(gether), 2534 SH_PFC_FUNCTION(hscif0), 2535 SH_PFC_FUNCTION(hscif1), 2536 SH_PFC_FUNCTION(hscif2), 2537 SH_PFC_FUNCTION(hscif3), 2538 SH_PFC_FUNCTION(i2c0), 2539 SH_PFC_FUNCTION(i2c1), 2540 SH_PFC_FUNCTION(i2c2), 2541 SH_PFC_FUNCTION(i2c3), 2542 SH_PFC_FUNCTION(i2c4), 2543 SH_PFC_FUNCTION(i2c5), 2544 SH_PFC_FUNCTION(intc_ex), 2545 SH_PFC_FUNCTION(mmc), 2546 SH_PFC_FUNCTION(msiof0), 2547 SH_PFC_FUNCTION(msiof1), 2548 SH_PFC_FUNCTION(msiof2), 2549 SH_PFC_FUNCTION(msiof3), 2550 SH_PFC_FUNCTION(pwm0), 2551 SH_PFC_FUNCTION(pwm1), 2552 SH_PFC_FUNCTION(pwm2), 2553 SH_PFC_FUNCTION(pwm3), 2554 SH_PFC_FUNCTION(pwm4), 2555 SH_PFC_FUNCTION(qspi0), 2556 SH_PFC_FUNCTION(qspi1), 2557 SH_PFC_FUNCTION(rpc), 2558 SH_PFC_FUNCTION(scif0), 2559 SH_PFC_FUNCTION(scif1), 2560 SH_PFC_FUNCTION(scif3), 2561 SH_PFC_FUNCTION(scif4), 2562 SH_PFC_FUNCTION(scif_clk), 2563 SH_PFC_FUNCTION(tmu), 2564 SH_PFC_FUNCTION(tpu), 2565 SH_PFC_FUNCTION(vin0), 2566 SH_PFC_FUNCTION(vin1), 2567 }; 2568 2569 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 2570 #define F_(x, y) FN_##y 2571 #define FM(x) FN_##x 2572 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( 2573 0, 0, 2574 0, 0, 2575 0, 0, 2576 0, 0, 2577 0, 0, 2578 0, 0, 2579 0, 0, 2580 0, 0, 2581 0, 0, 2582 0, 0, 2583 GP_0_21_FN, GPSR0_21, 2584 GP_0_20_FN, GPSR0_20, 2585 GP_0_19_FN, GPSR0_19, 2586 GP_0_18_FN, GPSR0_18, 2587 GP_0_17_FN, GPSR0_17, 2588 GP_0_16_FN, GPSR0_16, 2589 GP_0_15_FN, GPSR0_15, 2590 GP_0_14_FN, GPSR0_14, 2591 GP_0_13_FN, GPSR0_13, 2592 GP_0_12_FN, GPSR0_12, 2593 GP_0_11_FN, GPSR0_11, 2594 GP_0_10_FN, GPSR0_10, 2595 GP_0_9_FN, GPSR0_9, 2596 GP_0_8_FN, GPSR0_8, 2597 GP_0_7_FN, GPSR0_7, 2598 GP_0_6_FN, GPSR0_6, 2599 GP_0_5_FN, GPSR0_5, 2600 GP_0_4_FN, GPSR0_4, 2601 GP_0_3_FN, GPSR0_3, 2602 GP_0_2_FN, GPSR0_2, 2603 GP_0_1_FN, GPSR0_1, 2604 GP_0_0_FN, GPSR0_0, )) 2605 }, 2606 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( 2607 0, 0, 2608 0, 0, 2609 0, 0, 2610 0, 0, 2611 GP_1_27_FN, GPSR1_27, 2612 GP_1_26_FN, GPSR1_26, 2613 GP_1_25_FN, GPSR1_25, 2614 GP_1_24_FN, GPSR1_24, 2615 GP_1_23_FN, GPSR1_23, 2616 GP_1_22_FN, GPSR1_22, 2617 GP_1_21_FN, GPSR1_21, 2618 GP_1_20_FN, GPSR1_20, 2619 GP_1_19_FN, GPSR1_19, 2620 GP_1_18_FN, GPSR1_18, 2621 GP_1_17_FN, GPSR1_17, 2622 GP_1_16_FN, GPSR1_16, 2623 GP_1_15_FN, GPSR1_15, 2624 GP_1_14_FN, GPSR1_14, 2625 GP_1_13_FN, GPSR1_13, 2626 GP_1_12_FN, GPSR1_12, 2627 GP_1_11_FN, GPSR1_11, 2628 GP_1_10_FN, GPSR1_10, 2629 GP_1_9_FN, GPSR1_9, 2630 GP_1_8_FN, GPSR1_8, 2631 GP_1_7_FN, GPSR1_7, 2632 GP_1_6_FN, GPSR1_6, 2633 GP_1_5_FN, GPSR1_5, 2634 GP_1_4_FN, GPSR1_4, 2635 GP_1_3_FN, GPSR1_3, 2636 GP_1_2_FN, GPSR1_2, 2637 GP_1_1_FN, GPSR1_1, 2638 GP_1_0_FN, GPSR1_0, )) 2639 }, 2640 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( 2641 0, 0, 2642 0, 0, 2643 GP_2_29_FN, GPSR2_29, 2644 GP_2_28_FN, GPSR2_28, 2645 GP_2_27_FN, GPSR2_27, 2646 GP_2_26_FN, GPSR2_26, 2647 GP_2_25_FN, GPSR2_25, 2648 GP_2_24_FN, GPSR2_24, 2649 GP_2_23_FN, GPSR2_23, 2650 GP_2_22_FN, GPSR2_22, 2651 GP_2_21_FN, GPSR2_21, 2652 GP_2_20_FN, GPSR2_20, 2653 GP_2_19_FN, GPSR2_19, 2654 GP_2_18_FN, GPSR2_18, 2655 GP_2_17_FN, GPSR2_17, 2656 GP_2_16_FN, GPSR2_16, 2657 GP_2_15_FN, GPSR2_15, 2658 GP_2_14_FN, GPSR2_14, 2659 GP_2_13_FN, GPSR2_13, 2660 GP_2_12_FN, GPSR2_12, 2661 GP_2_11_FN, GPSR2_11, 2662 GP_2_10_FN, GPSR2_10, 2663 GP_2_9_FN, GPSR2_9, 2664 GP_2_8_FN, GPSR2_8, 2665 GP_2_7_FN, GPSR2_7, 2666 GP_2_6_FN, GPSR2_6, 2667 GP_2_5_FN, GPSR2_5, 2668 GP_2_4_FN, GPSR2_4, 2669 GP_2_3_FN, GPSR2_3, 2670 GP_2_2_FN, GPSR2_2, 2671 GP_2_1_FN, GPSR2_1, 2672 GP_2_0_FN, GPSR2_0, )) 2673 }, 2674 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( 2675 0, 0, 2676 0, 0, 2677 0, 0, 2678 0, 0, 2679 0, 0, 2680 0, 0, 2681 0, 0, 2682 0, 0, 2683 0, 0, 2684 0, 0, 2685 0, 0, 2686 0, 0, 2687 0, 0, 2688 0, 0, 2689 0, 0, 2690 GP_3_16_FN, GPSR3_16, 2691 GP_3_15_FN, GPSR3_15, 2692 GP_3_14_FN, GPSR3_14, 2693 GP_3_13_FN, GPSR3_13, 2694 GP_3_12_FN, GPSR3_12, 2695 GP_3_11_FN, GPSR3_11, 2696 GP_3_10_FN, GPSR3_10, 2697 GP_3_9_FN, GPSR3_9, 2698 GP_3_8_FN, GPSR3_8, 2699 GP_3_7_FN, GPSR3_7, 2700 GP_3_6_FN, GPSR3_6, 2701 GP_3_5_FN, GPSR3_5, 2702 GP_3_4_FN, GPSR3_4, 2703 GP_3_3_FN, GPSR3_3, 2704 GP_3_2_FN, GPSR3_2, 2705 GP_3_1_FN, GPSR3_1, 2706 GP_3_0_FN, GPSR3_0, )) 2707 }, 2708 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( 2709 0, 0, 2710 0, 0, 2711 0, 0, 2712 0, 0, 2713 0, 0, 2714 0, 0, 2715 0, 0, 2716 GP_4_24_FN, GPSR4_24, 2717 GP_4_23_FN, GPSR4_23, 2718 GP_4_22_FN, GPSR4_22, 2719 GP_4_21_FN, GPSR4_21, 2720 GP_4_20_FN, GPSR4_20, 2721 GP_4_19_FN, GPSR4_19, 2722 GP_4_18_FN, GPSR4_18, 2723 GP_4_17_FN, GPSR4_17, 2724 GP_4_16_FN, GPSR4_16, 2725 GP_4_15_FN, GPSR4_15, 2726 GP_4_14_FN, GPSR4_14, 2727 GP_4_13_FN, GPSR4_13, 2728 GP_4_12_FN, GPSR4_12, 2729 GP_4_11_FN, GPSR4_11, 2730 GP_4_10_FN, GPSR4_10, 2731 GP_4_9_FN, GPSR4_9, 2732 GP_4_8_FN, GPSR4_8, 2733 GP_4_7_FN, GPSR4_7, 2734 GP_4_6_FN, GPSR4_6, 2735 GP_4_5_FN, GPSR4_5, 2736 GP_4_4_FN, GPSR4_4, 2737 GP_4_3_FN, GPSR4_3, 2738 GP_4_2_FN, GPSR4_2, 2739 GP_4_1_FN, GPSR4_1, 2740 GP_4_0_FN, GPSR4_0, )) 2741 }, 2742 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( 2743 0, 0, 2744 0, 0, 2745 0, 0, 2746 0, 0, 2747 0, 0, 2748 0, 0, 2749 0, 0, 2750 0, 0, 2751 0, 0, 2752 0, 0, 2753 0, 0, 2754 0, 0, 2755 0, 0, 2756 0, 0, 2757 0, 0, 2758 0, 0, 2759 0, 0, 2760 GP_5_14_FN, GPSR5_14, 2761 GP_5_13_FN, GPSR5_13, 2762 GP_5_12_FN, GPSR5_12, 2763 GP_5_11_FN, GPSR5_11, 2764 GP_5_10_FN, GPSR5_10, 2765 GP_5_9_FN, GPSR5_9, 2766 GP_5_8_FN, GPSR5_8, 2767 GP_5_7_FN, GPSR5_7, 2768 GP_5_6_FN, GPSR5_6, 2769 GP_5_5_FN, GPSR5_5, 2770 GP_5_4_FN, GPSR5_4, 2771 GP_5_3_FN, GPSR5_3, 2772 GP_5_2_FN, GPSR5_2, 2773 GP_5_1_FN, GPSR5_1, 2774 GP_5_0_FN, GPSR5_0, )) 2775 }, 2776 #undef F_ 2777 #undef FM 2778 2779 #define F_(x, y) x, 2780 #define FM(x) FN_##x, 2781 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( 2782 IP0_31_28 2783 IP0_27_24 2784 IP0_23_20 2785 IP0_19_16 2786 IP0_15_12 2787 IP0_11_8 2788 IP0_7_4 2789 IP0_3_0 )) 2790 }, 2791 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( 2792 IP1_31_28 2793 IP1_27_24 2794 IP1_23_20 2795 IP1_19_16 2796 IP1_15_12 2797 IP1_11_8 2798 IP1_7_4 2799 IP1_3_0 )) 2800 }, 2801 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( 2802 IP2_31_28 2803 IP2_27_24 2804 IP2_23_20 2805 IP2_19_16 2806 IP2_15_12 2807 IP2_11_8 2808 IP2_7_4 2809 IP2_3_0 )) 2810 }, 2811 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( 2812 IP3_31_28 2813 IP3_27_24 2814 IP3_23_20 2815 IP3_19_16 2816 IP3_15_12 2817 IP3_11_8 2818 IP3_7_4 2819 IP3_3_0 )) 2820 }, 2821 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( 2822 IP4_31_28 2823 IP4_27_24 2824 IP4_23_20 2825 IP4_19_16 2826 IP4_15_12 2827 IP4_11_8 2828 IP4_7_4 2829 IP4_3_0 )) 2830 }, 2831 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( 2832 IP5_31_28 2833 IP5_27_24 2834 IP5_23_20 2835 IP5_19_16 2836 IP5_15_12 2837 IP5_11_8 2838 IP5_7_4 2839 IP5_3_0 )) 2840 }, 2841 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( 2842 IP6_31_28 2843 IP6_27_24 2844 IP6_23_20 2845 IP6_19_16 2846 IP6_15_12 2847 IP6_11_8 2848 IP6_7_4 2849 IP6_3_0 )) 2850 }, 2851 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( 2852 IP7_31_28 2853 IP7_27_24 2854 IP7_23_20 2855 IP7_19_16 2856 IP7_15_12 2857 IP7_11_8 2858 IP7_7_4 2859 IP7_3_0 )) 2860 }, 2861 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( 2862 IP8_31_28 2863 IP8_27_24 2864 IP8_23_20 2865 IP8_19_16 2866 IP8_15_12 2867 IP8_11_8 2868 IP8_7_4 2869 IP8_3_0 )) 2870 }, 2871 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP( 2872 IP9_31_28 2873 IP9_27_24 2874 IP9_23_20 2875 IP9_19_16 2876 IP9_15_12 2877 IP9_11_8 2878 IP9_7_4 2879 IP9_3_0 )) 2880 }, 2881 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP( 2882 IP10_31_28 2883 IP10_27_24 2884 IP10_23_20 2885 IP10_19_16 2886 IP10_15_12 2887 IP10_11_8 2888 IP10_7_4 2889 IP10_3_0 )) 2890 }, 2891 #undef F_ 2892 #undef FM 2893 2894 #define F_(x, y) x, 2895 #define FM(x) FN_##x, 2896 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, 2897 GROUP(4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 2898 1, 1, 1, 1, 1), 2899 GROUP( 2900 /* RESERVED 31, 30, 29, 28 */ 2901 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2902 /* RESERVED 27, 26, 25, 24 */ 2903 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2904 /* RESERVED 23, 22, 21, 20 */ 2905 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2906 /* RESERVED 19, 18, 17, 16 */ 2907 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2908 /* RESERVED 15, 14, 13, 12 */ 2909 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2910 MOD_SEL0_11 2911 MOD_SEL0_10 2912 MOD_SEL0_9 2913 MOD_SEL0_8 2914 MOD_SEL0_7 2915 MOD_SEL0_6 2916 MOD_SEL0_5 2917 MOD_SEL0_4 2918 0, 0, 2919 MOD_SEL0_2 2920 MOD_SEL0_1 2921 MOD_SEL0_0 )) 2922 }, 2923 { }, 2924 }; 2925 2926 enum ioctrl_regs { 2927 POCCTRL0, 2928 POCCTRL1, 2929 POCCTRL2, 2930 POCCTRL3, 2931 TDSELCTRL, 2932 }; 2933 2934 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { 2935 [POCCTRL0] = { 0xe6060380, }, 2936 [POCCTRL1] = { 0xe6060384, }, 2937 [POCCTRL2] = { 0xe6060388, }, 2938 [POCCTRL3] = { 0xe606038c, }, 2939 [TDSELCTRL] = { 0xe60603c0, }, 2940 { /* sentinel */ }, 2941 }; 2942 2943 static int r8a77980_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, 2944 u32 *pocctrl) 2945 { 2946 int bit = pin & 0x1f; 2947 2948 *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg; 2949 if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21)) 2950 return bit; 2951 else if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9)) 2952 return bit + 22; 2953 2954 *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg; 2955 if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16)) 2956 return bit - 10; 2957 if ((pin >= RCAR_GP_PIN(2, 17) && pin <= RCAR_GP_PIN(2, 24)) || 2958 (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))) 2959 return bit + 7; 2960 2961 *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg; 2962 if (pin >= RCAR_GP_PIN(2, 25) && pin <= RCAR_GP_PIN(2, 29)) 2963 return pin - 25; 2964 2965 return -EINVAL; 2966 } 2967 2968 static const struct pinmux_bias_reg pinmux_bias_regs[] = { 2969 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { 2970 [ 0] = RCAR_GP_PIN(0, 0), /* DU_DR2 */ 2971 [ 1] = RCAR_GP_PIN(0, 1), /* DU_DR3 */ 2972 [ 2] = RCAR_GP_PIN(0, 2), /* DU_DR4 */ 2973 [ 3] = RCAR_GP_PIN(0, 3), /* DU_DR5 */ 2974 [ 4] = RCAR_GP_PIN(0, 4), /* DU_DR6 */ 2975 [ 5] = RCAR_GP_PIN(0, 5), /* DU_DR7 */ 2976 [ 6] = RCAR_GP_PIN(0, 6), /* DU_DG2 */ 2977 [ 7] = RCAR_GP_PIN(0, 7), /* DU_DG3 */ 2978 [ 8] = RCAR_GP_PIN(0, 8), /* DU_DG4 */ 2979 [ 9] = RCAR_GP_PIN(0, 9), /* DU_DG5 */ 2980 [10] = RCAR_GP_PIN(0, 10), /* DU_DG6 */ 2981 [11] = RCAR_GP_PIN(0, 11), /* DU_DG7 */ 2982 [12] = RCAR_GP_PIN(0, 12), /* DU_DB2 */ 2983 [13] = RCAR_GP_PIN(0, 13), /* DU_DB3 */ 2984 [14] = RCAR_GP_PIN(0, 14), /* DU_DB4 */ 2985 [15] = RCAR_GP_PIN(0, 15), /* DU_DB5 */ 2986 [16] = RCAR_GP_PIN(0, 16), /* DU_DB6 */ 2987 [17] = RCAR_GP_PIN(0, 17), /* DU_DB7 */ 2988 [18] = RCAR_GP_PIN(0, 18), /* DU_DOTCLKOUT */ 2989 [19] = RCAR_GP_PIN(0, 19), /* DU_EXHSYNC/DU_HSYNC */ 2990 [20] = RCAR_GP_PIN(0, 20), /* DU_EXVSYNC/DU_VSYNC */ 2991 [21] = RCAR_GP_PIN(0, 21), /* DU_EXODDF/DU_ODDF/DISP/CDE */ 2992 [22] = SH_PFC_PIN_NONE, 2993 [23] = SH_PFC_PIN_NONE, 2994 [24] = PIN_DU_DOTCLKIN, /* DU_DOTCLKIN */ 2995 [25] = SH_PFC_PIN_NONE, 2996 [26] = PIN_PRESETOUT_N, /* PRESETOUT# */ 2997 [27] = SH_PFC_PIN_NONE, 2998 [28] = SH_PFC_PIN_NONE, 2999 [29] = SH_PFC_PIN_NONE, 3000 [30] = PIN_EXTALR, /* EXTALR */ 3001 [31] = PIN_FSCLKST_N, /* FSCLKST# */ 3002 } }, 3003 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) { 3004 [ 0] = PIN_FSCLKST, /* FSCLKST */ 3005 [ 1] = SH_PFC_PIN_NONE, 3006 [ 2] = RCAR_GP_PIN(1, 0), /* IRQ0 */ 3007 [ 3] = PIN_DCUTRST_N, /* DCUTRST# */ 3008 [ 4] = PIN_DCUTCK_LPDCLK, /* DCUTCK_LPDCLK */ 3009 [ 5] = PIN_DCUTMS, /* DCUTMS */ 3010 [ 6] = PIN_DCUTDI_LPDI, /* DCUTDI_LPDI */ 3011 [ 7] = SH_PFC_PIN_NONE, 3012 [ 8] = RCAR_GP_PIN(2, 0), /* VI0_CLK */ 3013 [ 9] = RCAR_GP_PIN(2, 1), /* VI0_CLKENB */ 3014 [10] = RCAR_GP_PIN(2, 2), /* VI0_HSYNC# */ 3015 [11] = RCAR_GP_PIN(2, 3), /* VI0_VSYNC# */ 3016 [12] = RCAR_GP_PIN(2, 4), /* VI0_DATA0 */ 3017 [13] = RCAR_GP_PIN(2, 5), /* VI0_DATA1 */ 3018 [14] = RCAR_GP_PIN(2, 6), /* VI0_DATA2 */ 3019 [15] = RCAR_GP_PIN(2, 7), /* VI0_DATA3 */ 3020 [16] = RCAR_GP_PIN(2, 8), /* VI0_DATA4 */ 3021 [17] = RCAR_GP_PIN(2, 9), /* VI0_DATA5 */ 3022 [18] = RCAR_GP_PIN(2, 10), /* VI0_DATA6 */ 3023 [19] = RCAR_GP_PIN(2, 11), /* VI0_DATA7 */ 3024 [20] = RCAR_GP_PIN(2, 12), /* VI0_DATA8 */ 3025 [21] = RCAR_GP_PIN(2, 13), /* VI0_DATA9 */ 3026 [22] = RCAR_GP_PIN(2, 14), /* VI0_DATA10 */ 3027 [23] = RCAR_GP_PIN(2, 15), /* VI0_DATA11 */ 3028 [24] = RCAR_GP_PIN(2, 16), /* VI0_FIELD */ 3029 [25] = RCAR_GP_PIN(3, 0), /* VI1_CLK */ 3030 [26] = RCAR_GP_PIN(3, 1), /* VI1_CLKENB */ 3031 [27] = RCAR_GP_PIN(3, 2), /* VI1_HSYNC# */ 3032 [28] = RCAR_GP_PIN(3, 3), /* VI1_VSYNC# */ 3033 [29] = RCAR_GP_PIN(3, 4), /* VI1_DATA0 */ 3034 [30] = RCAR_GP_PIN(3, 5), /* VI1_DATA1 */ 3035 [31] = RCAR_GP_PIN(3, 6), /* VI1_DATA2 */ 3036 } }, 3037 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { 3038 [ 0] = RCAR_GP_PIN(3, 7), /* VI1_DATA3 */ 3039 [ 1] = RCAR_GP_PIN(3, 8), /* VI1_DATA4 */ 3040 [ 2] = RCAR_GP_PIN(3, 9), /* VI1_DATA5 */ 3041 [ 3] = RCAR_GP_PIN(3, 10), /* VI1_DATA6 */ 3042 [ 4] = RCAR_GP_PIN(3, 11), /* VI1_DATA7 */ 3043 [ 5] = RCAR_GP_PIN(3, 12), /* VI1_DATA8 */ 3044 [ 6] = RCAR_GP_PIN(3, 13), /* VI1_DATA9 */ 3045 [ 7] = RCAR_GP_PIN(3, 14), /* VI1_DATA10 */ 3046 [ 8] = RCAR_GP_PIN(3, 15), /* VI1_DATA11 */ 3047 [ 9] = RCAR_GP_PIN(3, 16), /* VI1_FIELD */ 3048 [10] = RCAR_GP_PIN(4, 0), /* SCL0 */ 3049 [11] = RCAR_GP_PIN(4, 1), /* SDA0 */ 3050 [12] = RCAR_GP_PIN(4, 2), /* SCL1 */ 3051 [13] = RCAR_GP_PIN(4, 3), /* SDA1 */ 3052 [14] = RCAR_GP_PIN(4, 4), /* SCL2 */ 3053 [15] = RCAR_GP_PIN(4, 5), /* SDA2 */ 3054 [16] = RCAR_GP_PIN(1, 1), /* AVB_RX_CTL */ 3055 [17] = RCAR_GP_PIN(1, 2), /* AVB_RXC */ 3056 [18] = RCAR_GP_PIN(1, 3), /* AVB_RD0 */ 3057 [19] = RCAR_GP_PIN(1, 4), /* AVB_RD1 */ 3058 [20] = RCAR_GP_PIN(1, 5), /* AVB_RD2 */ 3059 [21] = RCAR_GP_PIN(1, 6), /* AVB_RD3 */ 3060 [22] = RCAR_GP_PIN(1, 7), /* AVB_TX_CTL */ 3061 [23] = RCAR_GP_PIN(1, 8), /* AVB_TXC */ 3062 [24] = RCAR_GP_PIN(1, 9), /* AVB_TD0 */ 3063 [25] = RCAR_GP_PIN(1, 10), /* AVB_TD1 */ 3064 [26] = RCAR_GP_PIN(1, 11), /* AVB_TD2 */ 3065 [27] = RCAR_GP_PIN(1, 12), /* AVB_TD3 */ 3066 [28] = RCAR_GP_PIN(1, 13), /* AVB_TXCREFCLK */ 3067 [29] = RCAR_GP_PIN(1, 14), /* AVB_MDIO */ 3068 [30] = RCAR_GP_PIN(1, 15), /* AVB_MDC */ 3069 [31] = RCAR_GP_PIN(1, 16), /* AVB_MAGIC */ 3070 } }, 3071 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { 3072 [ 0] = RCAR_GP_PIN(1, 17), /* AVB_PHY_INT */ 3073 [ 1] = RCAR_GP_PIN(1, 18), /* AVB_LINK */ 3074 [ 2] = RCAR_GP_PIN(1, 19), /* AVB_AVTP_MATCH */ 3075 [ 3] = RCAR_GP_PIN(1, 20), /* AVTP_CAPTURE */ 3076 [ 4] = RCAR_GP_PIN(4, 6), /* GETHER_RX_CTL */ 3077 [ 5] = RCAR_GP_PIN(4, 7), /* GETHER_RXC */ 3078 [ 6] = RCAR_GP_PIN(4, 8), /* GETHER_RD0 */ 3079 [ 7] = RCAR_GP_PIN(4, 9), /* GETHER_RD1 */ 3080 [ 8] = RCAR_GP_PIN(4, 10), /* GETHER_RD2 */ 3081 [ 9] = RCAR_GP_PIN(4, 11), /* GETHER_RD3 */ 3082 [10] = RCAR_GP_PIN(4, 12), /* GETHER_TX_CTL */ 3083 [11] = RCAR_GP_PIN(4, 13), /* GETHER_TXC */ 3084 [12] = RCAR_GP_PIN(4, 14), /* GETHER_TD0 */ 3085 [13] = RCAR_GP_PIN(4, 15), /* GETHER_TD1 */ 3086 [14] = RCAR_GP_PIN(4, 16), /* GETHER_TD2 */ 3087 [15] = RCAR_GP_PIN(4, 17), /* GETHER_TD3 */ 3088 [16] = RCAR_GP_PIN(4, 18), /* GETHER_TXCREFCLK */ 3089 [17] = RCAR_GP_PIN(4, 19), /* GETHER_TXCREFCLK_MEGA */ 3090 [18] = RCAR_GP_PIN(4, 20), /* GETHER_MDIO_A */ 3091 [19] = RCAR_GP_PIN(4, 21), /* GETHER_MDC_A */ 3092 [20] = RCAR_GP_PIN(4, 22), /* GETHER_MAGIC */ 3093 [21] = RCAR_GP_PIN(4, 23), /* GETHER_PHY_INT_A */ 3094 [22] = RCAR_GP_PIN(4, 24), /* GETHER_LINK_A */ 3095 [23] = RCAR_GP_PIN(1, 21), /* CANFD0_TX_A */ 3096 [24] = RCAR_GP_PIN(1, 22), /* CANFD0_RX_A */ 3097 [25] = RCAR_GP_PIN(1, 23), /* CANFD1_TX */ 3098 [26] = RCAR_GP_PIN(1, 24), /* CANFD1_RX */ 3099 [27] = RCAR_GP_PIN(1, 25), /* CAN_CLK_A */ 3100 [28] = RCAR_GP_PIN(5, 0), /* QSPI0_SPCLK */ 3101 [29] = RCAR_GP_PIN(5, 1), /* QSPI0_MOSI_IO0 */ 3102 [30] = RCAR_GP_PIN(5, 2), /* QSPI0_MISO_IO1 */ 3103 [31] = RCAR_GP_PIN(5, 3), /* QSPI0_IO2 */ 3104 } }, 3105 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) { 3106 [ 0] = RCAR_GP_PIN(5, 4), /* QSPI0_IO3 */ 3107 [ 1] = RCAR_GP_PIN(5, 5), /* QSPI0_SSL */ 3108 [ 2] = RCAR_GP_PIN(5, 6), /* QSPI1_SPCLK */ 3109 [ 3] = RCAR_GP_PIN(5, 7), /* QSPI1_MOSI_IO0 */ 3110 [ 4] = RCAR_GP_PIN(5, 8), /* QSPI1_MISO_IO1 */ 3111 [ 5] = RCAR_GP_PIN(5, 9), /* QSPI1_IO2 */ 3112 [ 6] = RCAR_GP_PIN(5, 10), /* QSPI1_IO3 */ 3113 [ 7] = RCAR_GP_PIN(5, 11), /* QSPI1_SSL */ 3114 [ 8] = RCAR_GP_PIN(5, 12), /* RPC_RESET# */ 3115 [ 9] = RCAR_GP_PIN(5, 13), /* RPC_WP# */ 3116 [10] = RCAR_GP_PIN(5, 14), /* RPC_INT# */ 3117 [11] = RCAR_GP_PIN(1, 26), /* DIGRF_CLKIN */ 3118 [12] = RCAR_GP_PIN(1, 27), /* DIGRF_CLKOUT */ 3119 [13] = RCAR_GP_PIN(2, 17), /* IRQ4 */ 3120 [14] = RCAR_GP_PIN(2, 18), /* IRQ5 */ 3121 [15] = RCAR_GP_PIN(2, 25), /* SCL3 */ 3122 [16] = RCAR_GP_PIN(2, 26), /* SDA3 */ 3123 [17] = RCAR_GP_PIN(2, 19), /* MSIOF0_RXD */ 3124 [18] = RCAR_GP_PIN(2, 20), /* MSIOF0_TXD */ 3125 [19] = RCAR_GP_PIN(2, 21), /* MSIOF0_SCK */ 3126 [20] = RCAR_GP_PIN(2, 22), /* MSIOF0_SYNC */ 3127 [21] = RCAR_GP_PIN(2, 23), /* MSIOF0_SS1 */ 3128 [22] = RCAR_GP_PIN(2, 24), /* MSIOF0_SS2 */ 3129 [23] = RCAR_GP_PIN(2, 27), /* FSO_CFE_0# */ 3130 [24] = RCAR_GP_PIN(2, 28), /* FSO_CFE_1# */ 3131 [25] = RCAR_GP_PIN(2, 29), /* FSO_TOE# */ 3132 [26] = SH_PFC_PIN_NONE, 3133 [27] = SH_PFC_PIN_NONE, 3134 [28] = SH_PFC_PIN_NONE, 3135 [29] = SH_PFC_PIN_NONE, 3136 [30] = SH_PFC_PIN_NONE, 3137 [31] = SH_PFC_PIN_NONE, 3138 } }, 3139 { /* sentinel */ } 3140 }; 3141 3142 static const struct sh_pfc_soc_operations pinmux_ops = { 3143 .pin_to_pocctrl = r8a77980_pin_to_pocctrl, 3144 .get_bias = rcar_pinmux_get_bias, 3145 .set_bias = rcar_pinmux_set_bias, 3146 }; 3147 3148 const struct sh_pfc_soc_info r8a77980_pinmux_info = { 3149 .name = "r8a77980_pfc", 3150 .ops = &pinmux_ops, 3151 .unlock_reg = 0xe6060000, /* PMMR */ 3152 3153 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 3154 3155 .pins = pinmux_pins, 3156 .nr_pins = ARRAY_SIZE(pinmux_pins), 3157 .groups = pinmux_groups, 3158 .nr_groups = ARRAY_SIZE(pinmux_groups), 3159 .functions = pinmux_functions, 3160 .nr_functions = ARRAY_SIZE(pinmux_functions), 3161 3162 .cfg_regs = pinmux_config_regs, 3163 .bias_regs = pinmux_bias_regs, 3164 .ioctrl_regs = pinmux_ioctrl_regs, 3165 3166 .pinmux_data = pinmux_data, 3167 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 3168 }; 3169