1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * R8A77980 processor support - PFC hardware block. 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 * Copyright (C) 2018 Cogent Embedded, Inc. 7 * 8 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c 9 * 10 * R-Car Gen3 processor support - PFC hardware block. 11 * 12 * Copyright (C) 2015 Renesas Electronics Corporation 13 */ 14 15 #include <linux/errno.h> 16 #include <linux/io.h> 17 #include <linux/kernel.h> 18 19 #include "sh_pfc.h" 20 21 #define CPU_ALL_GP(fn, sfx) \ 22 PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ 23 PORT_GP_28(1, fn, sfx), \ 24 PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ 25 PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ 26 PORT_GP_25(4, fn, sfx), \ 27 PORT_GP_15(5, fn, sfx) 28 29 /* 30 * F_() : just information 31 * FM() : macro for FN_xxx / xxx_MARK 32 */ 33 34 /* GPSR0 */ 35 #define GPSR0_21 F_(DU_EXODDF_DU_ODDF_DISP_CDE, IP2_23_20) 36 #define GPSR0_20 F_(DU_EXVSYNC_DU_VSYNC, IP2_19_16) 37 #define GPSR0_19 F_(DU_EXHSYNC_DU_HSYNC, IP2_15_12) 38 #define GPSR0_18 F_(DU_DOTCLKOUT, IP2_11_8) 39 #define GPSR0_17 F_(DU_DB7, IP2_7_4) 40 #define GPSR0_16 F_(DU_DB6, IP2_3_0) 41 #define GPSR0_15 F_(DU_DB5, IP1_31_28) 42 #define GPSR0_14 F_(DU_DB4, IP1_27_24) 43 #define GPSR0_13 F_(DU_DB3, IP1_23_20) 44 #define GPSR0_12 F_(DU_DB2, IP1_19_16) 45 #define GPSR0_11 F_(DU_DG7, IP1_15_12) 46 #define GPSR0_10 F_(DU_DG6, IP1_11_8) 47 #define GPSR0_9 F_(DU_DG5, IP1_7_4) 48 #define GPSR0_8 F_(DU_DG4, IP1_3_0) 49 #define GPSR0_7 F_(DU_DG3, IP0_31_28) 50 #define GPSR0_6 F_(DU_DG2, IP0_27_24) 51 #define GPSR0_5 F_(DU_DR7, IP0_23_20) 52 #define GPSR0_4 F_(DU_DR6, IP0_19_16) 53 #define GPSR0_3 F_(DU_DR5, IP0_15_12) 54 #define GPSR0_2 F_(DU_DR4, IP0_11_8) 55 #define GPSR0_1 F_(DU_DR3, IP0_7_4) 56 #define GPSR0_0 F_(DU_DR2, IP0_3_0) 57 58 /* GPSR1 */ 59 #define GPSR1_27 F_(DIGRF_CLKOUT, IP8_31_28) 60 #define GPSR1_26 F_(DIGRF_CLKIN, IP8_27_24) 61 #define GPSR1_25 F_(CANFD_CLK_A, IP8_23_20) 62 #define GPSR1_24 F_(CANFD1_RX, IP8_19_16) 63 #define GPSR1_23 F_(CANFD1_TX, IP8_15_12) 64 #define GPSR1_22 F_(CANFD0_RX_A, IP8_11_8) 65 #define GPSR1_21 F_(CANFD0_TX_A, IP8_7_4) 66 #define GPSR1_20 F_(AVB_AVTP_CAPTURE, IP8_3_0) 67 #define GPSR1_19 F_(AVB_AVTP_MATCH, IP7_31_28) 68 #define GPSR1_18 FM(AVB_LINK) 69 #define GPSR1_17 FM(AVB_PHY_INT) 70 #define GPSR1_16 FM(AVB_MAGIC) 71 #define GPSR1_15 FM(AVB_MDC) 72 #define GPSR1_14 FM(AVB_MDIO) 73 #define GPSR1_13 FM(AVB_TXCREFCLK) 74 #define GPSR1_12 FM(AVB_TD3) 75 #define GPSR1_11 FM(AVB_TD2) 76 #define GPSR1_10 FM(AVB_TD1) 77 #define GPSR1_9 FM(AVB_TD0) 78 #define GPSR1_8 FM(AVB_TXC) 79 #define GPSR1_7 FM(AVB_TX_CTL) 80 #define GPSR1_6 FM(AVB_RD3) 81 #define GPSR1_5 FM(AVB_RD2) 82 #define GPSR1_4 FM(AVB_RD1) 83 #define GPSR1_3 FM(AVB_RD0) 84 #define GPSR1_2 FM(AVB_RXC) 85 #define GPSR1_1 FM(AVB_RX_CTL) 86 #define GPSR1_0 F_(IRQ0, IP2_27_24) 87 88 /* GPSR2 */ 89 #define GPSR2_29 F_(FSO_TOE_N, IP10_19_16) 90 #define GPSR2_28 F_(FSO_CFE_1_N, IP10_15_12) 91 #define GPSR2_27 F_(FSO_CFE_0_N, IP10_11_8) 92 #define GPSR2_26 F_(SDA3, IP10_7_4) 93 #define GPSR2_25 F_(SCL3, IP10_3_0) 94 #define GPSR2_24 F_(MSIOF0_SS2, IP9_31_28) 95 #define GPSR2_23 F_(MSIOF0_SS1, IP9_27_24) 96 #define GPSR2_22 F_(MSIOF0_SYNC, IP9_23_20) 97 #define GPSR2_21 F_(MSIOF0_SCK, IP9_19_16) 98 #define GPSR2_20 F_(MSIOF0_TXD, IP9_15_12) 99 #define GPSR2_19 F_(MSIOF0_RXD, IP9_11_8) 100 #define GPSR2_18 F_(IRQ5, IP9_7_4) 101 #define GPSR2_17 F_(IRQ4, IP9_3_0) 102 #define GPSR2_16 F_(VI0_FIELD, IP4_31_28) 103 #define GPSR2_15 F_(VI0_DATA11, IP4_27_24) 104 #define GPSR2_14 F_(VI0_DATA10, IP4_23_20) 105 #define GPSR2_13 F_(VI0_DATA9, IP4_19_16) 106 #define GPSR2_12 F_(VI0_DATA8, IP4_15_12) 107 #define GPSR2_11 F_(VI0_DATA7, IP4_11_8) 108 #define GPSR2_10 F_(VI0_DATA6, IP4_7_4) 109 #define GPSR2_9 F_(VI0_DATA5, IP4_3_0) 110 #define GPSR2_8 F_(VI0_DATA4, IP3_31_28) 111 #define GPSR2_7 F_(VI0_DATA3, IP3_27_24) 112 #define GPSR2_6 F_(VI0_DATA2, IP3_23_20) 113 #define GPSR2_5 F_(VI0_DATA1, IP3_19_16) 114 #define GPSR2_4 F_(VI0_DATA0, IP3_15_12) 115 #define GPSR2_3 F_(VI0_VSYNC_N, IP3_11_8) 116 #define GPSR2_2 F_(VI0_HSYNC_N, IP3_7_4) 117 #define GPSR2_1 F_(VI0_CLKENB, IP3_3_0) 118 #define GPSR2_0 F_(VI0_CLK, IP2_31_28) 119 120 /* GPSR3 */ 121 #define GPSR3_16 F_(VI1_FIELD, IP7_3_0) 122 #define GPSR3_15 F_(VI1_DATA11, IP6_31_28) 123 #define GPSR3_14 F_(VI1_DATA10, IP6_27_24) 124 #define GPSR3_13 F_(VI1_DATA9, IP6_23_20) 125 #define GPSR3_12 F_(VI1_DATA8, IP6_19_16) 126 #define GPSR3_11 F_(VI1_DATA7, IP6_15_12) 127 #define GPSR3_10 F_(VI1_DATA6, IP6_11_8) 128 #define GPSR3_9 F_(VI1_DATA5, IP6_7_4) 129 #define GPSR3_8 F_(VI1_DATA4, IP6_3_0) 130 #define GPSR3_7 F_(VI1_DATA3, IP5_31_28) 131 #define GPSR3_6 F_(VI1_DATA2, IP5_27_24) 132 #define GPSR3_5 F_(VI1_DATA1, IP5_23_20) 133 #define GPSR3_4 F_(VI1_DATA0, IP5_19_16) 134 #define GPSR3_3 F_(VI1_VSYNC_N, IP5_15_12) 135 #define GPSR3_2 F_(VI1_HSYNC_N, IP5_11_8) 136 #define GPSR3_1 F_(VI1_CLKENB, IP5_7_4) 137 #define GPSR3_0 F_(VI1_CLK, IP5_3_0) 138 139 /* GPSR4 */ 140 #define GPSR4_24 FM(GETHER_LINK_A) 141 #define GPSR4_23 FM(GETHER_PHY_INT_A) 142 #define GPSR4_22 FM(GETHER_MAGIC) 143 #define GPSR4_21 FM(GETHER_MDC_A) 144 #define GPSR4_20 FM(GETHER_MDIO_A) 145 #define GPSR4_19 FM(GETHER_TXCREFCLK_MEGA) 146 #define GPSR4_18 FM(GETHER_TXCREFCLK) 147 #define GPSR4_17 FM(GETHER_TD3) 148 #define GPSR4_16 FM(GETHER_TD2) 149 #define GPSR4_15 FM(GETHER_TD1) 150 #define GPSR4_14 FM(GETHER_TD0) 151 #define GPSR4_13 FM(GETHER_TXC) 152 #define GPSR4_12 FM(GETHER_TX_CTL) 153 #define GPSR4_11 FM(GETHER_RD3) 154 #define GPSR4_10 FM(GETHER_RD2) 155 #define GPSR4_9 FM(GETHER_RD1) 156 #define GPSR4_8 FM(GETHER_RD0) 157 #define GPSR4_7 FM(GETHER_RXC) 158 #define GPSR4_6 FM(GETHER_RX_CTL) 159 #define GPSR4_5 F_(SDA2, IP7_27_24) 160 #define GPSR4_4 F_(SCL2, IP7_23_20) 161 #define GPSR4_3 F_(SDA1, IP7_19_16) 162 #define GPSR4_2 F_(SCL1, IP7_15_12) 163 #define GPSR4_1 F_(SDA0, IP7_11_8) 164 #define GPSR4_0 F_(SCL0, IP7_7_4) 165 166 /* GPSR5 */ 167 #define GPSR5_14 FM(RPC_INT_N) 168 #define GPSR5_13 FM(RPC_WP_N) 169 #define GPSR5_12 FM(RPC_RESET_N) 170 #define GPSR5_11 FM(QSPI1_SSL) 171 #define GPSR5_10 FM(QSPI1_IO3) 172 #define GPSR5_9 FM(QSPI1_IO2) 173 #define GPSR5_8 FM(QSPI1_MISO_IO1) 174 #define GPSR5_7 FM(QSPI1_MOSI_IO0) 175 #define GPSR5_6 FM(QSPI1_SPCLK) 176 #define GPSR5_5 FM(QSPI0_SSL) 177 #define GPSR5_4 FM(QSPI0_IO3) 178 #define GPSR5_3 FM(QSPI0_IO2) 179 #define GPSR5_2 FM(QSPI0_MISO_IO1) 180 #define GPSR5_1 FM(QSPI0_MOSI_IO0) 181 #define GPSR5_0 FM(QSPI0_SPCLK) 182 183 184 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ 185 #define IP0_3_0 FM(DU_DR2) FM(SCK4) FM(GETHER_RMII_CRS_DV) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 186 #define IP0_7_4 FM(DU_DR3) FM(RX4) FM(GETHER_RMII_RX_ER) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 187 #define IP0_11_8 FM(DU_DR4) FM(TX4) FM(GETHER_RMII_RXD0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 188 #define IP0_15_12 FM(DU_DR5) FM(CTS4_N) FM(GETHER_RMII_RXD1) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 189 #define IP0_19_16 FM(DU_DR6) FM(RTS4_N) FM(GETHER_RMII_TXD_EN) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 190 #define IP0_23_20 FM(DU_DR7) F_(0, 0) FM(GETHER_RMII_TXD0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 191 #define IP0_27_24 FM(DU_DG2) F_(0, 0) FM(GETHER_RMII_TXD1) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 192 #define IP0_31_28 FM(DU_DG3) FM(CPG_CPCKOUT) FM(GETHER_RMII_REFCLK) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 193 #define IP1_3_0 FM(DU_DG4) FM(SCL5) F_(0, 0) FM(A8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 194 #define IP1_7_4 FM(DU_DG5) FM(SDA5) FM(GETHER_MDC_B) FM(A9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 195 #define IP1_11_8 FM(DU_DG6) FM(SCIF_CLK_A) FM(GETHER_MDIO_B) FM(A10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 196 #define IP1_15_12 FM(DU_DG7) FM(HRX0_A) F_(0, 0) FM(A11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 197 #define IP1_19_16 FM(DU_DB2) FM(HSCK0_A) F_(0, 0) FM(A12) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 198 #define IP1_23_20 FM(DU_DB3) FM(HRTS0_N_A) F_(0, 0) FM(A13) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 199 #define IP1_27_24 FM(DU_DB4) FM(HCTS0_N_A) F_(0, 0) FM(A14) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 200 #define IP1_31_28 FM(DU_DB5) FM(HTX0_A) FM(PWM0_A) FM(A15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 201 #define IP2_3_0 FM(DU_DB6) FM(MSIOF3_RXD) F_(0, 0) FM(A16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 202 #define IP2_7_4 FM(DU_DB7) FM(MSIOF3_TXD) F_(0, 0) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 203 #define IP2_11_8 FM(DU_DOTCLKOUT) FM(MSIOF3_SS1) FM(GETHER_LINK_B) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 204 #define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(MSIOF3_SS2) FM(GETHER_PHY_INT_B) FM(A19) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 205 #define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 206 #define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 207 #define IP2_27_24 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 208 #define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 209 #define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 210 #define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 211 #define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 212 #define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 213 #define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 214 #define IP3_23_20 FM(VI0_DATA2) FM(AVB_AVTP_PPS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 215 #define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 216 #define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 217 #define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 218 #define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 219 #define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 220 #define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 221 #define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 222 #define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 223 #define IP4_27_24 FM(VI0_DATA11) FM(HTX2) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 224 #define IP4_31_28 FM(VI0_FIELD) FM(HRX2) FM(PWM4_A) FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 225 #define IP5_3_0 FM(VI1_CLK) FM(MSIOF1_RXD) F_(0, 0) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 226 #define IP5_7_4 FM(VI1_CLKENB) FM(MSIOF1_TXD) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 227 #define IP5_11_8 FM(VI1_HSYNC_N) FM(MSIOF1_SCK) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 228 #define IP5_15_12 FM(VI1_VSYNC_N) FM(MSIOF1_SYNC) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 229 #define IP5_19_16 FM(VI1_DATA0) FM(MSIOF1_SS1) F_(0, 0) FM(D3) FM(MMC_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 230 #define IP5_23_20 FM(VI1_DATA1) FM(MSIOF1_SS2) F_(0, 0) FM(D4) FM(MMC_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 231 #define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 232 #define IP5_31_28 FM(VI1_DATA3) FM(CANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 233 #define IP6_3_0 FM(VI1_DATA4) FM(CANFD_CLK_B) F_(0, 0) FM(D7) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 234 #define IP6_7_4 FM(VI1_DATA5) F_(0, 0) F_(0, 0) FM(D8) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 235 #define IP6_11_8 FM(VI1_DATA6) F_(0, 0) F_(0, 0) FM(D9) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 236 #define IP6_15_12 FM(VI1_DATA7) F_(0, 0) F_(0, 0) FM(D10) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 237 #define IP6_19_16 FM(VI1_DATA8) F_(0, 0) F_(0, 0) FM(D11) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 238 #define IP6_23_20 FM(VI1_DATA9) FM(TCLK1_A) F_(0, 0) FM(D12) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 239 #define IP6_27_24 FM(VI1_DATA10) FM(TCLK2_A) F_(0, 0) FM(D13) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 240 #define IP6_31_28 FM(VI1_DATA11) FM(SCL4) F_(0, 0) FM(D14) FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 241 #define IP7_3_0 FM(VI1_FIELD) FM(SDA4) F_(0, 0) FM(D15) FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 242 #define IP7_7_4 FM(SCL0) F_(0, 0) F_(0, 0) FM(CLKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 243 #define IP7_11_8 FM(SDA0) F_(0, 0) F_(0, 0) FM(BS_N) FM(SCK0) FM(HSCK0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 244 #define IP7_15_12 FM(SCL1) F_(0, 0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(HCTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 245 #define IP7_19_16 FM(SDA1) F_(0, 0) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N) FM(HRTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 246 #define IP7_23_20 FM(SCL2) F_(0, 0) F_(0, 0) FM(WE1_N) FM(RX0) FM(HRX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 247 #define IP7_27_24 FM(SDA2) F_(0, 0) F_(0, 0) FM(EX_WAIT0) FM(TX0) FM(HTX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 248 #define IP7_31_28 FM(AVB_AVTP_MATCH) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 249 #define IP8_3_0 FM(AVB_AVTP_CAPTURE) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 250 #define IP8_7_4 FM(CANFD0_TX_A) FM(FXR_TXDA) FM(PWM0_B) FM(DU_DISP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 251 #define IP8_11_8 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 252 #define IP8_15_12 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 253 #define IP8_19_16 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 254 #define IP8_23_20 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 255 #define IP8_27_24 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 256 #define IP8_31_28 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 257 #define IP9_3_0 FM(IRQ4) F_(0, 0) F_(0, 0) FM(VI0_DATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 258 #define IP9_7_4 FM(IRQ5) F_(0, 0) F_(0, 0) FM(VI0_DATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 259 #define IP9_11_8 FM(MSIOF0_RXD) FM(DU_DR0) F_(0, 0) FM(VI0_DATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 260 #define IP9_15_12 FM(MSIOF0_TXD) FM(DU_DR1) F_(0, 0) FM(VI0_DATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 261 #define IP9_19_16 FM(MSIOF0_SCK) FM(DU_DG0) F_(0, 0) FM(VI0_DATA16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 262 #define IP9_23_20 FM(MSIOF0_SYNC) FM(DU_DG1) F_(0, 0) FM(VI0_DATA17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 263 #define IP9_27_24 FM(MSIOF0_SS1) FM(DU_DB0) FM(TCLK3) FM(VI0_DATA18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 264 #define IP9_31_28 FM(MSIOF0_SS2) FM(DU_DB1) FM(TCLK4) FM(VI0_DATA19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 265 #define IP10_3_0 FM(SCL3) F_(0, 0) F_(0, 0) FM(VI0_DATA20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 266 #define IP10_7_4 FM(SDA3) F_(0, 0) F_(0, 0) FM(VI0_DATA21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 267 #define IP10_11_8 FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) FM(VI0_DATA22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 268 #define IP10_15_12 FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) FM(VI0_DATA23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 269 #define IP10_19_16 FM(FSO_TOE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 270 #define IP10_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 271 #define IP10_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 272 #define IP10_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 273 274 #define PINMUX_GPSR \ 275 \ 276 GPSR2_29 \ 277 GPSR2_28 \ 278 GPSR1_27 GPSR2_27 \ 279 GPSR1_26 GPSR2_26 \ 280 GPSR1_25 GPSR2_25 \ 281 GPSR1_24 GPSR2_24 GPSR4_24 \ 282 GPSR1_23 GPSR2_23 GPSR4_23 \ 283 GPSR1_22 GPSR2_22 GPSR4_22 \ 284 GPSR0_21 GPSR1_21 GPSR2_21 GPSR4_21 \ 285 GPSR0_20 GPSR1_20 GPSR2_20 GPSR4_20 \ 286 GPSR0_19 GPSR1_19 GPSR2_19 GPSR4_19 \ 287 GPSR0_18 GPSR1_18 GPSR2_18 GPSR4_18 \ 288 GPSR0_17 GPSR1_17 GPSR2_17 GPSR4_17 \ 289 GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 GPSR4_16 \ 290 GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR4_15 \ 291 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 \ 292 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 \ 293 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 \ 294 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 \ 295 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 \ 296 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 \ 297 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 \ 298 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 \ 299 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 \ 300 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 \ 301 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 \ 302 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 \ 303 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 \ 304 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 \ 305 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 306 307 #define PINMUX_IPSR \ 308 \ 309 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \ 310 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \ 311 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \ 312 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \ 313 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \ 314 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \ 315 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ 316 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \ 317 \ 318 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ 319 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ 320 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ 321 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \ 322 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ 323 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ 324 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ 325 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ 326 \ 327 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 \ 328 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 \ 329 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 \ 330 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 \ 331 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 \ 332 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 \ 333 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 \ 334 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 335 336 /* MOD_SEL0 */ /* 0 */ /* 1 */ 337 #define MOD_SEL0_11 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) 338 #define MOD_SEL0_10 FM(SEL_GETHER_0) FM(SEL_GETHER_1) 339 #define MOD_SEL0_9 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1) 340 #define MOD_SEL0_8 FM(SEL_PWM0_0) FM(SEL_PWM0_1) 341 #define MOD_SEL0_7 FM(SEL_PWM1_0) FM(SEL_PWM1_1) 342 #define MOD_SEL0_6 FM(SEL_PWM2_0) FM(SEL_PWM2_1) 343 #define MOD_SEL0_5 FM(SEL_PWM3_0) FM(SEL_PWM3_1) 344 #define MOD_SEL0_4 FM(SEL_PWM4_0) FM(SEL_PWM4_1) 345 #define MOD_SEL0_2 FM(SEL_RSP_0) FM(SEL_RSP_1) 346 #define MOD_SEL0_1 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1) 347 #define MOD_SEL0_0 FM(SEL_TMU_0) FM(SEL_TMU_1) 348 349 #define PINMUX_MOD_SELS \ 350 \ 351 MOD_SEL0_11 \ 352 MOD_SEL0_10 \ 353 MOD_SEL0_9 \ 354 MOD_SEL0_8 \ 355 MOD_SEL0_7 \ 356 MOD_SEL0_6 \ 357 MOD_SEL0_5 \ 358 MOD_SEL0_4 \ 359 MOD_SEL0_2 \ 360 MOD_SEL0_1 \ 361 MOD_SEL0_0 362 363 enum { 364 PINMUX_RESERVED = 0, 365 366 PINMUX_DATA_BEGIN, 367 GP_ALL(DATA), 368 PINMUX_DATA_END, 369 370 #define F_(x, y) 371 #define FM(x) FN_##x, 372 PINMUX_FUNCTION_BEGIN, 373 GP_ALL(FN), 374 PINMUX_GPSR 375 PINMUX_IPSR 376 PINMUX_MOD_SELS 377 PINMUX_FUNCTION_END, 378 #undef F_ 379 #undef FM 380 381 #define F_(x, y) 382 #define FM(x) x##_MARK, 383 PINMUX_MARK_BEGIN, 384 PINMUX_GPSR 385 PINMUX_IPSR 386 PINMUX_MOD_SELS 387 PINMUX_MARK_END, 388 #undef F_ 389 #undef FM 390 }; 391 392 static const u16 pinmux_data[] = { 393 PINMUX_DATA_GP_ALL(), 394 395 PINMUX_SINGLE(AVB_RX_CTL), 396 PINMUX_SINGLE(AVB_RXC), 397 PINMUX_SINGLE(AVB_RD0), 398 PINMUX_SINGLE(AVB_RD1), 399 PINMUX_SINGLE(AVB_RD2), 400 PINMUX_SINGLE(AVB_RD3), 401 PINMUX_SINGLE(AVB_TX_CTL), 402 PINMUX_SINGLE(AVB_TXC), 403 PINMUX_SINGLE(AVB_TD0), 404 PINMUX_SINGLE(AVB_TD1), 405 PINMUX_SINGLE(AVB_TD2), 406 PINMUX_SINGLE(AVB_TD3), 407 PINMUX_SINGLE(AVB_TXCREFCLK), 408 PINMUX_SINGLE(AVB_MDIO), 409 PINMUX_SINGLE(AVB_MDC), 410 PINMUX_SINGLE(AVB_MAGIC), 411 PINMUX_SINGLE(AVB_PHY_INT), 412 PINMUX_SINGLE(AVB_LINK), 413 414 PINMUX_SINGLE(GETHER_RX_CTL), 415 PINMUX_SINGLE(GETHER_RXC), 416 PINMUX_SINGLE(GETHER_RD0), 417 PINMUX_SINGLE(GETHER_RD1), 418 PINMUX_SINGLE(GETHER_RD2), 419 PINMUX_SINGLE(GETHER_RD3), 420 PINMUX_SINGLE(GETHER_TX_CTL), 421 PINMUX_SINGLE(GETHER_TXC), 422 PINMUX_SINGLE(GETHER_TD0), 423 PINMUX_SINGLE(GETHER_TD1), 424 PINMUX_SINGLE(GETHER_TD2), 425 PINMUX_SINGLE(GETHER_TD3), 426 PINMUX_SINGLE(GETHER_TXCREFCLK), 427 PINMUX_SINGLE(GETHER_TXCREFCLK_MEGA), 428 PINMUX_SINGLE(GETHER_MDIO_A), 429 PINMUX_SINGLE(GETHER_MDC_A), 430 PINMUX_SINGLE(GETHER_MAGIC), 431 PINMUX_SINGLE(GETHER_PHY_INT_A), 432 PINMUX_SINGLE(GETHER_LINK_A), 433 434 PINMUX_SINGLE(QSPI0_SPCLK), 435 PINMUX_SINGLE(QSPI0_MOSI_IO0), 436 PINMUX_SINGLE(QSPI0_MISO_IO1), 437 PINMUX_SINGLE(QSPI0_IO2), 438 PINMUX_SINGLE(QSPI0_IO3), 439 PINMUX_SINGLE(QSPI0_SSL), 440 PINMUX_SINGLE(QSPI1_SPCLK), 441 PINMUX_SINGLE(QSPI1_MOSI_IO0), 442 PINMUX_SINGLE(QSPI1_MISO_IO1), 443 PINMUX_SINGLE(QSPI1_IO2), 444 PINMUX_SINGLE(QSPI1_IO3), 445 PINMUX_SINGLE(QSPI1_SSL), 446 PINMUX_SINGLE(RPC_RESET_N), 447 PINMUX_SINGLE(RPC_WP_N), 448 PINMUX_SINGLE(RPC_INT_N), 449 450 /* IPSR0 */ 451 PINMUX_IPSR_GPSR(IP0_3_0, DU_DR2), 452 PINMUX_IPSR_GPSR(IP0_3_0, SCK4), 453 PINMUX_IPSR_GPSR(IP0_3_0, GETHER_RMII_CRS_DV), 454 PINMUX_IPSR_GPSR(IP0_3_0, A0), 455 456 PINMUX_IPSR_GPSR(IP0_7_4, DU_DR3), 457 PINMUX_IPSR_GPSR(IP0_7_4, RX4), 458 PINMUX_IPSR_GPSR(IP0_7_4, GETHER_RMII_RX_ER), 459 PINMUX_IPSR_GPSR(IP0_7_4, A1), 460 461 PINMUX_IPSR_GPSR(IP0_11_8, DU_DR4), 462 PINMUX_IPSR_GPSR(IP0_11_8, TX4), 463 PINMUX_IPSR_GPSR(IP0_11_8, GETHER_RMII_RXD0), 464 PINMUX_IPSR_GPSR(IP0_11_8, A2), 465 466 PINMUX_IPSR_GPSR(IP0_15_12, DU_DR5), 467 PINMUX_IPSR_GPSR(IP0_15_12, CTS4_N), 468 PINMUX_IPSR_GPSR(IP0_15_12, GETHER_RMII_RXD1), 469 PINMUX_IPSR_GPSR(IP0_15_12, A3), 470 471 PINMUX_IPSR_GPSR(IP0_19_16, DU_DR6), 472 PINMUX_IPSR_GPSR(IP0_19_16, RTS4_N), 473 PINMUX_IPSR_GPSR(IP0_19_16, GETHER_RMII_TXD_EN), 474 PINMUX_IPSR_GPSR(IP0_19_16, A4), 475 476 PINMUX_IPSR_GPSR(IP0_23_20, DU_DR7), 477 PINMUX_IPSR_GPSR(IP0_23_20, GETHER_RMII_TXD0), 478 PINMUX_IPSR_GPSR(IP0_23_20, A5), 479 480 PINMUX_IPSR_GPSR(IP0_27_24, DU_DG2), 481 PINMUX_IPSR_GPSR(IP0_27_24, GETHER_RMII_TXD1), 482 PINMUX_IPSR_GPSR(IP0_27_24, A6), 483 484 PINMUX_IPSR_GPSR(IP0_31_28, DU_DG3), 485 PINMUX_IPSR_GPSR(IP0_31_28, CPG_CPCKOUT), 486 PINMUX_IPSR_GPSR(IP0_31_28, GETHER_RMII_REFCLK), 487 PINMUX_IPSR_GPSR(IP0_31_28, A7), 488 PINMUX_IPSR_GPSR(IP0_31_28, PWMFSW0), 489 490 /* IPSR1 */ 491 PINMUX_IPSR_GPSR(IP1_3_0, DU_DG4), 492 PINMUX_IPSR_GPSR(IP1_3_0, SCL5), 493 PINMUX_IPSR_GPSR(IP1_3_0, A8), 494 495 PINMUX_IPSR_GPSR(IP1_7_4, DU_DG5), 496 PINMUX_IPSR_GPSR(IP1_7_4, SDA5), 497 PINMUX_IPSR_MSEL(IP1_7_4, GETHER_MDC_B, SEL_GETHER_1), 498 PINMUX_IPSR_GPSR(IP1_7_4, A9), 499 500 PINMUX_IPSR_GPSR(IP1_11_8, DU_DG6), 501 PINMUX_IPSR_MSEL(IP1_11_8, SCIF_CLK_A, SEL_HSCIF0_0), 502 PINMUX_IPSR_MSEL(IP1_11_8, GETHER_MDIO_B, SEL_GETHER_1), 503 PINMUX_IPSR_GPSR(IP1_11_8, A10), 504 505 PINMUX_IPSR_GPSR(IP1_15_12, DU_DG7), 506 PINMUX_IPSR_MSEL(IP1_15_12, HRX0_A, SEL_HSCIF0_0), 507 PINMUX_IPSR_GPSR(IP1_15_12, A11), 508 509 PINMUX_IPSR_GPSR(IP1_19_16, DU_DB2), 510 PINMUX_IPSR_MSEL(IP1_19_16, HSCK0_A, SEL_HSCIF0_0), 511 PINMUX_IPSR_GPSR(IP1_19_16, A12), 512 PINMUX_IPSR_GPSR(IP1_19_16, IRQ1), 513 514 PINMUX_IPSR_GPSR(IP1_23_20, DU_DB3), 515 PINMUX_IPSR_MSEL(IP1_23_20, HRTS0_N_A, SEL_HSCIF0_0), 516 PINMUX_IPSR_GPSR(IP1_23_20, A13), 517 PINMUX_IPSR_GPSR(IP1_23_20, IRQ2), 518 519 PINMUX_IPSR_GPSR(IP1_27_24, DU_DB4), 520 PINMUX_IPSR_MSEL(IP1_27_24, HCTS0_N_A, SEL_HSCIF0_0), 521 PINMUX_IPSR_GPSR(IP1_27_24, A14), 522 PINMUX_IPSR_GPSR(IP1_27_24, IRQ3), 523 524 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB5), 525 PINMUX_IPSR_MSEL(IP1_31_28, HTX0_A, SEL_HSCIF0_0), 526 PINMUX_IPSR_MSEL(IP1_31_28, PWM0_A, SEL_PWM0_0), 527 PINMUX_IPSR_GPSR(IP1_31_28, A15), 528 529 /* IPSR2 */ 530 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB6), 531 PINMUX_IPSR_GPSR(IP2_3_0, MSIOF3_RXD), 532 PINMUX_IPSR_GPSR(IP2_3_0, A16), 533 534 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB7), 535 PINMUX_IPSR_GPSR(IP2_7_4, MSIOF3_TXD), 536 PINMUX_IPSR_GPSR(IP2_7_4, A17), 537 538 PINMUX_IPSR_GPSR(IP2_11_8, DU_DOTCLKOUT), 539 PINMUX_IPSR_GPSR(IP2_11_8, MSIOF3_SS1), 540 PINMUX_IPSR_MSEL(IP2_11_8, GETHER_LINK_B, SEL_GETHER_1), 541 PINMUX_IPSR_GPSR(IP2_11_8, A18), 542 543 PINMUX_IPSR_GPSR(IP2_15_12, DU_EXHSYNC_DU_HSYNC), 544 PINMUX_IPSR_GPSR(IP2_15_12, MSIOF3_SS2), 545 PINMUX_IPSR_MSEL(IP2_15_12, GETHER_PHY_INT_B, SEL_GETHER_1), 546 PINMUX_IPSR_GPSR(IP2_15_12, A19), 547 PINMUX_IPSR_GPSR(IP2_15_12, FXR_TXENA_N), 548 549 PINMUX_IPSR_GPSR(IP2_19_16, DU_EXVSYNC_DU_VSYNC), 550 PINMUX_IPSR_GPSR(IP2_19_16, MSIOF3_SCK), 551 PINMUX_IPSR_GPSR(IP2_19_16, FXR_TXENB_N), 552 553 PINMUX_IPSR_GPSR(IP2_23_20, DU_EXODDF_DU_ODDF_DISP_CDE), 554 PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC), 555 556 PINMUX_IPSR_GPSR(IP2_27_24, IRQ0), 557 558 PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK), 559 PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK), 560 PINMUX_IPSR_GPSR(IP2_31_28, SCK3), 561 PINMUX_IPSR_GPSR(IP2_31_28, HSCK3), 562 563 /* IPSR3 */ 564 PINMUX_IPSR_GPSR(IP3_3_0, VI0_CLKENB), 565 PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_RXD), 566 PINMUX_IPSR_GPSR(IP3_3_0, RX3), 567 PINMUX_IPSR_GPSR(IP3_3_0, RD_WR_N), 568 PINMUX_IPSR_GPSR(IP3_3_0, HCTS3_N), 569 570 PINMUX_IPSR_GPSR(IP3_7_4, VI0_HSYNC_N), 571 PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD), 572 PINMUX_IPSR_GPSR(IP3_7_4, TX3), 573 PINMUX_IPSR_GPSR(IP3_7_4, HRTS3_N), 574 575 PINMUX_IPSR_GPSR(IP3_11_8, VI0_VSYNC_N), 576 PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_SYNC), 577 PINMUX_IPSR_GPSR(IP3_11_8, CTS3_N), 578 PINMUX_IPSR_GPSR(IP3_11_8, HTX3), 579 580 PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0), 581 PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1), 582 PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N), 583 PINMUX_IPSR_GPSR(IP3_15_12, HRX3), 584 585 PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1), 586 PINMUX_IPSR_GPSR(IP3_19_16, MSIOF2_SS2), 587 PINMUX_IPSR_GPSR(IP3_19_16, SCK1), 588 PINMUX_IPSR_MSEL(IP3_19_16, SPEEDIN_A, SEL_RSP_0), 589 590 PINMUX_IPSR_GPSR(IP3_23_20, VI0_DATA2), 591 PINMUX_IPSR_GPSR(IP3_23_20, AVB_AVTP_PPS), 592 593 PINMUX_IPSR_GPSR(IP3_27_24, VI0_DATA3), 594 PINMUX_IPSR_GPSR(IP3_27_24, HSCK1), 595 596 PINMUX_IPSR_GPSR(IP3_31_28, VI0_DATA4), 597 PINMUX_IPSR_GPSR(IP3_31_28, HRTS1_N), 598 PINMUX_IPSR_MSEL(IP3_31_28, RX1_A, SEL_SCIF1_0), 599 600 /* IPSR4 */ 601 PINMUX_IPSR_GPSR(IP4_3_0, VI0_DATA5), 602 PINMUX_IPSR_GPSR(IP4_3_0, HCTS1_N), 603 PINMUX_IPSR_MSEL(IP4_3_0, TX1_A, SEL_SCIF1_0), 604 605 PINMUX_IPSR_GPSR(IP4_7_4, VI0_DATA6), 606 PINMUX_IPSR_GPSR(IP4_7_4, HTX1), 607 PINMUX_IPSR_GPSR(IP4_7_4, CTS1_N), 608 609 PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7), 610 PINMUX_IPSR_GPSR(IP4_11_8, HRX1), 611 PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N), 612 613 PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8), 614 PINMUX_IPSR_GPSR(IP4_15_12, HSCK2), 615 616 PINMUX_IPSR_GPSR(IP4_19_16, VI0_DATA9), 617 PINMUX_IPSR_GPSR(IP4_19_16, HCTS2_N), 618 PINMUX_IPSR_MSEL(IP4_19_16, PWM1_A, SEL_PWM1_0), 619 620 PINMUX_IPSR_GPSR(IP4_23_20, VI0_DATA10), 621 PINMUX_IPSR_GPSR(IP4_23_20, HRTS2_N), 622 PINMUX_IPSR_MSEL(IP4_23_20, PWM2_A, SEL_PWM2_0), 623 624 PINMUX_IPSR_GPSR(IP4_27_24, VI0_DATA11), 625 PINMUX_IPSR_GPSR(IP4_27_24, HTX2), 626 PINMUX_IPSR_MSEL(IP4_27_24, PWM3_A, SEL_PWM3_0), 627 628 PINMUX_IPSR_GPSR(IP4_31_28, VI0_FIELD), 629 PINMUX_IPSR_GPSR(IP4_31_28, HRX2), 630 PINMUX_IPSR_MSEL(IP4_31_28, PWM4_A, SEL_PWM4_0), 631 PINMUX_IPSR_GPSR(IP4_31_28, CS1_N), 632 633 /* IPSR5 */ 634 PINMUX_IPSR_GPSR(IP5_3_0, VI1_CLK), 635 PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD), 636 PINMUX_IPSR_GPSR(IP5_3_0, CS0_N), 637 638 PINMUX_IPSR_GPSR(IP5_7_4, VI1_CLKENB), 639 PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD), 640 PINMUX_IPSR_GPSR(IP5_7_4, D0), 641 642 PINMUX_IPSR_GPSR(IP5_11_8, VI1_HSYNC_N), 643 PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK), 644 PINMUX_IPSR_GPSR(IP5_11_8, D1), 645 646 PINMUX_IPSR_GPSR(IP5_15_12, VI1_VSYNC_N), 647 PINMUX_IPSR_GPSR(IP5_15_12, MSIOF1_SYNC), 648 PINMUX_IPSR_GPSR(IP5_15_12, D2), 649 650 PINMUX_IPSR_GPSR(IP5_19_16, VI1_DATA0), 651 PINMUX_IPSR_GPSR(IP5_19_16, MSIOF1_SS1), 652 PINMUX_IPSR_GPSR(IP5_19_16, D3), 653 PINMUX_IPSR_GPSR(IP5_19_16, MMC_WP), 654 655 PINMUX_IPSR_GPSR(IP5_23_20, VI1_DATA1), 656 PINMUX_IPSR_GPSR(IP5_23_20, MSIOF1_SS2), 657 PINMUX_IPSR_GPSR(IP5_23_20, D4), 658 PINMUX_IPSR_GPSR(IP5_23_20, MMC_CD), 659 660 PINMUX_IPSR_GPSR(IP5_27_24, VI1_DATA2), 661 PINMUX_IPSR_MSEL(IP5_27_24, CANFD0_TX_B, SEL_CANFD0_1), 662 PINMUX_IPSR_GPSR(IP5_27_24, D5), 663 PINMUX_IPSR_GPSR(IP5_27_24, MMC_DS), 664 665 PINMUX_IPSR_GPSR(IP5_31_28, VI1_DATA3), 666 PINMUX_IPSR_MSEL(IP5_31_28, CANFD0_RX_B, SEL_CANFD0_1), 667 PINMUX_IPSR_GPSR(IP5_31_28, D6), 668 PINMUX_IPSR_GPSR(IP5_31_28, MMC_CMD), 669 670 /* IPSR6 */ 671 PINMUX_IPSR_GPSR(IP6_3_0, VI1_DATA4), 672 PINMUX_IPSR_MSEL(IP6_3_0, CANFD_CLK_B, SEL_CANFD0_1), 673 PINMUX_IPSR_GPSR(IP6_3_0, D7), 674 PINMUX_IPSR_GPSR(IP6_3_0, MMC_D0), 675 676 PINMUX_IPSR_GPSR(IP6_7_4, VI1_DATA5), 677 PINMUX_IPSR_GPSR(IP6_7_4, D8), 678 PINMUX_IPSR_GPSR(IP6_7_4, MMC_D1), 679 680 PINMUX_IPSR_GPSR(IP6_11_8, VI1_DATA6), 681 PINMUX_IPSR_GPSR(IP6_11_8, D9), 682 PINMUX_IPSR_GPSR(IP6_11_8, MMC_D2), 683 684 PINMUX_IPSR_GPSR(IP6_15_12, VI1_DATA7), 685 PINMUX_IPSR_GPSR(IP6_15_12, D10), 686 PINMUX_IPSR_GPSR(IP6_15_12, MMC_D3), 687 688 PINMUX_IPSR_GPSR(IP6_19_16, VI1_DATA8), 689 PINMUX_IPSR_GPSR(IP6_19_16, D11), 690 PINMUX_IPSR_GPSR(IP6_19_16, MMC_CLK), 691 692 PINMUX_IPSR_GPSR(IP6_23_20, VI1_DATA9), 693 PINMUX_IPSR_MSEL(IP6_23_20, TCLK1_A, SEL_TMU_0), 694 PINMUX_IPSR_GPSR(IP6_23_20, D12), 695 PINMUX_IPSR_GPSR(IP6_23_20, MMC_D4), 696 697 PINMUX_IPSR_GPSR(IP6_27_24, VI1_DATA10), 698 PINMUX_IPSR_MSEL(IP6_27_24, TCLK2_A, SEL_TMU_0), 699 PINMUX_IPSR_GPSR(IP6_27_24, D13), 700 PINMUX_IPSR_GPSR(IP6_27_24, MMC_D5), 701 702 PINMUX_IPSR_GPSR(IP6_31_28, VI1_DATA11), 703 PINMUX_IPSR_GPSR(IP6_31_28, SCL4), 704 PINMUX_IPSR_GPSR(IP6_31_28, D14), 705 PINMUX_IPSR_GPSR(IP6_31_28, MMC_D6), 706 707 /* IPSR7 */ 708 PINMUX_IPSR_GPSR(IP7_3_0, VI1_FIELD), 709 PINMUX_IPSR_GPSR(IP7_3_0, SDA4), 710 PINMUX_IPSR_GPSR(IP7_3_0, D15), 711 PINMUX_IPSR_GPSR(IP7_3_0, MMC_D7), 712 713 PINMUX_IPSR_GPSR(IP7_7_4, SCL0), 714 PINMUX_IPSR_GPSR(IP7_7_4, CLKOUT), 715 716 PINMUX_IPSR_GPSR(IP7_11_8, SDA0), 717 PINMUX_IPSR_GPSR(IP7_11_8, BS_N), 718 PINMUX_IPSR_GPSR(IP7_11_8, SCK0), 719 PINMUX_IPSR_MSEL(IP7_11_8, HSCK0_B, SEL_HSCIF0_1), 720 721 PINMUX_IPSR_GPSR(IP7_15_12, SCL1), 722 PINMUX_IPSR_GPSR(IP7_15_12, TPU0TO2), 723 PINMUX_IPSR_GPSR(IP7_15_12, RD_N), 724 PINMUX_IPSR_GPSR(IP7_15_12, CTS0_N), 725 PINMUX_IPSR_GPSR(IP7_15_12, HCTS0_N_B), 726 727 PINMUX_IPSR_GPSR(IP7_19_16, SDA1), 728 PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3), 729 PINMUX_IPSR_GPSR(IP7_19_16, WE0_N), 730 PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N), 731 PINMUX_IPSR_MSEL(IP1_23_20, HRTS0_N_B, SEL_HSCIF0_1), 732 733 PINMUX_IPSR_GPSR(IP7_23_20, SCL2), 734 PINMUX_IPSR_GPSR(IP7_23_20, WE1_N), 735 PINMUX_IPSR_GPSR(IP7_23_20, RX0), 736 PINMUX_IPSR_MSEL(IP7_23_20, HRX0_B, SEL_HSCIF0_1), 737 738 PINMUX_IPSR_GPSR(IP7_27_24, SDA2), 739 PINMUX_IPSR_GPSR(IP7_27_24, EX_WAIT0), 740 PINMUX_IPSR_GPSR(IP7_27_24, TX0), 741 PINMUX_IPSR_MSEL(IP7_27_24, HTX0_B, SEL_HSCIF0_1), 742 743 PINMUX_IPSR_GPSR(IP7_31_28, AVB_AVTP_MATCH), 744 PINMUX_IPSR_GPSR(IP7_31_28, TPU0TO0), 745 746 /* IPSR8 */ 747 PINMUX_IPSR_GPSR(IP8_3_0, AVB_AVTP_CAPTURE), 748 PINMUX_IPSR_GPSR(IP8_3_0, TPU0TO1), 749 750 PINMUX_IPSR_MSEL(IP8_7_4, CANFD0_TX_A, SEL_CANFD0_0), 751 PINMUX_IPSR_GPSR(IP8_7_4, FXR_TXDA), 752 PINMUX_IPSR_MSEL(IP8_7_4, PWM0_B, SEL_PWM0_1), 753 PINMUX_IPSR_GPSR(IP8_7_4, DU_DISP), 754 755 PINMUX_IPSR_MSEL(IP8_11_8, CANFD0_RX_A, SEL_CANFD0_0), 756 PINMUX_IPSR_GPSR(IP8_11_8, RXDA_EXTFXR), 757 PINMUX_IPSR_MSEL(IP8_11_8, PWM1_B, SEL_PWM1_1), 758 PINMUX_IPSR_GPSR(IP8_11_8, DU_CDE), 759 760 PINMUX_IPSR_GPSR(IP8_15_12, CANFD1_TX), 761 PINMUX_IPSR_GPSR(IP8_15_12, FXR_TXDB), 762 PINMUX_IPSR_MSEL(IP8_15_12, PWM2_B, SEL_PWM2_1), 763 PINMUX_IPSR_MSEL(IP8_15_12, TCLK1_B, SEL_TMU_1), 764 PINMUX_IPSR_MSEL(IP8_15_12, TX1_B, SEL_SCIF1_1), 765 766 PINMUX_IPSR_GPSR(IP8_19_16, CANFD1_RX), 767 PINMUX_IPSR_GPSR(IP8_19_16, RXDB_EXTFXR), 768 PINMUX_IPSR_MSEL(IP8_19_16, PWM3_B, SEL_PWM3_1), 769 PINMUX_IPSR_MSEL(IP8_19_16, TCLK2_B, SEL_TMU_1), 770 PINMUX_IPSR_MSEL(IP8_19_16, RX1_B, SEL_SCIF1_1), 771 772 PINMUX_IPSR_MSEL(IP8_23_20, CANFD_CLK_A, SEL_CANFD0_0), 773 PINMUX_IPSR_GPSR(IP8_23_20, CLK_EXTFXR), 774 PINMUX_IPSR_MSEL(IP8_23_20, PWM4_B, SEL_PWM4_1), 775 PINMUX_IPSR_MSEL(IP8_23_20, SPEEDIN_B, SEL_RSP_1), 776 PINMUX_IPSR_MSEL(IP8_23_20, SCIF_CLK_B, SEL_HSCIF0_1), 777 778 PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKIN), 779 PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKEN_IN), 780 781 PINMUX_IPSR_GPSR(IP8_31_28, DIGRF_CLKOUT), 782 PINMUX_IPSR_GPSR(IP8_31_28, DIGRF_CLKEN_OUT), 783 784 /* IPSR9 */ 785 PINMUX_IPSR_GPSR(IP9_3_0, IRQ4), 786 PINMUX_IPSR_GPSR(IP9_3_0, VI0_DATA12), 787 788 PINMUX_IPSR_GPSR(IP9_7_4, IRQ5), 789 PINMUX_IPSR_GPSR(IP9_7_4, VI0_DATA13), 790 791 PINMUX_IPSR_GPSR(IP9_11_8, MSIOF0_RXD), 792 PINMUX_IPSR_GPSR(IP9_11_8, DU_DR0), 793 PINMUX_IPSR_GPSR(IP9_11_8, VI0_DATA14), 794 795 PINMUX_IPSR_GPSR(IP9_15_12, MSIOF0_TXD), 796 PINMUX_IPSR_GPSR(IP9_15_12, DU_DR1), 797 PINMUX_IPSR_GPSR(IP9_15_12, VI0_DATA15), 798 799 PINMUX_IPSR_GPSR(IP9_19_16, MSIOF0_SCK), 800 PINMUX_IPSR_GPSR(IP9_19_16, DU_DG0), 801 PINMUX_IPSR_GPSR(IP9_19_16, VI0_DATA16), 802 803 PINMUX_IPSR_GPSR(IP9_23_20, MSIOF0_SYNC), 804 PINMUX_IPSR_GPSR(IP9_23_20, DU_DG1), 805 PINMUX_IPSR_GPSR(IP9_23_20, VI0_DATA17), 806 807 PINMUX_IPSR_GPSR(IP9_27_24, MSIOF0_SS1), 808 PINMUX_IPSR_GPSR(IP9_27_24, DU_DB0), 809 PINMUX_IPSR_GPSR(IP9_27_24, TCLK3), 810 PINMUX_IPSR_GPSR(IP9_27_24, VI0_DATA18), 811 812 PINMUX_IPSR_GPSR(IP9_31_28, MSIOF0_SS2), 813 PINMUX_IPSR_GPSR(IP9_31_28, DU_DB1), 814 PINMUX_IPSR_GPSR(IP9_31_28, TCLK4), 815 PINMUX_IPSR_GPSR(IP9_31_28, VI0_DATA19), 816 817 /* IPSR10 */ 818 PINMUX_IPSR_GPSR(IP10_3_0, SCL3), 819 PINMUX_IPSR_GPSR(IP10_3_0, VI0_DATA20), 820 821 PINMUX_IPSR_GPSR(IP10_7_4, SDA3), 822 PINMUX_IPSR_GPSR(IP10_7_4, VI0_DATA21), 823 824 PINMUX_IPSR_GPSR(IP10_11_8, FSO_CFE_0_N), 825 PINMUX_IPSR_GPSR(IP10_11_8, VI0_DATA22), 826 827 PINMUX_IPSR_GPSR(IP10_15_12, FSO_CFE_1_N), 828 PINMUX_IPSR_GPSR(IP10_15_12, VI0_DATA23), 829 830 PINMUX_IPSR_GPSR(IP10_19_16, FSO_TOE_N), 831 }; 832 833 static const struct sh_pfc_pin pinmux_pins[] = { 834 PINMUX_GPIO_GP_ALL(), 835 }; 836 837 /* - AVB -------------------------------------------------------------------- */ 838 static const unsigned int avb_link_pins[] = { 839 /* AVB_LINK */ 840 RCAR_GP_PIN(1, 18), 841 }; 842 static const unsigned int avb_link_mux[] = { 843 AVB_LINK_MARK, 844 }; 845 static const unsigned int avb_magic_pins[] = { 846 /* AVB_MAGIC */ 847 RCAR_GP_PIN(1, 16), 848 }; 849 static const unsigned int avb_magic_mux[] = { 850 AVB_MAGIC_MARK, 851 }; 852 static const unsigned int avb_phy_int_pins[] = { 853 /* AVB_PHY_INT */ 854 RCAR_GP_PIN(1, 17), 855 }; 856 static const unsigned int avb_phy_int_mux[] = { 857 AVB_PHY_INT_MARK, 858 }; 859 static const unsigned int avb_mdio_pins[] = { 860 /* AVB_MDC, AVB_MDIO */ 861 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), 862 }; 863 static const unsigned int avb_mdio_mux[] = { 864 AVB_MDC_MARK, AVB_MDIO_MARK, 865 }; 866 static const unsigned int avb_rgmii_pins[] = { 867 /* 868 * AVB_TX_CTL, AVB_TXC, AVB_TD0, AVB_TD1, AVB_TD2, AVB_TD3, 869 * AVB_RX_CTL, AVB_RXC, AVB_RD0, AVB_RD1, AVB_RD2, AVB_RD3, 870 */ 871 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), 872 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10), 873 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12), 874 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2), 875 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4), 876 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), 877 }; 878 static const unsigned int avb_rgmii_mux[] = { 879 AVB_TX_CTL_MARK, AVB_TXC_MARK, 880 AVB_TD0_MARK, AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK, 881 AVB_RX_CTL_MARK, AVB_RXC_MARK, 882 AVB_RD0_MARK, AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK, 883 }; 884 static const unsigned int avb_txcrefclk_pins[] = { 885 /* AVB_TXCREFCLK */ 886 RCAR_GP_PIN(1, 13), 887 }; 888 static const unsigned int avb_txcrefclk_mux[] = { 889 AVB_TXCREFCLK_MARK, 890 }; 891 static const unsigned int avb_avtp_pps_pins[] = { 892 /* AVB_AVTP_PPS */ 893 RCAR_GP_PIN(2, 6), 894 }; 895 static const unsigned int avb_avtp_pps_mux[] = { 896 AVB_AVTP_PPS_MARK, 897 }; 898 static const unsigned int avb_avtp_capture_pins[] = { 899 /* AVB_AVTP_CAPTURE */ 900 RCAR_GP_PIN(1, 20), 901 }; 902 static const unsigned int avb_avtp_capture_mux[] = { 903 AVB_AVTP_CAPTURE_MARK, 904 }; 905 static const unsigned int avb_avtp_match_pins[] = { 906 /* AVB_AVTP_MATCH */ 907 RCAR_GP_PIN(1, 19), 908 }; 909 static const unsigned int avb_avtp_match_mux[] = { 910 AVB_AVTP_MATCH_MARK, 911 }; 912 913 /* - CANFD0 ----------------------------------------------------------------- */ 914 static const unsigned int canfd0_data_a_pins[] = { 915 /* CANFD0_TX, CANFD0_RX */ 916 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), 917 }; 918 static const unsigned int canfd0_data_a_mux[] = { 919 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK, 920 }; 921 static const unsigned int canfd0_data_b_pins[] = { 922 /* CANFD0_TX, CANFD0_RX */ 923 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 924 }; 925 static const unsigned int canfd0_data_b_mux[] = { 926 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK, 927 }; 928 929 /* - CANFD1 ----------------------------------------------------------------- */ 930 static const unsigned int canfd1_data_pins[] = { 931 /* CANFD1_TX, CANFD1_RX */ 932 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 933 }; 934 static const unsigned int canfd1_data_mux[] = { 935 CANFD1_TX_MARK, CANFD1_RX_MARK, 936 }; 937 938 /* - CANFD Clock ------------------------------------------------------------ */ 939 static const unsigned int canfd_clk_a_pins[] = { 940 /* CANFD_CLK */ 941 RCAR_GP_PIN(1, 25), 942 }; 943 static const unsigned int canfd_clk_a_mux[] = { 944 CANFD_CLK_A_MARK, 945 }; 946 static const unsigned int canfd_clk_b_pins[] = { 947 /* CANFD_CLK */ 948 RCAR_GP_PIN(3, 8), 949 }; 950 static const unsigned int canfd_clk_b_mux[] = { 951 CANFD_CLK_B_MARK, 952 }; 953 954 /* - DU --------------------------------------------------------------------- */ 955 static const unsigned int du_rgb666_pins[] = { 956 /* DU_DR[7:2], DU_DG[7:2], DU_DB[7:2] */ 957 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), 958 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0), 959 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9), 960 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), 961 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15), 962 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12), 963 }; 964 static const unsigned int du_rgb666_mux[] = { 965 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, 966 DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK, 967 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, 968 DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK, 969 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, 970 DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK, 971 }; 972 static const unsigned int du_rgb888_pins[] = { 973 /* DU_DR[7:0], DU_DG[7:0], DU_DB[7:0] */ 974 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), 975 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0), 976 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), 977 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9), 978 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), 979 RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21), 980 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15), 981 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12), 982 RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23), 983 }; 984 static const unsigned int du_rgb888_mux[] = { 985 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, 986 DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK, 987 DU_DR1_MARK, DU_DR0_MARK, 988 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, 989 DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK, 990 DU_DG1_MARK, DU_DG0_MARK, 991 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, 992 DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK, 993 DU_DB1_MARK, DU_DB0_MARK, 994 }; 995 static const unsigned int du_clk_out_pins[] = { 996 /* DU_DOTCLKOUT */ 997 RCAR_GP_PIN(0, 18), 998 }; 999 static const unsigned int du_clk_out_mux[] = { 1000 DU_DOTCLKOUT_MARK, 1001 }; 1002 static const unsigned int du_sync_pins[] = { 1003 /* DU_EXVSYNC/DU_VSYNC, DU_EXHSYNC/DU_HSYNC */ 1004 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), 1005 }; 1006 static const unsigned int du_sync_mux[] = { 1007 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK, 1008 }; 1009 static const unsigned int du_oddf_pins[] = { 1010 /* DU_EXODDF/DU_ODDF/DISP/CDE */ 1011 RCAR_GP_PIN(0, 21), 1012 }; 1013 static const unsigned int du_oddf_mux[] = { 1014 DU_EXODDF_DU_ODDF_DISP_CDE_MARK, 1015 }; 1016 static const unsigned int du_cde_pins[] = { 1017 /* DU_CDE */ 1018 RCAR_GP_PIN(1, 22), 1019 }; 1020 static const unsigned int du_cde_mux[] = { 1021 DU_CDE_MARK, 1022 }; 1023 static const unsigned int du_disp_pins[] = { 1024 /* DU_DISP */ 1025 RCAR_GP_PIN(1, 21), 1026 }; 1027 static const unsigned int du_disp_mux[] = { 1028 DU_DISP_MARK, 1029 }; 1030 1031 /* - GETHER ----------------------------------------------------------------- */ 1032 static const unsigned int gether_link_a_pins[] = { 1033 /* GETHER_LINK */ 1034 RCAR_GP_PIN(4, 24), 1035 }; 1036 static const unsigned int gether_link_a_mux[] = { 1037 GETHER_LINK_A_MARK, 1038 }; 1039 static const unsigned int gether_phy_int_a_pins[] = { 1040 /* GETHER_PHY_INT */ 1041 RCAR_GP_PIN(4, 23), 1042 }; 1043 static const unsigned int gether_phy_int_a_mux[] = { 1044 GETHER_PHY_INT_A_MARK, 1045 }; 1046 static const unsigned int gether_mdio_a_pins[] = { 1047 /* GETHER_MDC, GETHER_MDIO */ 1048 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), 1049 }; 1050 static const unsigned int gether_mdio_a_mux[] = { 1051 GETHER_MDC_A_MARK, GETHER_MDIO_A_MARK, 1052 }; 1053 static const unsigned int gether_link_b_pins[] = { 1054 /* GETHER_LINK */ 1055 RCAR_GP_PIN(0, 18), 1056 }; 1057 static const unsigned int gether_link_b_mux[] = { 1058 GETHER_LINK_B_MARK, 1059 }; 1060 static const unsigned int gether_phy_int_b_pins[] = { 1061 /* GETHER_PHY_INT */ 1062 RCAR_GP_PIN(0, 19), 1063 }; 1064 static const unsigned int gether_phy_int_b_mux[] = { 1065 GETHER_PHY_INT_B_MARK, 1066 }; 1067 static const unsigned int gether_mdio_b_mux[] = { 1068 GETHER_MDC_B_MARK, GETHER_MDIO_B_MARK, 1069 }; 1070 static const unsigned int gether_mdio_b_pins[] = { 1071 /* GETHER_MDC, GETHER_MDIO */ 1072 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), 1073 }; 1074 static const unsigned int gether_magic_pins[] = { 1075 /* GETHER_MAGIC */ 1076 RCAR_GP_PIN(4, 22), 1077 }; 1078 static const unsigned int gether_magic_mux[] = { 1079 GETHER_MAGIC_MARK, 1080 }; 1081 static const unsigned int gether_rgmii_pins[] = { 1082 /* 1083 * GETHER_TX_CTL, GETHER_TXC, 1084 * GETHER_TD0, GETHER_TD1, GETHER_TD2, GETHER_TD3, 1085 * GETHER_RX_CTL, GETHER_RXC, 1086 * GETHER_RD0, GETHER_RD1, GETHER_RD2, GETHER_RD3, 1087 */ 1088 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13), 1089 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15), 1090 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17), 1091 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7), 1092 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), 1093 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), 1094 }; 1095 static const unsigned int gether_rgmii_mux[] = { 1096 GETHER_TX_CTL_MARK, GETHER_TXC_MARK, 1097 GETHER_TD0_MARK, GETHER_TD1_MARK, 1098 GETHER_TD2_MARK, GETHER_TD3_MARK, 1099 GETHER_RX_CTL_MARK, GETHER_RXC_MARK, 1100 GETHER_RD0_MARK, AVB_RD1_MARK, 1101 GETHER_RD2_MARK, AVB_RD3_MARK, 1102 }; 1103 static const unsigned int gether_txcrefclk_pins[] = { 1104 /* GETHER_TXCREFCLK */ 1105 RCAR_GP_PIN(4, 18), 1106 }; 1107 static const unsigned int gether_txcrefclk_mux[] = { 1108 GETHER_TXCREFCLK_MARK, 1109 }; 1110 static const unsigned int gether_txcrefclk_mega_pins[] = { 1111 /* GETHER_TXCREFCLK_MEGA */ 1112 RCAR_GP_PIN(4, 19), 1113 }; 1114 static const unsigned int gether_txcrefclk_mega_mux[] = { 1115 GETHER_TXCREFCLK_MEGA_MARK, 1116 }; 1117 static const unsigned int gether_rmii_pins[] = { 1118 /* 1119 * GETHER_RMII_CRS_DV, GETHER_RMII_RX_ER, 1120 * GETHER_RMII_RXD0, GETHER_RMII_RXD1, 1121 * GETHER_RMII_TXD_EN, GETHER_RMII_TXD0, 1122 * GETHER_RMII_TXD1, GETHER_RMII_REFCLK 1123 */ 1124 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 1125 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 1126 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 1127 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 1128 }; 1129 static const unsigned int gether_rmii_mux[] = { 1130 GETHER_RMII_CRS_DV_MARK, GETHER_RMII_RX_ER_MARK, 1131 GETHER_RMII_RXD0_MARK, GETHER_RMII_RXD1_MARK, 1132 GETHER_RMII_TXD_EN_MARK, GETHER_RMII_TXD0_MARK, 1133 GETHER_RMII_TXD1_MARK, GETHER_RMII_REFCLK_MARK, 1134 }; 1135 1136 /* - HSCIF0 ----------------------------------------------------------------- */ 1137 static const unsigned int hscif0_data_a_pins[] = { 1138 /* HRX0, HTX0 */ 1139 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 15), 1140 }; 1141 static const unsigned int hscif0_data_a_mux[] = { 1142 HRX0_A_MARK, HTX0_A_MARK, 1143 }; 1144 static const unsigned int hscif0_clk_a_pins[] = { 1145 /* HSCK0 */ 1146 RCAR_GP_PIN(0, 12), 1147 }; 1148 static const unsigned int hscif0_clk_a_mux[] = { 1149 HSCK0_A_MARK, 1150 }; 1151 static const unsigned int hscif0_ctrl_a_pins[] = { 1152 /* HRTS0#, HCTS0# */ 1153 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14), 1154 }; 1155 static const unsigned int hscif0_ctrl_a_mux[] = { 1156 HRTS0_N_A_MARK, HCTS0_N_A_MARK, 1157 }; 1158 static const unsigned int hscif0_data_b_pins[] = { 1159 /* HRX0, HTX0 */ 1160 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), 1161 }; 1162 static const unsigned int hscif0_data_b_mux[] = { 1163 HRX0_B_MARK, HTX0_B_MARK, 1164 }; 1165 static const unsigned int hscif0_clk_b_pins[] = { 1166 /* HSCK0 */ 1167 RCAR_GP_PIN(4, 1), 1168 }; 1169 static const unsigned int hscif0_clk_b_mux[] = { 1170 HSCK0_B_MARK, 1171 }; 1172 static const unsigned int hscif0_ctrl_b_pins[] = { 1173 /* HRTS0#, HCTS0# */ 1174 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2), 1175 }; 1176 static const unsigned int hscif0_ctrl_b_mux[] = { 1177 HRTS0_N_B_MARK, HCTS0_N_B_MARK, 1178 }; 1179 1180 /* - HSCIF1 ----------------------------------------------------------------- */ 1181 static const unsigned int hscif1_data_pins[] = { 1182 /* HRX1, HTX1 */ 1183 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10), 1184 }; 1185 static const unsigned int hscif1_data_mux[] = { 1186 HRX1_MARK, HTX1_MARK, 1187 }; 1188 static const unsigned int hscif1_clk_pins[] = { 1189 /* HSCK1 */ 1190 RCAR_GP_PIN(2, 7), 1191 }; 1192 static const unsigned int hscif1_clk_mux[] = { 1193 HSCK1_MARK, 1194 }; 1195 static const unsigned int hscif1_ctrl_pins[] = { 1196 /* HRTS1#, HCTS1# */ 1197 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 1198 }; 1199 static const unsigned int hscif1_ctrl_mux[] = { 1200 HRTS1_N_MARK, HCTS1_N_MARK, 1201 }; 1202 1203 /* - HSCIF2 ----------------------------------------------------------------- */ 1204 static const unsigned int hscif2_data_pins[] = { 1205 /* HRX2, HTX2 */ 1206 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15), 1207 }; 1208 static const unsigned int hscif2_data_mux[] = { 1209 HRX2_MARK, HTX2_MARK, 1210 }; 1211 static const unsigned int hscif2_clk_pins[] = { 1212 /* HSCK2 */ 1213 RCAR_GP_PIN(2, 12), 1214 }; 1215 static const unsigned int hscif2_clk_mux[] = { 1216 HSCK2_MARK, 1217 }; 1218 static const unsigned int hscif2_ctrl_pins[] = { 1219 /* HRTS2#, HCTS2# */ 1220 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), 1221 }; 1222 static const unsigned int hscif2_ctrl_mux[] = { 1223 HRTS2_N_MARK, HCTS2_N_MARK, 1224 }; 1225 1226 /* - HSCIF3 ----------------------------------------------------------------- */ 1227 static const unsigned int hscif3_data_pins[] = { 1228 /* HRX3, HTX3 */ 1229 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), 1230 }; 1231 static const unsigned int hscif3_data_mux[] = { 1232 HRX3_MARK, HTX3_MARK, 1233 }; 1234 static const unsigned int hscif3_clk_pins[] = { 1235 /* HSCK3 */ 1236 RCAR_GP_PIN(2, 0), 1237 }; 1238 static const unsigned int hscif3_clk_mux[] = { 1239 HSCK3_MARK, 1240 }; 1241 static const unsigned int hscif3_ctrl_pins[] = { 1242 /* HRTS3#, HCTS3# */ 1243 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1), 1244 }; 1245 static const unsigned int hscif3_ctrl_mux[] = { 1246 HRTS3_N_MARK, HCTS3_N_MARK, 1247 }; 1248 1249 /* - I2C0 ------------------------------------------------------------------- */ 1250 static const unsigned int i2c0_pins[] = { 1251 /* SDA0, SCL0 */ 1252 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0), 1253 }; 1254 static const unsigned int i2c0_mux[] = { 1255 SDA0_MARK, SCL0_MARK, 1256 }; 1257 1258 /* - I2C1 ------------------------------------------------------------------- */ 1259 static const unsigned int i2c1_pins[] = { 1260 /* SDA1, SCL1 */ 1261 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2), 1262 }; 1263 static const unsigned int i2c1_mux[] = { 1264 SDA1_MARK, SCL1_MARK, 1265 }; 1266 1267 /* - I2C2 ------------------------------------------------------------------- */ 1268 static const unsigned int i2c2_pins[] = { 1269 /* SDA2, SCL2 */ 1270 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4), 1271 }; 1272 static const unsigned int i2c2_mux[] = { 1273 SDA2_MARK, SCL2_MARK, 1274 }; 1275 1276 /* - I2C3 ------------------------------------------------------------------- */ 1277 static const unsigned int i2c3_pins[] = { 1278 /* SDA3, SCL3 */ 1279 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 25), 1280 }; 1281 static const unsigned int i2c3_mux[] = { 1282 SDA3_MARK, SCL3_MARK, 1283 }; 1284 1285 /* - I2C4 ------------------------------------------------------------------- */ 1286 static const unsigned int i2c4_pins[] = { 1287 /* SDA4, SCL4 */ 1288 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15), 1289 }; 1290 static const unsigned int i2c4_mux[] = { 1291 SDA4_MARK, SCL4_MARK, 1292 }; 1293 1294 /* - I2C5 ------------------------------------------------------------------- */ 1295 static const unsigned int i2c5_pins[] = { 1296 /* SDA5, SCL5 */ 1297 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8), 1298 }; 1299 static const unsigned int i2c5_mux[] = { 1300 SDA5_MARK, SCL5_MARK, 1301 }; 1302 1303 /* - INTC-EX ---------------------------------------------------------------- */ 1304 static const unsigned int intc_ex_irq0_pins[] = { 1305 /* IRQ0 */ 1306 RCAR_GP_PIN(1, 0), 1307 }; 1308 static const unsigned int intc_ex_irq0_mux[] = { 1309 IRQ0_MARK, 1310 }; 1311 static const unsigned int intc_ex_irq1_pins[] = { 1312 /* IRQ1 */ 1313 RCAR_GP_PIN(0, 12), 1314 }; 1315 static const unsigned int intc_ex_irq1_mux[] = { 1316 IRQ1_MARK, 1317 }; 1318 static const unsigned int intc_ex_irq2_pins[] = { 1319 /* IRQ2 */ 1320 RCAR_GP_PIN(0, 13), 1321 }; 1322 static const unsigned int intc_ex_irq2_mux[] = { 1323 IRQ2_MARK, 1324 }; 1325 static const unsigned int intc_ex_irq3_pins[] = { 1326 /* IRQ3 */ 1327 RCAR_GP_PIN(0, 14), 1328 }; 1329 static const unsigned int intc_ex_irq3_mux[] = { 1330 IRQ3_MARK, 1331 }; 1332 static const unsigned int intc_ex_irq4_pins[] = { 1333 /* IRQ4 */ 1334 RCAR_GP_PIN(2, 17), 1335 }; 1336 static const unsigned int intc_ex_irq4_mux[] = { 1337 IRQ4_MARK, 1338 }; 1339 static const unsigned int intc_ex_irq5_pins[] = { 1340 /* IRQ5 */ 1341 RCAR_GP_PIN(2, 18), 1342 }; 1343 static const unsigned int intc_ex_irq5_mux[] = { 1344 IRQ5_MARK, 1345 }; 1346 1347 /* - MMC -------------------------------------------------------------------- */ 1348 static const unsigned int mmc_data1_pins[] = { 1349 /* MMC_D0 */ 1350 RCAR_GP_PIN(3, 8), 1351 }; 1352 static const unsigned int mmc_data1_mux[] = { 1353 MMC_D0_MARK, 1354 }; 1355 static const unsigned int mmc_data4_pins[] = { 1356 /* MMC_D[0:3] */ 1357 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 1358 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 1359 }; 1360 static const unsigned int mmc_data4_mux[] = { 1361 MMC_D0_MARK, MMC_D1_MARK, 1362 MMC_D2_MARK, MMC_D3_MARK, 1363 }; 1364 static const unsigned int mmc_data8_pins[] = { 1365 /* MMC_D[0:7] */ 1366 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 1367 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 1368 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), 1369 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), 1370 }; 1371 static const unsigned int mmc_data8_mux[] = { 1372 MMC_D0_MARK, MMC_D1_MARK, 1373 MMC_D2_MARK, MMC_D3_MARK, 1374 MMC_D4_MARK, MMC_D5_MARK, 1375 MMC_D6_MARK, MMC_D7_MARK, 1376 }; 1377 static const unsigned int mmc_ctrl_pins[] = { 1378 /* MMC_CLK, MMC_CMD */ 1379 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 7), 1380 }; 1381 static const unsigned int mmc_ctrl_mux[] = { 1382 MMC_CLK_MARK, MMC_CMD_MARK, 1383 }; 1384 static const unsigned int mmc_cd_pins[] = { 1385 /* MMC_CD */ 1386 RCAR_GP_PIN(3, 5), 1387 }; 1388 static const unsigned int mmc_cd_mux[] = { 1389 MMC_CD_MARK, 1390 }; 1391 static const unsigned int mmc_wp_pins[] = { 1392 /* MMC_WP */ 1393 RCAR_GP_PIN(3, 4), 1394 }; 1395 static const unsigned int mmc_wp_mux[] = { 1396 MMC_WP_MARK, 1397 }; 1398 static const unsigned int mmc_ds_pins[] = { 1399 /* MMC_DS */ 1400 RCAR_GP_PIN(3, 6), 1401 }; 1402 static const unsigned int mmc_ds_mux[] = { 1403 MMC_DS_MARK, 1404 }; 1405 1406 /* - MSIOF0 ----------------------------------------------------------------- */ 1407 static const unsigned int msiof0_clk_pins[] = { 1408 /* MSIOF0_SCK */ 1409 RCAR_GP_PIN(2, 21), 1410 }; 1411 static const unsigned int msiof0_clk_mux[] = { 1412 MSIOF0_SCK_MARK, 1413 }; 1414 static const unsigned int msiof0_sync_pins[] = { 1415 /* MSIOF0_SYNC */ 1416 RCAR_GP_PIN(2, 22), 1417 }; 1418 static const unsigned int msiof0_sync_mux[] = { 1419 MSIOF0_SYNC_MARK, 1420 }; 1421 static const unsigned int msiof0_ss1_pins[] = { 1422 /* MSIOF0_SS1 */ 1423 RCAR_GP_PIN(2, 23), 1424 }; 1425 static const unsigned int msiof0_ss1_mux[] = { 1426 MSIOF0_SS1_MARK, 1427 }; 1428 static const unsigned int msiof0_ss2_pins[] = { 1429 /* MSIOF0_SS2 */ 1430 RCAR_GP_PIN(2, 24), 1431 }; 1432 static const unsigned int msiof0_ss2_mux[] = { 1433 MSIOF0_SS2_MARK, 1434 }; 1435 static const unsigned int msiof0_txd_pins[] = { 1436 /* MSIOF0_TXD */ 1437 RCAR_GP_PIN(2, 20), 1438 }; 1439 static const unsigned int msiof0_txd_mux[] = { 1440 MSIOF0_TXD_MARK, 1441 }; 1442 static const unsigned int msiof0_rxd_pins[] = { 1443 /* MSIOF0_RXD */ 1444 RCAR_GP_PIN(2, 19), 1445 }; 1446 static const unsigned int msiof0_rxd_mux[] = { 1447 MSIOF0_RXD_MARK, 1448 }; 1449 1450 /* - MSIOF1 ----------------------------------------------------------------- */ 1451 static const unsigned int msiof1_clk_pins[] = { 1452 /* MSIOF1_SCK */ 1453 RCAR_GP_PIN(3, 2), 1454 }; 1455 static const unsigned int msiof1_clk_mux[] = { 1456 MSIOF1_SCK_MARK, 1457 }; 1458 static const unsigned int msiof1_sync_pins[] = { 1459 /* MSIOF1_SYNC */ 1460 RCAR_GP_PIN(3, 3), 1461 }; 1462 static const unsigned int msiof1_sync_mux[] = { 1463 MSIOF1_SYNC_MARK, 1464 }; 1465 static const unsigned int msiof1_ss1_pins[] = { 1466 /* MSIOF1_SS1 */ 1467 RCAR_GP_PIN(3, 4), 1468 }; 1469 static const unsigned int msiof1_ss1_mux[] = { 1470 MSIOF1_SS1_MARK, 1471 }; 1472 static const unsigned int msiof1_ss2_pins[] = { 1473 /* MSIOF1_SS2 */ 1474 RCAR_GP_PIN(3, 5), 1475 }; 1476 static const unsigned int msiof1_ss2_mux[] = { 1477 MSIOF1_SS2_MARK, 1478 }; 1479 static const unsigned int msiof1_txd_pins[] = { 1480 /* MSIOF1_TXD */ 1481 RCAR_GP_PIN(3, 1), 1482 }; 1483 static const unsigned int msiof1_txd_mux[] = { 1484 MSIOF1_TXD_MARK, 1485 }; 1486 static const unsigned int msiof1_rxd_pins[] = { 1487 /* MSIOF1_RXD */ 1488 RCAR_GP_PIN(3, 0), 1489 }; 1490 static const unsigned int msiof1_rxd_mux[] = { 1491 MSIOF1_RXD_MARK, 1492 }; 1493 1494 /* - MSIOF2 ----------------------------------------------------------------- */ 1495 static const unsigned int msiof2_clk_pins[] = { 1496 /* MSIOF2_SCK */ 1497 RCAR_GP_PIN(2, 0), 1498 }; 1499 static const unsigned int msiof2_clk_mux[] = { 1500 MSIOF2_SCK_MARK, 1501 }; 1502 static const unsigned int msiof2_sync_pins[] = { 1503 /* MSIOF2_SYNC */ 1504 RCAR_GP_PIN(2, 3), 1505 }; 1506 static const unsigned int msiof2_sync_mux[] = { 1507 MSIOF2_SYNC_MARK, 1508 }; 1509 static const unsigned int msiof2_ss1_pins[] = { 1510 /* MSIOF2_SS1 */ 1511 RCAR_GP_PIN(2, 4), 1512 }; 1513 static const unsigned int msiof2_ss1_mux[] = { 1514 MSIOF2_SS1_MARK, 1515 }; 1516 static const unsigned int msiof2_ss2_pins[] = { 1517 /* MSIOF2_SS2 */ 1518 RCAR_GP_PIN(2, 5), 1519 }; 1520 static const unsigned int msiof2_ss2_mux[] = { 1521 MSIOF2_SS2_MARK, 1522 }; 1523 static const unsigned int msiof2_txd_pins[] = { 1524 /* MSIOF2_TXD */ 1525 RCAR_GP_PIN(2, 2), 1526 }; 1527 static const unsigned int msiof2_txd_mux[] = { 1528 MSIOF2_TXD_MARK, 1529 }; 1530 static const unsigned int msiof2_rxd_pins[] = { 1531 /* MSIOF2_RXD */ 1532 RCAR_GP_PIN(2, 1), 1533 }; 1534 static const unsigned int msiof2_rxd_mux[] = { 1535 MSIOF2_RXD_MARK, 1536 }; 1537 1538 /* - MSIOF3 ----------------------------------------------------------------- */ 1539 static const unsigned int msiof3_clk_pins[] = { 1540 /* MSIOF3_SCK */ 1541 RCAR_GP_PIN(0, 20), 1542 }; 1543 static const unsigned int msiof3_clk_mux[] = { 1544 MSIOF3_SCK_MARK, 1545 }; 1546 static const unsigned int msiof3_sync_pins[] = { 1547 /* MSIOF3_SYNC */ 1548 RCAR_GP_PIN(0, 21), 1549 }; 1550 static const unsigned int msiof3_sync_mux[] = { 1551 MSIOF3_SYNC_MARK, 1552 }; 1553 static const unsigned int msiof3_ss1_pins[] = { 1554 /* MSIOF3_SS1 */ 1555 RCAR_GP_PIN(0, 18), 1556 }; 1557 static const unsigned int msiof3_ss1_mux[] = { 1558 MSIOF3_SS1_MARK, 1559 }; 1560 static const unsigned int msiof3_ss2_pins[] = { 1561 /* MSIOF3_SS2 */ 1562 RCAR_GP_PIN(0, 19), 1563 }; 1564 static const unsigned int msiof3_ss2_mux[] = { 1565 MSIOF3_SS2_MARK, 1566 }; 1567 static const unsigned int msiof3_txd_pins[] = { 1568 /* MSIOF3_TXD */ 1569 RCAR_GP_PIN(0, 17), 1570 }; 1571 static const unsigned int msiof3_txd_mux[] = { 1572 MSIOF3_TXD_MARK, 1573 }; 1574 static const unsigned int msiof3_rxd_pins[] = { 1575 /* MSIOF3_RXD */ 1576 RCAR_GP_PIN(0, 16), 1577 }; 1578 static const unsigned int msiof3_rxd_mux[] = { 1579 MSIOF3_RXD_MARK, 1580 }; 1581 1582 /* - PWM0 ------------------------------------------------------------------- */ 1583 static const unsigned int pwm0_a_pins[] = { 1584 /* PWM0 */ 1585 RCAR_GP_PIN(0, 15), 1586 }; 1587 static const unsigned int pwm0_a_mux[] = { 1588 PWM0_A_MARK, 1589 }; 1590 static const unsigned int pwm0_b_pins[] = { 1591 /* PWM0 */ 1592 RCAR_GP_PIN(1, 21), 1593 }; 1594 static const unsigned int pwm0_b_mux[] = { 1595 PWM0_B_MARK, 1596 }; 1597 1598 /* - PWM1 ------------------------------------------------------------------- */ 1599 static const unsigned int pwm1_a_pins[] = { 1600 /* PWM1 */ 1601 RCAR_GP_PIN(2, 13), 1602 }; 1603 static const unsigned int pwm1_a_mux[] = { 1604 PWM1_A_MARK, 1605 }; 1606 static const unsigned int pwm1_b_pins[] = { 1607 /* PWM1 */ 1608 RCAR_GP_PIN(1, 22), 1609 }; 1610 static const unsigned int pwm1_b_mux[] = { 1611 PWM1_B_MARK, 1612 }; 1613 1614 /* - PWM2 ------------------------------------------------------------------- */ 1615 static const unsigned int pwm2_a_pins[] = { 1616 /* PWM2 */ 1617 RCAR_GP_PIN(2, 14), 1618 }; 1619 static const unsigned int pwm2_a_mux[] = { 1620 PWM2_A_MARK, 1621 }; 1622 static const unsigned int pwm2_b_pins[] = { 1623 /* PWM2 */ 1624 RCAR_GP_PIN(1, 23), 1625 }; 1626 static const unsigned int pwm2_b_mux[] = { 1627 PWM2_B_MARK, 1628 }; 1629 1630 /* - PWM3 ------------------------------------------------------------------- */ 1631 static const unsigned int pwm3_a_pins[] = { 1632 /* PWM3 */ 1633 RCAR_GP_PIN(2, 15), 1634 }; 1635 static const unsigned int pwm3_a_mux[] = { 1636 PWM3_A_MARK, 1637 }; 1638 static const unsigned int pwm3_b_pins[] = { 1639 /* PWM3 */ 1640 RCAR_GP_PIN(1, 24), 1641 }; 1642 static const unsigned int pwm3_b_mux[] = { 1643 PWM3_B_MARK, 1644 }; 1645 1646 /* - PWM4 ------------------------------------------------------------------- */ 1647 static const unsigned int pwm4_a_pins[] = { 1648 /* PWM4 */ 1649 RCAR_GP_PIN(2, 16), 1650 }; 1651 static const unsigned int pwm4_a_mux[] = { 1652 PWM4_A_MARK, 1653 }; 1654 static const unsigned int pwm4_b_pins[] = { 1655 /* PWM4 */ 1656 RCAR_GP_PIN(1, 25), 1657 }; 1658 static const unsigned int pwm4_b_mux[] = { 1659 PWM4_B_MARK, 1660 }; 1661 1662 /* - QSPI0 ------------------------------------------------------------------ */ 1663 static const unsigned int qspi0_ctrl_pins[] = { 1664 /* SPCLK, SSL */ 1665 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 5), 1666 }; 1667 static const unsigned int qspi0_ctrl_mux[] = { 1668 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, 1669 }; 1670 static const unsigned int qspi0_data2_pins[] = { 1671 /* MOSI_IO0, MISO_IO1 */ 1672 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 1673 }; 1674 static const unsigned int qspi0_data2_mux[] = { 1675 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, 1676 }; 1677 static const unsigned int qspi0_data4_pins[] = { 1678 /* MOSI_IO0, MISO_IO1, IO2, IO3 */ 1679 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 1680 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), 1681 }; 1682 static const unsigned int qspi0_data4_mux[] = { 1683 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, 1684 QSPI0_IO2_MARK, QSPI0_IO3_MARK 1685 }; 1686 1687 /* - QSPI1 ------------------------------------------------------------------ */ 1688 static const unsigned int qspi1_ctrl_pins[] = { 1689 /* SPCLK, SSL */ 1690 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 11), 1691 }; 1692 static const unsigned int qspi1_ctrl_mux[] = { 1693 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, 1694 }; 1695 static const unsigned int qspi1_data2_pins[] = { 1696 /* MOSI_IO0, MISO_IO1 */ 1697 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), 1698 }; 1699 static const unsigned int qspi1_data2_mux[] = { 1700 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, 1701 }; 1702 static const unsigned int qspi1_data4_pins[] = { 1703 /* MOSI_IO0, MISO_IO1, IO2, IO3 */ 1704 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), 1705 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), 1706 }; 1707 static const unsigned int qspi1_data4_mux[] = { 1708 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, 1709 QSPI1_IO2_MARK, QSPI1_IO3_MARK 1710 }; 1711 1712 /* - RPC -------------------------------------------------------------------- */ 1713 static const unsigned int rpc_clk1_pins[] = { 1714 /* Octal-SPI flash: C/SCLK */ 1715 RCAR_GP_PIN(5, 0), 1716 }; 1717 static const unsigned int rpc_clk1_mux[] = { 1718 QSPI0_SPCLK_MARK, 1719 }; 1720 static const unsigned int rpc_clk2_pins[] = { 1721 /* HyperFlash: CK, CK# */ 1722 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6), 1723 }; 1724 static const unsigned int rpc_clk2_mux[] = { 1725 QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK, 1726 }; 1727 static const unsigned int rpc_ctrl_pins[] = { 1728 /* Octal-SPI flash: S#/CS, DQS */ 1729 /* HyperFlash: CS#, RDS */ 1730 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11), 1731 }; 1732 static const unsigned int rpc_ctrl_mux[] = { 1733 QSPI0_SSL_MARK, QSPI1_SSL_MARK, 1734 }; 1735 static const unsigned int rpc_data_pins[] = { 1736 /* DQ[0:7] */ 1737 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 1738 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), 1739 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), 1740 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), 1741 }; 1742 static const unsigned int rpc_data_mux[] = { 1743 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, 1744 QSPI0_IO2_MARK, QSPI0_IO3_MARK, 1745 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, 1746 QSPI1_IO2_MARK, QSPI1_IO3_MARK, 1747 }; 1748 static const unsigned int rpc_reset_pins[] = { 1749 /* RPC_RESET# */ 1750 RCAR_GP_PIN(5, 12), 1751 }; 1752 static const unsigned int rpc_reset_mux[] = { 1753 RPC_RESET_N_MARK, 1754 }; 1755 static const unsigned int rpc_int_pins[] = { 1756 /* RPC_INT# */ 1757 RCAR_GP_PIN(5, 14), 1758 }; 1759 static const unsigned int rpc_int_mux[] = { 1760 RPC_INT_N_MARK, 1761 }; 1762 static const unsigned int rpc_wp_pins[] = { 1763 /* RPC_WP# */ 1764 RCAR_GP_PIN(5, 13), 1765 }; 1766 static const unsigned int rpc_wp_mux[] = { 1767 RPC_WP_N_MARK, 1768 }; 1769 1770 /* - SCIF0 ------------------------------------------------------------------ */ 1771 static const unsigned int scif0_data_pins[] = { 1772 /* RX0, TX0 */ 1773 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), 1774 }; 1775 static const unsigned int scif0_data_mux[] = { 1776 RX0_MARK, TX0_MARK, 1777 }; 1778 static const unsigned int scif0_clk_pins[] = { 1779 /* SCK0 */ 1780 RCAR_GP_PIN(4, 1), 1781 }; 1782 static const unsigned int scif0_clk_mux[] = { 1783 SCK0_MARK, 1784 }; 1785 static const unsigned int scif0_ctrl_pins[] = { 1786 /* RTS0#, CTS0# */ 1787 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2), 1788 }; 1789 static const unsigned int scif0_ctrl_mux[] = { 1790 RTS0_N_MARK, CTS0_N_MARK, 1791 }; 1792 1793 /* - SCIF1 ------------------------------------------------------------------ */ 1794 static const unsigned int scif1_data_a_pins[] = { 1795 /* RX1, TX1 */ 1796 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 1797 }; 1798 static const unsigned int scif1_data_a_mux[] = { 1799 RX1_A_MARK, TX1_A_MARK, 1800 }; 1801 static const unsigned int scif1_clk_pins[] = { 1802 /* SCK1 */ 1803 RCAR_GP_PIN(2, 5), 1804 }; 1805 static const unsigned int scif1_clk_mux[] = { 1806 SCK1_MARK, 1807 }; 1808 static const unsigned int scif1_ctrl_pins[] = { 1809 /* RTS1#, CTS1# */ 1810 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10), 1811 }; 1812 static const unsigned int scif1_ctrl_mux[] = { 1813 RTS1_N_MARK, CTS1_N_MARK, 1814 }; 1815 static const unsigned int scif1_data_b_pins[] = { 1816 /* RX1, TX1 */ 1817 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23), 1818 }; 1819 static const unsigned int scif1_data_b_mux[] = { 1820 RX1_B_MARK, TX1_B_MARK, 1821 }; 1822 1823 /* - SCIF3 ------------------------------------------------------------------ */ 1824 static const unsigned int scif3_data_pins[] = { 1825 /* RX3, TX3 */ 1826 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), 1827 }; 1828 static const unsigned int scif3_data_mux[] = { 1829 RX3_MARK, TX3_MARK, 1830 }; 1831 static const unsigned int scif3_clk_pins[] = { 1832 /* SCK3 */ 1833 RCAR_GP_PIN(2, 0), 1834 }; 1835 static const unsigned int scif3_clk_mux[] = { 1836 SCK3_MARK, 1837 }; 1838 static const unsigned int scif3_ctrl_pins[] = { 1839 /* RTS3#, CTS3# */ 1840 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), 1841 }; 1842 static const unsigned int scif3_ctrl_mux[] = { 1843 RTS3_N_MARK, CTS3_N_MARK, 1844 }; 1845 1846 /* - SCIF4 ------------------------------------------------------------------ */ 1847 static const unsigned int scif4_data_pins[] = { 1848 /* RX4, TX4 */ 1849 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2), 1850 }; 1851 static const unsigned int scif4_data_mux[] = { 1852 RX4_MARK, TX4_MARK, 1853 }; 1854 static const unsigned int scif4_clk_pins[] = { 1855 /* SCK4 */ 1856 RCAR_GP_PIN(0, 0), 1857 }; 1858 static const unsigned int scif4_clk_mux[] = { 1859 SCK4_MARK, 1860 }; 1861 static const unsigned int scif4_ctrl_pins[] = { 1862 /* RTS4#, CTS4# */ 1863 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), 1864 }; 1865 static const unsigned int scif4_ctrl_mux[] = { 1866 RTS4_N_MARK, CTS4_N_MARK, 1867 }; 1868 1869 /* - SCIF Clock ------------------------------------------------------------- */ 1870 static const unsigned int scif_clk_a_pins[] = { 1871 /* SCIF_CLK */ 1872 RCAR_GP_PIN(0, 10), 1873 }; 1874 static const unsigned int scif_clk_a_mux[] = { 1875 SCIF_CLK_A_MARK, 1876 }; 1877 static const unsigned int scif_clk_b_pins[] = { 1878 /* SCIF_CLK */ 1879 RCAR_GP_PIN(1, 25), 1880 }; 1881 static const unsigned int scif_clk_b_mux[] = { 1882 SCIF_CLK_B_MARK, 1883 }; 1884 1885 /* - TMU -------------------------------------------------------------------- */ 1886 static const unsigned int tmu_tclk1_a_pins[] = { 1887 /* TCLK1 */ 1888 RCAR_GP_PIN(3, 13), 1889 }; 1890 static const unsigned int tmu_tclk1_a_mux[] = { 1891 TCLK1_A_MARK, 1892 }; 1893 static const unsigned int tmu_tclk1_b_pins[] = { 1894 /* TCLK1 */ 1895 RCAR_GP_PIN(1, 23), 1896 }; 1897 static const unsigned int tmu_tclk1_b_mux[] = { 1898 TCLK1_B_MARK, 1899 }; 1900 static const unsigned int tmu_tclk2_a_pins[] = { 1901 /* TCLK2 */ 1902 RCAR_GP_PIN(3, 14), 1903 }; 1904 static const unsigned int tmu_tclk2_a_mux[] = { 1905 TCLK2_A_MARK, 1906 }; 1907 static const unsigned int tmu_tclk2_b_pins[] = { 1908 /* TCLK2 */ 1909 RCAR_GP_PIN(1, 24), 1910 }; 1911 static const unsigned int tmu_tclk2_b_mux[] = { 1912 TCLK2_B_MARK, 1913 }; 1914 1915 /* - TPU ------------------------------------------------------------------- */ 1916 static const unsigned int tpu_to0_pins[] = { 1917 /* TPU0TO0 */ 1918 RCAR_GP_PIN(1, 19), 1919 }; 1920 static const unsigned int tpu_to0_mux[] = { 1921 TPU0TO0_MARK, 1922 }; 1923 static const unsigned int tpu_to1_pins[] = { 1924 /* TPU0TO1 */ 1925 RCAR_GP_PIN(1, 20), 1926 }; 1927 static const unsigned int tpu_to1_mux[] = { 1928 TPU0TO1_MARK, 1929 }; 1930 static const unsigned int tpu_to2_pins[] = { 1931 /* TPU0TO2 */ 1932 RCAR_GP_PIN(4, 2), 1933 }; 1934 static const unsigned int tpu_to2_mux[] = { 1935 TPU0TO2_MARK, 1936 }; 1937 static const unsigned int tpu_to3_pins[] = { 1938 /* TPU0TO3 */ 1939 RCAR_GP_PIN(4, 3), 1940 }; 1941 static const unsigned int tpu_to3_mux[] = { 1942 TPU0TO3_MARK, 1943 }; 1944 1945 /* - VIN0 ------------------------------------------------------------------- */ 1946 static const union vin_data vin0_data_pins = { 1947 .data24 = { 1948 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 1949 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 1950 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 1951 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), 1952 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), 1953 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), 1954 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), 1955 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), 1956 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), 1957 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24), 1958 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26), 1959 RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28), 1960 }, 1961 }; 1962 static const union vin_data vin0_data_mux = { 1963 .data24 = { 1964 VI0_DATA0_MARK, VI0_DATA1_MARK, 1965 VI0_DATA2_MARK, VI0_DATA3_MARK, 1966 VI0_DATA4_MARK, VI0_DATA5_MARK, 1967 VI0_DATA6_MARK, VI0_DATA7_MARK, 1968 VI0_DATA8_MARK, VI0_DATA9_MARK, 1969 VI0_DATA10_MARK, VI0_DATA11_MARK, 1970 VI0_DATA12_MARK, VI0_DATA13_MARK, 1971 VI0_DATA14_MARK, VI0_DATA15_MARK, 1972 VI0_DATA16_MARK, VI0_DATA17_MARK, 1973 VI0_DATA18_MARK, VI0_DATA19_MARK, 1974 VI0_DATA20_MARK, VI0_DATA21_MARK, 1975 VI0_DATA22_MARK, VI0_DATA23_MARK, 1976 }, 1977 }; 1978 static const unsigned int vin0_data18_pins[] = { 1979 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 1980 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 1981 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), 1982 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), 1983 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), 1984 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), 1985 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24), 1986 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26), 1987 RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28), 1988 }; 1989 static const unsigned int vin0_data18_mux[] = { 1990 VI0_DATA2_MARK, VI0_DATA3_MARK, 1991 VI0_DATA4_MARK, VI0_DATA5_MARK, 1992 VI0_DATA6_MARK, VI0_DATA7_MARK, 1993 VI0_DATA10_MARK, VI0_DATA11_MARK, 1994 VI0_DATA12_MARK, VI0_DATA13_MARK, 1995 VI0_DATA14_MARK, VI0_DATA15_MARK, 1996 VI0_DATA18_MARK, VI0_DATA19_MARK, 1997 VI0_DATA20_MARK, VI0_DATA21_MARK, 1998 VI0_DATA22_MARK, VI0_DATA23_MARK, 1999 }; 2000 static const unsigned int vin0_sync_pins[] = { 2001 /* VI0_VSYNC#, VI0_HSYNC# */ 2002 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2), 2003 }; 2004 static const unsigned int vin0_sync_mux[] = { 2005 VI0_VSYNC_N_MARK, VI0_HSYNC_N_MARK, 2006 }; 2007 static const unsigned int vin0_field_pins[] = { 2008 /* VI0_FIELD */ 2009 RCAR_GP_PIN(2, 16), 2010 }; 2011 static const unsigned int vin0_field_mux[] = { 2012 VI0_FIELD_MARK, 2013 }; 2014 static const unsigned int vin0_clkenb_pins[] = { 2015 /* VI0_CLKENB */ 2016 RCAR_GP_PIN(2, 1), 2017 }; 2018 static const unsigned int vin0_clkenb_mux[] = { 2019 VI0_CLKENB_MARK, 2020 }; 2021 static const unsigned int vin0_clk_pins[] = { 2022 /* VI0_CLK */ 2023 RCAR_GP_PIN(2, 0), 2024 }; 2025 static const unsigned int vin0_clk_mux[] = { 2026 VI0_CLK_MARK, 2027 }; 2028 2029 /* - VIN1 ------------------------------------------------------------------- */ 2030 static const union vin_data12 vin1_data_pins = { 2031 .data12 = { 2032 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), 2033 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 2034 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 2035 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 2036 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), 2037 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), 2038 }, 2039 }; 2040 static const union vin_data12 vin1_data_mux = { 2041 .data12 = { 2042 VI1_DATA0_MARK, VI1_DATA1_MARK, 2043 VI1_DATA2_MARK, VI1_DATA3_MARK, 2044 VI1_DATA4_MARK, VI1_DATA5_MARK, 2045 VI1_DATA6_MARK, VI1_DATA7_MARK, 2046 VI1_DATA8_MARK, VI1_DATA9_MARK, 2047 VI1_DATA10_MARK, VI1_DATA11_MARK, 2048 }, 2049 }; 2050 static const unsigned int vin1_sync_pins[] = { 2051 /* VI1_VSYNC#, VI1_HSYNC# */ 2052 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2), 2053 }; 2054 static const unsigned int vin1_sync_mux[] = { 2055 VI1_VSYNC_N_MARK, VI1_HSYNC_N_MARK, 2056 }; 2057 static const unsigned int vin1_field_pins[] = { 2058 /* VI1_FIELD */ 2059 RCAR_GP_PIN(3, 16), 2060 }; 2061 static const unsigned int vin1_field_mux[] = { 2062 VI1_FIELD_MARK, 2063 }; 2064 static const unsigned int vin1_clkenb_pins[] = { 2065 /* VI1_CLKENB */ 2066 RCAR_GP_PIN(3, 1), 2067 }; 2068 static const unsigned int vin1_clkenb_mux[] = { 2069 VI1_CLKENB_MARK, 2070 }; 2071 static const unsigned int vin1_clk_pins[] = { 2072 /* VI1_CLK */ 2073 RCAR_GP_PIN(3, 0), 2074 }; 2075 static const unsigned int vin1_clk_mux[] = { 2076 VI1_CLK_MARK, 2077 }; 2078 2079 static const struct sh_pfc_pin_group pinmux_groups[] = { 2080 SH_PFC_PIN_GROUP(avb_link), 2081 SH_PFC_PIN_GROUP(avb_magic), 2082 SH_PFC_PIN_GROUP(avb_phy_int), 2083 SH_PFC_PIN_GROUP(avb_mdio), 2084 SH_PFC_PIN_GROUP(avb_rgmii), 2085 SH_PFC_PIN_GROUP(avb_txcrefclk), 2086 SH_PFC_PIN_GROUP(avb_avtp_pps), 2087 SH_PFC_PIN_GROUP(avb_avtp_capture), 2088 SH_PFC_PIN_GROUP(avb_avtp_match), 2089 SH_PFC_PIN_GROUP(canfd0_data_a), 2090 SH_PFC_PIN_GROUP(canfd0_data_b), 2091 SH_PFC_PIN_GROUP(canfd1_data), 2092 SH_PFC_PIN_GROUP(canfd_clk_a), 2093 SH_PFC_PIN_GROUP(canfd_clk_b), 2094 SH_PFC_PIN_GROUP(du_rgb666), 2095 SH_PFC_PIN_GROUP(du_rgb888), 2096 SH_PFC_PIN_GROUP(du_clk_out), 2097 SH_PFC_PIN_GROUP(du_sync), 2098 SH_PFC_PIN_GROUP(du_oddf), 2099 SH_PFC_PIN_GROUP(du_cde), 2100 SH_PFC_PIN_GROUP(du_disp), 2101 SH_PFC_PIN_GROUP(gether_link_a), 2102 SH_PFC_PIN_GROUP(gether_phy_int_a), 2103 SH_PFC_PIN_GROUP(gether_mdio_a), 2104 SH_PFC_PIN_GROUP(gether_link_b), 2105 SH_PFC_PIN_GROUP(gether_phy_int_b), 2106 SH_PFC_PIN_GROUP(gether_mdio_b), 2107 SH_PFC_PIN_GROUP(gether_magic), 2108 SH_PFC_PIN_GROUP(gether_rgmii), 2109 SH_PFC_PIN_GROUP(gether_txcrefclk), 2110 SH_PFC_PIN_GROUP(gether_txcrefclk_mega), 2111 SH_PFC_PIN_GROUP(gether_rmii), 2112 SH_PFC_PIN_GROUP(hscif0_data_a), 2113 SH_PFC_PIN_GROUP(hscif0_clk_a), 2114 SH_PFC_PIN_GROUP(hscif0_ctrl_a), 2115 SH_PFC_PIN_GROUP(hscif0_data_b), 2116 SH_PFC_PIN_GROUP(hscif0_clk_b), 2117 SH_PFC_PIN_GROUP(hscif0_ctrl_b), 2118 SH_PFC_PIN_GROUP(hscif1_data), 2119 SH_PFC_PIN_GROUP(hscif1_clk), 2120 SH_PFC_PIN_GROUP(hscif1_ctrl), 2121 SH_PFC_PIN_GROUP(hscif2_data), 2122 SH_PFC_PIN_GROUP(hscif2_clk), 2123 SH_PFC_PIN_GROUP(hscif2_ctrl), 2124 SH_PFC_PIN_GROUP(hscif3_data), 2125 SH_PFC_PIN_GROUP(hscif3_clk), 2126 SH_PFC_PIN_GROUP(hscif3_ctrl), 2127 SH_PFC_PIN_GROUP(i2c0), 2128 SH_PFC_PIN_GROUP(i2c1), 2129 SH_PFC_PIN_GROUP(i2c2), 2130 SH_PFC_PIN_GROUP(i2c3), 2131 SH_PFC_PIN_GROUP(i2c4), 2132 SH_PFC_PIN_GROUP(i2c5), 2133 SH_PFC_PIN_GROUP(intc_ex_irq0), 2134 SH_PFC_PIN_GROUP(intc_ex_irq1), 2135 SH_PFC_PIN_GROUP(intc_ex_irq2), 2136 SH_PFC_PIN_GROUP(intc_ex_irq3), 2137 SH_PFC_PIN_GROUP(intc_ex_irq4), 2138 SH_PFC_PIN_GROUP(intc_ex_irq5), 2139 SH_PFC_PIN_GROUP(mmc_data1), 2140 SH_PFC_PIN_GROUP(mmc_data4), 2141 SH_PFC_PIN_GROUP(mmc_data8), 2142 SH_PFC_PIN_GROUP(mmc_ctrl), 2143 SH_PFC_PIN_GROUP(mmc_cd), 2144 SH_PFC_PIN_GROUP(mmc_wp), 2145 SH_PFC_PIN_GROUP(mmc_ds), 2146 SH_PFC_PIN_GROUP(msiof0_clk), 2147 SH_PFC_PIN_GROUP(msiof0_sync), 2148 SH_PFC_PIN_GROUP(msiof0_ss1), 2149 SH_PFC_PIN_GROUP(msiof0_ss2), 2150 SH_PFC_PIN_GROUP(msiof0_txd), 2151 SH_PFC_PIN_GROUP(msiof0_rxd), 2152 SH_PFC_PIN_GROUP(msiof1_clk), 2153 SH_PFC_PIN_GROUP(msiof1_sync), 2154 SH_PFC_PIN_GROUP(msiof1_ss1), 2155 SH_PFC_PIN_GROUP(msiof1_ss2), 2156 SH_PFC_PIN_GROUP(msiof1_txd), 2157 SH_PFC_PIN_GROUP(msiof1_rxd), 2158 SH_PFC_PIN_GROUP(msiof2_clk), 2159 SH_PFC_PIN_GROUP(msiof2_sync), 2160 SH_PFC_PIN_GROUP(msiof2_ss1), 2161 SH_PFC_PIN_GROUP(msiof2_ss2), 2162 SH_PFC_PIN_GROUP(msiof2_txd), 2163 SH_PFC_PIN_GROUP(msiof2_rxd), 2164 SH_PFC_PIN_GROUP(msiof3_clk), 2165 SH_PFC_PIN_GROUP(msiof3_sync), 2166 SH_PFC_PIN_GROUP(msiof3_ss1), 2167 SH_PFC_PIN_GROUP(msiof3_ss2), 2168 SH_PFC_PIN_GROUP(msiof3_txd), 2169 SH_PFC_PIN_GROUP(msiof3_rxd), 2170 SH_PFC_PIN_GROUP(pwm0_a), 2171 SH_PFC_PIN_GROUP(pwm0_b), 2172 SH_PFC_PIN_GROUP(pwm1_a), 2173 SH_PFC_PIN_GROUP(pwm1_b), 2174 SH_PFC_PIN_GROUP(pwm2_a), 2175 SH_PFC_PIN_GROUP(pwm2_b), 2176 SH_PFC_PIN_GROUP(pwm3_a), 2177 SH_PFC_PIN_GROUP(pwm3_b), 2178 SH_PFC_PIN_GROUP(pwm4_a), 2179 SH_PFC_PIN_GROUP(pwm4_b), 2180 SH_PFC_PIN_GROUP(qspi0_ctrl), 2181 SH_PFC_PIN_GROUP(qspi0_data2), 2182 SH_PFC_PIN_GROUP(qspi0_data4), 2183 SH_PFC_PIN_GROUP(qspi1_ctrl), 2184 SH_PFC_PIN_GROUP(qspi1_data2), 2185 SH_PFC_PIN_GROUP(qspi1_data4), 2186 SH_PFC_PIN_GROUP(rpc_clk1), 2187 SH_PFC_PIN_GROUP(rpc_clk2), 2188 SH_PFC_PIN_GROUP(rpc_ctrl), 2189 SH_PFC_PIN_GROUP(rpc_data), 2190 SH_PFC_PIN_GROUP(rpc_reset), 2191 SH_PFC_PIN_GROUP(rpc_int), 2192 SH_PFC_PIN_GROUP(rpc_wp), 2193 SH_PFC_PIN_GROUP(scif0_data), 2194 SH_PFC_PIN_GROUP(scif0_clk), 2195 SH_PFC_PIN_GROUP(scif0_ctrl), 2196 SH_PFC_PIN_GROUP(scif1_data_a), 2197 SH_PFC_PIN_GROUP(scif1_clk), 2198 SH_PFC_PIN_GROUP(scif1_ctrl), 2199 SH_PFC_PIN_GROUP(scif1_data_b), 2200 SH_PFC_PIN_GROUP(scif3_data), 2201 SH_PFC_PIN_GROUP(scif3_clk), 2202 SH_PFC_PIN_GROUP(scif3_ctrl), 2203 SH_PFC_PIN_GROUP(scif4_data), 2204 SH_PFC_PIN_GROUP(scif4_clk), 2205 SH_PFC_PIN_GROUP(scif4_ctrl), 2206 SH_PFC_PIN_GROUP(scif_clk_a), 2207 SH_PFC_PIN_GROUP(scif_clk_b), 2208 SH_PFC_PIN_GROUP(tmu_tclk1_a), 2209 SH_PFC_PIN_GROUP(tmu_tclk1_b), 2210 SH_PFC_PIN_GROUP(tmu_tclk2_a), 2211 SH_PFC_PIN_GROUP(tmu_tclk2_b), 2212 SH_PFC_PIN_GROUP(tpu_to0), 2213 SH_PFC_PIN_GROUP(tpu_to1), 2214 SH_PFC_PIN_GROUP(tpu_to2), 2215 SH_PFC_PIN_GROUP(tpu_to3), 2216 VIN_DATA_PIN_GROUP(vin0_data, 8), 2217 VIN_DATA_PIN_GROUP(vin0_data, 10), 2218 VIN_DATA_PIN_GROUP(vin0_data, 12), 2219 VIN_DATA_PIN_GROUP(vin0_data, 16), 2220 SH_PFC_PIN_GROUP(vin0_data18), 2221 VIN_DATA_PIN_GROUP(vin0_data, 20), 2222 VIN_DATA_PIN_GROUP(vin0_data, 24), 2223 SH_PFC_PIN_GROUP(vin0_sync), 2224 SH_PFC_PIN_GROUP(vin0_field), 2225 SH_PFC_PIN_GROUP(vin0_clkenb), 2226 SH_PFC_PIN_GROUP(vin0_clk), 2227 VIN_DATA_PIN_GROUP(vin1_data, 8), 2228 VIN_DATA_PIN_GROUP(vin1_data, 10), 2229 VIN_DATA_PIN_GROUP(vin1_data, 12), 2230 SH_PFC_PIN_GROUP(vin1_sync), 2231 SH_PFC_PIN_GROUP(vin1_field), 2232 SH_PFC_PIN_GROUP(vin1_clkenb), 2233 SH_PFC_PIN_GROUP(vin1_clk), 2234 }; 2235 2236 static const char * const avb_groups[] = { 2237 "avb_link", 2238 "avb_magic", 2239 "avb_phy_int", 2240 "avb_mdio", 2241 "avb_rgmii", 2242 "avb_txcrefclk", 2243 "avb_avtp_pps", 2244 "avb_avtp_capture", 2245 "avb_avtp_match", 2246 }; 2247 2248 static const char * const canfd0_groups[] = { 2249 "canfd0_data_a", 2250 "canfd0_data_b", 2251 }; 2252 2253 static const char * const canfd1_groups[] = { 2254 "canfd1_data", 2255 }; 2256 2257 static const char * const canfd_clk_groups[] = { 2258 "canfd_clk_a", 2259 "canfd_clk_b", 2260 }; 2261 2262 static const char * const du_groups[] = { 2263 "du_rgb666", 2264 "du_rgb888", 2265 "du_clk_out", 2266 "du_sync", 2267 "du_oddf", 2268 "du_cde", 2269 "du_disp", 2270 }; 2271 2272 static const char * const gether_groups[] = { 2273 "gether_link_a", 2274 "gether_phy_int_a", 2275 "gether_mdio_a", 2276 "gether_link_b", 2277 "gether_phy_int_b", 2278 "gether_mdio_b", 2279 "gether_magic", 2280 "gether_rgmii", 2281 "gether_txcrefclk", 2282 "gether_txcrefclk_mega", 2283 "gether_rmii", 2284 }; 2285 2286 static const char * const hscif0_groups[] = { 2287 "hscif0_data_a", 2288 "hscif0_clk_a", 2289 "hscif0_ctrl_a", 2290 "hscif0_data_b", 2291 "hscif0_clk_b", 2292 "hscif0_ctrl_b", 2293 }; 2294 2295 static const char * const hscif1_groups[] = { 2296 "hscif1_data", 2297 "hscif1_clk", 2298 "hscif1_ctrl", 2299 }; 2300 2301 static const char * const hscif2_groups[] = { 2302 "hscif2_data", 2303 "hscif2_clk", 2304 "hscif2_ctrl", 2305 }; 2306 2307 static const char * const hscif3_groups[] = { 2308 "hscif3_data", 2309 "hscif3_clk", 2310 "hscif3_ctrl", 2311 }; 2312 2313 static const char * const i2c0_groups[] = { 2314 "i2c0", 2315 }; 2316 2317 static const char * const i2c1_groups[] = { 2318 "i2c1", 2319 }; 2320 2321 static const char * const i2c2_groups[] = { 2322 "i2c2", 2323 }; 2324 2325 static const char * const i2c3_groups[] = { 2326 "i2c3", 2327 }; 2328 2329 static const char * const i2c4_groups[] = { 2330 "i2c4", 2331 }; 2332 2333 static const char * const i2c5_groups[] = { 2334 "i2c5", 2335 }; 2336 2337 static const char * const intc_ex_groups[] = { 2338 "intc_ex_irq0", 2339 "intc_ex_irq1", 2340 "intc_ex_irq2", 2341 "intc_ex_irq3", 2342 "intc_ex_irq4", 2343 "intc_ex_irq5", 2344 }; 2345 2346 static const char * const mmc_groups[] = { 2347 "mmc_data1", 2348 "mmc_data4", 2349 "mmc_data8", 2350 "mmc_ctrl", 2351 "mmc_cd", 2352 "mmc_wp", 2353 "mmc_ds", 2354 }; 2355 2356 static const char * const msiof0_groups[] = { 2357 "msiof0_clk", 2358 "msiof0_sync", 2359 "msiof0_ss1", 2360 "msiof0_ss2", 2361 "msiof0_txd", 2362 "msiof0_rxd", 2363 }; 2364 2365 static const char * const msiof1_groups[] = { 2366 "msiof1_clk", 2367 "msiof1_sync", 2368 "msiof1_ss1", 2369 "msiof1_ss2", 2370 "msiof1_txd", 2371 "msiof1_rxd", 2372 }; 2373 2374 static const char * const msiof2_groups[] = { 2375 "msiof2_clk", 2376 "msiof2_sync", 2377 "msiof2_ss1", 2378 "msiof2_ss2", 2379 "msiof2_txd", 2380 "msiof2_rxd", 2381 }; 2382 2383 static const char * const msiof3_groups[] = { 2384 "msiof3_clk", 2385 "msiof3_sync", 2386 "msiof3_ss1", 2387 "msiof3_ss2", 2388 "msiof3_txd", 2389 "msiof3_rxd", 2390 }; 2391 2392 static const char * const pwm0_groups[] = { 2393 "pwm0_a", 2394 "pwm0_b", 2395 }; 2396 2397 static const char * const pwm1_groups[] = { 2398 "pwm1_a", 2399 "pwm1_b", 2400 }; 2401 2402 static const char * const pwm2_groups[] = { 2403 "pwm2_a", 2404 "pwm2_b", 2405 }; 2406 2407 static const char * const pwm3_groups[] = { 2408 "pwm3_a", 2409 "pwm3_b", 2410 }; 2411 2412 static const char * const pwm4_groups[] = { 2413 "pwm4_a", 2414 "pwm4_b", 2415 }; 2416 2417 static const char * const qspi0_groups[] = { 2418 "qspi0_ctrl", 2419 "qspi0_data2", 2420 "qspi0_data4", 2421 }; 2422 2423 static const char * const qspi1_groups[] = { 2424 "qspi1_ctrl", 2425 "qspi1_data2", 2426 "qspi1_data4", 2427 }; 2428 2429 static const char * const rpc_groups[] = { 2430 "rpc_clk1", 2431 "rpc_clk2", 2432 "rpc_ctrl", 2433 "rpc_data", 2434 "rpc_reset", 2435 "rpc_int", 2436 "rpc_wp", 2437 }; 2438 2439 static const char * const scif0_groups[] = { 2440 "scif0_data", 2441 "scif0_clk", 2442 "scif0_ctrl", 2443 }; 2444 2445 static const char * const scif1_groups[] = { 2446 "scif1_data_a", 2447 "scif1_clk", 2448 "scif1_ctrl", 2449 "scif1_data_b", 2450 }; 2451 2452 static const char * const scif3_groups[] = { 2453 "scif3_data", 2454 "scif3_clk", 2455 "scif3_ctrl", 2456 }; 2457 2458 static const char * const scif4_groups[] = { 2459 "scif4_data", 2460 "scif4_clk", 2461 "scif4_ctrl", 2462 }; 2463 2464 static const char * const scif_clk_groups[] = { 2465 "scif_clk_a", 2466 "scif_clk_b", 2467 }; 2468 2469 static const char * const tmu_groups[] = { 2470 "tmu_tclk1_a", 2471 "tmu_tclk1_b", 2472 "tmu_tclk2_a", 2473 "tmu_tclk2_b", 2474 }; 2475 2476 static const char * const tpu_groups[] = { 2477 "tpu_to0", 2478 "tpu_to1", 2479 "tpu_to2", 2480 "tpu_to3", 2481 }; 2482 2483 static const char * const vin0_groups[] = { 2484 "vin0_data8", 2485 "vin0_data10", 2486 "vin0_data12", 2487 "vin0_data16", 2488 "vin0_data18", 2489 "vin0_data20", 2490 "vin0_data24", 2491 "vin0_sync", 2492 "vin0_field", 2493 "vin0_clkenb", 2494 "vin0_clk", 2495 }; 2496 2497 static const char * const vin1_groups[] = { 2498 "vin1_data8", 2499 "vin1_data10", 2500 "vin1_data12", 2501 "vin1_sync", 2502 "vin1_field", 2503 "vin1_clkenb", 2504 "vin1_clk", 2505 }; 2506 2507 static const struct sh_pfc_function pinmux_functions[] = { 2508 SH_PFC_FUNCTION(avb), 2509 SH_PFC_FUNCTION(canfd0), 2510 SH_PFC_FUNCTION(canfd1), 2511 SH_PFC_FUNCTION(canfd_clk), 2512 SH_PFC_FUNCTION(du), 2513 SH_PFC_FUNCTION(gether), 2514 SH_PFC_FUNCTION(hscif0), 2515 SH_PFC_FUNCTION(hscif1), 2516 SH_PFC_FUNCTION(hscif2), 2517 SH_PFC_FUNCTION(hscif3), 2518 SH_PFC_FUNCTION(i2c0), 2519 SH_PFC_FUNCTION(i2c1), 2520 SH_PFC_FUNCTION(i2c2), 2521 SH_PFC_FUNCTION(i2c3), 2522 SH_PFC_FUNCTION(i2c4), 2523 SH_PFC_FUNCTION(i2c5), 2524 SH_PFC_FUNCTION(intc_ex), 2525 SH_PFC_FUNCTION(mmc), 2526 SH_PFC_FUNCTION(msiof0), 2527 SH_PFC_FUNCTION(msiof1), 2528 SH_PFC_FUNCTION(msiof2), 2529 SH_PFC_FUNCTION(msiof3), 2530 SH_PFC_FUNCTION(pwm0), 2531 SH_PFC_FUNCTION(pwm1), 2532 SH_PFC_FUNCTION(pwm2), 2533 SH_PFC_FUNCTION(pwm3), 2534 SH_PFC_FUNCTION(pwm4), 2535 SH_PFC_FUNCTION(qspi0), 2536 SH_PFC_FUNCTION(qspi1), 2537 SH_PFC_FUNCTION(rpc), 2538 SH_PFC_FUNCTION(scif0), 2539 SH_PFC_FUNCTION(scif1), 2540 SH_PFC_FUNCTION(scif3), 2541 SH_PFC_FUNCTION(scif4), 2542 SH_PFC_FUNCTION(scif_clk), 2543 SH_PFC_FUNCTION(tmu), 2544 SH_PFC_FUNCTION(tpu), 2545 SH_PFC_FUNCTION(vin0), 2546 SH_PFC_FUNCTION(vin1), 2547 }; 2548 2549 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 2550 #define F_(x, y) FN_##y 2551 #define FM(x) FN_##x 2552 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( 2553 0, 0, 2554 0, 0, 2555 0, 0, 2556 0, 0, 2557 0, 0, 2558 0, 0, 2559 0, 0, 2560 0, 0, 2561 0, 0, 2562 0, 0, 2563 GP_0_21_FN, GPSR0_21, 2564 GP_0_20_FN, GPSR0_20, 2565 GP_0_19_FN, GPSR0_19, 2566 GP_0_18_FN, GPSR0_18, 2567 GP_0_17_FN, GPSR0_17, 2568 GP_0_16_FN, GPSR0_16, 2569 GP_0_15_FN, GPSR0_15, 2570 GP_0_14_FN, GPSR0_14, 2571 GP_0_13_FN, GPSR0_13, 2572 GP_0_12_FN, GPSR0_12, 2573 GP_0_11_FN, GPSR0_11, 2574 GP_0_10_FN, GPSR0_10, 2575 GP_0_9_FN, GPSR0_9, 2576 GP_0_8_FN, GPSR0_8, 2577 GP_0_7_FN, GPSR0_7, 2578 GP_0_6_FN, GPSR0_6, 2579 GP_0_5_FN, GPSR0_5, 2580 GP_0_4_FN, GPSR0_4, 2581 GP_0_3_FN, GPSR0_3, 2582 GP_0_2_FN, GPSR0_2, 2583 GP_0_1_FN, GPSR0_1, 2584 GP_0_0_FN, GPSR0_0, )) 2585 }, 2586 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( 2587 0, 0, 2588 0, 0, 2589 0, 0, 2590 0, 0, 2591 GP_1_27_FN, GPSR1_27, 2592 GP_1_26_FN, GPSR1_26, 2593 GP_1_25_FN, GPSR1_25, 2594 GP_1_24_FN, GPSR1_24, 2595 GP_1_23_FN, GPSR1_23, 2596 GP_1_22_FN, GPSR1_22, 2597 GP_1_21_FN, GPSR1_21, 2598 GP_1_20_FN, GPSR1_20, 2599 GP_1_19_FN, GPSR1_19, 2600 GP_1_18_FN, GPSR1_18, 2601 GP_1_17_FN, GPSR1_17, 2602 GP_1_16_FN, GPSR1_16, 2603 GP_1_15_FN, GPSR1_15, 2604 GP_1_14_FN, GPSR1_14, 2605 GP_1_13_FN, GPSR1_13, 2606 GP_1_12_FN, GPSR1_12, 2607 GP_1_11_FN, GPSR1_11, 2608 GP_1_10_FN, GPSR1_10, 2609 GP_1_9_FN, GPSR1_9, 2610 GP_1_8_FN, GPSR1_8, 2611 GP_1_7_FN, GPSR1_7, 2612 GP_1_6_FN, GPSR1_6, 2613 GP_1_5_FN, GPSR1_5, 2614 GP_1_4_FN, GPSR1_4, 2615 GP_1_3_FN, GPSR1_3, 2616 GP_1_2_FN, GPSR1_2, 2617 GP_1_1_FN, GPSR1_1, 2618 GP_1_0_FN, GPSR1_0, )) 2619 }, 2620 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( 2621 0, 0, 2622 0, 0, 2623 GP_2_29_FN, GPSR2_29, 2624 GP_2_28_FN, GPSR2_28, 2625 GP_2_27_FN, GPSR2_27, 2626 GP_2_26_FN, GPSR2_26, 2627 GP_2_25_FN, GPSR2_25, 2628 GP_2_24_FN, GPSR2_24, 2629 GP_2_23_FN, GPSR2_23, 2630 GP_2_22_FN, GPSR2_22, 2631 GP_2_21_FN, GPSR2_21, 2632 GP_2_20_FN, GPSR2_20, 2633 GP_2_19_FN, GPSR2_19, 2634 GP_2_18_FN, GPSR2_18, 2635 GP_2_17_FN, GPSR2_17, 2636 GP_2_16_FN, GPSR2_16, 2637 GP_2_15_FN, GPSR2_15, 2638 GP_2_14_FN, GPSR2_14, 2639 GP_2_13_FN, GPSR2_13, 2640 GP_2_12_FN, GPSR2_12, 2641 GP_2_11_FN, GPSR2_11, 2642 GP_2_10_FN, GPSR2_10, 2643 GP_2_9_FN, GPSR2_9, 2644 GP_2_8_FN, GPSR2_8, 2645 GP_2_7_FN, GPSR2_7, 2646 GP_2_6_FN, GPSR2_6, 2647 GP_2_5_FN, GPSR2_5, 2648 GP_2_4_FN, GPSR2_4, 2649 GP_2_3_FN, GPSR2_3, 2650 GP_2_2_FN, GPSR2_2, 2651 GP_2_1_FN, GPSR2_1, 2652 GP_2_0_FN, GPSR2_0, )) 2653 }, 2654 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( 2655 0, 0, 2656 0, 0, 2657 0, 0, 2658 0, 0, 2659 0, 0, 2660 0, 0, 2661 0, 0, 2662 0, 0, 2663 0, 0, 2664 0, 0, 2665 0, 0, 2666 0, 0, 2667 0, 0, 2668 0, 0, 2669 0, 0, 2670 GP_3_16_FN, GPSR3_16, 2671 GP_3_15_FN, GPSR3_15, 2672 GP_3_14_FN, GPSR3_14, 2673 GP_3_13_FN, GPSR3_13, 2674 GP_3_12_FN, GPSR3_12, 2675 GP_3_11_FN, GPSR3_11, 2676 GP_3_10_FN, GPSR3_10, 2677 GP_3_9_FN, GPSR3_9, 2678 GP_3_8_FN, GPSR3_8, 2679 GP_3_7_FN, GPSR3_7, 2680 GP_3_6_FN, GPSR3_6, 2681 GP_3_5_FN, GPSR3_5, 2682 GP_3_4_FN, GPSR3_4, 2683 GP_3_3_FN, GPSR3_3, 2684 GP_3_2_FN, GPSR3_2, 2685 GP_3_1_FN, GPSR3_1, 2686 GP_3_0_FN, GPSR3_0, )) 2687 }, 2688 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( 2689 0, 0, 2690 0, 0, 2691 0, 0, 2692 0, 0, 2693 0, 0, 2694 0, 0, 2695 0, 0, 2696 GP_4_24_FN, GPSR4_24, 2697 GP_4_23_FN, GPSR4_23, 2698 GP_4_22_FN, GPSR4_22, 2699 GP_4_21_FN, GPSR4_21, 2700 GP_4_20_FN, GPSR4_20, 2701 GP_4_19_FN, GPSR4_19, 2702 GP_4_18_FN, GPSR4_18, 2703 GP_4_17_FN, GPSR4_17, 2704 GP_4_16_FN, GPSR4_16, 2705 GP_4_15_FN, GPSR4_15, 2706 GP_4_14_FN, GPSR4_14, 2707 GP_4_13_FN, GPSR4_13, 2708 GP_4_12_FN, GPSR4_12, 2709 GP_4_11_FN, GPSR4_11, 2710 GP_4_10_FN, GPSR4_10, 2711 GP_4_9_FN, GPSR4_9, 2712 GP_4_8_FN, GPSR4_8, 2713 GP_4_7_FN, GPSR4_7, 2714 GP_4_6_FN, GPSR4_6, 2715 GP_4_5_FN, GPSR4_5, 2716 GP_4_4_FN, GPSR4_4, 2717 GP_4_3_FN, GPSR4_3, 2718 GP_4_2_FN, GPSR4_2, 2719 GP_4_1_FN, GPSR4_1, 2720 GP_4_0_FN, GPSR4_0, )) 2721 }, 2722 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( 2723 0, 0, 2724 0, 0, 2725 0, 0, 2726 0, 0, 2727 0, 0, 2728 0, 0, 2729 0, 0, 2730 0, 0, 2731 0, 0, 2732 0, 0, 2733 0, 0, 2734 0, 0, 2735 0, 0, 2736 0, 0, 2737 0, 0, 2738 0, 0, 2739 0, 0, 2740 GP_5_14_FN, GPSR5_14, 2741 GP_5_13_FN, GPSR5_13, 2742 GP_5_12_FN, GPSR5_12, 2743 GP_5_11_FN, GPSR5_11, 2744 GP_5_10_FN, GPSR5_10, 2745 GP_5_9_FN, GPSR5_9, 2746 GP_5_8_FN, GPSR5_8, 2747 GP_5_7_FN, GPSR5_7, 2748 GP_5_6_FN, GPSR5_6, 2749 GP_5_5_FN, GPSR5_5, 2750 GP_5_4_FN, GPSR5_4, 2751 GP_5_3_FN, GPSR5_3, 2752 GP_5_2_FN, GPSR5_2, 2753 GP_5_1_FN, GPSR5_1, 2754 GP_5_0_FN, GPSR5_0, )) 2755 }, 2756 #undef F_ 2757 #undef FM 2758 2759 #define F_(x, y) x, 2760 #define FM(x) FN_##x, 2761 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( 2762 IP0_31_28 2763 IP0_27_24 2764 IP0_23_20 2765 IP0_19_16 2766 IP0_15_12 2767 IP0_11_8 2768 IP0_7_4 2769 IP0_3_0 )) 2770 }, 2771 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( 2772 IP1_31_28 2773 IP1_27_24 2774 IP1_23_20 2775 IP1_19_16 2776 IP1_15_12 2777 IP1_11_8 2778 IP1_7_4 2779 IP1_3_0 )) 2780 }, 2781 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( 2782 IP2_31_28 2783 IP2_27_24 2784 IP2_23_20 2785 IP2_19_16 2786 IP2_15_12 2787 IP2_11_8 2788 IP2_7_4 2789 IP2_3_0 )) 2790 }, 2791 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( 2792 IP3_31_28 2793 IP3_27_24 2794 IP3_23_20 2795 IP3_19_16 2796 IP3_15_12 2797 IP3_11_8 2798 IP3_7_4 2799 IP3_3_0 )) 2800 }, 2801 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( 2802 IP4_31_28 2803 IP4_27_24 2804 IP4_23_20 2805 IP4_19_16 2806 IP4_15_12 2807 IP4_11_8 2808 IP4_7_4 2809 IP4_3_0 )) 2810 }, 2811 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( 2812 IP5_31_28 2813 IP5_27_24 2814 IP5_23_20 2815 IP5_19_16 2816 IP5_15_12 2817 IP5_11_8 2818 IP5_7_4 2819 IP5_3_0 )) 2820 }, 2821 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( 2822 IP6_31_28 2823 IP6_27_24 2824 IP6_23_20 2825 IP6_19_16 2826 IP6_15_12 2827 IP6_11_8 2828 IP6_7_4 2829 IP6_3_0 )) 2830 }, 2831 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( 2832 IP7_31_28 2833 IP7_27_24 2834 IP7_23_20 2835 IP7_19_16 2836 IP7_15_12 2837 IP7_11_8 2838 IP7_7_4 2839 IP7_3_0 )) 2840 }, 2841 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( 2842 IP8_31_28 2843 IP8_27_24 2844 IP8_23_20 2845 IP8_19_16 2846 IP8_15_12 2847 IP8_11_8 2848 IP8_7_4 2849 IP8_3_0 )) 2850 }, 2851 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP( 2852 IP9_31_28 2853 IP9_27_24 2854 IP9_23_20 2855 IP9_19_16 2856 IP9_15_12 2857 IP9_11_8 2858 IP9_7_4 2859 IP9_3_0 )) 2860 }, 2861 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP( 2862 IP10_31_28 2863 IP10_27_24 2864 IP10_23_20 2865 IP10_19_16 2866 IP10_15_12 2867 IP10_11_8 2868 IP10_7_4 2869 IP10_3_0 )) 2870 }, 2871 #undef F_ 2872 #undef FM 2873 2874 #define F_(x, y) x, 2875 #define FM(x) FN_##x, 2876 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, 2877 GROUP(4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 2878 1, 1, 1, 1, 1), 2879 GROUP( 2880 /* RESERVED 31, 30, 29, 28 */ 2881 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2882 /* RESERVED 27, 26, 25, 24 */ 2883 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2884 /* RESERVED 23, 22, 21, 20 */ 2885 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2886 /* RESERVED 19, 18, 17, 16 */ 2887 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2888 /* RESERVED 15, 14, 13, 12 */ 2889 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2890 MOD_SEL0_11 2891 MOD_SEL0_10 2892 MOD_SEL0_9 2893 MOD_SEL0_8 2894 MOD_SEL0_7 2895 MOD_SEL0_6 2896 MOD_SEL0_5 2897 MOD_SEL0_4 2898 0, 0, 2899 MOD_SEL0_2 2900 MOD_SEL0_1 2901 MOD_SEL0_0 )) 2902 }, 2903 { }, 2904 }; 2905 2906 enum ioctrl_regs { 2907 POCCTRL0, 2908 POCCTRL1, 2909 POCCTRL2, 2910 POCCTRL3, 2911 TDSELCTRL, 2912 }; 2913 2914 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { 2915 [POCCTRL0] = { 0xe6060380, }, 2916 [POCCTRL1] = { 0xe6060384, }, 2917 [POCCTRL2] = { 0xe6060388, }, 2918 [POCCTRL3] = { 0xe606038c, }, 2919 [TDSELCTRL] = { 0xe60603c0, }, 2920 { /* sentinel */ }, 2921 }; 2922 2923 static int r8a77980_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, 2924 u32 *pocctrl) 2925 { 2926 int bit = pin & 0x1f; 2927 2928 *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg; 2929 if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21)) 2930 return bit; 2931 else if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9)) 2932 return bit + 22; 2933 2934 *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg; 2935 if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16)) 2936 return bit - 10; 2937 if ((pin >= RCAR_GP_PIN(2, 17) && pin <= RCAR_GP_PIN(2, 24)) || 2938 (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))) 2939 return bit + 7; 2940 2941 *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg; 2942 if (pin >= RCAR_GP_PIN(2, 25) && pin <= RCAR_GP_PIN(2, 29)) 2943 return pin - 25; 2944 2945 return -EINVAL; 2946 } 2947 2948 static const struct sh_pfc_soc_operations pinmux_ops = { 2949 .pin_to_pocctrl = r8a77980_pin_to_pocctrl, 2950 }; 2951 2952 const struct sh_pfc_soc_info r8a77980_pinmux_info = { 2953 .name = "r8a77980_pfc", 2954 .ops = &pinmux_ops, 2955 .unlock_reg = 0xe6060000, /* PMMR */ 2956 2957 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 2958 2959 .pins = pinmux_pins, 2960 .nr_pins = ARRAY_SIZE(pinmux_pins), 2961 .groups = pinmux_groups, 2962 .nr_groups = ARRAY_SIZE(pinmux_groups), 2963 .functions = pinmux_functions, 2964 .nr_functions = ARRAY_SIZE(pinmux_functions), 2965 2966 .cfg_regs = pinmux_config_regs, 2967 .ioctrl_regs = pinmux_ioctrl_regs, 2968 2969 .pinmux_data = pinmux_data, 2970 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 2971 }; 2972