1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * R8A77970 processor support - PFC hardware block. 4 * 5 * Copyright (C) 2016 Renesas Electronics Corp. 6 * Copyright (C) 2017 Cogent Embedded, Inc. <source@cogentembedded.com> 7 * 8 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c 9 * 10 * R-Car Gen3 processor support - PFC hardware block. 11 * 12 * Copyright (C) 2015 Renesas Electronics Corporation 13 */ 14 15 #include <linux/errno.h> 16 #include <linux/io.h> 17 #include <linux/kernel.h> 18 19 #include "sh_pfc.h" 20 21 #define CPU_ALL_GP(fn, sfx) \ 22 PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ 23 PORT_GP_28(1, fn, sfx), \ 24 PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ 25 PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ 26 PORT_GP_6(4, fn, sfx), \ 27 PORT_GP_15(5, fn, sfx) 28 /* 29 * F_() : just information 30 * FM() : macro for FN_xxx / xxx_MARK 31 */ 32 33 /* GPSR0 */ 34 #define GPSR0_21 F_(DU_EXODDF_DU_ODDF_DISP_CDE, IP2_23_20) 35 #define GPSR0_20 F_(DU_EXVSYNC_DU_VSYNC, IP2_19_16) 36 #define GPSR0_19 F_(DU_EXHSYNC_DU_HSYNC, IP2_15_12) 37 #define GPSR0_18 F_(DU_DOTCLKOUT, IP2_11_8) 38 #define GPSR0_17 F_(DU_DB7, IP2_7_4) 39 #define GPSR0_16 F_(DU_DB6, IP2_3_0) 40 #define GPSR0_15 F_(DU_DB5, IP1_31_28) 41 #define GPSR0_14 F_(DU_DB4, IP1_27_24) 42 #define GPSR0_13 F_(DU_DB3, IP1_23_20) 43 #define GPSR0_12 F_(DU_DB2, IP1_19_16) 44 #define GPSR0_11 F_(DU_DG7, IP1_15_12) 45 #define GPSR0_10 F_(DU_DG6, IP1_11_8) 46 #define GPSR0_9 F_(DU_DG5, IP1_7_4) 47 #define GPSR0_8 F_(DU_DG4, IP1_3_0) 48 #define GPSR0_7 F_(DU_DG3, IP0_31_28) 49 #define GPSR0_6 F_(DU_DG2, IP0_27_24) 50 #define GPSR0_5 F_(DU_DR7, IP0_23_20) 51 #define GPSR0_4 F_(DU_DR6, IP0_19_16) 52 #define GPSR0_3 F_(DU_DR5, IP0_15_12) 53 #define GPSR0_2 F_(DU_DR4, IP0_11_8) 54 #define GPSR0_1 F_(DU_DR3, IP0_7_4) 55 #define GPSR0_0 F_(DU_DR2, IP0_3_0) 56 57 /* GPSR1 */ 58 #define GPSR1_27 F_(DIGRF_CLKOUT, IP8_27_24) 59 #define GPSR1_26 F_(DIGRF_CLKIN, IP8_23_20) 60 #define GPSR1_25 F_(CANFD_CLK_A, IP8_19_16) 61 #define GPSR1_24 F_(CANFD1_RX, IP8_15_12) 62 #define GPSR1_23 F_(CANFD1_TX, IP8_11_8) 63 #define GPSR1_22 F_(CANFD0_RX_A, IP8_7_4) 64 #define GPSR1_21 F_(CANFD0_TX_A, IP8_3_0) 65 #define GPSR1_20 F_(AVB0_AVTP_CAPTURE, IP7_31_28) 66 #define GPSR1_19 FM(AVB0_AVTP_MATCH) 67 #define GPSR1_18 FM(AVB0_LINK) 68 #define GPSR1_17 FM(AVB0_PHY_INT) 69 #define GPSR1_16 FM(AVB0_MAGIC) 70 #define GPSR1_15 FM(AVB0_MDC) 71 #define GPSR1_14 FM(AVB0_MDIO) 72 #define GPSR1_13 FM(AVB0_TXCREFCLK) 73 #define GPSR1_12 FM(AVB0_TD3) 74 #define GPSR1_11 FM(AVB0_TD2) 75 #define GPSR1_10 FM(AVB0_TD1) 76 #define GPSR1_9 FM(AVB0_TD0) 77 #define GPSR1_8 FM(AVB0_TXC) 78 #define GPSR1_7 FM(AVB0_TX_CTL) 79 #define GPSR1_6 FM(AVB0_RD3) 80 #define GPSR1_5 FM(AVB0_RD2) 81 #define GPSR1_4 FM(AVB0_RD1) 82 #define GPSR1_3 FM(AVB0_RD0) 83 #define GPSR1_2 FM(AVB0_RXC) 84 #define GPSR1_1 FM(AVB0_RX_CTL) 85 #define GPSR1_0 F_(IRQ0, IP2_27_24) 86 87 /* GPSR2 */ 88 #define GPSR2_16 F_(VI0_FIELD, IP4_31_28) 89 #define GPSR2_15 F_(VI0_DATA11, IP4_27_24) 90 #define GPSR2_14 F_(VI0_DATA10, IP4_23_20) 91 #define GPSR2_13 F_(VI0_DATA9, IP4_19_16) 92 #define GPSR2_12 F_(VI0_DATA8, IP4_15_12) 93 #define GPSR2_11 F_(VI0_DATA7, IP4_11_8) 94 #define GPSR2_10 F_(VI0_DATA6, IP4_7_4) 95 #define GPSR2_9 F_(VI0_DATA5, IP4_3_0) 96 #define GPSR2_8 F_(VI0_DATA4, IP3_31_28) 97 #define GPSR2_7 F_(VI0_DATA3, IP3_27_24) 98 #define GPSR2_6 F_(VI0_DATA2, IP3_23_20) 99 #define GPSR2_5 F_(VI0_DATA1, IP3_19_16) 100 #define GPSR2_4 F_(VI0_DATA0, IP3_15_12) 101 #define GPSR2_3 F_(VI0_VSYNC_N, IP3_11_8) 102 #define GPSR2_2 F_(VI0_HSYNC_N, IP3_7_4) 103 #define GPSR2_1 F_(VI0_CLKENB, IP3_3_0) 104 #define GPSR2_0 F_(VI0_CLK, IP2_31_28) 105 106 /* GPSR3 */ 107 #define GPSR3_16 F_(VI1_FIELD, IP7_3_0) 108 #define GPSR3_15 F_(VI1_DATA11, IP6_31_28) 109 #define GPSR3_14 F_(VI1_DATA10, IP6_27_24) 110 #define GPSR3_13 F_(VI1_DATA9, IP6_23_20) 111 #define GPSR3_12 F_(VI1_DATA8, IP6_19_16) 112 #define GPSR3_11 F_(VI1_DATA7, IP6_15_12) 113 #define GPSR3_10 F_(VI1_DATA6, IP6_11_8) 114 #define GPSR3_9 F_(VI1_DATA5, IP6_7_4) 115 #define GPSR3_8 F_(VI1_DATA4, IP6_3_0) 116 #define GPSR3_7 F_(VI1_DATA3, IP5_31_28) 117 #define GPSR3_6 F_(VI1_DATA2, IP5_27_24) 118 #define GPSR3_5 F_(VI1_DATA1, IP5_23_20) 119 #define GPSR3_4 F_(VI1_DATA0, IP5_19_16) 120 #define GPSR3_3 F_(VI1_VSYNC_N, IP5_15_12) 121 #define GPSR3_2 F_(VI1_HSYNC_N, IP5_11_8) 122 #define GPSR3_1 F_(VI1_CLKENB, IP5_7_4) 123 #define GPSR3_0 F_(VI1_CLK, IP5_3_0) 124 125 /* GPSR4 */ 126 #define GPSR4_5 F_(SDA2, IP7_27_24) 127 #define GPSR4_4 F_(SCL2, IP7_23_20) 128 #define GPSR4_3 F_(SDA1, IP7_19_16) 129 #define GPSR4_2 F_(SCL1, IP7_15_12) 130 #define GPSR4_1 F_(SDA0, IP7_11_8) 131 #define GPSR4_0 F_(SCL0, IP7_7_4) 132 133 /* GPSR5 */ 134 #define GPSR5_14 FM(RPC_INT_N) 135 #define GPSR5_13 FM(RPC_WP_N) 136 #define GPSR5_12 FM(RPC_RESET_N) 137 #define GPSR5_11 FM(QSPI1_SSL) 138 #define GPSR5_10 FM(QSPI1_IO3) 139 #define GPSR5_9 FM(QSPI1_IO2) 140 #define GPSR5_8 FM(QSPI1_MISO_IO1) 141 #define GPSR5_7 FM(QSPI1_MOSI_IO0) 142 #define GPSR5_6 FM(QSPI1_SPCLK) 143 #define GPSR5_5 FM(QSPI0_SSL) 144 #define GPSR5_4 FM(QSPI0_IO3) 145 #define GPSR5_3 FM(QSPI0_IO2) 146 #define GPSR5_2 FM(QSPI0_MISO_IO1) 147 #define GPSR5_1 FM(QSPI0_MOSI_IO0) 148 #define GPSR5_0 FM(QSPI0_SPCLK) 149 150 151 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ 152 #define IP0_3_0 FM(DU_DR2) FM(HSCK0) F_(0, 0) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 153 #define IP0_7_4 FM(DU_DR3) FM(HRTS0_N) F_(0, 0) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 154 #define IP0_11_8 FM(DU_DR4) FM(HCTS0_N) F_(0, 0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 155 #define IP0_15_12 FM(DU_DR5) FM(HTX0) F_(0, 0) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 156 #define IP0_19_16 FM(DU_DR6) FM(MSIOF3_RXD) F_(0, 0) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 157 #define IP0_23_20 FM(DU_DR7) FM(MSIOF3_TXD) F_(0, 0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 158 #define IP0_27_24 FM(DU_DG2) FM(MSIOF3_SS1) F_(0, 0) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 159 #define IP0_31_28 FM(DU_DG3) FM(MSIOF3_SS2) F_(0, 0) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 160 #define IP1_3_0 FM(DU_DG4) F_(0, 0) F_(0, 0) FM(A8) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 161 #define IP1_7_4 FM(DU_DG5) F_(0, 0) F_(0, 0) FM(A9) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 162 #define IP1_11_8 FM(DU_DG6) F_(0, 0) F_(0, 0) FM(A10) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 163 #define IP1_15_12 FM(DU_DG7) F_(0, 0) F_(0, 0) FM(A11) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 164 #define IP1_19_16 FM(DU_DB2) F_(0, 0) F_(0, 0) FM(A12) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 165 #define IP1_23_20 FM(DU_DB3) F_(0, 0) F_(0, 0) FM(A13) FM(FXR_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 166 #define IP1_27_24 FM(DU_DB4) F_(0, 0) F_(0, 0) FM(A14) FM(FXR_CLKOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 167 #define IP1_31_28 FM(DU_DB5) F_(0, 0) F_(0, 0) FM(A15) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 168 #define IP2_3_0 FM(DU_DB6) F_(0, 0) F_(0, 0) FM(A16) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 169 #define IP2_7_4 FM(DU_DB7) F_(0, 0) F_(0, 0) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 170 #define IP2_11_8 FM(DU_DOTCLKOUT) FM(SCIF_CLK_A) F_(0, 0) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 171 #define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(HRX0) F_(0, 0) FM(A19) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 172 #define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 173 #define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 174 #define IP2_27_24 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 175 #define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 176 #define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 177 #define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 178 #define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 179 #define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 180 #define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 181 #define IP3_23_20 FM(VI0_DATA2) FM(AVB0_AVTP_PPS) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 182 #define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 183 #define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 184 #define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 185 #define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 186 #define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 187 #define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) FM(PWM0_A) FM(A22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 188 #define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) FM(A23) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 189 #define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) FM(A24) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 190 #define IP4_27_24 FM(VI0_DATA11) FM(HTX2) FM(PWM3_A) FM(A25) FM(FSO_TOE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 191 #define IP4_31_28 FM(VI0_FIELD) FM(HRX2) FM(PWM4_A) FM(CS1_N) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 192 #define IP5_3_0 FM(VI1_CLK) FM(MSIOF1_RXD) F_(0, 0) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 193 #define IP5_7_4 FM(VI1_CLKENB) FM(MSIOF1_TXD) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 194 #define IP5_11_8 FM(VI1_HSYNC_N) FM(MSIOF1_SCK) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 195 #define IP5_15_12 FM(VI1_VSYNC_N) FM(MSIOF1_SYNC) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 196 #define IP5_19_16 FM(VI1_DATA0) FM(MSIOF1_SS1) F_(0, 0) FM(D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 197 #define IP5_23_20 FM(VI1_DATA1) FM(MSIOF1_SS2) F_(0, 0) FM(D4) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 198 #define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 199 #define IP5_31_28 FM(VI1_DATA3) FM(CANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 200 #define IP6_3_0 FM(VI1_DATA4) FM(CANFD_CLK_B) F_(0, 0) FM(D7) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 201 #define IP6_7_4 FM(VI1_DATA5) F_(0, 0) FM(SCK4) FM(D8) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 202 #define IP6_11_8 FM(VI1_DATA6) F_(0, 0) FM(RX4) FM(D9) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 203 #define IP6_15_12 FM(VI1_DATA7) F_(0, 0) FM(TX4) FM(D10) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 204 #define IP6_19_16 FM(VI1_DATA8) F_(0, 0) FM(CTS4_N) FM(D11) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 205 #define IP6_23_20 FM(VI1_DATA9) F_(0, 0) FM(RTS4_N) FM(D12) FM(MMC_D6) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 206 #define IP6_27_24 FM(VI1_DATA10) F_(0, 0) F_(0, 0) FM(D13) FM(MMC_D7) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 207 #define IP6_31_28 FM(VI1_DATA11) FM(SCL4) FM(IRQ4) FM(D14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 208 #define IP7_3_0 FM(VI1_FIELD) FM(SDA4) FM(IRQ5) FM(D15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 209 #define IP7_7_4 FM(SCL0) FM(DU_DR0) FM(TPU0TO0) FM(CLKOUT) F_(0, 0) FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 210 #define IP7_11_8 FM(SDA0) FM(DU_DR1) FM(TPU0TO1) FM(BS_N) FM(SCK0) FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 211 #define IP7_15_12 FM(SCL1) FM(DU_DG0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 212 #define IP7_19_16 FM(SDA1) FM(DU_DG1) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N) FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 213 #define IP7_23_20 FM(SCL2) FM(DU_DB0) FM(TCLK1_A) FM(WE1_N) FM(RX0) FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 214 #define IP7_27_24 FM(SDA2) FM(DU_DB1) FM(TCLK2_A) FM(EX_WAIT0) FM(TX0) FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 215 #define IP7_31_28 FM(AVB0_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSCLKST2_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 216 #define IP8_3_0 FM(CANFD0_TX_A) FM(FXR_TXDA) FM(PWM0_B) FM(DU_DISP) FM(FSCLKST2_N_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 217 #define IP8_7_4 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 218 #define IP8_11_8 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 219 #define IP8_15_12 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 220 #define IP8_19_16 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 221 #define IP8_23_20 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 222 #define IP8_27_24 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 223 #define IP8_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 224 225 #define PINMUX_GPSR \ 226 \ 227 GPSR1_27 \ 228 GPSR1_26 \ 229 GPSR1_25 \ 230 GPSR1_24 \ 231 GPSR1_23 \ 232 GPSR1_22 \ 233 GPSR0_21 GPSR1_21 \ 234 GPSR0_20 GPSR1_20 \ 235 GPSR0_19 GPSR1_19 \ 236 GPSR0_18 GPSR1_18 \ 237 GPSR0_17 GPSR1_17 \ 238 GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 \ 239 GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 \ 240 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR5_14 \ 241 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR5_13 \ 242 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR5_12 \ 243 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR5_11 \ 244 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR5_10 \ 245 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR5_9 \ 246 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR5_8 \ 247 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR5_7 \ 248 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR5_6 \ 249 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 \ 250 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 \ 251 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 \ 252 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 \ 253 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 \ 254 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 255 256 #define PINMUX_IPSR \ 257 \ 258 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \ 259 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \ 260 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \ 261 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \ 262 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \ 263 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \ 264 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ 265 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \ 266 \ 267 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ 268 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ 269 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ 270 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \ 271 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ 272 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ 273 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ 274 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ 275 \ 276 FM(IP8_3_0) IP8_3_0 \ 277 FM(IP8_7_4) IP8_7_4 \ 278 FM(IP8_11_8) IP8_11_8 \ 279 FM(IP8_15_12) IP8_15_12 \ 280 FM(IP8_19_16) IP8_19_16 \ 281 FM(IP8_23_20) IP8_23_20 \ 282 FM(IP8_27_24) IP8_27_24 \ 283 FM(IP8_31_28) IP8_31_28 284 285 /* MOD_SEL0 */ /* 0 */ /* 1 */ 286 #define MOD_SEL0_11 FM(SEL_I2C3_0) FM(SEL_I2C3_1) 287 #define MOD_SEL0_10 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1) 288 #define MOD_SEL0_9 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1) 289 #define MOD_SEL0_8 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) 290 #define MOD_SEL0_7 FM(SEL_PWM4_0) FM(SEL_PWM4_1) 291 #define MOD_SEL0_6 FM(SEL_PWM3_0) FM(SEL_PWM3_1) 292 #define MOD_SEL0_5 FM(SEL_PWM2_0) FM(SEL_PWM2_1) 293 #define MOD_SEL0_4 FM(SEL_PWM1_0) FM(SEL_PWM1_1) 294 #define MOD_SEL0_3 FM(SEL_PWM0_0) FM(SEL_PWM0_1) 295 #define MOD_SEL0_2 FM(SEL_RFSO_0) FM(SEL_RFSO_1) 296 #define MOD_SEL0_1 FM(SEL_RSP_0) FM(SEL_RSP_1) 297 #define MOD_SEL0_0 FM(SEL_TMU_0) FM(SEL_TMU_1) 298 299 #define PINMUX_MOD_SELS \ 300 \ 301 MOD_SEL0_11 \ 302 MOD_SEL0_10 \ 303 MOD_SEL0_9 \ 304 MOD_SEL0_8 \ 305 MOD_SEL0_7 \ 306 MOD_SEL0_6 \ 307 MOD_SEL0_5 \ 308 MOD_SEL0_4 \ 309 MOD_SEL0_3 \ 310 MOD_SEL0_2 \ 311 MOD_SEL0_1 \ 312 MOD_SEL0_0 313 314 enum { 315 PINMUX_RESERVED = 0, 316 317 PINMUX_DATA_BEGIN, 318 GP_ALL(DATA), 319 PINMUX_DATA_END, 320 321 #define F_(x, y) 322 #define FM(x) FN_##x, 323 PINMUX_FUNCTION_BEGIN, 324 GP_ALL(FN), 325 PINMUX_GPSR 326 PINMUX_IPSR 327 PINMUX_MOD_SELS 328 PINMUX_FUNCTION_END, 329 #undef F_ 330 #undef FM 331 332 #define F_(x, y) 333 #define FM(x) x##_MARK, 334 PINMUX_MARK_BEGIN, 335 PINMUX_GPSR 336 PINMUX_IPSR 337 PINMUX_MOD_SELS 338 PINMUX_MARK_END, 339 #undef F_ 340 #undef FM 341 }; 342 343 static const u16 pinmux_data[] = { 344 PINMUX_DATA_GP_ALL(), 345 346 PINMUX_SINGLE(AVB0_RX_CTL), 347 PINMUX_SINGLE(AVB0_RXC), 348 PINMUX_SINGLE(AVB0_RD0), 349 PINMUX_SINGLE(AVB0_RD1), 350 PINMUX_SINGLE(AVB0_RD2), 351 PINMUX_SINGLE(AVB0_RD3), 352 PINMUX_SINGLE(AVB0_TX_CTL), 353 PINMUX_SINGLE(AVB0_TXC), 354 PINMUX_SINGLE(AVB0_TD0), 355 PINMUX_SINGLE(AVB0_TD1), 356 PINMUX_SINGLE(AVB0_TD2), 357 PINMUX_SINGLE(AVB0_TD3), 358 PINMUX_SINGLE(AVB0_TXCREFCLK), 359 PINMUX_SINGLE(AVB0_MDIO), 360 PINMUX_SINGLE(AVB0_MDC), 361 PINMUX_SINGLE(AVB0_MAGIC), 362 PINMUX_SINGLE(AVB0_PHY_INT), 363 PINMUX_SINGLE(AVB0_LINK), 364 PINMUX_SINGLE(AVB0_AVTP_MATCH), 365 366 PINMUX_SINGLE(QSPI0_SPCLK), 367 PINMUX_SINGLE(QSPI0_MOSI_IO0), 368 PINMUX_SINGLE(QSPI0_MISO_IO1), 369 PINMUX_SINGLE(QSPI0_IO2), 370 PINMUX_SINGLE(QSPI0_IO3), 371 PINMUX_SINGLE(QSPI0_SSL), 372 PINMUX_SINGLE(QSPI1_SPCLK), 373 PINMUX_SINGLE(QSPI1_MOSI_IO0), 374 PINMUX_SINGLE(QSPI1_MISO_IO1), 375 PINMUX_SINGLE(QSPI1_IO2), 376 PINMUX_SINGLE(QSPI1_IO3), 377 PINMUX_SINGLE(QSPI1_SSL), 378 PINMUX_SINGLE(RPC_RESET_N), 379 PINMUX_SINGLE(RPC_WP_N), 380 PINMUX_SINGLE(RPC_INT_N), 381 382 /* IPSR0 */ 383 PINMUX_IPSR_GPSR(IP0_3_0, DU_DR2), 384 PINMUX_IPSR_GPSR(IP0_3_0, HSCK0), 385 PINMUX_IPSR_GPSR(IP0_3_0, A0), 386 387 PINMUX_IPSR_GPSR(IP0_7_4, DU_DR3), 388 PINMUX_IPSR_GPSR(IP0_7_4, HRTS0_N), 389 PINMUX_IPSR_GPSR(IP0_7_4, A1), 390 391 PINMUX_IPSR_GPSR(IP0_11_8, DU_DR4), 392 PINMUX_IPSR_GPSR(IP0_11_8, HCTS0_N), 393 PINMUX_IPSR_GPSR(IP0_11_8, A2), 394 395 PINMUX_IPSR_GPSR(IP0_15_12, DU_DR5), 396 PINMUX_IPSR_GPSR(IP0_15_12, HTX0), 397 PINMUX_IPSR_GPSR(IP0_15_12, A3), 398 399 PINMUX_IPSR_GPSR(IP0_19_16, DU_DR6), 400 PINMUX_IPSR_GPSR(IP0_19_16, MSIOF3_RXD), 401 PINMUX_IPSR_GPSR(IP0_19_16, A4), 402 403 PINMUX_IPSR_GPSR(IP0_23_20, DU_DR7), 404 PINMUX_IPSR_GPSR(IP0_23_20, MSIOF3_TXD), 405 PINMUX_IPSR_GPSR(IP0_23_20, A5), 406 407 PINMUX_IPSR_GPSR(IP0_27_24, DU_DG2), 408 PINMUX_IPSR_GPSR(IP0_27_24, MSIOF3_SS1), 409 PINMUX_IPSR_GPSR(IP0_27_24, A6), 410 411 PINMUX_IPSR_GPSR(IP0_31_28, DU_DG3), 412 PINMUX_IPSR_GPSR(IP0_31_28, MSIOF3_SS2), 413 PINMUX_IPSR_GPSR(IP0_31_28, A7), 414 PINMUX_IPSR_GPSR(IP0_31_28, PWMFSW0), 415 416 /* IPSR1 */ 417 PINMUX_IPSR_GPSR(IP1_3_0, DU_DG4), 418 PINMUX_IPSR_GPSR(IP1_3_0, A8), 419 PINMUX_IPSR_MSEL(IP1_3_0, FSO_CFE_0_N_A, SEL_RFSO_0), 420 421 PINMUX_IPSR_GPSR(IP1_7_4, DU_DG5), 422 PINMUX_IPSR_GPSR(IP1_7_4, A9), 423 PINMUX_IPSR_MSEL(IP1_7_4, FSO_CFE_1_N_A, SEL_RFSO_0), 424 425 PINMUX_IPSR_GPSR(IP1_11_8, DU_DG6), 426 PINMUX_IPSR_GPSR(IP1_11_8, A10), 427 PINMUX_IPSR_MSEL(IP1_11_8, FSO_TOE_N_A, SEL_RFSO_0), 428 429 PINMUX_IPSR_GPSR(IP1_15_12, DU_DG7), 430 PINMUX_IPSR_GPSR(IP1_15_12, A11), 431 PINMUX_IPSR_GPSR(IP1_15_12, IRQ1), 432 433 PINMUX_IPSR_GPSR(IP1_19_16, DU_DB2), 434 PINMUX_IPSR_GPSR(IP1_19_16, A12), 435 PINMUX_IPSR_GPSR(IP1_19_16, IRQ2), 436 437 PINMUX_IPSR_GPSR(IP1_23_20, DU_DB3), 438 PINMUX_IPSR_GPSR(IP1_23_20, A13), 439 PINMUX_IPSR_GPSR(IP1_23_20, FXR_CLKOUT1), 440 441 PINMUX_IPSR_GPSR(IP1_27_24, DU_DB4), 442 PINMUX_IPSR_GPSR(IP1_27_24, A14), 443 PINMUX_IPSR_GPSR(IP1_27_24, FXR_CLKOUT2), 444 445 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB5), 446 PINMUX_IPSR_GPSR(IP1_31_28, A15), 447 PINMUX_IPSR_GPSR(IP1_31_28, FXR_TXENA_N), 448 449 /* IPSR2 */ 450 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB6), 451 PINMUX_IPSR_GPSR(IP2_3_0, A16), 452 PINMUX_IPSR_GPSR(IP2_3_0, FXR_TXENB_N), 453 454 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB7), 455 PINMUX_IPSR_GPSR(IP2_7_4, A17), 456 457 PINMUX_IPSR_GPSR(IP2_11_8, DU_DOTCLKOUT), 458 PINMUX_IPSR_MSEL(IP2_11_8, SCIF_CLK_A, SEL_HSCIF0_0), 459 PINMUX_IPSR_GPSR(IP2_11_8, A18), 460 461 PINMUX_IPSR_GPSR(IP2_15_12, DU_EXHSYNC_DU_HSYNC), 462 PINMUX_IPSR_GPSR(IP2_15_12, HRX0), 463 PINMUX_IPSR_GPSR(IP2_15_12, A19), 464 PINMUX_IPSR_GPSR(IP2_15_12, IRQ3), 465 466 PINMUX_IPSR_GPSR(IP2_19_16, DU_EXVSYNC_DU_VSYNC), 467 PINMUX_IPSR_GPSR(IP2_19_16, MSIOF3_SCK), 468 469 PINMUX_IPSR_GPSR(IP2_23_20, DU_EXODDF_DU_ODDF_DISP_CDE), 470 PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC), 471 472 PINMUX_IPSR_GPSR(IP2_27_24, IRQ0), 473 474 PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK), 475 PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK), 476 PINMUX_IPSR_GPSR(IP2_31_28, SCK3), 477 PINMUX_IPSR_GPSR(IP2_31_28, HSCK3), 478 479 /* IPSR3 */ 480 PINMUX_IPSR_GPSR(IP3_3_0, VI0_CLKENB), 481 PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_RXD), 482 PINMUX_IPSR_GPSR(IP3_3_0, RX3), 483 PINMUX_IPSR_GPSR(IP3_3_0, RD_WR_N), 484 PINMUX_IPSR_GPSR(IP3_3_0, HCTS3_N), 485 486 PINMUX_IPSR_GPSR(IP3_7_4, VI0_HSYNC_N), 487 PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD), 488 PINMUX_IPSR_GPSR(IP3_7_4, TX3), 489 PINMUX_IPSR_GPSR(IP3_7_4, HRTS3_N), 490 491 PINMUX_IPSR_GPSR(IP3_11_8, VI0_VSYNC_N), 492 PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_SYNC), 493 PINMUX_IPSR_GPSR(IP3_11_8, CTS3_N), 494 PINMUX_IPSR_GPSR(IP3_11_8, HTX3), 495 496 PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0), 497 PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1), 498 PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N), 499 PINMUX_IPSR_GPSR(IP3_15_12, HRX3), 500 501 PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1), 502 PINMUX_IPSR_GPSR(IP3_19_16, MSIOF2_SS2), 503 PINMUX_IPSR_GPSR(IP3_19_16, SCK1), 504 PINMUX_IPSR_MSEL(IP3_19_16, SPEEDIN_A, SEL_RSP_0), 505 506 PINMUX_IPSR_GPSR(IP3_23_20, VI0_DATA2), 507 PINMUX_IPSR_GPSR(IP3_23_20, AVB0_AVTP_PPS), 508 PINMUX_IPSR_MSEL(IP3_23_20, SDA3_A, SEL_I2C3_0), 509 510 PINMUX_IPSR_GPSR(IP3_27_24, VI0_DATA3), 511 PINMUX_IPSR_GPSR(IP3_27_24, HSCK1), 512 PINMUX_IPSR_MSEL(IP3_27_24, SCL3_A, SEL_I2C3_0), 513 514 PINMUX_IPSR_GPSR(IP3_31_28, VI0_DATA4), 515 PINMUX_IPSR_GPSR(IP3_31_28, HRTS1_N), 516 PINMUX_IPSR_MSEL(IP3_31_28, RX1_A, SEL_SCIF1_0), 517 518 /* IPSR4 */ 519 PINMUX_IPSR_GPSR(IP4_3_0, VI0_DATA5), 520 PINMUX_IPSR_GPSR(IP4_3_0, HCTS1_N), 521 PINMUX_IPSR_MSEL(IP4_3_0, TX1_A, SEL_SCIF1_0), 522 523 PINMUX_IPSR_GPSR(IP4_7_4, VI0_DATA6), 524 PINMUX_IPSR_GPSR(IP4_7_4, HTX1), 525 PINMUX_IPSR_GPSR(IP4_7_4, CTS1_N), 526 527 PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7), 528 PINMUX_IPSR_GPSR(IP4_11_8, HRX1), 529 PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N), 530 531 PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8), 532 PINMUX_IPSR_GPSR(IP4_15_12, HSCK2), 533 PINMUX_IPSR_MSEL(IP4_15_12, PWM0_A, SEL_PWM0_0), 534 535 PINMUX_IPSR_GPSR(IP4_19_16, VI0_DATA9), 536 PINMUX_IPSR_GPSR(IP4_19_16, HCTS2_N), 537 PINMUX_IPSR_MSEL(IP4_19_16, PWM1_A, SEL_PWM1_0), 538 PINMUX_IPSR_MSEL(IP4_19_16, FSO_CFE_0_N_B, SEL_RFSO_1), 539 540 PINMUX_IPSR_GPSR(IP4_23_20, VI0_DATA10), 541 PINMUX_IPSR_GPSR(IP4_23_20, HRTS2_N), 542 PINMUX_IPSR_MSEL(IP4_23_20, PWM2_A, SEL_PWM2_0), 543 PINMUX_IPSR_MSEL(IP4_23_20, FSO_CFE_1_N_B, SEL_RFSO_1), 544 545 PINMUX_IPSR_GPSR(IP4_27_24, VI0_DATA11), 546 PINMUX_IPSR_GPSR(IP4_27_24, HTX2), 547 PINMUX_IPSR_MSEL(IP4_27_24, PWM3_A, SEL_PWM3_0), 548 PINMUX_IPSR_MSEL(IP4_27_24, FSO_TOE_N_B, SEL_RFSO_1), 549 550 PINMUX_IPSR_GPSR(IP4_31_28, VI0_FIELD), 551 PINMUX_IPSR_GPSR(IP4_31_28, HRX2), 552 PINMUX_IPSR_MSEL(IP4_31_28, PWM4_A, SEL_PWM4_0), 553 PINMUX_IPSR_GPSR(IP4_31_28, CS1_N), 554 PINMUX_IPSR_GPSR(IP4_31_28, FSCLKST2_N_A), 555 556 /* IPSR5 */ 557 PINMUX_IPSR_GPSR(IP5_3_0, VI1_CLK), 558 PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD), 559 PINMUX_IPSR_GPSR(IP5_3_0, CS0_N), 560 561 PINMUX_IPSR_GPSR(IP5_7_4, VI1_CLKENB), 562 PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD), 563 PINMUX_IPSR_GPSR(IP5_7_4, D0), 564 565 PINMUX_IPSR_GPSR(IP5_11_8, VI1_HSYNC_N), 566 PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK), 567 PINMUX_IPSR_GPSR(IP5_11_8, D1), 568 569 PINMUX_IPSR_GPSR(IP5_15_12, VI1_VSYNC_N), 570 PINMUX_IPSR_GPSR(IP5_15_12, MSIOF1_SYNC), 571 PINMUX_IPSR_GPSR(IP5_15_12, D2), 572 573 PINMUX_IPSR_GPSR(IP5_19_16, VI1_DATA0), 574 PINMUX_IPSR_GPSR(IP5_19_16, MSIOF1_SS1), 575 PINMUX_IPSR_GPSR(IP5_19_16, D3), 576 577 PINMUX_IPSR_GPSR(IP5_23_20, VI1_DATA1), 578 PINMUX_IPSR_GPSR(IP5_23_20, MSIOF1_SS2), 579 PINMUX_IPSR_GPSR(IP5_23_20, D4), 580 PINMUX_IPSR_GPSR(IP5_23_20, MMC_CMD), 581 582 PINMUX_IPSR_GPSR(IP5_27_24, VI1_DATA2), 583 PINMUX_IPSR_MSEL(IP5_27_24, CANFD0_TX_B, SEL_CANFD0_1), 584 PINMUX_IPSR_GPSR(IP5_27_24, D5), 585 PINMUX_IPSR_GPSR(IP5_27_24, MMC_D0), 586 587 PINMUX_IPSR_GPSR(IP5_31_28, VI1_DATA3), 588 PINMUX_IPSR_MSEL(IP5_31_28, CANFD0_RX_B, SEL_CANFD0_1), 589 PINMUX_IPSR_GPSR(IP5_31_28, D6), 590 PINMUX_IPSR_GPSR(IP5_31_28, MMC_D1), 591 592 /* IPSR6 */ 593 PINMUX_IPSR_GPSR(IP6_3_0, VI1_DATA4), 594 PINMUX_IPSR_MSEL(IP6_3_0, CANFD_CLK_B, SEL_CANFD0_1), 595 PINMUX_IPSR_GPSR(IP6_3_0, D7), 596 PINMUX_IPSR_GPSR(IP6_3_0, MMC_D2), 597 598 PINMUX_IPSR_GPSR(IP6_7_4, VI1_DATA5), 599 PINMUX_IPSR_GPSR(IP6_7_4, SCK4), 600 PINMUX_IPSR_GPSR(IP6_7_4, D8), 601 PINMUX_IPSR_GPSR(IP6_7_4, MMC_D3), 602 603 PINMUX_IPSR_GPSR(IP6_11_8, VI1_DATA6), 604 PINMUX_IPSR_GPSR(IP6_11_8, RX4), 605 PINMUX_IPSR_GPSR(IP6_11_8, D9), 606 PINMUX_IPSR_GPSR(IP6_11_8, MMC_CLK), 607 608 PINMUX_IPSR_GPSR(IP6_15_12, VI1_DATA7), 609 PINMUX_IPSR_GPSR(IP6_15_12, TX4), 610 PINMUX_IPSR_GPSR(IP6_15_12, D10), 611 PINMUX_IPSR_GPSR(IP6_15_12, MMC_D4), 612 613 PINMUX_IPSR_GPSR(IP6_19_16, VI1_DATA8), 614 PINMUX_IPSR_GPSR(IP6_19_16, CTS4_N), 615 PINMUX_IPSR_GPSR(IP6_19_16, D11), 616 PINMUX_IPSR_GPSR(IP6_19_16, MMC_D5), 617 618 PINMUX_IPSR_GPSR(IP6_23_20, VI1_DATA9), 619 PINMUX_IPSR_GPSR(IP6_23_20, RTS4_N), 620 PINMUX_IPSR_GPSR(IP6_23_20, D12), 621 PINMUX_IPSR_GPSR(IP6_23_20, MMC_D6), 622 PINMUX_IPSR_MSEL(IP6_23_20, SCL3_B, SEL_I2C3_1), 623 624 PINMUX_IPSR_GPSR(IP6_27_24, VI1_DATA10), 625 PINMUX_IPSR_GPSR(IP6_27_24, D13), 626 PINMUX_IPSR_GPSR(IP6_27_24, MMC_D7), 627 PINMUX_IPSR_MSEL(IP6_27_24, SDA3_B, SEL_I2C3_1), 628 629 PINMUX_IPSR_GPSR(IP6_31_28, VI1_DATA11), 630 PINMUX_IPSR_GPSR(IP6_31_28, SCL4), 631 PINMUX_IPSR_GPSR(IP6_31_28, IRQ4), 632 PINMUX_IPSR_GPSR(IP6_31_28, D14), 633 634 /* IPSR7 */ 635 PINMUX_IPSR_GPSR(IP7_3_0, VI1_FIELD), 636 PINMUX_IPSR_GPSR(IP7_3_0, SDA4), 637 PINMUX_IPSR_GPSR(IP7_3_0, IRQ5), 638 PINMUX_IPSR_GPSR(IP7_3_0, D15), 639 640 PINMUX_IPSR_GPSR(IP7_7_4, SCL0), 641 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR0), 642 PINMUX_IPSR_GPSR(IP7_7_4, TPU0TO0), 643 PINMUX_IPSR_GPSR(IP7_7_4, CLKOUT), 644 PINMUX_IPSR_GPSR(IP7_7_4, MSIOF0_RXD), 645 646 PINMUX_IPSR_GPSR(IP7_11_8, SDA0), 647 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR1), 648 PINMUX_IPSR_GPSR(IP7_11_8, TPU0TO1), 649 PINMUX_IPSR_GPSR(IP7_11_8, BS_N), 650 PINMUX_IPSR_GPSR(IP7_11_8, SCK0), 651 PINMUX_IPSR_GPSR(IP7_11_8, MSIOF0_TXD), 652 653 PINMUX_IPSR_GPSR(IP7_15_12, SCL1), 654 PINMUX_IPSR_GPSR(IP7_15_12, DU_DG0), 655 PINMUX_IPSR_GPSR(IP7_15_12, TPU0TO2), 656 PINMUX_IPSR_GPSR(IP7_15_12, RD_N), 657 PINMUX_IPSR_GPSR(IP7_15_12, CTS0_N), 658 PINMUX_IPSR_GPSR(IP7_15_12, MSIOF0_SCK), 659 660 PINMUX_IPSR_GPSR(IP7_19_16, SDA1), 661 PINMUX_IPSR_GPSR(IP7_19_16, DU_DG1), 662 PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3), 663 PINMUX_IPSR_GPSR(IP7_19_16, WE0_N), 664 PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N), 665 PINMUX_IPSR_GPSR(IP7_19_16, MSIOF0_SYNC), 666 667 PINMUX_IPSR_GPSR(IP7_23_20, SCL2), 668 PINMUX_IPSR_GPSR(IP7_23_20, DU_DB0), 669 PINMUX_IPSR_MSEL(IP7_23_20, TCLK1_A, SEL_TMU_0), 670 PINMUX_IPSR_GPSR(IP7_23_20, WE1_N), 671 PINMUX_IPSR_GPSR(IP7_23_20, RX0), 672 PINMUX_IPSR_GPSR(IP7_23_20, MSIOF0_SS1), 673 674 PINMUX_IPSR_GPSR(IP7_27_24, SDA2), 675 PINMUX_IPSR_GPSR(IP7_27_24, DU_DB1), 676 PINMUX_IPSR_MSEL(IP7_27_24, TCLK2_A, SEL_TMU_0), 677 PINMUX_IPSR_GPSR(IP7_27_24, EX_WAIT0), 678 PINMUX_IPSR_GPSR(IP7_27_24, TX0), 679 PINMUX_IPSR_GPSR(IP7_27_24, MSIOF0_SS2), 680 681 PINMUX_IPSR_GPSR(IP7_31_28, AVB0_AVTP_CAPTURE), 682 PINMUX_IPSR_GPSR(IP7_31_28, FSCLKST2_N_B), 683 684 /* IPSR8 */ 685 PINMUX_IPSR_MSEL(IP8_3_0, CANFD0_TX_A, SEL_CANFD0_0), 686 PINMUX_IPSR_GPSR(IP8_3_0, FXR_TXDA), 687 PINMUX_IPSR_MSEL(IP8_3_0, PWM0_B, SEL_PWM0_1), 688 PINMUX_IPSR_GPSR(IP8_3_0, DU_DISP), 689 PINMUX_IPSR_GPSR(IP8_3_0, FSCLKST2_N_C), 690 691 PINMUX_IPSR_MSEL(IP8_7_4, CANFD0_RX_A, SEL_CANFD0_0), 692 PINMUX_IPSR_GPSR(IP8_7_4, RXDA_EXTFXR), 693 PINMUX_IPSR_MSEL(IP8_7_4, PWM1_B, SEL_PWM1_1), 694 PINMUX_IPSR_GPSR(IP8_7_4, DU_CDE), 695 696 PINMUX_IPSR_GPSR(IP8_11_8, CANFD1_TX), 697 PINMUX_IPSR_GPSR(IP8_11_8, FXR_TXDB), 698 PINMUX_IPSR_MSEL(IP8_11_8, PWM2_B, SEL_PWM2_1), 699 PINMUX_IPSR_MSEL(IP8_11_8, TCLK1_B, SEL_TMU_1), 700 PINMUX_IPSR_MSEL(IP8_11_8, TX1_B, SEL_SCIF1_1), 701 702 PINMUX_IPSR_GPSR(IP8_15_12, CANFD1_RX), 703 PINMUX_IPSR_GPSR(IP8_15_12, RXDB_EXTFXR), 704 PINMUX_IPSR_MSEL(IP8_15_12, PWM3_B, SEL_PWM3_1), 705 PINMUX_IPSR_MSEL(IP8_15_12, TCLK2_B, SEL_TMU_1), 706 PINMUX_IPSR_MSEL(IP8_15_12, RX1_B, SEL_SCIF1_1), 707 708 PINMUX_IPSR_MSEL(IP8_19_16, CANFD_CLK_A, SEL_CANFD0_0), 709 PINMUX_IPSR_GPSR(IP8_19_16, CLK_EXTFXR), 710 PINMUX_IPSR_MSEL(IP8_19_16, PWM4_B, SEL_PWM4_1), 711 PINMUX_IPSR_MSEL(IP8_19_16, SPEEDIN_B, SEL_RSP_1), 712 PINMUX_IPSR_MSEL(IP8_19_16, SCIF_CLK_B, SEL_HSCIF0_1), 713 714 PINMUX_IPSR_GPSR(IP8_23_20, DIGRF_CLKIN), 715 PINMUX_IPSR_GPSR(IP8_23_20, DIGRF_CLKEN_IN), 716 717 PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKOUT), 718 PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKEN_OUT), 719 }; 720 721 static const struct sh_pfc_pin pinmux_pins[] = { 722 PINMUX_GPIO_GP_ALL(), 723 }; 724 725 /* - AVB0 ------------------------------------------------------------------- */ 726 static const unsigned int avb0_link_pins[] = { 727 /* AVB0_LINK */ 728 RCAR_GP_PIN(1, 18), 729 }; 730 static const unsigned int avb0_link_mux[] = { 731 AVB0_LINK_MARK, 732 }; 733 static const unsigned int avb0_magic_pins[] = { 734 /* AVB0_MAGIC */ 735 RCAR_GP_PIN(1, 16), 736 }; 737 static const unsigned int avb0_magic_mux[] = { 738 AVB0_MAGIC_MARK, 739 }; 740 static const unsigned int avb0_phy_int_pins[] = { 741 /* AVB0_PHY_INT */ 742 RCAR_GP_PIN(1, 17), 743 }; 744 static const unsigned int avb0_phy_int_mux[] = { 745 AVB0_PHY_INT_MARK, 746 }; 747 static const unsigned int avb0_mdio_pins[] = { 748 /* AVB0_MDC, AVB0_MDIO */ 749 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), 750 }; 751 static const unsigned int avb0_mdio_mux[] = { 752 AVB0_MDC_MARK, AVB0_MDIO_MARK, 753 }; 754 static const unsigned int avb0_rgmii_pins[] = { 755 /* 756 * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3, 757 * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3 758 */ 759 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), 760 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10), 761 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12), 762 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2), 763 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4), 764 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), 765 }; 766 static const unsigned int avb0_rgmii_mux[] = { 767 AVB0_TX_CTL_MARK, AVB0_TXC_MARK, 768 AVB0_TD0_MARK, AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK, 769 AVB0_RX_CTL_MARK, AVB0_RXC_MARK, 770 AVB0_RD0_MARK, AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK, 771 }; 772 static const unsigned int avb0_txcrefclk_pins[] = { 773 /* AVB0_TXCREFCLK */ 774 RCAR_GP_PIN(1, 13), 775 }; 776 static const unsigned int avb0_txcrefclk_mux[] = { 777 AVB0_TXCREFCLK_MARK, 778 }; 779 static const unsigned int avb0_avtp_pps_pins[] = { 780 /* AVB0_AVTP_PPS */ 781 RCAR_GP_PIN(2, 6), 782 }; 783 static const unsigned int avb0_avtp_pps_mux[] = { 784 AVB0_AVTP_PPS_MARK, 785 }; 786 static const unsigned int avb0_avtp_capture_pins[] = { 787 /* AVB0_AVTP_CAPTURE */ 788 RCAR_GP_PIN(1, 20), 789 }; 790 static const unsigned int avb0_avtp_capture_mux[] = { 791 AVB0_AVTP_CAPTURE_MARK, 792 }; 793 static const unsigned int avb0_avtp_match_pins[] = { 794 /* AVB0_AVTP_MATCH */ 795 RCAR_GP_PIN(1, 19), 796 }; 797 static const unsigned int avb0_avtp_match_mux[] = { 798 AVB0_AVTP_MATCH_MARK, 799 }; 800 801 /* - CANFD Clock ------------------------------------------------------------ */ 802 static const unsigned int canfd_clk_a_pins[] = { 803 /* CANFD_CLK */ 804 RCAR_GP_PIN(1, 25), 805 }; 806 static const unsigned int canfd_clk_a_mux[] = { 807 CANFD_CLK_A_MARK, 808 }; 809 static const unsigned int canfd_clk_b_pins[] = { 810 /* CANFD_CLK */ 811 RCAR_GP_PIN(3, 8), 812 }; 813 static const unsigned int canfd_clk_b_mux[] = { 814 CANFD_CLK_B_MARK, 815 }; 816 817 /* - CANFD0 ----------------------------------------------------------------- */ 818 static const unsigned int canfd0_data_a_pins[] = { 819 /* TX, RX */ 820 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), 821 }; 822 static const unsigned int canfd0_data_a_mux[] = { 823 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK, 824 }; 825 static const unsigned int canfd0_data_b_pins[] = { 826 /* TX, RX */ 827 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 828 }; 829 static const unsigned int canfd0_data_b_mux[] = { 830 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK, 831 }; 832 833 /* - CANFD1 ----------------------------------------------------------------- */ 834 static const unsigned int canfd1_data_pins[] = { 835 /* TX, RX */ 836 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 837 }; 838 static const unsigned int canfd1_data_mux[] = { 839 CANFD1_TX_MARK, CANFD1_RX_MARK, 840 }; 841 842 /* - DU --------------------------------------------------------------------- */ 843 static const unsigned int du_rgb666_pins[] = { 844 /* R[7:2], G[7:2], B[7:2] */ 845 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), 846 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0), 847 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9), 848 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), 849 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15), 850 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12), 851 }; 852 static const unsigned int du_rgb666_mux[] = { 853 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, 854 DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK, 855 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, 856 DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK, 857 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, 858 DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK, 859 }; 860 static const unsigned int du_clk_out_pins[] = { 861 /* DOTCLKOUT */ 862 RCAR_GP_PIN(0, 18), 863 }; 864 static const unsigned int du_clk_out_mux[] = { 865 DU_DOTCLKOUT_MARK, 866 }; 867 static const unsigned int du_sync_pins[] = { 868 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ 869 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), 870 }; 871 static const unsigned int du_sync_mux[] = { 872 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK 873 }; 874 static const unsigned int du_oddf_pins[] = { 875 /* EXODDF/ODDF/DISP/CDE */ 876 RCAR_GP_PIN(0, 21), 877 }; 878 static const unsigned int du_oddf_mux[] = { 879 DU_EXODDF_DU_ODDF_DISP_CDE_MARK, 880 }; 881 static const unsigned int du_cde_pins[] = { 882 /* CDE */ 883 RCAR_GP_PIN(1, 22), 884 }; 885 static const unsigned int du_cde_mux[] = { 886 DU_CDE_MARK, 887 }; 888 static const unsigned int du_disp_pins[] = { 889 /* DISP */ 890 RCAR_GP_PIN(1, 21), 891 }; 892 static const unsigned int du_disp_mux[] = { 893 DU_DISP_MARK, 894 }; 895 896 /* - HSCIF0 ----------------------------------------------------------------- */ 897 static const unsigned int hscif0_data_pins[] = { 898 /* HRX, HTX */ 899 RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 3), 900 }; 901 static const unsigned int hscif0_data_mux[] = { 902 HRX0_MARK, HTX0_MARK, 903 }; 904 static const unsigned int hscif0_clk_pins[] = { 905 /* HSCK */ 906 RCAR_GP_PIN(0, 0), 907 }; 908 static const unsigned int hscif0_clk_mux[] = { 909 HSCK0_MARK, 910 }; 911 static const unsigned int hscif0_ctrl_pins[] = { 912 /* HRTS#, HCTS# */ 913 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2), 914 }; 915 static const unsigned int hscif0_ctrl_mux[] = { 916 HRTS0_N_MARK, HCTS0_N_MARK, 917 }; 918 919 /* - HSCIF1 ----------------------------------------------------------------- */ 920 static const unsigned int hscif1_data_pins[] = { 921 /* HRX, HTX */ 922 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10), 923 }; 924 static const unsigned int hscif1_data_mux[] = { 925 HRX1_MARK, HTX1_MARK, 926 }; 927 static const unsigned int hscif1_clk_pins[] = { 928 /* HSCK */ 929 RCAR_GP_PIN(2, 7), 930 }; 931 static const unsigned int hscif1_clk_mux[] = { 932 HSCK1_MARK, 933 }; 934 static const unsigned int hscif1_ctrl_pins[] = { 935 /* HRTS#, HCTS# */ 936 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 937 }; 938 static const unsigned int hscif1_ctrl_mux[] = { 939 HRTS1_N_MARK, HCTS1_N_MARK, 940 }; 941 942 /* - HSCIF2 ----------------------------------------------------------------- */ 943 static const unsigned int hscif2_data_pins[] = { 944 /* HRX, HTX */ 945 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15), 946 }; 947 static const unsigned int hscif2_data_mux[] = { 948 HRX2_MARK, HTX2_MARK, 949 }; 950 static const unsigned int hscif2_clk_pins[] = { 951 /* HSCK */ 952 RCAR_GP_PIN(2, 12), 953 }; 954 static const unsigned int hscif2_clk_mux[] = { 955 HSCK2_MARK, 956 }; 957 static const unsigned int hscif2_ctrl_pins[] = { 958 /* HRTS#, HCTS# */ 959 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), 960 }; 961 static const unsigned int hscif2_ctrl_mux[] = { 962 HRTS2_N_MARK, HCTS2_N_MARK, 963 }; 964 965 /* - HSCIF3 ----------------------------------------------------------------- */ 966 static const unsigned int hscif3_data_pins[] = { 967 /* HRX, HTX */ 968 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), 969 }; 970 static const unsigned int hscif3_data_mux[] = { 971 HRX3_MARK, HTX3_MARK, 972 }; 973 static const unsigned int hscif3_clk_pins[] = { 974 /* HSCK */ 975 RCAR_GP_PIN(2, 0), 976 }; 977 static const unsigned int hscif3_clk_mux[] = { 978 HSCK3_MARK, 979 }; 980 static const unsigned int hscif3_ctrl_pins[] = { 981 /* HRTS#, HCTS# */ 982 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1), 983 }; 984 static const unsigned int hscif3_ctrl_mux[] = { 985 HRTS3_N_MARK, HCTS3_N_MARK, 986 }; 987 988 /* - I2C0 ------------------------------------------------------------------- */ 989 static const unsigned int i2c0_pins[] = { 990 /* SDA, SCL */ 991 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0), 992 }; 993 static const unsigned int i2c0_mux[] = { 994 SDA0_MARK, SCL0_MARK, 995 }; 996 997 /* - I2C1 ------------------------------------------------------------------- */ 998 static const unsigned int i2c1_pins[] = { 999 /* SDA, SCL */ 1000 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2), 1001 }; 1002 static const unsigned int i2c1_mux[] = { 1003 SDA1_MARK, SCL1_MARK, 1004 }; 1005 1006 /* - I2C2 ------------------------------------------------------------------- */ 1007 static const unsigned int i2c2_pins[] = { 1008 /* SDA, SCL */ 1009 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4), 1010 }; 1011 static const unsigned int i2c2_mux[] = { 1012 SDA2_MARK, SCL2_MARK, 1013 }; 1014 1015 /* - I2C3 ------------------------------------------------------------------- */ 1016 static const unsigned int i2c3_a_pins[] = { 1017 /* SDA, SCL */ 1018 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 1019 }; 1020 static const unsigned int i2c3_a_mux[] = { 1021 SDA3_A_MARK, SCL3_A_MARK, 1022 }; 1023 static const unsigned int i2c3_b_pins[] = { 1024 /* SDA, SCL */ 1025 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13), 1026 }; 1027 static const unsigned int i2c3_b_mux[] = { 1028 SDA3_B_MARK, SCL3_B_MARK, 1029 }; 1030 1031 /* - I2C4 ------------------------------------------------------------------- */ 1032 static const unsigned int i2c4_pins[] = { 1033 /* SDA, SCL */ 1034 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15), 1035 }; 1036 static const unsigned int i2c4_mux[] = { 1037 SDA4_MARK, SCL4_MARK, 1038 }; 1039 1040 /* - INTC-EX ---------------------------------------------------------------- */ 1041 static const unsigned int intc_ex_irq0_pins[] = { 1042 /* IRQ0 */ 1043 RCAR_GP_PIN(1, 0), 1044 }; 1045 static const unsigned int intc_ex_irq0_mux[] = { 1046 IRQ0_MARK, 1047 }; 1048 static const unsigned int intc_ex_irq1_pins[] = { 1049 /* IRQ1 */ 1050 RCAR_GP_PIN(0, 11), 1051 }; 1052 static const unsigned int intc_ex_irq1_mux[] = { 1053 IRQ1_MARK, 1054 }; 1055 static const unsigned int intc_ex_irq2_pins[] = { 1056 /* IRQ2 */ 1057 RCAR_GP_PIN(0, 12), 1058 }; 1059 static const unsigned int intc_ex_irq2_mux[] = { 1060 IRQ2_MARK, 1061 }; 1062 static const unsigned int intc_ex_irq3_pins[] = { 1063 /* IRQ3 */ 1064 RCAR_GP_PIN(0, 19), 1065 }; 1066 static const unsigned int intc_ex_irq3_mux[] = { 1067 IRQ3_MARK, 1068 }; 1069 static const unsigned int intc_ex_irq4_pins[] = { 1070 /* IRQ4 */ 1071 RCAR_GP_PIN(3, 15), 1072 }; 1073 static const unsigned int intc_ex_irq4_mux[] = { 1074 IRQ4_MARK, 1075 }; 1076 static const unsigned int intc_ex_irq5_pins[] = { 1077 /* IRQ5 */ 1078 RCAR_GP_PIN(3, 16), 1079 }; 1080 static const unsigned int intc_ex_irq5_mux[] = { 1081 IRQ5_MARK, 1082 }; 1083 1084 /* - MMC -------------------------------------------------------------------- */ 1085 static const unsigned int mmc_data1_pins[] = { 1086 /* D0 */ 1087 RCAR_GP_PIN(3, 6), 1088 }; 1089 static const unsigned int mmc_data1_mux[] = { 1090 MMC_D0_MARK, 1091 }; 1092 static const unsigned int mmc_data4_pins[] = { 1093 /* D[0:3] */ 1094 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 1095 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 1096 }; 1097 static const unsigned int mmc_data4_mux[] = { 1098 MMC_D0_MARK, MMC_D1_MARK, 1099 MMC_D2_MARK, MMC_D3_MARK, 1100 }; 1101 static const unsigned int mmc_data8_pins[] = { 1102 /* D[0:7] */ 1103 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 1104 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 1105 RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), 1106 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), 1107 }; 1108 static const unsigned int mmc_data8_mux[] = { 1109 MMC_D0_MARK, MMC_D1_MARK, 1110 MMC_D2_MARK, MMC_D3_MARK, 1111 MMC_D4_MARK, MMC_D5_MARK, 1112 MMC_D6_MARK, MMC_D7_MARK, 1113 }; 1114 static const unsigned int mmc_ctrl_pins[] = { 1115 /* CLK, CMD */ 1116 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 5), 1117 }; 1118 static const unsigned int mmc_ctrl_mux[] = { 1119 MMC_CLK_MARK, MMC_CMD_MARK, 1120 }; 1121 1122 /* - MSIOF0 ----------------------------------------------------------------- */ 1123 static const unsigned int msiof0_clk_pins[] = { 1124 /* SCK */ 1125 RCAR_GP_PIN(4, 2), 1126 }; 1127 static const unsigned int msiof0_clk_mux[] = { 1128 MSIOF0_SCK_MARK, 1129 }; 1130 static const unsigned int msiof0_sync_pins[] = { 1131 /* SYNC */ 1132 RCAR_GP_PIN(4, 3), 1133 }; 1134 static const unsigned int msiof0_sync_mux[] = { 1135 MSIOF0_SYNC_MARK, 1136 }; 1137 static const unsigned int msiof0_ss1_pins[] = { 1138 /* SS1 */ 1139 RCAR_GP_PIN(4, 4), 1140 }; 1141 static const unsigned int msiof0_ss1_mux[] = { 1142 MSIOF0_SS1_MARK, 1143 }; 1144 static const unsigned int msiof0_ss2_pins[] = { 1145 /* SS2 */ 1146 RCAR_GP_PIN(4, 5), 1147 }; 1148 static const unsigned int msiof0_ss2_mux[] = { 1149 MSIOF0_SS2_MARK, 1150 }; 1151 static const unsigned int msiof0_txd_pins[] = { 1152 /* TXD */ 1153 RCAR_GP_PIN(4, 1), 1154 }; 1155 static const unsigned int msiof0_txd_mux[] = { 1156 MSIOF0_TXD_MARK, 1157 }; 1158 static const unsigned int msiof0_rxd_pins[] = { 1159 /* RXD */ 1160 RCAR_GP_PIN(4, 0), 1161 }; 1162 static const unsigned int msiof0_rxd_mux[] = { 1163 MSIOF0_RXD_MARK, 1164 }; 1165 1166 /* - MSIOF1 ----------------------------------------------------------------- */ 1167 static const unsigned int msiof1_clk_pins[] = { 1168 /* SCK */ 1169 RCAR_GP_PIN(3, 2), 1170 }; 1171 static const unsigned int msiof1_clk_mux[] = { 1172 MSIOF1_SCK_MARK, 1173 }; 1174 static const unsigned int msiof1_sync_pins[] = { 1175 /* SYNC */ 1176 RCAR_GP_PIN(3, 3), 1177 }; 1178 static const unsigned int msiof1_sync_mux[] = { 1179 MSIOF1_SYNC_MARK, 1180 }; 1181 static const unsigned int msiof1_ss1_pins[] = { 1182 /* SS1 */ 1183 RCAR_GP_PIN(3, 4), 1184 }; 1185 static const unsigned int msiof1_ss1_mux[] = { 1186 MSIOF1_SS1_MARK, 1187 }; 1188 static const unsigned int msiof1_ss2_pins[] = { 1189 /* SS2 */ 1190 RCAR_GP_PIN(3, 5), 1191 }; 1192 static const unsigned int msiof1_ss2_mux[] = { 1193 MSIOF1_SS2_MARK, 1194 }; 1195 static const unsigned int msiof1_txd_pins[] = { 1196 /* TXD */ 1197 RCAR_GP_PIN(3, 1), 1198 }; 1199 static const unsigned int msiof1_txd_mux[] = { 1200 MSIOF1_TXD_MARK, 1201 }; 1202 static const unsigned int msiof1_rxd_pins[] = { 1203 /* RXD */ 1204 RCAR_GP_PIN(3, 0), 1205 }; 1206 static const unsigned int msiof1_rxd_mux[] = { 1207 MSIOF1_RXD_MARK, 1208 }; 1209 1210 /* - MSIOF2 ----------------------------------------------------------------- */ 1211 static const unsigned int msiof2_clk_pins[] = { 1212 /* SCK */ 1213 RCAR_GP_PIN(2, 0), 1214 }; 1215 static const unsigned int msiof2_clk_mux[] = { 1216 MSIOF2_SCK_MARK, 1217 }; 1218 static const unsigned int msiof2_sync_pins[] = { 1219 /* SYNC */ 1220 RCAR_GP_PIN(2, 3), 1221 }; 1222 static const unsigned int msiof2_sync_mux[] = { 1223 MSIOF2_SYNC_MARK, 1224 }; 1225 static const unsigned int msiof2_ss1_pins[] = { 1226 /* SS1 */ 1227 RCAR_GP_PIN(2, 4), 1228 }; 1229 static const unsigned int msiof2_ss1_mux[] = { 1230 MSIOF2_SS1_MARK, 1231 }; 1232 static const unsigned int msiof2_ss2_pins[] = { 1233 /* SS2 */ 1234 RCAR_GP_PIN(2, 5), 1235 }; 1236 static const unsigned int msiof2_ss2_mux[] = { 1237 MSIOF2_SS2_MARK, 1238 }; 1239 static const unsigned int msiof2_txd_pins[] = { 1240 /* TXD */ 1241 RCAR_GP_PIN(2, 2), 1242 }; 1243 static const unsigned int msiof2_txd_mux[] = { 1244 MSIOF2_TXD_MARK, 1245 }; 1246 static const unsigned int msiof2_rxd_pins[] = { 1247 /* RXD */ 1248 RCAR_GP_PIN(2, 1), 1249 }; 1250 static const unsigned int msiof2_rxd_mux[] = { 1251 MSIOF2_RXD_MARK, 1252 }; 1253 1254 /* - MSIOF3 ----------------------------------------------------------------- */ 1255 static const unsigned int msiof3_clk_pins[] = { 1256 /* SCK */ 1257 RCAR_GP_PIN(0, 20), 1258 }; 1259 static const unsigned int msiof3_clk_mux[] = { 1260 MSIOF3_SCK_MARK, 1261 }; 1262 static const unsigned int msiof3_sync_pins[] = { 1263 /* SYNC */ 1264 RCAR_GP_PIN(0, 21), 1265 }; 1266 static const unsigned int msiof3_sync_mux[] = { 1267 MSIOF3_SYNC_MARK, 1268 }; 1269 static const unsigned int msiof3_ss1_pins[] = { 1270 /* SS1 */ 1271 RCAR_GP_PIN(0, 6), 1272 }; 1273 static const unsigned int msiof3_ss1_mux[] = { 1274 MSIOF3_SS1_MARK, 1275 }; 1276 static const unsigned int msiof3_ss2_pins[] = { 1277 /* SS2 */ 1278 RCAR_GP_PIN(0, 7), 1279 }; 1280 static const unsigned int msiof3_ss2_mux[] = { 1281 MSIOF3_SS2_MARK, 1282 }; 1283 static const unsigned int msiof3_txd_pins[] = { 1284 /* TXD */ 1285 RCAR_GP_PIN(0, 5), 1286 }; 1287 static const unsigned int msiof3_txd_mux[] = { 1288 MSIOF3_TXD_MARK, 1289 }; 1290 static const unsigned int msiof3_rxd_pins[] = { 1291 /* RXD */ 1292 RCAR_GP_PIN(0, 4), 1293 }; 1294 static const unsigned int msiof3_rxd_mux[] = { 1295 MSIOF3_RXD_MARK, 1296 }; 1297 1298 /* - PWM0 ------------------------------------------------------------------- */ 1299 static const unsigned int pwm0_a_pins[] = { 1300 RCAR_GP_PIN(2, 12), 1301 }; 1302 static const unsigned int pwm0_a_mux[] = { 1303 PWM0_A_MARK, 1304 }; 1305 static const unsigned int pwm0_b_pins[] = { 1306 RCAR_GP_PIN(1, 21), 1307 }; 1308 static const unsigned int pwm0_b_mux[] = { 1309 PWM0_B_MARK, 1310 }; 1311 1312 /* - PWM1 ------------------------------------------------------------------- */ 1313 static const unsigned int pwm1_a_pins[] = { 1314 RCAR_GP_PIN(2, 13), 1315 }; 1316 static const unsigned int pwm1_a_mux[] = { 1317 PWM1_A_MARK, 1318 }; 1319 static const unsigned int pwm1_b_pins[] = { 1320 RCAR_GP_PIN(1, 22), 1321 }; 1322 static const unsigned int pwm1_b_mux[] = { 1323 PWM1_B_MARK, 1324 }; 1325 1326 /* - PWM2 ------------------------------------------------------------------- */ 1327 static const unsigned int pwm2_a_pins[] = { 1328 RCAR_GP_PIN(2, 14), 1329 }; 1330 static const unsigned int pwm2_a_mux[] = { 1331 PWM2_A_MARK, 1332 }; 1333 static const unsigned int pwm2_b_pins[] = { 1334 RCAR_GP_PIN(1, 23), 1335 }; 1336 static const unsigned int pwm2_b_mux[] = { 1337 PWM2_B_MARK, 1338 }; 1339 1340 /* - PWM3 ------------------------------------------------------------------- */ 1341 static const unsigned int pwm3_a_pins[] = { 1342 RCAR_GP_PIN(2, 15), 1343 }; 1344 static const unsigned int pwm3_a_mux[] = { 1345 PWM3_A_MARK, 1346 }; 1347 static const unsigned int pwm3_b_pins[] = { 1348 RCAR_GP_PIN(1, 24), 1349 }; 1350 static const unsigned int pwm3_b_mux[] = { 1351 PWM3_B_MARK, 1352 }; 1353 1354 /* - PWM4 ------------------------------------------------------------------- */ 1355 static const unsigned int pwm4_a_pins[] = { 1356 RCAR_GP_PIN(2, 16), 1357 }; 1358 static const unsigned int pwm4_a_mux[] = { 1359 PWM4_A_MARK, 1360 }; 1361 static const unsigned int pwm4_b_pins[] = { 1362 RCAR_GP_PIN(1, 25), 1363 }; 1364 static const unsigned int pwm4_b_mux[] = { 1365 PWM4_B_MARK, 1366 }; 1367 1368 /* - QSPI0 ------------------------------------------------------------------ */ 1369 static const unsigned int qspi0_ctrl_pins[] = { 1370 /* SPCLK, SSL */ 1371 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 5), 1372 }; 1373 static const unsigned int qspi0_ctrl_mux[] = { 1374 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, 1375 }; 1376 static const unsigned int qspi0_data2_pins[] = { 1377 /* MOSI_IO0, MISO_IO1 */ 1378 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 1379 }; 1380 static const unsigned int qspi0_data2_mux[] = { 1381 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, 1382 }; 1383 static const unsigned int qspi0_data4_pins[] = { 1384 /* MOSI_IO0, MISO_IO1, IO2, IO3 */ 1385 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 1386 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), 1387 }; 1388 static const unsigned int qspi0_data4_mux[] = { 1389 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, 1390 QSPI0_IO2_MARK, QSPI0_IO3_MARK 1391 }; 1392 1393 /* - QSPI1 ------------------------------------------------------------------ */ 1394 static const unsigned int qspi1_ctrl_pins[] = { 1395 /* SPCLK, SSL */ 1396 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 11), 1397 }; 1398 static const unsigned int qspi1_ctrl_mux[] = { 1399 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, 1400 }; 1401 static const unsigned int qspi1_data2_pins[] = { 1402 /* MOSI_IO0, MISO_IO1 */ 1403 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), 1404 }; 1405 static const unsigned int qspi1_data2_mux[] = { 1406 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, 1407 }; 1408 static const unsigned int qspi1_data4_pins[] = { 1409 /* MOSI_IO0, MISO_IO1, IO2, IO3 */ 1410 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), 1411 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), 1412 }; 1413 static const unsigned int qspi1_data4_mux[] = { 1414 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, 1415 QSPI1_IO2_MARK, QSPI1_IO3_MARK 1416 }; 1417 1418 /* - RPC -------------------------------------------------------------------- */ 1419 static const unsigned int rpc_clk1_pins[] = { 1420 /* Octal-SPI flash: C/SCLK */ 1421 RCAR_GP_PIN(5, 0), 1422 }; 1423 static const unsigned int rpc_clk1_mux[] = { 1424 QSPI0_SPCLK_MARK, 1425 }; 1426 static const unsigned int rpc_clk2_pins[] = { 1427 /* HyperFlash: CK, CK# */ 1428 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6), 1429 }; 1430 static const unsigned int rpc_clk2_mux[] = { 1431 QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK, 1432 }; 1433 static const unsigned int rpc_ctrl_pins[] = { 1434 /* Octal-SPI flash: S#/CS, DQS */ 1435 /* HyperFlash: CS#, RDS */ 1436 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11), 1437 }; 1438 static const unsigned int rpc_ctrl_mux[] = { 1439 QSPI0_SSL_MARK, QSPI1_SSL_MARK, 1440 }; 1441 static const unsigned int rpc_data_pins[] = { 1442 /* DQ[0:7] */ 1443 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 1444 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), 1445 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), 1446 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), 1447 }; 1448 static const unsigned int rpc_data_mux[] = { 1449 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, 1450 QSPI0_IO2_MARK, QSPI0_IO3_MARK, 1451 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, 1452 QSPI1_IO2_MARK, QSPI1_IO3_MARK, 1453 }; 1454 static const unsigned int rpc_reset_pins[] = { 1455 /* RPC_RESET# */ 1456 RCAR_GP_PIN(5, 12), 1457 }; 1458 static const unsigned int rpc_reset_mux[] = { 1459 RPC_RESET_N_MARK, 1460 }; 1461 static const unsigned int rpc_int_pins[] = { 1462 /* RPC_INT# */ 1463 RCAR_GP_PIN(5, 14), 1464 }; 1465 static const unsigned int rpc_int_mux[] = { 1466 RPC_INT_N_MARK, 1467 }; 1468 static const unsigned int rpc_wp_pins[] = { 1469 /* RPC_WP# */ 1470 RCAR_GP_PIN(5, 13), 1471 }; 1472 static const unsigned int rpc_wp_mux[] = { 1473 RPC_WP_N_MARK, 1474 }; 1475 1476 /* - SCIF Clock ------------------------------------------------------------- */ 1477 static const unsigned int scif_clk_a_pins[] = { 1478 /* SCIF_CLK */ 1479 RCAR_GP_PIN(0, 18), 1480 }; 1481 static const unsigned int scif_clk_a_mux[] = { 1482 SCIF_CLK_A_MARK, 1483 }; 1484 static const unsigned int scif_clk_b_pins[] = { 1485 /* SCIF_CLK */ 1486 RCAR_GP_PIN(1, 25), 1487 }; 1488 static const unsigned int scif_clk_b_mux[] = { 1489 SCIF_CLK_B_MARK, 1490 }; 1491 1492 /* - SCIF0 ------------------------------------------------------------------ */ 1493 static const unsigned int scif0_data_pins[] = { 1494 /* RX, TX */ 1495 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), 1496 }; 1497 static const unsigned int scif0_data_mux[] = { 1498 RX0_MARK, TX0_MARK, 1499 }; 1500 static const unsigned int scif0_clk_pins[] = { 1501 /* SCK */ 1502 RCAR_GP_PIN(4, 1), 1503 }; 1504 static const unsigned int scif0_clk_mux[] = { 1505 SCK0_MARK, 1506 }; 1507 static const unsigned int scif0_ctrl_pins[] = { 1508 /* RTS#, CTS# */ 1509 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2), 1510 }; 1511 static const unsigned int scif0_ctrl_mux[] = { 1512 RTS0_N_MARK, CTS0_N_MARK, 1513 }; 1514 1515 /* - SCIF1 ------------------------------------------------------------------ */ 1516 static const unsigned int scif1_data_a_pins[] = { 1517 /* RX, TX */ 1518 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 1519 }; 1520 static const unsigned int scif1_data_a_mux[] = { 1521 RX1_A_MARK, TX1_A_MARK, 1522 }; 1523 static const unsigned int scif1_clk_pins[] = { 1524 /* SCK */ 1525 RCAR_GP_PIN(2, 5), 1526 }; 1527 static const unsigned int scif1_clk_mux[] = { 1528 SCK1_MARK, 1529 }; 1530 static const unsigned int scif1_ctrl_pins[] = { 1531 /* RTS#, CTS# */ 1532 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10), 1533 }; 1534 static const unsigned int scif1_ctrl_mux[] = { 1535 RTS1_N_MARK, CTS1_N_MARK, 1536 }; 1537 static const unsigned int scif1_data_b_pins[] = { 1538 /* RX, TX */ 1539 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23), 1540 }; 1541 static const unsigned int scif1_data_b_mux[] = { 1542 RX1_B_MARK, TX1_B_MARK, 1543 }; 1544 1545 /* - SCIF3 ------------------------------------------------------------------ */ 1546 static const unsigned int scif3_data_pins[] = { 1547 /* RX, TX */ 1548 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), 1549 }; 1550 static const unsigned int scif3_data_mux[] = { 1551 RX3_MARK, TX3_MARK, 1552 }; 1553 static const unsigned int scif3_clk_pins[] = { 1554 /* SCK */ 1555 RCAR_GP_PIN(2, 0), 1556 }; 1557 static const unsigned int scif3_clk_mux[] = { 1558 SCK3_MARK, 1559 }; 1560 static const unsigned int scif3_ctrl_pins[] = { 1561 /* RTS#, CTS# */ 1562 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), 1563 }; 1564 static const unsigned int scif3_ctrl_mux[] = { 1565 RTS3_N_MARK, CTS3_N_MARK, 1566 }; 1567 1568 /* - SCIF4 ------------------------------------------------------------------ */ 1569 static const unsigned int scif4_data_pins[] = { 1570 /* RX, TX */ 1571 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 1572 }; 1573 static const unsigned int scif4_data_mux[] = { 1574 RX4_MARK, TX4_MARK, 1575 }; 1576 static const unsigned int scif4_clk_pins[] = { 1577 /* SCK */ 1578 RCAR_GP_PIN(3, 9), 1579 }; 1580 static const unsigned int scif4_clk_mux[] = { 1581 SCK4_MARK, 1582 }; 1583 static const unsigned int scif4_ctrl_pins[] = { 1584 /* RTS#, CTS# */ 1585 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), 1586 }; 1587 static const unsigned int scif4_ctrl_mux[] = { 1588 RTS4_N_MARK, CTS4_N_MARK, 1589 }; 1590 1591 /* - TMU -------------------------------------------------------------------- */ 1592 static const unsigned int tmu_tclk1_a_pins[] = { 1593 /* TCLK1 */ 1594 RCAR_GP_PIN(4, 4), 1595 }; 1596 static const unsigned int tmu_tclk1_a_mux[] = { 1597 TCLK1_A_MARK, 1598 }; 1599 static const unsigned int tmu_tclk1_b_pins[] = { 1600 /* TCLK1 */ 1601 RCAR_GP_PIN(1, 23), 1602 }; 1603 static const unsigned int tmu_tclk1_b_mux[] = { 1604 TCLK1_B_MARK, 1605 }; 1606 static const unsigned int tmu_tclk2_a_pins[] = { 1607 /* TCLK2 */ 1608 RCAR_GP_PIN(4, 5), 1609 }; 1610 static const unsigned int tmu_tclk2_a_mux[] = { 1611 TCLK2_A_MARK, 1612 }; 1613 static const unsigned int tmu_tclk2_b_pins[] = { 1614 /* TCLK2 */ 1615 RCAR_GP_PIN(1, 24), 1616 }; 1617 static const unsigned int tmu_tclk2_b_mux[] = { 1618 TCLK2_B_MARK, 1619 }; 1620 1621 /* - VIN0 ------------------------------------------------------------------- */ 1622 static const union vin_data12 vin0_data_pins = { 1623 .data12 = { 1624 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 1625 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 1626 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 1627 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), 1628 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), 1629 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), 1630 }, 1631 }; 1632 static const union vin_data12 vin0_data_mux = { 1633 .data12 = { 1634 VI0_DATA0_MARK, VI0_DATA1_MARK, 1635 VI0_DATA2_MARK, VI0_DATA3_MARK, 1636 VI0_DATA4_MARK, VI0_DATA5_MARK, 1637 VI0_DATA6_MARK, VI0_DATA7_MARK, 1638 VI0_DATA8_MARK, VI0_DATA9_MARK, 1639 VI0_DATA10_MARK, VI0_DATA11_MARK, 1640 }, 1641 }; 1642 static const unsigned int vin0_sync_pins[] = { 1643 /* HSYNC#, VSYNC# */ 1644 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), 1645 }; 1646 static const unsigned int vin0_sync_mux[] = { 1647 VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK, 1648 }; 1649 static const unsigned int vin0_field_pins[] = { 1650 /* FIELD */ 1651 RCAR_GP_PIN(2, 16), 1652 }; 1653 static const unsigned int vin0_field_mux[] = { 1654 VI0_FIELD_MARK, 1655 }; 1656 static const unsigned int vin0_clkenb_pins[] = { 1657 /* CLKENB */ 1658 RCAR_GP_PIN(2, 1), 1659 }; 1660 static const unsigned int vin0_clkenb_mux[] = { 1661 VI0_CLKENB_MARK, 1662 }; 1663 static const unsigned int vin0_clk_pins[] = { 1664 /* CLK */ 1665 RCAR_GP_PIN(2, 0), 1666 }; 1667 static const unsigned int vin0_clk_mux[] = { 1668 VI0_CLK_MARK, 1669 }; 1670 1671 /* - VIN1 ------------------------------------------------------------------- */ 1672 static const union vin_data12 vin1_data_pins = { 1673 .data12 = { 1674 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), 1675 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 1676 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 1677 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 1678 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), 1679 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), 1680 }, 1681 }; 1682 static const union vin_data12 vin1_data_mux = { 1683 .data12 = { 1684 VI1_DATA0_MARK, VI1_DATA1_MARK, 1685 VI1_DATA2_MARK, VI1_DATA3_MARK, 1686 VI1_DATA4_MARK, VI1_DATA5_MARK, 1687 VI1_DATA6_MARK, VI1_DATA7_MARK, 1688 VI1_DATA8_MARK, VI1_DATA9_MARK, 1689 VI1_DATA10_MARK, VI1_DATA11_MARK, 1690 }, 1691 }; 1692 static const unsigned int vin1_sync_pins[] = { 1693 /* HSYNC#, VSYNC# */ 1694 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), 1695 }; 1696 static const unsigned int vin1_sync_mux[] = { 1697 VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK, 1698 }; 1699 static const unsigned int vin1_field_pins[] = { 1700 RCAR_GP_PIN(3, 16), 1701 }; 1702 static const unsigned int vin1_field_mux[] = { 1703 /* FIELD */ 1704 VI1_FIELD_MARK, 1705 }; 1706 static const unsigned int vin1_clkenb_pins[] = { 1707 RCAR_GP_PIN(3, 1), 1708 }; 1709 static const unsigned int vin1_clkenb_mux[] = { 1710 /* CLKENB */ 1711 VI1_CLKENB_MARK, 1712 }; 1713 static const unsigned int vin1_clk_pins[] = { 1714 RCAR_GP_PIN(3, 0), 1715 }; 1716 static const unsigned int vin1_clk_mux[] = { 1717 /* CLK */ 1718 VI1_CLK_MARK, 1719 }; 1720 1721 static const struct sh_pfc_pin_group pinmux_groups[] = { 1722 SH_PFC_PIN_GROUP(avb0_link), 1723 SH_PFC_PIN_GROUP(avb0_magic), 1724 SH_PFC_PIN_GROUP(avb0_phy_int), 1725 SH_PFC_PIN_GROUP(avb0_mdio), 1726 SH_PFC_PIN_GROUP(avb0_rgmii), 1727 SH_PFC_PIN_GROUP(avb0_txcrefclk), 1728 SH_PFC_PIN_GROUP(avb0_avtp_pps), 1729 SH_PFC_PIN_GROUP(avb0_avtp_capture), 1730 SH_PFC_PIN_GROUP(avb0_avtp_match), 1731 SH_PFC_PIN_GROUP(canfd_clk_a), 1732 SH_PFC_PIN_GROUP(canfd_clk_b), 1733 SH_PFC_PIN_GROUP(canfd0_data_a), 1734 SH_PFC_PIN_GROUP(canfd0_data_b), 1735 SH_PFC_PIN_GROUP(canfd1_data), 1736 SH_PFC_PIN_GROUP(du_rgb666), 1737 SH_PFC_PIN_GROUP(du_clk_out), 1738 SH_PFC_PIN_GROUP(du_sync), 1739 SH_PFC_PIN_GROUP(du_oddf), 1740 SH_PFC_PIN_GROUP(du_cde), 1741 SH_PFC_PIN_GROUP(du_disp), 1742 SH_PFC_PIN_GROUP(hscif0_data), 1743 SH_PFC_PIN_GROUP(hscif0_clk), 1744 SH_PFC_PIN_GROUP(hscif0_ctrl), 1745 SH_PFC_PIN_GROUP(hscif1_data), 1746 SH_PFC_PIN_GROUP(hscif1_clk), 1747 SH_PFC_PIN_GROUP(hscif1_ctrl), 1748 SH_PFC_PIN_GROUP(hscif2_data), 1749 SH_PFC_PIN_GROUP(hscif2_clk), 1750 SH_PFC_PIN_GROUP(hscif2_ctrl), 1751 SH_PFC_PIN_GROUP(hscif3_data), 1752 SH_PFC_PIN_GROUP(hscif3_clk), 1753 SH_PFC_PIN_GROUP(hscif3_ctrl), 1754 SH_PFC_PIN_GROUP(i2c0), 1755 SH_PFC_PIN_GROUP(i2c1), 1756 SH_PFC_PIN_GROUP(i2c2), 1757 SH_PFC_PIN_GROUP(i2c3_a), 1758 SH_PFC_PIN_GROUP(i2c3_b), 1759 SH_PFC_PIN_GROUP(i2c4), 1760 SH_PFC_PIN_GROUP(intc_ex_irq0), 1761 SH_PFC_PIN_GROUP(intc_ex_irq1), 1762 SH_PFC_PIN_GROUP(intc_ex_irq2), 1763 SH_PFC_PIN_GROUP(intc_ex_irq3), 1764 SH_PFC_PIN_GROUP(intc_ex_irq4), 1765 SH_PFC_PIN_GROUP(intc_ex_irq5), 1766 SH_PFC_PIN_GROUP(mmc_data1), 1767 SH_PFC_PIN_GROUP(mmc_data4), 1768 SH_PFC_PIN_GROUP(mmc_data8), 1769 SH_PFC_PIN_GROUP(mmc_ctrl), 1770 SH_PFC_PIN_GROUP(msiof0_clk), 1771 SH_PFC_PIN_GROUP(msiof0_sync), 1772 SH_PFC_PIN_GROUP(msiof0_ss1), 1773 SH_PFC_PIN_GROUP(msiof0_ss2), 1774 SH_PFC_PIN_GROUP(msiof0_txd), 1775 SH_PFC_PIN_GROUP(msiof0_rxd), 1776 SH_PFC_PIN_GROUP(msiof1_clk), 1777 SH_PFC_PIN_GROUP(msiof1_sync), 1778 SH_PFC_PIN_GROUP(msiof1_ss1), 1779 SH_PFC_PIN_GROUP(msiof1_ss2), 1780 SH_PFC_PIN_GROUP(msiof1_txd), 1781 SH_PFC_PIN_GROUP(msiof1_rxd), 1782 SH_PFC_PIN_GROUP(msiof2_clk), 1783 SH_PFC_PIN_GROUP(msiof2_sync), 1784 SH_PFC_PIN_GROUP(msiof2_ss1), 1785 SH_PFC_PIN_GROUP(msiof2_ss2), 1786 SH_PFC_PIN_GROUP(msiof2_txd), 1787 SH_PFC_PIN_GROUP(msiof2_rxd), 1788 SH_PFC_PIN_GROUP(msiof3_clk), 1789 SH_PFC_PIN_GROUP(msiof3_sync), 1790 SH_PFC_PIN_GROUP(msiof3_ss1), 1791 SH_PFC_PIN_GROUP(msiof3_ss2), 1792 SH_PFC_PIN_GROUP(msiof3_txd), 1793 SH_PFC_PIN_GROUP(msiof3_rxd), 1794 SH_PFC_PIN_GROUP(pwm0_a), 1795 SH_PFC_PIN_GROUP(pwm0_b), 1796 SH_PFC_PIN_GROUP(pwm1_a), 1797 SH_PFC_PIN_GROUP(pwm1_b), 1798 SH_PFC_PIN_GROUP(pwm2_a), 1799 SH_PFC_PIN_GROUP(pwm2_b), 1800 SH_PFC_PIN_GROUP(pwm3_a), 1801 SH_PFC_PIN_GROUP(pwm3_b), 1802 SH_PFC_PIN_GROUP(pwm4_a), 1803 SH_PFC_PIN_GROUP(pwm4_b), 1804 SH_PFC_PIN_GROUP(qspi0_ctrl), 1805 SH_PFC_PIN_GROUP(qspi0_data2), 1806 SH_PFC_PIN_GROUP(qspi0_data4), 1807 SH_PFC_PIN_GROUP(qspi1_ctrl), 1808 SH_PFC_PIN_GROUP(qspi1_data2), 1809 SH_PFC_PIN_GROUP(qspi1_data4), 1810 SH_PFC_PIN_GROUP(rpc_clk1), 1811 SH_PFC_PIN_GROUP(rpc_clk2), 1812 SH_PFC_PIN_GROUP(rpc_ctrl), 1813 SH_PFC_PIN_GROUP(rpc_data), 1814 SH_PFC_PIN_GROUP(rpc_reset), 1815 SH_PFC_PIN_GROUP(rpc_int), 1816 SH_PFC_PIN_GROUP(rpc_wp), 1817 SH_PFC_PIN_GROUP(scif_clk_a), 1818 SH_PFC_PIN_GROUP(scif_clk_b), 1819 SH_PFC_PIN_GROUP(scif0_data), 1820 SH_PFC_PIN_GROUP(scif0_clk), 1821 SH_PFC_PIN_GROUP(scif0_ctrl), 1822 SH_PFC_PIN_GROUP(scif1_data_a), 1823 SH_PFC_PIN_GROUP(scif1_clk), 1824 SH_PFC_PIN_GROUP(scif1_ctrl), 1825 SH_PFC_PIN_GROUP(scif1_data_b), 1826 SH_PFC_PIN_GROUP(scif3_data), 1827 SH_PFC_PIN_GROUP(scif3_clk), 1828 SH_PFC_PIN_GROUP(scif3_ctrl), 1829 SH_PFC_PIN_GROUP(scif4_data), 1830 SH_PFC_PIN_GROUP(scif4_clk), 1831 SH_PFC_PIN_GROUP(scif4_ctrl), 1832 SH_PFC_PIN_GROUP(tmu_tclk1_a), 1833 SH_PFC_PIN_GROUP(tmu_tclk1_b), 1834 SH_PFC_PIN_GROUP(tmu_tclk2_a), 1835 SH_PFC_PIN_GROUP(tmu_tclk2_b), 1836 VIN_DATA_PIN_GROUP(vin0_data, 8), 1837 VIN_DATA_PIN_GROUP(vin0_data, 10), 1838 VIN_DATA_PIN_GROUP(vin0_data, 12), 1839 SH_PFC_PIN_GROUP(vin0_sync), 1840 SH_PFC_PIN_GROUP(vin0_field), 1841 SH_PFC_PIN_GROUP(vin0_clkenb), 1842 SH_PFC_PIN_GROUP(vin0_clk), 1843 VIN_DATA_PIN_GROUP(vin1_data, 8), 1844 VIN_DATA_PIN_GROUP(vin1_data, 10), 1845 VIN_DATA_PIN_GROUP(vin1_data, 12), 1846 SH_PFC_PIN_GROUP(vin1_sync), 1847 SH_PFC_PIN_GROUP(vin1_field), 1848 SH_PFC_PIN_GROUP(vin1_clkenb), 1849 SH_PFC_PIN_GROUP(vin1_clk), 1850 }; 1851 1852 static const char * const avb0_groups[] = { 1853 "avb0_link", 1854 "avb0_magic", 1855 "avb0_phy_int", 1856 "avb0_mdio", 1857 "avb0_rgmii", 1858 "avb0_txcrefclk", 1859 "avb0_avtp_pps", 1860 "avb0_avtp_capture", 1861 "avb0_avtp_match", 1862 }; 1863 1864 static const char * const canfd_clk_groups[] = { 1865 "canfd_clk_a", 1866 "canfd_clk_b", 1867 }; 1868 1869 static const char * const canfd0_groups[] = { 1870 "canfd0_data_a", 1871 "canfd0_data_b", 1872 }; 1873 1874 static const char * const canfd1_groups[] = { 1875 "canfd1_data", 1876 }; 1877 1878 static const char * const du_groups[] = { 1879 "du_rgb666", 1880 "du_clk_out", 1881 "du_sync", 1882 "du_oddf", 1883 "du_cde", 1884 "du_disp", 1885 }; 1886 1887 static const char * const hscif0_groups[] = { 1888 "hscif0_data", 1889 "hscif0_clk", 1890 "hscif0_ctrl", 1891 }; 1892 1893 static const char * const hscif1_groups[] = { 1894 "hscif1_data", 1895 "hscif1_clk", 1896 "hscif1_ctrl", 1897 }; 1898 1899 static const char * const hscif2_groups[] = { 1900 "hscif2_data", 1901 "hscif2_clk", 1902 "hscif2_ctrl", 1903 }; 1904 1905 static const char * const hscif3_groups[] = { 1906 "hscif3_data", 1907 "hscif3_clk", 1908 "hscif3_ctrl", 1909 }; 1910 1911 static const char * const i2c0_groups[] = { 1912 "i2c0", 1913 }; 1914 1915 static const char * const i2c1_groups[] = { 1916 "i2c1", 1917 }; 1918 1919 static const char * const i2c2_groups[] = { 1920 "i2c2", 1921 }; 1922 1923 static const char * const i2c3_groups[] = { 1924 "i2c3_a", 1925 "i2c3_b", 1926 }; 1927 1928 static const char * const i2c4_groups[] = { 1929 "i2c4", 1930 }; 1931 1932 static const char * const intc_ex_groups[] = { 1933 "intc_ex_irq0", 1934 "intc_ex_irq1", 1935 "intc_ex_irq2", 1936 "intc_ex_irq3", 1937 "intc_ex_irq4", 1938 "intc_ex_irq5", 1939 }; 1940 1941 static const char * const mmc_groups[] = { 1942 "mmc_data1", 1943 "mmc_data4", 1944 "mmc_data8", 1945 "mmc_ctrl", 1946 }; 1947 1948 static const char * const msiof0_groups[] = { 1949 "msiof0_clk", 1950 "msiof0_sync", 1951 "msiof0_ss1", 1952 "msiof0_ss2", 1953 "msiof0_txd", 1954 "msiof0_rxd", 1955 }; 1956 1957 static const char * const msiof1_groups[] = { 1958 "msiof1_clk", 1959 "msiof1_sync", 1960 "msiof1_ss1", 1961 "msiof1_ss2", 1962 "msiof1_txd", 1963 "msiof1_rxd", 1964 }; 1965 1966 static const char * const msiof2_groups[] = { 1967 "msiof2_clk", 1968 "msiof2_sync", 1969 "msiof2_ss1", 1970 "msiof2_ss2", 1971 "msiof2_txd", 1972 "msiof2_rxd", 1973 }; 1974 1975 static const char * const msiof3_groups[] = { 1976 "msiof3_clk", 1977 "msiof3_sync", 1978 "msiof3_ss1", 1979 "msiof3_ss2", 1980 "msiof3_txd", 1981 "msiof3_rxd", 1982 }; 1983 1984 static const char * const pwm0_groups[] = { 1985 "pwm0_a", 1986 "pwm0_b", 1987 }; 1988 1989 static const char * const pwm1_groups[] = { 1990 "pwm1_a", 1991 "pwm1_b", 1992 }; 1993 1994 static const char * const pwm2_groups[] = { 1995 "pwm2_a", 1996 "pwm2_b", 1997 }; 1998 1999 static const char * const pwm3_groups[] = { 2000 "pwm3_a", 2001 "pwm3_b", 2002 }; 2003 2004 static const char * const pwm4_groups[] = { 2005 "pwm4_a", 2006 "pwm4_b", 2007 }; 2008 2009 static const char * const qspi0_groups[] = { 2010 "qspi0_ctrl", 2011 "qspi0_data2", 2012 "qspi0_data4", 2013 }; 2014 2015 static const char * const qspi1_groups[] = { 2016 "qspi1_ctrl", 2017 "qspi1_data2", 2018 "qspi1_data4", 2019 }; 2020 2021 static const char * const rpc_groups[] = { 2022 "rpc_clk1", 2023 "rpc_clk2", 2024 "rpc_ctrl", 2025 "rpc_data", 2026 "rpc_reset", 2027 "rpc_int", 2028 "rpc_wp", 2029 }; 2030 2031 static const char * const scif_clk_groups[] = { 2032 "scif_clk_a", 2033 "scif_clk_b", 2034 }; 2035 2036 static const char * const scif0_groups[] = { 2037 "scif0_data", 2038 "scif0_clk", 2039 "scif0_ctrl", 2040 }; 2041 2042 static const char * const scif1_groups[] = { 2043 "scif1_data_a", 2044 "scif1_clk", 2045 "scif1_ctrl", 2046 "scif1_data_b", 2047 }; 2048 2049 static const char * const scif3_groups[] = { 2050 "scif3_data", 2051 "scif3_clk", 2052 "scif3_ctrl", 2053 }; 2054 2055 static const char * const scif4_groups[] = { 2056 "scif4_data", 2057 "scif4_clk", 2058 "scif4_ctrl", 2059 }; 2060 2061 static const char * const tmu_groups[] = { 2062 "tmu_tclk1_a", 2063 "tmu_tclk1_b", 2064 "tmu_tclk2_a", 2065 "tmu_tclk2_b", 2066 }; 2067 2068 static const char * const vin0_groups[] = { 2069 "vin0_data8", 2070 "vin0_data10", 2071 "vin0_data12", 2072 "vin0_sync", 2073 "vin0_field", 2074 "vin0_clkenb", 2075 "vin0_clk", 2076 }; 2077 2078 static const char * const vin1_groups[] = { 2079 "vin1_data8", 2080 "vin1_data10", 2081 "vin1_data12", 2082 "vin1_sync", 2083 "vin1_field", 2084 "vin1_clkenb", 2085 "vin1_clk", 2086 }; 2087 2088 static const struct sh_pfc_function pinmux_functions[] = { 2089 SH_PFC_FUNCTION(avb0), 2090 SH_PFC_FUNCTION(canfd_clk), 2091 SH_PFC_FUNCTION(canfd0), 2092 SH_PFC_FUNCTION(canfd1), 2093 SH_PFC_FUNCTION(du), 2094 SH_PFC_FUNCTION(hscif0), 2095 SH_PFC_FUNCTION(hscif1), 2096 SH_PFC_FUNCTION(hscif2), 2097 SH_PFC_FUNCTION(hscif3), 2098 SH_PFC_FUNCTION(i2c0), 2099 SH_PFC_FUNCTION(i2c1), 2100 SH_PFC_FUNCTION(i2c2), 2101 SH_PFC_FUNCTION(i2c3), 2102 SH_PFC_FUNCTION(i2c4), 2103 SH_PFC_FUNCTION(intc_ex), 2104 SH_PFC_FUNCTION(mmc), 2105 SH_PFC_FUNCTION(msiof0), 2106 SH_PFC_FUNCTION(msiof1), 2107 SH_PFC_FUNCTION(msiof2), 2108 SH_PFC_FUNCTION(msiof3), 2109 SH_PFC_FUNCTION(pwm0), 2110 SH_PFC_FUNCTION(pwm1), 2111 SH_PFC_FUNCTION(pwm2), 2112 SH_PFC_FUNCTION(pwm3), 2113 SH_PFC_FUNCTION(pwm4), 2114 SH_PFC_FUNCTION(qspi0), 2115 SH_PFC_FUNCTION(qspi1), 2116 SH_PFC_FUNCTION(rpc), 2117 SH_PFC_FUNCTION(scif_clk), 2118 SH_PFC_FUNCTION(scif0), 2119 SH_PFC_FUNCTION(scif1), 2120 SH_PFC_FUNCTION(scif3), 2121 SH_PFC_FUNCTION(scif4), 2122 SH_PFC_FUNCTION(tmu), 2123 SH_PFC_FUNCTION(vin0), 2124 SH_PFC_FUNCTION(vin1), 2125 }; 2126 2127 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 2128 #define F_(x, y) FN_##y 2129 #define FM(x) FN_##x 2130 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( 2131 0, 0, 2132 0, 0, 2133 0, 0, 2134 0, 0, 2135 0, 0, 2136 0, 0, 2137 0, 0, 2138 0, 0, 2139 0, 0, 2140 0, 0, 2141 GP_0_21_FN, GPSR0_21, 2142 GP_0_20_FN, GPSR0_20, 2143 GP_0_19_FN, GPSR0_19, 2144 GP_0_18_FN, GPSR0_18, 2145 GP_0_17_FN, GPSR0_17, 2146 GP_0_16_FN, GPSR0_16, 2147 GP_0_15_FN, GPSR0_15, 2148 GP_0_14_FN, GPSR0_14, 2149 GP_0_13_FN, GPSR0_13, 2150 GP_0_12_FN, GPSR0_12, 2151 GP_0_11_FN, GPSR0_11, 2152 GP_0_10_FN, GPSR0_10, 2153 GP_0_9_FN, GPSR0_9, 2154 GP_0_8_FN, GPSR0_8, 2155 GP_0_7_FN, GPSR0_7, 2156 GP_0_6_FN, GPSR0_6, 2157 GP_0_5_FN, GPSR0_5, 2158 GP_0_4_FN, GPSR0_4, 2159 GP_0_3_FN, GPSR0_3, 2160 GP_0_2_FN, GPSR0_2, 2161 GP_0_1_FN, GPSR0_1, 2162 GP_0_0_FN, GPSR0_0, )) 2163 }, 2164 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( 2165 0, 0, 2166 0, 0, 2167 0, 0, 2168 0, 0, 2169 GP_1_27_FN, GPSR1_27, 2170 GP_1_26_FN, GPSR1_26, 2171 GP_1_25_FN, GPSR1_25, 2172 GP_1_24_FN, GPSR1_24, 2173 GP_1_23_FN, GPSR1_23, 2174 GP_1_22_FN, GPSR1_22, 2175 GP_1_21_FN, GPSR1_21, 2176 GP_1_20_FN, GPSR1_20, 2177 GP_1_19_FN, GPSR1_19, 2178 GP_1_18_FN, GPSR1_18, 2179 GP_1_17_FN, GPSR1_17, 2180 GP_1_16_FN, GPSR1_16, 2181 GP_1_15_FN, GPSR1_15, 2182 GP_1_14_FN, GPSR1_14, 2183 GP_1_13_FN, GPSR1_13, 2184 GP_1_12_FN, GPSR1_12, 2185 GP_1_11_FN, GPSR1_11, 2186 GP_1_10_FN, GPSR1_10, 2187 GP_1_9_FN, GPSR1_9, 2188 GP_1_8_FN, GPSR1_8, 2189 GP_1_7_FN, GPSR1_7, 2190 GP_1_6_FN, GPSR1_6, 2191 GP_1_5_FN, GPSR1_5, 2192 GP_1_4_FN, GPSR1_4, 2193 GP_1_3_FN, GPSR1_3, 2194 GP_1_2_FN, GPSR1_2, 2195 GP_1_1_FN, GPSR1_1, 2196 GP_1_0_FN, GPSR1_0, )) 2197 }, 2198 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( 2199 0, 0, 2200 0, 0, 2201 0, 0, 2202 0, 0, 2203 0, 0, 2204 0, 0, 2205 0, 0, 2206 0, 0, 2207 0, 0, 2208 0, 0, 2209 0, 0, 2210 0, 0, 2211 0, 0, 2212 0, 0, 2213 0, 0, 2214 GP_2_16_FN, GPSR2_16, 2215 GP_2_15_FN, GPSR2_15, 2216 GP_2_14_FN, GPSR2_14, 2217 GP_2_13_FN, GPSR2_13, 2218 GP_2_12_FN, GPSR2_12, 2219 GP_2_11_FN, GPSR2_11, 2220 GP_2_10_FN, GPSR2_10, 2221 GP_2_9_FN, GPSR2_9, 2222 GP_2_8_FN, GPSR2_8, 2223 GP_2_7_FN, GPSR2_7, 2224 GP_2_6_FN, GPSR2_6, 2225 GP_2_5_FN, GPSR2_5, 2226 GP_2_4_FN, GPSR2_4, 2227 GP_2_3_FN, GPSR2_3, 2228 GP_2_2_FN, GPSR2_2, 2229 GP_2_1_FN, GPSR2_1, 2230 GP_2_0_FN, GPSR2_0, )) 2231 }, 2232 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( 2233 0, 0, 2234 0, 0, 2235 0, 0, 2236 0, 0, 2237 0, 0, 2238 0, 0, 2239 0, 0, 2240 0, 0, 2241 0, 0, 2242 0, 0, 2243 0, 0, 2244 0, 0, 2245 0, 0, 2246 0, 0, 2247 0, 0, 2248 GP_3_16_FN, GPSR3_16, 2249 GP_3_15_FN, GPSR3_15, 2250 GP_3_14_FN, GPSR3_14, 2251 GP_3_13_FN, GPSR3_13, 2252 GP_3_12_FN, GPSR3_12, 2253 GP_3_11_FN, GPSR3_11, 2254 GP_3_10_FN, GPSR3_10, 2255 GP_3_9_FN, GPSR3_9, 2256 GP_3_8_FN, GPSR3_8, 2257 GP_3_7_FN, GPSR3_7, 2258 GP_3_6_FN, GPSR3_6, 2259 GP_3_5_FN, GPSR3_5, 2260 GP_3_4_FN, GPSR3_4, 2261 GP_3_3_FN, GPSR3_3, 2262 GP_3_2_FN, GPSR3_2, 2263 GP_3_1_FN, GPSR3_1, 2264 GP_3_0_FN, GPSR3_0, )) 2265 }, 2266 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( 2267 0, 0, 2268 0, 0, 2269 0, 0, 2270 0, 0, 2271 0, 0, 2272 0, 0, 2273 0, 0, 2274 0, 0, 2275 0, 0, 2276 0, 0, 2277 0, 0, 2278 0, 0, 2279 0, 0, 2280 0, 0, 2281 0, 0, 2282 0, 0, 2283 0, 0, 2284 0, 0, 2285 0, 0, 2286 0, 0, 2287 0, 0, 2288 0, 0, 2289 0, 0, 2290 0, 0, 2291 0, 0, 2292 0, 0, 2293 GP_4_5_FN, GPSR4_5, 2294 GP_4_4_FN, GPSR4_4, 2295 GP_4_3_FN, GPSR4_3, 2296 GP_4_2_FN, GPSR4_2, 2297 GP_4_1_FN, GPSR4_1, 2298 GP_4_0_FN, GPSR4_0, )) 2299 }, 2300 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( 2301 0, 0, 2302 0, 0, 2303 0, 0, 2304 0, 0, 2305 0, 0, 2306 0, 0, 2307 0, 0, 2308 0, 0, 2309 0, 0, 2310 0, 0, 2311 0, 0, 2312 0, 0, 2313 0, 0, 2314 0, 0, 2315 0, 0, 2316 0, 0, 2317 0, 0, 2318 GP_5_14_FN, GPSR5_14, 2319 GP_5_13_FN, GPSR5_13, 2320 GP_5_12_FN, GPSR5_12, 2321 GP_5_11_FN, GPSR5_11, 2322 GP_5_10_FN, GPSR5_10, 2323 GP_5_9_FN, GPSR5_9, 2324 GP_5_8_FN, GPSR5_8, 2325 GP_5_7_FN, GPSR5_7, 2326 GP_5_6_FN, GPSR5_6, 2327 GP_5_5_FN, GPSR5_5, 2328 GP_5_4_FN, GPSR5_4, 2329 GP_5_3_FN, GPSR5_3, 2330 GP_5_2_FN, GPSR5_2, 2331 GP_5_1_FN, GPSR5_1, 2332 GP_5_0_FN, GPSR5_0, )) 2333 }, 2334 #undef F_ 2335 #undef FM 2336 2337 #define F_(x, y) x, 2338 #define FM(x) FN_##x, 2339 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( 2340 IP0_31_28 2341 IP0_27_24 2342 IP0_23_20 2343 IP0_19_16 2344 IP0_15_12 2345 IP0_11_8 2346 IP0_7_4 2347 IP0_3_0 )) 2348 }, 2349 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( 2350 IP1_31_28 2351 IP1_27_24 2352 IP1_23_20 2353 IP1_19_16 2354 IP1_15_12 2355 IP1_11_8 2356 IP1_7_4 2357 IP1_3_0 )) 2358 }, 2359 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( 2360 IP2_31_28 2361 IP2_27_24 2362 IP2_23_20 2363 IP2_19_16 2364 IP2_15_12 2365 IP2_11_8 2366 IP2_7_4 2367 IP2_3_0 )) 2368 }, 2369 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( 2370 IP3_31_28 2371 IP3_27_24 2372 IP3_23_20 2373 IP3_19_16 2374 IP3_15_12 2375 IP3_11_8 2376 IP3_7_4 2377 IP3_3_0 )) 2378 }, 2379 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( 2380 IP4_31_28 2381 IP4_27_24 2382 IP4_23_20 2383 IP4_19_16 2384 IP4_15_12 2385 IP4_11_8 2386 IP4_7_4 2387 IP4_3_0 )) 2388 }, 2389 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( 2390 IP5_31_28 2391 IP5_27_24 2392 IP5_23_20 2393 IP5_19_16 2394 IP5_15_12 2395 IP5_11_8 2396 IP5_7_4 2397 IP5_3_0 )) 2398 }, 2399 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( 2400 IP6_31_28 2401 IP6_27_24 2402 IP6_23_20 2403 IP6_19_16 2404 IP6_15_12 2405 IP6_11_8 2406 IP6_7_4 2407 IP6_3_0 )) 2408 }, 2409 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( 2410 IP7_31_28 2411 IP7_27_24 2412 IP7_23_20 2413 IP7_19_16 2414 IP7_15_12 2415 IP7_11_8 2416 IP7_7_4 2417 IP7_3_0 )) 2418 }, 2419 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( 2420 IP8_31_28 2421 IP8_27_24 2422 IP8_23_20 2423 IP8_19_16 2424 IP8_15_12 2425 IP8_11_8 2426 IP8_7_4 2427 IP8_3_0 )) 2428 }, 2429 #undef F_ 2430 #undef FM 2431 2432 #define F_(x, y) x, 2433 #define FM(x) FN_##x, 2434 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, 2435 GROUP(4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 2436 1, 1, 1, 1, 1), 2437 GROUP( 2438 /* RESERVED 31, 30, 29, 28 */ 2439 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2440 /* RESERVED 27, 26, 25, 24 */ 2441 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2442 /* RESERVED 23, 22, 21, 20 */ 2443 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2444 /* RESERVED 19, 18, 17, 16 */ 2445 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2446 /* RESERVED 15, 14, 13, 12 */ 2447 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2448 MOD_SEL0_11 2449 MOD_SEL0_10 2450 MOD_SEL0_9 2451 MOD_SEL0_8 2452 MOD_SEL0_7 2453 MOD_SEL0_6 2454 MOD_SEL0_5 2455 MOD_SEL0_4 2456 MOD_SEL0_3 2457 MOD_SEL0_2 2458 MOD_SEL0_1 2459 MOD_SEL0_0 )) 2460 }, 2461 { }, 2462 }; 2463 2464 enum ioctrl_regs { 2465 POCCTRL0, 2466 POCCTRL1, 2467 POCCTRL2, 2468 TDSELCTRL, 2469 }; 2470 2471 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { 2472 [POCCTRL0] = { 0xe6060380 }, 2473 [POCCTRL1] = { 0xe6060384 }, 2474 [POCCTRL2] = { 0xe6060388 }, 2475 [TDSELCTRL] = { 0xe60603c0, }, 2476 { /* sentinel */ }, 2477 }; 2478 2479 static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, 2480 u32 *pocctrl) 2481 { 2482 int bit = pin & 0x1f; 2483 2484 *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg; 2485 if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21)) 2486 return bit; 2487 if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9)) 2488 return bit + 22; 2489 2490 *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg; 2491 if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16)) 2492 return bit - 10; 2493 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16)) 2494 return bit + 7; 2495 2496 return -EINVAL; 2497 } 2498 2499 static const struct sh_pfc_soc_operations pinmux_ops = { 2500 .pin_to_pocctrl = r8a77970_pin_to_pocctrl, 2501 }; 2502 2503 const struct sh_pfc_soc_info r8a77970_pinmux_info = { 2504 .name = "r8a77970_pfc", 2505 .ops = &pinmux_ops, 2506 .unlock_reg = 0xe6060000, /* PMMR */ 2507 2508 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 2509 2510 .pins = pinmux_pins, 2511 .nr_pins = ARRAY_SIZE(pinmux_pins), 2512 .groups = pinmux_groups, 2513 .nr_groups = ARRAY_SIZE(pinmux_groups), 2514 .functions = pinmux_functions, 2515 .nr_functions = ARRAY_SIZE(pinmux_functions), 2516 2517 .cfg_regs = pinmux_config_regs, 2518 .ioctrl_regs = pinmux_ioctrl_regs, 2519 2520 .pinmux_data = pinmux_data, 2521 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 2522 }; 2523