1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * R8A77970 processor support - PFC hardware block. 4 * 5 * Copyright (C) 2016 Renesas Electronics Corp. 6 * Copyright (C) 2017 Cogent Embedded, Inc. <source@cogentembedded.com> 7 * 8 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c 9 * 10 * R-Car Gen3 processor support - PFC hardware block. 11 * 12 * Copyright (C) 2015 Renesas Electronics Corporation 13 */ 14 15 #include <linux/errno.h> 16 #include <linux/io.h> 17 #include <linux/kernel.h> 18 19 #include "sh_pfc.h" 20 21 #define CPU_ALL_GP(fn, sfx) \ 22 PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 23 PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 24 PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 25 PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 26 PORT_GP_CFG_6(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 27 PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN) 28 29 #define CPU_ALL_NOGP(fn) \ 30 PIN_NOGP_CFG(DU_DOTCLKIN, "DU_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_DOWN), \ 31 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_DOWN), \ 32 PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 33 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 34 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \ 35 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \ 36 PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \ 37 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP) 38 39 /* 40 * F_() : just information 41 * FM() : macro for FN_xxx / xxx_MARK 42 */ 43 44 /* GPSR0 */ 45 #define GPSR0_21 F_(DU_EXODDF_DU_ODDF_DISP_CDE, IP2_23_20) 46 #define GPSR0_20 F_(DU_EXVSYNC_DU_VSYNC, IP2_19_16) 47 #define GPSR0_19 F_(DU_EXHSYNC_DU_HSYNC, IP2_15_12) 48 #define GPSR0_18 F_(DU_DOTCLKOUT, IP2_11_8) 49 #define GPSR0_17 F_(DU_DB7, IP2_7_4) 50 #define GPSR0_16 F_(DU_DB6, IP2_3_0) 51 #define GPSR0_15 F_(DU_DB5, IP1_31_28) 52 #define GPSR0_14 F_(DU_DB4, IP1_27_24) 53 #define GPSR0_13 F_(DU_DB3, IP1_23_20) 54 #define GPSR0_12 F_(DU_DB2, IP1_19_16) 55 #define GPSR0_11 F_(DU_DG7, IP1_15_12) 56 #define GPSR0_10 F_(DU_DG6, IP1_11_8) 57 #define GPSR0_9 F_(DU_DG5, IP1_7_4) 58 #define GPSR0_8 F_(DU_DG4, IP1_3_0) 59 #define GPSR0_7 F_(DU_DG3, IP0_31_28) 60 #define GPSR0_6 F_(DU_DG2, IP0_27_24) 61 #define GPSR0_5 F_(DU_DR7, IP0_23_20) 62 #define GPSR0_4 F_(DU_DR6, IP0_19_16) 63 #define GPSR0_3 F_(DU_DR5, IP0_15_12) 64 #define GPSR0_2 F_(DU_DR4, IP0_11_8) 65 #define GPSR0_1 F_(DU_DR3, IP0_7_4) 66 #define GPSR0_0 F_(DU_DR2, IP0_3_0) 67 68 /* GPSR1 */ 69 #define GPSR1_27 F_(DIGRF_CLKOUT, IP8_27_24) 70 #define GPSR1_26 F_(DIGRF_CLKIN, IP8_23_20) 71 #define GPSR1_25 F_(CANFD_CLK_A, IP8_19_16) 72 #define GPSR1_24 F_(CANFD1_RX, IP8_15_12) 73 #define GPSR1_23 F_(CANFD1_TX, IP8_11_8) 74 #define GPSR1_22 F_(CANFD0_RX_A, IP8_7_4) 75 #define GPSR1_21 F_(CANFD0_TX_A, IP8_3_0) 76 #define GPSR1_20 F_(AVB0_AVTP_CAPTURE, IP7_31_28) 77 #define GPSR1_19 FM(AVB0_AVTP_MATCH) 78 #define GPSR1_18 FM(AVB0_LINK) 79 #define GPSR1_17 FM(AVB0_PHY_INT) 80 #define GPSR1_16 FM(AVB0_MAGIC) 81 #define GPSR1_15 FM(AVB0_MDC) 82 #define GPSR1_14 FM(AVB0_MDIO) 83 #define GPSR1_13 FM(AVB0_TXCREFCLK) 84 #define GPSR1_12 FM(AVB0_TD3) 85 #define GPSR1_11 FM(AVB0_TD2) 86 #define GPSR1_10 FM(AVB0_TD1) 87 #define GPSR1_9 FM(AVB0_TD0) 88 #define GPSR1_8 FM(AVB0_TXC) 89 #define GPSR1_7 FM(AVB0_TX_CTL) 90 #define GPSR1_6 FM(AVB0_RD3) 91 #define GPSR1_5 FM(AVB0_RD2) 92 #define GPSR1_4 FM(AVB0_RD1) 93 #define GPSR1_3 FM(AVB0_RD0) 94 #define GPSR1_2 FM(AVB0_RXC) 95 #define GPSR1_1 FM(AVB0_RX_CTL) 96 #define GPSR1_0 F_(IRQ0, IP2_27_24) 97 98 /* GPSR2 */ 99 #define GPSR2_16 F_(VI0_FIELD, IP4_31_28) 100 #define GPSR2_15 F_(VI0_DATA11, IP4_27_24) 101 #define GPSR2_14 F_(VI0_DATA10, IP4_23_20) 102 #define GPSR2_13 F_(VI0_DATA9, IP4_19_16) 103 #define GPSR2_12 F_(VI0_DATA8, IP4_15_12) 104 #define GPSR2_11 F_(VI0_DATA7, IP4_11_8) 105 #define GPSR2_10 F_(VI0_DATA6, IP4_7_4) 106 #define GPSR2_9 F_(VI0_DATA5, IP4_3_0) 107 #define GPSR2_8 F_(VI0_DATA4, IP3_31_28) 108 #define GPSR2_7 F_(VI0_DATA3, IP3_27_24) 109 #define GPSR2_6 F_(VI0_DATA2, IP3_23_20) 110 #define GPSR2_5 F_(VI0_DATA1, IP3_19_16) 111 #define GPSR2_4 F_(VI0_DATA0, IP3_15_12) 112 #define GPSR2_3 F_(VI0_VSYNC_N, IP3_11_8) 113 #define GPSR2_2 F_(VI0_HSYNC_N, IP3_7_4) 114 #define GPSR2_1 F_(VI0_CLKENB, IP3_3_0) 115 #define GPSR2_0 F_(VI0_CLK, IP2_31_28) 116 117 /* GPSR3 */ 118 #define GPSR3_16 F_(VI1_FIELD, IP7_3_0) 119 #define GPSR3_15 F_(VI1_DATA11, IP6_31_28) 120 #define GPSR3_14 F_(VI1_DATA10, IP6_27_24) 121 #define GPSR3_13 F_(VI1_DATA9, IP6_23_20) 122 #define GPSR3_12 F_(VI1_DATA8, IP6_19_16) 123 #define GPSR3_11 F_(VI1_DATA7, IP6_15_12) 124 #define GPSR3_10 F_(VI1_DATA6, IP6_11_8) 125 #define GPSR3_9 F_(VI1_DATA5, IP6_7_4) 126 #define GPSR3_8 F_(VI1_DATA4, IP6_3_0) 127 #define GPSR3_7 F_(VI1_DATA3, IP5_31_28) 128 #define GPSR3_6 F_(VI1_DATA2, IP5_27_24) 129 #define GPSR3_5 F_(VI1_DATA1, IP5_23_20) 130 #define GPSR3_4 F_(VI1_DATA0, IP5_19_16) 131 #define GPSR3_3 F_(VI1_VSYNC_N, IP5_15_12) 132 #define GPSR3_2 F_(VI1_HSYNC_N, IP5_11_8) 133 #define GPSR3_1 F_(VI1_CLKENB, IP5_7_4) 134 #define GPSR3_0 F_(VI1_CLK, IP5_3_0) 135 136 /* GPSR4 */ 137 #define GPSR4_5 F_(SDA2, IP7_27_24) 138 #define GPSR4_4 F_(SCL2, IP7_23_20) 139 #define GPSR4_3 F_(SDA1, IP7_19_16) 140 #define GPSR4_2 F_(SCL1, IP7_15_12) 141 #define GPSR4_1 F_(SDA0, IP7_11_8) 142 #define GPSR4_0 F_(SCL0, IP7_7_4) 143 144 /* GPSR5 */ 145 #define GPSR5_14 FM(RPC_INT_N) 146 #define GPSR5_13 FM(RPC_WP_N) 147 #define GPSR5_12 FM(RPC_RESET_N) 148 #define GPSR5_11 FM(QSPI1_SSL) 149 #define GPSR5_10 FM(QSPI1_IO3) 150 #define GPSR5_9 FM(QSPI1_IO2) 151 #define GPSR5_8 FM(QSPI1_MISO_IO1) 152 #define GPSR5_7 FM(QSPI1_MOSI_IO0) 153 #define GPSR5_6 FM(QSPI1_SPCLK) 154 #define GPSR5_5 FM(QSPI0_SSL) 155 #define GPSR5_4 FM(QSPI0_IO3) 156 #define GPSR5_3 FM(QSPI0_IO2) 157 #define GPSR5_2 FM(QSPI0_MISO_IO1) 158 #define GPSR5_1 FM(QSPI0_MOSI_IO0) 159 #define GPSR5_0 FM(QSPI0_SPCLK) 160 161 162 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ 163 #define IP0_3_0 FM(DU_DR2) FM(HSCK0) F_(0, 0) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 164 #define IP0_7_4 FM(DU_DR3) FM(HRTS0_N) F_(0, 0) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 165 #define IP0_11_8 FM(DU_DR4) FM(HCTS0_N) F_(0, 0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 166 #define IP0_15_12 FM(DU_DR5) FM(HTX0) F_(0, 0) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 167 #define IP0_19_16 FM(DU_DR6) FM(MSIOF3_RXD) F_(0, 0) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 168 #define IP0_23_20 FM(DU_DR7) FM(MSIOF3_TXD) F_(0, 0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 169 #define IP0_27_24 FM(DU_DG2) FM(MSIOF3_SS1) F_(0, 0) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 170 #define IP0_31_28 FM(DU_DG3) FM(MSIOF3_SS2) F_(0, 0) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 171 #define IP1_3_0 FM(DU_DG4) F_(0, 0) F_(0, 0) FM(A8) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 172 #define IP1_7_4 FM(DU_DG5) F_(0, 0) F_(0, 0) FM(A9) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 173 #define IP1_11_8 FM(DU_DG6) F_(0, 0) F_(0, 0) FM(A10) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 174 #define IP1_15_12 FM(DU_DG7) F_(0, 0) F_(0, 0) FM(A11) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 175 #define IP1_19_16 FM(DU_DB2) F_(0, 0) F_(0, 0) FM(A12) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 176 #define IP1_23_20 FM(DU_DB3) F_(0, 0) F_(0, 0) FM(A13) FM(FXR_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 177 #define IP1_27_24 FM(DU_DB4) F_(0, 0) F_(0, 0) FM(A14) FM(FXR_CLKOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 178 #define IP1_31_28 FM(DU_DB5) F_(0, 0) F_(0, 0) FM(A15) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 179 #define IP2_3_0 FM(DU_DB6) F_(0, 0) F_(0, 0) FM(A16) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 180 #define IP2_7_4 FM(DU_DB7) F_(0, 0) F_(0, 0) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 181 #define IP2_11_8 FM(DU_DOTCLKOUT) FM(SCIF_CLK_A) F_(0, 0) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 182 #define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(HRX0) F_(0, 0) FM(A19) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 183 #define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 184 #define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 185 #define IP2_27_24 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 186 #define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 187 #define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 188 #define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 189 #define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 190 #define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 191 #define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 192 #define IP3_23_20 FM(VI0_DATA2) FM(AVB0_AVTP_PPS) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 193 #define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 194 #define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 195 #define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 196 #define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 197 #define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 198 #define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) FM(PWM0_A) FM(A22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 199 #define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) FM(A23) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 200 #define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) FM(A24) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 201 #define IP4_27_24 FM(VI0_DATA11) FM(HTX2) FM(PWM3_A) FM(A25) FM(FSO_TOE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 202 #define IP4_31_28 FM(VI0_FIELD) FM(HRX2) FM(PWM4_A) FM(CS1_N) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 203 #define IP5_3_0 FM(VI1_CLK) FM(MSIOF1_RXD) F_(0, 0) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 204 #define IP5_7_4 FM(VI1_CLKENB) FM(MSIOF1_TXD) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 205 #define IP5_11_8 FM(VI1_HSYNC_N) FM(MSIOF1_SCK) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 206 #define IP5_15_12 FM(VI1_VSYNC_N) FM(MSIOF1_SYNC) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 207 #define IP5_19_16 FM(VI1_DATA0) FM(MSIOF1_SS1) F_(0, 0) FM(D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 208 #define IP5_23_20 FM(VI1_DATA1) FM(MSIOF1_SS2) F_(0, 0) FM(D4) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 209 #define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 210 #define IP5_31_28 FM(VI1_DATA3) FM(CANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 211 #define IP6_3_0 FM(VI1_DATA4) FM(CANFD_CLK_B) F_(0, 0) FM(D7) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 212 #define IP6_7_4 FM(VI1_DATA5) F_(0, 0) FM(SCK4) FM(D8) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 213 #define IP6_11_8 FM(VI1_DATA6) F_(0, 0) FM(RX4) FM(D9) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 214 #define IP6_15_12 FM(VI1_DATA7) F_(0, 0) FM(TX4) FM(D10) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 215 #define IP6_19_16 FM(VI1_DATA8) F_(0, 0) FM(CTS4_N) FM(D11) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 216 #define IP6_23_20 FM(VI1_DATA9) F_(0, 0) FM(RTS4_N) FM(D12) FM(MMC_D6) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 217 #define IP6_27_24 FM(VI1_DATA10) F_(0, 0) F_(0, 0) FM(D13) FM(MMC_D7) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 218 #define IP6_31_28 FM(VI1_DATA11) FM(SCL4) FM(IRQ4) FM(D14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 219 #define IP7_3_0 FM(VI1_FIELD) FM(SDA4) FM(IRQ5) FM(D15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 220 #define IP7_7_4 FM(SCL0) FM(DU_DR0) FM(TPU0TO0) FM(CLKOUT) F_(0, 0) FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 221 #define IP7_11_8 FM(SDA0) FM(DU_DR1) FM(TPU0TO1) FM(BS_N) FM(SCK0) FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 222 #define IP7_15_12 FM(SCL1) FM(DU_DG0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 223 #define IP7_19_16 FM(SDA1) FM(DU_DG1) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N) FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 224 #define IP7_23_20 FM(SCL2) FM(DU_DB0) FM(TCLK1_A) FM(WE1_N) FM(RX0) FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 225 #define IP7_27_24 FM(SDA2) FM(DU_DB1) FM(TCLK2_A) FM(EX_WAIT0) FM(TX0) FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 226 #define IP7_31_28 FM(AVB0_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSCLKST2_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 227 #define IP8_3_0 FM(CANFD0_TX_A) FM(FXR_TXDA) FM(PWM0_B) FM(DU_DISP) FM(FSCLKST2_N_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 228 #define IP8_7_4 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 229 #define IP8_11_8 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 230 #define IP8_15_12 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 231 #define IP8_19_16 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 232 #define IP8_23_20 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 233 #define IP8_27_24 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 234 235 #define PINMUX_GPSR \ 236 \ 237 GPSR1_27 \ 238 GPSR1_26 \ 239 GPSR1_25 \ 240 GPSR1_24 \ 241 GPSR1_23 \ 242 GPSR1_22 \ 243 GPSR0_21 GPSR1_21 \ 244 GPSR0_20 GPSR1_20 \ 245 GPSR0_19 GPSR1_19 \ 246 GPSR0_18 GPSR1_18 \ 247 GPSR0_17 GPSR1_17 \ 248 GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 \ 249 GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 \ 250 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR5_14 \ 251 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR5_13 \ 252 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR5_12 \ 253 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR5_11 \ 254 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR5_10 \ 255 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR5_9 \ 256 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR5_8 \ 257 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR5_7 \ 258 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR5_6 \ 259 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 \ 260 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 \ 261 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 \ 262 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 \ 263 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 \ 264 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 265 266 #define PINMUX_IPSR \ 267 \ 268 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \ 269 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \ 270 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \ 271 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \ 272 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \ 273 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \ 274 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ 275 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \ 276 \ 277 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ 278 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ 279 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ 280 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \ 281 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ 282 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ 283 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ 284 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ 285 \ 286 FM(IP8_3_0) IP8_3_0 \ 287 FM(IP8_7_4) IP8_7_4 \ 288 FM(IP8_11_8) IP8_11_8 \ 289 FM(IP8_15_12) IP8_15_12 \ 290 FM(IP8_19_16) IP8_19_16 \ 291 FM(IP8_23_20) IP8_23_20 \ 292 FM(IP8_27_24) IP8_27_24 293 294 /* MOD_SEL0 */ /* 0 */ /* 1 */ 295 #define MOD_SEL0_11 FM(SEL_I2C3_0) FM(SEL_I2C3_1) 296 #define MOD_SEL0_10 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1) 297 #define MOD_SEL0_9 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1) 298 #define MOD_SEL0_8 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) 299 #define MOD_SEL0_7 FM(SEL_PWM4_0) FM(SEL_PWM4_1) 300 #define MOD_SEL0_6 FM(SEL_PWM3_0) FM(SEL_PWM3_1) 301 #define MOD_SEL0_5 FM(SEL_PWM2_0) FM(SEL_PWM2_1) 302 #define MOD_SEL0_4 FM(SEL_PWM1_0) FM(SEL_PWM1_1) 303 #define MOD_SEL0_3 FM(SEL_PWM0_0) FM(SEL_PWM0_1) 304 #define MOD_SEL0_2 FM(SEL_RFSO_0) FM(SEL_RFSO_1) 305 #define MOD_SEL0_1 FM(SEL_RSP_0) FM(SEL_RSP_1) 306 #define MOD_SEL0_0 FM(SEL_TMU_0) FM(SEL_TMU_1) 307 308 #define PINMUX_MOD_SELS \ 309 \ 310 MOD_SEL0_11 \ 311 MOD_SEL0_10 \ 312 MOD_SEL0_9 \ 313 MOD_SEL0_8 \ 314 MOD_SEL0_7 \ 315 MOD_SEL0_6 \ 316 MOD_SEL0_5 \ 317 MOD_SEL0_4 \ 318 MOD_SEL0_3 \ 319 MOD_SEL0_2 \ 320 MOD_SEL0_1 \ 321 MOD_SEL0_0 322 323 enum { 324 PINMUX_RESERVED = 0, 325 326 PINMUX_DATA_BEGIN, 327 GP_ALL(DATA), 328 PINMUX_DATA_END, 329 330 #define F_(x, y) 331 #define FM(x) FN_##x, 332 PINMUX_FUNCTION_BEGIN, 333 GP_ALL(FN), 334 PINMUX_GPSR 335 PINMUX_IPSR 336 PINMUX_MOD_SELS 337 PINMUX_FUNCTION_END, 338 #undef F_ 339 #undef FM 340 341 #define F_(x, y) 342 #define FM(x) x##_MARK, 343 PINMUX_MARK_BEGIN, 344 PINMUX_GPSR 345 PINMUX_IPSR 346 PINMUX_MOD_SELS 347 PINMUX_MARK_END, 348 #undef F_ 349 #undef FM 350 }; 351 352 static const u16 pinmux_data[] = { 353 PINMUX_DATA_GP_ALL(), 354 355 PINMUX_SINGLE(AVB0_RX_CTL), 356 PINMUX_SINGLE(AVB0_RXC), 357 PINMUX_SINGLE(AVB0_RD0), 358 PINMUX_SINGLE(AVB0_RD1), 359 PINMUX_SINGLE(AVB0_RD2), 360 PINMUX_SINGLE(AVB0_RD3), 361 PINMUX_SINGLE(AVB0_TX_CTL), 362 PINMUX_SINGLE(AVB0_TXC), 363 PINMUX_SINGLE(AVB0_TD0), 364 PINMUX_SINGLE(AVB0_TD1), 365 PINMUX_SINGLE(AVB0_TD2), 366 PINMUX_SINGLE(AVB0_TD3), 367 PINMUX_SINGLE(AVB0_TXCREFCLK), 368 PINMUX_SINGLE(AVB0_MDIO), 369 PINMUX_SINGLE(AVB0_MDC), 370 PINMUX_SINGLE(AVB0_MAGIC), 371 PINMUX_SINGLE(AVB0_PHY_INT), 372 PINMUX_SINGLE(AVB0_LINK), 373 PINMUX_SINGLE(AVB0_AVTP_MATCH), 374 375 PINMUX_SINGLE(QSPI0_SPCLK), 376 PINMUX_SINGLE(QSPI0_MOSI_IO0), 377 PINMUX_SINGLE(QSPI0_MISO_IO1), 378 PINMUX_SINGLE(QSPI0_IO2), 379 PINMUX_SINGLE(QSPI0_IO3), 380 PINMUX_SINGLE(QSPI0_SSL), 381 PINMUX_SINGLE(QSPI1_SPCLK), 382 PINMUX_SINGLE(QSPI1_MOSI_IO0), 383 PINMUX_SINGLE(QSPI1_MISO_IO1), 384 PINMUX_SINGLE(QSPI1_IO2), 385 PINMUX_SINGLE(QSPI1_IO3), 386 PINMUX_SINGLE(QSPI1_SSL), 387 PINMUX_SINGLE(RPC_RESET_N), 388 PINMUX_SINGLE(RPC_WP_N), 389 PINMUX_SINGLE(RPC_INT_N), 390 391 /* IPSR0 */ 392 PINMUX_IPSR_GPSR(IP0_3_0, DU_DR2), 393 PINMUX_IPSR_GPSR(IP0_3_0, HSCK0), 394 PINMUX_IPSR_GPSR(IP0_3_0, A0), 395 396 PINMUX_IPSR_GPSR(IP0_7_4, DU_DR3), 397 PINMUX_IPSR_GPSR(IP0_7_4, HRTS0_N), 398 PINMUX_IPSR_GPSR(IP0_7_4, A1), 399 400 PINMUX_IPSR_GPSR(IP0_11_8, DU_DR4), 401 PINMUX_IPSR_GPSR(IP0_11_8, HCTS0_N), 402 PINMUX_IPSR_GPSR(IP0_11_8, A2), 403 404 PINMUX_IPSR_GPSR(IP0_15_12, DU_DR5), 405 PINMUX_IPSR_GPSR(IP0_15_12, HTX0), 406 PINMUX_IPSR_GPSR(IP0_15_12, A3), 407 408 PINMUX_IPSR_GPSR(IP0_19_16, DU_DR6), 409 PINMUX_IPSR_GPSR(IP0_19_16, MSIOF3_RXD), 410 PINMUX_IPSR_GPSR(IP0_19_16, A4), 411 412 PINMUX_IPSR_GPSR(IP0_23_20, DU_DR7), 413 PINMUX_IPSR_GPSR(IP0_23_20, MSIOF3_TXD), 414 PINMUX_IPSR_GPSR(IP0_23_20, A5), 415 416 PINMUX_IPSR_GPSR(IP0_27_24, DU_DG2), 417 PINMUX_IPSR_GPSR(IP0_27_24, MSIOF3_SS1), 418 PINMUX_IPSR_GPSR(IP0_27_24, A6), 419 420 PINMUX_IPSR_GPSR(IP0_31_28, DU_DG3), 421 PINMUX_IPSR_GPSR(IP0_31_28, MSIOF3_SS2), 422 PINMUX_IPSR_GPSR(IP0_31_28, A7), 423 PINMUX_IPSR_GPSR(IP0_31_28, PWMFSW0), 424 425 /* IPSR1 */ 426 PINMUX_IPSR_GPSR(IP1_3_0, DU_DG4), 427 PINMUX_IPSR_GPSR(IP1_3_0, A8), 428 PINMUX_IPSR_MSEL(IP1_3_0, FSO_CFE_0_N_A, SEL_RFSO_0), 429 430 PINMUX_IPSR_GPSR(IP1_7_4, DU_DG5), 431 PINMUX_IPSR_GPSR(IP1_7_4, A9), 432 PINMUX_IPSR_MSEL(IP1_7_4, FSO_CFE_1_N_A, SEL_RFSO_0), 433 434 PINMUX_IPSR_GPSR(IP1_11_8, DU_DG6), 435 PINMUX_IPSR_GPSR(IP1_11_8, A10), 436 PINMUX_IPSR_MSEL(IP1_11_8, FSO_TOE_N_A, SEL_RFSO_0), 437 438 PINMUX_IPSR_GPSR(IP1_15_12, DU_DG7), 439 PINMUX_IPSR_GPSR(IP1_15_12, A11), 440 PINMUX_IPSR_GPSR(IP1_15_12, IRQ1), 441 442 PINMUX_IPSR_GPSR(IP1_19_16, DU_DB2), 443 PINMUX_IPSR_GPSR(IP1_19_16, A12), 444 PINMUX_IPSR_GPSR(IP1_19_16, IRQ2), 445 446 PINMUX_IPSR_GPSR(IP1_23_20, DU_DB3), 447 PINMUX_IPSR_GPSR(IP1_23_20, A13), 448 PINMUX_IPSR_GPSR(IP1_23_20, FXR_CLKOUT1), 449 450 PINMUX_IPSR_GPSR(IP1_27_24, DU_DB4), 451 PINMUX_IPSR_GPSR(IP1_27_24, A14), 452 PINMUX_IPSR_GPSR(IP1_27_24, FXR_CLKOUT2), 453 454 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB5), 455 PINMUX_IPSR_GPSR(IP1_31_28, A15), 456 PINMUX_IPSR_GPSR(IP1_31_28, FXR_TXENA_N), 457 458 /* IPSR2 */ 459 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB6), 460 PINMUX_IPSR_GPSR(IP2_3_0, A16), 461 PINMUX_IPSR_GPSR(IP2_3_0, FXR_TXENB_N), 462 463 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB7), 464 PINMUX_IPSR_GPSR(IP2_7_4, A17), 465 466 PINMUX_IPSR_GPSR(IP2_11_8, DU_DOTCLKOUT), 467 PINMUX_IPSR_MSEL(IP2_11_8, SCIF_CLK_A, SEL_HSCIF0_0), 468 PINMUX_IPSR_GPSR(IP2_11_8, A18), 469 470 PINMUX_IPSR_GPSR(IP2_15_12, DU_EXHSYNC_DU_HSYNC), 471 PINMUX_IPSR_GPSR(IP2_15_12, HRX0), 472 PINMUX_IPSR_GPSR(IP2_15_12, A19), 473 PINMUX_IPSR_GPSR(IP2_15_12, IRQ3), 474 475 PINMUX_IPSR_GPSR(IP2_19_16, DU_EXVSYNC_DU_VSYNC), 476 PINMUX_IPSR_GPSR(IP2_19_16, MSIOF3_SCK), 477 478 PINMUX_IPSR_GPSR(IP2_23_20, DU_EXODDF_DU_ODDF_DISP_CDE), 479 PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC), 480 481 PINMUX_IPSR_GPSR(IP2_27_24, IRQ0), 482 483 PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK), 484 PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK), 485 PINMUX_IPSR_GPSR(IP2_31_28, SCK3), 486 PINMUX_IPSR_GPSR(IP2_31_28, HSCK3), 487 488 /* IPSR3 */ 489 PINMUX_IPSR_GPSR(IP3_3_0, VI0_CLKENB), 490 PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_RXD), 491 PINMUX_IPSR_GPSR(IP3_3_0, RX3), 492 PINMUX_IPSR_GPSR(IP3_3_0, RD_WR_N), 493 PINMUX_IPSR_GPSR(IP3_3_0, HCTS3_N), 494 495 PINMUX_IPSR_GPSR(IP3_7_4, VI0_HSYNC_N), 496 PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD), 497 PINMUX_IPSR_GPSR(IP3_7_4, TX3), 498 PINMUX_IPSR_GPSR(IP3_7_4, HRTS3_N), 499 500 PINMUX_IPSR_GPSR(IP3_11_8, VI0_VSYNC_N), 501 PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_SYNC), 502 PINMUX_IPSR_GPSR(IP3_11_8, CTS3_N), 503 PINMUX_IPSR_GPSR(IP3_11_8, HTX3), 504 505 PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0), 506 PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1), 507 PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N), 508 PINMUX_IPSR_GPSR(IP3_15_12, HRX3), 509 510 PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1), 511 PINMUX_IPSR_GPSR(IP3_19_16, MSIOF2_SS2), 512 PINMUX_IPSR_GPSR(IP3_19_16, SCK1), 513 PINMUX_IPSR_MSEL(IP3_19_16, SPEEDIN_A, SEL_RSP_0), 514 515 PINMUX_IPSR_GPSR(IP3_23_20, VI0_DATA2), 516 PINMUX_IPSR_GPSR(IP3_23_20, AVB0_AVTP_PPS), 517 PINMUX_IPSR_MSEL(IP3_23_20, SDA3_A, SEL_I2C3_0), 518 519 PINMUX_IPSR_GPSR(IP3_27_24, VI0_DATA3), 520 PINMUX_IPSR_GPSR(IP3_27_24, HSCK1), 521 PINMUX_IPSR_MSEL(IP3_27_24, SCL3_A, SEL_I2C3_0), 522 523 PINMUX_IPSR_GPSR(IP3_31_28, VI0_DATA4), 524 PINMUX_IPSR_GPSR(IP3_31_28, HRTS1_N), 525 PINMUX_IPSR_MSEL(IP3_31_28, RX1_A, SEL_SCIF1_0), 526 527 /* IPSR4 */ 528 PINMUX_IPSR_GPSR(IP4_3_0, VI0_DATA5), 529 PINMUX_IPSR_GPSR(IP4_3_0, HCTS1_N), 530 PINMUX_IPSR_MSEL(IP4_3_0, TX1_A, SEL_SCIF1_0), 531 532 PINMUX_IPSR_GPSR(IP4_7_4, VI0_DATA6), 533 PINMUX_IPSR_GPSR(IP4_7_4, HTX1), 534 PINMUX_IPSR_GPSR(IP4_7_4, CTS1_N), 535 536 PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7), 537 PINMUX_IPSR_GPSR(IP4_11_8, HRX1), 538 PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N), 539 540 PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8), 541 PINMUX_IPSR_GPSR(IP4_15_12, HSCK2), 542 PINMUX_IPSR_MSEL(IP4_15_12, PWM0_A, SEL_PWM0_0), 543 544 PINMUX_IPSR_GPSR(IP4_19_16, VI0_DATA9), 545 PINMUX_IPSR_GPSR(IP4_19_16, HCTS2_N), 546 PINMUX_IPSR_MSEL(IP4_19_16, PWM1_A, SEL_PWM1_0), 547 PINMUX_IPSR_MSEL(IP4_19_16, FSO_CFE_0_N_B, SEL_RFSO_1), 548 549 PINMUX_IPSR_GPSR(IP4_23_20, VI0_DATA10), 550 PINMUX_IPSR_GPSR(IP4_23_20, HRTS2_N), 551 PINMUX_IPSR_MSEL(IP4_23_20, PWM2_A, SEL_PWM2_0), 552 PINMUX_IPSR_MSEL(IP4_23_20, FSO_CFE_1_N_B, SEL_RFSO_1), 553 554 PINMUX_IPSR_GPSR(IP4_27_24, VI0_DATA11), 555 PINMUX_IPSR_GPSR(IP4_27_24, HTX2), 556 PINMUX_IPSR_MSEL(IP4_27_24, PWM3_A, SEL_PWM3_0), 557 PINMUX_IPSR_MSEL(IP4_27_24, FSO_TOE_N_B, SEL_RFSO_1), 558 559 PINMUX_IPSR_GPSR(IP4_31_28, VI0_FIELD), 560 PINMUX_IPSR_GPSR(IP4_31_28, HRX2), 561 PINMUX_IPSR_MSEL(IP4_31_28, PWM4_A, SEL_PWM4_0), 562 PINMUX_IPSR_GPSR(IP4_31_28, CS1_N), 563 PINMUX_IPSR_GPSR(IP4_31_28, FSCLKST2_N_A), 564 565 /* IPSR5 */ 566 PINMUX_IPSR_GPSR(IP5_3_0, VI1_CLK), 567 PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD), 568 PINMUX_IPSR_GPSR(IP5_3_0, CS0_N), 569 570 PINMUX_IPSR_GPSR(IP5_7_4, VI1_CLKENB), 571 PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD), 572 PINMUX_IPSR_GPSR(IP5_7_4, D0), 573 574 PINMUX_IPSR_GPSR(IP5_11_8, VI1_HSYNC_N), 575 PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK), 576 PINMUX_IPSR_GPSR(IP5_11_8, D1), 577 578 PINMUX_IPSR_GPSR(IP5_15_12, VI1_VSYNC_N), 579 PINMUX_IPSR_GPSR(IP5_15_12, MSIOF1_SYNC), 580 PINMUX_IPSR_GPSR(IP5_15_12, D2), 581 582 PINMUX_IPSR_GPSR(IP5_19_16, VI1_DATA0), 583 PINMUX_IPSR_GPSR(IP5_19_16, MSIOF1_SS1), 584 PINMUX_IPSR_GPSR(IP5_19_16, D3), 585 586 PINMUX_IPSR_GPSR(IP5_23_20, VI1_DATA1), 587 PINMUX_IPSR_GPSR(IP5_23_20, MSIOF1_SS2), 588 PINMUX_IPSR_GPSR(IP5_23_20, D4), 589 PINMUX_IPSR_GPSR(IP5_23_20, MMC_CMD), 590 591 PINMUX_IPSR_GPSR(IP5_27_24, VI1_DATA2), 592 PINMUX_IPSR_MSEL(IP5_27_24, CANFD0_TX_B, SEL_CANFD0_1), 593 PINMUX_IPSR_GPSR(IP5_27_24, D5), 594 PINMUX_IPSR_GPSR(IP5_27_24, MMC_D0), 595 596 PINMUX_IPSR_GPSR(IP5_31_28, VI1_DATA3), 597 PINMUX_IPSR_MSEL(IP5_31_28, CANFD0_RX_B, SEL_CANFD0_1), 598 PINMUX_IPSR_GPSR(IP5_31_28, D6), 599 PINMUX_IPSR_GPSR(IP5_31_28, MMC_D1), 600 601 /* IPSR6 */ 602 PINMUX_IPSR_GPSR(IP6_3_0, VI1_DATA4), 603 PINMUX_IPSR_MSEL(IP6_3_0, CANFD_CLK_B, SEL_CANFD0_1), 604 PINMUX_IPSR_GPSR(IP6_3_0, D7), 605 PINMUX_IPSR_GPSR(IP6_3_0, MMC_D2), 606 607 PINMUX_IPSR_GPSR(IP6_7_4, VI1_DATA5), 608 PINMUX_IPSR_GPSR(IP6_7_4, SCK4), 609 PINMUX_IPSR_GPSR(IP6_7_4, D8), 610 PINMUX_IPSR_GPSR(IP6_7_4, MMC_D3), 611 612 PINMUX_IPSR_GPSR(IP6_11_8, VI1_DATA6), 613 PINMUX_IPSR_GPSR(IP6_11_8, RX4), 614 PINMUX_IPSR_GPSR(IP6_11_8, D9), 615 PINMUX_IPSR_GPSR(IP6_11_8, MMC_CLK), 616 617 PINMUX_IPSR_GPSR(IP6_15_12, VI1_DATA7), 618 PINMUX_IPSR_GPSR(IP6_15_12, TX4), 619 PINMUX_IPSR_GPSR(IP6_15_12, D10), 620 PINMUX_IPSR_GPSR(IP6_15_12, MMC_D4), 621 622 PINMUX_IPSR_GPSR(IP6_19_16, VI1_DATA8), 623 PINMUX_IPSR_GPSR(IP6_19_16, CTS4_N), 624 PINMUX_IPSR_GPSR(IP6_19_16, D11), 625 PINMUX_IPSR_GPSR(IP6_19_16, MMC_D5), 626 627 PINMUX_IPSR_GPSR(IP6_23_20, VI1_DATA9), 628 PINMUX_IPSR_GPSR(IP6_23_20, RTS4_N), 629 PINMUX_IPSR_GPSR(IP6_23_20, D12), 630 PINMUX_IPSR_GPSR(IP6_23_20, MMC_D6), 631 PINMUX_IPSR_MSEL(IP6_23_20, SCL3_B, SEL_I2C3_1), 632 633 PINMUX_IPSR_GPSR(IP6_27_24, VI1_DATA10), 634 PINMUX_IPSR_GPSR(IP6_27_24, D13), 635 PINMUX_IPSR_GPSR(IP6_27_24, MMC_D7), 636 PINMUX_IPSR_MSEL(IP6_27_24, SDA3_B, SEL_I2C3_1), 637 638 PINMUX_IPSR_GPSR(IP6_31_28, VI1_DATA11), 639 PINMUX_IPSR_GPSR(IP6_31_28, SCL4), 640 PINMUX_IPSR_GPSR(IP6_31_28, IRQ4), 641 PINMUX_IPSR_GPSR(IP6_31_28, D14), 642 643 /* IPSR7 */ 644 PINMUX_IPSR_GPSR(IP7_3_0, VI1_FIELD), 645 PINMUX_IPSR_GPSR(IP7_3_0, SDA4), 646 PINMUX_IPSR_GPSR(IP7_3_0, IRQ5), 647 PINMUX_IPSR_GPSR(IP7_3_0, D15), 648 649 PINMUX_IPSR_GPSR(IP7_7_4, SCL0), 650 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR0), 651 PINMUX_IPSR_GPSR(IP7_7_4, TPU0TO0), 652 PINMUX_IPSR_GPSR(IP7_7_4, CLKOUT), 653 PINMUX_IPSR_GPSR(IP7_7_4, MSIOF0_RXD), 654 655 PINMUX_IPSR_GPSR(IP7_11_8, SDA0), 656 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR1), 657 PINMUX_IPSR_GPSR(IP7_11_8, TPU0TO1), 658 PINMUX_IPSR_GPSR(IP7_11_8, BS_N), 659 PINMUX_IPSR_GPSR(IP7_11_8, SCK0), 660 PINMUX_IPSR_GPSR(IP7_11_8, MSIOF0_TXD), 661 662 PINMUX_IPSR_GPSR(IP7_15_12, SCL1), 663 PINMUX_IPSR_GPSR(IP7_15_12, DU_DG0), 664 PINMUX_IPSR_GPSR(IP7_15_12, TPU0TO2), 665 PINMUX_IPSR_GPSR(IP7_15_12, RD_N), 666 PINMUX_IPSR_GPSR(IP7_15_12, CTS0_N), 667 PINMUX_IPSR_GPSR(IP7_15_12, MSIOF0_SCK), 668 669 PINMUX_IPSR_GPSR(IP7_19_16, SDA1), 670 PINMUX_IPSR_GPSR(IP7_19_16, DU_DG1), 671 PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3), 672 PINMUX_IPSR_GPSR(IP7_19_16, WE0_N), 673 PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N), 674 PINMUX_IPSR_GPSR(IP7_19_16, MSIOF0_SYNC), 675 676 PINMUX_IPSR_GPSR(IP7_23_20, SCL2), 677 PINMUX_IPSR_GPSR(IP7_23_20, DU_DB0), 678 PINMUX_IPSR_MSEL(IP7_23_20, TCLK1_A, SEL_TMU_0), 679 PINMUX_IPSR_GPSR(IP7_23_20, WE1_N), 680 PINMUX_IPSR_GPSR(IP7_23_20, RX0), 681 PINMUX_IPSR_GPSR(IP7_23_20, MSIOF0_SS1), 682 683 PINMUX_IPSR_GPSR(IP7_27_24, SDA2), 684 PINMUX_IPSR_GPSR(IP7_27_24, DU_DB1), 685 PINMUX_IPSR_MSEL(IP7_27_24, TCLK2_A, SEL_TMU_0), 686 PINMUX_IPSR_GPSR(IP7_27_24, EX_WAIT0), 687 PINMUX_IPSR_GPSR(IP7_27_24, TX0), 688 PINMUX_IPSR_GPSR(IP7_27_24, MSIOF0_SS2), 689 690 PINMUX_IPSR_GPSR(IP7_31_28, AVB0_AVTP_CAPTURE), 691 PINMUX_IPSR_GPSR(IP7_31_28, FSCLKST2_N_B), 692 693 /* IPSR8 */ 694 PINMUX_IPSR_MSEL(IP8_3_0, CANFD0_TX_A, SEL_CANFD0_0), 695 PINMUX_IPSR_GPSR(IP8_3_0, FXR_TXDA), 696 PINMUX_IPSR_MSEL(IP8_3_0, PWM0_B, SEL_PWM0_1), 697 PINMUX_IPSR_GPSR(IP8_3_0, DU_DISP), 698 PINMUX_IPSR_GPSR(IP8_3_0, FSCLKST2_N_C), 699 700 PINMUX_IPSR_MSEL(IP8_7_4, CANFD0_RX_A, SEL_CANFD0_0), 701 PINMUX_IPSR_GPSR(IP8_7_4, RXDA_EXTFXR), 702 PINMUX_IPSR_MSEL(IP8_7_4, PWM1_B, SEL_PWM1_1), 703 PINMUX_IPSR_GPSR(IP8_7_4, DU_CDE), 704 705 PINMUX_IPSR_GPSR(IP8_11_8, CANFD1_TX), 706 PINMUX_IPSR_GPSR(IP8_11_8, FXR_TXDB), 707 PINMUX_IPSR_MSEL(IP8_11_8, PWM2_B, SEL_PWM2_1), 708 PINMUX_IPSR_MSEL(IP8_11_8, TCLK1_B, SEL_TMU_1), 709 PINMUX_IPSR_MSEL(IP8_11_8, TX1_B, SEL_SCIF1_1), 710 711 PINMUX_IPSR_GPSR(IP8_15_12, CANFD1_RX), 712 PINMUX_IPSR_GPSR(IP8_15_12, RXDB_EXTFXR), 713 PINMUX_IPSR_MSEL(IP8_15_12, PWM3_B, SEL_PWM3_1), 714 PINMUX_IPSR_MSEL(IP8_15_12, TCLK2_B, SEL_TMU_1), 715 PINMUX_IPSR_MSEL(IP8_15_12, RX1_B, SEL_SCIF1_1), 716 717 PINMUX_IPSR_MSEL(IP8_19_16, CANFD_CLK_A, SEL_CANFD0_0), 718 PINMUX_IPSR_GPSR(IP8_19_16, CLK_EXTFXR), 719 PINMUX_IPSR_MSEL(IP8_19_16, PWM4_B, SEL_PWM4_1), 720 PINMUX_IPSR_MSEL(IP8_19_16, SPEEDIN_B, SEL_RSP_1), 721 PINMUX_IPSR_MSEL(IP8_19_16, SCIF_CLK_B, SEL_HSCIF0_1), 722 723 PINMUX_IPSR_GPSR(IP8_23_20, DIGRF_CLKIN), 724 PINMUX_IPSR_GPSR(IP8_23_20, DIGRF_CLKEN_IN), 725 726 PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKOUT), 727 PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKEN_OUT), 728 }; 729 730 /* 731 * Pins not associated with a GPIO port. 732 */ 733 enum { 734 GP_ASSIGN_LAST(), 735 NOGP_ALL(), 736 }; 737 738 static const struct sh_pfc_pin pinmux_pins[] = { 739 PINMUX_GPIO_GP_ALL(), 740 PINMUX_NOGP_ALL(), 741 }; 742 743 /* - AVB0 ------------------------------------------------------------------- */ 744 static const unsigned int avb0_link_pins[] = { 745 /* AVB0_LINK */ 746 RCAR_GP_PIN(1, 18), 747 }; 748 static const unsigned int avb0_link_mux[] = { 749 AVB0_LINK_MARK, 750 }; 751 static const unsigned int avb0_magic_pins[] = { 752 /* AVB0_MAGIC */ 753 RCAR_GP_PIN(1, 16), 754 }; 755 static const unsigned int avb0_magic_mux[] = { 756 AVB0_MAGIC_MARK, 757 }; 758 static const unsigned int avb0_phy_int_pins[] = { 759 /* AVB0_PHY_INT */ 760 RCAR_GP_PIN(1, 17), 761 }; 762 static const unsigned int avb0_phy_int_mux[] = { 763 AVB0_PHY_INT_MARK, 764 }; 765 static const unsigned int avb0_mdio_pins[] = { 766 /* AVB0_MDC, AVB0_MDIO */ 767 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), 768 }; 769 static const unsigned int avb0_mdio_mux[] = { 770 AVB0_MDC_MARK, AVB0_MDIO_MARK, 771 }; 772 static const unsigned int avb0_rgmii_pins[] = { 773 /* 774 * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3, 775 * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3 776 */ 777 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), 778 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10), 779 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12), 780 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2), 781 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4), 782 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), 783 }; 784 static const unsigned int avb0_rgmii_mux[] = { 785 AVB0_TX_CTL_MARK, AVB0_TXC_MARK, 786 AVB0_TD0_MARK, AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK, 787 AVB0_RX_CTL_MARK, AVB0_RXC_MARK, 788 AVB0_RD0_MARK, AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK, 789 }; 790 static const unsigned int avb0_txcrefclk_pins[] = { 791 /* AVB0_TXCREFCLK */ 792 RCAR_GP_PIN(1, 13), 793 }; 794 static const unsigned int avb0_txcrefclk_mux[] = { 795 AVB0_TXCREFCLK_MARK, 796 }; 797 static const unsigned int avb0_avtp_pps_pins[] = { 798 /* AVB0_AVTP_PPS */ 799 RCAR_GP_PIN(2, 6), 800 }; 801 static const unsigned int avb0_avtp_pps_mux[] = { 802 AVB0_AVTP_PPS_MARK, 803 }; 804 static const unsigned int avb0_avtp_capture_pins[] = { 805 /* AVB0_AVTP_CAPTURE */ 806 RCAR_GP_PIN(1, 20), 807 }; 808 static const unsigned int avb0_avtp_capture_mux[] = { 809 AVB0_AVTP_CAPTURE_MARK, 810 }; 811 static const unsigned int avb0_avtp_match_pins[] = { 812 /* AVB0_AVTP_MATCH */ 813 RCAR_GP_PIN(1, 19), 814 }; 815 static const unsigned int avb0_avtp_match_mux[] = { 816 AVB0_AVTP_MATCH_MARK, 817 }; 818 819 /* - CANFD Clock ------------------------------------------------------------ */ 820 static const unsigned int canfd_clk_a_pins[] = { 821 /* CANFD_CLK */ 822 RCAR_GP_PIN(1, 25), 823 }; 824 static const unsigned int canfd_clk_a_mux[] = { 825 CANFD_CLK_A_MARK, 826 }; 827 static const unsigned int canfd_clk_b_pins[] = { 828 /* CANFD_CLK */ 829 RCAR_GP_PIN(3, 8), 830 }; 831 static const unsigned int canfd_clk_b_mux[] = { 832 CANFD_CLK_B_MARK, 833 }; 834 835 /* - CANFD0 ----------------------------------------------------------------- */ 836 static const unsigned int canfd0_data_a_pins[] = { 837 /* TX, RX */ 838 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), 839 }; 840 static const unsigned int canfd0_data_a_mux[] = { 841 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK, 842 }; 843 static const unsigned int canfd0_data_b_pins[] = { 844 /* TX, RX */ 845 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 846 }; 847 static const unsigned int canfd0_data_b_mux[] = { 848 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK, 849 }; 850 851 /* - CANFD1 ----------------------------------------------------------------- */ 852 static const unsigned int canfd1_data_pins[] = { 853 /* TX, RX */ 854 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 855 }; 856 static const unsigned int canfd1_data_mux[] = { 857 CANFD1_TX_MARK, CANFD1_RX_MARK, 858 }; 859 860 /* - DU --------------------------------------------------------------------- */ 861 static const unsigned int du_rgb666_pins[] = { 862 /* R[7:2], G[7:2], B[7:2] */ 863 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), 864 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0), 865 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9), 866 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), 867 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15), 868 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12), 869 }; 870 static const unsigned int du_rgb666_mux[] = { 871 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, 872 DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK, 873 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, 874 DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK, 875 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, 876 DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK, 877 }; 878 static const unsigned int du_clk_out_pins[] = { 879 /* DOTCLKOUT */ 880 RCAR_GP_PIN(0, 18), 881 }; 882 static const unsigned int du_clk_out_mux[] = { 883 DU_DOTCLKOUT_MARK, 884 }; 885 static const unsigned int du_sync_pins[] = { 886 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ 887 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), 888 }; 889 static const unsigned int du_sync_mux[] = { 890 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK 891 }; 892 static const unsigned int du_oddf_pins[] = { 893 /* EXODDF/ODDF/DISP/CDE */ 894 RCAR_GP_PIN(0, 21), 895 }; 896 static const unsigned int du_oddf_mux[] = { 897 DU_EXODDF_DU_ODDF_DISP_CDE_MARK, 898 }; 899 static const unsigned int du_cde_pins[] = { 900 /* CDE */ 901 RCAR_GP_PIN(1, 22), 902 }; 903 static const unsigned int du_cde_mux[] = { 904 DU_CDE_MARK, 905 }; 906 static const unsigned int du_disp_pins[] = { 907 /* DISP */ 908 RCAR_GP_PIN(1, 21), 909 }; 910 static const unsigned int du_disp_mux[] = { 911 DU_DISP_MARK, 912 }; 913 914 /* - HSCIF0 ----------------------------------------------------------------- */ 915 static const unsigned int hscif0_data_pins[] = { 916 /* HRX, HTX */ 917 RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 3), 918 }; 919 static const unsigned int hscif0_data_mux[] = { 920 HRX0_MARK, HTX0_MARK, 921 }; 922 static const unsigned int hscif0_clk_pins[] = { 923 /* HSCK */ 924 RCAR_GP_PIN(0, 0), 925 }; 926 static const unsigned int hscif0_clk_mux[] = { 927 HSCK0_MARK, 928 }; 929 static const unsigned int hscif0_ctrl_pins[] = { 930 /* HRTS#, HCTS# */ 931 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2), 932 }; 933 static const unsigned int hscif0_ctrl_mux[] = { 934 HRTS0_N_MARK, HCTS0_N_MARK, 935 }; 936 937 /* - HSCIF1 ----------------------------------------------------------------- */ 938 static const unsigned int hscif1_data_pins[] = { 939 /* HRX, HTX */ 940 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10), 941 }; 942 static const unsigned int hscif1_data_mux[] = { 943 HRX1_MARK, HTX1_MARK, 944 }; 945 static const unsigned int hscif1_clk_pins[] = { 946 /* HSCK */ 947 RCAR_GP_PIN(2, 7), 948 }; 949 static const unsigned int hscif1_clk_mux[] = { 950 HSCK1_MARK, 951 }; 952 static const unsigned int hscif1_ctrl_pins[] = { 953 /* HRTS#, HCTS# */ 954 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 955 }; 956 static const unsigned int hscif1_ctrl_mux[] = { 957 HRTS1_N_MARK, HCTS1_N_MARK, 958 }; 959 960 /* - HSCIF2 ----------------------------------------------------------------- */ 961 static const unsigned int hscif2_data_pins[] = { 962 /* HRX, HTX */ 963 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15), 964 }; 965 static const unsigned int hscif2_data_mux[] = { 966 HRX2_MARK, HTX2_MARK, 967 }; 968 static const unsigned int hscif2_clk_pins[] = { 969 /* HSCK */ 970 RCAR_GP_PIN(2, 12), 971 }; 972 static const unsigned int hscif2_clk_mux[] = { 973 HSCK2_MARK, 974 }; 975 static const unsigned int hscif2_ctrl_pins[] = { 976 /* HRTS#, HCTS# */ 977 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), 978 }; 979 static const unsigned int hscif2_ctrl_mux[] = { 980 HRTS2_N_MARK, HCTS2_N_MARK, 981 }; 982 983 /* - HSCIF3 ----------------------------------------------------------------- */ 984 static const unsigned int hscif3_data_pins[] = { 985 /* HRX, HTX */ 986 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), 987 }; 988 static const unsigned int hscif3_data_mux[] = { 989 HRX3_MARK, HTX3_MARK, 990 }; 991 static const unsigned int hscif3_clk_pins[] = { 992 /* HSCK */ 993 RCAR_GP_PIN(2, 0), 994 }; 995 static const unsigned int hscif3_clk_mux[] = { 996 HSCK3_MARK, 997 }; 998 static const unsigned int hscif3_ctrl_pins[] = { 999 /* HRTS#, HCTS# */ 1000 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1), 1001 }; 1002 static const unsigned int hscif3_ctrl_mux[] = { 1003 HRTS3_N_MARK, HCTS3_N_MARK, 1004 }; 1005 1006 /* - I2C0 ------------------------------------------------------------------- */ 1007 static const unsigned int i2c0_pins[] = { 1008 /* SDA, SCL */ 1009 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0), 1010 }; 1011 static const unsigned int i2c0_mux[] = { 1012 SDA0_MARK, SCL0_MARK, 1013 }; 1014 1015 /* - I2C1 ------------------------------------------------------------------- */ 1016 static const unsigned int i2c1_pins[] = { 1017 /* SDA, SCL */ 1018 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2), 1019 }; 1020 static const unsigned int i2c1_mux[] = { 1021 SDA1_MARK, SCL1_MARK, 1022 }; 1023 1024 /* - I2C2 ------------------------------------------------------------------- */ 1025 static const unsigned int i2c2_pins[] = { 1026 /* SDA, SCL */ 1027 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4), 1028 }; 1029 static const unsigned int i2c2_mux[] = { 1030 SDA2_MARK, SCL2_MARK, 1031 }; 1032 1033 /* - I2C3 ------------------------------------------------------------------- */ 1034 static const unsigned int i2c3_a_pins[] = { 1035 /* SDA, SCL */ 1036 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 1037 }; 1038 static const unsigned int i2c3_a_mux[] = { 1039 SDA3_A_MARK, SCL3_A_MARK, 1040 }; 1041 static const unsigned int i2c3_b_pins[] = { 1042 /* SDA, SCL */ 1043 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13), 1044 }; 1045 static const unsigned int i2c3_b_mux[] = { 1046 SDA3_B_MARK, SCL3_B_MARK, 1047 }; 1048 1049 /* - I2C4 ------------------------------------------------------------------- */ 1050 static const unsigned int i2c4_pins[] = { 1051 /* SDA, SCL */ 1052 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15), 1053 }; 1054 static const unsigned int i2c4_mux[] = { 1055 SDA4_MARK, SCL4_MARK, 1056 }; 1057 1058 /* - INTC-EX ---------------------------------------------------------------- */ 1059 static const unsigned int intc_ex_irq0_pins[] = { 1060 /* IRQ0 */ 1061 RCAR_GP_PIN(1, 0), 1062 }; 1063 static const unsigned int intc_ex_irq0_mux[] = { 1064 IRQ0_MARK, 1065 }; 1066 static const unsigned int intc_ex_irq1_pins[] = { 1067 /* IRQ1 */ 1068 RCAR_GP_PIN(0, 11), 1069 }; 1070 static const unsigned int intc_ex_irq1_mux[] = { 1071 IRQ1_MARK, 1072 }; 1073 static const unsigned int intc_ex_irq2_pins[] = { 1074 /* IRQ2 */ 1075 RCAR_GP_PIN(0, 12), 1076 }; 1077 static const unsigned int intc_ex_irq2_mux[] = { 1078 IRQ2_MARK, 1079 }; 1080 static const unsigned int intc_ex_irq3_pins[] = { 1081 /* IRQ3 */ 1082 RCAR_GP_PIN(0, 19), 1083 }; 1084 static const unsigned int intc_ex_irq3_mux[] = { 1085 IRQ3_MARK, 1086 }; 1087 static const unsigned int intc_ex_irq4_pins[] = { 1088 /* IRQ4 */ 1089 RCAR_GP_PIN(3, 15), 1090 }; 1091 static const unsigned int intc_ex_irq4_mux[] = { 1092 IRQ4_MARK, 1093 }; 1094 static const unsigned int intc_ex_irq5_pins[] = { 1095 /* IRQ5 */ 1096 RCAR_GP_PIN(3, 16), 1097 }; 1098 static const unsigned int intc_ex_irq5_mux[] = { 1099 IRQ5_MARK, 1100 }; 1101 1102 /* - MMC -------------------------------------------------------------------- */ 1103 static const unsigned int mmc_data_pins[] = { 1104 /* D[0:7] */ 1105 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 1106 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 1107 RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), 1108 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), 1109 }; 1110 static const unsigned int mmc_data_mux[] = { 1111 MMC_D0_MARK, MMC_D1_MARK, 1112 MMC_D2_MARK, MMC_D3_MARK, 1113 MMC_D4_MARK, MMC_D5_MARK, 1114 MMC_D6_MARK, MMC_D7_MARK, 1115 }; 1116 static const unsigned int mmc_ctrl_pins[] = { 1117 /* CLK, CMD */ 1118 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 5), 1119 }; 1120 static const unsigned int mmc_ctrl_mux[] = { 1121 MMC_CLK_MARK, MMC_CMD_MARK, 1122 }; 1123 1124 /* - MSIOF0 ----------------------------------------------------------------- */ 1125 static const unsigned int msiof0_clk_pins[] = { 1126 /* SCK */ 1127 RCAR_GP_PIN(4, 2), 1128 }; 1129 static const unsigned int msiof0_clk_mux[] = { 1130 MSIOF0_SCK_MARK, 1131 }; 1132 static const unsigned int msiof0_sync_pins[] = { 1133 /* SYNC */ 1134 RCAR_GP_PIN(4, 3), 1135 }; 1136 static const unsigned int msiof0_sync_mux[] = { 1137 MSIOF0_SYNC_MARK, 1138 }; 1139 static const unsigned int msiof0_ss1_pins[] = { 1140 /* SS1 */ 1141 RCAR_GP_PIN(4, 4), 1142 }; 1143 static const unsigned int msiof0_ss1_mux[] = { 1144 MSIOF0_SS1_MARK, 1145 }; 1146 static const unsigned int msiof0_ss2_pins[] = { 1147 /* SS2 */ 1148 RCAR_GP_PIN(4, 5), 1149 }; 1150 static const unsigned int msiof0_ss2_mux[] = { 1151 MSIOF0_SS2_MARK, 1152 }; 1153 static const unsigned int msiof0_txd_pins[] = { 1154 /* TXD */ 1155 RCAR_GP_PIN(4, 1), 1156 }; 1157 static const unsigned int msiof0_txd_mux[] = { 1158 MSIOF0_TXD_MARK, 1159 }; 1160 static const unsigned int msiof0_rxd_pins[] = { 1161 /* RXD */ 1162 RCAR_GP_PIN(4, 0), 1163 }; 1164 static const unsigned int msiof0_rxd_mux[] = { 1165 MSIOF0_RXD_MARK, 1166 }; 1167 1168 /* - MSIOF1 ----------------------------------------------------------------- */ 1169 static const unsigned int msiof1_clk_pins[] = { 1170 /* SCK */ 1171 RCAR_GP_PIN(3, 2), 1172 }; 1173 static const unsigned int msiof1_clk_mux[] = { 1174 MSIOF1_SCK_MARK, 1175 }; 1176 static const unsigned int msiof1_sync_pins[] = { 1177 /* SYNC */ 1178 RCAR_GP_PIN(3, 3), 1179 }; 1180 static const unsigned int msiof1_sync_mux[] = { 1181 MSIOF1_SYNC_MARK, 1182 }; 1183 static const unsigned int msiof1_ss1_pins[] = { 1184 /* SS1 */ 1185 RCAR_GP_PIN(3, 4), 1186 }; 1187 static const unsigned int msiof1_ss1_mux[] = { 1188 MSIOF1_SS1_MARK, 1189 }; 1190 static const unsigned int msiof1_ss2_pins[] = { 1191 /* SS2 */ 1192 RCAR_GP_PIN(3, 5), 1193 }; 1194 static const unsigned int msiof1_ss2_mux[] = { 1195 MSIOF1_SS2_MARK, 1196 }; 1197 static const unsigned int msiof1_txd_pins[] = { 1198 /* TXD */ 1199 RCAR_GP_PIN(3, 1), 1200 }; 1201 static const unsigned int msiof1_txd_mux[] = { 1202 MSIOF1_TXD_MARK, 1203 }; 1204 static const unsigned int msiof1_rxd_pins[] = { 1205 /* RXD */ 1206 RCAR_GP_PIN(3, 0), 1207 }; 1208 static const unsigned int msiof1_rxd_mux[] = { 1209 MSIOF1_RXD_MARK, 1210 }; 1211 1212 /* - MSIOF2 ----------------------------------------------------------------- */ 1213 static const unsigned int msiof2_clk_pins[] = { 1214 /* SCK */ 1215 RCAR_GP_PIN(2, 0), 1216 }; 1217 static const unsigned int msiof2_clk_mux[] = { 1218 MSIOF2_SCK_MARK, 1219 }; 1220 static const unsigned int msiof2_sync_pins[] = { 1221 /* SYNC */ 1222 RCAR_GP_PIN(2, 3), 1223 }; 1224 static const unsigned int msiof2_sync_mux[] = { 1225 MSIOF2_SYNC_MARK, 1226 }; 1227 static const unsigned int msiof2_ss1_pins[] = { 1228 /* SS1 */ 1229 RCAR_GP_PIN(2, 4), 1230 }; 1231 static const unsigned int msiof2_ss1_mux[] = { 1232 MSIOF2_SS1_MARK, 1233 }; 1234 static const unsigned int msiof2_ss2_pins[] = { 1235 /* SS2 */ 1236 RCAR_GP_PIN(2, 5), 1237 }; 1238 static const unsigned int msiof2_ss2_mux[] = { 1239 MSIOF2_SS2_MARK, 1240 }; 1241 static const unsigned int msiof2_txd_pins[] = { 1242 /* TXD */ 1243 RCAR_GP_PIN(2, 2), 1244 }; 1245 static const unsigned int msiof2_txd_mux[] = { 1246 MSIOF2_TXD_MARK, 1247 }; 1248 static const unsigned int msiof2_rxd_pins[] = { 1249 /* RXD */ 1250 RCAR_GP_PIN(2, 1), 1251 }; 1252 static const unsigned int msiof2_rxd_mux[] = { 1253 MSIOF2_RXD_MARK, 1254 }; 1255 1256 /* - MSIOF3 ----------------------------------------------------------------- */ 1257 static const unsigned int msiof3_clk_pins[] = { 1258 /* SCK */ 1259 RCAR_GP_PIN(0, 20), 1260 }; 1261 static const unsigned int msiof3_clk_mux[] = { 1262 MSIOF3_SCK_MARK, 1263 }; 1264 static const unsigned int msiof3_sync_pins[] = { 1265 /* SYNC */ 1266 RCAR_GP_PIN(0, 21), 1267 }; 1268 static const unsigned int msiof3_sync_mux[] = { 1269 MSIOF3_SYNC_MARK, 1270 }; 1271 static const unsigned int msiof3_ss1_pins[] = { 1272 /* SS1 */ 1273 RCAR_GP_PIN(0, 6), 1274 }; 1275 static const unsigned int msiof3_ss1_mux[] = { 1276 MSIOF3_SS1_MARK, 1277 }; 1278 static const unsigned int msiof3_ss2_pins[] = { 1279 /* SS2 */ 1280 RCAR_GP_PIN(0, 7), 1281 }; 1282 static const unsigned int msiof3_ss2_mux[] = { 1283 MSIOF3_SS2_MARK, 1284 }; 1285 static const unsigned int msiof3_txd_pins[] = { 1286 /* TXD */ 1287 RCAR_GP_PIN(0, 5), 1288 }; 1289 static const unsigned int msiof3_txd_mux[] = { 1290 MSIOF3_TXD_MARK, 1291 }; 1292 static const unsigned int msiof3_rxd_pins[] = { 1293 /* RXD */ 1294 RCAR_GP_PIN(0, 4), 1295 }; 1296 static const unsigned int msiof3_rxd_mux[] = { 1297 MSIOF3_RXD_MARK, 1298 }; 1299 1300 /* - PWM0 ------------------------------------------------------------------- */ 1301 static const unsigned int pwm0_a_pins[] = { 1302 RCAR_GP_PIN(2, 12), 1303 }; 1304 static const unsigned int pwm0_a_mux[] = { 1305 PWM0_A_MARK, 1306 }; 1307 static const unsigned int pwm0_b_pins[] = { 1308 RCAR_GP_PIN(1, 21), 1309 }; 1310 static const unsigned int pwm0_b_mux[] = { 1311 PWM0_B_MARK, 1312 }; 1313 1314 /* - PWM1 ------------------------------------------------------------------- */ 1315 static const unsigned int pwm1_a_pins[] = { 1316 RCAR_GP_PIN(2, 13), 1317 }; 1318 static const unsigned int pwm1_a_mux[] = { 1319 PWM1_A_MARK, 1320 }; 1321 static const unsigned int pwm1_b_pins[] = { 1322 RCAR_GP_PIN(1, 22), 1323 }; 1324 static const unsigned int pwm1_b_mux[] = { 1325 PWM1_B_MARK, 1326 }; 1327 1328 /* - PWM2 ------------------------------------------------------------------- */ 1329 static const unsigned int pwm2_a_pins[] = { 1330 RCAR_GP_PIN(2, 14), 1331 }; 1332 static const unsigned int pwm2_a_mux[] = { 1333 PWM2_A_MARK, 1334 }; 1335 static const unsigned int pwm2_b_pins[] = { 1336 RCAR_GP_PIN(1, 23), 1337 }; 1338 static const unsigned int pwm2_b_mux[] = { 1339 PWM2_B_MARK, 1340 }; 1341 1342 /* - PWM3 ------------------------------------------------------------------- */ 1343 static const unsigned int pwm3_a_pins[] = { 1344 RCAR_GP_PIN(2, 15), 1345 }; 1346 static const unsigned int pwm3_a_mux[] = { 1347 PWM3_A_MARK, 1348 }; 1349 static const unsigned int pwm3_b_pins[] = { 1350 RCAR_GP_PIN(1, 24), 1351 }; 1352 static const unsigned int pwm3_b_mux[] = { 1353 PWM3_B_MARK, 1354 }; 1355 1356 /* - PWM4 ------------------------------------------------------------------- */ 1357 static const unsigned int pwm4_a_pins[] = { 1358 RCAR_GP_PIN(2, 16), 1359 }; 1360 static const unsigned int pwm4_a_mux[] = { 1361 PWM4_A_MARK, 1362 }; 1363 static const unsigned int pwm4_b_pins[] = { 1364 RCAR_GP_PIN(1, 25), 1365 }; 1366 static const unsigned int pwm4_b_mux[] = { 1367 PWM4_B_MARK, 1368 }; 1369 1370 /* - QSPI0 ------------------------------------------------------------------ */ 1371 static const unsigned int qspi0_ctrl_pins[] = { 1372 /* SPCLK, SSL */ 1373 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 5), 1374 }; 1375 static const unsigned int qspi0_ctrl_mux[] = { 1376 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, 1377 }; 1378 1379 /* - QSPI1 ------------------------------------------------------------------ */ 1380 static const unsigned int qspi1_ctrl_pins[] = { 1381 /* SPCLK, SSL */ 1382 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 11), 1383 }; 1384 static const unsigned int qspi1_ctrl_mux[] = { 1385 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, 1386 }; 1387 1388 /* - RPC -------------------------------------------------------------------- */ 1389 static const unsigned int rpc_clk_pins[] = { 1390 /* Octal-SPI flash: C/SCLK */ 1391 /* HyperFlash: CK, CK# */ 1392 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6), 1393 }; 1394 static const unsigned int rpc_clk_mux[] = { 1395 QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK, 1396 }; 1397 static const unsigned int rpc_ctrl_pins[] = { 1398 /* Octal-SPI flash: S#/CS, DQS */ 1399 /* HyperFlash: CS#, RDS */ 1400 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11), 1401 }; 1402 static const unsigned int rpc_ctrl_mux[] = { 1403 QSPI0_SSL_MARK, QSPI1_SSL_MARK, 1404 }; 1405 static const unsigned int rpc_data_pins[] = { 1406 /* DQ[0:7] */ 1407 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 1408 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), 1409 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), 1410 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), 1411 }; 1412 static const unsigned int rpc_data_mux[] = { 1413 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, 1414 QSPI0_IO2_MARK, QSPI0_IO3_MARK, 1415 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, 1416 QSPI1_IO2_MARK, QSPI1_IO3_MARK, 1417 }; 1418 static const unsigned int rpc_reset_pins[] = { 1419 /* RPC_RESET# */ 1420 RCAR_GP_PIN(5, 12), 1421 }; 1422 static const unsigned int rpc_reset_mux[] = { 1423 RPC_RESET_N_MARK, 1424 }; 1425 static const unsigned int rpc_int_pins[] = { 1426 /* RPC_INT# */ 1427 RCAR_GP_PIN(5, 14), 1428 }; 1429 static const unsigned int rpc_int_mux[] = { 1430 RPC_INT_N_MARK, 1431 }; 1432 static const unsigned int rpc_wp_pins[] = { 1433 /* RPC_WP# */ 1434 RCAR_GP_PIN(5, 13), 1435 }; 1436 static const unsigned int rpc_wp_mux[] = { 1437 RPC_WP_N_MARK, 1438 }; 1439 1440 /* - SCIF Clock ------------------------------------------------------------- */ 1441 static const unsigned int scif_clk_a_pins[] = { 1442 /* SCIF_CLK */ 1443 RCAR_GP_PIN(0, 18), 1444 }; 1445 static const unsigned int scif_clk_a_mux[] = { 1446 SCIF_CLK_A_MARK, 1447 }; 1448 static const unsigned int scif_clk_b_pins[] = { 1449 /* SCIF_CLK */ 1450 RCAR_GP_PIN(1, 25), 1451 }; 1452 static const unsigned int scif_clk_b_mux[] = { 1453 SCIF_CLK_B_MARK, 1454 }; 1455 1456 /* - SCIF0 ------------------------------------------------------------------ */ 1457 static const unsigned int scif0_data_pins[] = { 1458 /* RX, TX */ 1459 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), 1460 }; 1461 static const unsigned int scif0_data_mux[] = { 1462 RX0_MARK, TX0_MARK, 1463 }; 1464 static const unsigned int scif0_clk_pins[] = { 1465 /* SCK */ 1466 RCAR_GP_PIN(4, 1), 1467 }; 1468 static const unsigned int scif0_clk_mux[] = { 1469 SCK0_MARK, 1470 }; 1471 static const unsigned int scif0_ctrl_pins[] = { 1472 /* RTS#, CTS# */ 1473 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2), 1474 }; 1475 static const unsigned int scif0_ctrl_mux[] = { 1476 RTS0_N_MARK, CTS0_N_MARK, 1477 }; 1478 1479 /* - SCIF1 ------------------------------------------------------------------ */ 1480 static const unsigned int scif1_data_a_pins[] = { 1481 /* RX, TX */ 1482 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 1483 }; 1484 static const unsigned int scif1_data_a_mux[] = { 1485 RX1_A_MARK, TX1_A_MARK, 1486 }; 1487 static const unsigned int scif1_clk_pins[] = { 1488 /* SCK */ 1489 RCAR_GP_PIN(2, 5), 1490 }; 1491 static const unsigned int scif1_clk_mux[] = { 1492 SCK1_MARK, 1493 }; 1494 static const unsigned int scif1_ctrl_pins[] = { 1495 /* RTS#, CTS# */ 1496 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10), 1497 }; 1498 static const unsigned int scif1_ctrl_mux[] = { 1499 RTS1_N_MARK, CTS1_N_MARK, 1500 }; 1501 static const unsigned int scif1_data_b_pins[] = { 1502 /* RX, TX */ 1503 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23), 1504 }; 1505 static const unsigned int scif1_data_b_mux[] = { 1506 RX1_B_MARK, TX1_B_MARK, 1507 }; 1508 1509 /* - SCIF3 ------------------------------------------------------------------ */ 1510 static const unsigned int scif3_data_pins[] = { 1511 /* RX, TX */ 1512 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), 1513 }; 1514 static const unsigned int scif3_data_mux[] = { 1515 RX3_MARK, TX3_MARK, 1516 }; 1517 static const unsigned int scif3_clk_pins[] = { 1518 /* SCK */ 1519 RCAR_GP_PIN(2, 0), 1520 }; 1521 static const unsigned int scif3_clk_mux[] = { 1522 SCK3_MARK, 1523 }; 1524 static const unsigned int scif3_ctrl_pins[] = { 1525 /* RTS#, CTS# */ 1526 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), 1527 }; 1528 static const unsigned int scif3_ctrl_mux[] = { 1529 RTS3_N_MARK, CTS3_N_MARK, 1530 }; 1531 1532 /* - SCIF4 ------------------------------------------------------------------ */ 1533 static const unsigned int scif4_data_pins[] = { 1534 /* RX, TX */ 1535 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 1536 }; 1537 static const unsigned int scif4_data_mux[] = { 1538 RX4_MARK, TX4_MARK, 1539 }; 1540 static const unsigned int scif4_clk_pins[] = { 1541 /* SCK */ 1542 RCAR_GP_PIN(3, 9), 1543 }; 1544 static const unsigned int scif4_clk_mux[] = { 1545 SCK4_MARK, 1546 }; 1547 static const unsigned int scif4_ctrl_pins[] = { 1548 /* RTS#, CTS# */ 1549 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), 1550 }; 1551 static const unsigned int scif4_ctrl_mux[] = { 1552 RTS4_N_MARK, CTS4_N_MARK, 1553 }; 1554 1555 /* - TMU -------------------------------------------------------------------- */ 1556 static const unsigned int tmu_tclk1_a_pins[] = { 1557 /* TCLK1 */ 1558 RCAR_GP_PIN(4, 4), 1559 }; 1560 static const unsigned int tmu_tclk1_a_mux[] = { 1561 TCLK1_A_MARK, 1562 }; 1563 static const unsigned int tmu_tclk1_b_pins[] = { 1564 /* TCLK1 */ 1565 RCAR_GP_PIN(1, 23), 1566 }; 1567 static const unsigned int tmu_tclk1_b_mux[] = { 1568 TCLK1_B_MARK, 1569 }; 1570 static const unsigned int tmu_tclk2_a_pins[] = { 1571 /* TCLK2 */ 1572 RCAR_GP_PIN(4, 5), 1573 }; 1574 static const unsigned int tmu_tclk2_a_mux[] = { 1575 TCLK2_A_MARK, 1576 }; 1577 static const unsigned int tmu_tclk2_b_pins[] = { 1578 /* TCLK2 */ 1579 RCAR_GP_PIN(1, 24), 1580 }; 1581 static const unsigned int tmu_tclk2_b_mux[] = { 1582 TCLK2_B_MARK, 1583 }; 1584 1585 /* - VIN0 ------------------------------------------------------------------- */ 1586 static const unsigned int vin0_data_pins[] = { 1587 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 1588 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 1589 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 1590 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), 1591 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), 1592 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), 1593 }; 1594 static const unsigned int vin0_data_mux[] = { 1595 VI0_DATA0_MARK, VI0_DATA1_MARK, 1596 VI0_DATA2_MARK, VI0_DATA3_MARK, 1597 VI0_DATA4_MARK, VI0_DATA5_MARK, 1598 VI0_DATA6_MARK, VI0_DATA7_MARK, 1599 VI0_DATA8_MARK, VI0_DATA9_MARK, 1600 VI0_DATA10_MARK, VI0_DATA11_MARK, 1601 }; 1602 static const unsigned int vin0_sync_pins[] = { 1603 /* HSYNC#, VSYNC# */ 1604 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), 1605 }; 1606 static const unsigned int vin0_sync_mux[] = { 1607 VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK, 1608 }; 1609 static const unsigned int vin0_field_pins[] = { 1610 /* FIELD */ 1611 RCAR_GP_PIN(2, 16), 1612 }; 1613 static const unsigned int vin0_field_mux[] = { 1614 VI0_FIELD_MARK, 1615 }; 1616 static const unsigned int vin0_clkenb_pins[] = { 1617 /* CLKENB */ 1618 RCAR_GP_PIN(2, 1), 1619 }; 1620 static const unsigned int vin0_clkenb_mux[] = { 1621 VI0_CLKENB_MARK, 1622 }; 1623 static const unsigned int vin0_clk_pins[] = { 1624 /* CLK */ 1625 RCAR_GP_PIN(2, 0), 1626 }; 1627 static const unsigned int vin0_clk_mux[] = { 1628 VI0_CLK_MARK, 1629 }; 1630 1631 /* - VIN1 ------------------------------------------------------------------- */ 1632 static const unsigned int vin1_data_pins[] = { 1633 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), 1634 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 1635 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 1636 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 1637 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), 1638 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), 1639 }; 1640 static const unsigned int vin1_data_mux[] = { 1641 VI1_DATA0_MARK, VI1_DATA1_MARK, 1642 VI1_DATA2_MARK, VI1_DATA3_MARK, 1643 VI1_DATA4_MARK, VI1_DATA5_MARK, 1644 VI1_DATA6_MARK, VI1_DATA7_MARK, 1645 VI1_DATA8_MARK, VI1_DATA9_MARK, 1646 VI1_DATA10_MARK, VI1_DATA11_MARK, 1647 }; 1648 static const unsigned int vin1_sync_pins[] = { 1649 /* HSYNC#, VSYNC# */ 1650 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), 1651 }; 1652 static const unsigned int vin1_sync_mux[] = { 1653 VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK, 1654 }; 1655 static const unsigned int vin1_field_pins[] = { 1656 RCAR_GP_PIN(3, 16), 1657 }; 1658 static const unsigned int vin1_field_mux[] = { 1659 /* FIELD */ 1660 VI1_FIELD_MARK, 1661 }; 1662 static const unsigned int vin1_clkenb_pins[] = { 1663 RCAR_GP_PIN(3, 1), 1664 }; 1665 static const unsigned int vin1_clkenb_mux[] = { 1666 /* CLKENB */ 1667 VI1_CLKENB_MARK, 1668 }; 1669 static const unsigned int vin1_clk_pins[] = { 1670 RCAR_GP_PIN(3, 0), 1671 }; 1672 static const unsigned int vin1_clk_mux[] = { 1673 /* CLK */ 1674 VI1_CLK_MARK, 1675 }; 1676 1677 static const struct sh_pfc_pin_group pinmux_groups[] = { 1678 SH_PFC_PIN_GROUP(avb0_link), 1679 SH_PFC_PIN_GROUP(avb0_magic), 1680 SH_PFC_PIN_GROUP(avb0_phy_int), 1681 SH_PFC_PIN_GROUP(avb0_mdio), 1682 SH_PFC_PIN_GROUP(avb0_rgmii), 1683 SH_PFC_PIN_GROUP(avb0_txcrefclk), 1684 SH_PFC_PIN_GROUP(avb0_avtp_pps), 1685 SH_PFC_PIN_GROUP(avb0_avtp_capture), 1686 SH_PFC_PIN_GROUP(avb0_avtp_match), 1687 SH_PFC_PIN_GROUP(canfd_clk_a), 1688 SH_PFC_PIN_GROUP(canfd_clk_b), 1689 SH_PFC_PIN_GROUP(canfd0_data_a), 1690 SH_PFC_PIN_GROUP(canfd0_data_b), 1691 SH_PFC_PIN_GROUP(canfd1_data), 1692 SH_PFC_PIN_GROUP(du_rgb666), 1693 SH_PFC_PIN_GROUP(du_clk_out), 1694 SH_PFC_PIN_GROUP(du_sync), 1695 SH_PFC_PIN_GROUP(du_oddf), 1696 SH_PFC_PIN_GROUP(du_cde), 1697 SH_PFC_PIN_GROUP(du_disp), 1698 SH_PFC_PIN_GROUP(hscif0_data), 1699 SH_PFC_PIN_GROUP(hscif0_clk), 1700 SH_PFC_PIN_GROUP(hscif0_ctrl), 1701 SH_PFC_PIN_GROUP(hscif1_data), 1702 SH_PFC_PIN_GROUP(hscif1_clk), 1703 SH_PFC_PIN_GROUP(hscif1_ctrl), 1704 SH_PFC_PIN_GROUP(hscif2_data), 1705 SH_PFC_PIN_GROUP(hscif2_clk), 1706 SH_PFC_PIN_GROUP(hscif2_ctrl), 1707 SH_PFC_PIN_GROUP(hscif3_data), 1708 SH_PFC_PIN_GROUP(hscif3_clk), 1709 SH_PFC_PIN_GROUP(hscif3_ctrl), 1710 SH_PFC_PIN_GROUP(i2c0), 1711 SH_PFC_PIN_GROUP(i2c1), 1712 SH_PFC_PIN_GROUP(i2c2), 1713 SH_PFC_PIN_GROUP(i2c3_a), 1714 SH_PFC_PIN_GROUP(i2c3_b), 1715 SH_PFC_PIN_GROUP(i2c4), 1716 SH_PFC_PIN_GROUP(intc_ex_irq0), 1717 SH_PFC_PIN_GROUP(intc_ex_irq1), 1718 SH_PFC_PIN_GROUP(intc_ex_irq2), 1719 SH_PFC_PIN_GROUP(intc_ex_irq3), 1720 SH_PFC_PIN_GROUP(intc_ex_irq4), 1721 SH_PFC_PIN_GROUP(intc_ex_irq5), 1722 BUS_DATA_PIN_GROUP(mmc_data, 1), 1723 BUS_DATA_PIN_GROUP(mmc_data, 4), 1724 BUS_DATA_PIN_GROUP(mmc_data, 8), 1725 SH_PFC_PIN_GROUP(mmc_ctrl), 1726 SH_PFC_PIN_GROUP(msiof0_clk), 1727 SH_PFC_PIN_GROUP(msiof0_sync), 1728 SH_PFC_PIN_GROUP(msiof0_ss1), 1729 SH_PFC_PIN_GROUP(msiof0_ss2), 1730 SH_PFC_PIN_GROUP(msiof0_txd), 1731 SH_PFC_PIN_GROUP(msiof0_rxd), 1732 SH_PFC_PIN_GROUP(msiof1_clk), 1733 SH_PFC_PIN_GROUP(msiof1_sync), 1734 SH_PFC_PIN_GROUP(msiof1_ss1), 1735 SH_PFC_PIN_GROUP(msiof1_ss2), 1736 SH_PFC_PIN_GROUP(msiof1_txd), 1737 SH_PFC_PIN_GROUP(msiof1_rxd), 1738 SH_PFC_PIN_GROUP(msiof2_clk), 1739 SH_PFC_PIN_GROUP(msiof2_sync), 1740 SH_PFC_PIN_GROUP(msiof2_ss1), 1741 SH_PFC_PIN_GROUP(msiof2_ss2), 1742 SH_PFC_PIN_GROUP(msiof2_txd), 1743 SH_PFC_PIN_GROUP(msiof2_rxd), 1744 SH_PFC_PIN_GROUP(msiof3_clk), 1745 SH_PFC_PIN_GROUP(msiof3_sync), 1746 SH_PFC_PIN_GROUP(msiof3_ss1), 1747 SH_PFC_PIN_GROUP(msiof3_ss2), 1748 SH_PFC_PIN_GROUP(msiof3_txd), 1749 SH_PFC_PIN_GROUP(msiof3_rxd), 1750 SH_PFC_PIN_GROUP(pwm0_a), 1751 SH_PFC_PIN_GROUP(pwm0_b), 1752 SH_PFC_PIN_GROUP(pwm1_a), 1753 SH_PFC_PIN_GROUP(pwm1_b), 1754 SH_PFC_PIN_GROUP(pwm2_a), 1755 SH_PFC_PIN_GROUP(pwm2_b), 1756 SH_PFC_PIN_GROUP(pwm3_a), 1757 SH_PFC_PIN_GROUP(pwm3_b), 1758 SH_PFC_PIN_GROUP(pwm4_a), 1759 SH_PFC_PIN_GROUP(pwm4_b), 1760 SH_PFC_PIN_GROUP(qspi0_ctrl), 1761 SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2), 1762 SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4), 1763 SH_PFC_PIN_GROUP(qspi1_ctrl), 1764 SH_PFC_PIN_GROUP_SUBSET(qspi1_data2, rpc_data, 4, 2), 1765 SH_PFC_PIN_GROUP_SUBSET(qspi1_data4, rpc_data, 4, 4), 1766 BUS_DATA_PIN_GROUP(rpc_clk, 1), 1767 BUS_DATA_PIN_GROUP(rpc_clk, 2), 1768 SH_PFC_PIN_GROUP(rpc_ctrl), 1769 SH_PFC_PIN_GROUP(rpc_data), 1770 SH_PFC_PIN_GROUP(rpc_reset), 1771 SH_PFC_PIN_GROUP(rpc_int), 1772 SH_PFC_PIN_GROUP(rpc_wp), 1773 SH_PFC_PIN_GROUP(scif_clk_a), 1774 SH_PFC_PIN_GROUP(scif_clk_b), 1775 SH_PFC_PIN_GROUP(scif0_data), 1776 SH_PFC_PIN_GROUP(scif0_clk), 1777 SH_PFC_PIN_GROUP(scif0_ctrl), 1778 SH_PFC_PIN_GROUP(scif1_data_a), 1779 SH_PFC_PIN_GROUP(scif1_clk), 1780 SH_PFC_PIN_GROUP(scif1_ctrl), 1781 SH_PFC_PIN_GROUP(scif1_data_b), 1782 SH_PFC_PIN_GROUP(scif3_data), 1783 SH_PFC_PIN_GROUP(scif3_clk), 1784 SH_PFC_PIN_GROUP(scif3_ctrl), 1785 SH_PFC_PIN_GROUP(scif4_data), 1786 SH_PFC_PIN_GROUP(scif4_clk), 1787 SH_PFC_PIN_GROUP(scif4_ctrl), 1788 SH_PFC_PIN_GROUP(tmu_tclk1_a), 1789 SH_PFC_PIN_GROUP(tmu_tclk1_b), 1790 SH_PFC_PIN_GROUP(tmu_tclk2_a), 1791 SH_PFC_PIN_GROUP(tmu_tclk2_b), 1792 BUS_DATA_PIN_GROUP(vin0_data, 8), 1793 BUS_DATA_PIN_GROUP(vin0_data, 10), 1794 BUS_DATA_PIN_GROUP(vin0_data, 12), 1795 SH_PFC_PIN_GROUP(vin0_sync), 1796 SH_PFC_PIN_GROUP(vin0_field), 1797 SH_PFC_PIN_GROUP(vin0_clkenb), 1798 SH_PFC_PIN_GROUP(vin0_clk), 1799 BUS_DATA_PIN_GROUP(vin1_data, 8), 1800 BUS_DATA_PIN_GROUP(vin1_data, 10), 1801 BUS_DATA_PIN_GROUP(vin1_data, 12), 1802 SH_PFC_PIN_GROUP(vin1_sync), 1803 SH_PFC_PIN_GROUP(vin1_field), 1804 SH_PFC_PIN_GROUP(vin1_clkenb), 1805 SH_PFC_PIN_GROUP(vin1_clk), 1806 }; 1807 1808 static const char * const avb0_groups[] = { 1809 "avb0_link", 1810 "avb0_magic", 1811 "avb0_phy_int", 1812 "avb0_mdio", 1813 "avb0_rgmii", 1814 "avb0_txcrefclk", 1815 "avb0_avtp_pps", 1816 "avb0_avtp_capture", 1817 "avb0_avtp_match", 1818 }; 1819 1820 static const char * const canfd_clk_groups[] = { 1821 "canfd_clk_a", 1822 "canfd_clk_b", 1823 }; 1824 1825 static const char * const canfd0_groups[] = { 1826 "canfd0_data_a", 1827 "canfd0_data_b", 1828 }; 1829 1830 static const char * const canfd1_groups[] = { 1831 "canfd1_data", 1832 }; 1833 1834 static const char * const du_groups[] = { 1835 "du_rgb666", 1836 "du_clk_out", 1837 "du_sync", 1838 "du_oddf", 1839 "du_cde", 1840 "du_disp", 1841 }; 1842 1843 static const char * const hscif0_groups[] = { 1844 "hscif0_data", 1845 "hscif0_clk", 1846 "hscif0_ctrl", 1847 }; 1848 1849 static const char * const hscif1_groups[] = { 1850 "hscif1_data", 1851 "hscif1_clk", 1852 "hscif1_ctrl", 1853 }; 1854 1855 static const char * const hscif2_groups[] = { 1856 "hscif2_data", 1857 "hscif2_clk", 1858 "hscif2_ctrl", 1859 }; 1860 1861 static const char * const hscif3_groups[] = { 1862 "hscif3_data", 1863 "hscif3_clk", 1864 "hscif3_ctrl", 1865 }; 1866 1867 static const char * const i2c0_groups[] = { 1868 "i2c0", 1869 }; 1870 1871 static const char * const i2c1_groups[] = { 1872 "i2c1", 1873 }; 1874 1875 static const char * const i2c2_groups[] = { 1876 "i2c2", 1877 }; 1878 1879 static const char * const i2c3_groups[] = { 1880 "i2c3_a", 1881 "i2c3_b", 1882 }; 1883 1884 static const char * const i2c4_groups[] = { 1885 "i2c4", 1886 }; 1887 1888 static const char * const intc_ex_groups[] = { 1889 "intc_ex_irq0", 1890 "intc_ex_irq1", 1891 "intc_ex_irq2", 1892 "intc_ex_irq3", 1893 "intc_ex_irq4", 1894 "intc_ex_irq5", 1895 }; 1896 1897 static const char * const mmc_groups[] = { 1898 "mmc_data1", 1899 "mmc_data4", 1900 "mmc_data8", 1901 "mmc_ctrl", 1902 }; 1903 1904 static const char * const msiof0_groups[] = { 1905 "msiof0_clk", 1906 "msiof0_sync", 1907 "msiof0_ss1", 1908 "msiof0_ss2", 1909 "msiof0_txd", 1910 "msiof0_rxd", 1911 }; 1912 1913 static const char * const msiof1_groups[] = { 1914 "msiof1_clk", 1915 "msiof1_sync", 1916 "msiof1_ss1", 1917 "msiof1_ss2", 1918 "msiof1_txd", 1919 "msiof1_rxd", 1920 }; 1921 1922 static const char * const msiof2_groups[] = { 1923 "msiof2_clk", 1924 "msiof2_sync", 1925 "msiof2_ss1", 1926 "msiof2_ss2", 1927 "msiof2_txd", 1928 "msiof2_rxd", 1929 }; 1930 1931 static const char * const msiof3_groups[] = { 1932 "msiof3_clk", 1933 "msiof3_sync", 1934 "msiof3_ss1", 1935 "msiof3_ss2", 1936 "msiof3_txd", 1937 "msiof3_rxd", 1938 }; 1939 1940 static const char * const pwm0_groups[] = { 1941 "pwm0_a", 1942 "pwm0_b", 1943 }; 1944 1945 static const char * const pwm1_groups[] = { 1946 "pwm1_a", 1947 "pwm1_b", 1948 }; 1949 1950 static const char * const pwm2_groups[] = { 1951 "pwm2_a", 1952 "pwm2_b", 1953 }; 1954 1955 static const char * const pwm3_groups[] = { 1956 "pwm3_a", 1957 "pwm3_b", 1958 }; 1959 1960 static const char * const pwm4_groups[] = { 1961 "pwm4_a", 1962 "pwm4_b", 1963 }; 1964 1965 static const char * const qspi0_groups[] = { 1966 "qspi0_ctrl", 1967 "qspi0_data2", 1968 "qspi0_data4", 1969 }; 1970 1971 static const char * const qspi1_groups[] = { 1972 "qspi1_ctrl", 1973 "qspi1_data2", 1974 "qspi1_data4", 1975 }; 1976 1977 static const char * const rpc_groups[] = { 1978 "rpc_clk1", 1979 "rpc_clk2", 1980 "rpc_ctrl", 1981 "rpc_data", 1982 "rpc_reset", 1983 "rpc_int", 1984 "rpc_wp", 1985 }; 1986 1987 static const char * const scif_clk_groups[] = { 1988 "scif_clk_a", 1989 "scif_clk_b", 1990 }; 1991 1992 static const char * const scif0_groups[] = { 1993 "scif0_data", 1994 "scif0_clk", 1995 "scif0_ctrl", 1996 }; 1997 1998 static const char * const scif1_groups[] = { 1999 "scif1_data_a", 2000 "scif1_clk", 2001 "scif1_ctrl", 2002 "scif1_data_b", 2003 }; 2004 2005 static const char * const scif3_groups[] = { 2006 "scif3_data", 2007 "scif3_clk", 2008 "scif3_ctrl", 2009 }; 2010 2011 static const char * const scif4_groups[] = { 2012 "scif4_data", 2013 "scif4_clk", 2014 "scif4_ctrl", 2015 }; 2016 2017 static const char * const tmu_groups[] = { 2018 "tmu_tclk1_a", 2019 "tmu_tclk1_b", 2020 "tmu_tclk2_a", 2021 "tmu_tclk2_b", 2022 }; 2023 2024 static const char * const vin0_groups[] = { 2025 "vin0_data8", 2026 "vin0_data10", 2027 "vin0_data12", 2028 "vin0_sync", 2029 "vin0_field", 2030 "vin0_clkenb", 2031 "vin0_clk", 2032 }; 2033 2034 static const char * const vin1_groups[] = { 2035 "vin1_data8", 2036 "vin1_data10", 2037 "vin1_data12", 2038 "vin1_sync", 2039 "vin1_field", 2040 "vin1_clkenb", 2041 "vin1_clk", 2042 }; 2043 2044 static const struct sh_pfc_function pinmux_functions[] = { 2045 SH_PFC_FUNCTION(avb0), 2046 SH_PFC_FUNCTION(canfd_clk), 2047 SH_PFC_FUNCTION(canfd0), 2048 SH_PFC_FUNCTION(canfd1), 2049 SH_PFC_FUNCTION(du), 2050 SH_PFC_FUNCTION(hscif0), 2051 SH_PFC_FUNCTION(hscif1), 2052 SH_PFC_FUNCTION(hscif2), 2053 SH_PFC_FUNCTION(hscif3), 2054 SH_PFC_FUNCTION(i2c0), 2055 SH_PFC_FUNCTION(i2c1), 2056 SH_PFC_FUNCTION(i2c2), 2057 SH_PFC_FUNCTION(i2c3), 2058 SH_PFC_FUNCTION(i2c4), 2059 SH_PFC_FUNCTION(intc_ex), 2060 SH_PFC_FUNCTION(mmc), 2061 SH_PFC_FUNCTION(msiof0), 2062 SH_PFC_FUNCTION(msiof1), 2063 SH_PFC_FUNCTION(msiof2), 2064 SH_PFC_FUNCTION(msiof3), 2065 SH_PFC_FUNCTION(pwm0), 2066 SH_PFC_FUNCTION(pwm1), 2067 SH_PFC_FUNCTION(pwm2), 2068 SH_PFC_FUNCTION(pwm3), 2069 SH_PFC_FUNCTION(pwm4), 2070 SH_PFC_FUNCTION(qspi0), 2071 SH_PFC_FUNCTION(qspi1), 2072 SH_PFC_FUNCTION(rpc), 2073 SH_PFC_FUNCTION(scif_clk), 2074 SH_PFC_FUNCTION(scif0), 2075 SH_PFC_FUNCTION(scif1), 2076 SH_PFC_FUNCTION(scif3), 2077 SH_PFC_FUNCTION(scif4), 2078 SH_PFC_FUNCTION(tmu), 2079 SH_PFC_FUNCTION(vin0), 2080 SH_PFC_FUNCTION(vin1), 2081 }; 2082 2083 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 2084 #define F_(x, y) FN_##y 2085 #define FM(x) FN_##x 2086 { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32, 2087 GROUP(-10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2088 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), 2089 GROUP( 2090 /* GP0_31_22 RESERVED */ 2091 GP_0_21_FN, GPSR0_21, 2092 GP_0_20_FN, GPSR0_20, 2093 GP_0_19_FN, GPSR0_19, 2094 GP_0_18_FN, GPSR0_18, 2095 GP_0_17_FN, GPSR0_17, 2096 GP_0_16_FN, GPSR0_16, 2097 GP_0_15_FN, GPSR0_15, 2098 GP_0_14_FN, GPSR0_14, 2099 GP_0_13_FN, GPSR0_13, 2100 GP_0_12_FN, GPSR0_12, 2101 GP_0_11_FN, GPSR0_11, 2102 GP_0_10_FN, GPSR0_10, 2103 GP_0_9_FN, GPSR0_9, 2104 GP_0_8_FN, GPSR0_8, 2105 GP_0_7_FN, GPSR0_7, 2106 GP_0_6_FN, GPSR0_6, 2107 GP_0_5_FN, GPSR0_5, 2108 GP_0_4_FN, GPSR0_4, 2109 GP_0_3_FN, GPSR0_3, 2110 GP_0_2_FN, GPSR0_2, 2111 GP_0_1_FN, GPSR0_1, 2112 GP_0_0_FN, GPSR0_0, )) 2113 }, 2114 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( 2115 0, 0, 2116 0, 0, 2117 0, 0, 2118 0, 0, 2119 GP_1_27_FN, GPSR1_27, 2120 GP_1_26_FN, GPSR1_26, 2121 GP_1_25_FN, GPSR1_25, 2122 GP_1_24_FN, GPSR1_24, 2123 GP_1_23_FN, GPSR1_23, 2124 GP_1_22_FN, GPSR1_22, 2125 GP_1_21_FN, GPSR1_21, 2126 GP_1_20_FN, GPSR1_20, 2127 GP_1_19_FN, GPSR1_19, 2128 GP_1_18_FN, GPSR1_18, 2129 GP_1_17_FN, GPSR1_17, 2130 GP_1_16_FN, GPSR1_16, 2131 GP_1_15_FN, GPSR1_15, 2132 GP_1_14_FN, GPSR1_14, 2133 GP_1_13_FN, GPSR1_13, 2134 GP_1_12_FN, GPSR1_12, 2135 GP_1_11_FN, GPSR1_11, 2136 GP_1_10_FN, GPSR1_10, 2137 GP_1_9_FN, GPSR1_9, 2138 GP_1_8_FN, GPSR1_8, 2139 GP_1_7_FN, GPSR1_7, 2140 GP_1_6_FN, GPSR1_6, 2141 GP_1_5_FN, GPSR1_5, 2142 GP_1_4_FN, GPSR1_4, 2143 GP_1_3_FN, GPSR1_3, 2144 GP_1_2_FN, GPSR1_2, 2145 GP_1_1_FN, GPSR1_1, 2146 GP_1_0_FN, GPSR1_0, )) 2147 }, 2148 { PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32, 2149 GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2150 1, 1, 1, 1, 1, 1), 2151 GROUP( 2152 /* GP2_31_17 RESERVED */ 2153 GP_2_16_FN, GPSR2_16, 2154 GP_2_15_FN, GPSR2_15, 2155 GP_2_14_FN, GPSR2_14, 2156 GP_2_13_FN, GPSR2_13, 2157 GP_2_12_FN, GPSR2_12, 2158 GP_2_11_FN, GPSR2_11, 2159 GP_2_10_FN, GPSR2_10, 2160 GP_2_9_FN, GPSR2_9, 2161 GP_2_8_FN, GPSR2_8, 2162 GP_2_7_FN, GPSR2_7, 2163 GP_2_6_FN, GPSR2_6, 2164 GP_2_5_FN, GPSR2_5, 2165 GP_2_4_FN, GPSR2_4, 2166 GP_2_3_FN, GPSR2_3, 2167 GP_2_2_FN, GPSR2_2, 2168 GP_2_1_FN, GPSR2_1, 2169 GP_2_0_FN, GPSR2_0, )) 2170 }, 2171 { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32, 2172 GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2173 1, 1, 1, 1, 1, 1), 2174 GROUP( 2175 /* GP3_31_17 RESERVED */ 2176 GP_3_16_FN, GPSR3_16, 2177 GP_3_15_FN, GPSR3_15, 2178 GP_3_14_FN, GPSR3_14, 2179 GP_3_13_FN, GPSR3_13, 2180 GP_3_12_FN, GPSR3_12, 2181 GP_3_11_FN, GPSR3_11, 2182 GP_3_10_FN, GPSR3_10, 2183 GP_3_9_FN, GPSR3_9, 2184 GP_3_8_FN, GPSR3_8, 2185 GP_3_7_FN, GPSR3_7, 2186 GP_3_6_FN, GPSR3_6, 2187 GP_3_5_FN, GPSR3_5, 2188 GP_3_4_FN, GPSR3_4, 2189 GP_3_3_FN, GPSR3_3, 2190 GP_3_2_FN, GPSR3_2, 2191 GP_3_1_FN, GPSR3_1, 2192 GP_3_0_FN, GPSR3_0, )) 2193 }, 2194 { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32, 2195 GROUP(-26, 1, 1, 1, 1, 1, 1), 2196 GROUP( 2197 /* GP4_31_6 RESERVED */ 2198 GP_4_5_FN, GPSR4_5, 2199 GP_4_4_FN, GPSR4_4, 2200 GP_4_3_FN, GPSR4_3, 2201 GP_4_2_FN, GPSR4_2, 2202 GP_4_1_FN, GPSR4_1, 2203 GP_4_0_FN, GPSR4_0, )) 2204 }, 2205 { PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32, 2206 GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2207 1, 1, 1, 1), 2208 GROUP( 2209 /* GP5_31_15 RESERVED */ 2210 GP_5_14_FN, GPSR5_14, 2211 GP_5_13_FN, GPSR5_13, 2212 GP_5_12_FN, GPSR5_12, 2213 GP_5_11_FN, GPSR5_11, 2214 GP_5_10_FN, GPSR5_10, 2215 GP_5_9_FN, GPSR5_9, 2216 GP_5_8_FN, GPSR5_8, 2217 GP_5_7_FN, GPSR5_7, 2218 GP_5_6_FN, GPSR5_6, 2219 GP_5_5_FN, GPSR5_5, 2220 GP_5_4_FN, GPSR5_4, 2221 GP_5_3_FN, GPSR5_3, 2222 GP_5_2_FN, GPSR5_2, 2223 GP_5_1_FN, GPSR5_1, 2224 GP_5_0_FN, GPSR5_0, )) 2225 }, 2226 #undef F_ 2227 #undef FM 2228 2229 #define F_(x, y) x, 2230 #define FM(x) FN_##x, 2231 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( 2232 IP0_31_28 2233 IP0_27_24 2234 IP0_23_20 2235 IP0_19_16 2236 IP0_15_12 2237 IP0_11_8 2238 IP0_7_4 2239 IP0_3_0 )) 2240 }, 2241 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( 2242 IP1_31_28 2243 IP1_27_24 2244 IP1_23_20 2245 IP1_19_16 2246 IP1_15_12 2247 IP1_11_8 2248 IP1_7_4 2249 IP1_3_0 )) 2250 }, 2251 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( 2252 IP2_31_28 2253 IP2_27_24 2254 IP2_23_20 2255 IP2_19_16 2256 IP2_15_12 2257 IP2_11_8 2258 IP2_7_4 2259 IP2_3_0 )) 2260 }, 2261 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( 2262 IP3_31_28 2263 IP3_27_24 2264 IP3_23_20 2265 IP3_19_16 2266 IP3_15_12 2267 IP3_11_8 2268 IP3_7_4 2269 IP3_3_0 )) 2270 }, 2271 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( 2272 IP4_31_28 2273 IP4_27_24 2274 IP4_23_20 2275 IP4_19_16 2276 IP4_15_12 2277 IP4_11_8 2278 IP4_7_4 2279 IP4_3_0 )) 2280 }, 2281 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( 2282 IP5_31_28 2283 IP5_27_24 2284 IP5_23_20 2285 IP5_19_16 2286 IP5_15_12 2287 IP5_11_8 2288 IP5_7_4 2289 IP5_3_0 )) 2290 }, 2291 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( 2292 IP6_31_28 2293 IP6_27_24 2294 IP6_23_20 2295 IP6_19_16 2296 IP6_15_12 2297 IP6_11_8 2298 IP6_7_4 2299 IP6_3_0 )) 2300 }, 2301 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( 2302 IP7_31_28 2303 IP7_27_24 2304 IP7_23_20 2305 IP7_19_16 2306 IP7_15_12 2307 IP7_11_8 2308 IP7_7_4 2309 IP7_3_0 )) 2310 }, 2311 { PINMUX_CFG_REG_VAR("IPSR8", 0xe6060220, 32, 2312 GROUP(-4, 4, 4, 4, 4, 4, 4, 4), 2313 GROUP( 2314 /* IP8_31_28 RESERVED */ 2315 IP8_27_24 2316 IP8_23_20 2317 IP8_19_16 2318 IP8_15_12 2319 IP8_11_8 2320 IP8_7_4 2321 IP8_3_0 )) 2322 }, 2323 #undef F_ 2324 #undef FM 2325 2326 #define F_(x, y) x, 2327 #define FM(x) FN_##x, 2328 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, 2329 GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), 2330 GROUP( 2331 /* RESERVED 31-12 */ 2332 MOD_SEL0_11 2333 MOD_SEL0_10 2334 MOD_SEL0_9 2335 MOD_SEL0_8 2336 MOD_SEL0_7 2337 MOD_SEL0_6 2338 MOD_SEL0_5 2339 MOD_SEL0_4 2340 MOD_SEL0_3 2341 MOD_SEL0_2 2342 MOD_SEL0_1 2343 MOD_SEL0_0 )) 2344 }, 2345 { }, 2346 }; 2347 2348 enum ioctrl_regs { 2349 POCCTRL0, 2350 POCCTRL1, 2351 POCCTRL2, 2352 TDSELCTRL, 2353 }; 2354 2355 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { 2356 [POCCTRL0] = { 0xe6060380 }, 2357 [POCCTRL1] = { 0xe6060384 }, 2358 [POCCTRL2] = { 0xe6060388 }, 2359 [TDSELCTRL] = { 0xe60603c0, }, 2360 { /* sentinel */ }, 2361 }; 2362 2363 static int r8a77970_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) 2364 { 2365 int bit = pin & 0x1f; 2366 2367 *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg; 2368 if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21)) 2369 return bit; 2370 if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9)) 2371 return bit + 22; 2372 2373 *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg; 2374 if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16)) 2375 return bit - 10; 2376 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16)) 2377 return bit + 7; 2378 2379 return -EINVAL; 2380 } 2381 2382 static const struct pinmux_bias_reg pinmux_bias_regs[] = { 2383 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { 2384 [ 0] = RCAR_GP_PIN(0, 0), /* DU_DR2 */ 2385 [ 1] = RCAR_GP_PIN(0, 1), /* DU_DR3 */ 2386 [ 2] = RCAR_GP_PIN(0, 2), /* DU_DR4 */ 2387 [ 3] = RCAR_GP_PIN(0, 3), /* DU_DR5 */ 2388 [ 4] = RCAR_GP_PIN(0, 4), /* DU_DR6 */ 2389 [ 5] = RCAR_GP_PIN(0, 5), /* DU_DR7 */ 2390 [ 6] = RCAR_GP_PIN(0, 6), /* DU_DG2 */ 2391 [ 7] = RCAR_GP_PIN(0, 7), /* DU_DG3 */ 2392 [ 8] = RCAR_GP_PIN(0, 8), /* DU_DG4 */ 2393 [ 9] = RCAR_GP_PIN(0, 9), /* DU_DG5 */ 2394 [10] = RCAR_GP_PIN(0, 10), /* DU_DG6 */ 2395 [11] = RCAR_GP_PIN(0, 11), /* DU_DG7 */ 2396 [12] = RCAR_GP_PIN(0, 12), /* DU_DB2 */ 2397 [13] = RCAR_GP_PIN(0, 13), /* DU_DB3 */ 2398 [14] = RCAR_GP_PIN(0, 14), /* DU_DB4 */ 2399 [15] = RCAR_GP_PIN(0, 15), /* DU_DB5 */ 2400 [16] = RCAR_GP_PIN(0, 16), /* DU_DB6 */ 2401 [17] = RCAR_GP_PIN(0, 17), /* DU_DB7 */ 2402 [18] = RCAR_GP_PIN(0, 18), /* DU_DOTCLKOUT */ 2403 [19] = RCAR_GP_PIN(0, 19), /* DU_EXHSYNC/DU_HSYNC */ 2404 [20] = RCAR_GP_PIN(0, 20), /* DU_EXVSYNC/DU_VSYNC */ 2405 [21] = RCAR_GP_PIN(0, 21), /* DU_EXODDF/DU_ODDF/DISP/CDE */ 2406 [22] = PIN_DU_DOTCLKIN, /* DU_DOTCLKIN */ 2407 [23] = PIN_PRESETOUT_N, /* PRESETOUT# */ 2408 [24] = PIN_EXTALR, /* EXTALR */ 2409 [25] = PIN_FSCLKST_N, /* FSCLKST# */ 2410 [26] = RCAR_GP_PIN(1, 0), /* IRQ0 */ 2411 [27] = PIN_TRST_N, /* TRST# */ 2412 [28] = PIN_TCK, /* TCK */ 2413 [29] = PIN_TMS, /* TMS */ 2414 [30] = PIN_TDI, /* TDI */ 2415 [31] = RCAR_GP_PIN(2, 0), /* VI0_CLK */ 2416 } }, 2417 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) { 2418 [ 0] = RCAR_GP_PIN(2, 1), /* VI0_CLKENB */ 2419 [ 1] = RCAR_GP_PIN(2, 2), /* VI0_HSYNC# */ 2420 [ 2] = RCAR_GP_PIN(2, 3), /* VI0_VSYNC# */ 2421 [ 3] = RCAR_GP_PIN(2, 4), /* VI0_DATA0 */ 2422 [ 4] = RCAR_GP_PIN(2, 5), /* VI0_DATA1 */ 2423 [ 5] = RCAR_GP_PIN(2, 6), /* VI0_DATA2 */ 2424 [ 6] = RCAR_GP_PIN(2, 7), /* VI0_DATA3 */ 2425 [ 7] = RCAR_GP_PIN(2, 8), /* VI0_DATA4 */ 2426 [ 8] = RCAR_GP_PIN(2, 9), /* VI0_DATA5 */ 2427 [ 9] = RCAR_GP_PIN(2, 10), /* VI0_DATA6 */ 2428 [10] = RCAR_GP_PIN(2, 11), /* VI0_DATA7 */ 2429 [11] = RCAR_GP_PIN(2, 12), /* VI0_DATA8 */ 2430 [12] = RCAR_GP_PIN(2, 13), /* VI0_DATA9 */ 2431 [13] = RCAR_GP_PIN(2, 14), /* VI0_DATA10 */ 2432 [14] = RCAR_GP_PIN(2, 15), /* VI0_DATA11 */ 2433 [15] = RCAR_GP_PIN(2, 16), /* VI0_FIELD */ 2434 [16] = RCAR_GP_PIN(3, 0), /* VI1_CLK */ 2435 [17] = RCAR_GP_PIN(3, 1), /* VI1_CLKENB */ 2436 [18] = RCAR_GP_PIN(3, 2), /* VI1_HSYNC# */ 2437 [19] = RCAR_GP_PIN(3, 3), /* VI1_VSYNC# */ 2438 [20] = RCAR_GP_PIN(3, 4), /* VI1_DATA0 */ 2439 [21] = RCAR_GP_PIN(3, 5), /* VI1_DATA1 */ 2440 [22] = RCAR_GP_PIN(3, 6), /* VI1_DATA2 */ 2441 [23] = RCAR_GP_PIN(3, 7), /* VI1_DATA3 */ 2442 [24] = RCAR_GP_PIN(3, 8), /* VI1_DATA4 */ 2443 [25] = RCAR_GP_PIN(3, 9), /* VI1_DATA5 */ 2444 [26] = RCAR_GP_PIN(3, 10), /* VI1_DATA6 */ 2445 [27] = RCAR_GP_PIN(3, 11), /* VI1_DATA7 */ 2446 [28] = RCAR_GP_PIN(3, 12), /* VI1_DATA8 */ 2447 [29] = RCAR_GP_PIN(3, 13), /* VI1_DATA9 */ 2448 [30] = RCAR_GP_PIN(3, 14), /* VI1_DATA10 */ 2449 [31] = RCAR_GP_PIN(3, 15), /* VI1_DATA11 */ 2450 } }, 2451 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { 2452 [ 0] = RCAR_GP_PIN(3, 16), /* VI1_FIELD */ 2453 [ 1] = RCAR_GP_PIN(4, 0), /* SCL0 */ 2454 [ 2] = RCAR_GP_PIN(4, 1), /* SDA0 */ 2455 [ 3] = RCAR_GP_PIN(4, 2), /* SCL1 */ 2456 [ 4] = RCAR_GP_PIN(4, 3), /* SDA1 */ 2457 [ 5] = RCAR_GP_PIN(4, 4), /* SCL2 */ 2458 [ 6] = RCAR_GP_PIN(4, 5), /* SDA2 */ 2459 [ 7] = RCAR_GP_PIN(1, 1), /* AVB0_RX_CTL */ 2460 [ 8] = RCAR_GP_PIN(1, 2), /* AVB0_RXC */ 2461 [ 9] = RCAR_GP_PIN(1, 3), /* AVB0_RD0 */ 2462 [10] = RCAR_GP_PIN(1, 4), /* AVB0_RD1 */ 2463 [11] = RCAR_GP_PIN(1, 5), /* AVB0_RD2 */ 2464 [12] = RCAR_GP_PIN(1, 6), /* AVB0_RD3 */ 2465 [13] = RCAR_GP_PIN(1, 7), /* AVB0_TX_CTL */ 2466 [14] = RCAR_GP_PIN(1, 8), /* AVB0_TXC */ 2467 [15] = RCAR_GP_PIN(1, 9), /* AVB0_TD0 */ 2468 [16] = RCAR_GP_PIN(1, 10), /* AVB0_TD1 */ 2469 [17] = RCAR_GP_PIN(1, 11), /* AVB0_TD2 */ 2470 [18] = RCAR_GP_PIN(1, 12), /* AVB0_TD3 */ 2471 [19] = RCAR_GP_PIN(1, 13), /* AVB0_TXCREFCLK */ 2472 [20] = RCAR_GP_PIN(1, 14), /* AVB0_MDIO */ 2473 [21] = RCAR_GP_PIN(1, 15), /* AVB0_MDC */ 2474 [22] = RCAR_GP_PIN(1, 16), /* AVB0_MAGIC */ 2475 [23] = RCAR_GP_PIN(1, 17), /* AVB0_PHY_INT */ 2476 [24] = RCAR_GP_PIN(1, 18), /* AVB0_LINK */ 2477 [25] = RCAR_GP_PIN(1, 19), /* AVB0_AVTP_MATCH */ 2478 [26] = RCAR_GP_PIN(1, 20), /* AVB0_AVTP_CAPTURE */ 2479 [27] = RCAR_GP_PIN(1, 21), /* CANFD0_TX_A */ 2480 [28] = RCAR_GP_PIN(1, 22), /* CANFD0_RX_A */ 2481 [29] = RCAR_GP_PIN(1, 23), /* CANFD1_TX */ 2482 [30] = RCAR_GP_PIN(1, 24), /* CANFD1_RX */ 2483 [31] = RCAR_GP_PIN(1, 25), /* CANFD_CLK */ 2484 } }, 2485 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { 2486 [ 0] = RCAR_GP_PIN(5, 0), /* QSPI0_SPCLK */ 2487 [ 1] = RCAR_GP_PIN(5, 1), /* QSPI0_MOSI_IO0 */ 2488 [ 2] = RCAR_GP_PIN(5, 2), /* QSPI0_MISO_IO1 */ 2489 [ 3] = RCAR_GP_PIN(5, 3), /* QSPI0_IO2 */ 2490 [ 4] = RCAR_GP_PIN(5, 4), /* QSPI0_IO3 */ 2491 [ 5] = RCAR_GP_PIN(5, 5), /* QSPI0_SSL */ 2492 [ 6] = RCAR_GP_PIN(5, 6), /* QSPI1_SPCLK */ 2493 [ 7] = RCAR_GP_PIN(5, 7), /* QSPI1_MOSI_IO0 */ 2494 [ 8] = RCAR_GP_PIN(5, 8), /* QSPI1_MISO_IO1 */ 2495 [ 9] = RCAR_GP_PIN(5, 9), /* QSPI1_IO2 */ 2496 [10] = RCAR_GP_PIN(5, 10), /* QSPI1_IO3 */ 2497 [11] = RCAR_GP_PIN(5, 11), /* QSPI1_SSL */ 2498 [12] = RCAR_GP_PIN(5, 12), /* RPC_RESET# */ 2499 [13] = RCAR_GP_PIN(5, 13), /* RPC_WP# */ 2500 [14] = RCAR_GP_PIN(5, 14), /* RPC_INT# */ 2501 [15] = RCAR_GP_PIN(1, 26), /* DIGRF_CLKIN */ 2502 [16] = RCAR_GP_PIN(1, 27), /* DIGRF_CLKOUT */ 2503 [17] = SH_PFC_PIN_NONE, 2504 [18] = SH_PFC_PIN_NONE, 2505 [19] = SH_PFC_PIN_NONE, 2506 [20] = SH_PFC_PIN_NONE, 2507 [21] = SH_PFC_PIN_NONE, 2508 [22] = SH_PFC_PIN_NONE, 2509 [23] = SH_PFC_PIN_NONE, 2510 [24] = SH_PFC_PIN_NONE, 2511 [25] = SH_PFC_PIN_NONE, 2512 [26] = SH_PFC_PIN_NONE, 2513 [27] = SH_PFC_PIN_NONE, 2514 [28] = SH_PFC_PIN_NONE, 2515 [29] = SH_PFC_PIN_NONE, 2516 [30] = SH_PFC_PIN_NONE, 2517 [31] = SH_PFC_PIN_NONE, 2518 } }, 2519 { /* sentinel */ } 2520 }; 2521 2522 static const struct sh_pfc_soc_operations r8a77970_pfc_ops = { 2523 .pin_to_pocctrl = r8a77970_pin_to_pocctrl, 2524 .get_bias = rcar_pinmux_get_bias, 2525 .set_bias = rcar_pinmux_set_bias, 2526 }; 2527 2528 const struct sh_pfc_soc_info r8a77970_pinmux_info = { 2529 .name = "r8a77970_pfc", 2530 .ops = &r8a77970_pfc_ops, 2531 .unlock_reg = 0xe6060000, /* PMMR */ 2532 2533 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 2534 2535 .pins = pinmux_pins, 2536 .nr_pins = ARRAY_SIZE(pinmux_pins), 2537 .groups = pinmux_groups, 2538 .nr_groups = ARRAY_SIZE(pinmux_groups), 2539 .functions = pinmux_functions, 2540 .nr_functions = ARRAY_SIZE(pinmux_functions), 2541 2542 .cfg_regs = pinmux_config_regs, 2543 .bias_regs = pinmux_bias_regs, 2544 .ioctrl_regs = pinmux_ioctrl_regs, 2545 2546 .pinmux_data = pinmux_data, 2547 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 2548 }; 2549