1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * R8A77965 processor support - PFC hardware block. 4 * 5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org> 6 * Copyright (C) 2016-2019 Renesas Electronics Corp. 7 * 8 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c 9 * 10 * R-Car Gen3 processor support - PFC hardware block. 11 * 12 * Copyright (C) 2015 Renesas Electronics Corporation 13 */ 14 15 #include <linux/errno.h> 16 #include <linux/kernel.h> 17 18 #include "sh_pfc.h" 19 20 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN) 21 22 #define CPU_ALL_GP(fn, sfx) \ 23 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ 24 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \ 25 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \ 26 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ 27 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \ 28 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \ 29 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \ 30 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \ 31 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ 32 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \ 33 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \ 34 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS) 35 36 #define CPU_ALL_NOGP(fn) \ 37 PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \ 38 PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \ 39 PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \ 40 PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \ 41 PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \ 42 PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \ 43 PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \ 44 PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \ 45 PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \ 46 PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \ 47 PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \ 48 PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \ 49 PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \ 50 PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \ 51 PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \ 52 PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \ 53 PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \ 54 PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \ 55 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\ 56 PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS), \ 57 PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \ 58 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \ 59 PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \ 60 PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \ 61 PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \ 62 PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \ 63 PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \ 64 PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \ 65 PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \ 66 PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \ 67 PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \ 68 PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \ 69 PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \ 70 PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \ 71 PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \ 72 PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \ 73 PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \ 74 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 75 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 76 PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ 77 PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \ 78 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN) 79 80 /* 81 * F_() : just information 82 * FM() : macro for FN_xxx / xxx_MARK 83 */ 84 85 /* GPSR0 */ 86 #define GPSR0_15 F_(D15, IP7_11_8) 87 #define GPSR0_14 F_(D14, IP7_7_4) 88 #define GPSR0_13 F_(D13, IP7_3_0) 89 #define GPSR0_12 F_(D12, IP6_31_28) 90 #define GPSR0_11 F_(D11, IP6_27_24) 91 #define GPSR0_10 F_(D10, IP6_23_20) 92 #define GPSR0_9 F_(D9, IP6_19_16) 93 #define GPSR0_8 F_(D8, IP6_15_12) 94 #define GPSR0_7 F_(D7, IP6_11_8) 95 #define GPSR0_6 F_(D6, IP6_7_4) 96 #define GPSR0_5 F_(D5, IP6_3_0) 97 #define GPSR0_4 F_(D4, IP5_31_28) 98 #define GPSR0_3 F_(D3, IP5_27_24) 99 #define GPSR0_2 F_(D2, IP5_23_20) 100 #define GPSR0_1 F_(D1, IP5_19_16) 101 #define GPSR0_0 F_(D0, IP5_15_12) 102 103 /* GPSR1 */ 104 #define GPSR1_28 FM(CLKOUT) 105 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8) 106 #define GPSR1_26 F_(WE1_N, IP5_7_4) 107 #define GPSR1_25 F_(WE0_N, IP5_3_0) 108 #define GPSR1_24 F_(RD_WR_N, IP4_31_28) 109 #define GPSR1_23 F_(RD_N, IP4_27_24) 110 #define GPSR1_22 F_(BS_N, IP4_23_20) 111 #define GPSR1_21 F_(CS1_N, IP4_19_16) 112 #define GPSR1_20 F_(CS0_N, IP4_15_12) 113 #define GPSR1_19 F_(A19, IP4_11_8) 114 #define GPSR1_18 F_(A18, IP4_7_4) 115 #define GPSR1_17 F_(A17, IP4_3_0) 116 #define GPSR1_16 F_(A16, IP3_31_28) 117 #define GPSR1_15 F_(A15, IP3_27_24) 118 #define GPSR1_14 F_(A14, IP3_23_20) 119 #define GPSR1_13 F_(A13, IP3_19_16) 120 #define GPSR1_12 F_(A12, IP3_15_12) 121 #define GPSR1_11 F_(A11, IP3_11_8) 122 #define GPSR1_10 F_(A10, IP3_7_4) 123 #define GPSR1_9 F_(A9, IP3_3_0) 124 #define GPSR1_8 F_(A8, IP2_31_28) 125 #define GPSR1_7 F_(A7, IP2_27_24) 126 #define GPSR1_6 F_(A6, IP2_23_20) 127 #define GPSR1_5 F_(A5, IP2_19_16) 128 #define GPSR1_4 F_(A4, IP2_15_12) 129 #define GPSR1_3 F_(A3, IP2_11_8) 130 #define GPSR1_2 F_(A2, IP2_7_4) 131 #define GPSR1_1 F_(A1, IP2_3_0) 132 #define GPSR1_0 F_(A0, IP1_31_28) 133 134 /* GPSR2 */ 135 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20) 136 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16) 137 #define GPSR2_12 F_(AVB_LINK, IP0_15_12) 138 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8) 139 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4) 140 #define GPSR2_9 F_(AVB_MDC, IP0_3_0) 141 #define GPSR2_8 F_(PWM2_A, IP1_27_24) 142 #define GPSR2_7 F_(PWM1_A, IP1_23_20) 143 #define GPSR2_6 F_(PWM0, IP1_19_16) 144 #define GPSR2_5 F_(IRQ5, IP1_15_12) 145 #define GPSR2_4 F_(IRQ4, IP1_11_8) 146 #define GPSR2_3 F_(IRQ3, IP1_7_4) 147 #define GPSR2_2 F_(IRQ2, IP1_3_0) 148 #define GPSR2_1 F_(IRQ1, IP0_31_28) 149 #define GPSR2_0 F_(IRQ0, IP0_27_24) 150 151 /* GPSR3 */ 152 #define GPSR3_15 F_(SD1_WP, IP11_23_20) 153 #define GPSR3_14 F_(SD1_CD, IP11_19_16) 154 #define GPSR3_13 F_(SD0_WP, IP11_15_12) 155 #define GPSR3_12 F_(SD0_CD, IP11_11_8) 156 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28) 157 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24) 158 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20) 159 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16) 160 #define GPSR3_7 F_(SD1_CMD, IP8_15_12) 161 #define GPSR3_6 F_(SD1_CLK, IP8_11_8) 162 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4) 163 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0) 164 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28) 165 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24) 166 #define GPSR3_1 F_(SD0_CMD, IP7_23_20) 167 #define GPSR3_0 F_(SD0_CLK, IP7_19_16) 168 169 /* GPSR4 */ 170 #define GPSR4_17 F_(SD3_DS, IP11_7_4) 171 #define GPSR4_16 F_(SD3_DAT7, IP11_3_0) 172 #define GPSR4_15 F_(SD3_DAT6, IP10_31_28) 173 #define GPSR4_14 F_(SD3_DAT5, IP10_27_24) 174 #define GPSR4_13 F_(SD3_DAT4, IP10_23_20) 175 #define GPSR4_12 F_(SD3_DAT3, IP10_19_16) 176 #define GPSR4_11 F_(SD3_DAT2, IP10_15_12) 177 #define GPSR4_10 F_(SD3_DAT1, IP10_11_8) 178 #define GPSR4_9 F_(SD3_DAT0, IP10_7_4) 179 #define GPSR4_8 F_(SD3_CMD, IP10_3_0) 180 #define GPSR4_7 F_(SD3_CLK, IP9_31_28) 181 #define GPSR4_6 F_(SD2_DS, IP9_27_24) 182 #define GPSR4_5 F_(SD2_DAT3, IP9_23_20) 183 #define GPSR4_4 F_(SD2_DAT2, IP9_19_16) 184 #define GPSR4_3 F_(SD2_DAT1, IP9_15_12) 185 #define GPSR4_2 F_(SD2_DAT0, IP9_11_8) 186 #define GPSR4_1 F_(SD2_CMD, IP9_7_4) 187 #define GPSR4_0 F_(SD2_CLK, IP9_3_0) 188 189 /* GPSR5 */ 190 #define GPSR5_25 F_(MLB_DAT, IP14_19_16) 191 #define GPSR5_24 F_(MLB_SIG, IP14_15_12) 192 #define GPSR5_23 F_(MLB_CLK, IP14_11_8) 193 #define GPSR5_22 FM(MSIOF0_RXD) 194 #define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4) 195 #define GPSR5_20 FM(MSIOF0_TXD) 196 #define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0) 197 #define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28) 198 #define GPSR5_17 FM(MSIOF0_SCK) 199 #define GPSR5_16 F_(HRTS0_N, IP13_27_24) 200 #define GPSR5_15 F_(HCTS0_N, IP13_23_20) 201 #define GPSR5_14 F_(HTX0, IP13_19_16) 202 #define GPSR5_13 F_(HRX0, IP13_15_12) 203 #define GPSR5_12 F_(HSCK0, IP13_11_8) 204 #define GPSR5_11 F_(RX2_A, IP13_7_4) 205 #define GPSR5_10 F_(TX2_A, IP13_3_0) 206 #define GPSR5_9 F_(SCK2, IP12_31_28) 207 #define GPSR5_8 F_(RTS1_N, IP12_27_24) 208 #define GPSR5_7 F_(CTS1_N, IP12_23_20) 209 #define GPSR5_6 F_(TX1_A, IP12_19_16) 210 #define GPSR5_5 F_(RX1_A, IP12_15_12) 211 #define GPSR5_4 F_(RTS0_N, IP12_11_8) 212 #define GPSR5_3 F_(CTS0_N, IP12_7_4) 213 #define GPSR5_2 F_(TX0, IP12_3_0) 214 #define GPSR5_1 F_(RX0, IP11_31_28) 215 #define GPSR5_0 F_(SCK0, IP11_27_24) 216 217 /* GPSR6 */ 218 #define GPSR6_31 F_(GP6_31, IP18_7_4) 219 #define GPSR6_30 F_(GP6_30, IP18_3_0) 220 #define GPSR6_29 F_(USB30_OVC, IP17_31_28) 221 #define GPSR6_28 F_(USB30_PWEN, IP17_27_24) 222 #define GPSR6_27 F_(USB1_OVC, IP17_23_20) 223 #define GPSR6_26 F_(USB1_PWEN, IP17_19_16) 224 #define GPSR6_25 F_(USB0_OVC, IP17_15_12) 225 #define GPSR6_24 F_(USB0_PWEN, IP17_11_8) 226 #define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4) 227 #define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0) 228 #define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28) 229 #define GPSR6_20 F_(SSI_SDATA8, IP16_27_24) 230 #define GPSR6_19 F_(SSI_SDATA7, IP16_23_20) 231 #define GPSR6_18 F_(SSI_WS78, IP16_19_16) 232 #define GPSR6_17 F_(SSI_SCK78, IP16_15_12) 233 #define GPSR6_16 F_(SSI_SDATA6, IP16_11_8) 234 #define GPSR6_15 F_(SSI_WS6, IP16_7_4) 235 #define GPSR6_14 F_(SSI_SCK6, IP16_3_0) 236 #define GPSR6_13 FM(SSI_SDATA5) 237 #define GPSR6_12 FM(SSI_WS5) 238 #define GPSR6_11 FM(SSI_SCK5) 239 #define GPSR6_10 F_(SSI_SDATA4, IP15_31_28) 240 #define GPSR6_9 F_(SSI_WS4, IP15_27_24) 241 #define GPSR6_8 F_(SSI_SCK4, IP15_23_20) 242 #define GPSR6_7 F_(SSI_SDATA3, IP15_19_16) 243 #define GPSR6_6 F_(SSI_WS349, IP15_15_12) 244 #define GPSR6_5 F_(SSI_SCK349, IP15_11_8) 245 #define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4) 246 #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0) 247 #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28) 248 #define GPSR6_1 F_(SSI_WS01239, IP14_27_24) 249 #define GPSR6_0 F_(SSI_SCK01239, IP14_23_20) 250 251 /* GPSR7 */ 252 #define GPSR7_3 FM(GP7_03) 253 #define GPSR7_2 FM(GP7_02) 254 #define GPSR7_1 FM(AVS2) 255 #define GPSR7_0 FM(AVS1) 256 257 258 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 259 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 260 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 261 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 262 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 263 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 264 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 265 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 266 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 267 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 268 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 269 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 270 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 271 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 272 #define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 273 #define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 274 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 275 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 276 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 277 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 278 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 279 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 280 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 281 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 282 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 283 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 284 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 285 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 286 287 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 288 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 289 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 290 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 291 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 292 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 293 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 294 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 295 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 296 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 297 #define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 298 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 299 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 300 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 301 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 302 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 303 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 304 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 305 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 306 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 307 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 308 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 309 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 310 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 311 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 312 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 313 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 314 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 315 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 316 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 317 318 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 319 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 320 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 321 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 322 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 323 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 324 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 325 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 326 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 327 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 328 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 329 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 330 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 331 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 332 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 333 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 334 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 335 #define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 336 #define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 337 #define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 338 #define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 339 #define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 340 #define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 341 #define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 342 #define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 343 #define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 344 #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 345 #define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 346 #define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 347 #define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 348 #define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 349 #define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 350 #define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 351 #define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 352 #define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 353 354 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 355 #define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 356 #define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 357 #define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 358 #define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 359 #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 360 #define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 361 #define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 362 #define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 363 #define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 364 #define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 365 #define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 366 #define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 367 #define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 368 #define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 369 #define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 370 #define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 371 #define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 372 #define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 373 #define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 374 #define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 375 #define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0) 376 #define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 377 #define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 378 #define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 379 #define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 380 #define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 381 #define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 382 #define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 383 384 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 385 #define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 386 #define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 387 #define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 388 #define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 389 #define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 390 #define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 391 #define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 392 #define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 393 #define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 394 #define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 395 #define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 396 #define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 397 #define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 398 #define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 399 #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 400 #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 401 #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 402 #define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 403 #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 404 #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0) 405 #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0) 406 #define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0) 407 #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0) 408 #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0) 409 #define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 410 #define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0) 411 #define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0) 412 413 #define PINMUX_GPSR \ 414 \ 415 GPSR6_31 \ 416 GPSR6_30 \ 417 GPSR6_29 \ 418 GPSR1_28 GPSR6_28 \ 419 GPSR1_27 GPSR6_27 \ 420 GPSR1_26 GPSR6_26 \ 421 GPSR1_25 GPSR5_25 GPSR6_25 \ 422 GPSR1_24 GPSR5_24 GPSR6_24 \ 423 GPSR1_23 GPSR5_23 GPSR6_23 \ 424 GPSR1_22 GPSR5_22 GPSR6_22 \ 425 GPSR1_21 GPSR5_21 GPSR6_21 \ 426 GPSR1_20 GPSR5_20 GPSR6_20 \ 427 GPSR1_19 GPSR5_19 GPSR6_19 \ 428 GPSR1_18 GPSR5_18 GPSR6_18 \ 429 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \ 430 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \ 431 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \ 432 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \ 433 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \ 434 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \ 435 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \ 436 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \ 437 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \ 438 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \ 439 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \ 440 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \ 441 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \ 442 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \ 443 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \ 444 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \ 445 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \ 446 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0 447 448 #define PINMUX_IPSR \ 449 \ 450 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \ 451 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \ 452 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \ 453 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \ 454 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \ 455 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \ 456 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ 457 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \ 458 \ 459 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ 460 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ 461 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ 462 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \ 463 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ 464 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ 465 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ 466 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ 467 \ 468 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \ 469 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \ 470 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \ 471 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \ 472 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \ 473 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \ 474 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \ 475 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \ 476 \ 477 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \ 478 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \ 479 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \ 480 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \ 481 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \ 482 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \ 483 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \ 484 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \ 485 \ 486 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \ 487 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \ 488 FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \ 489 FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \ 490 FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \ 491 FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \ 492 FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \ 493 FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 494 495 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 496 #define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0) 497 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3) 498 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0) 499 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1) 500 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1) 501 #define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1) 502 #define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1) 503 #define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1) 504 #define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3) 505 #define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1) 506 #define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0) 507 #define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1) 508 #define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1) 509 #define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1) 510 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0) 511 #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0) 512 #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) 513 #define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3) 514 515 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 516 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3) 517 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0) 518 #define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1) 519 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3) 520 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0) 521 #define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1) 522 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1) 523 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3) 524 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1) 525 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0) 526 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1) 527 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1) 528 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1) 529 #define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1) 530 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1) 531 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1) 532 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1) 533 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1) 534 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1) 535 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1) 536 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1) 537 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1) 538 539 /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 540 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1) 541 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1) 542 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1) 543 #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3) 544 #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) 545 #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 546 #define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1) 547 #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1) 548 #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1) 549 #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1) 550 #define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1) 551 #define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1) 552 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1) 553 554 #define PINMUX_MOD_SELS \ 555 \ 556 MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \ 557 MOD_SEL2_30 \ 558 MOD_SEL1_29_28_27 MOD_SEL2_29 \ 559 MOD_SEL0_28_27 MOD_SEL2_28_27 \ 560 MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \ 561 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \ 562 MOD_SEL0_23 MOD_SEL1_23_22_21 \ 563 MOD_SEL0_22 MOD_SEL2_22 \ 564 MOD_SEL0_21 MOD_SEL2_21 \ 565 MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \ 566 MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \ 567 MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \ 568 MOD_SEL2_17 \ 569 MOD_SEL0_16 MOD_SEL1_16 \ 570 MOD_SEL1_15_14 \ 571 MOD_SEL0_14_13 \ 572 MOD_SEL1_13 \ 573 MOD_SEL0_12 MOD_SEL1_12 \ 574 MOD_SEL0_11 MOD_SEL1_11 \ 575 MOD_SEL0_10 MOD_SEL1_10 \ 576 MOD_SEL0_9_8 MOD_SEL1_9 \ 577 MOD_SEL0_7_6 \ 578 MOD_SEL1_6 \ 579 MOD_SEL0_5 MOD_SEL1_5 \ 580 MOD_SEL0_4_3 MOD_SEL1_4 \ 581 MOD_SEL1_3 \ 582 MOD_SEL1_2 \ 583 MOD_SEL1_1 \ 584 MOD_SEL1_0 MOD_SEL2_0 585 586 /* 587 * These pins are not able to be muxed but have other properties 588 * that can be set, such as drive-strength or pull-up/pull-down enable. 589 */ 590 #define PINMUX_STATIC \ 591 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \ 592 FM(QSPI0_IO2) FM(QSPI0_IO3) \ 593 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \ 594 FM(QSPI1_IO2) FM(QSPI1_IO3) \ 595 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \ 596 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \ 597 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \ 598 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \ 599 FM(PRESETOUT) \ 600 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN3) \ 601 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR) 602 603 #define PINMUX_PHYS \ 604 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5) 605 606 enum { 607 PINMUX_RESERVED = 0, 608 609 PINMUX_DATA_BEGIN, 610 GP_ALL(DATA), 611 PINMUX_DATA_END, 612 613 #define F_(x, y) 614 #define FM(x) FN_##x, 615 PINMUX_FUNCTION_BEGIN, 616 GP_ALL(FN), 617 PINMUX_GPSR 618 PINMUX_IPSR 619 PINMUX_MOD_SELS 620 PINMUX_FUNCTION_END, 621 #undef F_ 622 #undef FM 623 624 #define F_(x, y) 625 #define FM(x) x##_MARK, 626 PINMUX_MARK_BEGIN, 627 PINMUX_GPSR 628 PINMUX_IPSR 629 PINMUX_MOD_SELS 630 PINMUX_STATIC 631 PINMUX_PHYS 632 PINMUX_MARK_END, 633 #undef F_ 634 #undef FM 635 }; 636 637 static const u16 pinmux_data[] = { 638 PINMUX_DATA_GP_ALL(), 639 640 PINMUX_SINGLE(AVS1), 641 PINMUX_SINGLE(AVS2), 642 PINMUX_SINGLE(CLKOUT), 643 PINMUX_SINGLE(GP7_03), 644 PINMUX_SINGLE(GP7_02), 645 PINMUX_SINGLE(MSIOF0_RXD), 646 PINMUX_SINGLE(MSIOF0_SCK), 647 PINMUX_SINGLE(MSIOF0_TXD), 648 PINMUX_SINGLE(SSI_SCK5), 649 PINMUX_SINGLE(SSI_SDATA5), 650 PINMUX_SINGLE(SSI_WS5), 651 652 /* IPSR0 */ 653 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC), 654 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2), 655 656 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC), 657 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2), 658 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0), 659 660 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT), 661 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2), 662 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0), 663 664 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK), 665 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2), 666 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0), 667 PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A), 668 669 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0), 670 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), 671 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), 672 PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1), 673 674 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0), 675 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), 676 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), 677 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1), 678 679 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0), 680 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB), 681 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE), 682 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1), 683 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1), 684 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1), 685 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4), 686 687 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1), 688 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA), 689 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP), 690 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1), 691 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1), 692 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1), 693 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4), 694 695 /* IPSR1 */ 696 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2), 697 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE), 698 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE), 699 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1), 700 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1), 701 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4), 702 703 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3), 704 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE), 705 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1), 706 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1), 707 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1), 708 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4), 709 710 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4), 711 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS), 712 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC), 713 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1), 714 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1), 715 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4), 716 717 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5), 718 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE), 719 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC), 720 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1), 721 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1), 722 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B), 723 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4), 724 725 PINMUX_IPSR_GPSR(IP1_19_16, PWM0), 726 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS), 727 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1), 728 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1), 729 730 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0), 731 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), 732 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1), 733 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1), 734 PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1), 735 736 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0), 737 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), 738 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1), 739 PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1), 740 741 PINMUX_IPSR_GPSR(IP1_31_28, A0), 742 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16), 743 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1), 744 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8), 745 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0), 746 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0), 747 748 /* IPSR2 */ 749 PINMUX_IPSR_GPSR(IP2_3_0, A1), 750 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17), 751 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1), 752 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9), 753 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1), 754 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0), 755 756 PINMUX_IPSR_GPSR(IP2_7_4, A2), 757 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18), 758 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1), 759 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10), 760 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2), 761 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0), 762 763 PINMUX_IPSR_GPSR(IP2_11_8, A3), 764 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19), 765 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1), 766 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11), 767 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3), 768 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0), 769 770 PINMUX_IPSR_GPSR(IP2_15_12, A4), 771 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20), 772 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1), 773 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12), 774 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12), 775 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4), 776 777 PINMUX_IPSR_GPSR(IP2_19_16, A5), 778 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21), 779 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1), 780 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1), 781 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13), 782 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13), 783 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5), 784 785 PINMUX_IPSR_GPSR(IP2_23_20, A6), 786 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22), 787 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0), 788 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1), 789 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14), 790 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14), 791 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6), 792 793 PINMUX_IPSR_GPSR(IP2_27_24, A7), 794 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23), 795 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0), 796 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1), 797 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15), 798 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15), 799 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7), 800 801 PINMUX_IPSR_GPSR(IP2_31_28, A8), 802 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1), 803 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0), 804 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1), 805 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0), 806 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1), 807 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1), 808 809 /* IPSR3 */ 810 PINMUX_IPSR_GPSR(IP3_3_0, A9), 811 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0), 812 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1), 813 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N), 814 815 PINMUX_IPSR_GPSR(IP3_7_4, A10), 816 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0), 817 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1), 818 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N), 819 820 PINMUX_IPSR_GPSR(IP3_11_8, A11), 821 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1), 822 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0), 823 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1), 824 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4), 825 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD), 826 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0), 827 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1), 828 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1), 829 830 PINMUX_IPSR_GPSR(IP3_15_12, A12), 831 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12), 832 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2), 833 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0), 834 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8), 835 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4), 836 837 PINMUX_IPSR_GPSR(IP3_19_16, A13), 838 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13), 839 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2), 840 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0), 841 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9), 842 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5), 843 844 PINMUX_IPSR_GPSR(IP3_23_20, A14), 845 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14), 846 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2), 847 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N), 848 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10), 849 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6), 850 851 PINMUX_IPSR_GPSR(IP3_27_24, A15), 852 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15), 853 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2), 854 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N), 855 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11), 856 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7), 857 858 PINMUX_IPSR_GPSR(IP3_31_28, A16), 859 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8), 860 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD), 861 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0), 862 863 /* IPSR4 */ 864 PINMUX_IPSR_GPSR(IP4_3_0, A17), 865 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9), 866 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N), 867 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1), 868 869 PINMUX_IPSR_GPSR(IP4_7_4, A18), 870 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10), 871 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N), 872 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2), 873 874 PINMUX_IPSR_GPSR(IP4_11_8, A19), 875 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11), 876 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB), 877 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3), 878 879 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N), 880 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB), 881 882 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N), 883 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK), 884 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1), 885 886 PINMUX_IPSR_GPSR(IP4_23_20, BS_N), 887 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS), 888 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3), 889 PINMUX_IPSR_GPSR(IP4_23_20, SCK3), 890 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3), 891 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX), 892 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX), 893 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0), 894 895 PINMUX_IPSR_GPSR(IP4_27_24, RD_N), 896 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3), 897 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0), 898 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0), 899 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0), 900 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0), 901 902 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N), 903 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3), 904 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0), 905 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0), 906 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0), 907 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0), 908 909 /* IPSR5 */ 910 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N), 911 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3), 912 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N), 913 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N), 914 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1), 915 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK), 916 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0), 917 918 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N), 919 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3), 920 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N), 921 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N), 922 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1), 923 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX), 924 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX), 925 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0), 926 927 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0), 928 PINMUX_IPSR_GPSR(IP5_11_8, QCLK), 929 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK), 930 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0), 931 932 PINMUX_IPSR_GPSR(IP5_15_12, D0), 933 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1), 934 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0), 935 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16), 936 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0), 937 938 PINMUX_IPSR_GPSR(IP5_19_16, D1), 939 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1), 940 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0), 941 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17), 942 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1), 943 944 PINMUX_IPSR_GPSR(IP5_23_20, D2), 945 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0), 946 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18), 947 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2), 948 949 PINMUX_IPSR_GPSR(IP5_27_24, D3), 950 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0), 951 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19), 952 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3), 953 954 PINMUX_IPSR_GPSR(IP5_31_28, D4), 955 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1), 956 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20), 957 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4), 958 959 /* IPSR6 */ 960 PINMUX_IPSR_GPSR(IP6_3_0, D5), 961 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1), 962 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21), 963 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5), 964 965 PINMUX_IPSR_GPSR(IP6_7_4, D6), 966 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1), 967 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22), 968 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6), 969 970 PINMUX_IPSR_GPSR(IP6_11_8, D7), 971 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1), 972 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23), 973 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7), 974 975 PINMUX_IPSR_GPSR(IP6_15_12, D8), 976 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0), 977 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3), 978 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2), 979 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0), 980 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0), 981 982 PINMUX_IPSR_GPSR(IP6_19_16, D9), 983 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1), 984 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3), 985 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0), 986 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1), 987 988 PINMUX_IPSR_GPSR(IP6_23_20, D10), 989 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2), 990 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3), 991 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1), 992 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0), 993 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2), 994 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2), 995 996 PINMUX_IPSR_GPSR(IP6_27_24, D11), 997 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3), 998 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3), 999 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1), 1000 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0), 1001 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2), 1002 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3), 1003 1004 PINMUX_IPSR_GPSR(IP6_31_28, D12), 1005 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4), 1006 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3), 1007 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2), 1008 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0), 1009 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4), 1010 1011 /* IPSR7 */ 1012 PINMUX_IPSR_GPSR(IP7_3_0, D13), 1013 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5), 1014 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3), 1015 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2), 1016 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0), 1017 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5), 1018 1019 PINMUX_IPSR_GPSR(IP7_7_4, D14), 1020 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6), 1021 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0), 1022 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2), 1023 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0), 1024 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6), 1025 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2), 1026 1027 PINMUX_IPSR_GPSR(IP7_11_8, D15), 1028 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7), 1029 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0), 1030 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2), 1031 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0), 1032 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7), 1033 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2), 1034 1035 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK), 1036 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4), 1037 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1), 1038 1039 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD), 1040 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4), 1041 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1), 1042 1043 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0), 1044 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4), 1045 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1), 1046 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1), 1047 1048 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1), 1049 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4), 1050 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1), 1051 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1), 1052 1053 /* IPSR8 */ 1054 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2), 1055 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4), 1056 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1), 1057 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1), 1058 1059 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3), 1060 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4), 1061 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1), 1062 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1), 1063 1064 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK), 1065 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6), 1066 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0), 1067 1068 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD), 1069 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6), 1070 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1), 1071 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0), 1072 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1), 1073 1074 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0), 1075 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4), 1076 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6), 1077 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1), 1078 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1), 1079 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1), 1080 1081 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1), 1082 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5), 1083 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6), 1084 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1), 1085 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1), 1086 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1), 1087 1088 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2), 1089 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6), 1090 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6), 1091 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1), 1092 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1), 1093 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1), 1094 1095 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3), 1096 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7), 1097 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6), 1098 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1), 1099 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1), 1100 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1), 1101 1102 /* IPSR9 */ 1103 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK), 1104 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8), 1105 1106 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD), 1107 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9), 1108 1109 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0), 1110 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10), 1111 1112 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1), 1113 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11), 1114 1115 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2), 1116 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12), 1117 1118 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3), 1119 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13), 1120 1121 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS), 1122 PINMUX_IPSR_GPSR(IP9_27_24, NFALE), 1123 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B), 1124 1125 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK), 1126 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N), 1127 1128 /* IPSR10 */ 1129 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD), 1130 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N), 1131 1132 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0), 1133 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0), 1134 1135 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1), 1136 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1), 1137 1138 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2), 1139 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2), 1140 1141 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3), 1142 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3), 1143 1144 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4), 1145 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0), 1146 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4), 1147 1148 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5), 1149 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0), 1150 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5), 1151 1152 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6), 1153 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD), 1154 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6), 1155 1156 /* IPSR11 */ 1157 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7), 1158 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP), 1159 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7), 1160 1161 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS), 1162 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE), 1163 1164 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD), 1165 PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0), 1166 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1), 1167 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0), 1168 1169 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP), 1170 PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0), 1171 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1), 1172 1173 PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0), 1174 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0), 1175 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1), 1176 PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1), 1177 1178 PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0), 1179 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0), 1180 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1), 1181 PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1), 1182 1183 PINMUX_IPSR_GPSR(IP11_27_24, SCK0), 1184 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1), 1185 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1), 1186 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1), 1187 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0), 1188 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1), 1189 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2), 1190 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1), 1191 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2), 1192 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1), 1193 1194 PINMUX_IPSR_GPSR(IP11_31_28, RX0), 1195 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1), 1196 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2), 1197 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2), 1198 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1), 1199 1200 /* IPSR12 */ 1201 PINMUX_IPSR_GPSR(IP12_3_0, TX0), 1202 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1), 1203 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2), 1204 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2), 1205 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1), 1206 1207 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N), 1208 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1), 1209 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1), 1210 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2), 1211 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2), 1212 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1), 1213 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C), 1214 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP), 1215 1216 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N), 1217 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1), 1218 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), 1219 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1), 1220 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0), 1221 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2), 1222 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1), 1223 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1), 1224 1225 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0), 1226 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0), 1227 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2), 1228 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2), 1229 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2), 1230 1231 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0), 1232 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0), 1233 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2), 1234 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2), 1235 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2), 1236 1237 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N), 1238 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0), 1239 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1), 1240 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2), 1241 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2), 1242 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1), 1243 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA), 1244 1245 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N), 1246 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0), 1247 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1), 1248 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2), 1249 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2), 1250 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1), 1251 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0), 1252 1253 PINMUX_IPSR_GPSR(IP12_31_28, SCK2), 1254 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1), 1255 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1), 1256 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2), 1257 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2), 1258 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1), 1259 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK), 1260 1261 /* IPSR13 */ 1262 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0), 1263 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1), 1264 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0), 1265 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0), 1266 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2), 1267 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N), 1268 1269 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0), 1270 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1), 1271 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0), 1272 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0), 1273 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2), 1274 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N), 1275 1276 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0), 1277 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3), 1278 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0), 1279 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1), 1280 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3), 1281 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3), 1282 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2), 1283 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1), 1284 1285 PINMUX_IPSR_GPSR(IP13_15_12, HRX0), 1286 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3), 1287 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1), 1288 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3), 1289 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3), 1290 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2), 1291 1292 PINMUX_IPSR_GPSR(IP13_19_16, HTX0), 1293 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3), 1294 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1), 1295 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3), 1296 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3), 1297 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2), 1298 1299 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N), 1300 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1), 1301 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3), 1302 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0), 1303 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3), 1304 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3), 1305 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2), 1306 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A), 1307 1308 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N), 1309 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1), 1310 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3), 1311 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0), 1312 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3), 1313 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0), 1314 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A), 1315 1316 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC), 1317 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A), 1318 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1), 1319 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3), 1320 1321 /* IPSR14 */ 1322 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1), 1323 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0), 1324 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0), 1325 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2), 1326 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0), 1327 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2), 1328 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A), 1329 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1), 1330 1331 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2), 1332 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0), 1333 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3), 1334 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0), 1335 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0), 1336 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3), 1337 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D), 1338 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1), 1339 1340 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK), 1341 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5), 1342 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1), 1343 1344 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG), 1345 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1), 1346 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5), 1347 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1), 1348 1349 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT), 1350 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1), 1351 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5), 1352 1353 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239), 1354 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5), 1355 1356 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239), 1357 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5), 1358 1359 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0), 1360 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5), 1361 1362 /* IPSR15 */ 1363 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0), 1364 1365 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0), 1366 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1), 1367 1368 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349), 1369 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0), 1370 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0), 1371 1372 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349), 1373 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0), 1374 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0), 1375 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0), 1376 1377 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3), 1378 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0), 1379 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0), 1380 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0), 1381 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0), 1382 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0), 1383 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0), 1384 1385 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4), 1386 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0), 1387 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0), 1388 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0), 1389 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0), 1390 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0), 1391 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0), 1392 1393 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4), 1394 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0), 1395 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0), 1396 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0), 1397 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0), 1398 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0), 1399 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0), 1400 1401 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4), 1402 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0), 1403 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0), 1404 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0), 1405 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0), 1406 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0), 1407 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0), 1408 1409 /* IPSR16 */ 1410 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6), 1411 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3), 1412 1413 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6), 1414 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3), 1415 1416 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6), 1417 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3), 1418 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A), 1419 1420 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78), 1421 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1), 1422 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2), 1423 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0), 1424 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0), 1425 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0), 1426 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0), 1427 1428 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78), 1429 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1), 1430 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2), 1431 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0), 1432 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0), 1433 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0), 1434 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0), 1435 1436 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7), 1437 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1), 1438 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2), 1439 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0), 1440 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0), 1441 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0), 1442 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0), 1443 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0), 1444 1445 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8), 1446 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1), 1447 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2), 1448 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0), 1449 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0), 1450 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0), 1451 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0), 1452 1453 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0), 1454 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1), 1455 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2), 1456 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0), 1457 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1), 1458 PINMUX_IPSR_GPSR(IP16_31_28, SCK1), 1459 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0), 1460 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0), 1461 1462 /* IPSR17 */ 1463 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0), 1464 1465 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1), 1466 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0), 1467 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3), 1468 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0), 1469 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0), 1470 1471 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN), 1472 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2), 1473 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3), 1474 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3), 1475 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1), 1476 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1), 1477 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2), 1478 1479 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC), 1480 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2), 1481 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3), 1482 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3), 1483 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1), 1484 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2), 1485 1486 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN), 1487 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2), 1488 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0), 1489 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4), 1490 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4), 1491 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1), 1492 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1), 1493 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0), 1494 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2), 1495 1496 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC), 1497 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2), 1498 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0), 1499 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4), 1500 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4), 1501 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1), 1502 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1), 1503 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1), 1504 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2), 1505 1506 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN), 1507 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B), 1508 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1), 1509 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3), 1510 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3), 1511 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4), 1512 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1), 1513 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1), 1514 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0), 1515 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2), 1516 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2), 1517 1518 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC), 1519 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B), 1520 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1), 1521 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3), 1522 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3), 1523 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4), 1524 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1), 1525 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N), 1526 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1), 1527 1528 /* IPSR18 */ 1529 PINMUX_IPSR_GPSR(IP18_3_0, GP6_30), 1530 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B), 1531 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1), 1532 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4), 1533 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4), 1534 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1), 1535 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2), 1536 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2), 1537 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3), 1538 1539 PINMUX_IPSR_GPSR(IP18_7_4, GP6_31), 1540 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B), 1541 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1), 1542 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4), 1543 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4), 1544 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1), 1545 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3), 1546 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2), 1547 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3), 1548 1549 /* 1550 * Static pins can not be muxed between different functions but 1551 * still need mark entries in the pinmux list. Add each static 1552 * pin to the list without an associated function. The sh-pfc 1553 * core will do the right thing and skip trying to mux the pin 1554 * while still applying configuration to it. 1555 */ 1556 #define FM(x) PINMUX_DATA(x##_MARK, 0), 1557 PINMUX_STATIC 1558 #undef FM 1559 }; 1560 1561 /* 1562 * Pins not associated with a GPIO port. 1563 */ 1564 enum { 1565 GP_ASSIGN_LAST(), 1566 NOGP_ALL(), 1567 }; 1568 1569 static const struct sh_pfc_pin pinmux_pins[] = { 1570 PINMUX_GPIO_GP_ALL(), 1571 PINMUX_NOGP_ALL(), 1572 }; 1573 1574 /* - AUDIO CLOCK ------------------------------------------------------------ */ 1575 static const unsigned int audio_clk_a_a_pins[] = { 1576 /* CLK A */ 1577 RCAR_GP_PIN(6, 22), 1578 }; 1579 static const unsigned int audio_clk_a_a_mux[] = { 1580 AUDIO_CLKA_A_MARK, 1581 }; 1582 static const unsigned int audio_clk_a_b_pins[] = { 1583 /* CLK A */ 1584 RCAR_GP_PIN(5, 4), 1585 }; 1586 static const unsigned int audio_clk_a_b_mux[] = { 1587 AUDIO_CLKA_B_MARK, 1588 }; 1589 static const unsigned int audio_clk_a_c_pins[] = { 1590 /* CLK A */ 1591 RCAR_GP_PIN(5, 19), 1592 }; 1593 static const unsigned int audio_clk_a_c_mux[] = { 1594 AUDIO_CLKA_C_MARK, 1595 }; 1596 static const unsigned int audio_clk_b_a_pins[] = { 1597 /* CLK B */ 1598 RCAR_GP_PIN(5, 12), 1599 }; 1600 static const unsigned int audio_clk_b_a_mux[] = { 1601 AUDIO_CLKB_A_MARK, 1602 }; 1603 static const unsigned int audio_clk_b_b_pins[] = { 1604 /* CLK B */ 1605 RCAR_GP_PIN(6, 23), 1606 }; 1607 static const unsigned int audio_clk_b_b_mux[] = { 1608 AUDIO_CLKB_B_MARK, 1609 }; 1610 static const unsigned int audio_clk_c_a_pins[] = { 1611 /* CLK C */ 1612 RCAR_GP_PIN(5, 21), 1613 }; 1614 static const unsigned int audio_clk_c_a_mux[] = { 1615 AUDIO_CLKC_A_MARK, 1616 }; 1617 static const unsigned int audio_clk_c_b_pins[] = { 1618 /* CLK C */ 1619 RCAR_GP_PIN(5, 0), 1620 }; 1621 static const unsigned int audio_clk_c_b_mux[] = { 1622 AUDIO_CLKC_B_MARK, 1623 }; 1624 static const unsigned int audio_clkout_a_pins[] = { 1625 /* CLKOUT */ 1626 RCAR_GP_PIN(5, 18), 1627 }; 1628 static const unsigned int audio_clkout_a_mux[] = { 1629 AUDIO_CLKOUT_A_MARK, 1630 }; 1631 static const unsigned int audio_clkout_b_pins[] = { 1632 /* CLKOUT */ 1633 RCAR_GP_PIN(6, 28), 1634 }; 1635 static const unsigned int audio_clkout_b_mux[] = { 1636 AUDIO_CLKOUT_B_MARK, 1637 }; 1638 static const unsigned int audio_clkout_c_pins[] = { 1639 /* CLKOUT */ 1640 RCAR_GP_PIN(5, 3), 1641 }; 1642 static const unsigned int audio_clkout_c_mux[] = { 1643 AUDIO_CLKOUT_C_MARK, 1644 }; 1645 static const unsigned int audio_clkout_d_pins[] = { 1646 /* CLKOUT */ 1647 RCAR_GP_PIN(5, 21), 1648 }; 1649 static const unsigned int audio_clkout_d_mux[] = { 1650 AUDIO_CLKOUT_D_MARK, 1651 }; 1652 static const unsigned int audio_clkout1_a_pins[] = { 1653 /* CLKOUT1 */ 1654 RCAR_GP_PIN(5, 15), 1655 }; 1656 static const unsigned int audio_clkout1_a_mux[] = { 1657 AUDIO_CLKOUT1_A_MARK, 1658 }; 1659 static const unsigned int audio_clkout1_b_pins[] = { 1660 /* CLKOUT1 */ 1661 RCAR_GP_PIN(6, 29), 1662 }; 1663 static const unsigned int audio_clkout1_b_mux[] = { 1664 AUDIO_CLKOUT1_B_MARK, 1665 }; 1666 static const unsigned int audio_clkout2_a_pins[] = { 1667 /* CLKOUT2 */ 1668 RCAR_GP_PIN(5, 16), 1669 }; 1670 static const unsigned int audio_clkout2_a_mux[] = { 1671 AUDIO_CLKOUT2_A_MARK, 1672 }; 1673 static const unsigned int audio_clkout2_b_pins[] = { 1674 /* CLKOUT2 */ 1675 RCAR_GP_PIN(6, 30), 1676 }; 1677 static const unsigned int audio_clkout2_b_mux[] = { 1678 AUDIO_CLKOUT2_B_MARK, 1679 }; 1680 1681 static const unsigned int audio_clkout3_a_pins[] = { 1682 /* CLKOUT3 */ 1683 RCAR_GP_PIN(5, 19), 1684 }; 1685 static const unsigned int audio_clkout3_a_mux[] = { 1686 AUDIO_CLKOUT3_A_MARK, 1687 }; 1688 static const unsigned int audio_clkout3_b_pins[] = { 1689 /* CLKOUT3 */ 1690 RCAR_GP_PIN(6, 31), 1691 }; 1692 static const unsigned int audio_clkout3_b_mux[] = { 1693 AUDIO_CLKOUT3_B_MARK, 1694 }; 1695 1696 /* - EtherAVB --------------------------------------------------------------- */ 1697 static const unsigned int avb_link_pins[] = { 1698 /* AVB_LINK */ 1699 RCAR_GP_PIN(2, 12), 1700 }; 1701 static const unsigned int avb_link_mux[] = { 1702 AVB_LINK_MARK, 1703 }; 1704 static const unsigned int avb_magic_pins[] = { 1705 /* AVB_MAGIC_ */ 1706 RCAR_GP_PIN(2, 10), 1707 }; 1708 static const unsigned int avb_magic_mux[] = { 1709 AVB_MAGIC_MARK, 1710 }; 1711 static const unsigned int avb_phy_int_pins[] = { 1712 /* AVB_PHY_INT */ 1713 RCAR_GP_PIN(2, 11), 1714 }; 1715 static const unsigned int avb_phy_int_mux[] = { 1716 AVB_PHY_INT_MARK, 1717 }; 1718 static const unsigned int avb_mdio_pins[] = { 1719 /* AVB_MDC, AVB_MDIO */ 1720 RCAR_GP_PIN(2, 9), PIN_AVB_MDIO, 1721 }; 1722 static const unsigned int avb_mdio_mux[] = { 1723 AVB_MDC_MARK, AVB_MDIO_MARK, 1724 }; 1725 static const unsigned int avb_mii_pins[] = { 1726 /* 1727 * AVB_TX_CTL, AVB_TXC, AVB_TD0, 1728 * AVB_TD1, AVB_TD2, AVB_TD3, 1729 * AVB_RX_CTL, AVB_RXC, AVB_RD0, 1730 * AVB_RD1, AVB_RD2, AVB_RD3, 1731 * AVB_TXCREFCLK 1732 */ 1733 PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0, 1734 PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3, 1735 PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0, 1736 PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3, 1737 PIN_AVB_TXCREFCLK, 1738 }; 1739 static const unsigned int avb_mii_mux[] = { 1740 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK, 1741 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK, 1742 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK, 1743 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK, 1744 AVB_TXCREFCLK_MARK, 1745 }; 1746 static const unsigned int avb_avtp_pps_pins[] = { 1747 /* AVB_AVTP_PPS */ 1748 RCAR_GP_PIN(2, 6), 1749 }; 1750 static const unsigned int avb_avtp_pps_mux[] = { 1751 AVB_AVTP_PPS_MARK, 1752 }; 1753 static const unsigned int avb_avtp_match_a_pins[] = { 1754 /* AVB_AVTP_MATCH_A */ 1755 RCAR_GP_PIN(2, 13), 1756 }; 1757 static const unsigned int avb_avtp_match_a_mux[] = { 1758 AVB_AVTP_MATCH_A_MARK, 1759 }; 1760 static const unsigned int avb_avtp_capture_a_pins[] = { 1761 /* AVB_AVTP_CAPTURE_A */ 1762 RCAR_GP_PIN(2, 14), 1763 }; 1764 static const unsigned int avb_avtp_capture_a_mux[] = { 1765 AVB_AVTP_CAPTURE_A_MARK, 1766 }; 1767 static const unsigned int avb_avtp_match_b_pins[] = { 1768 /* AVB_AVTP_MATCH_B */ 1769 RCAR_GP_PIN(1, 8), 1770 }; 1771 static const unsigned int avb_avtp_match_b_mux[] = { 1772 AVB_AVTP_MATCH_B_MARK, 1773 }; 1774 static const unsigned int avb_avtp_capture_b_pins[] = { 1775 /* AVB_AVTP_CAPTURE_B */ 1776 RCAR_GP_PIN(1, 11), 1777 }; 1778 static const unsigned int avb_avtp_capture_b_mux[] = { 1779 AVB_AVTP_CAPTURE_B_MARK, 1780 }; 1781 1782 /* - CAN ------------------------------------------------------------------ */ 1783 static const unsigned int can0_data_a_pins[] = { 1784 /* TX, RX */ 1785 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 1786 }; 1787 1788 static const unsigned int can0_data_a_mux[] = { 1789 CAN0_TX_A_MARK, CAN0_RX_A_MARK, 1790 }; 1791 1792 static const unsigned int can0_data_b_pins[] = { 1793 /* TX, RX */ 1794 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 1795 }; 1796 1797 static const unsigned int can0_data_b_mux[] = { 1798 CAN0_TX_B_MARK, CAN0_RX_B_MARK, 1799 }; 1800 1801 static const unsigned int can1_data_pins[] = { 1802 /* TX, RX */ 1803 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), 1804 }; 1805 1806 static const unsigned int can1_data_mux[] = { 1807 CAN1_TX_MARK, CAN1_RX_MARK, 1808 }; 1809 1810 /* - CAN Clock -------------------------------------------------------------- */ 1811 static const unsigned int can_clk_pins[] = { 1812 /* CLK */ 1813 RCAR_GP_PIN(1, 25), 1814 }; 1815 1816 static const unsigned int can_clk_mux[] = { 1817 CAN_CLK_MARK, 1818 }; 1819 1820 /* - CAN FD --------------------------------------------------------------- */ 1821 static const unsigned int canfd0_data_a_pins[] = { 1822 /* TX, RX */ 1823 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 1824 }; 1825 1826 static const unsigned int canfd0_data_a_mux[] = { 1827 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK, 1828 }; 1829 1830 static const unsigned int canfd0_data_b_pins[] = { 1831 /* TX, RX */ 1832 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 1833 }; 1834 1835 static const unsigned int canfd0_data_b_mux[] = { 1836 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK, 1837 }; 1838 1839 static const unsigned int canfd1_data_pins[] = { 1840 /* TX, RX */ 1841 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), 1842 }; 1843 1844 static const unsigned int canfd1_data_mux[] = { 1845 CANFD1_TX_MARK, CANFD1_RX_MARK, 1846 }; 1847 1848 #ifdef CONFIG_PINCTRL_PFC_R8A77965 1849 /* - DRIF0 --------------------------------------------------------------- */ 1850 static const unsigned int drif0_ctrl_a_pins[] = { 1851 /* CLK, SYNC */ 1852 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 1853 }; 1854 1855 static const unsigned int drif0_ctrl_a_mux[] = { 1856 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK, 1857 }; 1858 1859 static const unsigned int drif0_data0_a_pins[] = { 1860 /* D0 */ 1861 RCAR_GP_PIN(6, 10), 1862 }; 1863 1864 static const unsigned int drif0_data0_a_mux[] = { 1865 RIF0_D0_A_MARK, 1866 }; 1867 1868 static const unsigned int drif0_data1_a_pins[] = { 1869 /* D1 */ 1870 RCAR_GP_PIN(6, 7), 1871 }; 1872 1873 static const unsigned int drif0_data1_a_mux[] = { 1874 RIF0_D1_A_MARK, 1875 }; 1876 1877 static const unsigned int drif0_ctrl_b_pins[] = { 1878 /* CLK, SYNC */ 1879 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), 1880 }; 1881 1882 static const unsigned int drif0_ctrl_b_mux[] = { 1883 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK, 1884 }; 1885 1886 static const unsigned int drif0_data0_b_pins[] = { 1887 /* D0 */ 1888 RCAR_GP_PIN(5, 1), 1889 }; 1890 1891 static const unsigned int drif0_data0_b_mux[] = { 1892 RIF0_D0_B_MARK, 1893 }; 1894 1895 static const unsigned int drif0_data1_b_pins[] = { 1896 /* D1 */ 1897 RCAR_GP_PIN(5, 2), 1898 }; 1899 1900 static const unsigned int drif0_data1_b_mux[] = { 1901 RIF0_D1_B_MARK, 1902 }; 1903 1904 static const unsigned int drif0_ctrl_c_pins[] = { 1905 /* CLK, SYNC */ 1906 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15), 1907 }; 1908 1909 static const unsigned int drif0_ctrl_c_mux[] = { 1910 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK, 1911 }; 1912 1913 static const unsigned int drif0_data0_c_pins[] = { 1914 /* D0 */ 1915 RCAR_GP_PIN(5, 13), 1916 }; 1917 1918 static const unsigned int drif0_data0_c_mux[] = { 1919 RIF0_D0_C_MARK, 1920 }; 1921 1922 static const unsigned int drif0_data1_c_pins[] = { 1923 /* D1 */ 1924 RCAR_GP_PIN(5, 14), 1925 }; 1926 1927 static const unsigned int drif0_data1_c_mux[] = { 1928 RIF0_D1_C_MARK, 1929 }; 1930 1931 /* - DRIF1 --------------------------------------------------------------- */ 1932 static const unsigned int drif1_ctrl_a_pins[] = { 1933 /* CLK, SYNC */ 1934 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 1935 }; 1936 1937 static const unsigned int drif1_ctrl_a_mux[] = { 1938 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK, 1939 }; 1940 1941 static const unsigned int drif1_data0_a_pins[] = { 1942 /* D0 */ 1943 RCAR_GP_PIN(6, 19), 1944 }; 1945 1946 static const unsigned int drif1_data0_a_mux[] = { 1947 RIF1_D0_A_MARK, 1948 }; 1949 1950 static const unsigned int drif1_data1_a_pins[] = { 1951 /* D1 */ 1952 RCAR_GP_PIN(6, 20), 1953 }; 1954 1955 static const unsigned int drif1_data1_a_mux[] = { 1956 RIF1_D1_A_MARK, 1957 }; 1958 1959 static const unsigned int drif1_ctrl_b_pins[] = { 1960 /* CLK, SYNC */ 1961 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3), 1962 }; 1963 1964 static const unsigned int drif1_ctrl_b_mux[] = { 1965 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK, 1966 }; 1967 1968 static const unsigned int drif1_data0_b_pins[] = { 1969 /* D0 */ 1970 RCAR_GP_PIN(5, 7), 1971 }; 1972 1973 static const unsigned int drif1_data0_b_mux[] = { 1974 RIF1_D0_B_MARK, 1975 }; 1976 1977 static const unsigned int drif1_data1_b_pins[] = { 1978 /* D1 */ 1979 RCAR_GP_PIN(5, 8), 1980 }; 1981 1982 static const unsigned int drif1_data1_b_mux[] = { 1983 RIF1_D1_B_MARK, 1984 }; 1985 1986 static const unsigned int drif1_ctrl_c_pins[] = { 1987 /* CLK, SYNC */ 1988 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11), 1989 }; 1990 1991 static const unsigned int drif1_ctrl_c_mux[] = { 1992 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK, 1993 }; 1994 1995 static const unsigned int drif1_data0_c_pins[] = { 1996 /* D0 */ 1997 RCAR_GP_PIN(5, 6), 1998 }; 1999 2000 static const unsigned int drif1_data0_c_mux[] = { 2001 RIF1_D0_C_MARK, 2002 }; 2003 2004 static const unsigned int drif1_data1_c_pins[] = { 2005 /* D1 */ 2006 RCAR_GP_PIN(5, 10), 2007 }; 2008 2009 static const unsigned int drif1_data1_c_mux[] = { 2010 RIF1_D1_C_MARK, 2011 }; 2012 2013 /* - DRIF2 --------------------------------------------------------------- */ 2014 static const unsigned int drif2_ctrl_a_pins[] = { 2015 /* CLK, SYNC */ 2016 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 2017 }; 2018 2019 static const unsigned int drif2_ctrl_a_mux[] = { 2020 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK, 2021 }; 2022 2023 static const unsigned int drif2_data0_a_pins[] = { 2024 /* D0 */ 2025 RCAR_GP_PIN(6, 7), 2026 }; 2027 2028 static const unsigned int drif2_data0_a_mux[] = { 2029 RIF2_D0_A_MARK, 2030 }; 2031 2032 static const unsigned int drif2_data1_a_pins[] = { 2033 /* D1 */ 2034 RCAR_GP_PIN(6, 10), 2035 }; 2036 2037 static const unsigned int drif2_data1_a_mux[] = { 2038 RIF2_D1_A_MARK, 2039 }; 2040 2041 static const unsigned int drif2_ctrl_b_pins[] = { 2042 /* CLK, SYNC */ 2043 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 2044 }; 2045 2046 static const unsigned int drif2_ctrl_b_mux[] = { 2047 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK, 2048 }; 2049 2050 static const unsigned int drif2_data0_b_pins[] = { 2051 /* D0 */ 2052 RCAR_GP_PIN(6, 30), 2053 }; 2054 2055 static const unsigned int drif2_data0_b_mux[] = { 2056 RIF2_D0_B_MARK, 2057 }; 2058 2059 static const unsigned int drif2_data1_b_pins[] = { 2060 /* D1 */ 2061 RCAR_GP_PIN(6, 31), 2062 }; 2063 2064 static const unsigned int drif2_data1_b_mux[] = { 2065 RIF2_D1_B_MARK, 2066 }; 2067 2068 /* - DRIF3 --------------------------------------------------------------- */ 2069 static const unsigned int drif3_ctrl_a_pins[] = { 2070 /* CLK, SYNC */ 2071 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 2072 }; 2073 2074 static const unsigned int drif3_ctrl_a_mux[] = { 2075 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK, 2076 }; 2077 2078 static const unsigned int drif3_data0_a_pins[] = { 2079 /* D0 */ 2080 RCAR_GP_PIN(6, 19), 2081 }; 2082 2083 static const unsigned int drif3_data0_a_mux[] = { 2084 RIF3_D0_A_MARK, 2085 }; 2086 2087 static const unsigned int drif3_data1_a_pins[] = { 2088 /* D1 */ 2089 RCAR_GP_PIN(6, 20), 2090 }; 2091 2092 static const unsigned int drif3_data1_a_mux[] = { 2093 RIF3_D1_A_MARK, 2094 }; 2095 2096 static const unsigned int drif3_ctrl_b_pins[] = { 2097 /* CLK, SYNC */ 2098 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), 2099 }; 2100 2101 static const unsigned int drif3_ctrl_b_mux[] = { 2102 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK, 2103 }; 2104 2105 static const unsigned int drif3_data0_b_pins[] = { 2106 /* D0 */ 2107 RCAR_GP_PIN(6, 28), 2108 }; 2109 2110 static const unsigned int drif3_data0_b_mux[] = { 2111 RIF3_D0_B_MARK, 2112 }; 2113 2114 static const unsigned int drif3_data1_b_pins[] = { 2115 /* D1 */ 2116 RCAR_GP_PIN(6, 29), 2117 }; 2118 2119 static const unsigned int drif3_data1_b_mux[] = { 2120 RIF3_D1_B_MARK, 2121 }; 2122 #endif /* CONFIG_PINCTRL_PFC_R8A77965 */ 2123 2124 /* - DU --------------------------------------------------------------------- */ 2125 static const unsigned int du_rgb666_pins[] = { 2126 /* R[7:2], G[7:2], B[7:2] */ 2127 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), 2128 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 2129 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 2130 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), 2131 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), 2132 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), 2133 }; 2134 2135 static const unsigned int du_rgb666_mux[] = { 2136 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, 2137 DU_DR3_MARK, DU_DR2_MARK, 2138 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, 2139 DU_DG3_MARK, DU_DG2_MARK, 2140 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, 2141 DU_DB3_MARK, DU_DB2_MARK, 2142 }; 2143 2144 static const unsigned int du_rgb888_pins[] = { 2145 /* R[7:0], G[7:0], B[7:0] */ 2146 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), 2147 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 2148 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8), 2149 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 2150 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), 2151 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), 2152 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), 2153 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), 2154 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0), 2155 }; 2156 2157 static const unsigned int du_rgb888_mux[] = { 2158 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, 2159 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK, 2160 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, 2161 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK, 2162 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, 2163 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK, 2164 }; 2165 2166 static const unsigned int du_clk_out_0_pins[] = { 2167 /* CLKOUT */ 2168 RCAR_GP_PIN(1, 27), 2169 }; 2170 2171 static const unsigned int du_clk_out_0_mux[] = { 2172 DU_DOTCLKOUT0_MARK 2173 }; 2174 2175 static const unsigned int du_clk_out_1_pins[] = { 2176 /* CLKOUT */ 2177 RCAR_GP_PIN(2, 3), 2178 }; 2179 2180 static const unsigned int du_clk_out_1_mux[] = { 2181 DU_DOTCLKOUT1_MARK 2182 }; 2183 2184 static const unsigned int du_sync_pins[] = { 2185 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ 2186 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4), 2187 }; 2188 2189 static const unsigned int du_sync_mux[] = { 2190 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK 2191 }; 2192 2193 static const unsigned int du_oddf_pins[] = { 2194 /* EXDISP/EXODDF/EXCDE */ 2195 RCAR_GP_PIN(2, 2), 2196 }; 2197 2198 static const unsigned int du_oddf_mux[] = { 2199 DU_EXODDF_DU_ODDF_DISP_CDE_MARK, 2200 }; 2201 2202 static const unsigned int du_cde_pins[] = { 2203 /* CDE */ 2204 RCAR_GP_PIN(2, 0), 2205 }; 2206 2207 static const unsigned int du_cde_mux[] = { 2208 DU_CDE_MARK, 2209 }; 2210 2211 static const unsigned int du_disp_pins[] = { 2212 /* DISP */ 2213 RCAR_GP_PIN(2, 1), 2214 }; 2215 2216 static const unsigned int du_disp_mux[] = { 2217 DU_DISP_MARK, 2218 }; 2219 2220 /* - HSCIF0 ----------------------------------------------------------------- */ 2221 static const unsigned int hscif0_data_pins[] = { 2222 /* RX, TX */ 2223 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), 2224 }; 2225 2226 static const unsigned int hscif0_data_mux[] = { 2227 HRX0_MARK, HTX0_MARK, 2228 }; 2229 2230 static const unsigned int hscif0_clk_pins[] = { 2231 /* SCK */ 2232 RCAR_GP_PIN(5, 12), 2233 }; 2234 2235 static const unsigned int hscif0_clk_mux[] = { 2236 HSCK0_MARK, 2237 }; 2238 2239 static const unsigned int hscif0_ctrl_pins[] = { 2240 /* RTS, CTS */ 2241 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15), 2242 }; 2243 2244 static const unsigned int hscif0_ctrl_mux[] = { 2245 HRTS0_N_MARK, HCTS0_N_MARK, 2246 }; 2247 2248 /* - HSCIF1 ----------------------------------------------------------------- */ 2249 static const unsigned int hscif1_data_a_pins[] = { 2250 /* RX, TX */ 2251 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 2252 }; 2253 2254 static const unsigned int hscif1_data_a_mux[] = { 2255 HRX1_A_MARK, HTX1_A_MARK, 2256 }; 2257 2258 static const unsigned int hscif1_clk_a_pins[] = { 2259 /* SCK */ 2260 RCAR_GP_PIN(6, 21), 2261 }; 2262 2263 static const unsigned int hscif1_clk_a_mux[] = { 2264 HSCK1_A_MARK, 2265 }; 2266 2267 static const unsigned int hscif1_ctrl_a_pins[] = { 2268 /* RTS, CTS */ 2269 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), 2270 }; 2271 2272 static const unsigned int hscif1_ctrl_a_mux[] = { 2273 HRTS1_N_A_MARK, HCTS1_N_A_MARK, 2274 }; 2275 2276 static const unsigned int hscif1_data_b_pins[] = { 2277 /* RX, TX */ 2278 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 2279 }; 2280 2281 static const unsigned int hscif1_data_b_mux[] = { 2282 HRX1_B_MARK, HTX1_B_MARK, 2283 }; 2284 2285 static const unsigned int hscif1_clk_b_pins[] = { 2286 /* SCK */ 2287 RCAR_GP_PIN(5, 0), 2288 }; 2289 2290 static const unsigned int hscif1_clk_b_mux[] = { 2291 HSCK1_B_MARK, 2292 }; 2293 2294 static const unsigned int hscif1_ctrl_b_pins[] = { 2295 /* RTS, CTS */ 2296 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), 2297 }; 2298 2299 static const unsigned int hscif1_ctrl_b_mux[] = { 2300 HRTS1_N_B_MARK, HCTS1_N_B_MARK, 2301 }; 2302 2303 /* - HSCIF2 ----------------------------------------------------------------- */ 2304 static const unsigned int hscif2_data_a_pins[] = { 2305 /* RX, TX */ 2306 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 2307 }; 2308 2309 static const unsigned int hscif2_data_a_mux[] = { 2310 HRX2_A_MARK, HTX2_A_MARK, 2311 }; 2312 2313 static const unsigned int hscif2_clk_a_pins[] = { 2314 /* SCK */ 2315 RCAR_GP_PIN(6, 10), 2316 }; 2317 2318 static const unsigned int hscif2_clk_a_mux[] = { 2319 HSCK2_A_MARK, 2320 }; 2321 2322 static const unsigned int hscif2_ctrl_a_pins[] = { 2323 /* RTS, CTS */ 2324 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), 2325 }; 2326 2327 static const unsigned int hscif2_ctrl_a_mux[] = { 2328 HRTS2_N_A_MARK, HCTS2_N_A_MARK, 2329 }; 2330 2331 static const unsigned int hscif2_data_b_pins[] = { 2332 /* RX, TX */ 2333 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 2334 }; 2335 2336 static const unsigned int hscif2_data_b_mux[] = { 2337 HRX2_B_MARK, HTX2_B_MARK, 2338 }; 2339 2340 static const unsigned int hscif2_clk_b_pins[] = { 2341 /* SCK */ 2342 RCAR_GP_PIN(6, 21), 2343 }; 2344 2345 static const unsigned int hscif2_clk_b_mux[] = { 2346 HSCK2_B_MARK, 2347 }; 2348 2349 static const unsigned int hscif2_ctrl_b_pins[] = { 2350 /* RTS, CTS */ 2351 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19), 2352 }; 2353 2354 static const unsigned int hscif2_ctrl_b_mux[] = { 2355 HRTS2_N_B_MARK, HCTS2_N_B_MARK, 2356 }; 2357 2358 static const unsigned int hscif2_data_c_pins[] = { 2359 /* RX, TX */ 2360 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26), 2361 }; 2362 2363 static const unsigned int hscif2_data_c_mux[] = { 2364 HRX2_C_MARK, HTX2_C_MARK, 2365 }; 2366 2367 static const unsigned int hscif2_clk_c_pins[] = { 2368 /* SCK */ 2369 RCAR_GP_PIN(6, 24), 2370 }; 2371 2372 static const unsigned int hscif2_clk_c_mux[] = { 2373 HSCK2_C_MARK, 2374 }; 2375 2376 static const unsigned int hscif2_ctrl_c_pins[] = { 2377 /* RTS, CTS */ 2378 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27), 2379 }; 2380 2381 static const unsigned int hscif2_ctrl_c_mux[] = { 2382 HRTS2_N_C_MARK, HCTS2_N_C_MARK, 2383 }; 2384 2385 /* - HSCIF3 ----------------------------------------------------------------- */ 2386 static const unsigned int hscif3_data_a_pins[] = { 2387 /* RX, TX */ 2388 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 2389 }; 2390 2391 static const unsigned int hscif3_data_a_mux[] = { 2392 HRX3_A_MARK, HTX3_A_MARK, 2393 }; 2394 2395 static const unsigned int hscif3_clk_pins[] = { 2396 /* SCK */ 2397 RCAR_GP_PIN(1, 22), 2398 }; 2399 2400 static const unsigned int hscif3_clk_mux[] = { 2401 HSCK3_MARK, 2402 }; 2403 2404 static const unsigned int hscif3_ctrl_pins[] = { 2405 /* RTS, CTS */ 2406 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 2407 }; 2408 2409 static const unsigned int hscif3_ctrl_mux[] = { 2410 HRTS3_N_MARK, HCTS3_N_MARK, 2411 }; 2412 2413 static const unsigned int hscif3_data_b_pins[] = { 2414 /* RX, TX */ 2415 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 2416 }; 2417 2418 static const unsigned int hscif3_data_b_mux[] = { 2419 HRX3_B_MARK, HTX3_B_MARK, 2420 }; 2421 2422 static const unsigned int hscif3_data_c_pins[] = { 2423 /* RX, TX */ 2424 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 2425 }; 2426 2427 static const unsigned int hscif3_data_c_mux[] = { 2428 HRX3_C_MARK, HTX3_C_MARK, 2429 }; 2430 2431 static const unsigned int hscif3_data_d_pins[] = { 2432 /* RX, TX */ 2433 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 2434 }; 2435 2436 static const unsigned int hscif3_data_d_mux[] = { 2437 HRX3_D_MARK, HTX3_D_MARK, 2438 }; 2439 2440 /* - HSCIF4 ----------------------------------------------------------------- */ 2441 static const unsigned int hscif4_data_a_pins[] = { 2442 /* RX, TX */ 2443 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), 2444 }; 2445 2446 static const unsigned int hscif4_data_a_mux[] = { 2447 HRX4_A_MARK, HTX4_A_MARK, 2448 }; 2449 2450 static const unsigned int hscif4_clk_pins[] = { 2451 /* SCK */ 2452 RCAR_GP_PIN(1, 11), 2453 }; 2454 2455 static const unsigned int hscif4_clk_mux[] = { 2456 HSCK4_MARK, 2457 }; 2458 2459 static const unsigned int hscif4_ctrl_pins[] = { 2460 /* RTS, CTS */ 2461 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), 2462 }; 2463 2464 static const unsigned int hscif4_ctrl_mux[] = { 2465 HRTS4_N_MARK, HCTS4_N_MARK, 2466 }; 2467 2468 static const unsigned int hscif4_data_b_pins[] = { 2469 /* RX, TX */ 2470 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 2471 }; 2472 2473 static const unsigned int hscif4_data_b_mux[] = { 2474 HRX4_B_MARK, HTX4_B_MARK, 2475 }; 2476 2477 /* - I2C -------------------------------------------------------------------- */ 2478 static const unsigned int i2c0_pins[] = { 2479 /* SCL, SDA */ 2480 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), 2481 }; 2482 2483 static const unsigned int i2c0_mux[] = { 2484 SCL0_MARK, SDA0_MARK, 2485 }; 2486 2487 static const unsigned int i2c1_a_pins[] = { 2488 /* SDA, SCL */ 2489 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), 2490 }; 2491 2492 static const unsigned int i2c1_a_mux[] = { 2493 SDA1_A_MARK, SCL1_A_MARK, 2494 }; 2495 2496 static const unsigned int i2c1_b_pins[] = { 2497 /* SDA, SCL */ 2498 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23), 2499 }; 2500 2501 static const unsigned int i2c1_b_mux[] = { 2502 SDA1_B_MARK, SCL1_B_MARK, 2503 }; 2504 2505 static const unsigned int i2c2_a_pins[] = { 2506 /* SDA, SCL */ 2507 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), 2508 }; 2509 2510 static const unsigned int i2c2_a_mux[] = { 2511 SDA2_A_MARK, SCL2_A_MARK, 2512 }; 2513 2514 static const unsigned int i2c2_b_pins[] = { 2515 /* SDA, SCL */ 2516 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), 2517 }; 2518 2519 static const unsigned int i2c2_b_mux[] = { 2520 SDA2_B_MARK, SCL2_B_MARK, 2521 }; 2522 2523 static const unsigned int i2c3_pins[] = { 2524 /* SCL, SDA */ 2525 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 2526 }; 2527 2528 static const unsigned int i2c3_mux[] = { 2529 SCL3_MARK, SDA3_MARK, 2530 }; 2531 2532 static const unsigned int i2c5_pins[] = { 2533 /* SCL, SDA */ 2534 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), 2535 }; 2536 2537 static const unsigned int i2c5_mux[] = { 2538 SCL5_MARK, SDA5_MARK, 2539 }; 2540 2541 static const unsigned int i2c6_a_pins[] = { 2542 /* SDA, SCL */ 2543 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 2544 }; 2545 2546 static const unsigned int i2c6_a_mux[] = { 2547 SDA6_A_MARK, SCL6_A_MARK, 2548 }; 2549 2550 static const unsigned int i2c6_b_pins[] = { 2551 /* SDA, SCL */ 2552 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 2553 }; 2554 2555 static const unsigned int i2c6_b_mux[] = { 2556 SDA6_B_MARK, SCL6_B_MARK, 2557 }; 2558 2559 static const unsigned int i2c6_c_pins[] = { 2560 /* SDA, SCL */ 2561 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), 2562 }; 2563 2564 static const unsigned int i2c6_c_mux[] = { 2565 SDA6_C_MARK, SCL6_C_MARK, 2566 }; 2567 2568 /* - INTC-EX ---------------------------------------------------------------- */ 2569 static const unsigned int intc_ex_irq0_pins[] = { 2570 /* IRQ0 */ 2571 RCAR_GP_PIN(2, 0), 2572 }; 2573 static const unsigned int intc_ex_irq0_mux[] = { 2574 IRQ0_MARK, 2575 }; 2576 static const unsigned int intc_ex_irq1_pins[] = { 2577 /* IRQ1 */ 2578 RCAR_GP_PIN(2, 1), 2579 }; 2580 static const unsigned int intc_ex_irq1_mux[] = { 2581 IRQ1_MARK, 2582 }; 2583 static const unsigned int intc_ex_irq2_pins[] = { 2584 /* IRQ2 */ 2585 RCAR_GP_PIN(2, 2), 2586 }; 2587 static const unsigned int intc_ex_irq2_mux[] = { 2588 IRQ2_MARK, 2589 }; 2590 static const unsigned int intc_ex_irq3_pins[] = { 2591 /* IRQ3 */ 2592 RCAR_GP_PIN(2, 3), 2593 }; 2594 static const unsigned int intc_ex_irq3_mux[] = { 2595 IRQ3_MARK, 2596 }; 2597 static const unsigned int intc_ex_irq4_pins[] = { 2598 /* IRQ4 */ 2599 RCAR_GP_PIN(2, 4), 2600 }; 2601 static const unsigned int intc_ex_irq4_mux[] = { 2602 IRQ4_MARK, 2603 }; 2604 static const unsigned int intc_ex_irq5_pins[] = { 2605 /* IRQ5 */ 2606 RCAR_GP_PIN(2, 5), 2607 }; 2608 static const unsigned int intc_ex_irq5_mux[] = { 2609 IRQ5_MARK, 2610 }; 2611 2612 #ifdef CONFIG_PINCTRL_PFC_R8A77965 2613 /* - MLB+ ------------------------------------------------------------------- */ 2614 static const unsigned int mlb_3pin_pins[] = { 2615 RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), 2616 }; 2617 static const unsigned int mlb_3pin_mux[] = { 2618 MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, 2619 }; 2620 #endif /* CONFIG_PINCTRL_PFC_R8A77965 */ 2621 2622 /* - MSIOF0 ----------------------------------------------------------------- */ 2623 static const unsigned int msiof0_clk_pins[] = { 2624 /* SCK */ 2625 RCAR_GP_PIN(5, 17), 2626 }; 2627 static const unsigned int msiof0_clk_mux[] = { 2628 MSIOF0_SCK_MARK, 2629 }; 2630 static const unsigned int msiof0_sync_pins[] = { 2631 /* SYNC */ 2632 RCAR_GP_PIN(5, 18), 2633 }; 2634 static const unsigned int msiof0_sync_mux[] = { 2635 MSIOF0_SYNC_MARK, 2636 }; 2637 static const unsigned int msiof0_ss1_pins[] = { 2638 /* SS1 */ 2639 RCAR_GP_PIN(5, 19), 2640 }; 2641 static const unsigned int msiof0_ss1_mux[] = { 2642 MSIOF0_SS1_MARK, 2643 }; 2644 static const unsigned int msiof0_ss2_pins[] = { 2645 /* SS2 */ 2646 RCAR_GP_PIN(5, 21), 2647 }; 2648 static const unsigned int msiof0_ss2_mux[] = { 2649 MSIOF0_SS2_MARK, 2650 }; 2651 static const unsigned int msiof0_txd_pins[] = { 2652 /* TXD */ 2653 RCAR_GP_PIN(5, 20), 2654 }; 2655 static const unsigned int msiof0_txd_mux[] = { 2656 MSIOF0_TXD_MARK, 2657 }; 2658 static const unsigned int msiof0_rxd_pins[] = { 2659 /* RXD */ 2660 RCAR_GP_PIN(5, 22), 2661 }; 2662 static const unsigned int msiof0_rxd_mux[] = { 2663 MSIOF0_RXD_MARK, 2664 }; 2665 /* - MSIOF1 ----------------------------------------------------------------- */ 2666 static const unsigned int msiof1_clk_a_pins[] = { 2667 /* SCK */ 2668 RCAR_GP_PIN(6, 8), 2669 }; 2670 static const unsigned int msiof1_clk_a_mux[] = { 2671 MSIOF1_SCK_A_MARK, 2672 }; 2673 static const unsigned int msiof1_sync_a_pins[] = { 2674 /* SYNC */ 2675 RCAR_GP_PIN(6, 9), 2676 }; 2677 static const unsigned int msiof1_sync_a_mux[] = { 2678 MSIOF1_SYNC_A_MARK, 2679 }; 2680 static const unsigned int msiof1_ss1_a_pins[] = { 2681 /* SS1 */ 2682 RCAR_GP_PIN(6, 5), 2683 }; 2684 static const unsigned int msiof1_ss1_a_mux[] = { 2685 MSIOF1_SS1_A_MARK, 2686 }; 2687 static const unsigned int msiof1_ss2_a_pins[] = { 2688 /* SS2 */ 2689 RCAR_GP_PIN(6, 6), 2690 }; 2691 static const unsigned int msiof1_ss2_a_mux[] = { 2692 MSIOF1_SS2_A_MARK, 2693 }; 2694 static const unsigned int msiof1_txd_a_pins[] = { 2695 /* TXD */ 2696 RCAR_GP_PIN(6, 7), 2697 }; 2698 static const unsigned int msiof1_txd_a_mux[] = { 2699 MSIOF1_TXD_A_MARK, 2700 }; 2701 static const unsigned int msiof1_rxd_a_pins[] = { 2702 /* RXD */ 2703 RCAR_GP_PIN(6, 10), 2704 }; 2705 static const unsigned int msiof1_rxd_a_mux[] = { 2706 MSIOF1_RXD_A_MARK, 2707 }; 2708 static const unsigned int msiof1_clk_b_pins[] = { 2709 /* SCK */ 2710 RCAR_GP_PIN(5, 9), 2711 }; 2712 static const unsigned int msiof1_clk_b_mux[] = { 2713 MSIOF1_SCK_B_MARK, 2714 }; 2715 static const unsigned int msiof1_sync_b_pins[] = { 2716 /* SYNC */ 2717 RCAR_GP_PIN(5, 3), 2718 }; 2719 static const unsigned int msiof1_sync_b_mux[] = { 2720 MSIOF1_SYNC_B_MARK, 2721 }; 2722 static const unsigned int msiof1_ss1_b_pins[] = { 2723 /* SS1 */ 2724 RCAR_GP_PIN(5, 4), 2725 }; 2726 static const unsigned int msiof1_ss1_b_mux[] = { 2727 MSIOF1_SS1_B_MARK, 2728 }; 2729 static const unsigned int msiof1_ss2_b_pins[] = { 2730 /* SS2 */ 2731 RCAR_GP_PIN(5, 0), 2732 }; 2733 static const unsigned int msiof1_ss2_b_mux[] = { 2734 MSIOF1_SS2_B_MARK, 2735 }; 2736 static const unsigned int msiof1_txd_b_pins[] = { 2737 /* TXD */ 2738 RCAR_GP_PIN(5, 8), 2739 }; 2740 static const unsigned int msiof1_txd_b_mux[] = { 2741 MSIOF1_TXD_B_MARK, 2742 }; 2743 static const unsigned int msiof1_rxd_b_pins[] = { 2744 /* RXD */ 2745 RCAR_GP_PIN(5, 7), 2746 }; 2747 static const unsigned int msiof1_rxd_b_mux[] = { 2748 MSIOF1_RXD_B_MARK, 2749 }; 2750 static const unsigned int msiof1_clk_c_pins[] = { 2751 /* SCK */ 2752 RCAR_GP_PIN(6, 17), 2753 }; 2754 static const unsigned int msiof1_clk_c_mux[] = { 2755 MSIOF1_SCK_C_MARK, 2756 }; 2757 static const unsigned int msiof1_sync_c_pins[] = { 2758 /* SYNC */ 2759 RCAR_GP_PIN(6, 18), 2760 }; 2761 static const unsigned int msiof1_sync_c_mux[] = { 2762 MSIOF1_SYNC_C_MARK, 2763 }; 2764 static const unsigned int msiof1_ss1_c_pins[] = { 2765 /* SS1 */ 2766 RCAR_GP_PIN(6, 21), 2767 }; 2768 static const unsigned int msiof1_ss1_c_mux[] = { 2769 MSIOF1_SS1_C_MARK, 2770 }; 2771 static const unsigned int msiof1_ss2_c_pins[] = { 2772 /* SS2 */ 2773 RCAR_GP_PIN(6, 27), 2774 }; 2775 static const unsigned int msiof1_ss2_c_mux[] = { 2776 MSIOF1_SS2_C_MARK, 2777 }; 2778 static const unsigned int msiof1_txd_c_pins[] = { 2779 /* TXD */ 2780 RCAR_GP_PIN(6, 20), 2781 }; 2782 static const unsigned int msiof1_txd_c_mux[] = { 2783 MSIOF1_TXD_C_MARK, 2784 }; 2785 static const unsigned int msiof1_rxd_c_pins[] = { 2786 /* RXD */ 2787 RCAR_GP_PIN(6, 19), 2788 }; 2789 static const unsigned int msiof1_rxd_c_mux[] = { 2790 MSIOF1_RXD_C_MARK, 2791 }; 2792 static const unsigned int msiof1_clk_d_pins[] = { 2793 /* SCK */ 2794 RCAR_GP_PIN(5, 12), 2795 }; 2796 static const unsigned int msiof1_clk_d_mux[] = { 2797 MSIOF1_SCK_D_MARK, 2798 }; 2799 static const unsigned int msiof1_sync_d_pins[] = { 2800 /* SYNC */ 2801 RCAR_GP_PIN(5, 15), 2802 }; 2803 static const unsigned int msiof1_sync_d_mux[] = { 2804 MSIOF1_SYNC_D_MARK, 2805 }; 2806 static const unsigned int msiof1_ss1_d_pins[] = { 2807 /* SS1 */ 2808 RCAR_GP_PIN(5, 16), 2809 }; 2810 static const unsigned int msiof1_ss1_d_mux[] = { 2811 MSIOF1_SS1_D_MARK, 2812 }; 2813 static const unsigned int msiof1_ss2_d_pins[] = { 2814 /* SS2 */ 2815 RCAR_GP_PIN(5, 21), 2816 }; 2817 static const unsigned int msiof1_ss2_d_mux[] = { 2818 MSIOF1_SS2_D_MARK, 2819 }; 2820 static const unsigned int msiof1_txd_d_pins[] = { 2821 /* TXD */ 2822 RCAR_GP_PIN(5, 14), 2823 }; 2824 static const unsigned int msiof1_txd_d_mux[] = { 2825 MSIOF1_TXD_D_MARK, 2826 }; 2827 static const unsigned int msiof1_rxd_d_pins[] = { 2828 /* RXD */ 2829 RCAR_GP_PIN(5, 13), 2830 }; 2831 static const unsigned int msiof1_rxd_d_mux[] = { 2832 MSIOF1_RXD_D_MARK, 2833 }; 2834 static const unsigned int msiof1_clk_e_pins[] = { 2835 /* SCK */ 2836 RCAR_GP_PIN(3, 0), 2837 }; 2838 static const unsigned int msiof1_clk_e_mux[] = { 2839 MSIOF1_SCK_E_MARK, 2840 }; 2841 static const unsigned int msiof1_sync_e_pins[] = { 2842 /* SYNC */ 2843 RCAR_GP_PIN(3, 1), 2844 }; 2845 static const unsigned int msiof1_sync_e_mux[] = { 2846 MSIOF1_SYNC_E_MARK, 2847 }; 2848 static const unsigned int msiof1_ss1_e_pins[] = { 2849 /* SS1 */ 2850 RCAR_GP_PIN(3, 4), 2851 }; 2852 static const unsigned int msiof1_ss1_e_mux[] = { 2853 MSIOF1_SS1_E_MARK, 2854 }; 2855 static const unsigned int msiof1_ss2_e_pins[] = { 2856 /* SS2 */ 2857 RCAR_GP_PIN(3, 5), 2858 }; 2859 static const unsigned int msiof1_ss2_e_mux[] = { 2860 MSIOF1_SS2_E_MARK, 2861 }; 2862 static const unsigned int msiof1_txd_e_pins[] = { 2863 /* TXD */ 2864 RCAR_GP_PIN(3, 3), 2865 }; 2866 static const unsigned int msiof1_txd_e_mux[] = { 2867 MSIOF1_TXD_E_MARK, 2868 }; 2869 static const unsigned int msiof1_rxd_e_pins[] = { 2870 /* RXD */ 2871 RCAR_GP_PIN(3, 2), 2872 }; 2873 static const unsigned int msiof1_rxd_e_mux[] = { 2874 MSIOF1_RXD_E_MARK, 2875 }; 2876 static const unsigned int msiof1_clk_f_pins[] = { 2877 /* SCK */ 2878 RCAR_GP_PIN(5, 23), 2879 }; 2880 static const unsigned int msiof1_clk_f_mux[] = { 2881 MSIOF1_SCK_F_MARK, 2882 }; 2883 static const unsigned int msiof1_sync_f_pins[] = { 2884 /* SYNC */ 2885 RCAR_GP_PIN(5, 24), 2886 }; 2887 static const unsigned int msiof1_sync_f_mux[] = { 2888 MSIOF1_SYNC_F_MARK, 2889 }; 2890 static const unsigned int msiof1_ss1_f_pins[] = { 2891 /* SS1 */ 2892 RCAR_GP_PIN(6, 1), 2893 }; 2894 static const unsigned int msiof1_ss1_f_mux[] = { 2895 MSIOF1_SS1_F_MARK, 2896 }; 2897 static const unsigned int msiof1_ss2_f_pins[] = { 2898 /* SS2 */ 2899 RCAR_GP_PIN(6, 2), 2900 }; 2901 static const unsigned int msiof1_ss2_f_mux[] = { 2902 MSIOF1_SS2_F_MARK, 2903 }; 2904 static const unsigned int msiof1_txd_f_pins[] = { 2905 /* TXD */ 2906 RCAR_GP_PIN(6, 0), 2907 }; 2908 static const unsigned int msiof1_txd_f_mux[] = { 2909 MSIOF1_TXD_F_MARK, 2910 }; 2911 static const unsigned int msiof1_rxd_f_pins[] = { 2912 /* RXD */ 2913 RCAR_GP_PIN(5, 25), 2914 }; 2915 static const unsigned int msiof1_rxd_f_mux[] = { 2916 MSIOF1_RXD_F_MARK, 2917 }; 2918 static const unsigned int msiof1_clk_g_pins[] = { 2919 /* SCK */ 2920 RCAR_GP_PIN(3, 6), 2921 }; 2922 static const unsigned int msiof1_clk_g_mux[] = { 2923 MSIOF1_SCK_G_MARK, 2924 }; 2925 static const unsigned int msiof1_sync_g_pins[] = { 2926 /* SYNC */ 2927 RCAR_GP_PIN(3, 7), 2928 }; 2929 static const unsigned int msiof1_sync_g_mux[] = { 2930 MSIOF1_SYNC_G_MARK, 2931 }; 2932 static const unsigned int msiof1_ss1_g_pins[] = { 2933 /* SS1 */ 2934 RCAR_GP_PIN(3, 10), 2935 }; 2936 static const unsigned int msiof1_ss1_g_mux[] = { 2937 MSIOF1_SS1_G_MARK, 2938 }; 2939 static const unsigned int msiof1_ss2_g_pins[] = { 2940 /* SS2 */ 2941 RCAR_GP_PIN(3, 11), 2942 }; 2943 static const unsigned int msiof1_ss2_g_mux[] = { 2944 MSIOF1_SS2_G_MARK, 2945 }; 2946 static const unsigned int msiof1_txd_g_pins[] = { 2947 /* TXD */ 2948 RCAR_GP_PIN(3, 9), 2949 }; 2950 static const unsigned int msiof1_txd_g_mux[] = { 2951 MSIOF1_TXD_G_MARK, 2952 }; 2953 static const unsigned int msiof1_rxd_g_pins[] = { 2954 /* RXD */ 2955 RCAR_GP_PIN(3, 8), 2956 }; 2957 static const unsigned int msiof1_rxd_g_mux[] = { 2958 MSIOF1_RXD_G_MARK, 2959 }; 2960 /* - MSIOF2 ----------------------------------------------------------------- */ 2961 static const unsigned int msiof2_clk_a_pins[] = { 2962 /* SCK */ 2963 RCAR_GP_PIN(1, 9), 2964 }; 2965 static const unsigned int msiof2_clk_a_mux[] = { 2966 MSIOF2_SCK_A_MARK, 2967 }; 2968 static const unsigned int msiof2_sync_a_pins[] = { 2969 /* SYNC */ 2970 RCAR_GP_PIN(1, 8), 2971 }; 2972 static const unsigned int msiof2_sync_a_mux[] = { 2973 MSIOF2_SYNC_A_MARK, 2974 }; 2975 static const unsigned int msiof2_ss1_a_pins[] = { 2976 /* SS1 */ 2977 RCAR_GP_PIN(1, 6), 2978 }; 2979 static const unsigned int msiof2_ss1_a_mux[] = { 2980 MSIOF2_SS1_A_MARK, 2981 }; 2982 static const unsigned int msiof2_ss2_a_pins[] = { 2983 /* SS2 */ 2984 RCAR_GP_PIN(1, 7), 2985 }; 2986 static const unsigned int msiof2_ss2_a_mux[] = { 2987 MSIOF2_SS2_A_MARK, 2988 }; 2989 static const unsigned int msiof2_txd_a_pins[] = { 2990 /* TXD */ 2991 RCAR_GP_PIN(1, 11), 2992 }; 2993 static const unsigned int msiof2_txd_a_mux[] = { 2994 MSIOF2_TXD_A_MARK, 2995 }; 2996 static const unsigned int msiof2_rxd_a_pins[] = { 2997 /* RXD */ 2998 RCAR_GP_PIN(1, 10), 2999 }; 3000 static const unsigned int msiof2_rxd_a_mux[] = { 3001 MSIOF2_RXD_A_MARK, 3002 }; 3003 static const unsigned int msiof2_clk_b_pins[] = { 3004 /* SCK */ 3005 RCAR_GP_PIN(0, 4), 3006 }; 3007 static const unsigned int msiof2_clk_b_mux[] = { 3008 MSIOF2_SCK_B_MARK, 3009 }; 3010 static const unsigned int msiof2_sync_b_pins[] = { 3011 /* SYNC */ 3012 RCAR_GP_PIN(0, 5), 3013 }; 3014 static const unsigned int msiof2_sync_b_mux[] = { 3015 MSIOF2_SYNC_B_MARK, 3016 }; 3017 static const unsigned int msiof2_ss1_b_pins[] = { 3018 /* SS1 */ 3019 RCAR_GP_PIN(0, 0), 3020 }; 3021 static const unsigned int msiof2_ss1_b_mux[] = { 3022 MSIOF2_SS1_B_MARK, 3023 }; 3024 static const unsigned int msiof2_ss2_b_pins[] = { 3025 /* SS2 */ 3026 RCAR_GP_PIN(0, 1), 3027 }; 3028 static const unsigned int msiof2_ss2_b_mux[] = { 3029 MSIOF2_SS2_B_MARK, 3030 }; 3031 static const unsigned int msiof2_txd_b_pins[] = { 3032 /* TXD */ 3033 RCAR_GP_PIN(0, 7), 3034 }; 3035 static const unsigned int msiof2_txd_b_mux[] = { 3036 MSIOF2_TXD_B_MARK, 3037 }; 3038 static const unsigned int msiof2_rxd_b_pins[] = { 3039 /* RXD */ 3040 RCAR_GP_PIN(0, 6), 3041 }; 3042 static const unsigned int msiof2_rxd_b_mux[] = { 3043 MSIOF2_RXD_B_MARK, 3044 }; 3045 static const unsigned int msiof2_clk_c_pins[] = { 3046 /* SCK */ 3047 RCAR_GP_PIN(2, 12), 3048 }; 3049 static const unsigned int msiof2_clk_c_mux[] = { 3050 MSIOF2_SCK_C_MARK, 3051 }; 3052 static const unsigned int msiof2_sync_c_pins[] = { 3053 /* SYNC */ 3054 RCAR_GP_PIN(2, 11), 3055 }; 3056 static const unsigned int msiof2_sync_c_mux[] = { 3057 MSIOF2_SYNC_C_MARK, 3058 }; 3059 static const unsigned int msiof2_ss1_c_pins[] = { 3060 /* SS1 */ 3061 RCAR_GP_PIN(2, 10), 3062 }; 3063 static const unsigned int msiof2_ss1_c_mux[] = { 3064 MSIOF2_SS1_C_MARK, 3065 }; 3066 static const unsigned int msiof2_ss2_c_pins[] = { 3067 /* SS2 */ 3068 RCAR_GP_PIN(2, 9), 3069 }; 3070 static const unsigned int msiof2_ss2_c_mux[] = { 3071 MSIOF2_SS2_C_MARK, 3072 }; 3073 static const unsigned int msiof2_txd_c_pins[] = { 3074 /* TXD */ 3075 RCAR_GP_PIN(2, 14), 3076 }; 3077 static const unsigned int msiof2_txd_c_mux[] = { 3078 MSIOF2_TXD_C_MARK, 3079 }; 3080 static const unsigned int msiof2_rxd_c_pins[] = { 3081 /* RXD */ 3082 RCAR_GP_PIN(2, 13), 3083 }; 3084 static const unsigned int msiof2_rxd_c_mux[] = { 3085 MSIOF2_RXD_C_MARK, 3086 }; 3087 static const unsigned int msiof2_clk_d_pins[] = { 3088 /* SCK */ 3089 RCAR_GP_PIN(0, 8), 3090 }; 3091 static const unsigned int msiof2_clk_d_mux[] = { 3092 MSIOF2_SCK_D_MARK, 3093 }; 3094 static const unsigned int msiof2_sync_d_pins[] = { 3095 /* SYNC */ 3096 RCAR_GP_PIN(0, 9), 3097 }; 3098 static const unsigned int msiof2_sync_d_mux[] = { 3099 MSIOF2_SYNC_D_MARK, 3100 }; 3101 static const unsigned int msiof2_ss1_d_pins[] = { 3102 /* SS1 */ 3103 RCAR_GP_PIN(0, 12), 3104 }; 3105 static const unsigned int msiof2_ss1_d_mux[] = { 3106 MSIOF2_SS1_D_MARK, 3107 }; 3108 static const unsigned int msiof2_ss2_d_pins[] = { 3109 /* SS2 */ 3110 RCAR_GP_PIN(0, 13), 3111 }; 3112 static const unsigned int msiof2_ss2_d_mux[] = { 3113 MSIOF2_SS2_D_MARK, 3114 }; 3115 static const unsigned int msiof2_txd_d_pins[] = { 3116 /* TXD */ 3117 RCAR_GP_PIN(0, 11), 3118 }; 3119 static const unsigned int msiof2_txd_d_mux[] = { 3120 MSIOF2_TXD_D_MARK, 3121 }; 3122 static const unsigned int msiof2_rxd_d_pins[] = { 3123 /* RXD */ 3124 RCAR_GP_PIN(0, 10), 3125 }; 3126 static const unsigned int msiof2_rxd_d_mux[] = { 3127 MSIOF2_RXD_D_MARK, 3128 }; 3129 /* - MSIOF3 ----------------------------------------------------------------- */ 3130 static const unsigned int msiof3_clk_a_pins[] = { 3131 /* SCK */ 3132 RCAR_GP_PIN(0, 0), 3133 }; 3134 static const unsigned int msiof3_clk_a_mux[] = { 3135 MSIOF3_SCK_A_MARK, 3136 }; 3137 static const unsigned int msiof3_sync_a_pins[] = { 3138 /* SYNC */ 3139 RCAR_GP_PIN(0, 1), 3140 }; 3141 static const unsigned int msiof3_sync_a_mux[] = { 3142 MSIOF3_SYNC_A_MARK, 3143 }; 3144 static const unsigned int msiof3_ss1_a_pins[] = { 3145 /* SS1 */ 3146 RCAR_GP_PIN(0, 14), 3147 }; 3148 static const unsigned int msiof3_ss1_a_mux[] = { 3149 MSIOF3_SS1_A_MARK, 3150 }; 3151 static const unsigned int msiof3_ss2_a_pins[] = { 3152 /* SS2 */ 3153 RCAR_GP_PIN(0, 15), 3154 }; 3155 static const unsigned int msiof3_ss2_a_mux[] = { 3156 MSIOF3_SS2_A_MARK, 3157 }; 3158 static const unsigned int msiof3_txd_a_pins[] = { 3159 /* TXD */ 3160 RCAR_GP_PIN(0, 3), 3161 }; 3162 static const unsigned int msiof3_txd_a_mux[] = { 3163 MSIOF3_TXD_A_MARK, 3164 }; 3165 static const unsigned int msiof3_rxd_a_pins[] = { 3166 /* RXD */ 3167 RCAR_GP_PIN(0, 2), 3168 }; 3169 static const unsigned int msiof3_rxd_a_mux[] = { 3170 MSIOF3_RXD_A_MARK, 3171 }; 3172 static const unsigned int msiof3_clk_b_pins[] = { 3173 /* SCK */ 3174 RCAR_GP_PIN(1, 2), 3175 }; 3176 static const unsigned int msiof3_clk_b_mux[] = { 3177 MSIOF3_SCK_B_MARK, 3178 }; 3179 static const unsigned int msiof3_sync_b_pins[] = { 3180 /* SYNC */ 3181 RCAR_GP_PIN(1, 0), 3182 }; 3183 static const unsigned int msiof3_sync_b_mux[] = { 3184 MSIOF3_SYNC_B_MARK, 3185 }; 3186 static const unsigned int msiof3_ss1_b_pins[] = { 3187 /* SS1 */ 3188 RCAR_GP_PIN(1, 4), 3189 }; 3190 static const unsigned int msiof3_ss1_b_mux[] = { 3191 MSIOF3_SS1_B_MARK, 3192 }; 3193 static const unsigned int msiof3_ss2_b_pins[] = { 3194 /* SS2 */ 3195 RCAR_GP_PIN(1, 5), 3196 }; 3197 static const unsigned int msiof3_ss2_b_mux[] = { 3198 MSIOF3_SS2_B_MARK, 3199 }; 3200 static const unsigned int msiof3_txd_b_pins[] = { 3201 /* TXD */ 3202 RCAR_GP_PIN(1, 1), 3203 }; 3204 static const unsigned int msiof3_txd_b_mux[] = { 3205 MSIOF3_TXD_B_MARK, 3206 }; 3207 static const unsigned int msiof3_rxd_b_pins[] = { 3208 /* RXD */ 3209 RCAR_GP_PIN(1, 3), 3210 }; 3211 static const unsigned int msiof3_rxd_b_mux[] = { 3212 MSIOF3_RXD_B_MARK, 3213 }; 3214 static const unsigned int msiof3_clk_c_pins[] = { 3215 /* SCK */ 3216 RCAR_GP_PIN(1, 12), 3217 }; 3218 static const unsigned int msiof3_clk_c_mux[] = { 3219 MSIOF3_SCK_C_MARK, 3220 }; 3221 static const unsigned int msiof3_sync_c_pins[] = { 3222 /* SYNC */ 3223 RCAR_GP_PIN(1, 13), 3224 }; 3225 static const unsigned int msiof3_sync_c_mux[] = { 3226 MSIOF3_SYNC_C_MARK, 3227 }; 3228 static const unsigned int msiof3_txd_c_pins[] = { 3229 /* TXD */ 3230 RCAR_GP_PIN(1, 15), 3231 }; 3232 static const unsigned int msiof3_txd_c_mux[] = { 3233 MSIOF3_TXD_C_MARK, 3234 }; 3235 static const unsigned int msiof3_rxd_c_pins[] = { 3236 /* RXD */ 3237 RCAR_GP_PIN(1, 14), 3238 }; 3239 static const unsigned int msiof3_rxd_c_mux[] = { 3240 MSIOF3_RXD_C_MARK, 3241 }; 3242 static const unsigned int msiof3_clk_d_pins[] = { 3243 /* SCK */ 3244 RCAR_GP_PIN(1, 22), 3245 }; 3246 static const unsigned int msiof3_clk_d_mux[] = { 3247 MSIOF3_SCK_D_MARK, 3248 }; 3249 static const unsigned int msiof3_sync_d_pins[] = { 3250 /* SYNC */ 3251 RCAR_GP_PIN(1, 23), 3252 }; 3253 static const unsigned int msiof3_sync_d_mux[] = { 3254 MSIOF3_SYNC_D_MARK, 3255 }; 3256 static const unsigned int msiof3_ss1_d_pins[] = { 3257 /* SS1 */ 3258 RCAR_GP_PIN(1, 26), 3259 }; 3260 static const unsigned int msiof3_ss1_d_mux[] = { 3261 MSIOF3_SS1_D_MARK, 3262 }; 3263 static const unsigned int msiof3_txd_d_pins[] = { 3264 /* TXD */ 3265 RCAR_GP_PIN(1, 25), 3266 }; 3267 static const unsigned int msiof3_txd_d_mux[] = { 3268 MSIOF3_TXD_D_MARK, 3269 }; 3270 static const unsigned int msiof3_rxd_d_pins[] = { 3271 /* RXD */ 3272 RCAR_GP_PIN(1, 24), 3273 }; 3274 static const unsigned int msiof3_rxd_d_mux[] = { 3275 MSIOF3_RXD_D_MARK, 3276 }; 3277 static const unsigned int msiof3_clk_e_pins[] = { 3278 /* SCK */ 3279 RCAR_GP_PIN(2, 3), 3280 }; 3281 static const unsigned int msiof3_clk_e_mux[] = { 3282 MSIOF3_SCK_E_MARK, 3283 }; 3284 static const unsigned int msiof3_sync_e_pins[] = { 3285 /* SYNC */ 3286 RCAR_GP_PIN(2, 2), 3287 }; 3288 static const unsigned int msiof3_sync_e_mux[] = { 3289 MSIOF3_SYNC_E_MARK, 3290 }; 3291 static const unsigned int msiof3_ss1_e_pins[] = { 3292 /* SS1 */ 3293 RCAR_GP_PIN(2, 1), 3294 }; 3295 static const unsigned int msiof3_ss1_e_mux[] = { 3296 MSIOF3_SS1_E_MARK, 3297 }; 3298 static const unsigned int msiof3_ss2_e_pins[] = { 3299 /* SS2 */ 3300 RCAR_GP_PIN(2, 0), 3301 }; 3302 static const unsigned int msiof3_ss2_e_mux[] = { 3303 MSIOF3_SS2_E_MARK, 3304 }; 3305 static const unsigned int msiof3_txd_e_pins[] = { 3306 /* TXD */ 3307 RCAR_GP_PIN(2, 5), 3308 }; 3309 static const unsigned int msiof3_txd_e_mux[] = { 3310 MSIOF3_TXD_E_MARK, 3311 }; 3312 static const unsigned int msiof3_rxd_e_pins[] = { 3313 /* RXD */ 3314 RCAR_GP_PIN(2, 4), 3315 }; 3316 static const unsigned int msiof3_rxd_e_mux[] = { 3317 MSIOF3_RXD_E_MARK, 3318 }; 3319 3320 /* - PWM0 --------------------------------------------------------------------*/ 3321 static const unsigned int pwm0_pins[] = { 3322 /* PWM */ 3323 RCAR_GP_PIN(2, 6), 3324 }; 3325 static const unsigned int pwm0_mux[] = { 3326 PWM0_MARK, 3327 }; 3328 /* - PWM1 --------------------------------------------------------------------*/ 3329 static const unsigned int pwm1_a_pins[] = { 3330 /* PWM */ 3331 RCAR_GP_PIN(2, 7), 3332 }; 3333 static const unsigned int pwm1_a_mux[] = { 3334 PWM1_A_MARK, 3335 }; 3336 static const unsigned int pwm1_b_pins[] = { 3337 /* PWM */ 3338 RCAR_GP_PIN(1, 8), 3339 }; 3340 static const unsigned int pwm1_b_mux[] = { 3341 PWM1_B_MARK, 3342 }; 3343 /* - PWM2 --------------------------------------------------------------------*/ 3344 static const unsigned int pwm2_a_pins[] = { 3345 /* PWM */ 3346 RCAR_GP_PIN(2, 8), 3347 }; 3348 static const unsigned int pwm2_a_mux[] = { 3349 PWM2_A_MARK, 3350 }; 3351 static const unsigned int pwm2_b_pins[] = { 3352 /* PWM */ 3353 RCAR_GP_PIN(1, 11), 3354 }; 3355 static const unsigned int pwm2_b_mux[] = { 3356 PWM2_B_MARK, 3357 }; 3358 /* - PWM3 --------------------------------------------------------------------*/ 3359 static const unsigned int pwm3_a_pins[] = { 3360 /* PWM */ 3361 RCAR_GP_PIN(1, 0), 3362 }; 3363 static const unsigned int pwm3_a_mux[] = { 3364 PWM3_A_MARK, 3365 }; 3366 static const unsigned int pwm3_b_pins[] = { 3367 /* PWM */ 3368 RCAR_GP_PIN(2, 2), 3369 }; 3370 static const unsigned int pwm3_b_mux[] = { 3371 PWM3_B_MARK, 3372 }; 3373 /* - PWM4 --------------------------------------------------------------------*/ 3374 static const unsigned int pwm4_a_pins[] = { 3375 /* PWM */ 3376 RCAR_GP_PIN(1, 1), 3377 }; 3378 static const unsigned int pwm4_a_mux[] = { 3379 PWM4_A_MARK, 3380 }; 3381 static const unsigned int pwm4_b_pins[] = { 3382 /* PWM */ 3383 RCAR_GP_PIN(2, 3), 3384 }; 3385 static const unsigned int pwm4_b_mux[] = { 3386 PWM4_B_MARK, 3387 }; 3388 /* - PWM5 --------------------------------------------------------------------*/ 3389 static const unsigned int pwm5_a_pins[] = { 3390 /* PWM */ 3391 RCAR_GP_PIN(1, 2), 3392 }; 3393 static const unsigned int pwm5_a_mux[] = { 3394 PWM5_A_MARK, 3395 }; 3396 static const unsigned int pwm5_b_pins[] = { 3397 /* PWM */ 3398 RCAR_GP_PIN(2, 4), 3399 }; 3400 static const unsigned int pwm5_b_mux[] = { 3401 PWM5_B_MARK, 3402 }; 3403 /* - PWM6 --------------------------------------------------------------------*/ 3404 static const unsigned int pwm6_a_pins[] = { 3405 /* PWM */ 3406 RCAR_GP_PIN(1, 3), 3407 }; 3408 static const unsigned int pwm6_a_mux[] = { 3409 PWM6_A_MARK, 3410 }; 3411 static const unsigned int pwm6_b_pins[] = { 3412 /* PWM */ 3413 RCAR_GP_PIN(2, 5), 3414 }; 3415 static const unsigned int pwm6_b_mux[] = { 3416 PWM6_B_MARK, 3417 }; 3418 3419 /* - QSPI0 ------------------------------------------------------------------ */ 3420 static const unsigned int qspi0_ctrl_pins[] = { 3421 /* QSPI0_SPCLK, QSPI0_SSL */ 3422 PIN_QSPI0_SPCLK, PIN_QSPI0_SSL, 3423 }; 3424 static const unsigned int qspi0_ctrl_mux[] = { 3425 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, 3426 }; 3427 static const unsigned int qspi0_data2_pins[] = { 3428 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ 3429 PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, 3430 }; 3431 static const unsigned int qspi0_data2_mux[] = { 3432 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, 3433 }; 3434 static const unsigned int qspi0_data4_pins[] = { 3435 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ 3436 PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, 3437 /* QSPI0_IO2, QSPI0_IO3 */ 3438 PIN_QSPI0_IO2, PIN_QSPI0_IO3, 3439 }; 3440 static const unsigned int qspi0_data4_mux[] = { 3441 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, 3442 QSPI0_IO2_MARK, QSPI0_IO3_MARK, 3443 }; 3444 /* - QSPI1 ------------------------------------------------------------------ */ 3445 static const unsigned int qspi1_ctrl_pins[] = { 3446 /* QSPI1_SPCLK, QSPI1_SSL */ 3447 PIN_QSPI1_SPCLK, PIN_QSPI1_SSL, 3448 }; 3449 static const unsigned int qspi1_ctrl_mux[] = { 3450 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, 3451 }; 3452 static const unsigned int qspi1_data2_pins[] = { 3453 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ 3454 PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, 3455 }; 3456 static const unsigned int qspi1_data2_mux[] = { 3457 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, 3458 }; 3459 static const unsigned int qspi1_data4_pins[] = { 3460 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ 3461 PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, 3462 /* QSPI1_IO2, QSPI1_IO3 */ 3463 PIN_QSPI1_IO2, PIN_QSPI1_IO3, 3464 }; 3465 static const unsigned int qspi1_data4_mux[] = { 3466 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, 3467 QSPI1_IO2_MARK, QSPI1_IO3_MARK, 3468 }; 3469 3470 /* - SATA --------------------------------------------------------------------*/ 3471 static const unsigned int sata0_devslp_a_pins[] = { 3472 /* DEVSLP */ 3473 RCAR_GP_PIN(6, 16), 3474 }; 3475 3476 static const unsigned int sata0_devslp_a_mux[] = { 3477 SATA_DEVSLP_A_MARK, 3478 }; 3479 3480 static const unsigned int sata0_devslp_b_pins[] = { 3481 /* DEVSLP */ 3482 RCAR_GP_PIN(4, 6), 3483 }; 3484 3485 static const unsigned int sata0_devslp_b_mux[] = { 3486 SATA_DEVSLP_B_MARK, 3487 }; 3488 3489 /* - SCIF0 ------------------------------------------------------------------ */ 3490 static const unsigned int scif0_data_pins[] = { 3491 /* RX, TX */ 3492 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 3493 }; 3494 static const unsigned int scif0_data_mux[] = { 3495 RX0_MARK, TX0_MARK, 3496 }; 3497 static const unsigned int scif0_clk_pins[] = { 3498 /* SCK */ 3499 RCAR_GP_PIN(5, 0), 3500 }; 3501 static const unsigned int scif0_clk_mux[] = { 3502 SCK0_MARK, 3503 }; 3504 static const unsigned int scif0_ctrl_pins[] = { 3505 /* RTS, CTS */ 3506 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), 3507 }; 3508 static const unsigned int scif0_ctrl_mux[] = { 3509 RTS0_N_MARK, CTS0_N_MARK, 3510 }; 3511 /* - SCIF1 ------------------------------------------------------------------ */ 3512 static const unsigned int scif1_data_a_pins[] = { 3513 /* RX, TX */ 3514 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 3515 }; 3516 static const unsigned int scif1_data_a_mux[] = { 3517 RX1_A_MARK, TX1_A_MARK, 3518 }; 3519 static const unsigned int scif1_clk_pins[] = { 3520 /* SCK */ 3521 RCAR_GP_PIN(6, 21), 3522 }; 3523 static const unsigned int scif1_clk_mux[] = { 3524 SCK1_MARK, 3525 }; 3526 static const unsigned int scif1_ctrl_pins[] = { 3527 /* RTS, CTS */ 3528 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), 3529 }; 3530 static const unsigned int scif1_ctrl_mux[] = { 3531 RTS1_N_MARK, CTS1_N_MARK, 3532 }; 3533 static const unsigned int scif1_data_b_pins[] = { 3534 /* RX, TX */ 3535 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), 3536 }; 3537 static const unsigned int scif1_data_b_mux[] = { 3538 RX1_B_MARK, TX1_B_MARK, 3539 }; 3540 /* - SCIF2 ------------------------------------------------------------------ */ 3541 static const unsigned int scif2_data_a_pins[] = { 3542 /* RX, TX */ 3543 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), 3544 }; 3545 static const unsigned int scif2_data_a_mux[] = { 3546 RX2_A_MARK, TX2_A_MARK, 3547 }; 3548 static const unsigned int scif2_clk_pins[] = { 3549 /* SCK */ 3550 RCAR_GP_PIN(5, 9), 3551 }; 3552 static const unsigned int scif2_clk_mux[] = { 3553 SCK2_MARK, 3554 }; 3555 static const unsigned int scif2_data_b_pins[] = { 3556 /* RX, TX */ 3557 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), 3558 }; 3559 static const unsigned int scif2_data_b_mux[] = { 3560 RX2_B_MARK, TX2_B_MARK, 3561 }; 3562 /* - SCIF3 ------------------------------------------------------------------ */ 3563 static const unsigned int scif3_data_a_pins[] = { 3564 /* RX, TX */ 3565 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 3566 }; 3567 static const unsigned int scif3_data_a_mux[] = { 3568 RX3_A_MARK, TX3_A_MARK, 3569 }; 3570 static const unsigned int scif3_clk_pins[] = { 3571 /* SCK */ 3572 RCAR_GP_PIN(1, 22), 3573 }; 3574 static const unsigned int scif3_clk_mux[] = { 3575 SCK3_MARK, 3576 }; 3577 static const unsigned int scif3_ctrl_pins[] = { 3578 /* RTS, CTS */ 3579 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 3580 }; 3581 static const unsigned int scif3_ctrl_mux[] = { 3582 RTS3_N_MARK, CTS3_N_MARK, 3583 }; 3584 static const unsigned int scif3_data_b_pins[] = { 3585 /* RX, TX */ 3586 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 3587 }; 3588 static const unsigned int scif3_data_b_mux[] = { 3589 RX3_B_MARK, TX3_B_MARK, 3590 }; 3591 /* - SCIF4 ------------------------------------------------------------------ */ 3592 static const unsigned int scif4_data_a_pins[] = { 3593 /* RX, TX */ 3594 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), 3595 }; 3596 static const unsigned int scif4_data_a_mux[] = { 3597 RX4_A_MARK, TX4_A_MARK, 3598 }; 3599 static const unsigned int scif4_clk_a_pins[] = { 3600 /* SCK */ 3601 RCAR_GP_PIN(2, 10), 3602 }; 3603 static const unsigned int scif4_clk_a_mux[] = { 3604 SCK4_A_MARK, 3605 }; 3606 static const unsigned int scif4_ctrl_a_pins[] = { 3607 /* RTS, CTS */ 3608 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), 3609 }; 3610 static const unsigned int scif4_ctrl_a_mux[] = { 3611 RTS4_N_A_MARK, CTS4_N_A_MARK, 3612 }; 3613 static const unsigned int scif4_data_b_pins[] = { 3614 /* RX, TX */ 3615 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3616 }; 3617 static const unsigned int scif4_data_b_mux[] = { 3618 RX4_B_MARK, TX4_B_MARK, 3619 }; 3620 static const unsigned int scif4_clk_b_pins[] = { 3621 /* SCK */ 3622 RCAR_GP_PIN(1, 5), 3623 }; 3624 static const unsigned int scif4_clk_b_mux[] = { 3625 SCK4_B_MARK, 3626 }; 3627 static const unsigned int scif4_ctrl_b_pins[] = { 3628 /* RTS, CTS */ 3629 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), 3630 }; 3631 static const unsigned int scif4_ctrl_b_mux[] = { 3632 RTS4_N_B_MARK, CTS4_N_B_MARK, 3633 }; 3634 static const unsigned int scif4_data_c_pins[] = { 3635 /* RX, TX */ 3636 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 3637 }; 3638 static const unsigned int scif4_data_c_mux[] = { 3639 RX4_C_MARK, TX4_C_MARK, 3640 }; 3641 static const unsigned int scif4_clk_c_pins[] = { 3642 /* SCK */ 3643 RCAR_GP_PIN(0, 8), 3644 }; 3645 static const unsigned int scif4_clk_c_mux[] = { 3646 SCK4_C_MARK, 3647 }; 3648 static const unsigned int scif4_ctrl_c_pins[] = { 3649 /* RTS, CTS */ 3650 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 3651 }; 3652 static const unsigned int scif4_ctrl_c_mux[] = { 3653 RTS4_N_C_MARK, CTS4_N_C_MARK, 3654 }; 3655 /* - SCIF5 ------------------------------------------------------------------ */ 3656 static const unsigned int scif5_data_a_pins[] = { 3657 /* RX, TX */ 3658 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21), 3659 }; 3660 static const unsigned int scif5_data_a_mux[] = { 3661 RX5_A_MARK, TX5_A_MARK, 3662 }; 3663 static const unsigned int scif5_clk_a_pins[] = { 3664 /* SCK */ 3665 RCAR_GP_PIN(6, 21), 3666 }; 3667 static const unsigned int scif5_clk_a_mux[] = { 3668 SCK5_A_MARK, 3669 }; 3670 static const unsigned int scif5_data_b_pins[] = { 3671 /* RX, TX */ 3672 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18), 3673 }; 3674 static const unsigned int scif5_data_b_mux[] = { 3675 RX5_B_MARK, TX5_B_MARK, 3676 }; 3677 static const unsigned int scif5_clk_b_pins[] = { 3678 /* SCK */ 3679 RCAR_GP_PIN(5, 0), 3680 }; 3681 static const unsigned int scif5_clk_b_mux[] = { 3682 SCK5_B_MARK, 3683 }; 3684 /* - SCIF Clock ------------------------------------------------------------- */ 3685 static const unsigned int scif_clk_a_pins[] = { 3686 /* SCIF_CLK */ 3687 RCAR_GP_PIN(6, 23), 3688 }; 3689 static const unsigned int scif_clk_a_mux[] = { 3690 SCIF_CLK_A_MARK, 3691 }; 3692 static const unsigned int scif_clk_b_pins[] = { 3693 /* SCIF_CLK */ 3694 RCAR_GP_PIN(5, 9), 3695 }; 3696 static const unsigned int scif_clk_b_mux[] = { 3697 SCIF_CLK_B_MARK, 3698 }; 3699 3700 /* - SDHI0 ------------------------------------------------------------------ */ 3701 static const unsigned int sdhi0_data1_pins[] = { 3702 /* D0 */ 3703 RCAR_GP_PIN(3, 2), 3704 }; 3705 3706 static const unsigned int sdhi0_data1_mux[] = { 3707 SD0_DAT0_MARK, 3708 }; 3709 3710 static const unsigned int sdhi0_data4_pins[] = { 3711 /* D[0:3] */ 3712 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), 3713 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), 3714 }; 3715 3716 static const unsigned int sdhi0_data4_mux[] = { 3717 SD0_DAT0_MARK, SD0_DAT1_MARK, 3718 SD0_DAT2_MARK, SD0_DAT3_MARK, 3719 }; 3720 3721 static const unsigned int sdhi0_ctrl_pins[] = { 3722 /* CLK, CMD */ 3723 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), 3724 }; 3725 3726 static const unsigned int sdhi0_ctrl_mux[] = { 3727 SD0_CLK_MARK, SD0_CMD_MARK, 3728 }; 3729 3730 static const unsigned int sdhi0_cd_pins[] = { 3731 /* CD */ 3732 RCAR_GP_PIN(3, 12), 3733 }; 3734 3735 static const unsigned int sdhi0_cd_mux[] = { 3736 SD0_CD_MARK, 3737 }; 3738 3739 static const unsigned int sdhi0_wp_pins[] = { 3740 /* WP */ 3741 RCAR_GP_PIN(3, 13), 3742 }; 3743 3744 static const unsigned int sdhi0_wp_mux[] = { 3745 SD0_WP_MARK, 3746 }; 3747 3748 /* - SDHI1 ------------------------------------------------------------------ */ 3749 static const unsigned int sdhi1_data1_pins[] = { 3750 /* D0 */ 3751 RCAR_GP_PIN(3, 8), 3752 }; 3753 3754 static const unsigned int sdhi1_data1_mux[] = { 3755 SD1_DAT0_MARK, 3756 }; 3757 3758 static const unsigned int sdhi1_data4_pins[] = { 3759 /* D[0:3] */ 3760 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 3761 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 3762 }; 3763 3764 static const unsigned int sdhi1_data4_mux[] = { 3765 SD1_DAT0_MARK, SD1_DAT1_MARK, 3766 SD1_DAT2_MARK, SD1_DAT3_MARK, 3767 }; 3768 3769 static const unsigned int sdhi1_ctrl_pins[] = { 3770 /* CLK, CMD */ 3771 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 3772 }; 3773 3774 static const unsigned int sdhi1_ctrl_mux[] = { 3775 SD1_CLK_MARK, SD1_CMD_MARK, 3776 }; 3777 3778 static const unsigned int sdhi1_cd_pins[] = { 3779 /* CD */ 3780 RCAR_GP_PIN(3, 14), 3781 }; 3782 3783 static const unsigned int sdhi1_cd_mux[] = { 3784 SD1_CD_MARK, 3785 }; 3786 3787 static const unsigned int sdhi1_wp_pins[] = { 3788 /* WP */ 3789 RCAR_GP_PIN(3, 15), 3790 }; 3791 3792 static const unsigned int sdhi1_wp_mux[] = { 3793 SD1_WP_MARK, 3794 }; 3795 3796 /* - SDHI2 ------------------------------------------------------------------ */ 3797 static const unsigned int sdhi2_data1_pins[] = { 3798 /* D0 */ 3799 RCAR_GP_PIN(4, 2), 3800 }; 3801 3802 static const unsigned int sdhi2_data1_mux[] = { 3803 SD2_DAT0_MARK, 3804 }; 3805 3806 static const unsigned int sdhi2_data4_pins[] = { 3807 /* D[0:3] */ 3808 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), 3809 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), 3810 }; 3811 3812 static const unsigned int sdhi2_data4_mux[] = { 3813 SD2_DAT0_MARK, SD2_DAT1_MARK, 3814 SD2_DAT2_MARK, SD2_DAT3_MARK, 3815 }; 3816 3817 static const unsigned int sdhi2_data8_pins[] = { 3818 /* D[0:7] */ 3819 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), 3820 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), 3821 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 3822 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 3823 }; 3824 3825 static const unsigned int sdhi2_data8_mux[] = { 3826 SD2_DAT0_MARK, SD2_DAT1_MARK, 3827 SD2_DAT2_MARK, SD2_DAT3_MARK, 3828 SD2_DAT4_MARK, SD2_DAT5_MARK, 3829 SD2_DAT6_MARK, SD2_DAT7_MARK, 3830 }; 3831 3832 static const unsigned int sdhi2_ctrl_pins[] = { 3833 /* CLK, CMD */ 3834 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), 3835 }; 3836 3837 static const unsigned int sdhi2_ctrl_mux[] = { 3838 SD2_CLK_MARK, SD2_CMD_MARK, 3839 }; 3840 3841 static const unsigned int sdhi2_cd_a_pins[] = { 3842 /* CD */ 3843 RCAR_GP_PIN(4, 13), 3844 }; 3845 3846 static const unsigned int sdhi2_cd_a_mux[] = { 3847 SD2_CD_A_MARK, 3848 }; 3849 3850 static const unsigned int sdhi2_cd_b_pins[] = { 3851 /* CD */ 3852 RCAR_GP_PIN(5, 10), 3853 }; 3854 3855 static const unsigned int sdhi2_cd_b_mux[] = { 3856 SD2_CD_B_MARK, 3857 }; 3858 3859 static const unsigned int sdhi2_wp_a_pins[] = { 3860 /* WP */ 3861 RCAR_GP_PIN(4, 14), 3862 }; 3863 3864 static const unsigned int sdhi2_wp_a_mux[] = { 3865 SD2_WP_A_MARK, 3866 }; 3867 3868 static const unsigned int sdhi2_wp_b_pins[] = { 3869 /* WP */ 3870 RCAR_GP_PIN(5, 11), 3871 }; 3872 3873 static const unsigned int sdhi2_wp_b_mux[] = { 3874 SD2_WP_B_MARK, 3875 }; 3876 3877 static const unsigned int sdhi2_ds_pins[] = { 3878 /* DS */ 3879 RCAR_GP_PIN(4, 6), 3880 }; 3881 3882 static const unsigned int sdhi2_ds_mux[] = { 3883 SD2_DS_MARK, 3884 }; 3885 3886 /* - SDHI3 ------------------------------------------------------------------ */ 3887 static const unsigned int sdhi3_data1_pins[] = { 3888 /* D0 */ 3889 RCAR_GP_PIN(4, 9), 3890 }; 3891 3892 static const unsigned int sdhi3_data1_mux[] = { 3893 SD3_DAT0_MARK, 3894 }; 3895 3896 static const unsigned int sdhi3_data4_pins[] = { 3897 /* D[0:3] */ 3898 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), 3899 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 3900 }; 3901 3902 static const unsigned int sdhi3_data4_mux[] = { 3903 SD3_DAT0_MARK, SD3_DAT1_MARK, 3904 SD3_DAT2_MARK, SD3_DAT3_MARK, 3905 }; 3906 3907 static const unsigned int sdhi3_data8_pins[] = { 3908 /* D[0:7] */ 3909 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), 3910 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 3911 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), 3912 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), 3913 }; 3914 3915 static const unsigned int sdhi3_data8_mux[] = { 3916 SD3_DAT0_MARK, SD3_DAT1_MARK, 3917 SD3_DAT2_MARK, SD3_DAT3_MARK, 3918 SD3_DAT4_MARK, SD3_DAT5_MARK, 3919 SD3_DAT6_MARK, SD3_DAT7_MARK, 3920 }; 3921 3922 static const unsigned int sdhi3_ctrl_pins[] = { 3923 /* CLK, CMD */ 3924 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), 3925 }; 3926 3927 static const unsigned int sdhi3_ctrl_mux[] = { 3928 SD3_CLK_MARK, SD3_CMD_MARK, 3929 }; 3930 3931 static const unsigned int sdhi3_cd_pins[] = { 3932 /* CD */ 3933 RCAR_GP_PIN(4, 15), 3934 }; 3935 3936 static const unsigned int sdhi3_cd_mux[] = { 3937 SD3_CD_MARK, 3938 }; 3939 3940 static const unsigned int sdhi3_wp_pins[] = { 3941 /* WP */ 3942 RCAR_GP_PIN(4, 16), 3943 }; 3944 3945 static const unsigned int sdhi3_wp_mux[] = { 3946 SD3_WP_MARK, 3947 }; 3948 3949 static const unsigned int sdhi3_ds_pins[] = { 3950 /* DS */ 3951 RCAR_GP_PIN(4, 17), 3952 }; 3953 3954 static const unsigned int sdhi3_ds_mux[] = { 3955 SD3_DS_MARK, 3956 }; 3957 3958 /* - SSI -------------------------------------------------------------------- */ 3959 static const unsigned int ssi0_data_pins[] = { 3960 /* SDATA */ 3961 RCAR_GP_PIN(6, 2), 3962 }; 3963 static const unsigned int ssi0_data_mux[] = { 3964 SSI_SDATA0_MARK, 3965 }; 3966 static const unsigned int ssi01239_ctrl_pins[] = { 3967 /* SCK, WS */ 3968 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), 3969 }; 3970 static const unsigned int ssi01239_ctrl_mux[] = { 3971 SSI_SCK01239_MARK, SSI_WS01239_MARK, 3972 }; 3973 static const unsigned int ssi1_data_a_pins[] = { 3974 /* SDATA */ 3975 RCAR_GP_PIN(6, 3), 3976 }; 3977 static const unsigned int ssi1_data_a_mux[] = { 3978 SSI_SDATA1_A_MARK, 3979 }; 3980 static const unsigned int ssi1_data_b_pins[] = { 3981 /* SDATA */ 3982 RCAR_GP_PIN(5, 12), 3983 }; 3984 static const unsigned int ssi1_data_b_mux[] = { 3985 SSI_SDATA1_B_MARK, 3986 }; 3987 static const unsigned int ssi1_ctrl_a_pins[] = { 3988 /* SCK, WS */ 3989 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 3990 }; 3991 static const unsigned int ssi1_ctrl_a_mux[] = { 3992 SSI_SCK1_A_MARK, SSI_WS1_A_MARK, 3993 }; 3994 static const unsigned int ssi1_ctrl_b_pins[] = { 3995 /* SCK, WS */ 3996 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21), 3997 }; 3998 static const unsigned int ssi1_ctrl_b_mux[] = { 3999 SSI_SCK1_B_MARK, SSI_WS1_B_MARK, 4000 }; 4001 static const unsigned int ssi2_data_a_pins[] = { 4002 /* SDATA */ 4003 RCAR_GP_PIN(6, 4), 4004 }; 4005 static const unsigned int ssi2_data_a_mux[] = { 4006 SSI_SDATA2_A_MARK, 4007 }; 4008 static const unsigned int ssi2_data_b_pins[] = { 4009 /* SDATA */ 4010 RCAR_GP_PIN(5, 13), 4011 }; 4012 static const unsigned int ssi2_data_b_mux[] = { 4013 SSI_SDATA2_B_MARK, 4014 }; 4015 static const unsigned int ssi2_ctrl_a_pins[] = { 4016 /* SCK, WS */ 4017 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21), 4018 }; 4019 static const unsigned int ssi2_ctrl_a_mux[] = { 4020 SSI_SCK2_A_MARK, SSI_WS2_A_MARK, 4021 }; 4022 static const unsigned int ssi2_ctrl_b_pins[] = { 4023 /* SCK, WS */ 4024 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), 4025 }; 4026 static const unsigned int ssi2_ctrl_b_mux[] = { 4027 SSI_SCK2_B_MARK, SSI_WS2_B_MARK, 4028 }; 4029 static const unsigned int ssi3_data_pins[] = { 4030 /* SDATA */ 4031 RCAR_GP_PIN(6, 7), 4032 }; 4033 static const unsigned int ssi3_data_mux[] = { 4034 SSI_SDATA3_MARK, 4035 }; 4036 static const unsigned int ssi349_ctrl_pins[] = { 4037 /* SCK, WS */ 4038 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6), 4039 }; 4040 static const unsigned int ssi349_ctrl_mux[] = { 4041 SSI_SCK349_MARK, SSI_WS349_MARK, 4042 }; 4043 static const unsigned int ssi4_data_pins[] = { 4044 /* SDATA */ 4045 RCAR_GP_PIN(6, 10), 4046 }; 4047 static const unsigned int ssi4_data_mux[] = { 4048 SSI_SDATA4_MARK, 4049 }; 4050 static const unsigned int ssi4_ctrl_pins[] = { 4051 /* SCK, WS */ 4052 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 4053 }; 4054 static const unsigned int ssi4_ctrl_mux[] = { 4055 SSI_SCK4_MARK, SSI_WS4_MARK, 4056 }; 4057 static const unsigned int ssi5_data_pins[] = { 4058 /* SDATA */ 4059 RCAR_GP_PIN(6, 13), 4060 }; 4061 static const unsigned int ssi5_data_mux[] = { 4062 SSI_SDATA5_MARK, 4063 }; 4064 static const unsigned int ssi5_ctrl_pins[] = { 4065 /* SCK, WS */ 4066 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), 4067 }; 4068 static const unsigned int ssi5_ctrl_mux[] = { 4069 SSI_SCK5_MARK, SSI_WS5_MARK, 4070 }; 4071 static const unsigned int ssi6_data_pins[] = { 4072 /* SDATA */ 4073 RCAR_GP_PIN(6, 16), 4074 }; 4075 static const unsigned int ssi6_data_mux[] = { 4076 SSI_SDATA6_MARK, 4077 }; 4078 static const unsigned int ssi6_ctrl_pins[] = { 4079 /* SCK, WS */ 4080 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), 4081 }; 4082 static const unsigned int ssi6_ctrl_mux[] = { 4083 SSI_SCK6_MARK, SSI_WS6_MARK, 4084 }; 4085 static const unsigned int ssi7_data_pins[] = { 4086 /* SDATA */ 4087 RCAR_GP_PIN(6, 19), 4088 }; 4089 static const unsigned int ssi7_data_mux[] = { 4090 SSI_SDATA7_MARK, 4091 }; 4092 static const unsigned int ssi78_ctrl_pins[] = { 4093 /* SCK, WS */ 4094 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 4095 }; 4096 static const unsigned int ssi78_ctrl_mux[] = { 4097 SSI_SCK78_MARK, SSI_WS78_MARK, 4098 }; 4099 static const unsigned int ssi8_data_pins[] = { 4100 /* SDATA */ 4101 RCAR_GP_PIN(6, 20), 4102 }; 4103 static const unsigned int ssi8_data_mux[] = { 4104 SSI_SDATA8_MARK, 4105 }; 4106 static const unsigned int ssi9_data_a_pins[] = { 4107 /* SDATA */ 4108 RCAR_GP_PIN(6, 21), 4109 }; 4110 static const unsigned int ssi9_data_a_mux[] = { 4111 SSI_SDATA9_A_MARK, 4112 }; 4113 static const unsigned int ssi9_data_b_pins[] = { 4114 /* SDATA */ 4115 RCAR_GP_PIN(5, 14), 4116 }; 4117 static const unsigned int ssi9_data_b_mux[] = { 4118 SSI_SDATA9_B_MARK, 4119 }; 4120 static const unsigned int ssi9_ctrl_a_pins[] = { 4121 /* SCK, WS */ 4122 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), 4123 }; 4124 static const unsigned int ssi9_ctrl_a_mux[] = { 4125 SSI_SCK9_A_MARK, SSI_WS9_A_MARK, 4126 }; 4127 static const unsigned int ssi9_ctrl_b_pins[] = { 4128 /* SCK, WS */ 4129 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31), 4130 }; 4131 static const unsigned int ssi9_ctrl_b_mux[] = { 4132 SSI_SCK9_B_MARK, SSI_WS9_B_MARK, 4133 }; 4134 4135 /* - TMU -------------------------------------------------------------------- */ 4136 static const unsigned int tmu_tclk1_a_pins[] = { 4137 /* TCLK */ 4138 RCAR_GP_PIN(6, 23), 4139 }; 4140 4141 static const unsigned int tmu_tclk1_a_mux[] = { 4142 TCLK1_A_MARK, 4143 }; 4144 4145 static const unsigned int tmu_tclk1_b_pins[] = { 4146 /* TCLK */ 4147 RCAR_GP_PIN(5, 19), 4148 }; 4149 4150 static const unsigned int tmu_tclk1_b_mux[] = { 4151 TCLK1_B_MARK, 4152 }; 4153 4154 static const unsigned int tmu_tclk2_a_pins[] = { 4155 /* TCLK */ 4156 RCAR_GP_PIN(6, 19), 4157 }; 4158 4159 static const unsigned int tmu_tclk2_a_mux[] = { 4160 TCLK2_A_MARK, 4161 }; 4162 4163 static const unsigned int tmu_tclk2_b_pins[] = { 4164 /* TCLK */ 4165 RCAR_GP_PIN(6, 28), 4166 }; 4167 4168 static const unsigned int tmu_tclk2_b_mux[] = { 4169 TCLK2_B_MARK, 4170 }; 4171 4172 /* - TPU ------------------------------------------------------------------- */ 4173 static const unsigned int tpu_to0_pins[] = { 4174 /* TPU0TO0 */ 4175 RCAR_GP_PIN(6, 28), 4176 }; 4177 static const unsigned int tpu_to0_mux[] = { 4178 TPU0TO0_MARK, 4179 }; 4180 static const unsigned int tpu_to1_pins[] = { 4181 /* TPU0TO1 */ 4182 RCAR_GP_PIN(6, 29), 4183 }; 4184 static const unsigned int tpu_to1_mux[] = { 4185 TPU0TO1_MARK, 4186 }; 4187 static const unsigned int tpu_to2_pins[] = { 4188 /* TPU0TO2 */ 4189 RCAR_GP_PIN(6, 30), 4190 }; 4191 static const unsigned int tpu_to2_mux[] = { 4192 TPU0TO2_MARK, 4193 }; 4194 static const unsigned int tpu_to3_pins[] = { 4195 /* TPU0TO3 */ 4196 RCAR_GP_PIN(6, 31), 4197 }; 4198 static const unsigned int tpu_to3_mux[] = { 4199 TPU0TO3_MARK, 4200 }; 4201 4202 /* - USB0 ------------------------------------------------------------------- */ 4203 static const unsigned int usb0_pins[] = { 4204 /* PWEN, OVC */ 4205 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), 4206 }; 4207 4208 static const unsigned int usb0_mux[] = { 4209 USB0_PWEN_MARK, USB0_OVC_MARK, 4210 }; 4211 4212 /* - USB1 ------------------------------------------------------------------- */ 4213 static const unsigned int usb1_pins[] = { 4214 /* PWEN, OVC */ 4215 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 4216 }; 4217 4218 static const unsigned int usb1_mux[] = { 4219 USB1_PWEN_MARK, USB1_OVC_MARK, 4220 }; 4221 4222 /* - USB30 ------------------------------------------------------------------ */ 4223 static const unsigned int usb30_pins[] = { 4224 /* PWEN, OVC */ 4225 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), 4226 }; 4227 4228 static const unsigned int usb30_mux[] = { 4229 USB30_PWEN_MARK, USB30_OVC_MARK, 4230 }; 4231 4232 /* - VIN4 ------------------------------------------------------------------- */ 4233 static const unsigned int vin4_data18_a_pins[] = { 4234 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 4235 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 4236 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 4237 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 4238 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4239 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4240 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4241 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4242 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4243 }; 4244 4245 static const unsigned int vin4_data18_a_mux[] = { 4246 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, 4247 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, 4248 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, 4249 VI4_DATA10_MARK, VI4_DATA11_MARK, 4250 VI4_DATA12_MARK, VI4_DATA13_MARK, 4251 VI4_DATA14_MARK, VI4_DATA15_MARK, 4252 VI4_DATA18_MARK, VI4_DATA19_MARK, 4253 VI4_DATA20_MARK, VI4_DATA21_MARK, 4254 VI4_DATA22_MARK, VI4_DATA23_MARK, 4255 }; 4256 4257 static const union vin_data vin4_data_a_pins = { 4258 .data24 = { 4259 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), 4260 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 4261 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 4262 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 4263 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), 4264 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 4265 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4266 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4267 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 4268 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4269 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4270 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4271 }, 4272 }; 4273 4274 static const union vin_data vin4_data_a_mux = { 4275 .data24 = { 4276 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, 4277 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, 4278 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, 4279 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, 4280 VI4_DATA8_MARK, VI4_DATA9_MARK, 4281 VI4_DATA10_MARK, VI4_DATA11_MARK, 4282 VI4_DATA12_MARK, VI4_DATA13_MARK, 4283 VI4_DATA14_MARK, VI4_DATA15_MARK, 4284 VI4_DATA16_MARK, VI4_DATA17_MARK, 4285 VI4_DATA18_MARK, VI4_DATA19_MARK, 4286 VI4_DATA20_MARK, VI4_DATA21_MARK, 4287 VI4_DATA22_MARK, VI4_DATA23_MARK, 4288 }, 4289 }; 4290 4291 static const unsigned int vin4_data18_b_pins[] = { 4292 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), 4293 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 4294 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 4295 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 4296 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4297 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4298 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4299 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4300 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4301 }; 4302 4303 static const unsigned int vin4_data18_b_mux[] = { 4304 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, 4305 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, 4306 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, 4307 VI4_DATA10_MARK, VI4_DATA11_MARK, 4308 VI4_DATA12_MARK, VI4_DATA13_MARK, 4309 VI4_DATA14_MARK, VI4_DATA15_MARK, 4310 VI4_DATA18_MARK, VI4_DATA19_MARK, 4311 VI4_DATA20_MARK, VI4_DATA21_MARK, 4312 VI4_DATA22_MARK, VI4_DATA23_MARK, 4313 }; 4314 4315 static const union vin_data vin4_data_b_pins = { 4316 .data24 = { 4317 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 4318 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), 4319 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 4320 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 4321 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), 4322 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 4323 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4324 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4325 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 4326 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4327 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4328 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4329 }, 4330 }; 4331 4332 static const union vin_data vin4_data_b_mux = { 4333 .data24 = { 4334 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, 4335 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, 4336 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, 4337 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, 4338 VI4_DATA8_MARK, VI4_DATA9_MARK, 4339 VI4_DATA10_MARK, VI4_DATA11_MARK, 4340 VI4_DATA12_MARK, VI4_DATA13_MARK, 4341 VI4_DATA14_MARK, VI4_DATA15_MARK, 4342 VI4_DATA16_MARK, VI4_DATA17_MARK, 4343 VI4_DATA18_MARK, VI4_DATA19_MARK, 4344 VI4_DATA20_MARK, VI4_DATA21_MARK, 4345 VI4_DATA22_MARK, VI4_DATA23_MARK, 4346 }, 4347 }; 4348 4349 static const unsigned int vin4_g8_pins[] = { 4350 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), 4351 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 4352 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4353 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4354 }; 4355 4356 static const unsigned int vin4_g8_mux[] = { 4357 VI4_DATA8_MARK, VI4_DATA9_MARK, 4358 VI4_DATA10_MARK, VI4_DATA11_MARK, 4359 VI4_DATA12_MARK, VI4_DATA13_MARK, 4360 VI4_DATA14_MARK, VI4_DATA15_MARK, 4361 }; 4362 4363 static const unsigned int vin4_sync_pins[] = { 4364 /* VSYNC_N, HSYNC_N */ 4365 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), 4366 }; 4367 4368 static const unsigned int vin4_sync_mux[] = { 4369 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK, 4370 }; 4371 4372 static const unsigned int vin4_field_pins[] = { 4373 RCAR_GP_PIN(1, 16), 4374 }; 4375 4376 static const unsigned int vin4_field_mux[] = { 4377 VI4_FIELD_MARK, 4378 }; 4379 4380 static const unsigned int vin4_clkenb_pins[] = { 4381 RCAR_GP_PIN(1, 19), 4382 }; 4383 4384 static const unsigned int vin4_clkenb_mux[] = { 4385 VI4_CLKENB_MARK, 4386 }; 4387 4388 static const unsigned int vin4_clk_pins[] = { 4389 RCAR_GP_PIN(1, 27), 4390 }; 4391 4392 static const unsigned int vin4_clk_mux[] = { 4393 VI4_CLK_MARK, 4394 }; 4395 4396 /* - VIN5 ------------------------------------------------------------------- */ 4397 static const union vin_data16 vin5_data_pins = { 4398 .data16 = { 4399 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 4400 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4401 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4402 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4403 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), 4404 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), 4405 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4406 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4407 }, 4408 }; 4409 4410 static const union vin_data16 vin5_data_mux = { 4411 .data16 = { 4412 VI5_DATA0_MARK, VI5_DATA1_MARK, 4413 VI5_DATA2_MARK, VI5_DATA3_MARK, 4414 VI5_DATA4_MARK, VI5_DATA5_MARK, 4415 VI5_DATA6_MARK, VI5_DATA7_MARK, 4416 VI5_DATA8_MARK, VI5_DATA9_MARK, 4417 VI5_DATA10_MARK, VI5_DATA11_MARK, 4418 VI5_DATA12_MARK, VI5_DATA13_MARK, 4419 VI5_DATA14_MARK, VI5_DATA15_MARK, 4420 }, 4421 }; 4422 4423 static const unsigned int vin5_high8_pins[] = { 4424 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), 4425 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), 4426 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4427 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4428 }; 4429 4430 static const unsigned int vin5_high8_mux[] = { 4431 VI5_DATA8_MARK, VI5_DATA9_MARK, 4432 VI5_DATA10_MARK, VI5_DATA11_MARK, 4433 VI5_DATA12_MARK, VI5_DATA13_MARK, 4434 VI5_DATA14_MARK, VI5_DATA15_MARK, 4435 }; 4436 4437 static const unsigned int vin5_sync_pins[] = { 4438 /* VSYNC_N, HSYNC_N */ 4439 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10), 4440 }; 4441 4442 static const unsigned int vin5_sync_mux[] = { 4443 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK, 4444 }; 4445 4446 static const unsigned int vin5_field_pins[] = { 4447 RCAR_GP_PIN(1, 11), 4448 }; 4449 4450 static const unsigned int vin5_field_mux[] = { 4451 VI5_FIELD_MARK, 4452 }; 4453 4454 static const unsigned int vin5_clkenb_pins[] = { 4455 RCAR_GP_PIN(1, 20), 4456 }; 4457 4458 static const unsigned int vin5_clkenb_mux[] = { 4459 VI5_CLKENB_MARK, 4460 }; 4461 4462 static const unsigned int vin5_clk_pins[] = { 4463 RCAR_GP_PIN(1, 21), 4464 }; 4465 4466 static const unsigned int vin5_clk_mux[] = { 4467 VI5_CLK_MARK, 4468 }; 4469 4470 static const struct { 4471 struct sh_pfc_pin_group common[326]; 4472 #ifdef CONFIG_PINCTRL_PFC_R8A77965 4473 struct sh_pfc_pin_group automotive[31]; 4474 #endif 4475 } pinmux_groups = { 4476 .common = { 4477 SH_PFC_PIN_GROUP(audio_clk_a_a), 4478 SH_PFC_PIN_GROUP(audio_clk_a_b), 4479 SH_PFC_PIN_GROUP(audio_clk_a_c), 4480 SH_PFC_PIN_GROUP(audio_clk_b_a), 4481 SH_PFC_PIN_GROUP(audio_clk_b_b), 4482 SH_PFC_PIN_GROUP(audio_clk_c_a), 4483 SH_PFC_PIN_GROUP(audio_clk_c_b), 4484 SH_PFC_PIN_GROUP(audio_clkout_a), 4485 SH_PFC_PIN_GROUP(audio_clkout_b), 4486 SH_PFC_PIN_GROUP(audio_clkout_c), 4487 SH_PFC_PIN_GROUP(audio_clkout_d), 4488 SH_PFC_PIN_GROUP(audio_clkout1_a), 4489 SH_PFC_PIN_GROUP(audio_clkout1_b), 4490 SH_PFC_PIN_GROUP(audio_clkout2_a), 4491 SH_PFC_PIN_GROUP(audio_clkout2_b), 4492 SH_PFC_PIN_GROUP(audio_clkout3_a), 4493 SH_PFC_PIN_GROUP(audio_clkout3_b), 4494 SH_PFC_PIN_GROUP(avb_link), 4495 SH_PFC_PIN_GROUP(avb_magic), 4496 SH_PFC_PIN_GROUP(avb_phy_int), 4497 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */ 4498 SH_PFC_PIN_GROUP(avb_mdio), 4499 SH_PFC_PIN_GROUP(avb_mii), 4500 SH_PFC_PIN_GROUP(avb_avtp_pps), 4501 SH_PFC_PIN_GROUP(avb_avtp_match_a), 4502 SH_PFC_PIN_GROUP(avb_avtp_capture_a), 4503 SH_PFC_PIN_GROUP(avb_avtp_match_b), 4504 SH_PFC_PIN_GROUP(avb_avtp_capture_b), 4505 SH_PFC_PIN_GROUP(can0_data_a), 4506 SH_PFC_PIN_GROUP(can0_data_b), 4507 SH_PFC_PIN_GROUP(can1_data), 4508 SH_PFC_PIN_GROUP(can_clk), 4509 SH_PFC_PIN_GROUP(canfd0_data_a), 4510 SH_PFC_PIN_GROUP(canfd0_data_b), 4511 SH_PFC_PIN_GROUP(canfd1_data), 4512 SH_PFC_PIN_GROUP(du_rgb666), 4513 SH_PFC_PIN_GROUP(du_rgb888), 4514 SH_PFC_PIN_GROUP(du_clk_out_0), 4515 SH_PFC_PIN_GROUP(du_clk_out_1), 4516 SH_PFC_PIN_GROUP(du_sync), 4517 SH_PFC_PIN_GROUP(du_oddf), 4518 SH_PFC_PIN_GROUP(du_cde), 4519 SH_PFC_PIN_GROUP(du_disp), 4520 SH_PFC_PIN_GROUP(hscif0_data), 4521 SH_PFC_PIN_GROUP(hscif0_clk), 4522 SH_PFC_PIN_GROUP(hscif0_ctrl), 4523 SH_PFC_PIN_GROUP(hscif1_data_a), 4524 SH_PFC_PIN_GROUP(hscif1_clk_a), 4525 SH_PFC_PIN_GROUP(hscif1_ctrl_a), 4526 SH_PFC_PIN_GROUP(hscif1_data_b), 4527 SH_PFC_PIN_GROUP(hscif1_clk_b), 4528 SH_PFC_PIN_GROUP(hscif1_ctrl_b), 4529 SH_PFC_PIN_GROUP(hscif2_data_a), 4530 SH_PFC_PIN_GROUP(hscif2_clk_a), 4531 SH_PFC_PIN_GROUP(hscif2_ctrl_a), 4532 SH_PFC_PIN_GROUP(hscif2_data_b), 4533 SH_PFC_PIN_GROUP(hscif2_clk_b), 4534 SH_PFC_PIN_GROUP(hscif2_ctrl_b), 4535 SH_PFC_PIN_GROUP(hscif2_data_c), 4536 SH_PFC_PIN_GROUP(hscif2_clk_c), 4537 SH_PFC_PIN_GROUP(hscif2_ctrl_c), 4538 SH_PFC_PIN_GROUP(hscif3_data_a), 4539 SH_PFC_PIN_GROUP(hscif3_clk), 4540 SH_PFC_PIN_GROUP(hscif3_ctrl), 4541 SH_PFC_PIN_GROUP(hscif3_data_b), 4542 SH_PFC_PIN_GROUP(hscif3_data_c), 4543 SH_PFC_PIN_GROUP(hscif3_data_d), 4544 SH_PFC_PIN_GROUP(hscif4_data_a), 4545 SH_PFC_PIN_GROUP(hscif4_clk), 4546 SH_PFC_PIN_GROUP(hscif4_ctrl), 4547 SH_PFC_PIN_GROUP(hscif4_data_b), 4548 SH_PFC_PIN_GROUP(i2c0), 4549 SH_PFC_PIN_GROUP(i2c1_a), 4550 SH_PFC_PIN_GROUP(i2c1_b), 4551 SH_PFC_PIN_GROUP(i2c2_a), 4552 SH_PFC_PIN_GROUP(i2c2_b), 4553 SH_PFC_PIN_GROUP(i2c3), 4554 SH_PFC_PIN_GROUP(i2c5), 4555 SH_PFC_PIN_GROUP(i2c6_a), 4556 SH_PFC_PIN_GROUP(i2c6_b), 4557 SH_PFC_PIN_GROUP(i2c6_c), 4558 SH_PFC_PIN_GROUP(intc_ex_irq0), 4559 SH_PFC_PIN_GROUP(intc_ex_irq1), 4560 SH_PFC_PIN_GROUP(intc_ex_irq2), 4561 SH_PFC_PIN_GROUP(intc_ex_irq3), 4562 SH_PFC_PIN_GROUP(intc_ex_irq4), 4563 SH_PFC_PIN_GROUP(intc_ex_irq5), 4564 SH_PFC_PIN_GROUP(msiof0_clk), 4565 SH_PFC_PIN_GROUP(msiof0_sync), 4566 SH_PFC_PIN_GROUP(msiof0_ss1), 4567 SH_PFC_PIN_GROUP(msiof0_ss2), 4568 SH_PFC_PIN_GROUP(msiof0_txd), 4569 SH_PFC_PIN_GROUP(msiof0_rxd), 4570 SH_PFC_PIN_GROUP(msiof1_clk_a), 4571 SH_PFC_PIN_GROUP(msiof1_sync_a), 4572 SH_PFC_PIN_GROUP(msiof1_ss1_a), 4573 SH_PFC_PIN_GROUP(msiof1_ss2_a), 4574 SH_PFC_PIN_GROUP(msiof1_txd_a), 4575 SH_PFC_PIN_GROUP(msiof1_rxd_a), 4576 SH_PFC_PIN_GROUP(msiof1_clk_b), 4577 SH_PFC_PIN_GROUP(msiof1_sync_b), 4578 SH_PFC_PIN_GROUP(msiof1_ss1_b), 4579 SH_PFC_PIN_GROUP(msiof1_ss2_b), 4580 SH_PFC_PIN_GROUP(msiof1_txd_b), 4581 SH_PFC_PIN_GROUP(msiof1_rxd_b), 4582 SH_PFC_PIN_GROUP(msiof1_clk_c), 4583 SH_PFC_PIN_GROUP(msiof1_sync_c), 4584 SH_PFC_PIN_GROUP(msiof1_ss1_c), 4585 SH_PFC_PIN_GROUP(msiof1_ss2_c), 4586 SH_PFC_PIN_GROUP(msiof1_txd_c), 4587 SH_PFC_PIN_GROUP(msiof1_rxd_c), 4588 SH_PFC_PIN_GROUP(msiof1_clk_d), 4589 SH_PFC_PIN_GROUP(msiof1_sync_d), 4590 SH_PFC_PIN_GROUP(msiof1_ss1_d), 4591 SH_PFC_PIN_GROUP(msiof1_ss2_d), 4592 SH_PFC_PIN_GROUP(msiof1_txd_d), 4593 SH_PFC_PIN_GROUP(msiof1_rxd_d), 4594 SH_PFC_PIN_GROUP(msiof1_clk_e), 4595 SH_PFC_PIN_GROUP(msiof1_sync_e), 4596 SH_PFC_PIN_GROUP(msiof1_ss1_e), 4597 SH_PFC_PIN_GROUP(msiof1_ss2_e), 4598 SH_PFC_PIN_GROUP(msiof1_txd_e), 4599 SH_PFC_PIN_GROUP(msiof1_rxd_e), 4600 SH_PFC_PIN_GROUP(msiof1_clk_f), 4601 SH_PFC_PIN_GROUP(msiof1_sync_f), 4602 SH_PFC_PIN_GROUP(msiof1_ss1_f), 4603 SH_PFC_PIN_GROUP(msiof1_ss2_f), 4604 SH_PFC_PIN_GROUP(msiof1_txd_f), 4605 SH_PFC_PIN_GROUP(msiof1_rxd_f), 4606 SH_PFC_PIN_GROUP(msiof1_clk_g), 4607 SH_PFC_PIN_GROUP(msiof1_sync_g), 4608 SH_PFC_PIN_GROUP(msiof1_ss1_g), 4609 SH_PFC_PIN_GROUP(msiof1_ss2_g), 4610 SH_PFC_PIN_GROUP(msiof1_txd_g), 4611 SH_PFC_PIN_GROUP(msiof1_rxd_g), 4612 SH_PFC_PIN_GROUP(msiof2_clk_a), 4613 SH_PFC_PIN_GROUP(msiof2_sync_a), 4614 SH_PFC_PIN_GROUP(msiof2_ss1_a), 4615 SH_PFC_PIN_GROUP(msiof2_ss2_a), 4616 SH_PFC_PIN_GROUP(msiof2_txd_a), 4617 SH_PFC_PIN_GROUP(msiof2_rxd_a), 4618 SH_PFC_PIN_GROUP(msiof2_clk_b), 4619 SH_PFC_PIN_GROUP(msiof2_sync_b), 4620 SH_PFC_PIN_GROUP(msiof2_ss1_b), 4621 SH_PFC_PIN_GROUP(msiof2_ss2_b), 4622 SH_PFC_PIN_GROUP(msiof2_txd_b), 4623 SH_PFC_PIN_GROUP(msiof2_rxd_b), 4624 SH_PFC_PIN_GROUP(msiof2_clk_c), 4625 SH_PFC_PIN_GROUP(msiof2_sync_c), 4626 SH_PFC_PIN_GROUP(msiof2_ss1_c), 4627 SH_PFC_PIN_GROUP(msiof2_ss2_c), 4628 SH_PFC_PIN_GROUP(msiof2_txd_c), 4629 SH_PFC_PIN_GROUP(msiof2_rxd_c), 4630 SH_PFC_PIN_GROUP(msiof2_clk_d), 4631 SH_PFC_PIN_GROUP(msiof2_sync_d), 4632 SH_PFC_PIN_GROUP(msiof2_ss1_d), 4633 SH_PFC_PIN_GROUP(msiof2_ss2_d), 4634 SH_PFC_PIN_GROUP(msiof2_txd_d), 4635 SH_PFC_PIN_GROUP(msiof2_rxd_d), 4636 SH_PFC_PIN_GROUP(msiof3_clk_a), 4637 SH_PFC_PIN_GROUP(msiof3_sync_a), 4638 SH_PFC_PIN_GROUP(msiof3_ss1_a), 4639 SH_PFC_PIN_GROUP(msiof3_ss2_a), 4640 SH_PFC_PIN_GROUP(msiof3_txd_a), 4641 SH_PFC_PIN_GROUP(msiof3_rxd_a), 4642 SH_PFC_PIN_GROUP(msiof3_clk_b), 4643 SH_PFC_PIN_GROUP(msiof3_sync_b), 4644 SH_PFC_PIN_GROUP(msiof3_ss1_b), 4645 SH_PFC_PIN_GROUP(msiof3_ss2_b), 4646 SH_PFC_PIN_GROUP(msiof3_txd_b), 4647 SH_PFC_PIN_GROUP(msiof3_rxd_b), 4648 SH_PFC_PIN_GROUP(msiof3_clk_c), 4649 SH_PFC_PIN_GROUP(msiof3_sync_c), 4650 SH_PFC_PIN_GROUP(msiof3_txd_c), 4651 SH_PFC_PIN_GROUP(msiof3_rxd_c), 4652 SH_PFC_PIN_GROUP(msiof3_clk_d), 4653 SH_PFC_PIN_GROUP(msiof3_sync_d), 4654 SH_PFC_PIN_GROUP(msiof3_ss1_d), 4655 SH_PFC_PIN_GROUP(msiof3_txd_d), 4656 SH_PFC_PIN_GROUP(msiof3_rxd_d), 4657 SH_PFC_PIN_GROUP(msiof3_clk_e), 4658 SH_PFC_PIN_GROUP(msiof3_sync_e), 4659 SH_PFC_PIN_GROUP(msiof3_ss1_e), 4660 SH_PFC_PIN_GROUP(msiof3_ss2_e), 4661 SH_PFC_PIN_GROUP(msiof3_txd_e), 4662 SH_PFC_PIN_GROUP(msiof3_rxd_e), 4663 SH_PFC_PIN_GROUP(pwm0), 4664 SH_PFC_PIN_GROUP(pwm1_a), 4665 SH_PFC_PIN_GROUP(pwm1_b), 4666 SH_PFC_PIN_GROUP(pwm2_a), 4667 SH_PFC_PIN_GROUP(pwm2_b), 4668 SH_PFC_PIN_GROUP(pwm3_a), 4669 SH_PFC_PIN_GROUP(pwm3_b), 4670 SH_PFC_PIN_GROUP(pwm4_a), 4671 SH_PFC_PIN_GROUP(pwm4_b), 4672 SH_PFC_PIN_GROUP(pwm5_a), 4673 SH_PFC_PIN_GROUP(pwm5_b), 4674 SH_PFC_PIN_GROUP(pwm6_a), 4675 SH_PFC_PIN_GROUP(pwm6_b), 4676 SH_PFC_PIN_GROUP(qspi0_ctrl), 4677 SH_PFC_PIN_GROUP(qspi0_data2), 4678 SH_PFC_PIN_GROUP(qspi0_data4), 4679 SH_PFC_PIN_GROUP(qspi1_ctrl), 4680 SH_PFC_PIN_GROUP(qspi1_data2), 4681 SH_PFC_PIN_GROUP(qspi1_data4), 4682 SH_PFC_PIN_GROUP(sata0_devslp_a), 4683 SH_PFC_PIN_GROUP(sata0_devslp_b), 4684 SH_PFC_PIN_GROUP(scif0_data), 4685 SH_PFC_PIN_GROUP(scif0_clk), 4686 SH_PFC_PIN_GROUP(scif0_ctrl), 4687 SH_PFC_PIN_GROUP(scif1_data_a), 4688 SH_PFC_PIN_GROUP(scif1_clk), 4689 SH_PFC_PIN_GROUP(scif1_ctrl), 4690 SH_PFC_PIN_GROUP(scif1_data_b), 4691 SH_PFC_PIN_GROUP(scif2_data_a), 4692 SH_PFC_PIN_GROUP(scif2_clk), 4693 SH_PFC_PIN_GROUP(scif2_data_b), 4694 SH_PFC_PIN_GROUP(scif3_data_a), 4695 SH_PFC_PIN_GROUP(scif3_clk), 4696 SH_PFC_PIN_GROUP(scif3_ctrl), 4697 SH_PFC_PIN_GROUP(scif3_data_b), 4698 SH_PFC_PIN_GROUP(scif4_data_a), 4699 SH_PFC_PIN_GROUP(scif4_clk_a), 4700 SH_PFC_PIN_GROUP(scif4_ctrl_a), 4701 SH_PFC_PIN_GROUP(scif4_data_b), 4702 SH_PFC_PIN_GROUP(scif4_clk_b), 4703 SH_PFC_PIN_GROUP(scif4_ctrl_b), 4704 SH_PFC_PIN_GROUP(scif4_data_c), 4705 SH_PFC_PIN_GROUP(scif4_clk_c), 4706 SH_PFC_PIN_GROUP(scif4_ctrl_c), 4707 SH_PFC_PIN_GROUP(scif5_data_a), 4708 SH_PFC_PIN_GROUP(scif5_clk_a), 4709 SH_PFC_PIN_GROUP(scif5_data_b), 4710 SH_PFC_PIN_GROUP(scif5_clk_b), 4711 SH_PFC_PIN_GROUP(scif_clk_a), 4712 SH_PFC_PIN_GROUP(scif_clk_b), 4713 SH_PFC_PIN_GROUP(sdhi0_data1), 4714 SH_PFC_PIN_GROUP(sdhi0_data4), 4715 SH_PFC_PIN_GROUP(sdhi0_ctrl), 4716 SH_PFC_PIN_GROUP(sdhi0_cd), 4717 SH_PFC_PIN_GROUP(sdhi0_wp), 4718 SH_PFC_PIN_GROUP(sdhi1_data1), 4719 SH_PFC_PIN_GROUP(sdhi1_data4), 4720 SH_PFC_PIN_GROUP(sdhi1_ctrl), 4721 SH_PFC_PIN_GROUP(sdhi1_cd), 4722 SH_PFC_PIN_GROUP(sdhi1_wp), 4723 SH_PFC_PIN_GROUP(sdhi2_data1), 4724 SH_PFC_PIN_GROUP(sdhi2_data4), 4725 SH_PFC_PIN_GROUP(sdhi2_data8), 4726 SH_PFC_PIN_GROUP(sdhi2_ctrl), 4727 SH_PFC_PIN_GROUP(sdhi2_cd_a), 4728 SH_PFC_PIN_GROUP(sdhi2_wp_a), 4729 SH_PFC_PIN_GROUP(sdhi2_cd_b), 4730 SH_PFC_PIN_GROUP(sdhi2_wp_b), 4731 SH_PFC_PIN_GROUP(sdhi2_ds), 4732 SH_PFC_PIN_GROUP(sdhi3_data1), 4733 SH_PFC_PIN_GROUP(sdhi3_data4), 4734 SH_PFC_PIN_GROUP(sdhi3_data8), 4735 SH_PFC_PIN_GROUP(sdhi3_ctrl), 4736 SH_PFC_PIN_GROUP(sdhi3_cd), 4737 SH_PFC_PIN_GROUP(sdhi3_wp), 4738 SH_PFC_PIN_GROUP(sdhi3_ds), 4739 SH_PFC_PIN_GROUP(ssi0_data), 4740 SH_PFC_PIN_GROUP(ssi01239_ctrl), 4741 SH_PFC_PIN_GROUP(ssi1_data_a), 4742 SH_PFC_PIN_GROUP(ssi1_data_b), 4743 SH_PFC_PIN_GROUP(ssi1_ctrl_a), 4744 SH_PFC_PIN_GROUP(ssi1_ctrl_b), 4745 SH_PFC_PIN_GROUP(ssi2_data_a), 4746 SH_PFC_PIN_GROUP(ssi2_data_b), 4747 SH_PFC_PIN_GROUP(ssi2_ctrl_a), 4748 SH_PFC_PIN_GROUP(ssi2_ctrl_b), 4749 SH_PFC_PIN_GROUP(ssi3_data), 4750 SH_PFC_PIN_GROUP(ssi349_ctrl), 4751 SH_PFC_PIN_GROUP(ssi4_data), 4752 SH_PFC_PIN_GROUP(ssi4_ctrl), 4753 SH_PFC_PIN_GROUP(ssi5_data), 4754 SH_PFC_PIN_GROUP(ssi5_ctrl), 4755 SH_PFC_PIN_GROUP(ssi6_data), 4756 SH_PFC_PIN_GROUP(ssi6_ctrl), 4757 SH_PFC_PIN_GROUP(ssi7_data), 4758 SH_PFC_PIN_GROUP(ssi78_ctrl), 4759 SH_PFC_PIN_GROUP(ssi8_data), 4760 SH_PFC_PIN_GROUP(ssi9_data_a), 4761 SH_PFC_PIN_GROUP(ssi9_data_b), 4762 SH_PFC_PIN_GROUP(ssi9_ctrl_a), 4763 SH_PFC_PIN_GROUP(ssi9_ctrl_b), 4764 SH_PFC_PIN_GROUP(tmu_tclk1_a), 4765 SH_PFC_PIN_GROUP(tmu_tclk1_b), 4766 SH_PFC_PIN_GROUP(tmu_tclk2_a), 4767 SH_PFC_PIN_GROUP(tmu_tclk2_b), 4768 SH_PFC_PIN_GROUP(tpu_to0), 4769 SH_PFC_PIN_GROUP(tpu_to1), 4770 SH_PFC_PIN_GROUP(tpu_to2), 4771 SH_PFC_PIN_GROUP(tpu_to3), 4772 SH_PFC_PIN_GROUP(usb0), 4773 SH_PFC_PIN_GROUP(usb1), 4774 SH_PFC_PIN_GROUP(usb30), 4775 VIN_DATA_PIN_GROUP(vin4_data, 8, _a), 4776 VIN_DATA_PIN_GROUP(vin4_data, 10, _a), 4777 VIN_DATA_PIN_GROUP(vin4_data, 12, _a), 4778 VIN_DATA_PIN_GROUP(vin4_data, 16, _a), 4779 SH_PFC_PIN_GROUP(vin4_data18_a), 4780 VIN_DATA_PIN_GROUP(vin4_data, 20, _a), 4781 VIN_DATA_PIN_GROUP(vin4_data, 24, _a), 4782 VIN_DATA_PIN_GROUP(vin4_data, 8, _b), 4783 VIN_DATA_PIN_GROUP(vin4_data, 10, _b), 4784 VIN_DATA_PIN_GROUP(vin4_data, 12, _b), 4785 VIN_DATA_PIN_GROUP(vin4_data, 16, _b), 4786 SH_PFC_PIN_GROUP(vin4_data18_b), 4787 VIN_DATA_PIN_GROUP(vin4_data, 20, _b), 4788 VIN_DATA_PIN_GROUP(vin4_data, 24, _b), 4789 SH_PFC_PIN_GROUP(vin4_g8), 4790 SH_PFC_PIN_GROUP(vin4_sync), 4791 SH_PFC_PIN_GROUP(vin4_field), 4792 SH_PFC_PIN_GROUP(vin4_clkenb), 4793 SH_PFC_PIN_GROUP(vin4_clk), 4794 VIN_DATA_PIN_GROUP(vin5_data, 8), 4795 VIN_DATA_PIN_GROUP(vin5_data, 10), 4796 VIN_DATA_PIN_GROUP(vin5_data, 12), 4797 VIN_DATA_PIN_GROUP(vin5_data, 16), 4798 SH_PFC_PIN_GROUP(vin5_high8), 4799 SH_PFC_PIN_GROUP(vin5_sync), 4800 SH_PFC_PIN_GROUP(vin5_field), 4801 SH_PFC_PIN_GROUP(vin5_clkenb), 4802 SH_PFC_PIN_GROUP(vin5_clk), 4803 }, 4804 #ifdef CONFIG_PINCTRL_PFC_R8A77965 4805 .automotive = { 4806 SH_PFC_PIN_GROUP(drif0_ctrl_a), 4807 SH_PFC_PIN_GROUP(drif0_data0_a), 4808 SH_PFC_PIN_GROUP(drif0_data1_a), 4809 SH_PFC_PIN_GROUP(drif0_ctrl_b), 4810 SH_PFC_PIN_GROUP(drif0_data0_b), 4811 SH_PFC_PIN_GROUP(drif0_data1_b), 4812 SH_PFC_PIN_GROUP(drif0_ctrl_c), 4813 SH_PFC_PIN_GROUP(drif0_data0_c), 4814 SH_PFC_PIN_GROUP(drif0_data1_c), 4815 SH_PFC_PIN_GROUP(drif1_ctrl_a), 4816 SH_PFC_PIN_GROUP(drif1_data0_a), 4817 SH_PFC_PIN_GROUP(drif1_data1_a), 4818 SH_PFC_PIN_GROUP(drif1_ctrl_b), 4819 SH_PFC_PIN_GROUP(drif1_data0_b), 4820 SH_PFC_PIN_GROUP(drif1_data1_b), 4821 SH_PFC_PIN_GROUP(drif1_ctrl_c), 4822 SH_PFC_PIN_GROUP(drif1_data0_c), 4823 SH_PFC_PIN_GROUP(drif1_data1_c), 4824 SH_PFC_PIN_GROUP(drif2_ctrl_a), 4825 SH_PFC_PIN_GROUP(drif2_data0_a), 4826 SH_PFC_PIN_GROUP(drif2_data1_a), 4827 SH_PFC_PIN_GROUP(drif2_ctrl_b), 4828 SH_PFC_PIN_GROUP(drif2_data0_b), 4829 SH_PFC_PIN_GROUP(drif2_data1_b), 4830 SH_PFC_PIN_GROUP(drif3_ctrl_a), 4831 SH_PFC_PIN_GROUP(drif3_data0_a), 4832 SH_PFC_PIN_GROUP(drif3_data1_a), 4833 SH_PFC_PIN_GROUP(drif3_ctrl_b), 4834 SH_PFC_PIN_GROUP(drif3_data0_b), 4835 SH_PFC_PIN_GROUP(drif3_data1_b), 4836 SH_PFC_PIN_GROUP(mlb_3pin), 4837 } 4838 #endif /* CONFIG_PINCTRL_PFC_R8A77965 */ 4839 }; 4840 4841 static const char * const audio_clk_groups[] = { 4842 "audio_clk_a_a", 4843 "audio_clk_a_b", 4844 "audio_clk_a_c", 4845 "audio_clk_b_a", 4846 "audio_clk_b_b", 4847 "audio_clk_c_a", 4848 "audio_clk_c_b", 4849 "audio_clkout_a", 4850 "audio_clkout_b", 4851 "audio_clkout_c", 4852 "audio_clkout_d", 4853 "audio_clkout1_a", 4854 "audio_clkout1_b", 4855 "audio_clkout2_a", 4856 "audio_clkout2_b", 4857 "audio_clkout3_a", 4858 "audio_clkout3_b", 4859 }; 4860 4861 static const char * const avb_groups[] = { 4862 "avb_link", 4863 "avb_magic", 4864 "avb_phy_int", 4865 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */ 4866 "avb_mdio", 4867 "avb_mii", 4868 "avb_avtp_pps", 4869 "avb_avtp_match_a", 4870 "avb_avtp_capture_a", 4871 "avb_avtp_match_b", 4872 "avb_avtp_capture_b", 4873 }; 4874 4875 static const char * const can0_groups[] = { 4876 "can0_data_a", 4877 "can0_data_b", 4878 }; 4879 4880 static const char * const can1_groups[] = { 4881 "can1_data", 4882 }; 4883 4884 static const char * const can_clk_groups[] = { 4885 "can_clk", 4886 }; 4887 4888 static const char * const canfd0_groups[] = { 4889 "canfd0_data_a", 4890 "canfd0_data_b", 4891 }; 4892 4893 static const char * const canfd1_groups[] = { 4894 "canfd1_data", 4895 }; 4896 4897 #ifdef CONFIG_PINCTRL_PFC_R8A77965 4898 static const char * const drif0_groups[] = { 4899 "drif0_ctrl_a", 4900 "drif0_data0_a", 4901 "drif0_data1_a", 4902 "drif0_ctrl_b", 4903 "drif0_data0_b", 4904 "drif0_data1_b", 4905 "drif0_ctrl_c", 4906 "drif0_data0_c", 4907 "drif0_data1_c", 4908 }; 4909 4910 static const char * const drif1_groups[] = { 4911 "drif1_ctrl_a", 4912 "drif1_data0_a", 4913 "drif1_data1_a", 4914 "drif1_ctrl_b", 4915 "drif1_data0_b", 4916 "drif1_data1_b", 4917 "drif1_ctrl_c", 4918 "drif1_data0_c", 4919 "drif1_data1_c", 4920 }; 4921 4922 static const char * const drif2_groups[] = { 4923 "drif2_ctrl_a", 4924 "drif2_data0_a", 4925 "drif2_data1_a", 4926 "drif2_ctrl_b", 4927 "drif2_data0_b", 4928 "drif2_data1_b", 4929 }; 4930 4931 static const char * const drif3_groups[] = { 4932 "drif3_ctrl_a", 4933 "drif3_data0_a", 4934 "drif3_data1_a", 4935 "drif3_ctrl_b", 4936 "drif3_data0_b", 4937 "drif3_data1_b", 4938 }; 4939 #endif /* CONFIG_PINCTRL_PFC_R8A77965 */ 4940 4941 static const char * const du_groups[] = { 4942 "du_rgb666", 4943 "du_rgb888", 4944 "du_clk_out_0", 4945 "du_clk_out_1", 4946 "du_sync", 4947 "du_oddf", 4948 "du_cde", 4949 "du_disp", 4950 }; 4951 4952 static const char * const hscif0_groups[] = { 4953 "hscif0_data", 4954 "hscif0_clk", 4955 "hscif0_ctrl", 4956 }; 4957 4958 static const char * const hscif1_groups[] = { 4959 "hscif1_data_a", 4960 "hscif1_clk_a", 4961 "hscif1_ctrl_a", 4962 "hscif1_data_b", 4963 "hscif1_clk_b", 4964 "hscif1_ctrl_b", 4965 }; 4966 4967 static const char * const hscif2_groups[] = { 4968 "hscif2_data_a", 4969 "hscif2_clk_a", 4970 "hscif2_ctrl_a", 4971 "hscif2_data_b", 4972 "hscif2_clk_b", 4973 "hscif2_ctrl_b", 4974 "hscif2_data_c", 4975 "hscif2_clk_c", 4976 "hscif2_ctrl_c", 4977 }; 4978 4979 static const char * const hscif3_groups[] = { 4980 "hscif3_data_a", 4981 "hscif3_clk", 4982 "hscif3_ctrl", 4983 "hscif3_data_b", 4984 "hscif3_data_c", 4985 "hscif3_data_d", 4986 }; 4987 4988 static const char * const hscif4_groups[] = { 4989 "hscif4_data_a", 4990 "hscif4_clk", 4991 "hscif4_ctrl", 4992 "hscif4_data_b", 4993 }; 4994 4995 static const char * const i2c0_groups[] = { 4996 "i2c0", 4997 }; 4998 4999 static const char * const i2c1_groups[] = { 5000 "i2c1_a", 5001 "i2c1_b", 5002 }; 5003 5004 static const char * const i2c2_groups[] = { 5005 "i2c2_a", 5006 "i2c2_b", 5007 }; 5008 5009 static const char * const i2c3_groups[] = { 5010 "i2c3", 5011 }; 5012 5013 static const char * const i2c5_groups[] = { 5014 "i2c5", 5015 }; 5016 5017 static const char * const i2c6_groups[] = { 5018 "i2c6_a", 5019 "i2c6_b", 5020 "i2c6_c", 5021 }; 5022 5023 static const char * const intc_ex_groups[] = { 5024 "intc_ex_irq0", 5025 "intc_ex_irq1", 5026 "intc_ex_irq2", 5027 "intc_ex_irq3", 5028 "intc_ex_irq4", 5029 "intc_ex_irq5", 5030 }; 5031 5032 #ifdef CONFIG_PINCTRL_PFC_R8A77965 5033 static const char * const mlb_3pin_groups[] = { 5034 "mlb_3pin", 5035 }; 5036 #endif /* CONFIG_PINCTRL_PFC_R8A77965 */ 5037 5038 static const char * const msiof0_groups[] = { 5039 "msiof0_clk", 5040 "msiof0_sync", 5041 "msiof0_ss1", 5042 "msiof0_ss2", 5043 "msiof0_txd", 5044 "msiof0_rxd", 5045 }; 5046 5047 static const char * const msiof1_groups[] = { 5048 "msiof1_clk_a", 5049 "msiof1_sync_a", 5050 "msiof1_ss1_a", 5051 "msiof1_ss2_a", 5052 "msiof1_txd_a", 5053 "msiof1_rxd_a", 5054 "msiof1_clk_b", 5055 "msiof1_sync_b", 5056 "msiof1_ss1_b", 5057 "msiof1_ss2_b", 5058 "msiof1_txd_b", 5059 "msiof1_rxd_b", 5060 "msiof1_clk_c", 5061 "msiof1_sync_c", 5062 "msiof1_ss1_c", 5063 "msiof1_ss2_c", 5064 "msiof1_txd_c", 5065 "msiof1_rxd_c", 5066 "msiof1_clk_d", 5067 "msiof1_sync_d", 5068 "msiof1_ss1_d", 5069 "msiof1_ss2_d", 5070 "msiof1_txd_d", 5071 "msiof1_rxd_d", 5072 "msiof1_clk_e", 5073 "msiof1_sync_e", 5074 "msiof1_ss1_e", 5075 "msiof1_ss2_e", 5076 "msiof1_txd_e", 5077 "msiof1_rxd_e", 5078 "msiof1_clk_f", 5079 "msiof1_sync_f", 5080 "msiof1_ss1_f", 5081 "msiof1_ss2_f", 5082 "msiof1_txd_f", 5083 "msiof1_rxd_f", 5084 "msiof1_clk_g", 5085 "msiof1_sync_g", 5086 "msiof1_ss1_g", 5087 "msiof1_ss2_g", 5088 "msiof1_txd_g", 5089 "msiof1_rxd_g", 5090 }; 5091 5092 static const char * const msiof2_groups[] = { 5093 "msiof2_clk_a", 5094 "msiof2_sync_a", 5095 "msiof2_ss1_a", 5096 "msiof2_ss2_a", 5097 "msiof2_txd_a", 5098 "msiof2_rxd_a", 5099 "msiof2_clk_b", 5100 "msiof2_sync_b", 5101 "msiof2_ss1_b", 5102 "msiof2_ss2_b", 5103 "msiof2_txd_b", 5104 "msiof2_rxd_b", 5105 "msiof2_clk_c", 5106 "msiof2_sync_c", 5107 "msiof2_ss1_c", 5108 "msiof2_ss2_c", 5109 "msiof2_txd_c", 5110 "msiof2_rxd_c", 5111 "msiof2_clk_d", 5112 "msiof2_sync_d", 5113 "msiof2_ss1_d", 5114 "msiof2_ss2_d", 5115 "msiof2_txd_d", 5116 "msiof2_rxd_d", 5117 }; 5118 5119 static const char * const msiof3_groups[] = { 5120 "msiof3_clk_a", 5121 "msiof3_sync_a", 5122 "msiof3_ss1_a", 5123 "msiof3_ss2_a", 5124 "msiof3_txd_a", 5125 "msiof3_rxd_a", 5126 "msiof3_clk_b", 5127 "msiof3_sync_b", 5128 "msiof3_ss1_b", 5129 "msiof3_ss2_b", 5130 "msiof3_txd_b", 5131 "msiof3_rxd_b", 5132 "msiof3_clk_c", 5133 "msiof3_sync_c", 5134 "msiof3_txd_c", 5135 "msiof3_rxd_c", 5136 "msiof3_clk_d", 5137 "msiof3_sync_d", 5138 "msiof3_ss1_d", 5139 "msiof3_txd_d", 5140 "msiof3_rxd_d", 5141 "msiof3_clk_e", 5142 "msiof3_sync_e", 5143 "msiof3_ss1_e", 5144 "msiof3_ss2_e", 5145 "msiof3_txd_e", 5146 "msiof3_rxd_e", 5147 }; 5148 5149 static const char * const pwm0_groups[] = { 5150 "pwm0", 5151 }; 5152 5153 static const char * const pwm1_groups[] = { 5154 "pwm1_a", 5155 "pwm1_b", 5156 }; 5157 5158 static const char * const pwm2_groups[] = { 5159 "pwm2_a", 5160 "pwm2_b", 5161 }; 5162 5163 static const char * const pwm3_groups[] = { 5164 "pwm3_a", 5165 "pwm3_b", 5166 }; 5167 5168 static const char * const pwm4_groups[] = { 5169 "pwm4_a", 5170 "pwm4_b", 5171 }; 5172 5173 static const char * const pwm5_groups[] = { 5174 "pwm5_a", 5175 "pwm5_b", 5176 }; 5177 5178 static const char * const pwm6_groups[] = { 5179 "pwm6_a", 5180 "pwm6_b", 5181 }; 5182 5183 static const char * const qspi0_groups[] = { 5184 "qspi0_ctrl", 5185 "qspi0_data2", 5186 "qspi0_data4", 5187 }; 5188 5189 static const char * const qspi1_groups[] = { 5190 "qspi1_ctrl", 5191 "qspi1_data2", 5192 "qspi1_data4", 5193 }; 5194 5195 static const char * const sata0_groups[] = { 5196 "sata0_devslp_a", 5197 "sata0_devslp_b", 5198 }; 5199 5200 static const char * const scif0_groups[] = { 5201 "scif0_data", 5202 "scif0_clk", 5203 "scif0_ctrl", 5204 }; 5205 5206 static const char * const scif1_groups[] = { 5207 "scif1_data_a", 5208 "scif1_clk", 5209 "scif1_ctrl", 5210 "scif1_data_b", 5211 }; 5212 static const char * const scif2_groups[] = { 5213 "scif2_data_a", 5214 "scif2_clk", 5215 "scif2_data_b", 5216 }; 5217 5218 static const char * const scif3_groups[] = { 5219 "scif3_data_a", 5220 "scif3_clk", 5221 "scif3_ctrl", 5222 "scif3_data_b", 5223 }; 5224 5225 static const char * const scif4_groups[] = { 5226 "scif4_data_a", 5227 "scif4_clk_a", 5228 "scif4_ctrl_a", 5229 "scif4_data_b", 5230 "scif4_clk_b", 5231 "scif4_ctrl_b", 5232 "scif4_data_c", 5233 "scif4_clk_c", 5234 "scif4_ctrl_c", 5235 }; 5236 5237 static const char * const scif5_groups[] = { 5238 "scif5_data_a", 5239 "scif5_clk_a", 5240 "scif5_data_b", 5241 "scif5_clk_b", 5242 }; 5243 5244 static const char * const scif_clk_groups[] = { 5245 "scif_clk_a", 5246 "scif_clk_b", 5247 }; 5248 5249 static const char * const sdhi0_groups[] = { 5250 "sdhi0_data1", 5251 "sdhi0_data4", 5252 "sdhi0_ctrl", 5253 "sdhi0_cd", 5254 "sdhi0_wp", 5255 }; 5256 5257 static const char * const sdhi1_groups[] = { 5258 "sdhi1_data1", 5259 "sdhi1_data4", 5260 "sdhi1_ctrl", 5261 "sdhi1_cd", 5262 "sdhi1_wp", 5263 }; 5264 5265 static const char * const sdhi2_groups[] = { 5266 "sdhi2_data1", 5267 "sdhi2_data4", 5268 "sdhi2_data8", 5269 "sdhi2_ctrl", 5270 "sdhi2_cd_a", 5271 "sdhi2_wp_a", 5272 "sdhi2_cd_b", 5273 "sdhi2_wp_b", 5274 "sdhi2_ds", 5275 }; 5276 5277 static const char * const sdhi3_groups[] = { 5278 "sdhi3_data1", 5279 "sdhi3_data4", 5280 "sdhi3_data8", 5281 "sdhi3_ctrl", 5282 "sdhi3_cd", 5283 "sdhi3_wp", 5284 "sdhi3_ds", 5285 }; 5286 5287 static const char * const ssi_groups[] = { 5288 "ssi0_data", 5289 "ssi01239_ctrl", 5290 "ssi1_data_a", 5291 "ssi1_data_b", 5292 "ssi1_ctrl_a", 5293 "ssi1_ctrl_b", 5294 "ssi2_data_a", 5295 "ssi2_data_b", 5296 "ssi2_ctrl_a", 5297 "ssi2_ctrl_b", 5298 "ssi3_data", 5299 "ssi349_ctrl", 5300 "ssi4_data", 5301 "ssi4_ctrl", 5302 "ssi5_data", 5303 "ssi5_ctrl", 5304 "ssi6_data", 5305 "ssi6_ctrl", 5306 "ssi7_data", 5307 "ssi78_ctrl", 5308 "ssi8_data", 5309 "ssi9_data_a", 5310 "ssi9_data_b", 5311 "ssi9_ctrl_a", 5312 "ssi9_ctrl_b", 5313 }; 5314 5315 static const char * const tmu_groups[] = { 5316 "tmu_tclk1_a", 5317 "tmu_tclk1_b", 5318 "tmu_tclk2_a", 5319 "tmu_tclk2_b", 5320 }; 5321 5322 static const char * const tpu_groups[] = { 5323 "tpu_to0", 5324 "tpu_to1", 5325 "tpu_to2", 5326 "tpu_to3", 5327 }; 5328 5329 static const char * const usb0_groups[] = { 5330 "usb0", 5331 }; 5332 5333 static const char * const usb1_groups[] = { 5334 "usb1", 5335 }; 5336 5337 static const char * const usb30_groups[] = { 5338 "usb30", 5339 }; 5340 5341 static const char * const vin4_groups[] = { 5342 "vin4_data8_a", 5343 "vin4_data10_a", 5344 "vin4_data12_a", 5345 "vin4_data16_a", 5346 "vin4_data18_a", 5347 "vin4_data20_a", 5348 "vin4_data24_a", 5349 "vin4_data8_b", 5350 "vin4_data10_b", 5351 "vin4_data12_b", 5352 "vin4_data16_b", 5353 "vin4_data18_b", 5354 "vin4_data20_b", 5355 "vin4_data24_b", 5356 "vin4_g8", 5357 "vin4_sync", 5358 "vin4_field", 5359 "vin4_clkenb", 5360 "vin4_clk", 5361 }; 5362 5363 static const char * const vin5_groups[] = { 5364 "vin5_data8", 5365 "vin5_data10", 5366 "vin5_data12", 5367 "vin5_data16", 5368 "vin5_high8", 5369 "vin5_sync", 5370 "vin5_field", 5371 "vin5_clkenb", 5372 "vin5_clk", 5373 }; 5374 5375 static const struct { 5376 struct sh_pfc_function common[53]; 5377 #ifdef CONFIG_PINCTRL_PFC_R8A77965 5378 struct sh_pfc_function automotive[5]; 5379 #endif 5380 } pinmux_functions = { 5381 .common = { 5382 SH_PFC_FUNCTION(audio_clk), 5383 SH_PFC_FUNCTION(avb), 5384 SH_PFC_FUNCTION(can0), 5385 SH_PFC_FUNCTION(can1), 5386 SH_PFC_FUNCTION(can_clk), 5387 SH_PFC_FUNCTION(canfd0), 5388 SH_PFC_FUNCTION(canfd1), 5389 SH_PFC_FUNCTION(du), 5390 SH_PFC_FUNCTION(hscif0), 5391 SH_PFC_FUNCTION(hscif1), 5392 SH_PFC_FUNCTION(hscif2), 5393 SH_PFC_FUNCTION(hscif3), 5394 SH_PFC_FUNCTION(hscif4), 5395 SH_PFC_FUNCTION(i2c0), 5396 SH_PFC_FUNCTION(i2c1), 5397 SH_PFC_FUNCTION(i2c2), 5398 SH_PFC_FUNCTION(i2c3), 5399 SH_PFC_FUNCTION(i2c5), 5400 SH_PFC_FUNCTION(i2c6), 5401 SH_PFC_FUNCTION(intc_ex), 5402 SH_PFC_FUNCTION(msiof0), 5403 SH_PFC_FUNCTION(msiof1), 5404 SH_PFC_FUNCTION(msiof2), 5405 SH_PFC_FUNCTION(msiof3), 5406 SH_PFC_FUNCTION(pwm0), 5407 SH_PFC_FUNCTION(pwm1), 5408 SH_PFC_FUNCTION(pwm2), 5409 SH_PFC_FUNCTION(pwm3), 5410 SH_PFC_FUNCTION(pwm4), 5411 SH_PFC_FUNCTION(pwm5), 5412 SH_PFC_FUNCTION(pwm6), 5413 SH_PFC_FUNCTION(qspi0), 5414 SH_PFC_FUNCTION(qspi1), 5415 SH_PFC_FUNCTION(sata0), 5416 SH_PFC_FUNCTION(scif0), 5417 SH_PFC_FUNCTION(scif1), 5418 SH_PFC_FUNCTION(scif2), 5419 SH_PFC_FUNCTION(scif3), 5420 SH_PFC_FUNCTION(scif4), 5421 SH_PFC_FUNCTION(scif5), 5422 SH_PFC_FUNCTION(scif_clk), 5423 SH_PFC_FUNCTION(sdhi0), 5424 SH_PFC_FUNCTION(sdhi1), 5425 SH_PFC_FUNCTION(sdhi2), 5426 SH_PFC_FUNCTION(sdhi3), 5427 SH_PFC_FUNCTION(ssi), 5428 SH_PFC_FUNCTION(tmu), 5429 SH_PFC_FUNCTION(tpu), 5430 SH_PFC_FUNCTION(usb0), 5431 SH_PFC_FUNCTION(usb1), 5432 SH_PFC_FUNCTION(usb30), 5433 SH_PFC_FUNCTION(vin4), 5434 SH_PFC_FUNCTION(vin5), 5435 }, 5436 #ifdef CONFIG_PINCTRL_PFC_R8A77965 5437 .automotive = { 5438 SH_PFC_FUNCTION(drif0), 5439 SH_PFC_FUNCTION(drif1), 5440 SH_PFC_FUNCTION(drif2), 5441 SH_PFC_FUNCTION(drif3), 5442 SH_PFC_FUNCTION(mlb_3pin), 5443 } 5444 #endif /* CONFIG_PINCTRL_PFC_R8A77965 */ 5445 }; 5446 5447 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 5448 #define F_(x, y) FN_##y 5449 #define FM(x) FN_##x 5450 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( 5451 0, 0, 5452 0, 0, 5453 0, 0, 5454 0, 0, 5455 0, 0, 5456 0, 0, 5457 0, 0, 5458 0, 0, 5459 0, 0, 5460 0, 0, 5461 0, 0, 5462 0, 0, 5463 0, 0, 5464 0, 0, 5465 0, 0, 5466 0, 0, 5467 GP_0_15_FN, GPSR0_15, 5468 GP_0_14_FN, GPSR0_14, 5469 GP_0_13_FN, GPSR0_13, 5470 GP_0_12_FN, GPSR0_12, 5471 GP_0_11_FN, GPSR0_11, 5472 GP_0_10_FN, GPSR0_10, 5473 GP_0_9_FN, GPSR0_9, 5474 GP_0_8_FN, GPSR0_8, 5475 GP_0_7_FN, GPSR0_7, 5476 GP_0_6_FN, GPSR0_6, 5477 GP_0_5_FN, GPSR0_5, 5478 GP_0_4_FN, GPSR0_4, 5479 GP_0_3_FN, GPSR0_3, 5480 GP_0_2_FN, GPSR0_2, 5481 GP_0_1_FN, GPSR0_1, 5482 GP_0_0_FN, GPSR0_0, )) 5483 }, 5484 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( 5485 0, 0, 5486 0, 0, 5487 0, 0, 5488 GP_1_28_FN, GPSR1_28, 5489 GP_1_27_FN, GPSR1_27, 5490 GP_1_26_FN, GPSR1_26, 5491 GP_1_25_FN, GPSR1_25, 5492 GP_1_24_FN, GPSR1_24, 5493 GP_1_23_FN, GPSR1_23, 5494 GP_1_22_FN, GPSR1_22, 5495 GP_1_21_FN, GPSR1_21, 5496 GP_1_20_FN, GPSR1_20, 5497 GP_1_19_FN, GPSR1_19, 5498 GP_1_18_FN, GPSR1_18, 5499 GP_1_17_FN, GPSR1_17, 5500 GP_1_16_FN, GPSR1_16, 5501 GP_1_15_FN, GPSR1_15, 5502 GP_1_14_FN, GPSR1_14, 5503 GP_1_13_FN, GPSR1_13, 5504 GP_1_12_FN, GPSR1_12, 5505 GP_1_11_FN, GPSR1_11, 5506 GP_1_10_FN, GPSR1_10, 5507 GP_1_9_FN, GPSR1_9, 5508 GP_1_8_FN, GPSR1_8, 5509 GP_1_7_FN, GPSR1_7, 5510 GP_1_6_FN, GPSR1_6, 5511 GP_1_5_FN, GPSR1_5, 5512 GP_1_4_FN, GPSR1_4, 5513 GP_1_3_FN, GPSR1_3, 5514 GP_1_2_FN, GPSR1_2, 5515 GP_1_1_FN, GPSR1_1, 5516 GP_1_0_FN, GPSR1_0, )) 5517 }, 5518 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( 5519 0, 0, 5520 0, 0, 5521 0, 0, 5522 0, 0, 5523 0, 0, 5524 0, 0, 5525 0, 0, 5526 0, 0, 5527 0, 0, 5528 0, 0, 5529 0, 0, 5530 0, 0, 5531 0, 0, 5532 0, 0, 5533 0, 0, 5534 0, 0, 5535 0, 0, 5536 GP_2_14_FN, GPSR2_14, 5537 GP_2_13_FN, GPSR2_13, 5538 GP_2_12_FN, GPSR2_12, 5539 GP_2_11_FN, GPSR2_11, 5540 GP_2_10_FN, GPSR2_10, 5541 GP_2_9_FN, GPSR2_9, 5542 GP_2_8_FN, GPSR2_8, 5543 GP_2_7_FN, GPSR2_7, 5544 GP_2_6_FN, GPSR2_6, 5545 GP_2_5_FN, GPSR2_5, 5546 GP_2_4_FN, GPSR2_4, 5547 GP_2_3_FN, GPSR2_3, 5548 GP_2_2_FN, GPSR2_2, 5549 GP_2_1_FN, GPSR2_1, 5550 GP_2_0_FN, GPSR2_0, )) 5551 }, 5552 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( 5553 0, 0, 5554 0, 0, 5555 0, 0, 5556 0, 0, 5557 0, 0, 5558 0, 0, 5559 0, 0, 5560 0, 0, 5561 0, 0, 5562 0, 0, 5563 0, 0, 5564 0, 0, 5565 0, 0, 5566 0, 0, 5567 0, 0, 5568 0, 0, 5569 GP_3_15_FN, GPSR3_15, 5570 GP_3_14_FN, GPSR3_14, 5571 GP_3_13_FN, GPSR3_13, 5572 GP_3_12_FN, GPSR3_12, 5573 GP_3_11_FN, GPSR3_11, 5574 GP_3_10_FN, GPSR3_10, 5575 GP_3_9_FN, GPSR3_9, 5576 GP_3_8_FN, GPSR3_8, 5577 GP_3_7_FN, GPSR3_7, 5578 GP_3_6_FN, GPSR3_6, 5579 GP_3_5_FN, GPSR3_5, 5580 GP_3_4_FN, GPSR3_4, 5581 GP_3_3_FN, GPSR3_3, 5582 GP_3_2_FN, GPSR3_2, 5583 GP_3_1_FN, GPSR3_1, 5584 GP_3_0_FN, GPSR3_0, )) 5585 }, 5586 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( 5587 0, 0, 5588 0, 0, 5589 0, 0, 5590 0, 0, 5591 0, 0, 5592 0, 0, 5593 0, 0, 5594 0, 0, 5595 0, 0, 5596 0, 0, 5597 0, 0, 5598 0, 0, 5599 0, 0, 5600 0, 0, 5601 GP_4_17_FN, GPSR4_17, 5602 GP_4_16_FN, GPSR4_16, 5603 GP_4_15_FN, GPSR4_15, 5604 GP_4_14_FN, GPSR4_14, 5605 GP_4_13_FN, GPSR4_13, 5606 GP_4_12_FN, GPSR4_12, 5607 GP_4_11_FN, GPSR4_11, 5608 GP_4_10_FN, GPSR4_10, 5609 GP_4_9_FN, GPSR4_9, 5610 GP_4_8_FN, GPSR4_8, 5611 GP_4_7_FN, GPSR4_7, 5612 GP_4_6_FN, GPSR4_6, 5613 GP_4_5_FN, GPSR4_5, 5614 GP_4_4_FN, GPSR4_4, 5615 GP_4_3_FN, GPSR4_3, 5616 GP_4_2_FN, GPSR4_2, 5617 GP_4_1_FN, GPSR4_1, 5618 GP_4_0_FN, GPSR4_0, )) 5619 }, 5620 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( 5621 0, 0, 5622 0, 0, 5623 0, 0, 5624 0, 0, 5625 0, 0, 5626 0, 0, 5627 GP_5_25_FN, GPSR5_25, 5628 GP_5_24_FN, GPSR5_24, 5629 GP_5_23_FN, GPSR5_23, 5630 GP_5_22_FN, GPSR5_22, 5631 GP_5_21_FN, GPSR5_21, 5632 GP_5_20_FN, GPSR5_20, 5633 GP_5_19_FN, GPSR5_19, 5634 GP_5_18_FN, GPSR5_18, 5635 GP_5_17_FN, GPSR5_17, 5636 GP_5_16_FN, GPSR5_16, 5637 GP_5_15_FN, GPSR5_15, 5638 GP_5_14_FN, GPSR5_14, 5639 GP_5_13_FN, GPSR5_13, 5640 GP_5_12_FN, GPSR5_12, 5641 GP_5_11_FN, GPSR5_11, 5642 GP_5_10_FN, GPSR5_10, 5643 GP_5_9_FN, GPSR5_9, 5644 GP_5_8_FN, GPSR5_8, 5645 GP_5_7_FN, GPSR5_7, 5646 GP_5_6_FN, GPSR5_6, 5647 GP_5_5_FN, GPSR5_5, 5648 GP_5_4_FN, GPSR5_4, 5649 GP_5_3_FN, GPSR5_3, 5650 GP_5_2_FN, GPSR5_2, 5651 GP_5_1_FN, GPSR5_1, 5652 GP_5_0_FN, GPSR5_0, )) 5653 }, 5654 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP( 5655 GP_6_31_FN, GPSR6_31, 5656 GP_6_30_FN, GPSR6_30, 5657 GP_6_29_FN, GPSR6_29, 5658 GP_6_28_FN, GPSR6_28, 5659 GP_6_27_FN, GPSR6_27, 5660 GP_6_26_FN, GPSR6_26, 5661 GP_6_25_FN, GPSR6_25, 5662 GP_6_24_FN, GPSR6_24, 5663 GP_6_23_FN, GPSR6_23, 5664 GP_6_22_FN, GPSR6_22, 5665 GP_6_21_FN, GPSR6_21, 5666 GP_6_20_FN, GPSR6_20, 5667 GP_6_19_FN, GPSR6_19, 5668 GP_6_18_FN, GPSR6_18, 5669 GP_6_17_FN, GPSR6_17, 5670 GP_6_16_FN, GPSR6_16, 5671 GP_6_15_FN, GPSR6_15, 5672 GP_6_14_FN, GPSR6_14, 5673 GP_6_13_FN, GPSR6_13, 5674 GP_6_12_FN, GPSR6_12, 5675 GP_6_11_FN, GPSR6_11, 5676 GP_6_10_FN, GPSR6_10, 5677 GP_6_9_FN, GPSR6_9, 5678 GP_6_8_FN, GPSR6_8, 5679 GP_6_7_FN, GPSR6_7, 5680 GP_6_6_FN, GPSR6_6, 5681 GP_6_5_FN, GPSR6_5, 5682 GP_6_4_FN, GPSR6_4, 5683 GP_6_3_FN, GPSR6_3, 5684 GP_6_2_FN, GPSR6_2, 5685 GP_6_1_FN, GPSR6_1, 5686 GP_6_0_FN, GPSR6_0, )) 5687 }, 5688 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP( 5689 0, 0, 5690 0, 0, 5691 0, 0, 5692 0, 0, 5693 0, 0, 5694 0, 0, 5695 0, 0, 5696 0, 0, 5697 0, 0, 5698 0, 0, 5699 0, 0, 5700 0, 0, 5701 0, 0, 5702 0, 0, 5703 0, 0, 5704 0, 0, 5705 0, 0, 5706 0, 0, 5707 0, 0, 5708 0, 0, 5709 0, 0, 5710 0, 0, 5711 0, 0, 5712 0, 0, 5713 0, 0, 5714 0, 0, 5715 0, 0, 5716 0, 0, 5717 GP_7_3_FN, GPSR7_3, 5718 GP_7_2_FN, GPSR7_2, 5719 GP_7_1_FN, GPSR7_1, 5720 GP_7_0_FN, GPSR7_0, )) 5721 }, 5722 #undef F_ 5723 #undef FM 5724 5725 #define F_(x, y) x, 5726 #define FM(x) FN_##x, 5727 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( 5728 IP0_31_28 5729 IP0_27_24 5730 IP0_23_20 5731 IP0_19_16 5732 IP0_15_12 5733 IP0_11_8 5734 IP0_7_4 5735 IP0_3_0 )) 5736 }, 5737 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( 5738 IP1_31_28 5739 IP1_27_24 5740 IP1_23_20 5741 IP1_19_16 5742 IP1_15_12 5743 IP1_11_8 5744 IP1_7_4 5745 IP1_3_0 )) 5746 }, 5747 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( 5748 IP2_31_28 5749 IP2_27_24 5750 IP2_23_20 5751 IP2_19_16 5752 IP2_15_12 5753 IP2_11_8 5754 IP2_7_4 5755 IP2_3_0 )) 5756 }, 5757 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( 5758 IP3_31_28 5759 IP3_27_24 5760 IP3_23_20 5761 IP3_19_16 5762 IP3_15_12 5763 IP3_11_8 5764 IP3_7_4 5765 IP3_3_0 )) 5766 }, 5767 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( 5768 IP4_31_28 5769 IP4_27_24 5770 IP4_23_20 5771 IP4_19_16 5772 IP4_15_12 5773 IP4_11_8 5774 IP4_7_4 5775 IP4_3_0 )) 5776 }, 5777 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( 5778 IP5_31_28 5779 IP5_27_24 5780 IP5_23_20 5781 IP5_19_16 5782 IP5_15_12 5783 IP5_11_8 5784 IP5_7_4 5785 IP5_3_0 )) 5786 }, 5787 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( 5788 IP6_31_28 5789 IP6_27_24 5790 IP6_23_20 5791 IP6_19_16 5792 IP6_15_12 5793 IP6_11_8 5794 IP6_7_4 5795 IP6_3_0 )) 5796 }, 5797 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( 5798 IP7_31_28 5799 IP7_27_24 5800 IP7_23_20 5801 IP7_19_16 5802 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5803 IP7_11_8 5804 IP7_7_4 5805 IP7_3_0 )) 5806 }, 5807 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( 5808 IP8_31_28 5809 IP8_27_24 5810 IP8_23_20 5811 IP8_19_16 5812 IP8_15_12 5813 IP8_11_8 5814 IP8_7_4 5815 IP8_3_0 )) 5816 }, 5817 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP( 5818 IP9_31_28 5819 IP9_27_24 5820 IP9_23_20 5821 IP9_19_16 5822 IP9_15_12 5823 IP9_11_8 5824 IP9_7_4 5825 IP9_3_0 )) 5826 }, 5827 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP( 5828 IP10_31_28 5829 IP10_27_24 5830 IP10_23_20 5831 IP10_19_16 5832 IP10_15_12 5833 IP10_11_8 5834 IP10_7_4 5835 IP10_3_0 )) 5836 }, 5837 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP( 5838 IP11_31_28 5839 IP11_27_24 5840 IP11_23_20 5841 IP11_19_16 5842 IP11_15_12 5843 IP11_11_8 5844 IP11_7_4 5845 IP11_3_0 )) 5846 }, 5847 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP( 5848 IP12_31_28 5849 IP12_27_24 5850 IP12_23_20 5851 IP12_19_16 5852 IP12_15_12 5853 IP12_11_8 5854 IP12_7_4 5855 IP12_3_0 )) 5856 }, 5857 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP( 5858 IP13_31_28 5859 IP13_27_24 5860 IP13_23_20 5861 IP13_19_16 5862 IP13_15_12 5863 IP13_11_8 5864 IP13_7_4 5865 IP13_3_0 )) 5866 }, 5867 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP( 5868 IP14_31_28 5869 IP14_27_24 5870 IP14_23_20 5871 IP14_19_16 5872 IP14_15_12 5873 IP14_11_8 5874 IP14_7_4 5875 IP14_3_0 )) 5876 }, 5877 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP( 5878 IP15_31_28 5879 IP15_27_24 5880 IP15_23_20 5881 IP15_19_16 5882 IP15_15_12 5883 IP15_11_8 5884 IP15_7_4 5885 IP15_3_0 )) 5886 }, 5887 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP( 5888 IP16_31_28 5889 IP16_27_24 5890 IP16_23_20 5891 IP16_19_16 5892 IP16_15_12 5893 IP16_11_8 5894 IP16_7_4 5895 IP16_3_0 )) 5896 }, 5897 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP( 5898 IP17_31_28 5899 IP17_27_24 5900 IP17_23_20 5901 IP17_19_16 5902 IP17_15_12 5903 IP17_11_8 5904 IP17_7_4 5905 IP17_3_0 )) 5906 }, 5907 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP( 5908 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5909 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5910 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5911 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5912 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5913 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5914 IP18_7_4 5915 IP18_3_0 )) 5916 }, 5917 #undef F_ 5918 #undef FM 5919 5920 #define F_(x, y) x, 5921 #define FM(x) FN_##x, 5922 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, 5923 GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2, 5924 1, 1, 1, 2, 2, 1, 2, 3), 5925 GROUP( 5926 MOD_SEL0_31_30_29 5927 MOD_SEL0_28_27 5928 MOD_SEL0_26_25_24 5929 MOD_SEL0_23 5930 MOD_SEL0_22 5931 MOD_SEL0_21 5932 MOD_SEL0_20 5933 MOD_SEL0_19 5934 MOD_SEL0_18_17 5935 MOD_SEL0_16 5936 0, 0, /* RESERVED 15 */ 5937 MOD_SEL0_14_13 5938 MOD_SEL0_12 5939 MOD_SEL0_11 5940 MOD_SEL0_10 5941 MOD_SEL0_9_8 5942 MOD_SEL0_7_6 5943 MOD_SEL0_5 5944 MOD_SEL0_4_3 5945 /* RESERVED 2, 1, 0 */ 5946 0, 0, 0, 0, 0, 0, 0, 0 )) 5947 }, 5948 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, 5949 GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1, 5950 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1), 5951 GROUP( 5952 MOD_SEL1_31_30 5953 MOD_SEL1_29_28_27 5954 MOD_SEL1_26 5955 MOD_SEL1_25_24 5956 MOD_SEL1_23_22_21 5957 MOD_SEL1_20 5958 MOD_SEL1_19 5959 MOD_SEL1_18_17 5960 MOD_SEL1_16 5961 MOD_SEL1_15_14 5962 MOD_SEL1_13 5963 MOD_SEL1_12 5964 MOD_SEL1_11 5965 MOD_SEL1_10 5966 MOD_SEL1_9 5967 0, 0, 0, 0, /* RESERVED 8, 7 */ 5968 MOD_SEL1_6 5969 MOD_SEL1_5 5970 MOD_SEL1_4 5971 MOD_SEL1_3 5972 MOD_SEL1_2 5973 MOD_SEL1_1 5974 MOD_SEL1_0 )) 5975 }, 5976 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32, 5977 GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 5978 1, 4, 4, 4, 3, 1), 5979 GROUP( 5980 MOD_SEL2_31 5981 MOD_SEL2_30 5982 MOD_SEL2_29 5983 MOD_SEL2_28_27 5984 MOD_SEL2_26 5985 MOD_SEL2_25_24_23 5986 MOD_SEL2_22 5987 MOD_SEL2_21 5988 MOD_SEL2_20 5989 MOD_SEL2_19 5990 MOD_SEL2_18 5991 MOD_SEL2_17 5992 /* RESERVED 16 */ 5993 0, 0, 5994 /* RESERVED 15, 14, 13, 12 */ 5995 0, 0, 0, 0, 0, 0, 0, 0, 5996 0, 0, 0, 0, 0, 0, 0, 0, 5997 /* RESERVED 11, 10, 9, 8 */ 5998 0, 0, 0, 0, 0, 0, 0, 0, 5999 0, 0, 0, 0, 0, 0, 0, 0, 6000 /* RESERVED 7, 6, 5, 4 */ 6001 0, 0, 0, 0, 0, 0, 0, 0, 6002 0, 0, 0, 0, 0, 0, 0, 0, 6003 /* RESERVED 3, 2, 1 */ 6004 0, 0, 0, 0, 0, 0, 0, 0, 6005 MOD_SEL2_0 )) 6006 }, 6007 { }, 6008 }; 6009 6010 static const struct pinmux_drive_reg pinmux_drive_regs[] = { 6011 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) { 6012 { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */ 6013 { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */ 6014 { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */ 6015 { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */ 6016 { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */ 6017 { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */ 6018 { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */ 6019 { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */ 6020 } }, 6021 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) { 6022 { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */ 6023 { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */ 6024 { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */ 6025 { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */ 6026 { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */ 6027 { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */ 6028 { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */ 6029 { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */ 6030 } }, 6031 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) { 6032 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */ 6033 { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */ 6034 { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */ 6035 { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */ 6036 { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */ 6037 { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */ 6038 { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */ 6039 { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */ 6040 } }, 6041 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) { 6042 { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */ 6043 { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */ 6044 { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */ 6045 { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */ 6046 { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */ 6047 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ 6048 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ 6049 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ 6050 } }, 6051 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) { 6052 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */ 6053 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */ 6054 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */ 6055 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */ 6056 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */ 6057 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */ 6058 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */ 6059 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */ 6060 } }, 6061 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) { 6062 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */ 6063 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */ 6064 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */ 6065 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */ 6066 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */ 6067 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */ 6068 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */ 6069 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */ 6070 } }, 6071 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) { 6072 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */ 6073 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */ 6074 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */ 6075 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */ 6076 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */ 6077 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */ 6078 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */ 6079 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */ 6080 } }, 6081 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) { 6082 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */ 6083 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */ 6084 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */ 6085 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */ 6086 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */ 6087 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */ 6088 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */ 6089 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */ 6090 } }, 6091 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) { 6092 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */ 6093 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */ 6094 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */ 6095 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */ 6096 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */ 6097 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */ 6098 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */ 6099 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */ 6100 } }, 6101 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) { 6102 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */ 6103 { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */ 6104 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */ 6105 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */ 6106 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */ 6107 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */ 6108 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */ 6109 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */ 6110 } }, 6111 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) { 6112 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */ 6113 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */ 6114 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */ 6115 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */ 6116 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */ 6117 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */ 6118 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */ 6119 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */ 6120 } }, 6121 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) { 6122 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ 6123 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ 6124 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ 6125 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ 6126 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ 6127 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ 6128 { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */ 6129 { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */ 6130 } }, 6131 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) { 6132 { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */ 6133 { PIN_FSCLKST, 20, 2 }, /* FSCLKST */ 6134 { PIN_TMS, 4, 2 }, /* TMS */ 6135 } }, 6136 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) { 6137 { PIN_TDO, 28, 2 }, /* TDO */ 6138 { PIN_ASEBRK, 24, 2 }, /* ASEBRK */ 6139 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ 6140 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ 6141 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ 6142 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ 6143 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ 6144 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ 6145 } }, 6146 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) { 6147 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */ 6148 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */ 6149 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */ 6150 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */ 6151 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */ 6152 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */ 6153 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */ 6154 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */ 6155 } }, 6156 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) { 6157 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */ 6158 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */ 6159 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */ 6160 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */ 6161 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */ 6162 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */ 6163 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */ 6164 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */ 6165 } }, 6166 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) { 6167 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */ 6168 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */ 6169 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */ 6170 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */ 6171 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */ 6172 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */ 6173 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */ 6174 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */ 6175 } }, 6176 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) { 6177 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */ 6178 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */ 6179 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */ 6180 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */ 6181 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */ 6182 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */ 6183 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */ 6184 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */ 6185 } }, 6186 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) { 6187 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */ 6188 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */ 6189 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */ 6190 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */ 6191 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */ 6192 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */ 6193 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */ 6194 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */ 6195 } }, 6196 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) { 6197 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */ 6198 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */ 6199 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */ 6200 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */ 6201 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */ 6202 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */ 6203 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */ 6204 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */ 6205 } }, 6206 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) { 6207 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */ 6208 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */ 6209 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */ 6210 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */ 6211 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */ 6212 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */ 6213 { PIN_MLB_REF, 4, 3 }, /* MLB_REF */ 6214 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */ 6215 } }, 6216 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) { 6217 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */ 6218 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */ 6219 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */ 6220 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */ 6221 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */ 6222 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */ 6223 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */ 6224 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */ 6225 } }, 6226 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) { 6227 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */ 6228 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */ 6229 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */ 6230 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */ 6231 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */ 6232 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */ 6233 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */ 6234 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */ 6235 } }, 6236 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) { 6237 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */ 6238 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */ 6239 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */ 6240 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */ 6241 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */ 6242 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */ 6243 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */ 6244 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */ 6245 } }, 6246 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) { 6247 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */ 6248 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */ 6249 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */ 6250 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */ 6251 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */ 6252 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */ 6253 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */ 6254 } }, 6255 { }, 6256 }; 6257 6258 enum ioctrl_regs { 6259 POCCTRL, 6260 TDSELCTRL, 6261 }; 6262 6263 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { 6264 [POCCTRL] = { 0xe6060380, }, 6265 [TDSELCTRL] = { 0xe60603c0, }, 6266 { /* sentinel */ }, 6267 }; 6268 6269 static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc, 6270 unsigned int pin, u32 *pocctrl) 6271 { 6272 int bit = -EINVAL; 6273 6274 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg; 6275 6276 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11)) 6277 bit = pin & 0x1f; 6278 6279 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17)) 6280 bit = (pin & 0x1f) + 12; 6281 6282 return bit; 6283 } 6284 6285 static const struct pinmux_bias_reg pinmux_bias_regs[] = { 6286 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { 6287 [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */ 6288 [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */ 6289 [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */ 6290 [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */ 6291 [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */ 6292 [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */ 6293 [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */ 6294 [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */ 6295 [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */ 6296 [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */ 6297 [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */ 6298 [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */ 6299 [12] = PIN_RPC_INT_N, /* RPC_INT# */ 6300 [13] = PIN_RPC_WP_N, /* RPC_WP# */ 6301 [14] = PIN_RPC_RESET_N, /* RPC_RESET# */ 6302 [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */ 6303 [16] = PIN_AVB_RXC, /* AVB_RXC */ 6304 [17] = PIN_AVB_RD0, /* AVB_RD0 */ 6305 [18] = PIN_AVB_RD1, /* AVB_RD1 */ 6306 [19] = PIN_AVB_RD2, /* AVB_RD2 */ 6307 [20] = PIN_AVB_RD3, /* AVB_RD3 */ 6308 [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */ 6309 [22] = PIN_AVB_TXC, /* AVB_TXC */ 6310 [23] = PIN_AVB_TD0, /* AVB_TD0 */ 6311 [24] = PIN_AVB_TD1, /* AVB_TD1 */ 6312 [25] = PIN_AVB_TD2, /* AVB_TD2 */ 6313 [26] = PIN_AVB_TD3, /* AVB_TD3 */ 6314 [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */ 6315 [28] = PIN_AVB_MDIO, /* AVB_MDIO */ 6316 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */ 6317 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */ 6318 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */ 6319 } }, 6320 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) { 6321 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */ 6322 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */ 6323 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */ 6324 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */ 6325 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */ 6326 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */ 6327 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */ 6328 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */ 6329 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */ 6330 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */ 6331 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */ 6332 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */ 6333 [12] = RCAR_GP_PIN(1, 0), /* A0 */ 6334 [13] = RCAR_GP_PIN(1, 1), /* A1 */ 6335 [14] = RCAR_GP_PIN(1, 2), /* A2 */ 6336 [15] = RCAR_GP_PIN(1, 3), /* A3 */ 6337 [16] = RCAR_GP_PIN(1, 4), /* A4 */ 6338 [17] = RCAR_GP_PIN(1, 5), /* A5 */ 6339 [18] = RCAR_GP_PIN(1, 6), /* A6 */ 6340 [19] = RCAR_GP_PIN(1, 7), /* A7 */ 6341 [20] = RCAR_GP_PIN(1, 8), /* A8 */ 6342 [21] = RCAR_GP_PIN(1, 9), /* A9 */ 6343 [22] = RCAR_GP_PIN(1, 10), /* A10 */ 6344 [23] = RCAR_GP_PIN(1, 11), /* A11 */ 6345 [24] = RCAR_GP_PIN(1, 12), /* A12 */ 6346 [25] = RCAR_GP_PIN(1, 13), /* A13 */ 6347 [26] = RCAR_GP_PIN(1, 14), /* A14 */ 6348 [27] = RCAR_GP_PIN(1, 15), /* A15 */ 6349 [28] = RCAR_GP_PIN(1, 16), /* A16 */ 6350 [29] = RCAR_GP_PIN(1, 17), /* A17 */ 6351 [30] = RCAR_GP_PIN(1, 18), /* A18 */ 6352 [31] = RCAR_GP_PIN(1, 19), /* A19 */ 6353 } }, 6354 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { 6355 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */ 6356 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */ 6357 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */ 6358 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */ 6359 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */ 6360 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */ 6361 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */ 6362 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */ 6363 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */ 6364 [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */ 6365 [10] = RCAR_GP_PIN(0, 0), /* D0 */ 6366 [11] = RCAR_GP_PIN(0, 1), /* D1 */ 6367 [12] = RCAR_GP_PIN(0, 2), /* D2 */ 6368 [13] = RCAR_GP_PIN(0, 3), /* D3 */ 6369 [14] = RCAR_GP_PIN(0, 4), /* D4 */ 6370 [15] = RCAR_GP_PIN(0, 5), /* D5 */ 6371 [16] = RCAR_GP_PIN(0, 6), /* D6 */ 6372 [17] = RCAR_GP_PIN(0, 7), /* D7 */ 6373 [18] = RCAR_GP_PIN(0, 8), /* D8 */ 6374 [19] = RCAR_GP_PIN(0, 9), /* D9 */ 6375 [20] = RCAR_GP_PIN(0, 10), /* D10 */ 6376 [21] = RCAR_GP_PIN(0, 11), /* D11 */ 6377 [22] = RCAR_GP_PIN(0, 12), /* D12 */ 6378 [23] = RCAR_GP_PIN(0, 13), /* D13 */ 6379 [24] = RCAR_GP_PIN(0, 14), /* D14 */ 6380 [25] = RCAR_GP_PIN(0, 15), /* D15 */ 6381 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */ 6382 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ 6383 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */ 6384 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */ 6385 [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */ 6386 [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */ 6387 } }, 6388 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { 6389 [ 0] = SH_PFC_PIN_NONE, 6390 [ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */ 6391 [ 2] = PIN_FSCLKST, /* FSCLKST */ 6392 [ 3] = PIN_EXTALR, /* EXTALR*/ 6393 [ 4] = PIN_TRST_N, /* TRST# */ 6394 [ 5] = PIN_TCK, /* TCK */ 6395 [ 6] = PIN_TMS, /* TMS */ 6396 [ 7] = PIN_TDI, /* TDI */ 6397 [ 8] = SH_PFC_PIN_NONE, 6398 [ 9] = PIN_ASEBRK, /* ASEBRK */ 6399 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ 6400 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ 6401 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ 6402 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */ 6403 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */ 6404 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */ 6405 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */ 6406 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */ 6407 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */ 6408 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */ 6409 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */ 6410 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */ 6411 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */ 6412 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */ 6413 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */ 6414 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */ 6415 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */ 6416 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */ 6417 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */ 6418 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */ 6419 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */ 6420 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */ 6421 } }, 6422 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) { 6423 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */ 6424 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */ 6425 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */ 6426 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */ 6427 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */ 6428 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */ 6429 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */ 6430 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */ 6431 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */ 6432 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */ 6433 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */ 6434 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */ 6435 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */ 6436 [13] = RCAR_GP_PIN(5, 1), /* RX0 */ 6437 [14] = RCAR_GP_PIN(5, 2), /* TX0 */ 6438 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */ 6439 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */ 6440 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */ 6441 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */ 6442 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */ 6443 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */ 6444 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */ 6445 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */ 6446 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */ 6447 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */ 6448 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */ 6449 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */ 6450 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */ 6451 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */ 6452 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */ 6453 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */ 6454 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */ 6455 } }, 6456 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) { 6457 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */ 6458 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */ 6459 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */ 6460 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */ 6461 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */ 6462 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */ 6463 [ 6] = PIN_MLB_REF, /* MLB_REF */ 6464 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ 6465 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ 6466 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */ 6467 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */ 6468 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */ 6469 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */ 6470 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */ 6471 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */ 6472 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */ 6473 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */ 6474 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */ 6475 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */ 6476 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */ 6477 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */ 6478 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */ 6479 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */ 6480 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */ 6481 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */ 6482 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */ 6483 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */ 6484 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */ 6485 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */ 6486 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */ 6487 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */ 6488 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */ 6489 } }, 6490 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) { 6491 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */ 6492 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */ 6493 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */ 6494 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */ 6495 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */ 6496 [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */ 6497 [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */ 6498 [ 7] = SH_PFC_PIN_NONE, 6499 [ 8] = SH_PFC_PIN_NONE, 6500 [ 9] = SH_PFC_PIN_NONE, 6501 [10] = SH_PFC_PIN_NONE, 6502 [11] = SH_PFC_PIN_NONE, 6503 [12] = SH_PFC_PIN_NONE, 6504 [13] = SH_PFC_PIN_NONE, 6505 [14] = SH_PFC_PIN_NONE, 6506 [15] = SH_PFC_PIN_NONE, 6507 [16] = SH_PFC_PIN_NONE, 6508 [17] = SH_PFC_PIN_NONE, 6509 [18] = SH_PFC_PIN_NONE, 6510 [19] = SH_PFC_PIN_NONE, 6511 [20] = SH_PFC_PIN_NONE, 6512 [21] = SH_PFC_PIN_NONE, 6513 [22] = SH_PFC_PIN_NONE, 6514 [23] = SH_PFC_PIN_NONE, 6515 [24] = SH_PFC_PIN_NONE, 6516 [25] = SH_PFC_PIN_NONE, 6517 [26] = SH_PFC_PIN_NONE, 6518 [27] = SH_PFC_PIN_NONE, 6519 [28] = SH_PFC_PIN_NONE, 6520 [29] = SH_PFC_PIN_NONE, 6521 [30] = SH_PFC_PIN_NONE, 6522 [31] = SH_PFC_PIN_NONE, 6523 } }, 6524 { /* sentinel */ }, 6525 }; 6526 6527 static const struct sh_pfc_soc_operations r8a77965_pfc_ops = { 6528 .pin_to_pocctrl = r8a77965_pin_to_pocctrl, 6529 .get_bias = rcar_pinmux_get_bias, 6530 .set_bias = rcar_pinmux_set_bias, 6531 }; 6532 6533 #ifdef CONFIG_PINCTRL_PFC_R8A774B1 6534 const struct sh_pfc_soc_info r8a774b1_pinmux_info = { 6535 .name = "r8a774b1_pfc", 6536 .ops = &r8a77965_pfc_ops, 6537 .unlock_reg = 0xe6060000, /* PMMR */ 6538 6539 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 6540 6541 .pins = pinmux_pins, 6542 .nr_pins = ARRAY_SIZE(pinmux_pins), 6543 .groups = pinmux_groups.common, 6544 .nr_groups = ARRAY_SIZE(pinmux_groups.common), 6545 .functions = pinmux_functions.common, 6546 .nr_functions = ARRAY_SIZE(pinmux_functions.common), 6547 6548 .cfg_regs = pinmux_config_regs, 6549 .drive_regs = pinmux_drive_regs, 6550 .bias_regs = pinmux_bias_regs, 6551 .ioctrl_regs = pinmux_ioctrl_regs, 6552 6553 .pinmux_data = pinmux_data, 6554 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 6555 }; 6556 #endif 6557 6558 #ifdef CONFIG_PINCTRL_PFC_R8A77965 6559 const struct sh_pfc_soc_info r8a77965_pinmux_info = { 6560 .name = "r8a77965_pfc", 6561 .ops = &r8a77965_pfc_ops, 6562 .unlock_reg = 0xe6060000, /* PMMR */ 6563 6564 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 6565 6566 .pins = pinmux_pins, 6567 .nr_pins = ARRAY_SIZE(pinmux_pins), 6568 .groups = pinmux_groups.common, 6569 .nr_groups = ARRAY_SIZE(pinmux_groups.common) + 6570 ARRAY_SIZE(pinmux_groups.automotive), 6571 .functions = pinmux_functions.common, 6572 .nr_functions = ARRAY_SIZE(pinmux_functions.common) + 6573 ARRAY_SIZE(pinmux_functions.automotive), 6574 6575 .cfg_regs = pinmux_config_regs, 6576 .drive_regs = pinmux_drive_regs, 6577 .bias_regs = pinmux_bias_regs, 6578 .ioctrl_regs = pinmux_ioctrl_regs, 6579 6580 .pinmux_data = pinmux_data, 6581 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 6582 }; 6583 #endif 6584